From 9039ffeb622876790cfa3cdf5da2f62d50ce5a2d Mon Sep 17 00:00:00 2001 From: Tan Yan Quan Date: Thu, 14 Nov 2024 10:35:29 +0800 Subject: [PATCH 001/118] feat(802.15.4): IEEE802.15.4 add rx buffer statistic --- components/ieee802154/Kconfig | 28 ++- .../ieee802154/driver/esp_ieee802154_debug.c | 49 ++++- .../ieee802154/driver/esp_ieee802154_dev.c | 7 +- components/ieee802154/esp_ieee802154.c | 21 ++- .../ieee802154/include/esp_ieee802154.h | 23 +++ .../private_include/esp_ieee802154_util.h | 41 ++++- .../cmd_ieee802154/ieee802154_cmd.c | 2 +- .../cmd_ieee802154_stats/CMakeLists.txt | 3 + .../cmd_ieee802154_stats/ieee802154_stats.c | 174 ++++++++++++++++++ .../cmd_ieee802154_stats/ieee802154_stats.h | 11 ++ .../ieee802154_cli/main/CMakeLists.txt | 3 +- .../ieee802154_cli/main/esp_ieee802154_cli.c | 4 + 12 files changed, 349 insertions(+), 17 deletions(-) create mode 100644 examples/ieee802154/ieee802154_cli/components/cmd_ieee802154_stats/CMakeLists.txt create mode 100644 examples/ieee802154/ieee802154_cli/components/cmd_ieee802154_stats/ieee802154_stats.c create mode 100644 examples/ieee802154/ieee802154_cli/components/cmd_ieee802154_stats/ieee802154_stats.h diff --git a/components/ieee802154/Kconfig b/components/ieee802154/Kconfig index 9c5d18e2375..9fb39d37dd8 100644 --- a/components/ieee802154/Kconfig +++ b/components/ieee802154/Kconfig @@ -97,17 +97,31 @@ menu "IEEE 802.15.4" Enabling this option allows different kinds of IEEE802154 debug output. All IEEE802154 debug features increase the size of the final binary. + config IEEE802154_RX_BUFFER_STATISTIC + bool "Rx buffer statistic" + depends on IEEE802154_DEBUG + default n + help + Enabling this option to count IEEE802154 rx buffer when allocating or freeing. + config IEEE802154_ASSERT - bool "Enrich the assert information with IEEE802154 state and event" + bool "Enrich the assert information" + depends on IEEE802154_DEBUG + select IEEE802154_RECORD + default n + help + Enabling this option to print more information when assert. + + config IEEE802154_RECORD + bool "Record the information with IEEE802154 state and event" depends on IEEE802154_DEBUG default n help - Enabling this option to add some probe codes in the driver, and these informations - will be printed when assert. + Enabling this option to add some probe codes in the driver, and record these information. config IEEE802154_RECORD_EVENT bool "Enable record event information for debugging" - depends on IEEE802154_DEBUG + depends on IEEE802154_RECORD default n help Enabling this option to record event, when assert, the recorded event will be printed. @@ -122,7 +136,7 @@ menu "IEEE 802.15.4" config IEEE802154_RECORD_STATE bool "Enable record state information for debugging" - depends on IEEE802154_DEBUG + depends on IEEE802154_RECORD default n help Enabling this option to record state, when assert, the recorded state will be printed. @@ -137,7 +151,7 @@ menu "IEEE 802.15.4" config IEEE802154_RECORD_CMD bool "Enable record command information for debugging" - depends on IEEE802154_DEBUG + depends on IEEE802154_RECORD default n help Enabling this option to record the command, when assert, the recorded @@ -153,7 +167,7 @@ menu "IEEE 802.15.4" config IEEE802154_RECORD_ABORT bool "Enable record abort information for debugging" - depends on IEEE802154_DEBUG + depends on IEEE802154_RECORD default n help Enabling this option to record the abort, when assert, the recorded diff --git a/components/ieee802154/driver/esp_ieee802154_debug.c b/components/ieee802154/driver/esp_ieee802154_debug.c index 0dbfd4bc590..7dec9832134 100644 --- a/components/ieee802154/driver/esp_ieee802154_debug.c +++ b/components/ieee802154/driver/esp_ieee802154_debug.c @@ -171,8 +171,8 @@ static char *ieee80154_tx_abort_reason_string[] = { #endif // CONFIG_IEEE802154_RECORD_EVENT -#if CONFIG_IEEE802154_ASSERT -void ieee802154_assert_print(void) +#if CONFIG_IEEE802154_RECORD +void ieee802154_record_print(void) { #if CONFIG_IEEE802154_RECORD_EVENT ESP_EARLY_LOGW(IEEE802154_TAG, "Print the record event, current event index: %d", g_ieee802154_probe.event_index); @@ -235,7 +235,7 @@ void ieee802154_assert_print(void) ESP_EARLY_LOGW(IEEE802154_TAG,"Print the record abort done."); #endif // CONFIG_IEEE802154_RECORD_ABORT } -#endif // CONFIG_IEEE802154_ASSERT +#endif // CONFIG_IEEE802154_RECORD #if CONFIG_IEEE802154_TXRX_STATISTIC static ieee802154_txrx_statistic_t s_ieee802154_txrx_statistic; @@ -370,4 +370,47 @@ void ieee802154_txrx_statistic_print(void) #endif // CONFIG_IEEE802154_TXRX_STATISTIC +#if CONFIG_IEEE802154_RX_BUFFER_STATISTIC +#define IEEE802154_RX_BUFFER_USED_TOTAL_LEVEL 10 +#define IEEE802154_RX_BUFFER_GET_USED_LEVEL(a) (((a) * IEEE802154_RX_BUFFER_USED_TOTAL_LEVEL) / (CONFIG_IEEE802154_RX_BUFFER_SIZE + 1)) +static uint16_t s_rx_buffer_used_nums = 0; +static uint64_t s_rx_buffer_used_water_level[IEEE802154_RX_BUFFER_USED_TOTAL_LEVEL + 1]; +void ieee802154_rx_buffer_statistic_is_free(bool is_free) +{ + if (is_free) { + s_rx_buffer_used_nums--; + } else { + s_rx_buffer_used_nums++; + // (CONFIG_IEEE802154_RX_BUFFER_SIZE + 1) means buffer full. + if (s_rx_buffer_used_nums > (CONFIG_IEEE802154_RX_BUFFER_SIZE + 1)) { + s_rx_buffer_used_nums = CONFIG_IEEE802154_RX_BUFFER_SIZE + 1; + } + s_rx_buffer_used_water_level[IEEE802154_RX_BUFFER_GET_USED_LEVEL(s_rx_buffer_used_nums)]++; + } +} + +void ieee802154_rx_buffer_statistic_clear(void) +{ + memset((void*)s_rx_buffer_used_water_level, 0, sizeof(uint64_t)*(IEEE802154_RX_BUFFER_USED_TOTAL_LEVEL + 1)); +} + +void ieee802154_rx_buffer_statistic_printf(void) +{ + uint64_t total_times = 0; + for (uint8_t i = 0; i < (IEEE802154_RX_BUFFER_USED_TOTAL_LEVEL + 1); i++) { + total_times += s_rx_buffer_used_water_level[i]; + } + ESP_LOGW(IEEE802154_TAG, "+--------------------+-------------------------+-------------------------+"); + ESP_LOGW(IEEE802154_TAG, "|%-20s|%-25s|%-25u|", "rx buff total size:", "", CONFIG_IEEE802154_RX_BUFFER_SIZE); + ESP_LOGW(IEEE802154_TAG, "|%-20s|%-25s|%-25llu|", "buffer alloc times:", "", total_times); + ESP_LOGW(IEEE802154_TAG, "+--------------------+-------------------------+-------------------------+"); + for (uint8_t i = 0; i < (IEEE802154_RX_BUFFER_USED_TOTAL_LEVEL); i++) { + ESP_LOGW(IEEE802154_TAG, "|%-20s|%4d%%%5s%4d%%%-10s|%-15llu%9.2f%%|", "", ((i) * 100 / IEEE802154_RX_BUFFER_USED_TOTAL_LEVEL), "~", ((i + 1) * 100 / IEEE802154_RX_BUFFER_USED_TOTAL_LEVEL), " used:", s_rx_buffer_used_water_level[i], ((float)s_rx_buffer_used_water_level[i] / (float)total_times)*100); + } + ESP_LOGW(IEEE802154_TAG, "|%-20s|%-25s|%-15llu%9.2f%%|", "", "full used:", s_rx_buffer_used_water_level[IEEE802154_RX_BUFFER_USED_TOTAL_LEVEL], ((float)s_rx_buffer_used_water_level[IEEE802154_RX_BUFFER_USED_TOTAL_LEVEL] / (float)total_times)*100); + ESP_LOGW(IEEE802154_TAG, "+--------------------+-------------------------+-------------------------+"); +} + +#endif // CONFIG_IEEE802154_RX_BUFFER_STATISTIC + #endif // CONFIG_IEEE802154_DEBUG diff --git a/components/ieee802154/driver/esp_ieee802154_dev.c b/components/ieee802154/driver/esp_ieee802154_dev.c index 6ce02905bc4..9df0a3a95c8 100644 --- a/components/ieee802154/driver/esp_ieee802154_dev.c +++ b/components/ieee802154/driver/esp_ieee802154_dev.c @@ -87,7 +87,10 @@ static pending_tx_t s_pending_tx = { 0 }; static void ieee802154_receive_done(uint8_t *data, esp_ieee802154_frame_info_t *frame_info) { // If the RX done packet is written in the stub buffer, drop it silently. - if (s_rx_index != CONFIG_IEEE802154_RX_BUFFER_SIZE) { + IEEE802154_RX_BUFFER_STAT_IS_FREE(false); + if (s_rx_index == CONFIG_IEEE802154_RX_BUFFER_SIZE) { + esp_rom_printf("receive buffer full, drop the current frame.\n"); + } else { // Otherwise, post it to the upper layer. // Ignore bit8 for the frame length, due to the max frame length is 127 based 802.15.4 spec. data[0] = data[0] & 0x7f; @@ -99,6 +102,7 @@ static void ieee802154_receive_done(uint8_t *data, esp_ieee802154_frame_info_t * static void ieee802154_transmit_done(const uint8_t *frame, const uint8_t *ack, esp_ieee802154_frame_info_t *ack_frame_info) { if (ack && ack_frame_info) { + IEEE802154_RX_BUFFER_STAT_IS_FREE(false); if (s_rx_index == CONFIG_IEEE802154_RX_BUFFER_SIZE) { esp_ieee802154_transmit_failed(frame, ESP_IEEE802154_TX_ERR_NO_ACK); } else { @@ -118,6 +122,7 @@ esp_err_t ieee802154_receive_handle_done(const uint8_t *data) return ESP_FAIL; } s_rx_frame_info[size / IEEE802154_RX_FRAME_SIZE].process = false; + IEEE802154_RX_BUFFER_STAT_IS_FREE(true); return ESP_OK; } diff --git a/components/ieee802154/esp_ieee802154.c b/components/ieee802154/esp_ieee802154.c index 796b161a7bb..2d021891a13 100644 --- a/components/ieee802154/esp_ieee802154.c +++ b/components/ieee802154/esp_ieee802154.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2020-2023 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2020-2024 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -414,3 +414,22 @@ void esp_ieee802154_txrx_statistic_print(void) ieee802154_txrx_statistic_print(); } #endif // CONFIG_IEEE802154_TXRX_STATISTIC + +#if CONFIG_IEEE802154_RX_BUFFER_STATISTIC +void esp_ieee802154_rx_buffer_statistic_clear(void) +{ + ieee802154_rx_buffer_statistic_clear(); +} + +void esp_ieee802154_rx_buffer_statistic_printf(void) +{ + ieee802154_rx_buffer_statistic_printf(); +} +#endif // CONFIG_IEEE802154_RX_BUFFER_STATISTIC + +#if CONFIG_IEEE802154_RECORD +void esp_ieee802154_record_print(void) +{ + ieee802154_record_print(); +} +#endif // CONFIG_IEEE802154_RECORD diff --git a/components/ieee802154/include/esp_ieee802154.h b/components/ieee802154/include/esp_ieee802154.h index 51adf6ce00b..90ffb2b41a7 100644 --- a/components/ieee802154/include/esp_ieee802154.h +++ b/components/ieee802154/include/esp_ieee802154.h @@ -623,6 +623,29 @@ void esp_ieee802154_txrx_statistic_clear(void); void esp_ieee802154_txrx_statistic_print(void); #endif // CONFIG_IEEE802154_TXRX_STATISTIC +#if CONFIG_IEEE802154_RX_BUFFER_STATISTIC + +/** + * @brief Print the current IEEE802.15.4 rx buffer statistic. + * + */ +void esp_ieee802154_rx_buffer_statistic_clear(void); + +/** + * @brief Clear the current IEEE802.15.4 rx buffer statistic. + * + */ +void esp_ieee802154_rx_buffer_statistic_printf(void); +#endif // CONFIG_IEEE802154_RX_BUFFER_STATISTIC + +#if CONFIG_IEEE802154_RECORD + +/** + * @brief Print the current IEEE802.15.4 event/command/state record. + * + */ +void esp_ieee802154_record_print(void); +#endif // CONFIG_IEEE802154_RECORD #ifdef __cplusplus } #endif diff --git a/components/ieee802154/private_include/esp_ieee802154_util.h b/components/ieee802154/private_include/esp_ieee802154_util.h index c1e843055a2..843e34117c4 100644 --- a/components/ieee802154/private_include/esp_ieee802154_util.h +++ b/components/ieee802154/private_include/esp_ieee802154_util.h @@ -168,19 +168,27 @@ typedef struct { extern ieee802154_probe_info_t g_ieee802154_probe; -#if CONFIG_IEEE802154_ASSERT +#if CONFIG_IEEE802154_RECORD /** * @brief This function print rich information, which is useful for debug. * Only can be used when `IEEE802154_ASSERT` is enabled. * */ -void ieee802154_assert_print(void); +void ieee802154_record_print(void); +#endif + +#if CONFIG_IEEE802154_ASSERT + +#if CONFIG_IEEE802154_RECORD #define IEEE802154_ASSERT(a) do { \ if(unlikely(!(a))) { \ - ieee802154_assert_print(); \ + ieee802154_record_print(); \ assert(a); \ } \ } while (0) +#else +#error "CONFIG_IEEE802154_RECORD must be enabled when CONFIG_IEEE802154_ASSERT enabled" +#endif #else // CONFIG_IEEE802154_ASSERT #define IEEE802154_ASSERT(a) assert(a) #endif // CONFIG_IEEE802154_ASSERT @@ -249,6 +257,33 @@ void ieee802154_tx_break_coex_nums_update(void); #define IEEE802154_TX_BREAK_COEX_NUMS_UPDATE() #endif // CONFIG_IEEE802154_TXRX_STATISTIC +#if CONFIG_IEEE802154_RX_BUFFER_STATISTIC + +/** + * @brief Count the rx buffer used. + * + * @param[in] is_free True for rx buffer frees and false for rx buffer allocates. + * + */ +void ieee802154_rx_buffer_statistic_is_free(bool is_free); + +/** + * @brief Clear the current IEEE802.15.4 rx buffer statistic. + * + */ +void ieee802154_rx_buffer_statistic_clear(void); + +/** + * @brief Print the current IEEE802.15.4 rx buffer statistic. + * + */ +void ieee802154_rx_buffer_statistic_printf(void); + +#define IEEE802154_RX_BUFFER_STAT_IS_FREE(a) ieee802154_rx_buffer_statistic_is_free(a) +#else +#define IEEE802154_RX_BUFFER_STAT_IS_FREE(a) +#endif + // TODO: replace etm code using common interface #define IEEE802154_ETM_CHANNEL0 0 diff --git a/examples/ieee802154/ieee802154_cli/components/cmd_ieee802154/ieee802154_cmd.c b/examples/ieee802154/ieee802154_cli/components/cmd_ieee802154/ieee802154_cmd.c index 00d62cf73cf..bef801beb48 100644 --- a/examples/ieee802154/ieee802154_cli/components/cmd_ieee802154/ieee802154_cmd.c +++ b/examples/ieee802154/ieee802154_cli/components/cmd_ieee802154/ieee802154_cmd.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2022-2024 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Unlicense OR CC0-1.0 */ diff --git a/examples/ieee802154/ieee802154_cli/components/cmd_ieee802154_stats/CMakeLists.txt b/examples/ieee802154/ieee802154_cli/components/cmd_ieee802154_stats/CMakeLists.txt new file mode 100644 index 00000000000..c59fc3d2d7f --- /dev/null +++ b/examples/ieee802154/ieee802154_cli/components/cmd_ieee802154_stats/CMakeLists.txt @@ -0,0 +1,3 @@ +idf_component_register(SRCS "ieee802154_stats.c" + INCLUDE_DIRS "." + REQUIRES ieee802154 console esp_phy) diff --git a/examples/ieee802154/ieee802154_cli/components/cmd_ieee802154_stats/ieee802154_stats.c b/examples/ieee802154/ieee802154_cli/components/cmd_ieee802154_stats/ieee802154_stats.c new file mode 100644 index 00000000000..dbda393bdcf --- /dev/null +++ b/examples/ieee802154/ieee802154_cli/components/cmd_ieee802154_stats/ieee802154_stats.c @@ -0,0 +1,174 @@ +/* + * SPDX-FileCopyrightText: 2022-2024 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Unlicense OR CC0-1.0 + */ + +#include +#include +#include "esp_log.h" +#include "esp_ieee802154.h" +#include "esp_console.h" +#include "argtable3/argtable3.h" +#include "ieee802154_stats.h" + +#if CONFIG_IEEE802154_DEBUG +static const char* TAG = "i154cmd"; +#if CONFIG_IEEE802154_RX_BUFFER_STATISTIC +static void register_rx_buffer_statistic(void); +#endif + +#if CONFIG_IEEE802154_TXRX_STATISTIC +static void register_txrx_statistic(void); +#endif + +#if CONFIG_IEEE802154_RECORD +static void register_record(void); +#endif + +void register_ieee802154_debug_cmd(void) +{ +#if CONFIG_IEEE802154_RX_BUFFER_STATISTIC + register_rx_buffer_statistic(); +#endif +#if CONFIG_IEEE802154_TXRX_STATISTIC + register_txrx_statistic(); +#endif +#if CONFIG_IEEE802154_RECORD + register_record(); +#endif +} +#endif + +#if CONFIG_IEEE802154_DEBUG +#if CONFIG_IEEE802154_RX_BUFFER_STATISTIC +static struct { + struct arg_lit *clear; + struct arg_lit *print; + struct arg_end *end; +} rx_buff_stat_args; + +static int process_rx_buffer_statistic(int argc, char **argv) +{ + int nerrors = arg_parse(argc, argv, (void **) &rx_buff_stat_args); + if (nerrors != 0) { + arg_print_errors(stderr, rx_buff_stat_args.end, argv[0]); + return 1; + } + if (rx_buff_stat_args.print->count) { + esp_ieee802154_rx_buffer_statistic_printf(); + } + if (rx_buff_stat_args.clear->count) { + esp_ieee802154_rx_buffer_statistic_clear(); + } + if (!rx_buff_stat_args.print->count && !rx_buff_stat_args.clear->count) { + ESP_LOGE(TAG, "no valid arguments"); + return 1; + } + return 0; +} + +static void register_rx_buffer_statistic(void) +{ + rx_buff_stat_args.print = + arg_lit0("p", "print", "print the result of rx buffer statistic"); + rx_buff_stat_args.clear = + arg_lit0("c", "clear", "clear the result of rx buffer statistic"); + rx_buff_stat_args.end = arg_end(2); + + const esp_console_cmd_t cmd = { + .command = "rxbufstat", + .help = "rx buffer statistic", + .hint = NULL, + .func = &process_rx_buffer_statistic, + .argtable = &rx_buff_stat_args + }; + ESP_ERROR_CHECK(esp_console_cmd_register(&cmd)); +} +#endif // CONFIG_IEEE802154_RX_BUFFER_STATISTIC + +#if CONFIG_IEEE802154_TXRX_STATISTIC +static struct { + struct arg_lit *clear; + struct arg_lit *print; + struct arg_end *end; +} txrx_stat_args; + +static int process_txrx_statistic(int argc, char **argv) +{ + int nerrors = arg_parse(argc, argv, (void **) &txrx_stat_args); + if (nerrors != 0) { + arg_print_errors(stderr, txrx_stat_args.end, argv[0]); + return 1; + } + if (txrx_stat_args.print->count) { + esp_ieee802154_txrx_statistic_print(); + } + if (txrx_stat_args.clear->count) { + esp_ieee802154_txrx_statistic_clear(); + } + if (!txrx_stat_args.print->count && !txrx_stat_args.clear->count) { + ESP_LOGE(TAG, "no valid arguments"); + return 1; + } + return 0; +} + +static void register_txrx_statistic(void) +{ + txrx_stat_args.print = + arg_lit0("p", "print", "print the result of txrx statistic"); + txrx_stat_args.clear = + arg_lit0("c", "clear", "clear the result of txrx statistic"); + txrx_stat_args.end = arg_end(2); + + const esp_console_cmd_t cmd = { + .command = "txrxstat", + .help = "txrx statistic", + .hint = NULL, + .func = &process_txrx_statistic, + .argtable = &txrx_stat_args + }; + ESP_ERROR_CHECK(esp_console_cmd_register(&cmd)); +} +#endif // CONFIG_IEEE802154_TXRX_STATISTIC + +#if CONFIG_IEEE802154_RECORD +static struct { + struct arg_lit *print; + struct arg_end *end; +} record_args; + +static int process_record(int argc, char **argv) +{ + int nerrors = arg_parse(argc, argv, (void **) &record_args); + if (nerrors != 0) { + arg_print_errors(stderr, record_args.end, argv[0]); + return 1; + } + if (record_args.print->count) { + esp_ieee802154_record_print(); + } else { + ESP_LOGE(TAG, "no valid arguments"); + return 1; + } + return 0; +} + +static void register_record(void) +{ + record_args.print = + arg_lit0("p", "print", "print the result of the recording"); + record_args.end = arg_end(2); + + const esp_console_cmd_t cmd = { + .command = "record", + .help = "print the recorded IEEE802154 state/event/cmd etc.", + .hint = NULL, + .func = &process_record, + .argtable = &record_args + }; + ESP_ERROR_CHECK(esp_console_cmd_register(&cmd)); +} +#endif // CONFIG_IEEE802154_RECORD +#endif // CONFIG_IEEE802154_DEBUG diff --git a/examples/ieee802154/ieee802154_cli/components/cmd_ieee802154_stats/ieee802154_stats.h b/examples/ieee802154/ieee802154_cli/components/cmd_ieee802154_stats/ieee802154_stats.h new file mode 100644 index 00000000000..bb7157c1408 --- /dev/null +++ b/examples/ieee802154/ieee802154_cli/components/cmd_ieee802154_stats/ieee802154_stats.h @@ -0,0 +1,11 @@ +/* + * SPDX-FileCopyrightText: 2022-2024 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Unlicense OR CC0-1.0 + */ + +#pragma once + +#if CONFIG_IEEE802154_DEBUG +void register_ieee802154_debug_cmd(void); +#endif diff --git a/examples/ieee802154/ieee802154_cli/main/CMakeLists.txt b/examples/ieee802154/ieee802154_cli/main/CMakeLists.txt index 1407c219b1e..eb76f86a735 100644 --- a/examples/ieee802154/ieee802154_cli/main/CMakeLists.txt +++ b/examples/ieee802154/ieee802154_cli/main/CMakeLists.txt @@ -6,5 +6,6 @@ set(include "." # In order for the cases defined by `TEST_CASE` to be linked into the final elf, # the component can be registered as WHOLE_ARCHIVE idf_component_register(SRCS ${srcs} - PRIV_REQUIRES ieee802154 console fatfs nvs_flash esp_phy cmd_ieee802154 cmd_system + PRIV_REQUIRES ieee802154 console fatfs nvs_flash esp_phy cmd_ieee802154 + cmd_ieee802154_stats cmd_system WHOLE_ARCHIVE) diff --git a/examples/ieee802154/ieee802154_cli/main/esp_ieee802154_cli.c b/examples/ieee802154/ieee802154_cli/main/esp_ieee802154_cli.c index 3ad3a546f60..64147755dab 100644 --- a/examples/ieee802154/ieee802154_cli/main/esp_ieee802154_cli.c +++ b/examples/ieee802154/ieee802154_cli/main/esp_ieee802154_cli.c @@ -16,6 +16,7 @@ #include "esp_ieee802154.h" #include "esp_phy_init.h" #include "cmd_system.h" +#include "ieee802154_stats.h" #define PROMPT_STR "ieee802154" @@ -46,6 +47,9 @@ void app_main(void) esp_console_register_help_command(); register_ieee802154_cmd(); register_system_common(); +#if CONFIG_IEEE802154_DEBUG + register_ieee802154_debug_cmd(); +#endif esp_console_dev_uart_config_t hw_config = ESP_CONSOLE_DEV_UART_CONFIG_DEFAULT(); ESP_ERROR_CHECK(esp_console_new_repl_uart(&hw_config, &repl_config, &repl)); From be6c49f79a0027bc292d7a333d35190ef907edb3 Mon Sep 17 00:00:00 2001 From: David Cermak Date: Thu, 28 Nov 2024 12:58:49 +0100 Subject: [PATCH 002/118] fix(lwip): Fix AUTOIP new address after rate limit --- components/lwip/lwip | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/components/lwip/lwip b/components/lwip/lwip index a587d929899..fa4dffdfac5 160000 --- a/components/lwip/lwip +++ b/components/lwip/lwip @@ -1 +1 @@ -Subproject commit a587d929899304264d81a469dc843316d0db5e64 +Subproject commit fa4dffdfac52587a26c1f29258376df750cf8474 From cdcf2973f7c61bee0117a871dd4a403e4376f9ff Mon Sep 17 00:00:00 2001 From: Tan Yan Quan Date: Thu, 28 Nov 2024 20:09:07 +0800 Subject: [PATCH 003/118] feat(802.15.4): IEEE802.15.4 add some minor edits for readability --- components/ieee802154/driver/esp_ieee802154_debug.c | 3 ++- components/ieee802154/driver/esp_ieee802154_dev.c | 4 +--- components/ieee802154/esp_ieee802154.c | 4 ++-- components/ieee802154/include/esp_ieee802154.h | 2 +- components/ieee802154/private_include/esp_ieee802154_util.h | 4 ++-- .../ieee802154_cli/components/cmd_ieee802154/ieee802154_cmd.c | 2 +- .../components/cmd_ieee802154_stats/ieee802154_stats.c | 2 +- 7 files changed, 10 insertions(+), 11 deletions(-) diff --git a/components/ieee802154/driver/esp_ieee802154_debug.c b/components/ieee802154/driver/esp_ieee802154_debug.c index 7dec9832134..71847308b67 100644 --- a/components/ieee802154/driver/esp_ieee802154_debug.c +++ b/components/ieee802154/driver/esp_ieee802154_debug.c @@ -375,6 +375,7 @@ void ieee802154_txrx_statistic_print(void) #define IEEE802154_RX_BUFFER_GET_USED_LEVEL(a) (((a) * IEEE802154_RX_BUFFER_USED_TOTAL_LEVEL) / (CONFIG_IEEE802154_RX_BUFFER_SIZE + 1)) static uint16_t s_rx_buffer_used_nums = 0; static uint64_t s_rx_buffer_used_water_level[IEEE802154_RX_BUFFER_USED_TOTAL_LEVEL + 1]; + void ieee802154_rx_buffer_statistic_is_free(bool is_free) { if (is_free) { @@ -394,7 +395,7 @@ void ieee802154_rx_buffer_statistic_clear(void) memset((void*)s_rx_buffer_used_water_level, 0, sizeof(uint64_t)*(IEEE802154_RX_BUFFER_USED_TOTAL_LEVEL + 1)); } -void ieee802154_rx_buffer_statistic_printf(void) +void ieee802154_rx_buffer_statistic_print(void) { uint64_t total_times = 0; for (uint8_t i = 0; i < (IEEE802154_RX_BUFFER_USED_TOTAL_LEVEL + 1); i++) { diff --git a/components/ieee802154/driver/esp_ieee802154_dev.c b/components/ieee802154/driver/esp_ieee802154_dev.c index 9df0a3a95c8..d4efd627792 100644 --- a/components/ieee802154/driver/esp_ieee802154_dev.c +++ b/components/ieee802154/driver/esp_ieee802154_dev.c @@ -88,9 +88,7 @@ static void ieee802154_receive_done(uint8_t *data, esp_ieee802154_frame_info_t * { // If the RX done packet is written in the stub buffer, drop it silently. IEEE802154_RX_BUFFER_STAT_IS_FREE(false); - if (s_rx_index == CONFIG_IEEE802154_RX_BUFFER_SIZE) { - esp_rom_printf("receive buffer full, drop the current frame.\n"); - } else { + if (s_rx_index != CONFIG_IEEE802154_RX_BUFFER_SIZE) { // Otherwise, post it to the upper layer. // Ignore bit8 for the frame length, due to the max frame length is 127 based 802.15.4 spec. data[0] = data[0] & 0x7f; diff --git a/components/ieee802154/esp_ieee802154.c b/components/ieee802154/esp_ieee802154.c index 2d021891a13..0b77579c7ff 100644 --- a/components/ieee802154/esp_ieee802154.c +++ b/components/ieee802154/esp_ieee802154.c @@ -421,9 +421,9 @@ void esp_ieee802154_rx_buffer_statistic_clear(void) ieee802154_rx_buffer_statistic_clear(); } -void esp_ieee802154_rx_buffer_statistic_printf(void) +void esp_ieee802154_rx_buffer_statistic_print(void) { - ieee802154_rx_buffer_statistic_printf(); + ieee802154_rx_buffer_statistic_print(); } #endif // CONFIG_IEEE802154_RX_BUFFER_STATISTIC diff --git a/components/ieee802154/include/esp_ieee802154.h b/components/ieee802154/include/esp_ieee802154.h index 90ffb2b41a7..5ad7998d79d 100644 --- a/components/ieee802154/include/esp_ieee802154.h +++ b/components/ieee802154/include/esp_ieee802154.h @@ -635,7 +635,7 @@ void esp_ieee802154_rx_buffer_statistic_clear(void); * @brief Clear the current IEEE802.15.4 rx buffer statistic. * */ -void esp_ieee802154_rx_buffer_statistic_printf(void); +void esp_ieee802154_rx_buffer_statistic_print(void); #endif // CONFIG_IEEE802154_RX_BUFFER_STATISTIC #if CONFIG_IEEE802154_RECORD diff --git a/components/ieee802154/private_include/esp_ieee802154_util.h b/components/ieee802154/private_include/esp_ieee802154_util.h index 843e34117c4..f33fc5823cf 100644 --- a/components/ieee802154/private_include/esp_ieee802154_util.h +++ b/components/ieee802154/private_include/esp_ieee802154_util.h @@ -277,12 +277,12 @@ void ieee802154_rx_buffer_statistic_clear(void); * @brief Print the current IEEE802.15.4 rx buffer statistic. * */ -void ieee802154_rx_buffer_statistic_printf(void); +void ieee802154_rx_buffer_statistic_print(void); #define IEEE802154_RX_BUFFER_STAT_IS_FREE(a) ieee802154_rx_buffer_statistic_is_free(a) #else #define IEEE802154_RX_BUFFER_STAT_IS_FREE(a) -#endif +#endif // CONFIG_IEEE802154_RX_BUFFER_STATISTIC // TODO: replace etm code using common interface diff --git a/examples/ieee802154/ieee802154_cli/components/cmd_ieee802154/ieee802154_cmd.c b/examples/ieee802154/ieee802154_cli/components/cmd_ieee802154/ieee802154_cmd.c index bef801beb48..00d62cf73cf 100644 --- a/examples/ieee802154/ieee802154_cli/components/cmd_ieee802154/ieee802154_cmd.c +++ b/examples/ieee802154/ieee802154_cli/components/cmd_ieee802154/ieee802154_cmd.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2022-2024 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Unlicense OR CC0-1.0 */ diff --git a/examples/ieee802154/ieee802154_cli/components/cmd_ieee802154_stats/ieee802154_stats.c b/examples/ieee802154/ieee802154_cli/components/cmd_ieee802154_stats/ieee802154_stats.c index dbda393bdcf..2941be74d49 100644 --- a/examples/ieee802154/ieee802154_cli/components/cmd_ieee802154_stats/ieee802154_stats.c +++ b/examples/ieee802154/ieee802154_cli/components/cmd_ieee802154_stats/ieee802154_stats.c @@ -56,7 +56,7 @@ static int process_rx_buffer_statistic(int argc, char **argv) return 1; } if (rx_buff_stat_args.print->count) { - esp_ieee802154_rx_buffer_statistic_printf(); + esp_ieee802154_rx_buffer_statistic_print(); } if (rx_buff_stat_args.clear->count) { esp_ieee802154_rx_buffer_statistic_clear(); From 7515df3ee2dc07bcada0b0aa6e163cb5f0e56392 Mon Sep 17 00:00:00 2001 From: Tan Yan Quan Date: Fri, 29 Nov 2024 15:54:53 +0800 Subject: [PATCH 004/118] feat(802.15.4): IEEE802.15.4 add documentation and refactor component structure --- .../ieee802154/driver/esp_ieee802154_debug.c | 14 ++-- .../cmd_ieee802154_debug}/CMakeLists.txt | 2 +- .../components/cmd_ieee802154_debug/README.md | 68 +++++++++++++++++++ .../cmd_ieee802154_debug/ieee802154_debug.c} | 9 +-- .../cmd_ieee802154_debug/ieee802154_debug.h} | 0 .../ieee802154_cli/main/CMakeLists.txt | 2 +- .../ieee802154_cli/main/esp_ieee802154_cli.c | 2 +- .../ieee802154_cli/main/idf_component.yml | 2 + 8 files changed, 85 insertions(+), 14 deletions(-) rename examples/ieee802154/{ieee802154_cli/components/cmd_ieee802154_stats => components/cmd_ieee802154_debug}/CMakeLists.txt (65%) create mode 100644 examples/ieee802154/components/cmd_ieee802154_debug/README.md rename examples/ieee802154/{ieee802154_cli/components/cmd_ieee802154_stats/ieee802154_stats.c => components/cmd_ieee802154_debug/ieee802154_debug.c} (94%) rename examples/ieee802154/{ieee802154_cli/components/cmd_ieee802154_stats/ieee802154_stats.h => components/cmd_ieee802154_debug/ieee802154_debug.h} (100%) diff --git a/components/ieee802154/driver/esp_ieee802154_debug.c b/components/ieee802154/driver/esp_ieee802154_debug.c index 71847308b67..cd5041f9107 100644 --- a/components/ieee802154/driver/esp_ieee802154_debug.c +++ b/components/ieee802154/driver/esp_ieee802154_debug.c @@ -401,15 +401,15 @@ void ieee802154_rx_buffer_statistic_print(void) for (uint8_t i = 0; i < (IEEE802154_RX_BUFFER_USED_TOTAL_LEVEL + 1); i++) { total_times += s_rx_buffer_used_water_level[i]; } - ESP_LOGW(IEEE802154_TAG, "+--------------------+-------------------------+-------------------------+"); - ESP_LOGW(IEEE802154_TAG, "|%-20s|%-25s|%-25u|", "rx buff total size:", "", CONFIG_IEEE802154_RX_BUFFER_SIZE); - ESP_LOGW(IEEE802154_TAG, "|%-20s|%-25s|%-25llu|", "buffer alloc times:", "", total_times); - ESP_LOGW(IEEE802154_TAG, "+--------------------+-------------------------+-------------------------+"); + ESP_LOGW(IEEE802154_TAG, "+-------------------------+-------------------------+"); + ESP_LOGW(IEEE802154_TAG, "|%25s|%-25u|", "rx buff total size:", CONFIG_IEEE802154_RX_BUFFER_SIZE); + ESP_LOGW(IEEE802154_TAG, "|%25s|%-25llu|", "buffer alloc times:", total_times); + ESP_LOGW(IEEE802154_TAG, "+-------------------------+-------------------------+"); for (uint8_t i = 0; i < (IEEE802154_RX_BUFFER_USED_TOTAL_LEVEL); i++) { - ESP_LOGW(IEEE802154_TAG, "|%-20s|%4d%%%5s%4d%%%-10s|%-15llu%9.2f%%|", "", ((i) * 100 / IEEE802154_RX_BUFFER_USED_TOTAL_LEVEL), "~", ((i + 1) * 100 / IEEE802154_RX_BUFFER_USED_TOTAL_LEVEL), " used:", s_rx_buffer_used_water_level[i], ((float)s_rx_buffer_used_water_level[i] / (float)total_times)*100); + ESP_LOGW(IEEE802154_TAG, "|%4d%%%5s%4d%%%10s|%-15llu%9.2f%%|", ((i) * 100 / IEEE802154_RX_BUFFER_USED_TOTAL_LEVEL), "~", ((i + 1) * 100 / IEEE802154_RX_BUFFER_USED_TOTAL_LEVEL), " used:", s_rx_buffer_used_water_level[i], ((float)s_rx_buffer_used_water_level[i] / (float)total_times)*100); } - ESP_LOGW(IEEE802154_TAG, "|%-20s|%-25s|%-15llu%9.2f%%|", "", "full used:", s_rx_buffer_used_water_level[IEEE802154_RX_BUFFER_USED_TOTAL_LEVEL], ((float)s_rx_buffer_used_water_level[IEEE802154_RX_BUFFER_USED_TOTAL_LEVEL] / (float)total_times)*100); - ESP_LOGW(IEEE802154_TAG, "+--------------------+-------------------------+-------------------------+"); + ESP_LOGW(IEEE802154_TAG, "|%25s|%-15llu%9.2f%%|", "full used:", s_rx_buffer_used_water_level[IEEE802154_RX_BUFFER_USED_TOTAL_LEVEL], ((float)s_rx_buffer_used_water_level[IEEE802154_RX_BUFFER_USED_TOTAL_LEVEL] / (float)total_times)*100); + ESP_LOGW(IEEE802154_TAG, "+-------------------------+-------------------------+"); } #endif // CONFIG_IEEE802154_RX_BUFFER_STATISTIC diff --git a/examples/ieee802154/ieee802154_cli/components/cmd_ieee802154_stats/CMakeLists.txt b/examples/ieee802154/components/cmd_ieee802154_debug/CMakeLists.txt similarity index 65% rename from examples/ieee802154/ieee802154_cli/components/cmd_ieee802154_stats/CMakeLists.txt rename to examples/ieee802154/components/cmd_ieee802154_debug/CMakeLists.txt index c59fc3d2d7f..24b8958a9e5 100644 --- a/examples/ieee802154/ieee802154_cli/components/cmd_ieee802154_stats/CMakeLists.txt +++ b/examples/ieee802154/components/cmd_ieee802154_debug/CMakeLists.txt @@ -1,3 +1,3 @@ -idf_component_register(SRCS "ieee802154_stats.c" +idf_component_register(SRCS "ieee802154_debug.c" INCLUDE_DIRS "." REQUIRES ieee802154 console esp_phy) diff --git a/examples/ieee802154/components/cmd_ieee802154_debug/README.md b/examples/ieee802154/components/cmd_ieee802154_debug/README.md new file mode 100644 index 00000000000..1393266cc9c --- /dev/null +++ b/examples/ieee802154/components/cmd_ieee802154_debug/README.md @@ -0,0 +1,68 @@ +| Supported Targets | ESP32-C5 | ESP32-C6 | ESP32-H2 | +| ----------------- | -------- | -------- | -------- | + +# IEEE802.15.4 RX Buffer Statistics Component + +This component is used to consolidate the RX buffer statistics for IEEE802.15.4. The use of this component is demonstrated in the `ieee802154_cli` example, but can be similarly implemented for other stack examples (e.g. Zigbee / Thread). + +## How to use component + +In addition to the necessary configurations described in the `ieee802154_cli` example, some additional steps are required for configuring the board to enable the RX buffer statistics component. + +``` +idf.py menuconfig +``` + +This component can be enabled through the menuconfig: + +``` +Component config → IEEE 802.15.4 → IEEE802154 Enable → Enable IEEE802154 Debug → Rx buffer statistic +``` + +### Build, Flash, and Run + +Build the project and flash it to the board, then run monitor tool to view serial output: + +``` +idf.py -p PORT build flash monitor +``` + +Now you'll get an IEEE802.15.4 command line shell. + +## IEEE802.15.4 Command List + +In addition to the commands available in the `ieee802154_cli` example, enabling this component provides a new command: + +- [rxbufstat](#rxbufstat) + +### rxbufstat +#### rxbufstat -p +Print a summary table of rx buffer statistics. + +```bash +> rxbufstat -p +W (913011) ieee802154: +-------------------------+-------------------------+ +W (913011) ieee802154: | rx buff total size:|20 | +W (913021) ieee802154: | buffer alloc times:|80 | +W (913021) ieee802154: +-------------------------+-------------------------+ +W (913031) ieee802154: | 0% ~ 10% used:|80 100.00%| +W (913031) ieee802154: | 10% ~ 20% used:|0 0.00%| +W (913041) ieee802154: | 20% ~ 30% used:|0 0.00%| +W (913051) ieee802154: | 30% ~ 40% used:|0 0.00%| +W (913051) ieee802154: | 40% ~ 50% used:|0 0.00%| +W (913061) ieee802154: | 50% ~ 60% used:|0 0.00%| +W (913061) ieee802154: | 60% ~ 70% used:|0 0.00%| +W (913081) ieee802154: | 70% ~ 80% used:|0 0.00%| +W (913091) ieee802154: | 80% ~ 90% used:|0 0.00%| +W (913091) ieee802154: | 90% ~ 100% used:|0 0.00%| +W (913101) ieee802154: | full used:|0 0.00%| +W (913101) ieee802154: +-------------------------+-------------------------+ +``` + +#### rxbufstat -c +Clear the rx buffer statistics. + +```bash +> rxbufstat -c +I (7971) i154cmd: clear the rx buffer statistics +``` \ No newline at end of file diff --git a/examples/ieee802154/ieee802154_cli/components/cmd_ieee802154_stats/ieee802154_stats.c b/examples/ieee802154/components/cmd_ieee802154_debug/ieee802154_debug.c similarity index 94% rename from examples/ieee802154/ieee802154_cli/components/cmd_ieee802154_stats/ieee802154_stats.c rename to examples/ieee802154/components/cmd_ieee802154_debug/ieee802154_debug.c index 2941be74d49..b97a53050c5 100644 --- a/examples/ieee802154/ieee802154_cli/components/cmd_ieee802154_stats/ieee802154_stats.c +++ b/examples/ieee802154/components/cmd_ieee802154_debug/ieee802154_debug.c @@ -10,7 +10,7 @@ #include "esp_ieee802154.h" #include "esp_console.h" #include "argtable3/argtable3.h" -#include "ieee802154_stats.h" +#include "ieee802154_debug.h" #if CONFIG_IEEE802154_DEBUG static const char* TAG = "i154cmd"; @@ -60,6 +60,7 @@ static int process_rx_buffer_statistic(int argc, char **argv) } if (rx_buff_stat_args.clear->count) { esp_ieee802154_rx_buffer_statistic_clear(); + ESP_LOGI(TAG, "clear the rx buffer statistics"); } if (!rx_buff_stat_args.print->count && !rx_buff_stat_args.clear->count) { ESP_LOGE(TAG, "no valid arguments"); @@ -71,14 +72,14 @@ static int process_rx_buffer_statistic(int argc, char **argv) static void register_rx_buffer_statistic(void) { rx_buff_stat_args.print = - arg_lit0("p", "print", "print the result of rx buffer statistic"); + arg_lit0("p", "print", "print a summary table of rx buffer statistics"); rx_buff_stat_args.clear = - arg_lit0("c", "clear", "clear the result of rx buffer statistic"); + arg_lit0("c", "clear", "clear the rx buffer statistics"); rx_buff_stat_args.end = arg_end(2); const esp_console_cmd_t cmd = { .command = "rxbufstat", - .help = "rx buffer statistic", + .help = "rx buffer statistics", .hint = NULL, .func = &process_rx_buffer_statistic, .argtable = &rx_buff_stat_args diff --git a/examples/ieee802154/ieee802154_cli/components/cmd_ieee802154_stats/ieee802154_stats.h b/examples/ieee802154/components/cmd_ieee802154_debug/ieee802154_debug.h similarity index 100% rename from examples/ieee802154/ieee802154_cli/components/cmd_ieee802154_stats/ieee802154_stats.h rename to examples/ieee802154/components/cmd_ieee802154_debug/ieee802154_debug.h diff --git a/examples/ieee802154/ieee802154_cli/main/CMakeLists.txt b/examples/ieee802154/ieee802154_cli/main/CMakeLists.txt index eb76f86a735..5c3a65e600c 100644 --- a/examples/ieee802154/ieee802154_cli/main/CMakeLists.txt +++ b/examples/ieee802154/ieee802154_cli/main/CMakeLists.txt @@ -7,5 +7,5 @@ set(include "." # the component can be registered as WHOLE_ARCHIVE idf_component_register(SRCS ${srcs} PRIV_REQUIRES ieee802154 console fatfs nvs_flash esp_phy cmd_ieee802154 - cmd_ieee802154_stats cmd_system + cmd_ieee802154_debug cmd_system WHOLE_ARCHIVE) diff --git a/examples/ieee802154/ieee802154_cli/main/esp_ieee802154_cli.c b/examples/ieee802154/ieee802154_cli/main/esp_ieee802154_cli.c index 64147755dab..fb66b716893 100644 --- a/examples/ieee802154/ieee802154_cli/main/esp_ieee802154_cli.c +++ b/examples/ieee802154/ieee802154_cli/main/esp_ieee802154_cli.c @@ -16,7 +16,7 @@ #include "esp_ieee802154.h" #include "esp_phy_init.h" #include "cmd_system.h" -#include "ieee802154_stats.h" +#include "ieee802154_debug.h" #define PROMPT_STR "ieee802154" diff --git a/examples/ieee802154/ieee802154_cli/main/idf_component.yml b/examples/ieee802154/ieee802154_cli/main/idf_component.yml index 77b231f2a7f..670c948277b 100644 --- a/examples/ieee802154/ieee802154_cli/main/idf_component.yml +++ b/examples/ieee802154/ieee802154_cli/main/idf_component.yml @@ -2,3 +2,5 @@ dependencies: cmd_system: path: ${IDF_PATH}/examples/system/console/advanced/components/cmd_system + cmd_ieee802154_debug: + path: ${IDF_PATH}/examples/ieee802154/components/cmd_ieee802154_debug From 37a7528af4b78961a124fb073415b2d14a1180c1 Mon Sep 17 00:00:00 2001 From: muhaidong Date: Tue, 8 Oct 2024 15:58:50 +0800 Subject: [PATCH 005/118] feat(wifi): Add exp-extconn to document WiFi expansion on wifi-less chips --- docs/en/api-guides/wifi-expansion.rst | 22 +++++++++++++++++-- .../libs-frameworks.rst | 2 ++ 2 files changed, 22 insertions(+), 2 deletions(-) diff --git a/docs/en/api-guides/wifi-expansion.rst b/docs/en/api-guides/wifi-expansion.rst index 8c11b7704ba..164a7270507 100644 --- a/docs/en/api-guides/wifi-expansion.rst +++ b/docs/en/api-guides/wifi-expansion.rst @@ -9,9 +9,12 @@ Wi-Fi Expansion .. only:: SOC_WIFI_SUPPORTED - {IDF_TARGET_NAME} does support Wi-Fi functionality natively, please refer to :doc:`wifi` documentation. Even though Wi-Fi is supported on {IDF_TARGET_NAME}, it is possible to expand it and use another instance of Wi-Fi expansion interfaces using esp_wifi_remote `_ component. + {IDF_TARGET_NAME} does support Wi-Fi functionality natively, please refer to :doc:`wifi` documentation. Even though Wi-Fi is supported on {IDF_TARGET_NAME}, it is possible to expand it and use another instance of Wi-Fi expansion interfaces using `esp_wifi_remote `_ component. +{IDF_TARGET_NAME} esp_wifi_remote +--------------------------------- + The principle of Wi-Fi Expansion operation is to add another ESP32 series, Wi-Fi capable, target connected to the {IDF_TARGET_NAME} in a pre-defined way. Your project could then include the `esp_wifi_remote `_ component using: .. code:: bash @@ -21,7 +24,22 @@ The principle of Wi-Fi Expansion operation is to add another ESP32 series, Wi-Fi Please follow the instructions described in the `esp_wifi_remote documentation `_. - .. only:: not SOC_WIFI_SUPPORTED To explore the Wi-Fi Expansion functionality on {IDF_TARGET_NAME}, you can get started with this example: :idf_file:`examples/protocols/mqtt/tcp/README.md` and choose Wi-Fi connection in the project configuration menu. + +.. only:: SOC_WIRELESS_HOST_SUPPORTED + + {IDF_TARGET_NAME} esp-extconn + ----------------------------------------- + + The principle of esp-extconn operation is to add another supported target series connected to the {IDF_TARGET_NAME} in a pre-defined way. Compared to the esp_wifi_remote approach, the target side can operate without flash, as the firmware is delivered by the hosted side. Your project could then include the `esp-extconn `_ component using: + + .. code:: bash + + idf.py add-dependency esp-extconn + + + Please follow the instructions described in the `esp-extconn documentation `_. + + To explore the esp-extconn functionality on {IDF_TARGET_NAME}, you can get started with this example: :idf_file:`examples/wifi/iperf/README.md` and choose Wi-Fi connection in the project configuration menu. diff --git a/docs/en/libraries-and-frameworks/libs-frameworks.rst b/docs/en/libraries-and-frameworks/libs-frameworks.rst index 5c18c5b1364..5da641982e9 100644 --- a/docs/en/libraries-and-frameworks/libs-frameworks.rst +++ b/docs/en/libraries-and-frameworks/libs-frameworks.rst @@ -98,6 +98,8 @@ ESP-Protocols components: * `esp_wifi_remote `_ is a Wi-Fi communication library that provides standard Wi-Fi API and networking of an external, Wi-Fi capable ESP32 chipset connected to the target device via a specified transport interface. See the :doc:`../api-guides/wifi-expansion`. +* `esp-extconn `_ is a Wi-Fi communication library that provides external wireless connectivity(Wi-Fi & Bluetooth) for ESP chips that do not have built-in wireless capabilities. See the :doc:`../api-guides/wifi-expansion`. + ESP-BSP ------- From d5d1bcb9f009b51234a031dbc879fd61602bc17c Mon Sep 17 00:00:00 2001 From: muhaidong Date: Tue, 8 Oct 2024 15:58:02 +0800 Subject: [PATCH 006/118] fix(docs): remove wifi related docs from docs_not_updated for esp32p4 --- docs/docs_not_updated/esp32p4.txt | 12 ------------ 1 file changed, 12 deletions(-) diff --git a/docs/docs_not_updated/esp32p4.txt b/docs/docs_not_updated/esp32p4.txt index fff012c1189..dc5c69dde7a 100644 --- a/docs/docs_not_updated/esp32p4.txt +++ b/docs/docs_not_updated/esp32p4.txt @@ -1,18 +1,6 @@ api-guides/partition-tables.rst -api-guides/RF_calibration.rst -api-guides/coexist.rst -api-guides/wifi.rst api-guides/usb-otg-console.rst -api-guides/esp-wifi-mesh.rst api-guides/dfu.rst -api-guides/wifi-security.rst api-reference/peripherals/adc_calibration.rst api-reference/peripherals/parlio.rst api-reference/peripherals/sd_pullup_requirements.rst -api-reference/network/esp_dpp.rst -api-reference/network/esp_now.rst -api-reference/network/esp-wifi-mesh.rst -api-reference/network/esp_smartconfig.rst -api-reference/network/esp_nan.rst -api-reference/network/esp_wifi.rst -api-reference/network/index.rst From 10115792ac061042aa173064dc8dbd78792fc967 Mon Sep 17 00:00:00 2001 From: Alexey Lapshin Date: Mon, 28 Oct 2024 16:28:25 +0700 Subject: [PATCH 007/118] fix(espcoredump): fix GCC-14 analyzer warnings for coredump --- components/esp_system/port/soc/esp32c61/system_internal.c | 5 ++--- components/espcoredump/src/core_dump_elf.c | 6 +++--- 2 files changed, 5 insertions(+), 6 deletions(-) diff --git a/components/esp_system/port/soc/esp32c61/system_internal.c b/components/esp_system/port/soc/esp32c61/system_internal.c index d5593fa9f28..94f6783b5ff 100644 --- a/components/esp_system/port/soc/esp32c61/system_internal.c +++ b/components/esp_system/port/soc/esp32c61/system_internal.c @@ -8,6 +8,7 @@ #include "sdkconfig.h" #include "esp_system.h" #include "esp_private/system_internal.h" +#include "esp_macros.h" #include "esp_attr.h" #include "esp_log.h" #include "esp_rom_sys.h" @@ -114,7 +115,5 @@ void IRAM_ATTR esp_restart_noos(void) // Reset PRO CPU esp_rom_software_reset_cpu(0); - while (true) { - ; - } + ESP_INFINITE_LOOP(); } diff --git a/components/espcoredump/src/core_dump_elf.c b/components/espcoredump/src/core_dump_elf.c index 57ea48e115e..cdd3420cc51 100644 --- a/components/espcoredump/src/core_dump_elf.c +++ b/components/espcoredump/src/core_dump_elf.c @@ -209,7 +209,7 @@ static int elf_write_note_header(core_dump_elf_t *self, elf_note note_hdr = { 0 }; memcpy(name_buffer, name, name_len); - note_hdr.n_namesz = ALIGN_UP(name_len, 4); + note_hdr.n_namesz = ALIGN_UP(name_len + 1, 4); note_hdr.n_descsz = data_sz; note_hdr.n_type = type; // write note header @@ -242,7 +242,7 @@ static int elf_write_note(core_dump_elf_t *self, // write segment data during second pass if (self->elf_stage == ELF_STAGE_PLACE_DATA) { ELF_CHECK_ERR(data, ELF_PROC_ERR_OTHER, "Invalid data pointer %x.", (uint32_t)data); - err = elf_write_note_header(self, name, name_len, data_sz, type); + err = elf_write_note_header(self, name, strlen(name), data_sz, type); if (err != ESP_OK) { return err; } @@ -688,7 +688,7 @@ static void elf_write_core_dump_note_cb(void *opaque, const char *data) static int elf_add_wdt_panic_details(core_dump_elf_t *self) { - uint32_t name_len = sizeof(ELF_ESP_CORE_DUMP_PANIC_DETAILS_NOTE_NAME); + uint32_t name_len = sizeof(ELF_ESP_CORE_DUMP_PANIC_DETAILS_NOTE_NAME) - 1; core_dump_elf_opaque_t param = { .self = self, .total_size = 0, From dc3c5956b1518a6d0ba0962597b64bff6d61f196 Mon Sep 17 00:00:00 2001 From: Erhan Kurubas Date: Fri, 29 Nov 2024 13:02:15 +0100 Subject: [PATCH 008/118] fix(espcoredump): fix incorrect pointer usage in checksum update call --- components/espcoredump/src/core_dump_flash.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/components/espcoredump/src/core_dump_flash.c b/components/espcoredump/src/core_dump_flash.c index 2cd6bfb55bb..ece2af211ad 100644 --- a/components/espcoredump/src/core_dump_flash.c +++ b/components/espcoredump/src/core_dump_flash.c @@ -185,7 +185,7 @@ static esp_err_t esp_core_dump_flash_write_data(core_dump_write_data_t* wr_data, wr_data->off += COREDUMP_CACHE_SIZE; /* Update checksum with the newly written data on the flash. */ - esp_core_dump_checksum_update(&wr_data->checksum_ctx, &wr_data->cached_data, COREDUMP_CACHE_SIZE); + esp_core_dump_checksum_update(&wr_data->checksum_ctx, wr_data->cached_data, COREDUMP_CACHE_SIZE); /* Reset cache from the next use. */ wr_data->cached_bytes = 0; From 62d59751c0a901fb6e4b8688497d98e3ad716097 Mon Sep 17 00:00:00 2001 From: Erhan Kurubas Date: Fri, 29 Nov 2024 13:36:07 +0100 Subject: [PATCH 009/118] change(tools): enhance `expect_reg_dump` to support any or specific core values --- tools/test_apps/system/panic/pytest_panic.py | 4 ++-- .../system/panic/test_panic_util/panic_dut.py | 10 +++++++--- 2 files changed, 9 insertions(+), 5 deletions(-) diff --git a/tools/test_apps/system/panic/pytest_panic.py b/tools/test_apps/system/panic/pytest_panic.py index c4b45cb31e9..1b0c2f3c673 100644 --- a/tools/test_apps/system/panic/pytest_panic.py +++ b/tools/test_apps/system/panic/pytest_panic.py @@ -1077,11 +1077,11 @@ def test_tcb_corrupted(dut: PanicTestDut, target: str, config: str, test_func_na dut.run_test_func(test_func_name) if dut.is_xtensa: dut.expect_gme('LoadProhibited') - dut.expect_reg_dump(0) + dut.expect_reg_dump() dut.expect_backtrace() else: dut.expect_gme('Load access fault') - dut.expect_reg_dump(0) + dut.expect_reg_dump() dut.expect_stack_dump() dut.expect_elf_sha256() diff --git a/tools/test_apps/system/panic/test_panic_util/panic_dut.py b/tools/test_apps/system/panic/test_panic_util/panic_dut.py index ba104f4af80..ff8004cb850 100644 --- a/tools/test_apps/system/panic/test_panic_util/panic_dut.py +++ b/tools/test_apps/system/panic/test_panic_util/panic_dut.py @@ -96,9 +96,13 @@ def expect_gme(self, reason: str) -> None: """Expect method for Guru Meditation Errors""" self.expect_exact(f"Guru Meditation Error: Core 0 panic'ed ({reason})") - def expect_reg_dump(self, core: int = 0) -> None: - """Expect method for the register dump""" - self.expect(r'Core\s+%d register dump:' % core) + def expect_reg_dump(self, core: Optional[int] = None) -> None: + if core is None: + # Match any core num + self.expect(r'Core\s+\d+\s+register dump:') + else: + # Match the exact core num provided + self.expect(r'Core\s+%d\s+register dump:' % core) def expect_cpu_reset(self) -> None: # no digital system reset for panic handling restarts (see IDF-7255) From 36ee603be9244dc396c4cdfec1aac0dade0e7b46 Mon Sep 17 00:00:00 2001 From: Erhan Kurubas Date: Sat, 30 Nov 2024 15:15:01 +0100 Subject: [PATCH 010/118] fix(espcoredump): prevent null pointer dereference in panic reason handling --- components/esp_system/panic.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/components/esp_system/panic.c b/components/esp_system/panic.c index 35f50785e48..ff9043ac31a 100644 --- a/components/esp_system/panic.c +++ b/components/esp_system/panic.c @@ -301,7 +301,7 @@ void esp_panic_handler(panic_info_t *info) char *panic_reason_str = NULL; if (info->pseudo_excause) { panic_reason_str = (char *)info->reason; - } else if (g_panic_abort && strlen(g_panic_abort_details)) { + } else if (g_panic_abort) { panic_reason_str = g_panic_abort_details; } if (panic_reason_str) { From 1e3dbeb6a82619fd3ffc0965958f1d2896e79034 Mon Sep 17 00:00:00 2001 From: Song Ruo Jing Date: Thu, 5 Dec 2024 11:39:44 +0800 Subject: [PATCH 011/118] fix(ledc): fix ledc driver coverity issues --- components/esp_driver_ledc/src/ledc.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/components/esp_driver_ledc/src/ledc.c b/components/esp_driver_ledc/src/ledc.c index 841d193a468..d7ecef8bcf0 100644 --- a/components/esp_driver_ledc/src/ledc.c +++ b/components/esp_driver_ledc/src/ledc.c @@ -1335,6 +1335,7 @@ static esp_err_t _ledc_set_fade_with_step(ledc_mode_t speed_mode, ledc_channel_t ledc_hal_get_duty(&(p_ledc_obj[speed_mode]->ledc_hal), channel, &duty_cur); // When duty == max_duty, meanwhile, if scale == 1 and fade_down == 1, counter would overflow. if (duty_cur == ledc_get_max_duty(speed_mode, channel)) { + assert(duty_cur > 0); duty_cur -= 1; } s_ledc_fade_rec[speed_mode][channel]->speed_mode = speed_mode; @@ -1776,7 +1777,7 @@ esp_err_t ledc_fill_multi_fade_param_list(ledc_mode_t speed_mode, ledc_channel_t } surplus_cycles_last_phase = cycles_per_phase - step * cycle; // If next phase is the last one, then account for all remaining duty and cycles - if (i == linear_phase_num - 2) { + if (linear_phase_num >= 2 && i == linear_phase_num - 2) { phase_tail = end_duty; surplus_cycles_last_phase += total_cycles - avg_cycles_per_phase * linear_phase_num; } From 83c244ecad30c4e777bdf04eb9cccc7dc3bf314f Mon Sep 17 00:00:00 2001 From: Song Ruo Jing Date: Thu, 5 Dec 2024 11:51:50 +0800 Subject: [PATCH 012/118] fix(ledc): fix ledc_get_freq calculation err due to overflow Closes https://github.com/espressif/esp-idf/pull/14882 --- components/esp_driver_ledc/src/ledc.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/components/esp_driver_ledc/src/ledc.c b/components/esp_driver_ledc/src/ledc.c index d7ecef8bcf0..be71b406382 100644 --- a/components/esp_driver_ledc/src/ledc.c +++ b/components/esp_driver_ledc/src/ledc.c @@ -1117,7 +1117,7 @@ uint32_t ledc_get_freq(ledc_mode_t speed_mode, ledc_timer_t timer_num) ledc_hal_get_clock_divider(&(p_ledc_obj[speed_mode]->ledc_hal), timer_num, &clock_divider); ledc_hal_get_duty_resolution(&(p_ledc_obj[speed_mode]->ledc_hal), timer_num, &duty_resolution); ledc_hal_get_clk_cfg(&(p_ledc_obj[speed_mode]->ledc_hal), timer_num, &clk_cfg); - uint32_t precision = (0x1 << duty_resolution); + uint64_t precision = (0x1 << duty_resolution); uint32_t src_clk_freq = 0; esp_clk_tree_src_get_freq_hz((soc_module_clk_t)clk_cfg, LEDC_CLK_SRC_FREQ_PRECISION, &src_clk_freq); portEXIT_CRITICAL(&ledc_spinlock); From 9d41a098d70dd9b38b7a136ffb92bb815005670b Mon Sep 17 00:00:00 2001 From: Konstantin Kondrashov Date: Thu, 28 Nov 2024 15:47:18 +0200 Subject: [PATCH 013/118] fix(esp_system): Fix structurally dead code in esp_ipc.c ipc_task --- components/esp_system/esp_ipc.c | 6 ------ 1 file changed, 6 deletions(-) diff --git a/components/esp_system/esp_ipc.c b/components/esp_system/esp_ipc.c index 0cbcfc41d04..84d9e2195b3 100644 --- a/components/esp_system/esp_ipc.c +++ b/components/esp_system/esp_ipc.c @@ -89,12 +89,6 @@ static void IRAM_ATTR ipc_task(void* arg) } #endif // !CONFIG_FREERTOS_UNICORE } - // TODO: currently this is unreachable code. Introduce esp_ipc_uninit - // function which will signal to both tasks that they can shut down. - // Not critical at this point, we don't have a use case for stopping - // IPC yet. - // Also need to delete the semaphore here. - vTaskDelete(NULL); } /* From 5a245a389ba5eebf097ae874a84e65562e702845 Mon Sep 17 00:00:00 2001 From: Konstantin Kondrashov Date: Thu, 28 Nov 2024 16:39:48 +0200 Subject: [PATCH 014/118] fix(bootloader_support): Fix overflowed constant in bootloader_sha256_flash_contents --- .../bootloader_support/src/bootloader_utility.c | 11 ++++++++++- 1 file changed, 10 insertions(+), 1 deletion(-) diff --git a/components/bootloader_support/src/bootloader_utility.c b/components/bootloader_support/src/bootloader_utility.c index 9da668af3e5..11d57ee1f0c 100644 --- a/components/bootloader_support/src/bootloader_utility.c +++ b/components/bootloader_support/src/bootloader_utility.c @@ -1234,7 +1234,16 @@ esp_err_t bootloader_sha256_flash_contents(uint32_t flash_offset, uint32_t len, while (len > 0) { uint32_t mmu_page_offset = ((flash_offset & MMAP_ALIGNED_MASK) != 0) ? 1 : 0; /* Skip 1st MMU Page if it is already populated */ - uint32_t partial_image_len = MIN(len, ((mmu_free_pages_count - mmu_page_offset) * SPI_FLASH_MMU_PAGE_SIZE)); /* Read the image that fits in the free MMU pages */ + uint32_t max_pages = (mmu_free_pages_count > mmu_page_offset) ? (mmu_free_pages_count - mmu_page_offset) : 0; + if (max_pages == 0) { + ESP_LOGE(TAG, "No free MMU pages are available"); + return ESP_ERR_NO_MEM; + } + uint32_t max_image_len; + if (__builtin_mul_overflow(max_pages, SPI_FLASH_MMU_PAGE_SIZE, &max_image_len)) { + max_image_len = UINT32_MAX; + } + uint32_t partial_image_len = MIN(len, max_image_len); /* Read the image that fits in the free MMU pages */ const void * image = bootloader_mmap(flash_offset, partial_image_len); if (image == NULL) { From ad38ba16ddf6b9291953f95a87b55616eba8d50c Mon Sep 17 00:00:00 2001 From: Konstantin Kondrashov Date: Thu, 28 Nov 2024 16:51:00 +0200 Subject: [PATCH 015/118] fix(bootloader_support): Fix overflowed constant in process_segment --- components/bootloader_support/src/esp_image_format.c | 11 ++++++++++- 1 file changed, 10 insertions(+), 1 deletion(-) diff --git a/components/bootloader_support/src/esp_image_format.c b/components/bootloader_support/src/esp_image_format.c index bb57d9f698e..cd91876fb84 100644 --- a/components/bootloader_support/src/esp_image_format.c +++ b/components/bootloader_support/src/esp_image_format.c @@ -616,7 +616,16 @@ static esp_err_t process_segment(int index, uint32_t flash_addr, esp_image_segme #endif uint32_t offset_page = ((data_addr & MMAP_ALIGNED_MASK) != 0) ? 1 : 0; /* Data we could map in case we are not aligned to PAGE boundary is one page size lesser. */ - data_len = MIN(data_len_remain, ((free_page_count - offset_page) * SPI_FLASH_MMU_PAGE_SIZE)); + uint32_t max_pages = (free_page_count > offset_page) ? (free_page_count - offset_page) : 0; + if (max_pages == 0) { + ESP_LOGE(TAG, "No free MMU pages are available"); + return ESP_ERR_NO_MEM; + } + uint32_t max_image_len; + if (__builtin_mul_overflow(max_pages, SPI_FLASH_MMU_PAGE_SIZE, &max_image_len)) { + max_image_len = UINT32_MAX; + } + data_len = MIN(data_len_remain, max_image_len); CHECK_ERR(process_segment_data(index, load_addr, data_addr, data_len, do_load, sha_handle, checksum, metadata)); data_addr += data_len; data_len_remain -= data_len; From 1cd5736e759c688e6cc2aa8aaa9267a63a138606 Mon Sep 17 00:00:00 2001 From: Song Ruo Jing Date: Thu, 5 Dec 2024 15:10:54 +0800 Subject: [PATCH 016/118] refactor(ledc): deprecate ledc_timer_set API Closes https://github.com/espressif/esp-idf/issues/14884 --- components/esp_driver_ledc/include/driver/ledc.h | 10 ++++++++-- components/esp_driver_ledc/src/ledc.c | 12 +++++++++--- docs/en/api-reference/peripherals/ledc.rst | 7 +++---- docs/zh_CN/api-reference/peripherals/ledc.rst | 7 +++---- 4 files changed, 23 insertions(+), 13 deletions(-) diff --git a/components/esp_driver_ledc/include/driver/ledc.h b/components/esp_driver_ledc/include/driver/ledc.h index 4245ae83da0..1e209d5b2b5 100644 --- a/components/esp_driver_ledc/include/driver/ledc.h +++ b/components/esp_driver_ledc/include/driver/ledc.h @@ -350,7 +350,13 @@ esp_err_t ledc_set_fade(ledc_mode_t speed_mode, ledc_channel_t channel, uint32_t esp_err_t ledc_isr_register(void (*fn)(void *), void *arg, int intr_alloc_flags, ledc_isr_handle_t *handle); /** - * @brief Configure LEDC settings + * @brief Configure LEDC timer settings + * + * This function does not take care of whether the chosen clock source is enabled or not, also does not handle the clock source + * to meet channel sleep mode choice. + * + * If the chosen clock source is a new clock source to the LEDC timer, please use `ledc_timer_config`; + * If the clock source is kept to be the same, but frequency needs to be updated, please use `ledc_set_freq`. * * @param speed_mode Select the LEDC channel group with specified speed mode. Note that not all targets support high speed mode. * @param timer_sel Timer index (0-3), there are 4 timers in LEDC module @@ -362,7 +368,7 @@ esp_err_t ledc_isr_register(void (*fn)(void *), void *arg, int intr_alloc_flags, * - (-1) Parameter error * - Other Current LEDC duty */ -esp_err_t ledc_timer_set(ledc_mode_t speed_mode, ledc_timer_t timer_sel, uint32_t clock_divider, uint32_t duty_resolution, ledc_clk_src_t clk_src); +esp_err_t ledc_timer_set(ledc_mode_t speed_mode, ledc_timer_t timer_sel, uint32_t clock_divider, uint32_t duty_resolution, ledc_clk_src_t clk_src) __attribute__((deprecated("Please use ledc_timer_config() or ledc_set_freq()"))); /** * @brief Reset LEDC timer diff --git a/components/esp_driver_ledc/src/ledc.c b/components/esp_driver_ledc/src/ledc.c index be71b406382..fdc9a042efd 100644 --- a/components/esp_driver_ledc/src/ledc.c +++ b/components/esp_driver_ledc/src/ledc.c @@ -248,8 +248,7 @@ static uint32_t ledc_get_max_duty(ledc_mode_t speed_mode, ledc_channel_t channel return max_duty; } -esp_err_t ledc_timer_set(ledc_mode_t speed_mode, ledc_timer_t timer_sel, uint32_t clock_divider, uint32_t duty_resolution, - ledc_clk_src_t clk_src) +static esp_err_t ledc_set_timer_params(ledc_mode_t speed_mode, ledc_timer_t timer_sel, uint32_t clock_divider, uint32_t duty_resolution, ledc_clk_src_t clk_src) { LEDC_ARG_CHECK(speed_mode < LEDC_SPEED_MODE_MAX, "speed_mode"); LEDC_ARG_CHECK(timer_sel < LEDC_TIMER_MAX, "timer_select"); @@ -268,6 +267,13 @@ esp_err_t ledc_timer_set(ledc_mode_t speed_mode, ledc_timer_t timer_sel, uint32_ return ESP_OK; } +// Deprecated public API +esp_err_t ledc_timer_set(ledc_mode_t speed_mode, ledc_timer_t timer_sel, uint32_t clock_divider, uint32_t duty_resolution, + ledc_clk_src_t clk_src) +{ + return ledc_set_timer_params(speed_mode, timer_sel, clock_divider, duty_resolution, clk_src); +} + static IRAM_ATTR esp_err_t ledc_duty_config(ledc_mode_t speed_mode, ledc_channel_t channel, int hpoint_val, int duty_val, ledc_duty_direction_t duty_direction, uint32_t duty_num, uint32_t duty_cycle, uint32_t duty_scale) { @@ -711,7 +717,7 @@ static esp_err_t ledc_set_timer_div(ledc_mode_t speed_mode, ledc_timer_t timer_n } /* The divisor is correct, we can write in the hardware. */ - ledc_timer_set(speed_mode, timer_num, div_param, duty_resolution, timer_clk_src); + ledc_set_timer_params(speed_mode, timer_num, div_param, duty_resolution, timer_clk_src); portENTER_CRITICAL(&ledc_spinlock); if (p_ledc_obj[speed_mode]->timer_xpd_ref_cnt[timer_num] > 0 && !p_ledc_obj[speed_mode]->glb_clk_xpd) { diff --git a/docs/en/api-reference/peripherals/ledc.rst b/docs/en/api-reference/peripherals/ledc.rst index 8005b6b5582..317ce17b702 100644 --- a/docs/en/api-reference/peripherals/ledc.rst +++ b/docs/en/api-reference/peripherals/ledc.rst @@ -319,14 +319,13 @@ The LEDC API provides several ways to change the PWM frequency "on the fly": More Control Over PWM """"""""""""""""""""" -There are several lower level timer-specific functions that can be used to change PWM settings: +There are several individual timer-specific functions that can be used to change PWM output: -* :cpp:func:`ledc_timer_set` * :cpp:func:`ledc_timer_rst` * :cpp:func:`ledc_timer_pause` * :cpp:func:`ledc_timer_resume` -The first two functions are called "behind the scenes" by :cpp:func:`ledc_channel_config` to provide a startup of a timer after it is configured. +The first function is called "behind the scenes" by :cpp:func:`ledc_timer_config` to provide a startup of a timer after it is configured. Use Interrupts @@ -356,7 +355,7 @@ If signal output needs to be maintained in Light-sleep, then select :cpp:enumera LEDC High and Low Speed Mode ---------------------------- - High speed mode enables a glitch-free changeover of timer settings. This means that if the timer settings are modified, the changes will be applied automatically on the next overflow interrupt of the timer. In contrast, when updating the low-speed timer, the change of settings should be explicitly triggered by software. The LEDC driver handles it in the background, e.g., when :cpp:func:`ledc_timer_config` or :cpp:func:`ledc_timer_set` is called. + High speed mode enables a glitch-free changeover of timer settings. This means that if the timer settings are modified, the changes will be applied automatically on the next overflow interrupt of the timer. In contrast, when updating the low-speed timer, the change of settings should be explicitly triggered by software. The LEDC driver handles it in the background, e.g., when :cpp:func:`ledc_timer_config` is called. For additional details regarding speed modes, see **{IDF_TARGET_NAME} Technical Reference Manual** > **LED PWM Controller (LEDC)** [`PDF <{IDF_TARGET_TRM_EN_URL}#ledpwm>`__]. diff --git a/docs/zh_CN/api-reference/peripherals/ledc.rst b/docs/zh_CN/api-reference/peripherals/ledc.rst index 51ce5785ecc..3137f3c4f17 100644 --- a/docs/zh_CN/api-reference/peripherals/ledc.rst +++ b/docs/zh_CN/api-reference/peripherals/ledc.rst @@ -319,14 +319,13 @@ LED PWM 控制器 API 有多种方式即时改变 PWM 频率： 控制 PWM 的更多方式 """"""""""""""""""""" -有一些较底层的定时器特定函数可用于更改 PWM 设置： +有一些较独立的定时器特定函数可用于更改 PWM 输出： -* :cpp:func:`ledc_timer_set` * :cpp:func:`ledc_timer_rst` * :cpp:func:`ledc_timer_pause` * :cpp:func:`ledc_timer_resume` -前两个功能可通过函数 :cpp:func:`ledc_channel_config` 在后台运行，在定时器配置后启动。 +第一个定时器复位函数在函数 :cpp:func:`ledc_timer_config` 内部完成所有定时器配置后会被调用一次。 使用中断 @@ -356,7 +355,7 @@ LEDC 驱动不使用电源管理锁来防止系统进入 Light-sleep 。相反 LED PWM 控制器高速和低速模式 ---------------------------------- - 高速模式的优点是可平稳地改变定时器设置。也就是说，高速模式下如定时器设置改变，此变更会自动应用于定时器的下一次溢出中断。而更新低速定时器时，设置变更应由软件显式触发。LED PWM 驱动的设置将在硬件层面被修改，比如在调用函数 :cpp:func:`ledc_timer_config` 或 :cpp:func:`ledc_timer_set` 时。 + 高速模式的优点是可平稳地改变定时器设置。也就是说，高速模式下如定时器设置改变，此变更会自动应用于定时器的下一次溢出中断。而更新低速定时器时，设置变更应由软件显式触发。LED PWM 驱动的设置将在硬件层面被修改，比如在调用函数 :cpp:func:`ledc_timer_config` 时。 更多关于速度模式的详细信息请参阅 **{IDF_TARGET_NAME} 技术参考手册** > **LED PWM 控制器 (LEDC)** [`PDF <{IDF_TARGET_TRM_EN_URL}#ledpwm>`__]。 From 54d3c090beeb452654dc54d839b1d6d3819eb966 Mon Sep 17 00:00:00 2001 From: Peter Dragun Date: Fri, 6 Dec 2024 09:21:07 +0100 Subject: [PATCH 017/118] fix(tools): fix running monitor without elf file --- tools/idf_py_actions/serial_ext.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/tools/idf_py_actions/serial_ext.py b/tools/idf_py_actions/serial_ext.py index bb9ca60be26..8e41153fa0c 100644 --- a/tools/idf_py_actions/serial_ext.py +++ b/tools/idf_py_actions/serial_ext.py @@ -172,7 +172,7 @@ def monitor( monitor_args += ['--print_filter', print_filter] elf_list = [str(elf) for elf in Path(args.build_dir).rglob('*.elf')] - if elf_file: + if elf_file and elf_file in elf_list: # prepend the main app elf file to the list; make sure it is the first one elf_list.insert(0, elf_list.pop(elf_list.index(elf_file))) monitor_args.extend(elf_list) From 251dbf44470bf11c378d392e35d95d54514ccade Mon Sep 17 00:00:00 2001 From: Rahul Tank Date: Fri, 6 Dec 2024 10:54:11 +0530 Subject: [PATCH 018/118] fix(nimble): Fixes for security vulnerabilities reported in NimBLE --- components/bt/host/nimble/nimble | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/components/bt/host/nimble/nimble b/components/bt/host/nimble/nimble index 46f1139a055..c58a8e7edfd 160000 --- a/components/bt/host/nimble/nimble +++ b/components/bt/host/nimble/nimble @@ -1 +1 @@ -Subproject commit 46f1139a055246d05c0744c2195c5f82155b5e6d +Subproject commit c58a8e7edfdad6e6b4e7742ef2aa3a07488b815e From 9fcc1c35da7870fe4dbb5b683668aae51b13d102 Mon Sep 17 00:00:00 2001 From: gaoxu Date: Sun, 8 Dec 2024 16:37:38 +0800 Subject: [PATCH 019/118] feat(esp32h21): add soc register header files (stage2, 2/3) --- .../soc/esp32h21/include/soc/gpio_sig_map.h | 262 +++++++++ .../soc/esp32h21/include/soc/interrupts.h | 91 ++++ .../esp32h21/include/soc/pmu_icg_mapping.h | 66 +++ .../soc/esp32h21/include/soc/soc_etm_source.h | 338 ++++++++++++ components/soc/esp32h21/interrupts.c | 75 +++ .../soc/esp32h21/ld/esp32h21.peripherals.ld | 57 ++ .../register/soc/lp_analog_peri_reg.h | 469 ++++++++++++++++ .../register/soc/lp_analog_peri_struct.h | 420 +++++++++++++++ .../soc/esp32h21/register/soc/lp_aon_reg.h | 470 ++++++++++++++++ .../soc/esp32h21/register/soc/lp_aon_struct.h | 487 +++++++++++++++++ .../soc/esp32h21/register/soc/lp_apm0_reg.h | 506 ++++++++++++++++++ .../esp32h21/register/soc/lp_apm0_struct.h | 499 +++++++++++++++++ .../soc/esp32h21/register/soc/lp_apm_reg.h | 322 +++++++++++ .../soc/esp32h21/register/soc/lp_apm_struct.h | 346 ++++++++++++ .../soc/esp32h21/register/soc/lp_clkrst_reg.h | 431 +++++++++++++++ .../esp32h21/register/soc/lp_clkrst_struct.h | 369 +++++++++++++ .../soc/esp32h21/register/soc/lp_peri_reg.h | 388 ++++++++++++++ .../esp32h21/register/soc/lp_peri_struct.h | 352 ++++++++++++ .../soc/esp32h21/register/soc/lp_wdt_reg.h | 350 ++++++++++++ .../soc/esp32h21/register/soc/lp_wdt_struct.h | 333 ++++++++++++ .../soc/esp32h21/register/soc/reg_base.h | 59 ++ 21 files changed, 6690 insertions(+) create mode 100644 components/soc/esp32h21/include/soc/gpio_sig_map.h create mode 100644 components/soc/esp32h21/include/soc/interrupts.h create mode 100644 components/soc/esp32h21/include/soc/pmu_icg_mapping.h create mode 100644 components/soc/esp32h21/include/soc/soc_etm_source.h create mode 100644 components/soc/esp32h21/ld/esp32h21.peripherals.ld create mode 100644 components/soc/esp32h21/register/soc/lp_analog_peri_reg.h create mode 100644 components/soc/esp32h21/register/soc/lp_analog_peri_struct.h create mode 100644 components/soc/esp32h21/register/soc/lp_aon_reg.h create mode 100644 components/soc/esp32h21/register/soc/lp_aon_struct.h create mode 100644 components/soc/esp32h21/register/soc/lp_apm0_reg.h create mode 100644 components/soc/esp32h21/register/soc/lp_apm0_struct.h create mode 100644 components/soc/esp32h21/register/soc/lp_apm_reg.h create mode 100644 components/soc/esp32h21/register/soc/lp_apm_struct.h create mode 100644 components/soc/esp32h21/register/soc/lp_clkrst_reg.h create mode 100644 components/soc/esp32h21/register/soc/lp_clkrst_struct.h create mode 100644 components/soc/esp32h21/register/soc/lp_peri_reg.h create mode 100644 components/soc/esp32h21/register/soc/lp_peri_struct.h create mode 100644 components/soc/esp32h21/register/soc/lp_wdt_reg.h create mode 100644 components/soc/esp32h21/register/soc/lp_wdt_struct.h create mode 100644 components/soc/esp32h21/register/soc/reg_base.h diff --git a/components/soc/esp32h21/include/soc/gpio_sig_map.h b/components/soc/esp32h21/include/soc/gpio_sig_map.h new file mode 100644 index 00000000000..e6e4080df82 --- /dev/null +++ b/components/soc/esp32h21/include/soc/gpio_sig_map.h @@ -0,0 +1,262 @@ +/* + * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#pragma once + +#define EXT_ADC_START_IDX 0 +#define LEDC_LS_SIG_OUT0_IDX 0 +#define LEDC_LS_SIG_OUT1_IDX 1 +#define LEDC_LS_SIG_OUT2_IDX 2 +#define LEDC_LS_SIG_OUT3_IDX 3 +#define LEDC_LS_SIG_OUT4_IDX 4 +#define LEDC_LS_SIG_OUT5_IDX 5 +#define U0RXD_IN_IDX 6 +#define U0TXD_OUT_IDX 6 +#define U0CTS_IN_IDX 7 +#define U0RTS_OUT_IDX 7 +#define U0DSR_IN_IDX 8 +#define U0DTR_OUT_IDX 8 +#define U1RXD_IN_IDX 9 +#define U1TXD_OUT_IDX 9 +#define U1CTS_IN_IDX 10 +#define U1RTS_OUT_IDX 10 +#define U1DSR_IN_IDX 11 +#define U1DTR_OUT_IDX 11 +#define I2S_MCLK_IN_IDX 12 +#define I2S_MCLK_OUT_IDX 12 +#define I2SO_BCK_IN_IDX 13 +#define I2SO_BCK_OUT_IDX 13 +#define I2SO_WS_IN_IDX 14 +#define I2SO_WS_OUT_IDX 14 +#define I2SI_SD_IN_IDX 15 +#define I2SO_SD_OUT_IDX 15 +#define I2SI_BCK_IN_IDX 16 +#define I2SI_BCK_OUT_IDX 16 +#define I2SI_WS_IN_IDX 17 +#define I2SI_WS_OUT_IDX 17 +#define I2SO_SD1_OUT_IDX 18 +#define USB_JTAG_TDO_BRIDGE_IDX 19 +#define USB_JTAG_TRST_IDX 19 +#define CPU_TESTBUS0_IDX 20 +#define CPU_TESTBUS1_IDX 21 +#define CPU_TESTBUS2_IDX 22 +#define CPU_TESTBUS3_IDX 23 +#define CPU_TESTBUS4_IDX 24 +#define CPU_TESTBUS5_IDX 25 +#define CPU_TESTBUS6_IDX 26 +#define CPU_TESTBUS7_IDX 27 +#define CPU_GPIO_IN0_IDX 28 +#define CPU_GPIO_OUT0_IDX 28 +#define CPU_GPIO_IN1_IDX 29 +#define CPU_GPIO_OUT1_IDX 29 +#define CPU_GPIO_IN2_IDX 30 +#define CPU_GPIO_OUT2_IDX 30 +#define CPU_GPIO_IN3_IDX 31 +#define CPU_GPIO_OUT3_IDX 31 +#define CPU_GPIO_IN4_IDX 32 +#define CPU_GPIO_OUT4_IDX 32 +#define CPU_GPIO_IN5_IDX 33 +#define CPU_GPIO_OUT5_IDX 33 +#define CPU_GPIO_IN6_IDX 34 +#define CPU_GPIO_OUT6_IDX 34 +#define CPU_GPIO_IN7_IDX 35 +#define CPU_GPIO_OUT7_IDX 35 +#define USB_JTAG_TCK_IDX 36 +#define USB_JTAG_TMS_IDX 37 +#define USB_JTAG_TDI_IDX 38 +#define USB_JTAG_TDO_IDX 39 +#define USB_EXTPHY_VP_IDX 40 +#define USB_EXTPHY_OEN_IDX 40 +#define USB_EXTPHY_VM_IDX 41 +#define USB_EXTPHY_SPEED_IDX 41 +#define USB_EXTPHY_RCV_IDX 42 +#define USB_EXTPHY_VPO_IDX 42 +#define USB_EXTPHY_VMO_IDX 43 +#define USB_EXTPHY_SUSPND_IDX 44 +#define I2CEXT0_SCL_IN_IDX 45 +#define I2CEXT0_SCL_OUT_IDX 45 +#define I2CEXT0_SDA_IN_IDX 46 +#define I2CEXT0_SDA_OUT_IDX 46 +#define PARL_RX_DATA0_IDX 47 +#define PARL_TX_DATA0_IDX 47 +#define PARL_RX_DATA1_IDX 48 +#define PARL_TX_DATA1_IDX 48 +#define PARL_RX_DATA2_IDX 49 +#define PARL_TX_DATA2_IDX 49 +#define PARL_RX_DATA3_IDX 50 +#define PARL_TX_DATA3_IDX 50 +#define PARL_RX_DATA4_IDX 51 +#define PARL_TX_DATA4_IDX 51 +#define PARL_RX_DATA5_IDX 52 +#define PARL_TX_DATA5_IDX 52 +#define PARL_RX_DATA6_IDX 53 +#define PARL_TX_DATA6_IDX 53 +#define PARL_RX_DATA7_IDX 54 +#define PARL_TX_DATA7_IDX 54 +#define I2CEXT1_SCL_IN_IDX 55 +#define I2CEXT1_SCL_OUT_IDX 55 +#define I2CEXT1_SDA_IN_IDX 56 +#define I2CEXT1_SDA_OUT_IDX 56 +#define CTE_ANT0_IDX 57 +#define CTE_ANT1_IDX 58 +#define CTE_ANT2_IDX 59 +#define CTE_ANT3_IDX 60 +#define CTE_ANT4_IDX 61 +#define CTE_ANT5_IDX 62 +#define FSPICLK_IN_IDX 63 +#define FSPICLK_OUT_IDX 63 +#define FSPIQ_IN_IDX 64 +#define FSPIQ_OUT_IDX 64 +#define FSPID_IN_IDX 65 +#define FSPID_OUT_IDX 65 +#define FSPIHD_IN_IDX 66 +#define FSPIHD_OUT_IDX 66 +#define FSPIWP_IN_IDX 67 +#define FSPIWP_OUT_IDX 67 +#define FSPICS0_IN_IDX 68 +#define FSPICS0_OUT_IDX 68 +#define PARL_RX_CLK_IN_IDX 69 +#define PARL_RX_CLK_OUT_IDX 69 +#define PARL_TX_CLK_IN_IDX 70 +#define PARL_TX_CLK_OUT_IDX 70 +#define RMT_SIG_IN0_IDX 71 +#define RMT_SIG_OUT0_IDX 71 +#define RMT_SIG_IN1_IDX 72 +#define RMT_SIG_OUT1_IDX 72 +#define TWAI0_RX_IDX 73 +#define TWAI0_TX_IDX 73 +#define TWAI0_BUS_OFF_ON_IDX 74 +#define TWAI0_CLKOUT_IDX 75 +#define TWAI0_STANDBY_IDX 76 +#define PCNT_RST_IN0_IDX 77 +#define CTE_ANT6_IDX 77 +#define PCNT_RST_IN1_IDX 78 +#define CTE_ANT7_IDX 78 +#define PCNT_RST_IN2_IDX 79 +#define CTE_ANT8_IDX 79 +#define PCNT_RST_IN3_IDX 80 +#define CTE_ANT9_IDX 80 +#define EXTERN_PRIORITY_I_IDX 81 +#define EXTERN_PRIORITY_O_IDX 81 +#define EXTERN_ACTIVE_I_IDX 82 +#define EXTERN_ACTIVE_O_IDX 82 +#define GPIO_SD0_OUT_IDX 83 +#define GPIO_SD1_OUT_IDX 84 +#define GPIO_SD2_OUT_IDX 85 +#define GPIO_SD3_OUT_IDX 86 +#define PWM0_SYNC0_IN_IDX 87 +#define PWM0_OUT0A_IDX 87 +#define PWM0_SYNC1_IN_IDX 88 +#define PWM0_OUT0B_IDX 88 +#define PWM0_SYNC2_IN_IDX 89 +#define PWM0_OUT1A_IDX 89 +#define PWM0_F0_IN_IDX 90 +#define PWM0_OUT1B_IDX 90 +#define PWM0_F1_IN_IDX 91 +#define PWM0_OUT2A_IDX 91 +#define PWM0_F2_IN_IDX 92 +#define PWM0_OUT2B_IDX 92 +#define PWM0_CAP0_IN_IDX 93 +#define ANT_SEL0_IDX 93 +#define PWM0_CAP1_IN_IDX 94 +#define ANT_SEL1_IDX 94 +#define PWM0_CAP2_IN_IDX 95 +#define ANT_SEL2_IDX 95 +#define ANT_SEL3_IDX 96 +#define SIG_IN_FUNC_97_IDX 97 +#define SIG_IN_FUNC97_IDX 97 +#define SIG_IN_FUNC_98_IDX 98 +#define SIG_IN_FUNC98_IDX 98 +#define SIG_IN_FUNC_99_IDX 99 +#define SIG_IN_FUNC99_IDX 99 +#define SIG_IN_FUNC_100_IDX 100 +#define SIG_IN_FUNC100_IDX 100 +#define PCNT_SIG_CH0_IN0_IDX 101 +#define FSPICS1_OUT_IDX 101 +#define PCNT_SIG_CH1_IN0_IDX 102 +#define FSPICS2_OUT_IDX 102 +#define PCNT_CTRL_CH0_IN0_IDX 103 +#define FSPICS3_OUT_IDX 103 +#define PCNT_CTRL_CH1_IN0_IDX 104 +#define FSPICS4_OUT_IDX 104 +#define PCNT_SIG_CH0_IN1_IDX 105 +#define FSPICS5_OUT_IDX 105 +#define PCNT_SIG_CH1_IN1_IDX 106 +#define CTE_ANT10_IDX 106 +#define PCNT_CTRL_CH0_IN1_IDX 107 +#define CTE_ANT11_IDX 107 +#define PCNT_CTRL_CH1_IN1_IDX 108 +#define CTE_ANT12_IDX 108 +#define PCNT_SIG_CH0_IN2_IDX 109 +#define CTE_ANT13_IDX 109 +#define PCNT_SIG_CH1_IN2_IDX 110 +#define CTE_ANT14_IDX 110 +#define PCNT_CTRL_CH0_IN2_IDX 111 +#define CTE_ANT15_IDX 111 +#define PCNT_CTRL_CH1_IN2_IDX 112 +#define USB_JTAG_SRST_IDX 112 +#define PCNT_SIG_CH0_IN3_IDX 113 +#define PCNT_SIG_CH1_IN3_IDX 114 +#define SPICLK_OUT_IDX 114 +#define PCNT_CTRL_CH0_IN3_IDX 115 +#define SPICS0_OUT_IDX 115 +#define PCNT_CTRL_CH1_IN3_IDX 116 +#define SPICS1_OUT_IDX 116 +#define GPIO_EVENT_MATRIX_IN0_IDX 117 +#define GPIO_TASK_MATRIX_OUT0_IDX 117 +#define GPIO_EVENT_MATRIX_IN1_IDX 118 +#define GPIO_TASK_MATRIX_OUT1_IDX 118 +#define GPIO_EVENT_MATRIX_IN2_IDX 119 +#define GPIO_TASK_MATRIX_OUT2_IDX 119 +#define GPIO_EVENT_MATRIX_IN3_IDX 120 +#define GPIO_TASK_MATRIX_OUT3_IDX 120 +#define SPIQ_IN_IDX 121 +#define SPIQ_OUT_IDX 121 +#define SPID_IN_IDX 122 +#define SPID_OUT_IDX 122 +#define SPIHD_IN_IDX 123 +#define SPIHD_OUT_IDX 123 +#define SPIWP_IN_IDX 124 +#define SPIWP_OUT_IDX 124 +#define CLK_OUT_OUT1_IDX 125 +#define CLK_OUT_OUT2_IDX 126 +#define CLK_OUT_OUT3_IDX 127 +#define MODEM_DIAG0_IDX 128 +#define MODEM_DIAG1_IDX 129 +#define MODEM_DIAG2_IDX 130 +#define MODEM_DIAG3_IDX 131 +#define MODEM_DIAG4_IDX 132 +#define MODEM_DIAG5_IDX 133 +#define MODEM_DIAG6_IDX 134 +#define MODEM_DIAG7_IDX 135 +#define MODEM_DIAG8_IDX 136 +#define MODEM_DIAG9_IDX 137 +#define MODEM_DIAG10_IDX 138 +#define MODEM_DIAG11_IDX 139 +#define MODEM_DIAG12_IDX 140 +#define MODEM_DIAG13_IDX 141 +#define MODEM_DIAG14_IDX 142 +#define MODEM_DIAG15_IDX 143 +#define MODEM_DIAG16_IDX 144 +#define MODEM_DIAG17_IDX 145 +#define MODEM_DIAG18_IDX 146 +#define MODEM_DIAG19_IDX 147 +#define MODEM_DIAG20_IDX 148 +#define MODEM_DIAG21_IDX 149 +#define MODEM_DIAG22_IDX 150 +#define MODEM_DIAG23_IDX 151 +#define MODEM_DIAG24_IDX 152 +#define MODEM_DIAG25_IDX 153 +#define MODEM_DIAG26_IDX 154 +#define MODEM_DIAG27_IDX 155 +#define MODEM_DIAG28_IDX 156 +#define MODEM_DIAG29_IDX 157 +#define MODEM_DIAG30_IDX 158 +#define MODEM_DIAG31_IDX 159 +#define COEX_PA_PWR_SWITCH_PIN0_IDX 160 +#define COEX_PA_PWR_SWITCH_PIN1_IDX 161 +// version date 2409110 +#define SIG_GPIO_OUT_IDX 256 diff --git a/components/soc/esp32h21/include/soc/interrupts.h b/components/soc/esp32h21/include/soc/interrupts.h new file mode 100644 index 00000000000..9f28a1ab24e --- /dev/null +++ b/components/soc/esp32h21/include/soc/interrupts.h @@ -0,0 +1,91 @@ +/* + * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#pragma once + +#include + +#ifdef __cplusplus +extern "C" +{ +#endif + +//Interrupt hardware source table +//This table is decided by hardware, don't touch this. +typedef enum { + ETS_PMU_INTR_SOURCE, + ETS_EFUSE_INTR_SOURCE, + ETS_LP_RTC_TIMER_INTR_SOURCE, + ETS_LP_BLE_TIMER_INTR_SOURCE, + ETS_LP_WDT_INTR_SOURCE, + ETS_LP_PERI_TIMEOUT_INTR_SOURCE, + ETS_LP_APM_M0_INTR_SOURCE, + ETS_CPU_INTR_FROM_CPU_0_SOURCE, + ETS_CPU_INTR_FROM_CPU_1_SOURCE, + ETS_CPU_INTR_FROM_CPU_2_SOURCE, + ETS_CPU_INTR_FROM_CPU_3_SOURCE, + ETS_ASSIST_DEBUG_INTR_SOURCE, + ETS_TRACE_INTR_SOURCE, + ETS_CACHE_INTR_SOURCE, + ETS_CPU_PERI_TIMEOUT_INTR_SOURCE, + ETS_BT_MAC_INTR_SOURCE, + ETS_BT_BB_INTR_SOURCE, + ETS_BT_BB_NMI_SOURCE, + ETS_COEX_INTR_SOURCE, + ETS_BLE_TIMER_INTR_SOURCE, + ETS_BLE_SEC_INTR_SOURCE, + ETS_ZB_MAC_INTR_SOURCE, + ETS_GPIO_INTERRUPT_PRO_SOURCE, + ETS_GPIO_INTERRUPT_PRO_NMI_SOURCE, + ETS_PAU_INTR_SOURCE, + ETS_HP_PERI_TIMEOUT_INTR_SOURCE, + ETS_HP_APM_M0_INTR_SOURCE, + ETS_HP_APM_M1_INTR_SOURCE, + ETS_HP_APM_M2_INTR_SOURCE, + ETS_HP_APM_M3_INTR_SOURCE, + ETS_MSPI_INTR_SOURCE, + ETS_I2S1_INTR_SOURCE, + ETS_UHCI0_INTR_SOURCE, + ETS_UART0_INTR_SOURCE, + ETS_UART1_INTR_SOURCE, + ETS_LEDC_INTR_SOURCE, + ETS_TWAI0_INTR_SOURCE, + ETS_USB_INTR_SOURCE, + ETS_RMT_INTR_SOURCE, + ETS_I2C_EXT0_INTR_SOURCE, + ETS_I2C_EXT1_INTR_SOURCE, + ETS_TG0_T0_INTR_SOURCE, + ETS_TG0_WDT_INTR_SOURCE, + ETS_TG1_T0_INTR_SOURCE, + ETS_TG1_WDT_INTR_SOURCE, + ETS_SYSTIMER_TARGET0_INTR_SOURCE, + ETS_SYSTIMER_TARGET1_INTR_SOURCE, + ETS_SYSTIMER_TARGET2_INTR_SOURCE, + ETS_APB_ADC_INTR_SOURCE, + ETS_PWM_INTR_SOURCE, + ETS_PCNT_INTR_SOURCE, + ETS_PARL_IO_TX_INTR_SOURCE, + ETS_PARL_IO_RX_INTR_SOURCE, + ETS_DMA_IN_CH0_INTR_SOURCE, + ETS_DMA_IN_CH1_INTR_SOURCE, + ETS_DMA_IN_CH2_INTR_SOURCE, + ETS_DMA_OUT_CH0_INTR_SOURCE, + ETS_DMA_OUT_CH1_INTR_SOURCE, + ETS_DMA_OUT_CH2_INTR_SOURCE, + ETS_GPSPI2_INTR_SOURCE, + ETS_AES_INTR_SOURCE, + ETS_SHA_INTR_SOURCE, + ETS_RSA_INTR_SOURCE, + ETS_ECC_INTR_SOURCE, + ETS_ECDSA_INTR_SOURCE, + ETS_MAX_INTR_SOURCE, +} periph_interrput_t; + +extern const char * const esp_isr_names[ETS_MAX_INTR_SOURCE]; + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32h21/include/soc/pmu_icg_mapping.h b/components/soc/esp32h21/include/soc/pmu_icg_mapping.h new file mode 100644 index 00000000000..972e2d6d097 --- /dev/null +++ b/components/soc/esp32h21/include/soc/pmu_icg_mapping.h @@ -0,0 +1,66 @@ +/* + * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#pragma once + +#define PMU_ICG_APB_ENA_SEC 0 +#define PMU_ICG_APB_ENA_GDMA 1 +#define PMU_ICG_APB_ENA_SPI2 2 +#define PMU_ICG_APB_ENA_INTMTX 3 +#define PMU_ICG_APB_ENA_I2S 4 +#define PMU_ICG_APB_ENA_MSPI 5 +#define PMU_ICG_APB_ENA_UART0 6 +#define PMU_ICG_APB_ENA_UART1 7 +#define PMU_ICG_APB_ENA_UHCI 8 +#define PMU_ICG_APB_ENA_SARADC 9 +#define PMU_ICG_APB_ENA_TG0 11 +#define PMU_ICG_APB_ENA_TG1 12 +#define PMU_ICG_APB_ENA_I2C0 13 +#define PMU_ICG_APB_ENA_I2C1 13 +#define PMU_ICG_APB_ENA_LEDC 14 +#define PMU_ICG_APB_ENA_RMT 15 +#define PMU_ICG_APB_ENA_SYSTIMER 16 +#define PMU_ICG_APB_ENA_USB_DEVICE 17 +#define PMU_ICG_APB_ENA_TWAI0 18 +#define PMU_ICG_APB_ENA_PCNT 20 +#define PMU_ICG_APB_ENA_PWM 21 +#define PMU_ICG_APB_ENA_SOC_ETM 22 +#define PMU_ICG_APB_ENA_PARL 23 +#define PMU_ICG_APB_ENA_REGDMA 24 +#define PMU_ICG_APB_ENA_MEM_MONITOR 25 +#define PMU_ICG_APB_ENA_IOMUX 26 +#define PMU_ICG_APB_ENA_PVT_MONITOR 27 +#define PMU_ICG_FUNC_ENA_GDMA 0 +#define PMU_ICG_FUNC_ENA_SPI2 1 +#define PMU_ICG_FUNC_ENA_I2S_RX 2 +#define PMU_ICG_FUNC_ENA_UART0 3 +#define PMU_ICG_FUNC_ENA_UART1 4 +#define PMU_ICG_FUNC_ENA_UHCI 5 +#define PMU_ICG_FUNC_ENA_USB_DEVICE 6 +#define PMU_ICG_FUNC_ENA_I2S_TX 7 +#define PMU_ICG_FUNC_ENA_REGDMA 8 +#define PMU_ICG_FUNC_ENA_MEM_MONITOR 10 +#define PMU_ICG_FUNC_ENA_TSENS 12 +#define PMU_ICG_FUNC_ENA_TG1 13 +#define PMU_ICG_FUNC_ENA_TG0 14 +#define PMU_ICG_FUNC_ENA_HPBUS 15 +#define PMU_ICG_FUNC_ENA_HPMEM 15 +#define PMU_ICG_FUNC_ENA_SOC_ETM 16 +#define PMU_ICG_FUNC_ENA_HPCORE 17 +#define PMU_ICG_FUNC_ENA_SYSTIMER 18 +#define PMU_ICG_FUNC_ENA_SEC 19 +#define PMU_ICG_FUNC_ENA_SARADC 20 +#define PMU_ICG_FUNC_ENA_RMT 21 +#define PMU_ICG_FUNC_ENA_PWM 22 +#define PMU_ICG_FUNC_ENA_PVT_MONITOR 23 +#define PMU_ICG_FUNC_ENA_PARL_TX 24 +#define PMU_ICG_FUNC_ENA_PARL_RX 25 +#define PMU_ICG_FUNC_ENA_MSPI 26 +#define PMU_ICG_FUNC_ENA_LEDC 27 +#define PMU_ICG_FUNC_ENA_IOMUX 28 +#define PMU_ICG_FUNC_ENA_I2C0 29 +#define PMU_ICG_FUNC_ENA_I2C1 29 +#define PMU_ICG_FUNC_ENA_TWAI0 31 diff --git a/components/soc/esp32h21/include/soc/soc_etm_source.h b/components/soc/esp32h21/include/soc/soc_etm_source.h new file mode 100644 index 00000000000..3c75bcff212 --- /dev/null +++ b/components/soc/esp32h21/include/soc/soc_etm_source.h @@ -0,0 +1,338 @@ +/* + * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#pragma once + +#define GPIO_EVT_CH0_RISE_EDGE 1 +#define GPIO_EVT_CH1_RISE_EDGE 2 +#define GPIO_EVT_CH2_RISE_EDGE 3 +#define GPIO_EVT_CH3_RISE_EDGE 4 +#define GPIO_EVT_CH4_RISE_EDGE 5 +#define GPIO_EVT_CH5_RISE_EDGE 6 +#define GPIO_EVT_CH6_RISE_EDGE 7 +#define GPIO_EVT_CH7_RISE_EDGE 8 +#define GPIO_EVT_CH0_FALL_EDGE 9 +#define GPIO_EVT_CH1_FALL_EDGE 10 +#define GPIO_EVT_CH2_FALL_EDGE 11 +#define GPIO_EVT_CH3_FALL_EDGE 12 +#define GPIO_EVT_CH4_FALL_EDGE 13 +#define GPIO_EVT_CH5_FALL_EDGE 14 +#define GPIO_EVT_CH6_FALL_EDGE 15 +#define GPIO_EVT_CH7_FALL_EDGE 16 +#define GPIO_EVT_CH0_ANY_EDGE 17 +#define GPIO_EVT_CH1_ANY_EDGE 18 +#define GPIO_EVT_CH2_ANY_EDGE 19 +#define GPIO_EVT_CH3_ANY_EDGE 20 +#define GPIO_EVT_CH4_ANY_EDGE 21 +#define GPIO_EVT_CH5_ANY_EDGE 22 +#define GPIO_EVT_CH6_ANY_EDGE 23 +#define GPIO_EVT_CH7_ANY_EDGE 24 +#define LEDC_EVT_DUTY_CHNG_END_CH0 25 +#define LEDC_EVT_DUTY_CHNG_END_CH1 26 +#define LEDC_EVT_DUTY_CHNG_END_CH2 27 +#define LEDC_EVT_DUTY_CHNG_END_CH3 28 +#define LEDC_EVT_DUTY_CHNG_END_CH4 29 +#define LEDC_EVT_DUTY_CHNG_END_CH5 30 +#define LEDC_EVT_OVF_CNT_PLS_CH0 31 +#define LEDC_EVT_OVF_CNT_PLS_CH1 32 +#define LEDC_EVT_OVF_CNT_PLS_CH2 33 +#define LEDC_EVT_OVF_CNT_PLS_CH3 34 +#define LEDC_EVT_OVF_CNT_PLS_CH4 35 +#define LEDC_EVT_OVF_CNT_PLS_CH5 36 +#define LEDC_EVT_TIME_OVF_TIMER0 37 +#define LEDC_EVT_TIME_OVF_TIMER1 38 +#define LEDC_EVT_TIME_OVF_TIMER2 39 +#define LEDC_EVT_TIME_OVF_TIMER3 40 +#define LEDC_EVT_TIMER0_CMP 41 +#define LEDC_EVT_TIMER1_CMP 42 +#define LEDC_EVT_TIMER2_CMP 43 +#define LEDC_EVT_TIMER3_CMP 44 +#define PCNT_EVT_CNT_EQ_THRESH 45 +#define PCNT_EVT_CNT_EQ_LMT 46 +#define PCNT_EVT_CNT_EQ_ZERO 47 +#define TIMER0_EVT_CNT_CMP_TIMER0 48 +#define TIMER1_EVT_CNT_CMP_TIMER0 49 +#define SYSTIMER_EVT_CNT_CMP0 50 +#define SYSTIMER_EVT_CNT_CMP1 51 +#define SYSTIMER_EVT_CNT_CMP2 52 +#define RMT_EVT_TX_END 53 +#define RMT_EVT_TX_LOOP 54 +#define RMT_EVT_RX_END 55 +#define RMT_EVT_TX_THRESH 56 +#define RMT_EVT_RX_THRESH 57 +#define MCPWM_EVT_TIMER0_STOP 58 +#define MCPWM_EVT_TIMER1_STOP 59 +#define MCPWM_EVT_TIMER2_STOP 60 +#define MCPWM_EVT_TIMER0_TEZ 61 +#define MCPWM_EVT_TIMER1_TEZ 62 +#define MCPWM_EVT_TIMER2_TEZ 63 +#define MCPWM_EVT_TIMER0_TEP 64 +#define MCPWM_EVT_TIMER1_TEP 65 +#define MCPWM_EVT_TIMER2_TEP 66 +#define MCPWM_EVT_OP0_TEA 67 +#define MCPWM_EVT_OP1_TEA 68 +#define MCPWM_EVT_OP2_TEA 69 +#define MCPWM_EVT_OP0_TEB 70 +#define MCPWM_EVT_OP1_TEB 71 +#define MCPWM_EVT_OP2_TEB 72 +#define MCPWM_EVT_F0 73 +#define MCPWM_EVT_F1 74 +#define MCPWM_EVT_F2 75 +#define MCPWM_EVT_F0_CLR 76 +#define MCPWM_EVT_F1_CLR 77 +#define MCPWM_EVT_F2_CLR 78 +#define MCPWM_EVT_TZ0_CBC 79 +#define MCPWM_EVT_TZ1_CBC 80 +#define MCPWM_EVT_TZ2_CBC 81 +#define MCPWM_EVT_TZ0_OST 82 +#define MCPWM_EVT_TZ1_OST 83 +#define MCPWM_EVT_TZ2_OST 84 +#define MCPWM_EVT_CAP0 85 +#define MCPWM_EVT_CAP1 86 +#define MCPWM_EVT_CAP2 87 +#define ADC_EVT_CONV_CMPLT0 88 +#define ADC_EVT_EQ_ABOVE_THRESH0 89 +#define ADC_EVT_EQ_ABOVE_THRESH1 90 +#define ADC_EVT_EQ_BELOW_THRESH0 91 +#define ADC_EVT_EQ_BELOW_THRESH1 92 +#define ADC_EVT_RESULT_DONE0 93 +#define ADC_EVT_STOPPED0 94 +#define ADC_EVT_STARTED0 95 +#define REGDMA_EVT_DONE0 96 +#define REGDMA_EVT_DONE1 97 +#define REGDMA_EVT_DONE2 98 +#define REGDMA_EVT_DONE3 99 +#define REGDMA_EVT_ERR0 100 +#define REGDMA_EVT_ERR1 101 +#define REGDMA_EVT_ERR2 102 +#define REGDMA_EVT_ERR3 103 +#define PDMA_EVT_TX_DONE 104 +#define PDMA_EVT_OUT_EOF 105 +#define PDMA_EVT_IN_SUC_EOF 106 +#define PDMA_EVT_FULL_OR_EMPTY 107 +#define PDMA_EVT_ALL_DONE 108 +#define PDMA_EVT_RX_DONE 109 +#define TMPSNSR_EVT_OVER_LIMIT 110 +#define UART_EVT_REC_DATA_OVF0 111 +#define UART_EVT_REC_DATA_OVF1 112 +#define UART_EVT_TX_DONE0 113 +#define UART_EVT_TX_DONE1 114 +#define UART_EVT_TIMEOUT0 115 +#define UART_EVT_TIMEOUT1 116 +#define UART_EVT_ERR0 117 +#define UART_EVT_ERR1 118 +#define UART_EVT_CTS0 119 +#define UART_EVT_CTS1 120 +#define UART_EVT_TX_EMPTY0 121 +#define UART_EVT_TX_EMPTY1 122 +#define UART_EVT_AT_PATTERNS0 123 +#define UART_EVT_AT_PATTERNS1 124 +#define SPI_EVT_STOPPED 125 +#define I2S_EVT_RX_DONE 126 +#define I2S_EVT_TX_DONE 127 +#define I2S_EVT_X_WORDS_RECEIVED 128 +#define I2S_EVT_X_WORDS_SENT 129 +#define I2C_EVT_TRANS_DONE 130 +#define LCDCAM_EVT_TRANS_DONE 131 +#define TWAI_EVT_TRANS_DONE 132 +#define ULP_EVT_ERR_INTR 133 +#define ULP_EVT_START_INTR 134 +#define RTC_EVT_TICK 135 +#define RTC_EVT_OVF 136 +#define RTC_EVT_CMP 137 +#define GDMA_EVT_IN_DONE_CH0 138 +#define GDMA_EVT_IN_DONE_CH1 139 +#define GDMA_EVT_IN_DONE_CH2 140 +#define GDMA_EVT_IN_SUC_EOF_CH0 141 +#define GDMA_EVT_IN_SUC_EOF_CH1 142 +#define GDMA_EVT_IN_SUC_EOF_CH2 143 +#define GDMA_EVT_IN_FIFO_EMPTY_CH0 144 +#define GDMA_EVT_IN_FIFO_EMPTY_CH1 145 +#define GDMA_EVT_IN_FIFO_EMPTY_CH2 146 +#define GDMA_EVT_IN_FIFO_FULL_CH0 147 +#define GDMA_EVT_IN_FIFO_FULL_CH1 148 +#define GDMA_EVT_IN_FIFO_FULL_CH2 149 +#define GDMA_EVT_OUT_DONE_CH0 150 +#define GDMA_EVT_OUT_DONE_CH1 151 +#define GDMA_EVT_OUT_DONE_CH2 152 +#define GDMA_EVT_OUT_EOF_CH0 153 +#define GDMA_EVT_OUT_EOF_CH1 154 +#define GDMA_EVT_OUT_EOF_CH2 155 +#define GDMA_EVT_OUT_TOTAL_EOF_CH0 156 +#define GDMA_EVT_OUT_TOTAL_EOF_CH1 157 +#define GDMA_EVT_OUT_TOTAL_EOF_CH2 158 +#define GDMA_EVT_OUT_FIFO_EMPTY_CH0 159 +#define GDMA_EVT_OUT_FIFO_EMPTY_CH1 160 +#define GDMA_EVT_OUT_FIFO_EMPTY_CH2 161 +#define GDMA_EVT_OUT_FIFO_FULL_CH0 162 +#define GDMA_EVT_OUT_FIFO_FULL_CH1 163 +#define GDMA_EVT_OUT_FIFO_FULL_CH2 164 +#define PMU_EVT_SLEEP_WEEKUP 165 +#define GPIO_TASK_CH0_SET 1 +#define GPIO_TASK_CH1_SET 2 +#define GPIO_TASK_CH2_SET 3 +#define GPIO_TASK_CH3_SET 4 +#define GPIO_TASK_CH4_SET 5 +#define GPIO_TASK_CH5_SET 6 +#define GPIO_TASK_CH6_SET 7 +#define GPIO_TASK_CH7_SET 8 +#define GPIO_TASK_CH0_CLEAR 9 +#define GPIO_TASK_CH1_CLEAR 10 +#define GPIO_TASK_CH2_CLEAR 11 +#define GPIO_TASK_CH3_CLEAR 12 +#define GPIO_TASK_CH4_CLEAR 13 +#define GPIO_TASK_CH5_CLEAR 14 +#define GPIO_TASK_CH6_CLEAR 15 +#define GPIO_TASK_CH7_CLEAR 16 +#define GPIO_TASK_CH0_TOGGLE 17 +#define GPIO_TASK_CH1_TOGGLE 18 +#define GPIO_TASK_CH2_TOGGLE 19 +#define GPIO_TASK_CH3_TOGGLE 20 +#define GPIO_TASK_CH4_TOGGLE 21 +#define GPIO_TASK_CH5_TOGGLE 22 +#define GPIO_TASK_CH6_TOGGLE 23 +#define GPIO_TASK_CH7_TOGGLE 24 +#define LEDC_TASK_TIMER0_RES_UPDATE 25 +#define LEDC_TASK_TIMER1_RES_UPDATE 26 +#define LEDC_TASK_TIMER2_RES_UPDATE 27 +#define LEDC_TASK_TIMER3_RES_UPDATE 28 +#define LEDC_TASK_RESERVED0 29 +#define LEDC_TASK_RESERVED1 30 +#define LEDC_TASK_DUTY_SCALE_UPDATE_CH0 31 +#define LEDC_TASK_DUTY_SCALE_UPDATE_CH1 32 +#define LEDC_TASK_DUTY_SCALE_UPDATE_CH2 33 +#define LEDC_TASK_DUTY_SCALE_UPDATE_CH3 34 +#define LEDC_TASK_DUTY_SCALE_UPDATE_CH4 35 +#define LEDC_TASK_DUTY_SCALE_UPDATE_CH5 36 +#define LEDC_TASK_TIMER0_CAP 37 +#define LEDC_TASK_TIMER1_CAP 38 +#define LEDC_TASK_TIMER2_CAP 39 +#define LEDC_TASK_TIMER3_CAP 40 +#define LEDC_TASK_SIG_OUT_DIS_CH0 41 +#define LEDC_TASK_SIG_OUT_DIS_CH1 42 +#define LEDC_TASK_SIG_OUT_DIS_CH2 43 +#define LEDC_TASK_SIG_OUT_DIS_CH3 44 +#define LEDC_TASK_SIG_OUT_DIS_CH4 45 +#define LEDC_TASK_SIG_OUT_DIS_CH5 46 +#define LEDC_TASK_OVF_CNT_RST_CH0 47 +#define LEDC_TASK_OVF_CNT_RST_CH1 48 +#define LEDC_TASK_OVF_CNT_RST_CH2 49 +#define LEDC_TASK_OVF_CNT_RST_CH3 50 +#define LEDC_TASK_OVF_CNT_RST_CH4 51 +#define LEDC_TASK_OVF_CNT_RST_CH5 52 +#define LEDC_TASK_TIMER0_RST 53 +#define LEDC_TASK_TIMER1_RST 54 +#define LEDC_TASK_TIMER2_RST 55 +#define LEDC_TASK_TIMER3_RST 56 +#define LEDC_TASK_TIMER0_RESUME 57 +#define LEDC_TASK_TIMER1_RESUME 58 +#define LEDC_TASK_TIMER2_RESUME 59 +#define LEDC_TASK_TIMER3_RESUME 60 +#define LEDC_TASK_TIMER0_PAUSE 61 +#define LEDC_TASK_TIMER1_PAUSE 62 +#define LEDC_TASK_TIMER2_PAUSE 63 +#define LEDC_TASK_TIMER3_PAUSE 64 +#define LEDC_TASK_GAMMA_RESTART_CH0 65 +#define LEDC_TASK_GAMMA_RESTART_CH1 66 +#define LEDC_TASK_GAMMA_RESTART_CH2 67 +#define LEDC_TASK_GAMMA_RESTART_CH3 68 +#define LEDC_TASK_GAMMA_RESTART_CH4 69 +#define LEDC_TASK_GAMMA_RESTART_CH5 70 +#define LEDC_TASK_GAMMA_PAUSE_CH0 71 +#define LEDC_TASK_GAMMA_PAUSE_CH1 72 +#define LEDC_TASK_GAMMA_PAUSE_CH2 73 +#define LEDC_TASK_GAMMA_PAUSE_CH3 74 +#define LEDC_TASK_GAMMA_PAUSE_CH4 75 +#define LEDC_TASK_GAMMA_PAUSE_CH5 76 +#define LEDC_TASK_GAMMA_RESUME_CH0 77 +#define LEDC_TASK_GAMMA_RESUME_CH1 78 +#define LEDC_TASK_GAMMA_RESUME_CH2 79 +#define LEDC_TASK_GAMMA_RESUME_CH3 80 +#define LEDC_TASK_GAMMA_RESUME_CH4 81 +#define LEDC_TASK_GAMMA_RESUME_CH5 82 +#define PCNT_TASK_START 83 +#define PCNT_TASK_STOP 84 +#define PCNT_TASK_CNT_INC 85 +#define PCNT_TASK_CNT_DEC 86 +#define PCNT_TASK_CNT_RST 87 +#define TIMER0_TASK_CNT_START_TIMER0 88 +#define TIMER1_TASK_CNT_START_TIMER0 89 +#define TIMER0_TASK_ALARM_START_TIMER0 90 +#define TIMER1_TASK_ALARM_START_TIMER0 91 +#define TIMER0_TASK_CNT_STOP_TIMER0 92 +#define TIMER1_TASK_CNT_STOP_TIMER0 93 +#define TIMER0_TASK_CNT_RELOAD_TIMER0 94 +#define TIMER1_TASK_CNT_RELOAD_TIMER0 95 +#define TIMER0_TASK_CNT_CAP_TIMER0 96 +#define TIMER1_TASK_CNT_CAP_TIMER0 97 +#define RMT_TASK_TX_START 98 +#define RMT_TASK_TX_STOP 99 +#define RMT_TASK_RX_DONE 100 +#define RMT_TASK_RX_START 101 +#define MCPWM_TASK_CMPR0_A_UP 102 +#define MCPWM_TASK_CMPR1_A_UP 103 +#define MCPWM_TASK_CMPR2_A_UP 104 +#define MCPWM_TASK_CMPR0_B_UP 105 +#define MCPWM_TASK_CMPR1_B_UP 106 +#define MCPWM_TASK_CMPR2_B_UP 107 +#define MCPWM_TASK_GEN_STOP 108 +#define MCPWM_TASK_TIMER0_SYN 109 +#define MCPWM_TASK_TIMER1_SYN 110 +#define MCPWM_TASK_TIMER2_SYN 111 +#define MCPWM_TASK_TIMER0_PERIOD_UP 112 +#define MCPWM_TASK_TIMER1_PERIOD_UP 113 +#define MCPWM_TASK_TIMER2_PERIOD_UP 114 +#define MCPWM_TASK_TZ0_OST 115 +#define MCPWM_TASK_TZ1_OST 116 +#define MCPWM_TASK_TZ2_OST 117 +#define MCPWM_TASK_CLR0_OST 118 +#define MCPWM_TASK_CLR1_OST 119 +#define MCPWM_TASK_CLR2_OST 120 +#define MCPWM_TASK_CAP0 121 +#define MCPWM_TASK_CAP1 122 +#define MCPWM_TASK_CAP2 123 +#define ADC_TASK_SAMPLE0 124 +#define ADC_TASK_SAMPLE1 125 +#define ADC_TASK_START0 126 +#define ADC_TASK_STOP0 127 +#define REGDMA_TASK_START0 128 +#define REGDMA_TASK_START1 129 +#define REGDMA_TASK_START2 130 +#define REGDMA_TASK_START3 131 +#define PDMA_TASK_START_TX 132 +#define PDMA_TASK_START_RX 133 +#define PDMA_TASK_STOP 134 +#define TMPSNSR_TASK_START_SAMPLE 135 +#define TMPSNSR_TASK_STOP_SAMPLE 136 +#define UART_TASK_TX_START0 137 +#define UART_TASK_TX_START1 138 +#define UART_TASK_TX_STOP0 139 +#define UART_TASK_TX_STOP1 140 +#define UART_TASK_RX_START0 141 +#define UART_TASK_RX_START1 142 +#define UART_TASK_RX_STOP0 143 +#define UART_TASK_RX_STOP1 144 +#define SPI_TASK_TX_START 145 +#define SPI_TASK_SLAVE_HD 146 +#define SPI_TASK_STOP 147 +#define I2S_TASK_START_RX 148 +#define I2S_TASK_START_TX 149 +#define I2S_TASK_STOP_RX 150 +#define I2S_TASK_STOP_TX 151 +#define I2C_TASK_START_TRANS 152 +#define TWAI_TASK_TRANS_START 153 +#define ULP_TASK_WAKEUP_CPU 154 +#define RTC_TASK_START 155 +#define RTC_TASK_STOP 156 +#define RTC_TASK_CLR 157 +#define RTC_TASK_TRIGGERFLW 158 +#define GDMA_TASK_IN_START_CH0 159 +#define GDMA_TASK_IN_START_CH1 160 +#define GDMA_TASK_IN_START_CH2 161 +#define GDMA_TASK_OUT_START_CH0 162 +#define GDMA_TASK_OUT_START_CH1 163 +#define GDMA_TASK_OUT_START_CH2 164 +#define PMU_TASK_SLEEP_REQ 165 diff --git a/components/soc/esp32h21/interrupts.c b/components/soc/esp32h21/interrupts.c index e69de29bb2d..5ebe02a84e4 100644 --- a/components/soc/esp32h21/interrupts.c +++ b/components/soc/esp32h21/interrupts.c @@ -0,0 +1,75 @@ +/* + * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include "soc/interrupts.h" + +const char *const esp_isr_names[] = { + [0] = "PMU", + [1] = "EFUSE", + [2] = "LP_RTC_TIMER", + [3] = "LP_BLE_TIMER", + [4] = "LP_WDT", + [5] = "LP_PERI_TIMEOUT", + [6] = "LP_APM_M0", + [7] = "CPU_FROM_CPU_0", + [8] = "CPU_FROM_CPU_1", + [9] = "CPU_FROM_CPU_2", + [10] = "CPU_FROM_CPU_3", + [11] = "ASSIST_DEBUG", + [12] = "TRACE", + [13] = "CACHE", + [14] = "CPU_PERI_TIMEOUT", + [15] = "BT_MAC", + [16] = "BT_BB", + [17] = "BT_BB_NMI", + [18] = "COEX", + [19] = "BLE_TIMER", + [20] = "BLE_SEC", + [21] = "ZB_MAC", + [22] = "GPIO_INTERRUPT_PRO", + [23] = "GPIO_INTERRUPT_PRO_NMI", + [24] = "PAU", + [25] = "HP_PERI_TIMEOUT", + [26] = "HP_APM_M0", + [27] = "HP_APM_M1", + [28] = "HP_APM_M2", + [29] = "HP_APM_M3", + [30] = "MSPI", + [31] = "I2S1", + [32] = "UHCI0", + [33] = "UART0", + [34] = "UART1", + [35] = "LEDC", + [36] = "TWAI0", + [37] = "USB", + [38] = "RMT", + [39] = "I2C_EXT0", + [40] = "I2C_EXT1", + [41] = "TG0_T0", + [42] = "TG0_WDT", + [43] = "TG1_T0", + [44] = "TG1_WDT", + [45] = "SYSTIMER_TARGET0", + [46] = "SYSTIMER_TARGET1", + [47] = "SYSTIMER_TARGET2", + [48] = "APB_ADC", + [49] = "PWM", + [50] = "PCNT", + [51] = "PARL_IO_TX", + [52] = "PARL_IO_RX", + [53] = "DMA_IN_CH0", + [54] = "DMA_IN_CH1", + [55] = "DMA_IN_CH2", + [56] = "DMA_OUT_CH0", + [57] = "DMA_OUT_CH1", + [58] = "DMA_OUT_CH2", + [59] = "GPSPI2", + [60] = "AES", + [61] = "SHA", + [62] = "RSA", + [63] = "ECC", + [64] = "ECDSA", +}; diff --git a/components/soc/esp32h21/ld/esp32h21.peripherals.ld b/components/soc/esp32h21/ld/esp32h21.peripherals.ld new file mode 100644 index 00000000000..1dc197c8fbc --- /dev/null +++ b/components/soc/esp32h21/ld/esp32h21.peripherals.ld @@ -0,0 +1,57 @@ +/* + * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +PROVIDE ( UART0 = 0x60000000 ); +PROVIDE ( UART1 = 0x60001000 ); +PROVIDE ( SPIMEM0 = 0x60002000 ); +PROVIDE ( SPIMEM1 = 0x60003000 ); +PROVIDE ( I2C0 = 0x60004000 ); +PROVIDE ( I2C1 = 0x60005000 ); +PROVIDE ( UHCI0 = 0x60006000 ); +PROVIDE ( RMT = 0x60007000 ); +PROVIDE ( LEDC = 0x60008000 ); +PROVIDE ( TIMERG0 = 0x60009000 ); +PROVIDE ( TIMERG1 = 0x6000A000 ); +PROVIDE ( SYSTIMER = 0x6000B000 ); +PROVIDE ( TWAI = 0x6000C000 ); +PROVIDE ( I2S0 = 0x6000D000 ); +PROVIDE ( APB_SARADC = 0x6000E000 ); +PROVIDE ( USB_SERIAL_JTAG = 0x6000F000 ); +PROVIDE ( INTMTX = 0x60010000 ); +PROVIDE ( PCNT = 0x60012000 ); +PROVIDE ( SOC_ETM = 0x60013000 ); +PROVIDE ( MCPWM0 = 0x60014000 ); +PROVIDE ( PARL_IO = 0x60015000 ); +PROVIDE ( PVT = 0x60019000 ); +PROVIDE ( GDMA = 0x60080000 ); +PROVIDE ( GPSPI2 = 0x60081000 ); +PROVIDE ( AES = 0x60088000 ); +PROVIDE ( SHA = 0x60089000 ); +PROVIDE ( RSA = 0x6008A000 ); +PROVIDE ( ECC = 0x6008B000 ); +PROVIDE ( DS = 0x6008C000 ); +PROVIDE ( HMAC = 0x6008D000 ); +PROVIDE ( ECDSA = 0x6008E000 ); +PROVIDE ( IO_MUX = 0x60090000 ); +PROVIDE ( GPIO = 0x60091000 ); +PROVIDE ( GPIO_EXT = 0x60091E00 ); +PROVIDE ( MEM_MONITOR = 0x60092000 ); +PROVIDE ( PAU = 0x60093000 ); +PROVIDE ( HP_SYSTEM = 0x60095000 ); +PROVIDE ( PCR = 0x60096000 ); +PROVIDE ( TEE = 0x60098000 ); +PROVIDE ( HP_APM = 0x60099000 ); +PROVIDE ( LP_APM0 = 0x60099800 ); +PROVIDE ( PMU = 0x600B0000 ); +PROVIDE ( LP_CLKRST = 0x600B0400 ); +PROVIDE ( LP_TIMER = 0x600B0C00 ); +PROVIDE ( LP_AON = 0x600B1000 ); +PROVIDE ( LP_WDT = 0x600B1C00 ); +PROVIDE ( LPPERI = 0x600B2800 ); +PROVIDE ( LP_ANA_PERI = 0x600B2C00 ); +PROVIDE ( LP_TIMER = 0x600B3000 ); +PROVIDE ( LP_APM = 0x600B3800 ); +PROVIDE ( EFUSE = 0x600B4000 ); diff --git a/components/soc/esp32h21/register/soc/lp_analog_peri_reg.h b/components/soc/esp32h21/register/soc/lp_analog_peri_reg.h new file mode 100644 index 00000000000..8ab77f212f9 --- /dev/null +++ b/components/soc/esp32h21/register/soc/lp_analog_peri_reg.h @@ -0,0 +1,469 @@ +/** + * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#include "soc/soc.h" +#ifdef __cplusplus +extern "C" { +#endif + +/** LP_ANA_BOD_MODE0_CNTL_REG register + * need_des + */ +#define LP_ANA_BOD_MODE0_CNTL_REG (DR_REG_LP_AON_BASE + 0x0) +/** LP_ANA_BOD_MODE0_CLOSE_FLASH_ENA : R/W; bitpos: [6]; default: 0; + * need_des + */ +#define LP_ANA_BOD_MODE0_CLOSE_FLASH_ENA (BIT(6)) +#define LP_ANA_BOD_MODE0_CLOSE_FLASH_ENA_M (LP_ANA_BOD_MODE0_CLOSE_FLASH_ENA_V << LP_ANA_BOD_MODE0_CLOSE_FLASH_ENA_S) +#define LP_ANA_BOD_MODE0_CLOSE_FLASH_ENA_V 0x00000001U +#define LP_ANA_BOD_MODE0_CLOSE_FLASH_ENA_S 6 +/** LP_ANA_BOD_MODE0_PD_RF_ENA : R/W; bitpos: [7]; default: 0; + * need_des + */ +#define LP_ANA_BOD_MODE0_PD_RF_ENA (BIT(7)) +#define LP_ANA_BOD_MODE0_PD_RF_ENA_M (LP_ANA_BOD_MODE0_PD_RF_ENA_V << LP_ANA_BOD_MODE0_PD_RF_ENA_S) +#define LP_ANA_BOD_MODE0_PD_RF_ENA_V 0x00000001U +#define LP_ANA_BOD_MODE0_PD_RF_ENA_S 7 +/** LP_ANA_BOD_MODE0_INTR_WAIT : R/W; bitpos: [17:8]; default: 1; + * need_des + */ +#define LP_ANA_BOD_MODE0_INTR_WAIT 0x000003FFU +#define LP_ANA_BOD_MODE0_INTR_WAIT_M (LP_ANA_BOD_MODE0_INTR_WAIT_V << LP_ANA_BOD_MODE0_INTR_WAIT_S) +#define LP_ANA_BOD_MODE0_INTR_WAIT_V 0x000003FFU +#define LP_ANA_BOD_MODE0_INTR_WAIT_S 8 +/** LP_ANA_BOD_MODE0_RESET_WAIT : R/W; bitpos: [27:18]; default: 1023; + * need_des + */ +#define LP_ANA_BOD_MODE0_RESET_WAIT 0x000003FFU +#define LP_ANA_BOD_MODE0_RESET_WAIT_M (LP_ANA_BOD_MODE0_RESET_WAIT_V << LP_ANA_BOD_MODE0_RESET_WAIT_S) +#define LP_ANA_BOD_MODE0_RESET_WAIT_V 0x000003FFU +#define LP_ANA_BOD_MODE0_RESET_WAIT_S 18 +/** LP_ANA_BOD_MODE0_CNT_CLR : R/W; bitpos: [28]; default: 0; + * need_des + */ +#define LP_ANA_BOD_MODE0_CNT_CLR (BIT(28)) +#define LP_ANA_BOD_MODE0_CNT_CLR_M (LP_ANA_BOD_MODE0_CNT_CLR_V << LP_ANA_BOD_MODE0_CNT_CLR_S) +#define LP_ANA_BOD_MODE0_CNT_CLR_V 0x00000001U +#define LP_ANA_BOD_MODE0_CNT_CLR_S 28 +/** LP_ANA_BOD_MODE0_INTR_ENA : R/W; bitpos: [29]; default: 0; + * need_des + */ +#define LP_ANA_BOD_MODE0_INTR_ENA (BIT(29)) +#define LP_ANA_BOD_MODE0_INTR_ENA_M (LP_ANA_BOD_MODE0_INTR_ENA_V << LP_ANA_BOD_MODE0_INTR_ENA_S) +#define LP_ANA_BOD_MODE0_INTR_ENA_V 0x00000001U +#define LP_ANA_BOD_MODE0_INTR_ENA_S 29 +/** LP_ANA_BOD_MODE0_RESET_SEL : R/W; bitpos: [30]; default: 0; + * need_des + */ +#define LP_ANA_BOD_MODE0_RESET_SEL (BIT(30)) +#define LP_ANA_BOD_MODE0_RESET_SEL_M (LP_ANA_BOD_MODE0_RESET_SEL_V << LP_ANA_BOD_MODE0_RESET_SEL_S) +#define LP_ANA_BOD_MODE0_RESET_SEL_V 0x00000001U +#define LP_ANA_BOD_MODE0_RESET_SEL_S 30 +/** LP_ANA_BOD_MODE0_RESET_ENA : R/W; bitpos: [31]; default: 0; + * need_des + */ +#define LP_ANA_BOD_MODE0_RESET_ENA (BIT(31)) +#define LP_ANA_BOD_MODE0_RESET_ENA_M (LP_ANA_BOD_MODE0_RESET_ENA_V << LP_ANA_BOD_MODE0_RESET_ENA_S) +#define LP_ANA_BOD_MODE0_RESET_ENA_V 0x00000001U +#define LP_ANA_BOD_MODE0_RESET_ENA_S 31 + +/** LP_ANA_BOD_MODE1_CNTL_REG register + * need_des + */ +#define LP_ANA_BOD_MODE1_CNTL_REG (DR_REG_LP_AON_BASE + 0x4) +/** LP_ANA_BOD_MODE1_RESET_ENA : R/W; bitpos: [31]; default: 0; + * need_des + */ +#define LP_ANA_BOD_MODE1_RESET_ENA (BIT(31)) +#define LP_ANA_BOD_MODE1_RESET_ENA_M (LP_ANA_BOD_MODE1_RESET_ENA_V << LP_ANA_BOD_MODE1_RESET_ENA_S) +#define LP_ANA_BOD_MODE1_RESET_ENA_V 0x00000001U +#define LP_ANA_BOD_MODE1_RESET_ENA_S 31 + +/** LP_ANA_VDD_SOURCE_CNTL_REG register + * need_des + */ +#define LP_ANA_VDD_SOURCE_CNTL_REG (DR_REG_LP_AON_BASE + 0x8) +/** LP_ANA_DETMODE_SEL : R/W; bitpos: [7:0]; default: 255; + * need_des + */ +#define LP_ANA_DETMODE_SEL 0x000000FFU +#define LP_ANA_DETMODE_SEL_M (LP_ANA_DETMODE_SEL_V << LP_ANA_DETMODE_SEL_S) +#define LP_ANA_DETMODE_SEL_V 0x000000FFU +#define LP_ANA_DETMODE_SEL_S 0 +/** LP_ANA_VGOOD_EVENT_RECORD : RO; bitpos: [15:8]; default: 0; + * need_des + */ +#define LP_ANA_VGOOD_EVENT_RECORD 0x000000FFU +#define LP_ANA_VGOOD_EVENT_RECORD_M (LP_ANA_VGOOD_EVENT_RECORD_V << LP_ANA_VGOOD_EVENT_RECORD_S) +#define LP_ANA_VGOOD_EVENT_RECORD_V 0x000000FFU +#define LP_ANA_VGOOD_EVENT_RECORD_S 8 +/** LP_ANA_VBAT_EVENT_RECORD_CLR : WT; bitpos: [23:16]; default: 0; + * need_des + */ +#define LP_ANA_VBAT_EVENT_RECORD_CLR 0x000000FFU +#define LP_ANA_VBAT_EVENT_RECORD_CLR_M (LP_ANA_VBAT_EVENT_RECORD_CLR_V << LP_ANA_VBAT_EVENT_RECORD_CLR_S) +#define LP_ANA_VBAT_EVENT_RECORD_CLR_V 0x000000FFU +#define LP_ANA_VBAT_EVENT_RECORD_CLR_S 16 +/** LP_ANA_BOD_SOURCE_ENA : R/W; bitpos: [31:24]; default: 4; + * need_des + */ +#define LP_ANA_BOD_SOURCE_ENA 0x000000FFU +#define LP_ANA_BOD_SOURCE_ENA_M (LP_ANA_BOD_SOURCE_ENA_V << LP_ANA_BOD_SOURCE_ENA_S) +#define LP_ANA_BOD_SOURCE_ENA_V 0x000000FFU +#define LP_ANA_BOD_SOURCE_ENA_S 24 + +/** LP_ANA_VDDBAT_BOD_CNTL_REG register + * need_des + */ +#define LP_ANA_VDDBAT_BOD_CNTL_REG (DR_REG_LP_AON_BASE + 0xc) +/** LP_ANA_VDDBAT_UNDERVOLTAGE_FLAG : RO; bitpos: [0]; default: 0; + * need_des + */ +#define LP_ANA_VDDBAT_UNDERVOLTAGE_FLAG (BIT(0)) +#define LP_ANA_VDDBAT_UNDERVOLTAGE_FLAG_M (LP_ANA_VDDBAT_UNDERVOLTAGE_FLAG_V << LP_ANA_VDDBAT_UNDERVOLTAGE_FLAG_S) +#define LP_ANA_VDDBAT_UNDERVOLTAGE_FLAG_V 0x00000001U +#define LP_ANA_VDDBAT_UNDERVOLTAGE_FLAG_S 0 +/** LP_ANA_VDDBAT_CHARGER : R/W; bitpos: [10]; default: 0; + * need_des + */ +#define LP_ANA_VDDBAT_CHARGER (BIT(10)) +#define LP_ANA_VDDBAT_CHARGER_M (LP_ANA_VDDBAT_CHARGER_V << LP_ANA_VDDBAT_CHARGER_S) +#define LP_ANA_VDDBAT_CHARGER_V 0x00000001U +#define LP_ANA_VDDBAT_CHARGER_S 10 +/** LP_ANA_VDDBAT_CNT_CLR : R/W; bitpos: [11]; default: 0; + * need_des + */ +#define LP_ANA_VDDBAT_CNT_CLR (BIT(11)) +#define LP_ANA_VDDBAT_CNT_CLR_M (LP_ANA_VDDBAT_CNT_CLR_V << LP_ANA_VDDBAT_CNT_CLR_S) +#define LP_ANA_VDDBAT_CNT_CLR_V 0x00000001U +#define LP_ANA_VDDBAT_CNT_CLR_S 11 +/** LP_ANA_VDDBAT_UPVOLTAGE_TARGET : R/W; bitpos: [21:12]; default: 0; + * need_des + */ +#define LP_ANA_VDDBAT_UPVOLTAGE_TARGET 0x000003FFU +#define LP_ANA_VDDBAT_UPVOLTAGE_TARGET_M (LP_ANA_VDDBAT_UPVOLTAGE_TARGET_V << LP_ANA_VDDBAT_UPVOLTAGE_TARGET_S) +#define LP_ANA_VDDBAT_UPVOLTAGE_TARGET_V 0x000003FFU +#define LP_ANA_VDDBAT_UPVOLTAGE_TARGET_S 12 +/** LP_ANA_VDDBAT_UNDERVOLTAGE_TARGET : R/W; bitpos: [31:22]; default: 1023; + * need_des + */ +#define LP_ANA_VDDBAT_UNDERVOLTAGE_TARGET 0x000003FFU +#define LP_ANA_VDDBAT_UNDERVOLTAGE_TARGET_M (LP_ANA_VDDBAT_UNDERVOLTAGE_TARGET_V << LP_ANA_VDDBAT_UNDERVOLTAGE_TARGET_S) +#define LP_ANA_VDDBAT_UNDERVOLTAGE_TARGET_V 0x000003FFU +#define LP_ANA_VDDBAT_UNDERVOLTAGE_TARGET_S 22 + +/** LP_ANA_VDDBAT_CHARGE_CNTL_REG register + * need_des + */ +#define LP_ANA_VDDBAT_CHARGE_CNTL_REG (DR_REG_LP_AON_BASE + 0x10) +/** LP_ANA_VDDBAT_CHARGE_UNDERVOLTAGE_FLAG : RO; bitpos: [0]; default: 0; + * need_des + */ +#define LP_ANA_VDDBAT_CHARGE_UNDERVOLTAGE_FLAG (BIT(0)) +#define LP_ANA_VDDBAT_CHARGE_UNDERVOLTAGE_FLAG_M (LP_ANA_VDDBAT_CHARGE_UNDERVOLTAGE_FLAG_V << LP_ANA_VDDBAT_CHARGE_UNDERVOLTAGE_FLAG_S) +#define LP_ANA_VDDBAT_CHARGE_UNDERVOLTAGE_FLAG_V 0x00000001U +#define LP_ANA_VDDBAT_CHARGE_UNDERVOLTAGE_FLAG_S 0 +/** LP_ANA_VDDBAT_CHARGE_CHARGER : R/W; bitpos: [10]; default: 0; + * need_des + */ +#define LP_ANA_VDDBAT_CHARGE_CHARGER (BIT(10)) +#define LP_ANA_VDDBAT_CHARGE_CHARGER_M (LP_ANA_VDDBAT_CHARGE_CHARGER_V << LP_ANA_VDDBAT_CHARGE_CHARGER_S) +#define LP_ANA_VDDBAT_CHARGE_CHARGER_V 0x00000001U +#define LP_ANA_VDDBAT_CHARGE_CHARGER_S 10 +/** LP_ANA_VDDBAT_CHARGE_CNT_CLR : R/W; bitpos: [11]; default: 0; + * need_des + */ +#define LP_ANA_VDDBAT_CHARGE_CNT_CLR (BIT(11)) +#define LP_ANA_VDDBAT_CHARGE_CNT_CLR_M (LP_ANA_VDDBAT_CHARGE_CNT_CLR_V << LP_ANA_VDDBAT_CHARGE_CNT_CLR_S) +#define LP_ANA_VDDBAT_CHARGE_CNT_CLR_V 0x00000001U +#define LP_ANA_VDDBAT_CHARGE_CNT_CLR_S 11 +/** LP_ANA_VDDBAT_CHARGE_UPVOLTAGE_TARGET : R/W; bitpos: [21:12]; default: 0; + * need_des + */ +#define LP_ANA_VDDBAT_CHARGE_UPVOLTAGE_TARGET 0x000003FFU +#define LP_ANA_VDDBAT_CHARGE_UPVOLTAGE_TARGET_M (LP_ANA_VDDBAT_CHARGE_UPVOLTAGE_TARGET_V << LP_ANA_VDDBAT_CHARGE_UPVOLTAGE_TARGET_S) +#define LP_ANA_VDDBAT_CHARGE_UPVOLTAGE_TARGET_V 0x000003FFU +#define LP_ANA_VDDBAT_CHARGE_UPVOLTAGE_TARGET_S 12 +/** LP_ANA_VDDBAT_CHARGE_UNDERVOLTAGE_TARGET : R/W; bitpos: [31:22]; default: 1023; + * need_des + */ +#define LP_ANA_VDDBAT_CHARGE_UNDERVOLTAGE_TARGET 0x000003FFU +#define LP_ANA_VDDBAT_CHARGE_UNDERVOLTAGE_TARGET_M (LP_ANA_VDDBAT_CHARGE_UNDERVOLTAGE_TARGET_V << LP_ANA_VDDBAT_CHARGE_UNDERVOLTAGE_TARGET_S) +#define LP_ANA_VDDBAT_CHARGE_UNDERVOLTAGE_TARGET_V 0x000003FFU +#define LP_ANA_VDDBAT_CHARGE_UNDERVOLTAGE_TARGET_S 22 + +/** LP_ANA_CK_GLITCH_CNTL_REG register + * need_des + */ +#define LP_ANA_CK_GLITCH_CNTL_REG (DR_REG_LP_AON_BASE + 0x14) +/** LP_ANA_CK_GLITCH_RESET_ENA : R/W; bitpos: [31]; default: 0; + * need_des + */ +#define LP_ANA_CK_GLITCH_RESET_ENA (BIT(31)) +#define LP_ANA_CK_GLITCH_RESET_ENA_M (LP_ANA_CK_GLITCH_RESET_ENA_V << LP_ANA_CK_GLITCH_RESET_ENA_S) +#define LP_ANA_CK_GLITCH_RESET_ENA_V 0x00000001U +#define LP_ANA_CK_GLITCH_RESET_ENA_S 31 + +/** LP_ANA_PG_GLITCH_CNTL_REG register + * need_des + */ +#define LP_ANA_PG_GLITCH_CNTL_REG (DR_REG_LP_AON_BASE + 0x18) +/** LP_ANA_POWER_GLITCH_RESET_ENA : R/W; bitpos: [31:26]; default: 0; + * need_des + */ +#define LP_ANA_POWER_GLITCH_RESET_ENA 0x0000003FU +#define LP_ANA_POWER_GLITCH_RESET_ENA_M (LP_ANA_POWER_GLITCH_RESET_ENA_V << LP_ANA_POWER_GLITCH_RESET_ENA_S) +#define LP_ANA_POWER_GLITCH_RESET_ENA_V 0x0000003FU +#define LP_ANA_POWER_GLITCH_RESET_ENA_S 26 + +/** LP_ANA_FIB_ENABLE_REG register + * need_des + */ +#define LP_ANA_FIB_ENABLE_REG (DR_REG_LP_AON_BASE + 0x1c) +/** LP_ANA_ANA_FIB_ENA : R/W; bitpos: [31:24]; default: 255; + * need_des + */ +#define LP_ANA_ANA_FIB_ENA 0x000000FFU +#define LP_ANA_ANA_FIB_ENA_M (LP_ANA_ANA_FIB_ENA_V << LP_ANA_ANA_FIB_ENA_S) +#define LP_ANA_ANA_FIB_ENA_V 0x000000FFU +#define LP_ANA_ANA_FIB_ENA_S 24 + +#define LP_ANALOG_PERI_LP_ANA_FIB_GLITCH_RST BIT(0) +#define LP_ANALOG_PERI_LP_ANA_FIB_BOD_RST BIT(1) +#define LP_ANALOG_PERI_LP_ANA_FIB_SUPER_WDT_RST BIT(2) + +/** LP_ANA_INT_RAW_REG register + * need_des + */ +#define LP_ANA_INT_RAW_REG (DR_REG_LP_AON_BASE + 0x20) +/** LP_ANA_VDDBAT_CHARGE_UPVOLTAGE_INT_RAW : R/WTC/SS; bitpos: [27]; default: 0; + * need_des + */ +#define LP_ANA_VDDBAT_CHARGE_UPVOLTAGE_INT_RAW (BIT(27)) +#define LP_ANA_VDDBAT_CHARGE_UPVOLTAGE_INT_RAW_M (LP_ANA_VDDBAT_CHARGE_UPVOLTAGE_INT_RAW_V << LP_ANA_VDDBAT_CHARGE_UPVOLTAGE_INT_RAW_S) +#define LP_ANA_VDDBAT_CHARGE_UPVOLTAGE_INT_RAW_V 0x00000001U +#define LP_ANA_VDDBAT_CHARGE_UPVOLTAGE_INT_RAW_S 27 +/** LP_ANA_VDDBAT_CHARGE_UNDERVOLTAGE_INT_RAW : R/WTC/SS; bitpos: [28]; default: 0; + * need_des + */ +#define LP_ANA_VDDBAT_CHARGE_UNDERVOLTAGE_INT_RAW (BIT(28)) +#define LP_ANA_VDDBAT_CHARGE_UNDERVOLTAGE_INT_RAW_M (LP_ANA_VDDBAT_CHARGE_UNDERVOLTAGE_INT_RAW_V << LP_ANA_VDDBAT_CHARGE_UNDERVOLTAGE_INT_RAW_S) +#define LP_ANA_VDDBAT_CHARGE_UNDERVOLTAGE_INT_RAW_V 0x00000001U +#define LP_ANA_VDDBAT_CHARGE_UNDERVOLTAGE_INT_RAW_S 28 +/** LP_ANA_VDDBAT_UPVOLTAGE_INT_RAW : R/WTC/SS; bitpos: [29]; default: 0; + * need_des + */ +#define LP_ANA_VDDBAT_UPVOLTAGE_INT_RAW (BIT(29)) +#define LP_ANA_VDDBAT_UPVOLTAGE_INT_RAW_M (LP_ANA_VDDBAT_UPVOLTAGE_INT_RAW_V << LP_ANA_VDDBAT_UPVOLTAGE_INT_RAW_S) +#define LP_ANA_VDDBAT_UPVOLTAGE_INT_RAW_V 0x00000001U +#define LP_ANA_VDDBAT_UPVOLTAGE_INT_RAW_S 29 +/** LP_ANA_VDDBAT_UNDERVOLTAGE_INT_RAW : R/WTC/SS; bitpos: [30]; default: 0; + * need_des + */ +#define LP_ANA_VDDBAT_UNDERVOLTAGE_INT_RAW (BIT(30)) +#define LP_ANA_VDDBAT_UNDERVOLTAGE_INT_RAW_M (LP_ANA_VDDBAT_UNDERVOLTAGE_INT_RAW_V << LP_ANA_VDDBAT_UNDERVOLTAGE_INT_RAW_S) +#define LP_ANA_VDDBAT_UNDERVOLTAGE_INT_RAW_V 0x00000001U +#define LP_ANA_VDDBAT_UNDERVOLTAGE_INT_RAW_S 30 +/** LP_ANA_BOD_MODE0_INT_RAW : R/WTC/SS; bitpos: [31]; default: 0; + * need_des + */ +#define LP_ANA_BOD_MODE0_INT_RAW (BIT(31)) +#define LP_ANA_BOD_MODE0_INT_RAW_M (LP_ANA_BOD_MODE0_INT_RAW_V << LP_ANA_BOD_MODE0_INT_RAW_S) +#define LP_ANA_BOD_MODE0_INT_RAW_V 0x00000001U +#define LP_ANA_BOD_MODE0_INT_RAW_S 31 + +/** LP_ANA_INT_ST_REG register + * need_des + */ +#define LP_ANA_INT_ST_REG (DR_REG_LP_AON_BASE + 0x24) +/** LP_ANA_VDDBAT_CHARGE_UPVOLTAGE_INT_ST : RO; bitpos: [27]; default: 0; + * need_des + */ +#define LP_ANA_VDDBAT_CHARGE_UPVOLTAGE_INT_ST (BIT(27)) +#define LP_ANA_VDDBAT_CHARGE_UPVOLTAGE_INT_ST_M (LP_ANA_VDDBAT_CHARGE_UPVOLTAGE_INT_ST_V << LP_ANA_VDDBAT_CHARGE_UPVOLTAGE_INT_ST_S) +#define LP_ANA_VDDBAT_CHARGE_UPVOLTAGE_INT_ST_V 0x00000001U +#define LP_ANA_VDDBAT_CHARGE_UPVOLTAGE_INT_ST_S 27 +/** LP_ANA_VDDBAT_CHARGE_UNDERVOLTAGE_INT_ST : RO; bitpos: [28]; default: 0; + * need_des + */ +#define LP_ANA_VDDBAT_CHARGE_UNDERVOLTAGE_INT_ST (BIT(28)) +#define LP_ANA_VDDBAT_CHARGE_UNDERVOLTAGE_INT_ST_M (LP_ANA_VDDBAT_CHARGE_UNDERVOLTAGE_INT_ST_V << LP_ANA_VDDBAT_CHARGE_UNDERVOLTAGE_INT_ST_S) +#define LP_ANA_VDDBAT_CHARGE_UNDERVOLTAGE_INT_ST_V 0x00000001U +#define LP_ANA_VDDBAT_CHARGE_UNDERVOLTAGE_INT_ST_S 28 +/** LP_ANA_VDDBAT_UPVOLTAGE_INT_ST : RO; bitpos: [29]; default: 0; + * need_des + */ +#define LP_ANA_VDDBAT_UPVOLTAGE_INT_ST (BIT(29)) +#define LP_ANA_VDDBAT_UPVOLTAGE_INT_ST_M (LP_ANA_VDDBAT_UPVOLTAGE_INT_ST_V << LP_ANA_VDDBAT_UPVOLTAGE_INT_ST_S) +#define LP_ANA_VDDBAT_UPVOLTAGE_INT_ST_V 0x00000001U +#define LP_ANA_VDDBAT_UPVOLTAGE_INT_ST_S 29 +/** LP_ANA_VDDBAT_UNDERVOLTAGE_INT_ST : RO; bitpos: [30]; default: 0; + * need_des + */ +#define LP_ANA_VDDBAT_UNDERVOLTAGE_INT_ST (BIT(30)) +#define LP_ANA_VDDBAT_UNDERVOLTAGE_INT_ST_M (LP_ANA_VDDBAT_UNDERVOLTAGE_INT_ST_V << LP_ANA_VDDBAT_UNDERVOLTAGE_INT_ST_S) +#define LP_ANA_VDDBAT_UNDERVOLTAGE_INT_ST_V 0x00000001U +#define LP_ANA_VDDBAT_UNDERVOLTAGE_INT_ST_S 30 +/** LP_ANA_BOD_MODE0_INT_ST : RO; bitpos: [31]; default: 0; + * need_des + */ +#define LP_ANA_BOD_MODE0_INT_ST (BIT(31)) +#define LP_ANA_BOD_MODE0_INT_ST_M (LP_ANA_BOD_MODE0_INT_ST_V << LP_ANA_BOD_MODE0_INT_ST_S) +#define LP_ANA_BOD_MODE0_INT_ST_V 0x00000001U +#define LP_ANA_BOD_MODE0_INT_ST_S 31 + +/** LP_ANA_INT_ENA_REG register + * need_des + */ +#define LP_ANA_INT_ENA_REG (DR_REG_LP_AON_BASE + 0x28) +/** LP_ANA_VDDBAT_CHARGE_UPVOLTAGE_INT_ENA : R/W; bitpos: [27]; default: 0; + * need_des + */ +#define LP_ANA_VDDBAT_CHARGE_UPVOLTAGE_INT_ENA (BIT(27)) +#define LP_ANA_VDDBAT_CHARGE_UPVOLTAGE_INT_ENA_M (LP_ANA_VDDBAT_CHARGE_UPVOLTAGE_INT_ENA_V << LP_ANA_VDDBAT_CHARGE_UPVOLTAGE_INT_ENA_S) +#define LP_ANA_VDDBAT_CHARGE_UPVOLTAGE_INT_ENA_V 0x00000001U +#define LP_ANA_VDDBAT_CHARGE_UPVOLTAGE_INT_ENA_S 27 +/** LP_ANA_VDDBAT_CHARGE_UNDERVOLTAGE_INT_ENA : R/W; bitpos: [28]; default: 0; + * need_des + */ +#define LP_ANA_VDDBAT_CHARGE_UNDERVOLTAGE_INT_ENA (BIT(28)) +#define LP_ANA_VDDBAT_CHARGE_UNDERVOLTAGE_INT_ENA_M (LP_ANA_VDDBAT_CHARGE_UNDERVOLTAGE_INT_ENA_V << LP_ANA_VDDBAT_CHARGE_UNDERVOLTAGE_INT_ENA_S) +#define LP_ANA_VDDBAT_CHARGE_UNDERVOLTAGE_INT_ENA_V 0x00000001U +#define LP_ANA_VDDBAT_CHARGE_UNDERVOLTAGE_INT_ENA_S 28 +/** LP_ANA_VDDBAT_UPVOLTAGE_INT_ENA : R/W; bitpos: [29]; default: 0; + * need_des + */ +#define LP_ANA_VDDBAT_UPVOLTAGE_INT_ENA (BIT(29)) +#define LP_ANA_VDDBAT_UPVOLTAGE_INT_ENA_M (LP_ANA_VDDBAT_UPVOLTAGE_INT_ENA_V << LP_ANA_VDDBAT_UPVOLTAGE_INT_ENA_S) +#define LP_ANA_VDDBAT_UPVOLTAGE_INT_ENA_V 0x00000001U +#define LP_ANA_VDDBAT_UPVOLTAGE_INT_ENA_S 29 +/** LP_ANA_VDDBAT_UNDERVOLTAGE_INT_ENA : R/W; bitpos: [30]; default: 0; + * need_des + */ +#define LP_ANA_VDDBAT_UNDERVOLTAGE_INT_ENA (BIT(30)) +#define LP_ANA_VDDBAT_UNDERVOLTAGE_INT_ENA_M (LP_ANA_VDDBAT_UNDERVOLTAGE_INT_ENA_V << LP_ANA_VDDBAT_UNDERVOLTAGE_INT_ENA_S) +#define LP_ANA_VDDBAT_UNDERVOLTAGE_INT_ENA_V 0x00000001U +#define LP_ANA_VDDBAT_UNDERVOLTAGE_INT_ENA_S 30 +/** LP_ANA_BOD_MODE0_INT_ENA : R/W; bitpos: [31]; default: 0; + * need_des + */ +#define LP_ANA_BOD_MODE0_INT_ENA (BIT(31)) +#define LP_ANA_BOD_MODE0_INT_ENA_M (LP_ANA_BOD_MODE0_INT_ENA_V << LP_ANA_BOD_MODE0_INT_ENA_S) +#define LP_ANA_BOD_MODE0_INT_ENA_V 0x00000001U +#define LP_ANA_BOD_MODE0_INT_ENA_S 31 + +/** LP_ANA_INT_CLR_REG register + * need_des + */ +#define LP_ANA_INT_CLR_REG (DR_REG_LP_AON_BASE + 0x2c) +/** LP_ANA_VDDBAT_CHARGE_UPVOLTAGE_INT_CLR : WT; bitpos: [27]; default: 0; + * need_des + */ +#define LP_ANA_VDDBAT_CHARGE_UPVOLTAGE_INT_CLR (BIT(27)) +#define LP_ANA_VDDBAT_CHARGE_UPVOLTAGE_INT_CLR_M (LP_ANA_VDDBAT_CHARGE_UPVOLTAGE_INT_CLR_V << LP_ANA_VDDBAT_CHARGE_UPVOLTAGE_INT_CLR_S) +#define LP_ANA_VDDBAT_CHARGE_UPVOLTAGE_INT_CLR_V 0x00000001U +#define LP_ANA_VDDBAT_CHARGE_UPVOLTAGE_INT_CLR_S 27 +/** LP_ANA_VDDBAT_CHARGE_UNDERVOLTAGE_INT_CLR : WT; bitpos: [28]; default: 0; + * need_des + */ +#define LP_ANA_VDDBAT_CHARGE_UNDERVOLTAGE_INT_CLR (BIT(28)) +#define LP_ANA_VDDBAT_CHARGE_UNDERVOLTAGE_INT_CLR_M (LP_ANA_VDDBAT_CHARGE_UNDERVOLTAGE_INT_CLR_V << LP_ANA_VDDBAT_CHARGE_UNDERVOLTAGE_INT_CLR_S) +#define LP_ANA_VDDBAT_CHARGE_UNDERVOLTAGE_INT_CLR_V 0x00000001U +#define LP_ANA_VDDBAT_CHARGE_UNDERVOLTAGE_INT_CLR_S 28 +/** LP_ANA_VDDBAT_UPVOLTAGE_INT_CLR : WT; bitpos: [29]; default: 0; + * need_des + */ +#define LP_ANA_VDDBAT_UPVOLTAGE_INT_CLR (BIT(29)) +#define LP_ANA_VDDBAT_UPVOLTAGE_INT_CLR_M (LP_ANA_VDDBAT_UPVOLTAGE_INT_CLR_V << LP_ANA_VDDBAT_UPVOLTAGE_INT_CLR_S) +#define LP_ANA_VDDBAT_UPVOLTAGE_INT_CLR_V 0x00000001U +#define LP_ANA_VDDBAT_UPVOLTAGE_INT_CLR_S 29 +/** LP_ANA_VDDBAT_UNDERVOLTAGE_INT_CLR : WT; bitpos: [30]; default: 0; + * need_des + */ +#define LP_ANA_VDDBAT_UNDERVOLTAGE_INT_CLR (BIT(30)) +#define LP_ANA_VDDBAT_UNDERVOLTAGE_INT_CLR_M (LP_ANA_VDDBAT_UNDERVOLTAGE_INT_CLR_V << LP_ANA_VDDBAT_UNDERVOLTAGE_INT_CLR_S) +#define LP_ANA_VDDBAT_UNDERVOLTAGE_INT_CLR_V 0x00000001U +#define LP_ANA_VDDBAT_UNDERVOLTAGE_INT_CLR_S 30 +/** LP_ANA_BOD_MODE0_INT_CLR : WT; bitpos: [31]; default: 0; + * need_des + */ +#define LP_ANA_BOD_MODE0_INT_CLR (BIT(31)) +#define LP_ANA_BOD_MODE0_INT_CLR_M (LP_ANA_BOD_MODE0_INT_CLR_V << LP_ANA_BOD_MODE0_INT_CLR_S) +#define LP_ANA_BOD_MODE0_INT_CLR_V 0x00000001U +#define LP_ANA_BOD_MODE0_INT_CLR_S 31 + +/** LP_ANA_LP_INT_RAW_REG register + * need_des + */ +#define LP_ANA_LP_INT_RAW_REG (DR_REG_LP_AON_BASE + 0x30) +/** LP_ANA_BOD_MODE0_LP_INT_RAW : R/WTC/SS; bitpos: [31]; default: 0; + * need_des + */ +#define LP_ANA_BOD_MODE0_LP_INT_RAW (BIT(31)) +#define LP_ANA_BOD_MODE0_LP_INT_RAW_M (LP_ANA_BOD_MODE0_LP_INT_RAW_V << LP_ANA_BOD_MODE0_LP_INT_RAW_S) +#define LP_ANA_BOD_MODE0_LP_INT_RAW_V 0x00000001U +#define LP_ANA_BOD_MODE0_LP_INT_RAW_S 31 + +/** LP_ANA_LP_INT_ST_REG register + * need_des + */ +#define LP_ANA_LP_INT_ST_REG (DR_REG_LP_AON_BASE + 0x34) +/** LP_ANA_BOD_MODE0_LP_INT_ST : RO; bitpos: [31]; default: 0; + * need_des + */ +#define LP_ANA_BOD_MODE0_LP_INT_ST (BIT(31)) +#define LP_ANA_BOD_MODE0_LP_INT_ST_M (LP_ANA_BOD_MODE0_LP_INT_ST_V << LP_ANA_BOD_MODE0_LP_INT_ST_S) +#define LP_ANA_BOD_MODE0_LP_INT_ST_V 0x00000001U +#define LP_ANA_BOD_MODE0_LP_INT_ST_S 31 + +/** LP_ANA_LP_INT_ENA_REG register + * need_des + */ +#define LP_ANA_LP_INT_ENA_REG (DR_REG_LP_AON_BASE + 0x38) +/** LP_ANA_BOD_MODE0_LP_INT_ENA : R/W; bitpos: [31]; default: 0; + * need_des + */ +#define LP_ANA_BOD_MODE0_LP_INT_ENA (BIT(31)) +#define LP_ANA_BOD_MODE0_LP_INT_ENA_M (LP_ANA_BOD_MODE0_LP_INT_ENA_V << LP_ANA_BOD_MODE0_LP_INT_ENA_S) +#define LP_ANA_BOD_MODE0_LP_INT_ENA_V 0x00000001U +#define LP_ANA_BOD_MODE0_LP_INT_ENA_S 31 + +/** LP_ANA_LP_INT_CLR_REG register + * need_des + */ +#define LP_ANA_LP_INT_CLR_REG (DR_REG_LP_AON_BASE + 0x3c) +/** LP_ANA_BOD_MODE0_LP_INT_CLR : WT; bitpos: [31]; default: 0; + * need_des + */ +#define LP_ANA_BOD_MODE0_LP_INT_CLR (BIT(31)) +#define LP_ANA_BOD_MODE0_LP_INT_CLR_M (LP_ANA_BOD_MODE0_LP_INT_CLR_V << LP_ANA_BOD_MODE0_LP_INT_CLR_S) +#define LP_ANA_BOD_MODE0_LP_INT_CLR_V 0x00000001U +#define LP_ANA_BOD_MODE0_LP_INT_CLR_S 31 + +/** LP_ANA_DATE_REG register + * need_des + */ +#define LP_ANA_DATE_REG (DR_REG_LP_AON_BASE + 0x3fc) +/** LP_ANA_LP_ANA_DATE : R/W; bitpos: [30:0]; default: 37765696; + * need_des + */ +#define LP_ANA_LP_ANA_DATE 0x7FFFFFFFU +#define LP_ANA_LP_ANA_DATE_M (LP_ANA_LP_ANA_DATE_V << LP_ANA_LP_ANA_DATE_S) +#define LP_ANA_LP_ANA_DATE_V 0x7FFFFFFFU +#define LP_ANA_LP_ANA_DATE_S 0 +/** LP_ANA_CLK_EN : R/W; bitpos: [31]; default: 0; + * need_des + */ +#define LP_ANA_CLK_EN (BIT(31)) +#define LP_ANA_CLK_EN_M (LP_ANA_CLK_EN_V << LP_ANA_CLK_EN_S) +#define LP_ANA_CLK_EN_V 0x00000001U +#define LP_ANA_CLK_EN_S 31 + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32h21/register/soc/lp_analog_peri_struct.h b/components/soc/esp32h21/register/soc/lp_analog_peri_struct.h new file mode 100644 index 00000000000..668408f504a --- /dev/null +++ b/components/soc/esp32h21/register/soc/lp_analog_peri_struct.h @@ -0,0 +1,420 @@ +/** + * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#ifdef __cplusplus +extern "C" { +#endif + +/** Group: configure_register */ +/** Type of ana_bod_mode0_cntl register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:6; + /** ana_bod_mode0_close_flash_ena : R/W; bitpos: [6]; default: 0; + * need_des + */ + uint32_t ana_bod_mode0_close_flash_ena:1; + /** ana_bod_mode0_pd_rf_ena : R/W; bitpos: [7]; default: 0; + * need_des + */ + uint32_t ana_bod_mode0_pd_rf_ena:1; + /** ana_bod_mode0_intr_wait : R/W; bitpos: [17:8]; default: 1; + * need_des + */ + uint32_t ana_bod_mode0_intr_wait:10; + /** ana_bod_mode0_reset_wait : R/W; bitpos: [27:18]; default: 1023; + * need_des + */ + uint32_t ana_bod_mode0_reset_wait:10; + /** ana_bod_mode0_cnt_clr : R/W; bitpos: [28]; default: 0; + * need_des + */ + uint32_t ana_bod_mode0_cnt_clr:1; + /** ana_bod_mode0_intr_ena : R/W; bitpos: [29]; default: 0; + * need_des + */ + uint32_t ana_bod_mode0_intr_ena:1; + /** ana_bod_mode0_reset_sel : R/W; bitpos: [30]; default: 0; + * need_des + */ + uint32_t ana_bod_mode0_reset_sel:1; + /** ana_bod_mode0_reset_ena : R/W; bitpos: [31]; default: 0; + * need_des + */ + uint32_t ana_bod_mode0_reset_ena:1; + }; + uint32_t val; +} lp_ana_bod_mode0_cntl_reg_t; + +/** Type of ana_bod_mode1_cntl register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:31; + /** ana_bod_mode1_reset_ena : R/W; bitpos: [31]; default: 0; + * need_des + */ + uint32_t ana_bod_mode1_reset_ena:1; + }; + uint32_t val; +} lp_ana_bod_mode1_cntl_reg_t; + +/** Type of ana_vdd_source_cntl register + * need_des + */ +typedef union { + struct { + /** ana_detmode_sel : R/W; bitpos: [7:0]; default: 255; + * need_des + */ + uint32_t ana_detmode_sel:8; + /** ana_vgood_event_record : RO; bitpos: [15:8]; default: 0; + * need_des + */ + uint32_t ana_vgood_event_record:8; + /** ana_vbat_event_record_clr : WT; bitpos: [23:16]; default: 0; + * need_des + */ + uint32_t ana_vbat_event_record_clr:8; + /** ana_bod_source_ena : R/W; bitpos: [31:24]; default: 4; + * need_des + */ + uint32_t ana_bod_source_ena:8; + }; + uint32_t val; +} lp_ana_vdd_source_cntl_reg_t; + +/** Type of ana_vddbat_bod_cntl register + * need_des + */ +typedef union { + struct { + /** ana_vddbat_undervoltage_flag : RO; bitpos: [0]; default: 0; + * need_des + */ + uint32_t ana_vddbat_undervoltage_flag:1; + uint32_t reserved_1:9; + /** ana_vddbat_charger : R/W; bitpos: [10]; default: 0; + * need_des + */ + uint32_t ana_vddbat_charger:1; + /** ana_vddbat_cnt_clr : R/W; bitpos: [11]; default: 0; + * need_des + */ + uint32_t ana_vddbat_cnt_clr:1; + /** ana_vddbat_upvoltage_target : R/W; bitpos: [21:12]; default: 0; + * need_des + */ + uint32_t ana_vddbat_upvoltage_target:10; + /** ana_vddbat_undervoltage_target : R/W; bitpos: [31:22]; default: 1023; + * need_des + */ + uint32_t ana_vddbat_undervoltage_target:10; + }; + uint32_t val; +} lp_ana_vddbat_bod_cntl_reg_t; + +/** Type of ana_vddbat_charge_cntl register + * need_des + */ +typedef union { + struct { + /** ana_vddbat_charge_undervoltage_flag : RO; bitpos: [0]; default: 0; + * need_des + */ + uint32_t ana_vddbat_charge_undervoltage_flag:1; + uint32_t reserved_1:9; + /** ana_vddbat_charge_charger : R/W; bitpos: [10]; default: 0; + * need_des + */ + uint32_t ana_vddbat_charge_charger:1; + /** ana_vddbat_charge_cnt_clr : R/W; bitpos: [11]; default: 0; + * need_des + */ + uint32_t ana_vddbat_charge_cnt_clr:1; + /** ana_vddbat_charge_upvoltage_target : R/W; bitpos: [21:12]; default: 0; + * need_des + */ + uint32_t ana_vddbat_charge_upvoltage_target:10; + /** ana_vddbat_charge_undervoltage_target : R/W; bitpos: [31:22]; default: 1023; + * need_des + */ + uint32_t ana_vddbat_charge_undervoltage_target:10; + }; + uint32_t val; +} lp_ana_vddbat_charge_cntl_reg_t; + +/** Type of ana_ck_glitch_cntl register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:31; + /** ana_ck_glitch_reset_ena : R/W; bitpos: [31]; default: 0; + * need_des + */ + uint32_t ana_ck_glitch_reset_ena:1; + }; + uint32_t val; +} lp_ana_ck_glitch_cntl_reg_t; + +/** Type of ana_pg_glitch_cntl register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:26; + /** ana_power_glitch_reset_ena : R/W; bitpos: [31:26]; default: 0; + * need_des + */ + uint32_t ana_power_glitch_reset_ena:6; + }; + uint32_t val; +} lp_ana_pg_glitch_cntl_reg_t; + +/** Type of ana_fib_enable register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:24; + /** ana_ana_fib_ena : R/W; bitpos: [31:24]; default: 255; + * need_des + */ + uint32_t ana_ana_fib_ena:8; + }; + uint32_t val; +} lp_ana_fib_enable_reg_t; + +/** Type of ana_int_raw register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:27; + /** ana_vddbat_charge_upvoltage_int_raw : R/WTC/SS; bitpos: [27]; default: 0; + * need_des + */ + uint32_t ana_vddbat_charge_upvoltage_int_raw:1; + /** ana_vddbat_charge_undervoltage_int_raw : R/WTC/SS; bitpos: [28]; default: 0; + * need_des + */ + uint32_t ana_vddbat_charge_undervoltage_int_raw:1; + /** ana_vddbat_upvoltage_int_raw : R/WTC/SS; bitpos: [29]; default: 0; + * need_des + */ + uint32_t ana_vddbat_upvoltage_int_raw:1; + /** ana_vddbat_undervoltage_int_raw : R/WTC/SS; bitpos: [30]; default: 0; + * need_des + */ + uint32_t ana_vddbat_undervoltage_int_raw:1; + /** ana_bod_mode0_int_raw : R/WTC/SS; bitpos: [31]; default: 0; + * need_des + */ + uint32_t ana_bod_mode0_int_raw:1; + }; + uint32_t val; +} lp_ana_int_raw_reg_t; + +/** Type of ana_int_st register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:27; + /** ana_vddbat_charge_upvoltage_int_st : RO; bitpos: [27]; default: 0; + * need_des + */ + uint32_t ana_vddbat_charge_upvoltage_int_st:1; + /** ana_vddbat_charge_undervoltage_int_st : RO; bitpos: [28]; default: 0; + * need_des + */ + uint32_t ana_vddbat_charge_undervoltage_int_st:1; + /** ana_vddbat_upvoltage_int_st : RO; bitpos: [29]; default: 0; + * need_des + */ + uint32_t ana_vddbat_upvoltage_int_st:1; + /** ana_vddbat_undervoltage_int_st : RO; bitpos: [30]; default: 0; + * need_des + */ + uint32_t ana_vddbat_undervoltage_int_st:1; + /** ana_bod_mode0_int_st : RO; bitpos: [31]; default: 0; + * need_des + */ + uint32_t ana_bod_mode0_int_st:1; + }; + uint32_t val; +} lp_ana_int_st_reg_t; + +/** Type of ana_int_ena register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:27; + /** ana_vddbat_charge_upvoltage_int_ena : R/W; bitpos: [27]; default: 0; + * need_des + */ + uint32_t ana_vddbat_charge_upvoltage_int_ena:1; + /** ana_vddbat_charge_undervoltage_int_ena : R/W; bitpos: [28]; default: 0; + * need_des + */ + uint32_t ana_vddbat_charge_undervoltage_int_ena:1; + /** ana_vddbat_upvoltage_int_ena : R/W; bitpos: [29]; default: 0; + * need_des + */ + uint32_t ana_vddbat_upvoltage_int_ena:1; + /** ana_vddbat_undervoltage_int_ena : R/W; bitpos: [30]; default: 0; + * need_des + */ + uint32_t ana_vddbat_undervoltage_int_ena:1; + /** ana_bod_mode0_int_ena : R/W; bitpos: [31]; default: 0; + * need_des + */ + uint32_t ana_bod_mode0_int_ena:1; + }; + uint32_t val; +} lp_ana_int_ena_reg_t; + +/** Type of ana_int_clr register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:27; + /** ana_vddbat_charge_upvoltage_int_clr : WT; bitpos: [27]; default: 0; + * need_des + */ + uint32_t ana_vddbat_charge_upvoltage_int_clr:1; + /** ana_vddbat_charge_undervoltage_int_clr : WT; bitpos: [28]; default: 0; + * need_des + */ + uint32_t ana_vddbat_charge_undervoltage_int_clr:1; + /** ana_vddbat_upvoltage_int_clr : WT; bitpos: [29]; default: 0; + * need_des + */ + uint32_t ana_vddbat_upvoltage_int_clr:1; + /** ana_vddbat_undervoltage_int_clr : WT; bitpos: [30]; default: 0; + * need_des + */ + uint32_t ana_vddbat_undervoltage_int_clr:1; + /** ana_bod_mode0_int_clr : WT; bitpos: [31]; default: 0; + * need_des + */ + uint32_t ana_bod_mode0_int_clr:1; + }; + uint32_t val; +} lp_ana_int_clr_reg_t; + +/** Type of ana_lp_int_raw register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:31; + /** ana_bod_mode0_lp_int_raw : R/WTC/SS; bitpos: [31]; default: 0; + * need_des + */ + uint32_t ana_bod_mode0_lp_int_raw:1; + }; + uint32_t val; +} lp_ana_lp_int_raw_reg_t; + +/** Type of ana_lp_int_st register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:31; + /** ana_bod_mode0_lp_int_st : RO; bitpos: [31]; default: 0; + * need_des + */ + uint32_t ana_bod_mode0_lp_int_st:1; + }; + uint32_t val; +} lp_ana_lp_int_st_reg_t; + +/** Type of ana_lp_int_ena register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:31; + /** ana_bod_mode0_lp_int_ena : R/W; bitpos: [31]; default: 0; + * need_des + */ + uint32_t ana_bod_mode0_lp_int_ena:1; + }; + uint32_t val; +} lp_ana_lp_int_ena_reg_t; + +/** Type of ana_lp_int_clr register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:31; + /** ana_bod_mode0_lp_int_clr : WT; bitpos: [31]; default: 0; + * need_des + */ + uint32_t ana_bod_mode0_lp_int_clr:1; + }; + uint32_t val; +} lp_ana_lp_int_clr_reg_t; + +/** Type of ana_date register + * need_des + */ +typedef union { + struct { + /** ana_lp_ana_date : R/W; bitpos: [30:0]; default: 37765696; + * need_des + */ + uint32_t ana_lp_ana_date:31; + /** ana_clk_en : R/W; bitpos: [31]; default: 0; + * need_des + */ + uint32_t ana_clk_en:1; + }; + uint32_t val; +} lp_ana_date_reg_t; + + +typedef struct { + volatile lp_ana_bod_mode0_cntl_reg_t ana_bod_mode0_cntl; + volatile lp_ana_bod_mode1_cntl_reg_t ana_bod_mode1_cntl; + volatile lp_ana_vdd_source_cntl_reg_t ana_vdd_source_cntl; + volatile lp_ana_vddbat_bod_cntl_reg_t ana_vddbat_bod_cntl; + volatile lp_ana_vddbat_charge_cntl_reg_t ana_vddbat_charge_cntl; + volatile lp_ana_ck_glitch_cntl_reg_t ana_ck_glitch_cntl; + volatile lp_ana_pg_glitch_cntl_reg_t ana_pg_glitch_cntl; + volatile lp_ana_fib_enable_reg_t ana_fib_enable; + volatile lp_ana_int_raw_reg_t ana_int_raw; + volatile lp_ana_int_st_reg_t ana_int_st; + volatile lp_ana_int_ena_reg_t ana_int_ena; + volatile lp_ana_int_clr_reg_t ana_int_clr; + volatile lp_ana_lp_int_raw_reg_t ana_lp_int_raw; + volatile lp_ana_lp_int_st_reg_t ana_lp_int_st; + volatile lp_ana_lp_int_ena_reg_t ana_lp_int_ena; + volatile lp_ana_lp_int_clr_reg_t ana_lp_int_clr; + uint32_t reserved_040[239]; + volatile lp_ana_date_reg_t ana_date; +} lp_ana_dev_t; + +extern lp_ana_dev_t LP_ANA_PERI; + +#ifndef __cplusplus +_Static_assert(sizeof(lp_ana_dev_t) == 0x400, "Invalid size of lp_ana_dev_t structure"); +#endif + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32h21/register/soc/lp_aon_reg.h b/components/soc/esp32h21/register/soc/lp_aon_reg.h new file mode 100644 index 00000000000..726e391d7ed --- /dev/null +++ b/components/soc/esp32h21/register/soc/lp_aon_reg.h @@ -0,0 +1,470 @@ +/** + * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#include "soc/soc.h" +#ifdef __cplusplus +extern "C" { +#endif + +/** LP_AON_STORE0_REG register + * need_des + */ +#define LP_AON_STORE0_REG (DR_REG_LP_AON_BASE + 0x0) +/** LP_AON_LP_AON_STORE0 : R/W; bitpos: [31:0]; default: 0; + * need_des + */ +#define LP_AON_LP_AON_STORE0 0xFFFFFFFFU +#define LP_AON_LP_AON_STORE0_M (LP_AON_LP_AON_STORE0_V << LP_AON_LP_AON_STORE0_S) +#define LP_AON_LP_AON_STORE0_V 0xFFFFFFFFU +#define LP_AON_LP_AON_STORE0_S 0 + +/** LP_AON_STORE1_REG register + * need_des + */ +#define LP_AON_STORE1_REG (DR_REG_LP_AON_BASE + 0x4) +/** LP_AON_LP_AON_STORE1 : R/W; bitpos: [31:0]; default: 0; + * need_des + */ +#define LP_AON_LP_AON_STORE1 0xFFFFFFFFU +#define LP_AON_LP_AON_STORE1_M (LP_AON_LP_AON_STORE1_V << LP_AON_LP_AON_STORE1_S) +#define LP_AON_LP_AON_STORE1_V 0xFFFFFFFFU +#define LP_AON_LP_AON_STORE1_S 0 + +/** LP_AON_STORE2_REG register + * need_des + */ +#define LP_AON_STORE2_REG (DR_REG_LP_AON_BASE + 0x8) +/** LP_AON_LP_AON_STORE2 : R/W; bitpos: [31:0]; default: 0; + * need_des + */ +#define LP_AON_LP_AON_STORE2 0xFFFFFFFFU +#define LP_AON_LP_AON_STORE2_M (LP_AON_LP_AON_STORE2_V << LP_AON_LP_AON_STORE2_S) +#define LP_AON_LP_AON_STORE2_V 0xFFFFFFFFU +#define LP_AON_LP_AON_STORE2_S 0 + +/** LP_AON_STORE3_REG register + * need_des + */ +#define LP_AON_STORE3_REG (DR_REG_LP_AON_BASE + 0xc) +/** LP_AON_LP_AON_STORE3 : R/W; bitpos: [31:0]; default: 0; + * need_des + */ +#define LP_AON_LP_AON_STORE3 0xFFFFFFFFU +#define LP_AON_LP_AON_STORE3_M (LP_AON_LP_AON_STORE3_V << LP_AON_LP_AON_STORE3_S) +#define LP_AON_LP_AON_STORE3_V 0xFFFFFFFFU +#define LP_AON_LP_AON_STORE3_S 0 + +/** LP_AON_STORE4_REG register + * need_des + */ +#define LP_AON_STORE4_REG (DR_REG_LP_AON_BASE + 0x10) +/** LP_AON_LP_AON_STORE4 : R/W; bitpos: [31:0]; default: 0; + * need_des + */ +#define LP_AON_LP_AON_STORE4 0xFFFFFFFFU +#define LP_AON_LP_AON_STORE4_M (LP_AON_LP_AON_STORE4_V << LP_AON_LP_AON_STORE4_S) +#define LP_AON_LP_AON_STORE4_V 0xFFFFFFFFU +#define LP_AON_LP_AON_STORE4_S 0 + +/** LP_AON_STORE5_REG register + * need_des + */ +#define LP_AON_STORE5_REG (DR_REG_LP_AON_BASE + 0x14) +/** LP_AON_LP_AON_STORE5 : R/W; bitpos: [31:0]; default: 0; + * need_des + */ +#define LP_AON_LP_AON_STORE5 0xFFFFFFFFU +#define LP_AON_LP_AON_STORE5_M (LP_AON_LP_AON_STORE5_V << LP_AON_LP_AON_STORE5_S) +#define LP_AON_LP_AON_STORE5_V 0xFFFFFFFFU +#define LP_AON_LP_AON_STORE5_S 0 + +/** LP_AON_STORE6_REG register + * need_des + */ +#define LP_AON_STORE6_REG (DR_REG_LP_AON_BASE + 0x18) +/** LP_AON_LP_AON_STORE6 : R/W; bitpos: [31:0]; default: 0; + * need_des + */ +#define LP_AON_LP_AON_STORE6 0xFFFFFFFFU +#define LP_AON_LP_AON_STORE6_M (LP_AON_LP_AON_STORE6_V << LP_AON_LP_AON_STORE6_S) +#define LP_AON_LP_AON_STORE6_V 0xFFFFFFFFU +#define LP_AON_LP_AON_STORE6_S 0 + +/** LP_AON_STORE7_REG register + * need_des + */ +#define LP_AON_STORE7_REG (DR_REG_LP_AON_BASE + 0x1c) +/** LP_AON_LP_AON_STORE7 : R/W; bitpos: [31:0]; default: 0; + * need_des + */ +#define LP_AON_LP_AON_STORE7 0xFFFFFFFFU +#define LP_AON_LP_AON_STORE7_M (LP_AON_LP_AON_STORE7_V << LP_AON_LP_AON_STORE7_S) +#define LP_AON_LP_AON_STORE7_V 0xFFFFFFFFU +#define LP_AON_LP_AON_STORE7_S 0 + +/** LP_AON_STORE8_REG register + * need_des + */ +#define LP_AON_STORE8_REG (DR_REG_LP_AON_BASE + 0x20) +/** LP_AON_LP_AON_STORE8 : R/W; bitpos: [31:0]; default: 0; + * need_des + */ +#define LP_AON_LP_AON_STORE8 0xFFFFFFFFU +#define LP_AON_LP_AON_STORE8_M (LP_AON_LP_AON_STORE8_V << LP_AON_LP_AON_STORE8_S) +#define LP_AON_LP_AON_STORE8_V 0xFFFFFFFFU +#define LP_AON_LP_AON_STORE8_S 0 + +/** LP_AON_STORE9_REG register + * need_des + */ +#define LP_AON_STORE9_REG (DR_REG_LP_AON_BASE + 0x24) +/** LP_AON_LP_AON_STORE9 : R/W; bitpos: [31:0]; default: 0; + * need_des + */ +#define LP_AON_LP_AON_STORE9 0xFFFFFFFFU +#define LP_AON_LP_AON_STORE9_M (LP_AON_LP_AON_STORE9_V << LP_AON_LP_AON_STORE9_S) +#define LP_AON_LP_AON_STORE9_V 0xFFFFFFFFU +#define LP_AON_LP_AON_STORE9_S 0 + +/** LP_AON_GPIO_MUX_REG register + * need_des + */ +#define LP_AON_GPIO_MUX_REG (DR_REG_LP_AON_BASE + 0x28) +/** LP_AON_GPIO_MUX_SEL : R/W; bitpos: [7:0]; default: 0; + * need_des + */ +#define LP_AON_GPIO_MUX_SEL 0x000000FFU +#define LP_AON_GPIO_MUX_SEL_M (LP_AON_GPIO_MUX_SEL_V << LP_AON_GPIO_MUX_SEL_S) +#define LP_AON_GPIO_MUX_SEL_V 0x000000FFU +#define LP_AON_GPIO_MUX_SEL_S 0 + +/** LP_AON_GPIO_HOLD0_REG register + * need_des + */ +#define LP_AON_GPIO_HOLD0_REG (DR_REG_LP_AON_BASE + 0x2c) +/** LP_AON_GPIO_HOLD0 : R/W; bitpos: [31:0]; default: 0; + * need_des + */ +#define LP_AON_GPIO_HOLD0 0xFFFFFFFFU +#define LP_AON_GPIO_HOLD0_M (LP_AON_GPIO_HOLD0_V << LP_AON_GPIO_HOLD0_S) +#define LP_AON_GPIO_HOLD0_V 0xFFFFFFFFU +#define LP_AON_GPIO_HOLD0_S 0 + +/** LP_AON_GPIO_HOLD1_REG register + * need_des + */ +#define LP_AON_GPIO_HOLD1_REG (DR_REG_LP_AON_BASE + 0x30) +/** LP_AON_GPIO_HOLD1 : R/W; bitpos: [31:0]; default: 0; + * need_des + */ +#define LP_AON_GPIO_HOLD1 0xFFFFFFFFU +#define LP_AON_GPIO_HOLD1_M (LP_AON_GPIO_HOLD1_V << LP_AON_GPIO_HOLD1_S) +#define LP_AON_GPIO_HOLD1_V 0xFFFFFFFFU +#define LP_AON_GPIO_HOLD1_S 0 + +/** LP_AON_SYS_CFG_REG register + * need_des + */ +#define LP_AON_SYS_CFG_REG (DR_REG_LP_AON_BASE + 0x34) +/** LP_AON_ANA_FIB_SWD_ENABLE : RO; bitpos: [0]; default: 1; + * need_des + */ +#define LP_AON_ANA_FIB_SWD_ENABLE (BIT(0)) +#define LP_AON_ANA_FIB_SWD_ENABLE_M (LP_AON_ANA_FIB_SWD_ENABLE_V << LP_AON_ANA_FIB_SWD_ENABLE_S) +#define LP_AON_ANA_FIB_SWD_ENABLE_V 0x00000001U +#define LP_AON_ANA_FIB_SWD_ENABLE_S 0 +/** LP_AON_ANA_FIB_CK_GLITCH_ENABLE : RO; bitpos: [1]; default: 1; + * need_des + */ +#define LP_AON_ANA_FIB_CK_GLITCH_ENABLE (BIT(1)) +#define LP_AON_ANA_FIB_CK_GLITCH_ENABLE_M (LP_AON_ANA_FIB_CK_GLITCH_ENABLE_V << LP_AON_ANA_FIB_CK_GLITCH_ENABLE_S) +#define LP_AON_ANA_FIB_CK_GLITCH_ENABLE_V 0x00000001U +#define LP_AON_ANA_FIB_CK_GLITCH_ENABLE_S 1 +/** LP_AON_ANA_FIB_BOD_ENABLE : RO; bitpos: [2]; default: 1; + * need_des + */ +#define LP_AON_ANA_FIB_BOD_ENABLE (BIT(2)) +#define LP_AON_ANA_FIB_BOD_ENABLE_M (LP_AON_ANA_FIB_BOD_ENABLE_V << LP_AON_ANA_FIB_BOD_ENABLE_S) +#define LP_AON_ANA_FIB_BOD_ENABLE_V 0x00000001U +#define LP_AON_ANA_FIB_BOD_ENABLE_S 2 +/** LP_AON_FORCE_DOWNLOAD_BOOT : R/W; bitpos: [30]; default: 0; + * need_des + */ +#define LP_AON_FORCE_DOWNLOAD_BOOT (BIT(30)) +#define LP_AON_FORCE_DOWNLOAD_BOOT_M (LP_AON_FORCE_DOWNLOAD_BOOT_V << LP_AON_FORCE_DOWNLOAD_BOOT_S) +#define LP_AON_FORCE_DOWNLOAD_BOOT_V 0x00000001U +#define LP_AON_FORCE_DOWNLOAD_BOOT_S 30 +/** LP_AON_HPSYS_SW_RESET : WT; bitpos: [31]; default: 0; + * need_des + */ +#define LP_AON_HPSYS_SW_RESET (BIT(31)) +#define LP_AON_HPSYS_SW_RESET_M (LP_AON_HPSYS_SW_RESET_V << LP_AON_HPSYS_SW_RESET_S) +#define LP_AON_HPSYS_SW_RESET_V 0x00000001U +#define LP_AON_HPSYS_SW_RESET_S 31 + +/** LP_AON_CPUCORE0_CFG_REG register + * need_des + */ +#define LP_AON_CPUCORE0_CFG_REG (DR_REG_LP_AON_BASE + 0x38) +/** LP_AON_CPU_CORE0_SW_STALL : R/W; bitpos: [7:0]; default: 0; + * need_des + */ +#define LP_AON_CPU_CORE0_SW_STALL 0x000000FFU +#define LP_AON_CPU_CORE0_SW_STALL_M (LP_AON_CPU_CORE0_SW_STALL_V << LP_AON_CPU_CORE0_SW_STALL_S) +#define LP_AON_CPU_CORE0_SW_STALL_V 0x000000FFU +#define LP_AON_CPU_CORE0_SW_STALL_S 0 +/** LP_AON_CPU_CORE0_SW_RESET : WT; bitpos: [28]; default: 0; + * need_des + */ +#define LP_AON_CPU_CORE0_SW_RESET (BIT(28)) +#define LP_AON_CPU_CORE0_SW_RESET_M (LP_AON_CPU_CORE0_SW_RESET_V << LP_AON_CPU_CORE0_SW_RESET_S) +#define LP_AON_CPU_CORE0_SW_RESET_V 0x00000001U +#define LP_AON_CPU_CORE0_SW_RESET_S 28 +/** LP_AON_CPU_CORE0_OCD_HALT_ON_RESET : R/W; bitpos: [29]; default: 0; + * need_des + */ +#define LP_AON_CPU_CORE0_OCD_HALT_ON_RESET (BIT(29)) +#define LP_AON_CPU_CORE0_OCD_HALT_ON_RESET_M (LP_AON_CPU_CORE0_OCD_HALT_ON_RESET_V << LP_AON_CPU_CORE0_OCD_HALT_ON_RESET_S) +#define LP_AON_CPU_CORE0_OCD_HALT_ON_RESET_V 0x00000001U +#define LP_AON_CPU_CORE0_OCD_HALT_ON_RESET_S 29 +/** LP_AON_CPU_CORE0_STAT_VECTOR_SEL : R/W; bitpos: [30]; default: 1; + * need_des + */ +#define LP_AON_CPU_CORE0_STAT_VECTOR_SEL (BIT(30)) +#define LP_AON_CPU_CORE0_STAT_VECTOR_SEL_M (LP_AON_CPU_CORE0_STAT_VECTOR_SEL_V << LP_AON_CPU_CORE0_STAT_VECTOR_SEL_S) +#define LP_AON_CPU_CORE0_STAT_VECTOR_SEL_V 0x00000001U +#define LP_AON_CPU_CORE0_STAT_VECTOR_SEL_S 30 +/** LP_AON_CPU_CORE0_DRESET_MASK : R/W; bitpos: [31]; default: 0; + * need_des + */ +#define LP_AON_CPU_CORE0_DRESET_MASK (BIT(31)) +#define LP_AON_CPU_CORE0_DRESET_MASK_M (LP_AON_CPU_CORE0_DRESET_MASK_V << LP_AON_CPU_CORE0_DRESET_MASK_S) +#define LP_AON_CPU_CORE0_DRESET_MASK_V 0x00000001U +#define LP_AON_CPU_CORE0_DRESET_MASK_S 31 + +/** LP_AON_IO_MUX_REG register + * need_des + */ +#define LP_AON_IO_MUX_REG (DR_REG_LP_AON_BASE + 0x3c) +/** LP_AON_IO_MUX_PULL_LDO : R/W; bitpos: [30:28]; default: 0; + * need_des + */ +#define LP_AON_IO_MUX_PULL_LDO 0x00000007U +#define LP_AON_IO_MUX_PULL_LDO_M (LP_AON_IO_MUX_PULL_LDO_V << LP_AON_IO_MUX_PULL_LDO_S) +#define LP_AON_IO_MUX_PULL_LDO_V 0x00000007U +#define LP_AON_IO_MUX_PULL_LDO_S 28 +/** LP_AON_IO_MUX_RESET_DISABLE : R/W; bitpos: [31]; default: 0; + * need_des + */ +#define LP_AON_IO_MUX_RESET_DISABLE (BIT(31)) +#define LP_AON_IO_MUX_RESET_DISABLE_M (LP_AON_IO_MUX_RESET_DISABLE_V << LP_AON_IO_MUX_RESET_DISABLE_S) +#define LP_AON_IO_MUX_RESET_DISABLE_V 0x00000001U +#define LP_AON_IO_MUX_RESET_DISABLE_S 31 + +/** LP_AON_EXT_WAKEUP_CNTL_REG register + * need_des + */ +#define LP_AON_EXT_WAKEUP_CNTL_REG (DR_REG_LP_AON_BASE + 0x40) +/** LP_AON_EXT_WAKEUP_STATUS : RO; bitpos: [7:0]; default: 0; + * need_des + */ +#define LP_AON_EXT_WAKEUP_STATUS 0x000000FFU +#define LP_AON_EXT_WAKEUP_STATUS_M (LP_AON_EXT_WAKEUP_STATUS_V << LP_AON_EXT_WAKEUP_STATUS_S) +#define LP_AON_EXT_WAKEUP_STATUS_V 0x000000FFU +#define LP_AON_EXT_WAKEUP_STATUS_S 0 +/** LP_AON_EXT_WAKEUP_STATUS_CLR : WT; bitpos: [14]; default: 0; + * need_des + */ +#define LP_AON_EXT_WAKEUP_STATUS_CLR (BIT(14)) +#define LP_AON_EXT_WAKEUP_STATUS_CLR_M (LP_AON_EXT_WAKEUP_STATUS_CLR_V << LP_AON_EXT_WAKEUP_STATUS_CLR_S) +#define LP_AON_EXT_WAKEUP_STATUS_CLR_V 0x00000001U +#define LP_AON_EXT_WAKEUP_STATUS_CLR_S 14 +/** LP_AON_EXT_WAKEUP_SEL : R/W; bitpos: [22:15]; default: 0; + * need_des + */ +#define LP_AON_EXT_WAKEUP_SEL 0x000000FFU +#define LP_AON_EXT_WAKEUP_SEL_M (LP_AON_EXT_WAKEUP_SEL_V << LP_AON_EXT_WAKEUP_SEL_S) +#define LP_AON_EXT_WAKEUP_SEL_V 0x000000FFU +#define LP_AON_EXT_WAKEUP_SEL_S 15 +/** LP_AON_EXT_WAKEUP_LV : R/W; bitpos: [30:23]; default: 0; + * need_des + */ +#define LP_AON_EXT_WAKEUP_LV 0x000000FFU +#define LP_AON_EXT_WAKEUP_LV_M (LP_AON_EXT_WAKEUP_LV_V << LP_AON_EXT_WAKEUP_LV_S) +#define LP_AON_EXT_WAKEUP_LV_V 0x000000FFU +#define LP_AON_EXT_WAKEUP_LV_S 23 +/** LP_AON_EXT_WAKEUP_FILTER : R/W; bitpos: [31]; default: 0; + * need_des + */ +#define LP_AON_EXT_WAKEUP_FILTER (BIT(31)) +#define LP_AON_EXT_WAKEUP_FILTER_M (LP_AON_EXT_WAKEUP_FILTER_V << LP_AON_EXT_WAKEUP_FILTER_S) +#define LP_AON_EXT_WAKEUP_FILTER_V 0x00000001U +#define LP_AON_EXT_WAKEUP_FILTER_S 31 + +/** LP_AON_USB_REG register + * need_des + */ +#define LP_AON_USB_REG (DR_REG_LP_AON_BASE + 0x44) +/** LP_AON_USB_RESET_DISABLE : R/W; bitpos: [31]; default: 0; + * need_des + */ +#define LP_AON_USB_RESET_DISABLE (BIT(31)) +#define LP_AON_USB_RESET_DISABLE_M (LP_AON_USB_RESET_DISABLE_V << LP_AON_USB_RESET_DISABLE_S) +#define LP_AON_USB_RESET_DISABLE_V 0x00000001U +#define LP_AON_USB_RESET_DISABLE_S 31 + +/** LP_AON_SDIO_ACTIVE_REG register + * need_des + */ +#define LP_AON_SDIO_ACTIVE_REG (DR_REG_LP_AON_BASE + 0x4c) +/** LP_AON_SDIO_ACT_DNUM : R/W; bitpos: [31:22]; default: 10; + * need_des + */ +#define LP_AON_SDIO_ACT_DNUM 0x000003FFU +#define LP_AON_SDIO_ACT_DNUM_M (LP_AON_SDIO_ACT_DNUM_V << LP_AON_SDIO_ACT_DNUM_S) +#define LP_AON_SDIO_ACT_DNUM_V 0x000003FFU +#define LP_AON_SDIO_ACT_DNUM_S 22 + +/** LP_AON_LPCORE_REG register + * need_des + */ +#define LP_AON_LPCORE_REG (DR_REG_LP_AON_BASE + 0x50) +/** LP_AON_LPCORE_ETM_WAKEUP_FLAG_CLR : WT; bitpos: [0]; default: 0; + * need_des + */ +#define LP_AON_LPCORE_ETM_WAKEUP_FLAG_CLR (BIT(0)) +#define LP_AON_LPCORE_ETM_WAKEUP_FLAG_CLR_M (LP_AON_LPCORE_ETM_WAKEUP_FLAG_CLR_V << LP_AON_LPCORE_ETM_WAKEUP_FLAG_CLR_S) +#define LP_AON_LPCORE_ETM_WAKEUP_FLAG_CLR_V 0x00000001U +#define LP_AON_LPCORE_ETM_WAKEUP_FLAG_CLR_S 0 +/** LP_AON_LPCORE_ETM_WAKEUP_FLAG : R/WTC/SS; bitpos: [1]; default: 0; + * need_des + */ +#define LP_AON_LPCORE_ETM_WAKEUP_FLAG (BIT(1)) +#define LP_AON_LPCORE_ETM_WAKEUP_FLAG_M (LP_AON_LPCORE_ETM_WAKEUP_FLAG_V << LP_AON_LPCORE_ETM_WAKEUP_FLAG_S) +#define LP_AON_LPCORE_ETM_WAKEUP_FLAG_V 0x00000001U +#define LP_AON_LPCORE_ETM_WAKEUP_FLAG_S 1 +/** LP_AON_LPCORE_DISABLE : R/W; bitpos: [31]; default: 0; + * need_des + */ +#define LP_AON_LPCORE_DISABLE (BIT(31)) +#define LP_AON_LPCORE_DISABLE_M (LP_AON_LPCORE_DISABLE_V << LP_AON_LPCORE_DISABLE_S) +#define LP_AON_LPCORE_DISABLE_V 0x00000001U +#define LP_AON_LPCORE_DISABLE_S 31 + +/** LP_AON_SAR_CCT_REG register + * need_des + */ +#define LP_AON_SAR_CCT_REG (DR_REG_LP_AON_BASE + 0x54) +/** LP_AON_SAR2_PWDET_CCT : R/W; bitpos: [31:29]; default: 0; + * need_des + */ +#define LP_AON_SAR2_PWDET_CCT 0x00000007U +#define LP_AON_SAR2_PWDET_CCT_M (LP_AON_SAR2_PWDET_CCT_V << LP_AON_SAR2_PWDET_CCT_S) +#define LP_AON_SAR2_PWDET_CCT_V 0x00000007U +#define LP_AON_SAR2_PWDET_CCT_S 29 + +/** LP_AON_JTAG_SEL_REG register + * need_des + */ +#define LP_AON_JTAG_SEL_REG (DR_REG_LP_AON_BASE + 0x58) +/** LP_AON_JTAG_SEL_SOFT : R/W; bitpos: [31]; default: 1; + * If strapping_sel_jtag feature is disabled by efuse, and if neither pad_jtag or + * usb_jtag is disabled by efuse, this field determines which one jtag between + * usb_jtag and pad_jtag will be used. 1'b1(default): usb_jtag, 1'b0: pad_jtag. + */ +#define LP_AON_JTAG_SEL_SOFT (BIT(31)) +#define LP_AON_JTAG_SEL_SOFT_M (LP_AON_JTAG_SEL_SOFT_V << LP_AON_JTAG_SEL_SOFT_S) +#define LP_AON_JTAG_SEL_SOFT_V 0x00000001U +#define LP_AON_JTAG_SEL_SOFT_S 31 + +/** LP_AON_BACKUP_DMA_CFG0_REG register + * configure regdma always on register + */ +#define LP_AON_BACKUP_DMA_CFG0_REG (DR_REG_LP_AON_BASE + 0x70) +/** LP_AON_BURST_LIMIT_AON : R/W; bitpos: [4:0]; default: 10; + * Set this field to configure max value of burst in single transfer. + */ +#define LP_AON_BURST_LIMIT_AON 0x0000001FU +#define LP_AON_BURST_LIMIT_AON_M (LP_AON_BURST_LIMIT_AON_V << LP_AON_BURST_LIMIT_AON_S) +#define LP_AON_BURST_LIMIT_AON_V 0x0000001FU +#define LP_AON_BURST_LIMIT_AON_S 0 +/** LP_AON_READ_INTERVAL_AON : R/W; bitpos: [11:5]; default: 10; + * Set this field to configure read registers' interval time in reading mode. + */ +#define LP_AON_READ_INTERVAL_AON 0x0000007FU +#define LP_AON_READ_INTERVAL_AON_M (LP_AON_READ_INTERVAL_AON_V << LP_AON_READ_INTERVAL_AON_S) +#define LP_AON_READ_INTERVAL_AON_V 0x0000007FU +#define LP_AON_READ_INTERVAL_AON_S 5 +/** LP_AON_BRANCH_LINK_LENGTH_AON : R/W; bitpos: [15:12]; default: 0; + * Set this field to configure link address. + */ +#define LP_AON_BRANCH_LINK_LENGTH_AON 0x0000000FU +#define LP_AON_BRANCH_LINK_LENGTH_AON_M (LP_AON_BRANCH_LINK_LENGTH_AON_V << LP_AON_BRANCH_LINK_LENGTH_AON_S) +#define LP_AON_BRANCH_LINK_LENGTH_AON_V 0x0000000FU +#define LP_AON_BRANCH_LINK_LENGTH_AON_S 12 + +/** LP_AON_BACKUP_DMA_CFG1_REG register + * configure regdma always on register + */ +#define LP_AON_BACKUP_DMA_CFG1_REG (DR_REG_LP_AON_BASE + 0x74) +/** LP_AON_LINK_WAIT_TOUT_THRES_AON : R/W; bitpos: [9:0]; default: 100; + * Set this field to configure the number of consecutive links of link list. + */ +#define LP_AON_LINK_WAIT_TOUT_THRES_AON 0x000003FFU +#define LP_AON_LINK_WAIT_TOUT_THRES_AON_M (LP_AON_LINK_WAIT_TOUT_THRES_AON_V << LP_AON_LINK_WAIT_TOUT_THRES_AON_S) +#define LP_AON_LINK_WAIT_TOUT_THRES_AON_V 0x000003FFU +#define LP_AON_LINK_WAIT_TOUT_THRES_AON_S 0 +/** LP_AON_LINK_WORK_TOUT_THRES_AON : R/W; bitpos: [19:10]; default: 100; + * Set this field to configure maximum waiting time in waiting mode. + */ +#define LP_AON_LINK_WORK_TOUT_THRES_AON 0x000003FFU +#define LP_AON_LINK_WORK_TOUT_THRES_AON_M (LP_AON_LINK_WORK_TOUT_THRES_AON_V << LP_AON_LINK_WORK_TOUT_THRES_AON_S) +#define LP_AON_LINK_WORK_TOUT_THRES_AON_V 0x000003FFU +#define LP_AON_LINK_WORK_TOUT_THRES_AON_S 10 +/** LP_AON_LINK_BACKUP_TOUT_THRES_AON : R/W; bitpos: [29:20]; default: 100; + * Set this field to configure maximum waiting time in backup mode. + */ +#define LP_AON_LINK_BACKUP_TOUT_THRES_AON 0x000003FFU +#define LP_AON_LINK_BACKUP_TOUT_THRES_AON_M (LP_AON_LINK_BACKUP_TOUT_THRES_AON_V << LP_AON_LINK_BACKUP_TOUT_THRES_AON_S) +#define LP_AON_LINK_BACKUP_TOUT_THRES_AON_V 0x000003FFU +#define LP_AON_LINK_BACKUP_TOUT_THRES_AON_S 20 + +/** LP_AON_BACKUP_DMA_CFG2_REG register + * configure regdma always on register + */ +#define LP_AON_BACKUP_DMA_CFG2_REG (DR_REG_LP_AON_BASE + 0x78) +/** LP_AON_LINK_ADDR_AON : R/W; bitpos: [31:0]; default: 0; + * Set this field to configure link address. + */ +#define LP_AON_LINK_ADDR_AON 0xFFFFFFFFU +#define LP_AON_LINK_ADDR_AON_M (LP_AON_LINK_ADDR_AON_V << LP_AON_LINK_ADDR_AON_S) +#define LP_AON_LINK_ADDR_AON_V 0xFFFFFFFFU +#define LP_AON_LINK_ADDR_AON_S 0 + +/** LP_AON_DATE_REG register + * need_des + */ +#define LP_AON_DATE_REG (DR_REG_LP_AON_BASE + 0x3fc) +/** LP_AON_DATE : R/W; bitpos: [30:0]; default: 37781648; + * need_des + */ +#define LP_AON_DATE 0x7FFFFFFFU +#define LP_AON_DATE_M (LP_AON_DATE_V << LP_AON_DATE_S) +#define LP_AON_DATE_V 0x7FFFFFFFU +#define LP_AON_DATE_S 0 +/** LP_AON_CLK_EN : R/W; bitpos: [31]; default: 0; + * need_des + */ +#define LP_AON_CLK_EN (BIT(31)) +#define LP_AON_CLK_EN_M (LP_AON_CLK_EN_V << LP_AON_CLK_EN_S) +#define LP_AON_CLK_EN_V 0x00000001U +#define LP_AON_CLK_EN_S 31 + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32h21/register/soc/lp_aon_struct.h b/components/soc/esp32h21/register/soc/lp_aon_struct.h new file mode 100644 index 00000000000..951d8cfc5d8 --- /dev/null +++ b/components/soc/esp32h21/register/soc/lp_aon_struct.h @@ -0,0 +1,487 @@ +/** + * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#ifdef __cplusplus +extern "C" { +#endif + +/** Group: configure_register */ +/** Type of aon_store0 register + * need_des + */ +typedef union { + struct { + /** aon_lp_aon_store0 : R/W; bitpos: [31:0]; default: 0; + * need_des + */ + uint32_t aon_lp_aon_store0:32; + }; + uint32_t val; +} lp_aon_store0_reg_t; + +/** Type of aon_store1 register + * need_des + */ +typedef union { + struct { + /** aon_lp_aon_store1 : R/W; bitpos: [31:0]; default: 0; + * need_des + */ + uint32_t aon_lp_aon_store1:32; + }; + uint32_t val; +} lp_aon_store1_reg_t; + +/** Type of aon_store2 register + * need_des + */ +typedef union { + struct { + /** aon_lp_aon_store2 : R/W; bitpos: [31:0]; default: 0; + * need_des + */ + uint32_t aon_lp_aon_store2:32; + }; + uint32_t val; +} lp_aon_store2_reg_t; + +/** Type of aon_store3 register + * need_des + */ +typedef union { + struct { + /** aon_lp_aon_store3 : R/W; bitpos: [31:0]; default: 0; + * need_des + */ + uint32_t aon_lp_aon_store3:32; + }; + uint32_t val; +} lp_aon_store3_reg_t; + +/** Type of aon_store4 register + * need_des + */ +typedef union { + struct { + /** aon_lp_aon_store4 : R/W; bitpos: [31:0]; default: 0; + * need_des + */ + uint32_t aon_lp_aon_store4:32; + }; + uint32_t val; +} lp_aon_store4_reg_t; + +/** Type of aon_store5 register + * need_des + */ +typedef union { + struct { + /** aon_lp_aon_store5 : R/W; bitpos: [31:0]; default: 0; + * need_des + */ + uint32_t aon_lp_aon_store5:32; + }; + uint32_t val; +} lp_aon_store5_reg_t; + +/** Type of aon_store6 register + * need_des + */ +typedef union { + struct { + /** aon_lp_aon_store6 : R/W; bitpos: [31:0]; default: 0; + * need_des + */ + uint32_t aon_lp_aon_store6:32; + }; + uint32_t val; +} lp_aon_store6_reg_t; + +/** Type of aon_store7 register + * need_des + */ +typedef union { + struct { + /** aon_lp_aon_store7 : R/W; bitpos: [31:0]; default: 0; + * need_des + */ + uint32_t aon_lp_aon_store7:32; + }; + uint32_t val; +} lp_aon_store7_reg_t; + +/** Type of aon_store8 register + * need_des + */ +typedef union { + struct { + /** aon_lp_aon_store8 : R/W; bitpos: [31:0]; default: 0; + * need_des + */ + uint32_t aon_lp_aon_store8:32; + }; + uint32_t val; +} lp_aon_store8_reg_t; + +/** Type of aon_store9 register + * need_des + */ +typedef union { + struct { + /** aon_lp_aon_store9 : R/W; bitpos: [31:0]; default: 0; + * need_des + */ + uint32_t aon_lp_aon_store9:32; + }; + uint32_t val; +} lp_aon_store9_reg_t; + +/** Type of aon_gpio_mux register + * need_des + */ +typedef union { + struct { + /** aon_gpio_mux_sel : R/W; bitpos: [7:0]; default: 0; + * need_des + */ + uint32_t aon_gpio_mux_sel:8; + uint32_t reserved_8:24; + }; + uint32_t val; +} lp_aon_gpio_mux_reg_t; + +/** Type of aon_gpio_hold0 register + * need_des + */ +typedef union { + struct { + /** gpio_hold0 : R/W; bitpos: [31:0]; default: 0; + * need_des + */ + uint32_t gpio_hold0:32; + }; + uint32_t val; +} lp_aon_gpio_hold0_reg_t; + +/** Type of aon_gpio_hold1 register + * need_des + */ +typedef union { + struct { + /** aon_gpio_hold1 : R/W; bitpos: [31:0]; default: 0; + * need_des + */ + uint32_t aon_gpio_hold1:32; + }; + uint32_t val; +} lp_aon_gpio_hold1_reg_t; + +/** Type of aon_sys_cfg register + * need_des + */ +typedef union { + struct { + /** aon_ana_fib_swd_enable : RO; bitpos: [0]; default: 1; + * need_des + */ + uint32_t aon_ana_fib_swd_enable:1; + /** aon_ana_fib_ck_glitch_enable : RO; bitpos: [1]; default: 1; + * need_des + */ + uint32_t aon_ana_fib_ck_glitch_enable:1; + /** aon_ana_fib_bod_enable : RO; bitpos: [2]; default: 1; + * need_des + */ + uint32_t aon_ana_fib_bod_enable:1; + uint32_t reserved_3:27; + /** aon_force_download_boot : R/W; bitpos: [30]; default: 0; + * need_des + */ + uint32_t aon_force_download_boot:1; + /** aon_hpsys_sw_reset : WT; bitpos: [31]; default: 0; + * need_des + */ + uint32_t aon_hpsys_sw_reset:1; + }; + uint32_t val; +} lp_aon_sys_cfg_reg_t; + +/** Type of aon_cpucore0_cfg register + * need_des + */ +typedef union { + struct { + /** aon_cpu_core0_sw_stall : R/W; bitpos: [7:0]; default: 0; + * need_des + */ + uint32_t aon_cpu_core0_sw_stall:8; + uint32_t reserved_8:20; + /** aon_cpu_core0_sw_reset : WT; bitpos: [28]; default: 0; + * need_des + */ + uint32_t aon_cpu_core0_sw_reset:1; + /** aon_cpu_core0_ocd_halt_on_reset : R/W; bitpos: [29]; default: 0; + * need_des + */ + uint32_t aon_cpu_core0_ocd_halt_on_reset:1; + /** aon_cpu_core0_stat_vector_sel : R/W; bitpos: [30]; default: 1; + * need_des + */ + uint32_t aon_cpu_core0_stat_vector_sel:1; + /** aon_cpu_core0_dreset_mask : R/W; bitpos: [31]; default: 0; + * need_des + */ + uint32_t aon_cpu_core0_dreset_mask:1; + }; + uint32_t val; +} lp_aon_cpucore0_cfg_reg_t; + +/** Type of aon_io_mux register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:28; + /** aon_io_mux_pull_ldo : R/W; bitpos: [30:28]; default: 0; + * need_des + */ + uint32_t aon_io_mux_pull_ldo:3; + /** aon_io_mux_reset_disable : R/W; bitpos: [31]; default: 0; + * need_des + */ + uint32_t aon_io_mux_reset_disable:1; + }; + uint32_t val; +} lp_aon_io_mux_reg_t; + +/** Type of aon_ext_wakeup_cntl register + * need_des + */ +typedef union { + struct { + /** aon_ext_wakeup_status : RO; bitpos: [7:0]; default: 0; + * need_des + */ + uint32_t aon_ext_wakeup_status:8; + uint32_t reserved_8:6; + /** aon_ext_wakeup_status_clr : WT; bitpos: [14]; default: 0; + * need_des + */ + uint32_t aon_ext_wakeup_status_clr:1; + /** aon_ext_wakeup_sel : R/W; bitpos: [22:15]; default: 0; + * need_des + */ + uint32_t aon_ext_wakeup_sel:8; + /** aon_ext_wakeup_lv : R/W; bitpos: [30:23]; default: 0; + * need_des + */ + uint32_t aon_ext_wakeup_lv:8; + /** aon_ext_wakeup_filter : R/W; bitpos: [31]; default: 0; + * need_des + */ + uint32_t aon_ext_wakeup_filter:1; + }; + uint32_t val; +} lp_aon_ext_wakeup_cntl_reg_t; + +/** Type of aon_usb register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:31; + /** aon_usb_reset_disable : R/W; bitpos: [31]; default: 0; + * need_des + */ + uint32_t aon_usb_reset_disable:1; + }; + uint32_t val; +} lp_aon_usb_reg_t; + +/** Type of aon_sdio_active register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:22; + /** aon_sdio_act_dnum : R/W; bitpos: [31:22]; default: 10; + * need_des + */ + uint32_t aon_sdio_act_dnum:10; + }; + uint32_t val; +} lp_aon_sdio_active_reg_t; + +/** Type of aon_lpcore register + * need_des + */ +typedef union { + struct { + /** aon_lpcore_etm_wakeup_flag_clr : WT; bitpos: [0]; default: 0; + * need_des + */ + uint32_t aon_lpcore_etm_wakeup_flag_clr:1; + /** aon_lpcore_etm_wakeup_flag : R/WTC/SS; bitpos: [1]; default: 0; + * need_des + */ + uint32_t aon_lpcore_etm_wakeup_flag:1; + uint32_t reserved_2:29; + /** aon_lpcore_disable : R/W; bitpos: [31]; default: 0; + * need_des + */ + uint32_t aon_lpcore_disable:1; + }; + uint32_t val; +} lp_aon_lpcore_reg_t; + +/** Type of aon_sar_cct register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:29; + /** aon_sar2_pwdet_cct : R/W; bitpos: [31:29]; default: 0; + * need_des + */ + uint32_t aon_sar2_pwdet_cct:3; + }; + uint32_t val; +} lp_aon_sar_cct_reg_t; + +/** Type of aon_jtag_sel register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:31; + /** aon_jtag_sel_soft : R/W; bitpos: [31]; default: 1; + * If strapping_sel_jtag feature is disabled by efuse, and if neither pad_jtag or + * usb_jtag is disabled by efuse, this field determines which one jtag between + * usb_jtag and pad_jtag will be used. 1'b1(default): usb_jtag, 1'b0: pad_jtag. + */ + uint32_t aon_jtag_sel_soft:1; + }; + uint32_t val; +} lp_aon_jtag_sel_reg_t; + +/** Type of aon_backup_dma_cfg0 register + * configure regdma always on register + */ +typedef union { + struct { + /** aon_burst_limit_aon : R/W; bitpos: [4:0]; default: 10; + * Set this field to configure max value of burst in single transfer. + */ + uint32_t aon_burst_limit_aon:5; + /** aon_read_interval_aon : R/W; bitpos: [11:5]; default: 10; + * Set this field to configure read registers' interval time in reading mode. + */ + uint32_t aon_read_interval_aon:7; + /** aon_branch_link_length_aon : R/W; bitpos: [15:12]; default: 0; + * Set this field to configure link address. + */ + uint32_t aon_branch_link_length_aon:4; + uint32_t reserved_16:16; + }; + uint32_t val; +} lp_aon_backup_dma_cfg0_reg_t; + +/** Type of aon_backup_dma_cfg1 register + * configure regdma always on register + */ +typedef union { + struct { + /** aon_link_wait_tout_thres_aon : R/W; bitpos: [9:0]; default: 100; + * Set this field to configure the number of consecutive links of link list. + */ + uint32_t aon_link_wait_tout_thres_aon:10; + /** aon_link_work_tout_thres_aon : R/W; bitpos: [19:10]; default: 100; + * Set this field to configure maximum waiting time in waiting mode. + */ + uint32_t aon_link_work_tout_thres_aon:10; + /** aon_link_backup_tout_thres_aon : R/W; bitpos: [29:20]; default: 100; + * Set this field to configure maximum waiting time in backup mode. + */ + uint32_t aon_link_backup_tout_thres_aon:10; + uint32_t reserved_30:2; + }; + uint32_t val; +} lp_aon_backup_dma_cfg1_reg_t; + +/** Type of aon_backup_dma_cfg2 register + * configure regdma always on register + */ +typedef union { + struct { + /** aon_link_addr_aon : R/W; bitpos: [31:0]; default: 0; + * Set this field to configure link address. + */ + uint32_t aon_link_addr_aon:32; + }; + uint32_t val; +} lp_aon_backup_dma_cfg2_reg_t; + +/** Type of aon_date register + * need_des + */ +typedef union { + struct { + /** aon_date : R/W; bitpos: [30:0]; default: 37781648; + * need_des + */ + uint32_t aon_date:31; + /** aon_clk_en : R/W; bitpos: [31]; default: 0; + * need_des + */ + uint32_t aon_clk_en:1; + }; + uint32_t val; +} lp_aon_date_reg_t; + + +typedef struct { + volatile lp_aon_store0_reg_t store0; + volatile lp_aon_store1_reg_t store1; + volatile lp_aon_store2_reg_t store2; + volatile lp_aon_store3_reg_t store3; + volatile lp_aon_store4_reg_t store4; + volatile lp_aon_store5_reg_t store5; + volatile lp_aon_store6_reg_t store6; + volatile lp_aon_store7_reg_t store7; + volatile lp_aon_store8_reg_t store8; + volatile lp_aon_store9_reg_t store9; + volatile lp_aon_gpio_mux_reg_t gpio_mux; + volatile lp_aon_gpio_hold0_reg_t gpio_hold0; + volatile lp_aon_gpio_hold1_reg_t gpio_hold1; + volatile lp_aon_sys_cfg_reg_t sys_cfg; + volatile lp_aon_cpucore0_cfg_reg_t cpucore0_cfg; + volatile lp_aon_io_mux_reg_t io_mux; + volatile lp_aon_ext_wakeup_cntl_reg_t ext_wakeup_cntl; + volatile lp_aon_usb_reg_t usb; + uint32_t reserved_048; + volatile lp_aon_sdio_active_reg_t sdio_active; + volatile lp_aon_lpcore_reg_t lpcore; + volatile lp_aon_sar_cct_reg_t sar_cct; + volatile lp_aon_jtag_sel_reg_t _jtag_sel; + uint32_t reserved_05c[5]; + volatile lp_aon_backup_dma_cfg0_reg_t backup_dma_cfg0; + volatile lp_aon_backup_dma_cfg1_reg_t backup_dma_cfg1; + volatile lp_aon_backup_dma_cfg2_reg_t backup_dma_cfg2; + uint32_t reserved_07c[224]; + volatile lp_aon_date_reg_t date; +} lp_aon_dev_t; + +extern lp_aon_dev_t LP_AON; + +#ifndef __cplusplus +_Static_assert(sizeof(lp_aon_dev_t) == 0x400, "Invalid size of lp_aon_dev_t structure"); +#endif + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32h21/register/soc/lp_apm0_reg.h b/components/soc/esp32h21/register/soc/lp_apm0_reg.h new file mode 100644 index 00000000000..17220e50a9b --- /dev/null +++ b/components/soc/esp32h21/register/soc/lp_apm0_reg.h @@ -0,0 +1,506 @@ +/** + * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#include "soc/soc.h" +#ifdef __cplusplus +extern "C" { +#endif + +/** LP_APM0_REGION_FILTER_EN_REG register + * Region filter enable register + */ +#define LP_APM0_REGION_FILTER_EN_REG (DR_REG_LP_BASE + 0x0) +/** LP_APM0_REGION_FILTER_EN : R/W; bitpos: [3:0]; default: 1; + * Region filter enable + */ +#define LP_APM0_REGION_FILTER_EN 0x0000000FU +#define LP_APM0_REGION_FILTER_EN_M (LP_APM0_REGION_FILTER_EN_V << LP_APM0_REGION_FILTER_EN_S) +#define LP_APM0_REGION_FILTER_EN_V 0x0000000FU +#define LP_APM0_REGION_FILTER_EN_S 0 + +/** LP_APM0_REGION0_ADDR_START_REG register + * Region address register + */ +#define LP_APM0_REGION0_ADDR_START_REG (DR_REG_LP_BASE + 0x4) +/** LP_APM0_REGION0_ADDR_START : R/W; bitpos: [31:0]; default: 0; + * Start address of region0 + */ +#define LP_APM0_REGION0_ADDR_START 0xFFFFFFFFU +#define LP_APM0_REGION0_ADDR_START_M (LP_APM0_REGION0_ADDR_START_V << LP_APM0_REGION0_ADDR_START_S) +#define LP_APM0_REGION0_ADDR_START_V 0xFFFFFFFFU +#define LP_APM0_REGION0_ADDR_START_S 0 + +/** LP_APM0_REGION0_ADDR_END_REG register + * Region address register + */ +#define LP_APM0_REGION0_ADDR_END_REG (DR_REG_LP_BASE + 0x8) +/** LP_APM0_REGION0_ADDR_END : R/W; bitpos: [31:0]; default: 4294967295; + * End address of region0 + */ +#define LP_APM0_REGION0_ADDR_END 0xFFFFFFFFU +#define LP_APM0_REGION0_ADDR_END_M (LP_APM0_REGION0_ADDR_END_V << LP_APM0_REGION0_ADDR_END_S) +#define LP_APM0_REGION0_ADDR_END_V 0xFFFFFFFFU +#define LP_APM0_REGION0_ADDR_END_S 0 + +/** LP_APM0_REGION0_PMS_ATTR_REG register + * Region access authority attribute register + */ +#define LP_APM0_REGION0_PMS_ATTR_REG (DR_REG_LP_BASE + 0xc) +/** LP_APM0_REGION0_R0_PMS_X : R/W; bitpos: [0]; default: 0; + * Region execute authority in REE_MODE0 + */ +#define LP_APM0_REGION0_R0_PMS_X (BIT(0)) +#define LP_APM0_REGION0_R0_PMS_X_M (LP_APM0_REGION0_R0_PMS_X_V << LP_APM0_REGION0_R0_PMS_X_S) +#define LP_APM0_REGION0_R0_PMS_X_V 0x00000001U +#define LP_APM0_REGION0_R0_PMS_X_S 0 +/** LP_APM0_REGION0_R0_PMS_W : R/W; bitpos: [1]; default: 0; + * Region write authority in REE_MODE0 + */ +#define LP_APM0_REGION0_R0_PMS_W (BIT(1)) +#define LP_APM0_REGION0_R0_PMS_W_M (LP_APM0_REGION0_R0_PMS_W_V << LP_APM0_REGION0_R0_PMS_W_S) +#define LP_APM0_REGION0_R0_PMS_W_V 0x00000001U +#define LP_APM0_REGION0_R0_PMS_W_S 1 +/** LP_APM0_REGION0_R0_PMS_R : R/W; bitpos: [2]; default: 0; + * Region read authority in REE_MODE0 + */ +#define LP_APM0_REGION0_R0_PMS_R (BIT(2)) +#define LP_APM0_REGION0_R0_PMS_R_M (LP_APM0_REGION0_R0_PMS_R_V << LP_APM0_REGION0_R0_PMS_R_S) +#define LP_APM0_REGION0_R0_PMS_R_V 0x00000001U +#define LP_APM0_REGION0_R0_PMS_R_S 2 +/** LP_APM0_REGION0_R1_PMS_X : R/W; bitpos: [4]; default: 0; + * Region execute authority in REE_MODE1 + */ +#define LP_APM0_REGION0_R1_PMS_X (BIT(4)) +#define LP_APM0_REGION0_R1_PMS_X_M (LP_APM0_REGION0_R1_PMS_X_V << LP_APM0_REGION0_R1_PMS_X_S) +#define LP_APM0_REGION0_R1_PMS_X_V 0x00000001U +#define LP_APM0_REGION0_R1_PMS_X_S 4 +/** LP_APM0_REGION0_R1_PMS_W : R/W; bitpos: [5]; default: 0; + * Region write authority in REE_MODE1 + */ +#define LP_APM0_REGION0_R1_PMS_W (BIT(5)) +#define LP_APM0_REGION0_R1_PMS_W_M (LP_APM0_REGION0_R1_PMS_W_V << LP_APM0_REGION0_R1_PMS_W_S) +#define LP_APM0_REGION0_R1_PMS_W_V 0x00000001U +#define LP_APM0_REGION0_R1_PMS_W_S 5 +/** LP_APM0_REGION0_R1_PMS_R : R/W; bitpos: [6]; default: 0; + * Region read authority in REE_MODE1 + */ +#define LP_APM0_REGION0_R1_PMS_R (BIT(6)) +#define LP_APM0_REGION0_R1_PMS_R_M (LP_APM0_REGION0_R1_PMS_R_V << LP_APM0_REGION0_R1_PMS_R_S) +#define LP_APM0_REGION0_R1_PMS_R_V 0x00000001U +#define LP_APM0_REGION0_R1_PMS_R_S 6 +/** LP_APM0_REGION0_R2_PMS_X : R/W; bitpos: [8]; default: 0; + * Region execute authority in REE_MODE2 + */ +#define LP_APM0_REGION0_R2_PMS_X (BIT(8)) +#define LP_APM0_REGION0_R2_PMS_X_M (LP_APM0_REGION0_R2_PMS_X_V << LP_APM0_REGION0_R2_PMS_X_S) +#define LP_APM0_REGION0_R2_PMS_X_V 0x00000001U +#define LP_APM0_REGION0_R2_PMS_X_S 8 +/** LP_APM0_REGION0_R2_PMS_W : R/W; bitpos: [9]; default: 0; + * Region write authority in REE_MODE2 + */ +#define LP_APM0_REGION0_R2_PMS_W (BIT(9)) +#define LP_APM0_REGION0_R2_PMS_W_M (LP_APM0_REGION0_R2_PMS_W_V << LP_APM0_REGION0_R2_PMS_W_S) +#define LP_APM0_REGION0_R2_PMS_W_V 0x00000001U +#define LP_APM0_REGION0_R2_PMS_W_S 9 +/** LP_APM0_REGION0_R2_PMS_R : R/W; bitpos: [10]; default: 0; + * Region read authority in REE_MODE2 + */ +#define LP_APM0_REGION0_R2_PMS_R (BIT(10)) +#define LP_APM0_REGION0_R2_PMS_R_M (LP_APM0_REGION0_R2_PMS_R_V << LP_APM0_REGION0_R2_PMS_R_S) +#define LP_APM0_REGION0_R2_PMS_R_V 0x00000001U +#define LP_APM0_REGION0_R2_PMS_R_S 10 + +/** LP_APM0_REGION1_ADDR_START_REG register + * Region address register + */ +#define LP_APM0_REGION1_ADDR_START_REG (DR_REG_LP_BASE + 0x10) +/** LP_APM0_REGION1_ADDR_START : R/W; bitpos: [31:0]; default: 0; + * Start address of region1 + */ +#define LP_APM0_REGION1_ADDR_START 0xFFFFFFFFU +#define LP_APM0_REGION1_ADDR_START_M (LP_APM0_REGION1_ADDR_START_V << LP_APM0_REGION1_ADDR_START_S) +#define LP_APM0_REGION1_ADDR_START_V 0xFFFFFFFFU +#define LP_APM0_REGION1_ADDR_START_S 0 + +/** LP_APM0_REGION1_ADDR_END_REG register + * Region address register + */ +#define LP_APM0_REGION1_ADDR_END_REG (DR_REG_LP_BASE + 0x14) +/** LP_APM0_REGION1_ADDR_END : R/W; bitpos: [31:0]; default: 4294967295; + * End address of region1 + */ +#define LP_APM0_REGION1_ADDR_END 0xFFFFFFFFU +#define LP_APM0_REGION1_ADDR_END_M (LP_APM0_REGION1_ADDR_END_V << LP_APM0_REGION1_ADDR_END_S) +#define LP_APM0_REGION1_ADDR_END_V 0xFFFFFFFFU +#define LP_APM0_REGION1_ADDR_END_S 0 + +/** LP_APM0_REGION1_PMS_ATTR_REG register + * Region access authority attribute register + */ +#define LP_APM0_REGION1_PMS_ATTR_REG (DR_REG_LP_BASE + 0x18) +/** LP_APM0_REGION1_R0_PMS_X : R/W; bitpos: [0]; default: 0; + * Region execute authority in REE_MODE0 + */ +#define LP_APM0_REGION1_R0_PMS_X (BIT(0)) +#define LP_APM0_REGION1_R0_PMS_X_M (LP_APM0_REGION1_R0_PMS_X_V << LP_APM0_REGION1_R0_PMS_X_S) +#define LP_APM0_REGION1_R0_PMS_X_V 0x00000001U +#define LP_APM0_REGION1_R0_PMS_X_S 0 +/** LP_APM0_REGION1_R0_PMS_W : R/W; bitpos: [1]; default: 0; + * Region write authority in REE_MODE0 + */ +#define LP_APM0_REGION1_R0_PMS_W (BIT(1)) +#define LP_APM0_REGION1_R0_PMS_W_M (LP_APM0_REGION1_R0_PMS_W_V << LP_APM0_REGION1_R0_PMS_W_S) +#define LP_APM0_REGION1_R0_PMS_W_V 0x00000001U +#define LP_APM0_REGION1_R0_PMS_W_S 1 +/** LP_APM0_REGION1_R0_PMS_R : R/W; bitpos: [2]; default: 0; + * Region read authority in REE_MODE0 + */ +#define LP_APM0_REGION1_R0_PMS_R (BIT(2)) +#define LP_APM0_REGION1_R0_PMS_R_M (LP_APM0_REGION1_R0_PMS_R_V << LP_APM0_REGION1_R0_PMS_R_S) +#define LP_APM0_REGION1_R0_PMS_R_V 0x00000001U +#define LP_APM0_REGION1_R0_PMS_R_S 2 +/** LP_APM0_REGION1_R1_PMS_X : R/W; bitpos: [4]; default: 0; + * Region execute authority in REE_MODE1 + */ +#define LP_APM0_REGION1_R1_PMS_X (BIT(4)) +#define LP_APM0_REGION1_R1_PMS_X_M (LP_APM0_REGION1_R1_PMS_X_V << LP_APM0_REGION1_R1_PMS_X_S) +#define LP_APM0_REGION1_R1_PMS_X_V 0x00000001U +#define LP_APM0_REGION1_R1_PMS_X_S 4 +/** LP_APM0_REGION1_R1_PMS_W : R/W; bitpos: [5]; default: 0; + * Region write authority in REE_MODE1 + */ +#define LP_APM0_REGION1_R1_PMS_W (BIT(5)) +#define LP_APM0_REGION1_R1_PMS_W_M (LP_APM0_REGION1_R1_PMS_W_V << LP_APM0_REGION1_R1_PMS_W_S) +#define LP_APM0_REGION1_R1_PMS_W_V 0x00000001U +#define LP_APM0_REGION1_R1_PMS_W_S 5 +/** LP_APM0_REGION1_R1_PMS_R : R/W; bitpos: [6]; default: 0; + * Region read authority in REE_MODE1 + */ +#define LP_APM0_REGION1_R1_PMS_R (BIT(6)) +#define LP_APM0_REGION1_R1_PMS_R_M (LP_APM0_REGION1_R1_PMS_R_V << LP_APM0_REGION1_R1_PMS_R_S) +#define LP_APM0_REGION1_R1_PMS_R_V 0x00000001U +#define LP_APM0_REGION1_R1_PMS_R_S 6 +/** LP_APM0_REGION1_R2_PMS_X : R/W; bitpos: [8]; default: 0; + * Region execute authority in REE_MODE2 + */ +#define LP_APM0_REGION1_R2_PMS_X (BIT(8)) +#define LP_APM0_REGION1_R2_PMS_X_M (LP_APM0_REGION1_R2_PMS_X_V << LP_APM0_REGION1_R2_PMS_X_S) +#define LP_APM0_REGION1_R2_PMS_X_V 0x00000001U +#define LP_APM0_REGION1_R2_PMS_X_S 8 +/** LP_APM0_REGION1_R2_PMS_W : R/W; bitpos: [9]; default: 0; + * Region write authority in REE_MODE2 + */ +#define LP_APM0_REGION1_R2_PMS_W (BIT(9)) +#define LP_APM0_REGION1_R2_PMS_W_M (LP_APM0_REGION1_R2_PMS_W_V << LP_APM0_REGION1_R2_PMS_W_S) +#define LP_APM0_REGION1_R2_PMS_W_V 0x00000001U +#define LP_APM0_REGION1_R2_PMS_W_S 9 +/** LP_APM0_REGION1_R2_PMS_R : R/W; bitpos: [10]; default: 0; + * Region read authority in REE_MODE2 + */ +#define LP_APM0_REGION1_R2_PMS_R (BIT(10)) +#define LP_APM0_REGION1_R2_PMS_R_M (LP_APM0_REGION1_R2_PMS_R_V << LP_APM0_REGION1_R2_PMS_R_S) +#define LP_APM0_REGION1_R2_PMS_R_V 0x00000001U +#define LP_APM0_REGION1_R2_PMS_R_S 10 + +/** LP_APM0_REGION2_ADDR_START_REG register + * Region address register + */ +#define LP_APM0_REGION2_ADDR_START_REG (DR_REG_LP_BASE + 0x1c) +/** LP_APM0_REGION2_ADDR_START : R/W; bitpos: [31:0]; default: 0; + * Start address of region2 + */ +#define LP_APM0_REGION2_ADDR_START 0xFFFFFFFFU +#define LP_APM0_REGION2_ADDR_START_M (LP_APM0_REGION2_ADDR_START_V << LP_APM0_REGION2_ADDR_START_S) +#define LP_APM0_REGION2_ADDR_START_V 0xFFFFFFFFU +#define LP_APM0_REGION2_ADDR_START_S 0 + +/** LP_APM0_REGION2_ADDR_END_REG register + * Region address register + */ +#define LP_APM0_REGION2_ADDR_END_REG (DR_REG_LP_BASE + 0x20) +/** LP_APM0_REGION2_ADDR_END : R/W; bitpos: [31:0]; default: 4294967295; + * End address of region2 + */ +#define LP_APM0_REGION2_ADDR_END 0xFFFFFFFFU +#define LP_APM0_REGION2_ADDR_END_M (LP_APM0_REGION2_ADDR_END_V << LP_APM0_REGION2_ADDR_END_S) +#define LP_APM0_REGION2_ADDR_END_V 0xFFFFFFFFU +#define LP_APM0_REGION2_ADDR_END_S 0 + +/** LP_APM0_REGION2_PMS_ATTR_REG register + * Region access authority attribute register + */ +#define LP_APM0_REGION2_PMS_ATTR_REG (DR_REG_LP_BASE + 0x24) +/** LP_APM0_REGION2_R0_PMS_X : R/W; bitpos: [0]; default: 0; + * Region execute authority in REE_MODE0 + */ +#define LP_APM0_REGION2_R0_PMS_X (BIT(0)) +#define LP_APM0_REGION2_R0_PMS_X_M (LP_APM0_REGION2_R0_PMS_X_V << LP_APM0_REGION2_R0_PMS_X_S) +#define LP_APM0_REGION2_R0_PMS_X_V 0x00000001U +#define LP_APM0_REGION2_R0_PMS_X_S 0 +/** LP_APM0_REGION2_R0_PMS_W : R/W; bitpos: [1]; default: 0; + * Region write authority in REE_MODE0 + */ +#define LP_APM0_REGION2_R0_PMS_W (BIT(1)) +#define LP_APM0_REGION2_R0_PMS_W_M (LP_APM0_REGION2_R0_PMS_W_V << LP_APM0_REGION2_R0_PMS_W_S) +#define LP_APM0_REGION2_R0_PMS_W_V 0x00000001U +#define LP_APM0_REGION2_R0_PMS_W_S 1 +/** LP_APM0_REGION2_R0_PMS_R : R/W; bitpos: [2]; default: 0; + * Region read authority in REE_MODE0 + */ +#define LP_APM0_REGION2_R0_PMS_R (BIT(2)) +#define LP_APM0_REGION2_R0_PMS_R_M (LP_APM0_REGION2_R0_PMS_R_V << LP_APM0_REGION2_R0_PMS_R_S) +#define LP_APM0_REGION2_R0_PMS_R_V 0x00000001U +#define LP_APM0_REGION2_R0_PMS_R_S 2 +/** LP_APM0_REGION2_R1_PMS_X : R/W; bitpos: [4]; default: 0; + * Region execute authority in REE_MODE1 + */ +#define LP_APM0_REGION2_R1_PMS_X (BIT(4)) +#define LP_APM0_REGION2_R1_PMS_X_M (LP_APM0_REGION2_R1_PMS_X_V << LP_APM0_REGION2_R1_PMS_X_S) +#define LP_APM0_REGION2_R1_PMS_X_V 0x00000001U +#define LP_APM0_REGION2_R1_PMS_X_S 4 +/** LP_APM0_REGION2_R1_PMS_W : R/W; bitpos: [5]; default: 0; + * Region write authority in REE_MODE1 + */ +#define LP_APM0_REGION2_R1_PMS_W (BIT(5)) +#define LP_APM0_REGION2_R1_PMS_W_M (LP_APM0_REGION2_R1_PMS_W_V << LP_APM0_REGION2_R1_PMS_W_S) +#define LP_APM0_REGION2_R1_PMS_W_V 0x00000001U +#define LP_APM0_REGION2_R1_PMS_W_S 5 +/** LP_APM0_REGION2_R1_PMS_R : R/W; bitpos: [6]; default: 0; + * Region read authority in REE_MODE1 + */ +#define LP_APM0_REGION2_R1_PMS_R (BIT(6)) +#define LP_APM0_REGION2_R1_PMS_R_M (LP_APM0_REGION2_R1_PMS_R_V << LP_APM0_REGION2_R1_PMS_R_S) +#define LP_APM0_REGION2_R1_PMS_R_V 0x00000001U +#define LP_APM0_REGION2_R1_PMS_R_S 6 +/** LP_APM0_REGION2_R2_PMS_X : R/W; bitpos: [8]; default: 0; + * Region execute authority in REE_MODE2 + */ +#define LP_APM0_REGION2_R2_PMS_X (BIT(8)) +#define LP_APM0_REGION2_R2_PMS_X_M (LP_APM0_REGION2_R2_PMS_X_V << LP_APM0_REGION2_R2_PMS_X_S) +#define LP_APM0_REGION2_R2_PMS_X_V 0x00000001U +#define LP_APM0_REGION2_R2_PMS_X_S 8 +/** LP_APM0_REGION2_R2_PMS_W : R/W; bitpos: [9]; default: 0; + * Region write authority in REE_MODE2 + */ +#define LP_APM0_REGION2_R2_PMS_W (BIT(9)) +#define LP_APM0_REGION2_R2_PMS_W_M (LP_APM0_REGION2_R2_PMS_W_V << LP_APM0_REGION2_R2_PMS_W_S) +#define LP_APM0_REGION2_R2_PMS_W_V 0x00000001U +#define LP_APM0_REGION2_R2_PMS_W_S 9 +/** LP_APM0_REGION2_R2_PMS_R : R/W; bitpos: [10]; default: 0; + * Region read authority in REE_MODE2 + */ +#define LP_APM0_REGION2_R2_PMS_R (BIT(10)) +#define LP_APM0_REGION2_R2_PMS_R_M (LP_APM0_REGION2_R2_PMS_R_V << LP_APM0_REGION2_R2_PMS_R_S) +#define LP_APM0_REGION2_R2_PMS_R_V 0x00000001U +#define LP_APM0_REGION2_R2_PMS_R_S 10 + +/** LP_APM0_REGION3_ADDR_START_REG register + * Region address register + */ +#define LP_APM0_REGION3_ADDR_START_REG (DR_REG_LP_BASE + 0x28) +/** LP_APM0_REGION3_ADDR_START : R/W; bitpos: [31:0]; default: 0; + * Start address of region3 + */ +#define LP_APM0_REGION3_ADDR_START 0xFFFFFFFFU +#define LP_APM0_REGION3_ADDR_START_M (LP_APM0_REGION3_ADDR_START_V << LP_APM0_REGION3_ADDR_START_S) +#define LP_APM0_REGION3_ADDR_START_V 0xFFFFFFFFU +#define LP_APM0_REGION3_ADDR_START_S 0 + +/** LP_APM0_REGION3_ADDR_END_REG register + * Region address register + */ +#define LP_APM0_REGION3_ADDR_END_REG (DR_REG_LP_BASE + 0x2c) +/** LP_APM0_REGION3_ADDR_END : R/W; bitpos: [31:0]; default: 4294967295; + * End address of region3 + */ +#define LP_APM0_REGION3_ADDR_END 0xFFFFFFFFU +#define LP_APM0_REGION3_ADDR_END_M (LP_APM0_REGION3_ADDR_END_V << LP_APM0_REGION3_ADDR_END_S) +#define LP_APM0_REGION3_ADDR_END_V 0xFFFFFFFFU +#define LP_APM0_REGION3_ADDR_END_S 0 + +/** LP_APM0_REGION3_PMS_ATTR_REG register + * Region access authority attribute register + */ +#define LP_APM0_REGION3_PMS_ATTR_REG (DR_REG_LP_BASE + 0x30) +/** LP_APM0_REGION3_R0_PMS_X : R/W; bitpos: [0]; default: 0; + * Region execute authority in REE_MODE0 + */ +#define LP_APM0_REGION3_R0_PMS_X (BIT(0)) +#define LP_APM0_REGION3_R0_PMS_X_M (LP_APM0_REGION3_R0_PMS_X_V << LP_APM0_REGION3_R0_PMS_X_S) +#define LP_APM0_REGION3_R0_PMS_X_V 0x00000001U +#define LP_APM0_REGION3_R0_PMS_X_S 0 +/** LP_APM0_REGION3_R0_PMS_W : R/W; bitpos: [1]; default: 0; + * Region write authority in REE_MODE0 + */ +#define LP_APM0_REGION3_R0_PMS_W (BIT(1)) +#define LP_APM0_REGION3_R0_PMS_W_M (LP_APM0_REGION3_R0_PMS_W_V << LP_APM0_REGION3_R0_PMS_W_S) +#define LP_APM0_REGION3_R0_PMS_W_V 0x00000001U +#define LP_APM0_REGION3_R0_PMS_W_S 1 +/** LP_APM0_REGION3_R0_PMS_R : R/W; bitpos: [2]; default: 0; + * Region read authority in REE_MODE0 + */ +#define LP_APM0_REGION3_R0_PMS_R (BIT(2)) +#define LP_APM0_REGION3_R0_PMS_R_M (LP_APM0_REGION3_R0_PMS_R_V << LP_APM0_REGION3_R0_PMS_R_S) +#define LP_APM0_REGION3_R0_PMS_R_V 0x00000001U +#define LP_APM0_REGION3_R0_PMS_R_S 2 +/** LP_APM0_REGION3_R1_PMS_X : R/W; bitpos: [4]; default: 0; + * Region execute authority in REE_MODE1 + */ +#define LP_APM0_REGION3_R1_PMS_X (BIT(4)) +#define LP_APM0_REGION3_R1_PMS_X_M (LP_APM0_REGION3_R1_PMS_X_V << LP_APM0_REGION3_R1_PMS_X_S) +#define LP_APM0_REGION3_R1_PMS_X_V 0x00000001U +#define LP_APM0_REGION3_R1_PMS_X_S 4 +/** LP_APM0_REGION3_R1_PMS_W : R/W; bitpos: [5]; default: 0; + * Region write authority in REE_MODE1 + */ +#define LP_APM0_REGION3_R1_PMS_W (BIT(5)) +#define LP_APM0_REGION3_R1_PMS_W_M (LP_APM0_REGION3_R1_PMS_W_V << LP_APM0_REGION3_R1_PMS_W_S) +#define LP_APM0_REGION3_R1_PMS_W_V 0x00000001U +#define LP_APM0_REGION3_R1_PMS_W_S 5 +/** LP_APM0_REGION3_R1_PMS_R : R/W; bitpos: [6]; default: 0; + * Region read authority in REE_MODE1 + */ +#define LP_APM0_REGION3_R1_PMS_R (BIT(6)) +#define LP_APM0_REGION3_R1_PMS_R_M (LP_APM0_REGION3_R1_PMS_R_V << LP_APM0_REGION3_R1_PMS_R_S) +#define LP_APM0_REGION3_R1_PMS_R_V 0x00000001U +#define LP_APM0_REGION3_R1_PMS_R_S 6 +/** LP_APM0_REGION3_R2_PMS_X : R/W; bitpos: [8]; default: 0; + * Region execute authority in REE_MODE2 + */ +#define LP_APM0_REGION3_R2_PMS_X (BIT(8)) +#define LP_APM0_REGION3_R2_PMS_X_M (LP_APM0_REGION3_R2_PMS_X_V << LP_APM0_REGION3_R2_PMS_X_S) +#define LP_APM0_REGION3_R2_PMS_X_V 0x00000001U +#define LP_APM0_REGION3_R2_PMS_X_S 8 +/** LP_APM0_REGION3_R2_PMS_W : R/W; bitpos: [9]; default: 0; + * Region write authority in REE_MODE2 + */ +#define LP_APM0_REGION3_R2_PMS_W (BIT(9)) +#define LP_APM0_REGION3_R2_PMS_W_M (LP_APM0_REGION3_R2_PMS_W_V << LP_APM0_REGION3_R2_PMS_W_S) +#define LP_APM0_REGION3_R2_PMS_W_V 0x00000001U +#define LP_APM0_REGION3_R2_PMS_W_S 9 +/** LP_APM0_REGION3_R2_PMS_R : R/W; bitpos: [10]; default: 0; + * Region read authority in REE_MODE2 + */ +#define LP_APM0_REGION3_R2_PMS_R (BIT(10)) +#define LP_APM0_REGION3_R2_PMS_R_M (LP_APM0_REGION3_R2_PMS_R_V << LP_APM0_REGION3_R2_PMS_R_S) +#define LP_APM0_REGION3_R2_PMS_R_V 0x00000001U +#define LP_APM0_REGION3_R2_PMS_R_S 10 + +/** LP_APM0_FUNC_CTRL_REG register + * PMS function control register + */ +#define LP_APM0_FUNC_CTRL_REG (DR_REG_LP_BASE + 0xc4) +/** LP_APM0_M0_PMS_FUNC_EN : R/W; bitpos: [0]; default: 1; + * PMS M0 function enable + */ +#define LP_APM0_M0_PMS_FUNC_EN (BIT(0)) +#define LP_APM0_M0_PMS_FUNC_EN_M (LP_APM0_M0_PMS_FUNC_EN_V << LP_APM0_M0_PMS_FUNC_EN_S) +#define LP_APM0_M0_PMS_FUNC_EN_V 0x00000001U +#define LP_APM0_M0_PMS_FUNC_EN_S 0 + +/** LP_APM0_M0_STATUS_REG register + * M0 status register + */ +#define LP_APM0_M0_STATUS_REG (DR_REG_LP_BASE + 0xc8) +/** LP_APM0_M0_EXCEPTION_STATUS : RO; bitpos: [1:0]; default: 0; + * Exception status + */ +#define LP_APM0_M0_EXCEPTION_STATUS 0x00000003U +#define LP_APM0_M0_EXCEPTION_STATUS_M (LP_APM0_M0_EXCEPTION_STATUS_V << LP_APM0_M0_EXCEPTION_STATUS_S) +#define LP_APM0_M0_EXCEPTION_STATUS_V 0x00000003U +#define LP_APM0_M0_EXCEPTION_STATUS_S 0 + +/** LP_APM0_M0_STATUS_CLR_REG register + * M0 status clear register + */ +#define LP_APM0_M0_STATUS_CLR_REG (DR_REG_LP_BASE + 0xcc) +/** LP_APM0_M0_REGION_STATUS_CLR : WT; bitpos: [0]; default: 0; + * Clear exception status + */ +#define LP_APM0_M0_REGION_STATUS_CLR (BIT(0)) +#define LP_APM0_M0_REGION_STATUS_CLR_M (LP_APM0_M0_REGION_STATUS_CLR_V << LP_APM0_M0_REGION_STATUS_CLR_S) +#define LP_APM0_M0_REGION_STATUS_CLR_V 0x00000001U +#define LP_APM0_M0_REGION_STATUS_CLR_S 0 + +/** LP_APM0_M0_EXCEPTION_INFO0_REG register + * M0 exception_info0 register + */ +#define LP_APM0_M0_EXCEPTION_INFO0_REG (DR_REG_LP_BASE + 0xd0) +/** LP_APM0_M0_EXCEPTION_REGION : RO; bitpos: [3:0]; default: 0; + * Exception region + */ +#define LP_APM0_M0_EXCEPTION_REGION 0x0000000FU +#define LP_APM0_M0_EXCEPTION_REGION_M (LP_APM0_M0_EXCEPTION_REGION_V << LP_APM0_M0_EXCEPTION_REGION_S) +#define LP_APM0_M0_EXCEPTION_REGION_V 0x0000000FU +#define LP_APM0_M0_EXCEPTION_REGION_S 0 +/** LP_APM0_M0_EXCEPTION_MODE : RO; bitpos: [17:16]; default: 0; + * Exception mode + */ +#define LP_APM0_M0_EXCEPTION_MODE 0x00000003U +#define LP_APM0_M0_EXCEPTION_MODE_M (LP_APM0_M0_EXCEPTION_MODE_V << LP_APM0_M0_EXCEPTION_MODE_S) +#define LP_APM0_M0_EXCEPTION_MODE_V 0x00000003U +#define LP_APM0_M0_EXCEPTION_MODE_S 16 +/** LP_APM0_M0_EXCEPTION_ID : RO; bitpos: [22:18]; default: 0; + * Exception id information + */ +#define LP_APM0_M0_EXCEPTION_ID 0x0000001FU +#define LP_APM0_M0_EXCEPTION_ID_M (LP_APM0_M0_EXCEPTION_ID_V << LP_APM0_M0_EXCEPTION_ID_S) +#define LP_APM0_M0_EXCEPTION_ID_V 0x0000001FU +#define LP_APM0_M0_EXCEPTION_ID_S 18 + +/** LP_APM0_M0_EXCEPTION_INFO1_REG register + * M0 exception_info1 register + */ +#define LP_APM0_M0_EXCEPTION_INFO1_REG (DR_REG_LP_BASE + 0xd4) +/** LP_APM0_M0_EXCEPTION_ADDR : RO; bitpos: [31:0]; default: 0; + * Exception addr + */ +#define LP_APM0_M0_EXCEPTION_ADDR 0xFFFFFFFFU +#define LP_APM0_M0_EXCEPTION_ADDR_M (LP_APM0_M0_EXCEPTION_ADDR_V << LP_APM0_M0_EXCEPTION_ADDR_S) +#define LP_APM0_M0_EXCEPTION_ADDR_V 0xFFFFFFFFU +#define LP_APM0_M0_EXCEPTION_ADDR_S 0 + +/** LP_APM0_INT_EN_REG register + * APM interrupt enable register + */ +#define LP_APM0_INT_EN_REG (DR_REG_LP_BASE + 0xd8) +/** LP_APM0_M0_APM_INT_EN : R/W; bitpos: [0]; default: 0; + * APM M0 interrupt enable + */ +#define LP_APM0_M0_APM_INT_EN (BIT(0)) +#define LP_APM0_M0_APM_INT_EN_M (LP_APM0_M0_APM_INT_EN_V << LP_APM0_M0_APM_INT_EN_S) +#define LP_APM0_M0_APM_INT_EN_V 0x00000001U +#define LP_APM0_M0_APM_INT_EN_S 0 + +/** LP_APM0_CLOCK_GATE_REG register + * clock gating register + */ +#define LP_APM0_CLOCK_GATE_REG (DR_REG_LP_BASE + 0xdc) +/** LP_APM0_CLK_EN : R/W; bitpos: [0]; default: 1; + * reg_clk_en + */ +#define LP_APM0_CLK_EN (BIT(0)) +#define LP_APM0_CLK_EN_M (LP_APM0_CLK_EN_V << LP_APM0_CLK_EN_S) +#define LP_APM0_CLK_EN_V 0x00000001U +#define LP_APM0_CLK_EN_S 0 + +/** LP_APM0_DATE_REG register + * Version register + */ +#define LP_APM0_DATE_REG (DR_REG_LP_BASE + 0x7fc) +/** LP_APM0_DATE : R/W; bitpos: [27:0]; default: 35672640; + * reg_date + */ +#define LP_APM0_DATE 0x0FFFFFFFU +#define LP_APM0_DATE_M (LP_APM0_DATE_V << LP_APM0_DATE_S) +#define LP_APM0_DATE_V 0x0FFFFFFFU +#define LP_APM0_DATE_S 0 + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32h21/register/soc/lp_apm0_struct.h b/components/soc/esp32h21/register/soc/lp_apm0_struct.h new file mode 100644 index 00000000000..48258e4a573 --- /dev/null +++ b/components/soc/esp32h21/register/soc/lp_apm0_struct.h @@ -0,0 +1,499 @@ +/** + * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#ifdef __cplusplus +extern "C" { +#endif + +/** Group: Region filter enable register */ +/** Type of apm0_region_filter_en register + * Region filter enable register + */ +typedef union { + struct { + /** apm0_region_filter_en : R/W; bitpos: [3:0]; default: 1; + * Region filter enable + */ + uint32_t apm0_region_filter_en:4; + uint32_t reserved_4:28; + }; + uint32_t val; +} lp_apm0_region_filter_en_reg_t; + + +/** Group: Region address register */ +/** Type of apm0_region0_addr_start register + * Region address register + */ +typedef union { + struct { + /** apm0_region0_addr_start : R/W; bitpos: [31:0]; default: 0; + * Start address of region0 + */ + uint32_t apm0_region0_addr_start:32; + }; + uint32_t val; +} lp_apm0_region0_addr_start_reg_t; + +/** Type of apm0_region0_addr_end register + * Region address register + */ +typedef union { + struct { + /** apm0_region0_addr_end : R/W; bitpos: [31:0]; default: 4294967295; + * End address of region0 + */ + uint32_t apm0_region0_addr_end:32; + }; + uint32_t val; +} lp_apm0_region0_addr_end_reg_t; + +/** Type of apm0_region1_addr_start register + * Region address register + */ +typedef union { + struct { + /** apm0_region1_addr_start : R/W; bitpos: [31:0]; default: 0; + * Start address of region1 + */ + uint32_t apm0_region1_addr_start:32; + }; + uint32_t val; +} lp_apm0_region1_addr_start_reg_t; + +/** Type of apm0_region1_addr_end register + * Region address register + */ +typedef union { + struct { + /** apm0_region1_addr_end : R/W; bitpos: [31:0]; default: 4294967295; + * End address of region1 + */ + uint32_t apm0_region1_addr_end:32; + }; + uint32_t val; +} lp_apm0_region1_addr_end_reg_t; + +/** Type of apm0_region2_addr_start register + * Region address register + */ +typedef union { + struct { + /** apm0_region2_addr_start : R/W; bitpos: [31:0]; default: 0; + * Start address of region2 + */ + uint32_t apm0_region2_addr_start:32; + }; + uint32_t val; +} lp_apm0_region2_addr_start_reg_t; + +/** Type of apm0_region2_addr_end register + * Region address register + */ +typedef union { + struct { + /** apm0_region2_addr_end : R/W; bitpos: [31:0]; default: 4294967295; + * End address of region2 + */ + uint32_t apm0_region2_addr_end:32; + }; + uint32_t val; +} lp_apm0_region2_addr_end_reg_t; + +/** Type of apm0_region3_addr_start register + * Region address register + */ +typedef union { + struct { + /** apm0_region3_addr_start : R/W; bitpos: [31:0]; default: 0; + * Start address of region3 + */ + uint32_t apm0_region3_addr_start:32; + }; + uint32_t val; +} lp_apm0_region3_addr_start_reg_t; + +/** Type of apm0_region3_addr_end register + * Region address register + */ +typedef union { + struct { + /** apm0_region3_addr_end : R/W; bitpos: [31:0]; default: 4294967295; + * End address of region3 + */ + uint32_t apm0_region3_addr_end:32; + }; + uint32_t val; +} lp_apm0_region3_addr_end_reg_t; + + +/** Group: Region access authority attribute register */ +/** Type of apm0_region0_pms_attr register + * Region access authority attribute register + */ +typedef union { + struct { + /** apm0_region0_r0_pms_x : R/W; bitpos: [0]; default: 0; + * Region execute authority in REE_MODE0 + */ + uint32_t apm0_region0_r0_pms_x:1; + /** apm0_region0_r0_pms_w : R/W; bitpos: [1]; default: 0; + * Region write authority in REE_MODE0 + */ + uint32_t apm0_region0_r0_pms_w:1; + /** apm0_region0_r0_pms_r : R/W; bitpos: [2]; default: 0; + * Region read authority in REE_MODE0 + */ + uint32_t apm0_region0_r0_pms_r:1; + uint32_t reserved_3:1; + /** apm0_region0_r1_pms_x : R/W; bitpos: [4]; default: 0; + * Region execute authority in REE_MODE1 + */ + uint32_t apm0_region0_r1_pms_x:1; + /** apm0_region0_r1_pms_w : R/W; bitpos: [5]; default: 0; + * Region write authority in REE_MODE1 + */ + uint32_t apm0_region0_r1_pms_w:1; + /** apm0_region0_r1_pms_r : R/W; bitpos: [6]; default: 0; + * Region read authority in REE_MODE1 + */ + uint32_t apm0_region0_r1_pms_r:1; + uint32_t reserved_7:1; + /** apm0_region0_r2_pms_x : R/W; bitpos: [8]; default: 0; + * Region execute authority in REE_MODE2 + */ + uint32_t apm0_region0_r2_pms_x:1; + /** apm0_region0_r2_pms_w : R/W; bitpos: [9]; default: 0; + * Region write authority in REE_MODE2 + */ + uint32_t apm0_region0_r2_pms_w:1; + /** apm0_region0_r2_pms_r : R/W; bitpos: [10]; default: 0; + * Region read authority in REE_MODE2 + */ + uint32_t apm0_region0_r2_pms_r:1; + uint32_t reserved_11:21; + }; + uint32_t val; +} lp_apm0_region0_pms_attr_reg_t; + +/** Type of apm0_region1_pms_attr register + * Region access authority attribute register + */ +typedef union { + struct { + /** apm0_region1_r0_pms_x : R/W; bitpos: [0]; default: 0; + * Region execute authority in REE_MODE0 + */ + uint32_t apm0_region1_r0_pms_x:1; + /** apm0_region1_r0_pms_w : R/W; bitpos: [1]; default: 0; + * Region write authority in REE_MODE0 + */ + uint32_t apm0_region1_r0_pms_w:1; + /** apm0_region1_r0_pms_r : R/W; bitpos: [2]; default: 0; + * Region read authority in REE_MODE0 + */ + uint32_t apm0_region1_r0_pms_r:1; + uint32_t reserved_3:1; + /** apm0_region1_r1_pms_x : R/W; bitpos: [4]; default: 0; + * Region execute authority in REE_MODE1 + */ + uint32_t apm0_region1_r1_pms_x:1; + /** apm0_region1_r1_pms_w : R/W; bitpos: [5]; default: 0; + * Region write authority in REE_MODE1 + */ + uint32_t apm0_region1_r1_pms_w:1; + /** apm0_region1_r1_pms_r : R/W; bitpos: [6]; default: 0; + * Region read authority in REE_MODE1 + */ + uint32_t apm0_region1_r1_pms_r:1; + uint32_t reserved_7:1; + /** apm0_region1_r2_pms_x : R/W; bitpos: [8]; default: 0; + * Region execute authority in REE_MODE2 + */ + uint32_t apm0_region1_r2_pms_x:1; + /** apm0_region1_r2_pms_w : R/W; bitpos: [9]; default: 0; + * Region write authority in REE_MODE2 + */ + uint32_t apm0_region1_r2_pms_w:1; + /** apm0_region1_r2_pms_r : R/W; bitpos: [10]; default: 0; + * Region read authority in REE_MODE2 + */ + uint32_t apm0_region1_r2_pms_r:1; + uint32_t reserved_11:21; + }; + uint32_t val; +} lp_apm0_region1_pms_attr_reg_t; + +/** Type of apm0_region2_pms_attr register + * Region access authority attribute register + */ +typedef union { + struct { + /** apm0_region2_r0_pms_x : R/W; bitpos: [0]; default: 0; + * Region execute authority in REE_MODE0 + */ + uint32_t apm0_region2_r0_pms_x:1; + /** apm0_region2_r0_pms_w : R/W; bitpos: [1]; default: 0; + * Region write authority in REE_MODE0 + */ + uint32_t apm0_region2_r0_pms_w:1; + /** apm0_region2_r0_pms_r : R/W; bitpos: [2]; default: 0; + * Region read authority in REE_MODE0 + */ + uint32_t apm0_region2_r0_pms_r:1; + uint32_t reserved_3:1; + /** apm0_region2_r1_pms_x : R/W; bitpos: [4]; default: 0; + * Region execute authority in REE_MODE1 + */ + uint32_t apm0_region2_r1_pms_x:1; + /** apm0_region2_r1_pms_w : R/W; bitpos: [5]; default: 0; + * Region write authority in REE_MODE1 + */ + uint32_t apm0_region2_r1_pms_w:1; + /** apm0_region2_r1_pms_r : R/W; bitpos: [6]; default: 0; + * Region read authority in REE_MODE1 + */ + uint32_t apm0_region2_r1_pms_r:1; + uint32_t reserved_7:1; + /** apm0_region2_r2_pms_x : R/W; bitpos: [8]; default: 0; + * Region execute authority in REE_MODE2 + */ + uint32_t apm0_region2_r2_pms_x:1; + /** apm0_region2_r2_pms_w : R/W; bitpos: [9]; default: 0; + * Region write authority in REE_MODE2 + */ + uint32_t apm0_region2_r2_pms_w:1; + /** apm0_region2_r2_pms_r : R/W; bitpos: [10]; default: 0; + * Region read authority in REE_MODE2 + */ + uint32_t apm0_region2_r2_pms_r:1; + uint32_t reserved_11:21; + }; + uint32_t val; +} lp_apm0_region2_pms_attr_reg_t; + +/** Type of apm0_region3_pms_attr register + * Region access authority attribute register + */ +typedef union { + struct { + /** apm0_region3_r0_pms_x : R/W; bitpos: [0]; default: 0; + * Region execute authority in REE_MODE0 + */ + uint32_t apm0_region3_r0_pms_x:1; + /** apm0_region3_r0_pms_w : R/W; bitpos: [1]; default: 0; + * Region write authority in REE_MODE0 + */ + uint32_t apm0_region3_r0_pms_w:1; + /** apm0_region3_r0_pms_r : R/W; bitpos: [2]; default: 0; + * Region read authority in REE_MODE0 + */ + uint32_t apm0_region3_r0_pms_r:1; + uint32_t reserved_3:1; + /** apm0_region3_r1_pms_x : R/W; bitpos: [4]; default: 0; + * Region execute authority in REE_MODE1 + */ + uint32_t apm0_region3_r1_pms_x:1; + /** apm0_region3_r1_pms_w : R/W; bitpos: [5]; default: 0; + * Region write authority in REE_MODE1 + */ + uint32_t apm0_region3_r1_pms_w:1; + /** apm0_region3_r1_pms_r : R/W; bitpos: [6]; default: 0; + * Region read authority in REE_MODE1 + */ + uint32_t apm0_region3_r1_pms_r:1; + uint32_t reserved_7:1; + /** apm0_region3_r2_pms_x : R/W; bitpos: [8]; default: 0; + * Region execute authority in REE_MODE2 + */ + uint32_t apm0_region3_r2_pms_x:1; + /** apm0_region3_r2_pms_w : R/W; bitpos: [9]; default: 0; + * Region write authority in REE_MODE2 + */ + uint32_t apm0_region3_r2_pms_w:1; + /** apm0_region3_r2_pms_r : R/W; bitpos: [10]; default: 0; + * Region read authority in REE_MODE2 + */ + uint32_t apm0_region3_r2_pms_r:1; + uint32_t reserved_11:21; + }; + uint32_t val; +} lp_apm0_region3_pms_attr_reg_t; + + +/** Group: PMS function control register */ +/** Type of apm0_func_ctrl register + * PMS function control register + */ +typedef union { + struct { + /** apm0_m0_pms_func_en : R/W; bitpos: [0]; default: 1; + * PMS M0 function enable + */ + uint32_t apm0_m0_pms_func_en:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} lp_apm0_func_ctrl_reg_t; + + +/** Group: M0 status register */ +/** Type of apm0_m0_status register + * M0 status register + */ +typedef union { + struct { + /** apm0_m0_exception_status : RO; bitpos: [1:0]; default: 0; + * Exception status + */ + uint32_t apm0_m0_exception_status:2; + uint32_t reserved_2:30; + }; + uint32_t val; +} lp_apm0_m0_status_reg_t; + + +/** Group: M0 status clear register */ +/** Type of apm0_m0_status_clr register + * M0 status clear register + */ +typedef union { + struct { + /** apm0_m0_region_status_clr : WT; bitpos: [0]; default: 0; + * Clear exception status + */ + uint32_t apm0_m0_region_status_clr:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} lp_apm0_m0_status_clr_reg_t; + + +/** Group: M0 exception_info0 register */ +/** Type of apm0_m0_exception_info0 register + * M0 exception_info0 register + */ +typedef union { + struct { + /** apm0_m0_exception_region : RO; bitpos: [3:0]; default: 0; + * Exception region + */ + uint32_t apm0_m0_exception_region:4; + uint32_t reserved_4:12; + /** apm0_m0_exception_mode : RO; bitpos: [17:16]; default: 0; + * Exception mode + */ + uint32_t apm0_m0_exception_mode:2; + /** apm0_m0_exception_id : RO; bitpos: [22:18]; default: 0; + * Exception id information + */ + uint32_t apm0_m0_exception_id:5; + uint32_t reserved_23:9; + }; + uint32_t val; +} lp_apm0_m0_exception_info0_reg_t; + + +/** Group: M0 exception_info1 register */ +/** Type of apm0_m0_exception_info1 register + * M0 exception_info1 register + */ +typedef union { + struct { + /** apm0_m0_exception_addr : RO; bitpos: [31:0]; default: 0; + * Exception addr + */ + uint32_t apm0_m0_exception_addr:32; + }; + uint32_t val; +} lp_apm0_m0_exception_info1_reg_t; + + +/** Group: APM interrupt enable register */ +/** Type of apm0_int_en register + * APM interrupt enable register + */ +typedef union { + struct { + /** apm0_m0_apm_int_en : R/W; bitpos: [0]; default: 0; + * APM M0 interrupt enable + */ + uint32_t apm0_m0_apm_int_en:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} lp_apm0_int_en_reg_t; + + +/** Group: clock gating register */ +/** Type of apm0_clock_gate register + * clock gating register + */ +typedef union { + struct { + /** apm0_clk_en : R/W; bitpos: [0]; default: 1; + * reg_clk_en + */ + uint32_t apm0_clk_en:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} lp_apm0_clock_gate_reg_t; + + +/** Group: Version register */ +/** Type of apm0_date register + * Version register + */ +typedef union { + struct { + /** apm0_date : R/W; bitpos: [27:0]; default: 35672640; + * reg_date + */ + uint32_t apm0_date:28; + uint32_t reserved_28:4; + }; + uint32_t val; +} lp_apm0_date_reg_t; + + +typedef struct { + volatile lp_apm0_region_filter_en_reg_t apm0_region_filter_en; + volatile lp_apm0_region0_addr_start_reg_t apm0_region0_addr_start; + volatile lp_apm0_region0_addr_end_reg_t apm0_region0_addr_end; + volatile lp_apm0_region0_pms_attr_reg_t apm0_region0_pms_attr; + volatile lp_apm0_region1_addr_start_reg_t apm0_region1_addr_start; + volatile lp_apm0_region1_addr_end_reg_t apm0_region1_addr_end; + volatile lp_apm0_region1_pms_attr_reg_t apm0_region1_pms_attr; + volatile lp_apm0_region2_addr_start_reg_t apm0_region2_addr_start; + volatile lp_apm0_region2_addr_end_reg_t apm0_region2_addr_end; + volatile lp_apm0_region2_pms_attr_reg_t apm0_region2_pms_attr; + volatile lp_apm0_region3_addr_start_reg_t apm0_region3_addr_start; + volatile lp_apm0_region3_addr_end_reg_t apm0_region3_addr_end; + volatile lp_apm0_region3_pms_attr_reg_t apm0_region3_pms_attr; + uint32_t reserved_034[36]; + volatile lp_apm0_func_ctrl_reg_t apm0_func_ctrl; + volatile lp_apm0_m0_status_reg_t apm0_m0_status; + volatile lp_apm0_m0_status_clr_reg_t apm0_m0_status_clr; + volatile lp_apm0_m0_exception_info0_reg_t apm0_m0_exception_info0; + volatile lp_apm0_m0_exception_info1_reg_t apm0_m0_exception_info1; + volatile lp_apm0_int_en_reg_t apm0_int_en; + volatile lp_apm0_clock_gate_reg_t apm0_clock_gate; + uint32_t reserved_0e0[455]; + volatile lp_apm0_date_reg_t apm0_date; +} lp_apm0_dev_t; + +extern lp_apm0_dev_t LP_APM0; + +#ifndef __cplusplus +_Static_assert(sizeof(lp_apm0_dev_t) == 0x800, "Invalid size of lp_apm0_dev_t structure"); +#endif + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32h21/register/soc/lp_apm_reg.h b/components/soc/esp32h21/register/soc/lp_apm_reg.h new file mode 100644 index 00000000000..6e433906e16 --- /dev/null +++ b/components/soc/esp32h21/register/soc/lp_apm_reg.h @@ -0,0 +1,322 @@ +/** + * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#include "soc/soc.h" +#ifdef __cplusplus +extern "C" { +#endif + +/** LP_APM_REGION_FILTER_EN_REG register + * Region filter enable register + */ +#define LP_APM_REGION_FILTER_EN_REG (DR_REG_LP_BASE + 0x0) +/** LP_APM_REGION_FILTER_EN : R/W; bitpos: [1:0]; default: 1; + * Region filter enable + */ +#define LP_APM_REGION_FILTER_EN 0x00000003U +#define LP_APM_REGION_FILTER_EN_M (LP_APM_REGION_FILTER_EN_V << LP_APM_REGION_FILTER_EN_S) +#define LP_APM_REGION_FILTER_EN_V 0x00000003U +#define LP_APM_REGION_FILTER_EN_S 0 + +/** LP_APM_REGION0_ADDR_START_REG register + * Region address register + */ +#define LP_APM_REGION0_ADDR_START_REG (DR_REG_LP_BASE + 0x4) +/** LP_APM_REGION0_ADDR_START : R/W; bitpos: [31:0]; default: 0; + * Start address of region0 + */ +#define LP_APM_REGION0_ADDR_START 0xFFFFFFFFU +#define LP_APM_REGION0_ADDR_START_M (LP_APM_REGION0_ADDR_START_V << LP_APM_REGION0_ADDR_START_S) +#define LP_APM_REGION0_ADDR_START_V 0xFFFFFFFFU +#define LP_APM_REGION0_ADDR_START_S 0 + +/** LP_APM_REGION0_ADDR_END_REG register + * Region address register + */ +#define LP_APM_REGION0_ADDR_END_REG (DR_REG_LP_BASE + 0x8) +/** LP_APM_REGION0_ADDR_END : R/W; bitpos: [31:0]; default: 4294967295; + * End address of region0 + */ +#define LP_APM_REGION0_ADDR_END 0xFFFFFFFFU +#define LP_APM_REGION0_ADDR_END_M (LP_APM_REGION0_ADDR_END_V << LP_APM_REGION0_ADDR_END_S) +#define LP_APM_REGION0_ADDR_END_V 0xFFFFFFFFU +#define LP_APM_REGION0_ADDR_END_S 0 + +/** LP_APM_REGION0_PMS_ATTR_REG register + * Region access authority attribute register + */ +#define LP_APM_REGION0_PMS_ATTR_REG (DR_REG_LP_BASE + 0xc) +/** LP_APM_REGION0_R0_PMS_X : R/W; bitpos: [0]; default: 0; + * Region execute authority in REE_MODE0 + */ +#define LP_APM_REGION0_R0_PMS_X (BIT(0)) +#define LP_APM_REGION0_R0_PMS_X_M (LP_APM_REGION0_R0_PMS_X_V << LP_APM_REGION0_R0_PMS_X_S) +#define LP_APM_REGION0_R0_PMS_X_V 0x00000001U +#define LP_APM_REGION0_R0_PMS_X_S 0 +/** LP_APM_REGION0_R0_PMS_W : R/W; bitpos: [1]; default: 0; + * Region write authority in REE_MODE0 + */ +#define LP_APM_REGION0_R0_PMS_W (BIT(1)) +#define LP_APM_REGION0_R0_PMS_W_M (LP_APM_REGION0_R0_PMS_W_V << LP_APM_REGION0_R0_PMS_W_S) +#define LP_APM_REGION0_R0_PMS_W_V 0x00000001U +#define LP_APM_REGION0_R0_PMS_W_S 1 +/** LP_APM_REGION0_R0_PMS_R : R/W; bitpos: [2]; default: 0; + * Region read authority in REE_MODE0 + */ +#define LP_APM_REGION0_R0_PMS_R (BIT(2)) +#define LP_APM_REGION0_R0_PMS_R_M (LP_APM_REGION0_R0_PMS_R_V << LP_APM_REGION0_R0_PMS_R_S) +#define LP_APM_REGION0_R0_PMS_R_V 0x00000001U +#define LP_APM_REGION0_R0_PMS_R_S 2 +/** LP_APM_REGION0_R1_PMS_X : R/W; bitpos: [4]; default: 0; + * Region execute authority in REE_MODE1 + */ +#define LP_APM_REGION0_R1_PMS_X (BIT(4)) +#define LP_APM_REGION0_R1_PMS_X_M (LP_APM_REGION0_R1_PMS_X_V << LP_APM_REGION0_R1_PMS_X_S) +#define LP_APM_REGION0_R1_PMS_X_V 0x00000001U +#define LP_APM_REGION0_R1_PMS_X_S 4 +/** LP_APM_REGION0_R1_PMS_W : R/W; bitpos: [5]; default: 0; + * Region write authority in REE_MODE1 + */ +#define LP_APM_REGION0_R1_PMS_W (BIT(5)) +#define LP_APM_REGION0_R1_PMS_W_M (LP_APM_REGION0_R1_PMS_W_V << LP_APM_REGION0_R1_PMS_W_S) +#define LP_APM_REGION0_R1_PMS_W_V 0x00000001U +#define LP_APM_REGION0_R1_PMS_W_S 5 +/** LP_APM_REGION0_R1_PMS_R : R/W; bitpos: [6]; default: 0; + * Region read authority in REE_MODE1 + */ +#define LP_APM_REGION0_R1_PMS_R (BIT(6)) +#define LP_APM_REGION0_R1_PMS_R_M (LP_APM_REGION0_R1_PMS_R_V << LP_APM_REGION0_R1_PMS_R_S) +#define LP_APM_REGION0_R1_PMS_R_V 0x00000001U +#define LP_APM_REGION0_R1_PMS_R_S 6 +/** LP_APM_REGION0_R2_PMS_X : R/W; bitpos: [8]; default: 0; + * Region execute authority in REE_MODE2 + */ +#define LP_APM_REGION0_R2_PMS_X (BIT(8)) +#define LP_APM_REGION0_R2_PMS_X_M (LP_APM_REGION0_R2_PMS_X_V << LP_APM_REGION0_R2_PMS_X_S) +#define LP_APM_REGION0_R2_PMS_X_V 0x00000001U +#define LP_APM_REGION0_R2_PMS_X_S 8 +/** LP_APM_REGION0_R2_PMS_W : R/W; bitpos: [9]; default: 0; + * Region write authority in REE_MODE2 + */ +#define LP_APM_REGION0_R2_PMS_W (BIT(9)) +#define LP_APM_REGION0_R2_PMS_W_M (LP_APM_REGION0_R2_PMS_W_V << LP_APM_REGION0_R2_PMS_W_S) +#define LP_APM_REGION0_R2_PMS_W_V 0x00000001U +#define LP_APM_REGION0_R2_PMS_W_S 9 +/** LP_APM_REGION0_R2_PMS_R : R/W; bitpos: [10]; default: 0; + * Region read authority in REE_MODE2 + */ +#define LP_APM_REGION0_R2_PMS_R (BIT(10)) +#define LP_APM_REGION0_R2_PMS_R_M (LP_APM_REGION0_R2_PMS_R_V << LP_APM_REGION0_R2_PMS_R_S) +#define LP_APM_REGION0_R2_PMS_R_V 0x00000001U +#define LP_APM_REGION0_R2_PMS_R_S 10 + +/** LP_APM_REGION1_ADDR_START_REG register + * Region address register + */ +#define LP_APM_REGION1_ADDR_START_REG (DR_REG_LP_BASE + 0x10) +/** LP_APM_REGION1_ADDR_START : R/W; bitpos: [31:0]; default: 0; + * Start address of region1 + */ +#define LP_APM_REGION1_ADDR_START 0xFFFFFFFFU +#define LP_APM_REGION1_ADDR_START_M (LP_APM_REGION1_ADDR_START_V << LP_APM_REGION1_ADDR_START_S) +#define LP_APM_REGION1_ADDR_START_V 0xFFFFFFFFU +#define LP_APM_REGION1_ADDR_START_S 0 + +/** LP_APM_REGION1_ADDR_END_REG register + * Region address register + */ +#define LP_APM_REGION1_ADDR_END_REG (DR_REG_LP_BASE + 0x14) +/** LP_APM_REGION1_ADDR_END : R/W; bitpos: [31:0]; default: 4294967295; + * End address of region1 + */ +#define LP_APM_REGION1_ADDR_END 0xFFFFFFFFU +#define LP_APM_REGION1_ADDR_END_M (LP_APM_REGION1_ADDR_END_V << LP_APM_REGION1_ADDR_END_S) +#define LP_APM_REGION1_ADDR_END_V 0xFFFFFFFFU +#define LP_APM_REGION1_ADDR_END_S 0 + +/** LP_APM_REGION1_PMS_ATTR_REG register + * Region access authority attribute register + */ +#define LP_APM_REGION1_PMS_ATTR_REG (DR_REG_LP_BASE + 0x18) +/** LP_APM_REGION1_R0_PMS_X : R/W; bitpos: [0]; default: 0; + * Region execute authority in REE_MODE0 + */ +#define LP_APM_REGION1_R0_PMS_X (BIT(0)) +#define LP_APM_REGION1_R0_PMS_X_M (LP_APM_REGION1_R0_PMS_X_V << LP_APM_REGION1_R0_PMS_X_S) +#define LP_APM_REGION1_R0_PMS_X_V 0x00000001U +#define LP_APM_REGION1_R0_PMS_X_S 0 +/** LP_APM_REGION1_R0_PMS_W : R/W; bitpos: [1]; default: 0; + * Region write authority in REE_MODE0 + */ +#define LP_APM_REGION1_R0_PMS_W (BIT(1)) +#define LP_APM_REGION1_R0_PMS_W_M (LP_APM_REGION1_R0_PMS_W_V << LP_APM_REGION1_R0_PMS_W_S) +#define LP_APM_REGION1_R0_PMS_W_V 0x00000001U +#define LP_APM_REGION1_R0_PMS_W_S 1 +/** LP_APM_REGION1_R0_PMS_R : R/W; bitpos: [2]; default: 0; + * Region read authority in REE_MODE0 + */ +#define LP_APM_REGION1_R0_PMS_R (BIT(2)) +#define LP_APM_REGION1_R0_PMS_R_M (LP_APM_REGION1_R0_PMS_R_V << LP_APM_REGION1_R0_PMS_R_S) +#define LP_APM_REGION1_R0_PMS_R_V 0x00000001U +#define LP_APM_REGION1_R0_PMS_R_S 2 +/** LP_APM_REGION1_R1_PMS_X : R/W; bitpos: [4]; default: 0; + * Region execute authority in REE_MODE1 + */ +#define LP_APM_REGION1_R1_PMS_X (BIT(4)) +#define LP_APM_REGION1_R1_PMS_X_M (LP_APM_REGION1_R1_PMS_X_V << LP_APM_REGION1_R1_PMS_X_S) +#define LP_APM_REGION1_R1_PMS_X_V 0x00000001U +#define LP_APM_REGION1_R1_PMS_X_S 4 +/** LP_APM_REGION1_R1_PMS_W : R/W; bitpos: [5]; default: 0; + * Region write authority in REE_MODE1 + */ +#define LP_APM_REGION1_R1_PMS_W (BIT(5)) +#define LP_APM_REGION1_R1_PMS_W_M (LP_APM_REGION1_R1_PMS_W_V << LP_APM_REGION1_R1_PMS_W_S) +#define LP_APM_REGION1_R1_PMS_W_V 0x00000001U +#define LP_APM_REGION1_R1_PMS_W_S 5 +/** LP_APM_REGION1_R1_PMS_R : R/W; bitpos: [6]; default: 0; + * Region read authority in REE_MODE1 + */ +#define LP_APM_REGION1_R1_PMS_R (BIT(6)) +#define LP_APM_REGION1_R1_PMS_R_M (LP_APM_REGION1_R1_PMS_R_V << LP_APM_REGION1_R1_PMS_R_S) +#define LP_APM_REGION1_R1_PMS_R_V 0x00000001U +#define LP_APM_REGION1_R1_PMS_R_S 6 +/** LP_APM_REGION1_R2_PMS_X : R/W; bitpos: [8]; default: 0; + * Region execute authority in REE_MODE2 + */ +#define LP_APM_REGION1_R2_PMS_X (BIT(8)) +#define LP_APM_REGION1_R2_PMS_X_M (LP_APM_REGION1_R2_PMS_X_V << LP_APM_REGION1_R2_PMS_X_S) +#define LP_APM_REGION1_R2_PMS_X_V 0x00000001U +#define LP_APM_REGION1_R2_PMS_X_S 8 +/** LP_APM_REGION1_R2_PMS_W : R/W; bitpos: [9]; default: 0; + * Region write authority in REE_MODE2 + */ +#define LP_APM_REGION1_R2_PMS_W (BIT(9)) +#define LP_APM_REGION1_R2_PMS_W_M (LP_APM_REGION1_R2_PMS_W_V << LP_APM_REGION1_R2_PMS_W_S) +#define LP_APM_REGION1_R2_PMS_W_V 0x00000001U +#define LP_APM_REGION1_R2_PMS_W_S 9 +/** LP_APM_REGION1_R2_PMS_R : R/W; bitpos: [10]; default: 0; + * Region read authority in REE_MODE2 + */ +#define LP_APM_REGION1_R2_PMS_R (BIT(10)) +#define LP_APM_REGION1_R2_PMS_R_M (LP_APM_REGION1_R2_PMS_R_V << LP_APM_REGION1_R2_PMS_R_S) +#define LP_APM_REGION1_R2_PMS_R_V 0x00000001U +#define LP_APM_REGION1_R2_PMS_R_S 10 + +/** LP_APM_FUNC_CTRL_REG register + * PMS function control register + */ +#define LP_APM_FUNC_CTRL_REG (DR_REG_LP_BASE + 0xc4) +/** LP_APM_M0_PMS_FUNC_EN : R/W; bitpos: [0]; default: 1; + * PMS M0 function enable + */ +#define LP_APM_M0_PMS_FUNC_EN (BIT(0)) +#define LP_APM_M0_PMS_FUNC_EN_M (LP_APM_M0_PMS_FUNC_EN_V << LP_APM_M0_PMS_FUNC_EN_S) +#define LP_APM_M0_PMS_FUNC_EN_V 0x00000001U +#define LP_APM_M0_PMS_FUNC_EN_S 0 + +/** LP_APM_M0_STATUS_REG register + * M0 status register + */ +#define LP_APM_M0_STATUS_REG (DR_REG_LP_BASE + 0xc8) +/** LP_APM_M0_EXCEPTION_STATUS : RO; bitpos: [1:0]; default: 0; + * Exception status + */ +#define LP_APM_M0_EXCEPTION_STATUS 0x00000003U +#define LP_APM_M0_EXCEPTION_STATUS_M (LP_APM_M0_EXCEPTION_STATUS_V << LP_APM_M0_EXCEPTION_STATUS_S) +#define LP_APM_M0_EXCEPTION_STATUS_V 0x00000003U +#define LP_APM_M0_EXCEPTION_STATUS_S 0 + +/** LP_APM_M0_STATUS_CLR_REG register + * M0 status clear register + */ +#define LP_APM_M0_STATUS_CLR_REG (DR_REG_LP_BASE + 0xcc) +/** LP_APM_M0_REGION_STATUS_CLR : WT; bitpos: [0]; default: 0; + * Clear exception status + */ +#define LP_APM_M0_REGION_STATUS_CLR (BIT(0)) +#define LP_APM_M0_REGION_STATUS_CLR_M (LP_APM_M0_REGION_STATUS_CLR_V << LP_APM_M0_REGION_STATUS_CLR_S) +#define LP_APM_M0_REGION_STATUS_CLR_V 0x00000001U +#define LP_APM_M0_REGION_STATUS_CLR_S 0 + +/** LP_APM_M0_EXCEPTION_INFO0_REG register + * M0 exception_info0 register + */ +#define LP_APM_M0_EXCEPTION_INFO0_REG (DR_REG_LP_BASE + 0xd0) +/** LP_APM_M0_EXCEPTION_REGION : RO; bitpos: [1:0]; default: 0; + * Exception region + */ +#define LP_APM_M0_EXCEPTION_REGION 0x00000003U +#define LP_APM_M0_EXCEPTION_REGION_M (LP_APM_M0_EXCEPTION_REGION_V << LP_APM_M0_EXCEPTION_REGION_S) +#define LP_APM_M0_EXCEPTION_REGION_V 0x00000003U +#define LP_APM_M0_EXCEPTION_REGION_S 0 +/** LP_APM_M0_EXCEPTION_MODE : RO; bitpos: [17:16]; default: 0; + * Exception mode + */ +#define LP_APM_M0_EXCEPTION_MODE 0x00000003U +#define LP_APM_M0_EXCEPTION_MODE_M (LP_APM_M0_EXCEPTION_MODE_V << LP_APM_M0_EXCEPTION_MODE_S) +#define LP_APM_M0_EXCEPTION_MODE_V 0x00000003U +#define LP_APM_M0_EXCEPTION_MODE_S 16 +/** LP_APM_M0_EXCEPTION_ID : RO; bitpos: [22:18]; default: 0; + * Exception id information + */ +#define LP_APM_M0_EXCEPTION_ID 0x0000001FU +#define LP_APM_M0_EXCEPTION_ID_M (LP_APM_M0_EXCEPTION_ID_V << LP_APM_M0_EXCEPTION_ID_S) +#define LP_APM_M0_EXCEPTION_ID_V 0x0000001FU +#define LP_APM_M0_EXCEPTION_ID_S 18 + +/** LP_APM_M0_EXCEPTION_INFO1_REG register + * M0 exception_info1 register + */ +#define LP_APM_M0_EXCEPTION_INFO1_REG (DR_REG_LP_BASE + 0xd4) +/** LP_APM_M0_EXCEPTION_ADDR : RO; bitpos: [31:0]; default: 0; + * Exception addr + */ +#define LP_APM_M0_EXCEPTION_ADDR 0xFFFFFFFFU +#define LP_APM_M0_EXCEPTION_ADDR_M (LP_APM_M0_EXCEPTION_ADDR_V << LP_APM_M0_EXCEPTION_ADDR_S) +#define LP_APM_M0_EXCEPTION_ADDR_V 0xFFFFFFFFU +#define LP_APM_M0_EXCEPTION_ADDR_S 0 + +/** LP_APM_INT_EN_REG register + * APM interrupt enable register + */ +#define LP_APM_INT_EN_REG (DR_REG_LP_BASE + 0xe8) +/** LP_APM_M0_APM_INT_EN : R/W; bitpos: [0]; default: 0; + * APM M0 interrupt enable + */ +#define LP_APM_M0_APM_INT_EN (BIT(0)) +#define LP_APM_M0_APM_INT_EN_M (LP_APM_M0_APM_INT_EN_V << LP_APM_M0_APM_INT_EN_S) +#define LP_APM_M0_APM_INT_EN_V 0x00000001U +#define LP_APM_M0_APM_INT_EN_S 0 + +/** LP_APM_CLOCK_GATE_REG register + * clock gating register + */ +#define LP_APM_CLOCK_GATE_REG (DR_REG_LP_BASE + 0xec) +/** LP_APM_CLK_EN : R/W; bitpos: [0]; default: 1; + * reg_clk_en + */ +#define LP_APM_CLK_EN (BIT(0)) +#define LP_APM_CLK_EN_M (LP_APM_CLK_EN_V << LP_APM_CLK_EN_S) +#define LP_APM_CLK_EN_V 0x00000001U +#define LP_APM_CLK_EN_S 0 + +/** LP_APM_DATE_REG register + * Version register + */ +#define LP_APM_DATE_REG (DR_REG_LP_BASE + 0xfc) +/** LP_APM_DATE : R/W; bitpos: [27:0]; default: 35680864; + * reg_date + */ +#define LP_APM_DATE 0x0FFFFFFFU +#define LP_APM_DATE_M (LP_APM_DATE_V << LP_APM_DATE_S) +#define LP_APM_DATE_V 0x0FFFFFFFU +#define LP_APM_DATE_S 0 + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32h21/register/soc/lp_apm_struct.h b/components/soc/esp32h21/register/soc/lp_apm_struct.h new file mode 100644 index 00000000000..974b642d00a --- /dev/null +++ b/components/soc/esp32h21/register/soc/lp_apm_struct.h @@ -0,0 +1,346 @@ +/** + * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#ifdef __cplusplus +extern "C" { +#endif + +/** Group: Region filter enable register */ +/** Type of apm_region_filter_en register + * Region filter enable register + */ +typedef union { + struct { + /** apm_region_filter_en : R/W; bitpos: [1:0]; default: 1; + * Region filter enable + */ + uint32_t apm_region_filter_en:2; + uint32_t reserved_2:30; + }; + uint32_t val; +} lp_apm_region_filter_en_reg_t; + + +/** Group: Region address register */ +/** Type of apm_region0_addr_start register + * Region address register + */ +typedef union { + struct { + /** apm_region0_addr_start : R/W; bitpos: [31:0]; default: 0; + * Start address of region0 + */ + uint32_t apm_region0_addr_start:32; + }; + uint32_t val; +} lp_apm_region0_addr_start_reg_t; + +/** Type of apm_region0_addr_end register + * Region address register + */ +typedef union { + struct { + /** apm_region0_addr_end : R/W; bitpos: [31:0]; default: 4294967295; + * End address of region0 + */ + uint32_t apm_region0_addr_end:32; + }; + uint32_t val; +} lp_apm_region0_addr_end_reg_t; + +/** Type of apm_region1_addr_start register + * Region address register + */ +typedef union { + struct { + /** apm_region1_addr_start : R/W; bitpos: [31:0]; default: 0; + * Start address of region1 + */ + uint32_t apm_region1_addr_start:32; + }; + uint32_t val; +} lp_apm_region1_addr_start_reg_t; + +/** Type of apm_region1_addr_end register + * Region address register + */ +typedef union { + struct { + /** apm_region1_addr_end : R/W; bitpos: [31:0]; default: 4294967295; + * End address of region1 + */ + uint32_t apm_region1_addr_end:32; + }; + uint32_t val; +} lp_apm_region1_addr_end_reg_t; + + +/** Group: Region access authority attribute register */ +/** Type of apm_region0_pms_attr register + * Region access authority attribute register + */ +typedef union { + struct { + /** apm_region0_r0_pms_x : R/W; bitpos: [0]; default: 0; + * Region execute authority in REE_MODE0 + */ + uint32_t apm_region0_r0_pms_x:1; + /** apm_region0_r0_pms_w : R/W; bitpos: [1]; default: 0; + * Region write authority in REE_MODE0 + */ + uint32_t apm_region0_r0_pms_w:1; + /** apm_region0_r0_pms_r : R/W; bitpos: [2]; default: 0; + * Region read authority in REE_MODE0 + */ + uint32_t apm_region0_r0_pms_r:1; + uint32_t reserved_3:1; + /** apm_region0_r1_pms_x : R/W; bitpos: [4]; default: 0; + * Region execute authority in REE_MODE1 + */ + uint32_t apm_region0_r1_pms_x:1; + /** apm_region0_r1_pms_w : R/W; bitpos: [5]; default: 0; + * Region write authority in REE_MODE1 + */ + uint32_t apm_region0_r1_pms_w:1; + /** apm_region0_r1_pms_r : R/W; bitpos: [6]; default: 0; + * Region read authority in REE_MODE1 + */ + uint32_t apm_region0_r1_pms_r:1; + uint32_t reserved_7:1; + /** apm_region0_r2_pms_x : R/W; bitpos: [8]; default: 0; + * Region execute authority in REE_MODE2 + */ + uint32_t apm_region0_r2_pms_x:1; + /** apm_region0_r2_pms_w : R/W; bitpos: [9]; default: 0; + * Region write authority in REE_MODE2 + */ + uint32_t apm_region0_r2_pms_w:1; + /** apm_region0_r2_pms_r : R/W; bitpos: [10]; default: 0; + * Region read authority in REE_MODE2 + */ + uint32_t apm_region0_r2_pms_r:1; + uint32_t reserved_11:21; + }; + uint32_t val; +} lp_apm_region0_pms_attr_reg_t; + +/** Type of apm_region1_pms_attr register + * Region access authority attribute register + */ +typedef union { + struct { + /** apm_region1_r0_pms_x : R/W; bitpos: [0]; default: 0; + * Region execute authority in REE_MODE0 + */ + uint32_t apm_region1_r0_pms_x:1; + /** apm_region1_r0_pms_w : R/W; bitpos: [1]; default: 0; + * Region write authority in REE_MODE0 + */ + uint32_t apm_region1_r0_pms_w:1; + /** apm_region1_r0_pms_r : R/W; bitpos: [2]; default: 0; + * Region read authority in REE_MODE0 + */ + uint32_t apm_region1_r0_pms_r:1; + uint32_t reserved_3:1; + /** apm_region1_r1_pms_x : R/W; bitpos: [4]; default: 0; + * Region execute authority in REE_MODE1 + */ + uint32_t apm_region1_r1_pms_x:1; + /** apm_region1_r1_pms_w : R/W; bitpos: [5]; default: 0; + * Region write authority in REE_MODE1 + */ + uint32_t apm_region1_r1_pms_w:1; + /** apm_region1_r1_pms_r : R/W; bitpos: [6]; default: 0; + * Region read authority in REE_MODE1 + */ + uint32_t apm_region1_r1_pms_r:1; + uint32_t reserved_7:1; + /** apm_region1_r2_pms_x : R/W; bitpos: [8]; default: 0; + * Region execute authority in REE_MODE2 + */ + uint32_t apm_region1_r2_pms_x:1; + /** apm_region1_r2_pms_w : R/W; bitpos: [9]; default: 0; + * Region write authority in REE_MODE2 + */ + uint32_t apm_region1_r2_pms_w:1; + /** apm_region1_r2_pms_r : R/W; bitpos: [10]; default: 0; + * Region read authority in REE_MODE2 + */ + uint32_t apm_region1_r2_pms_r:1; + uint32_t reserved_11:21; + }; + uint32_t val; +} lp_apm_region1_pms_attr_reg_t; + + +/** Group: PMS function control register */ +/** Type of apm_func_ctrl register + * PMS function control register + */ +typedef union { + struct { + /** apm_m0_pms_func_en : R/W; bitpos: [0]; default: 1; + * PMS M0 function enable + */ + uint32_t apm_m0_pms_func_en:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} lp_apm_func_ctrl_reg_t; + + +/** Group: M0 status register */ +/** Type of apm_m0_status register + * M0 status register + */ +typedef union { + struct { + /** apm_m0_exception_status : RO; bitpos: [1:0]; default: 0; + * Exception status + */ + uint32_t apm_m0_exception_status:2; + uint32_t reserved_2:30; + }; + uint32_t val; +} lp_apm_m0_status_reg_t; + + +/** Group: M0 status clear register */ +/** Type of apm_m0_status_clr register + * M0 status clear register + */ +typedef union { + struct { + /** apm_m0_region_status_clr : WT; bitpos: [0]; default: 0; + * Clear exception status + */ + uint32_t apm_m0_region_status_clr:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} lp_apm_m0_status_clr_reg_t; + + +/** Group: M0 exception_info0 register */ +/** Type of apm_m0_exception_info0 register + * M0 exception_info0 register + */ +typedef union { + struct { + /** apm_m0_exception_region : RO; bitpos: [1:0]; default: 0; + * Exception region + */ + uint32_t apm_m0_exception_region:2; + uint32_t reserved_2:14; + /** apm_m0_exception_mode : RO; bitpos: [17:16]; default: 0; + * Exception mode + */ + uint32_t apm_m0_exception_mode:2; + /** apm_m0_exception_id : RO; bitpos: [22:18]; default: 0; + * Exception id information + */ + uint32_t apm_m0_exception_id:5; + uint32_t reserved_23:9; + }; + uint32_t val; +} lp_apm_m0_exception_info0_reg_t; + + +/** Group: M0 exception_info1 register */ +/** Type of apm_m0_exception_info1 register + * M0 exception_info1 register + */ +typedef union { + struct { + /** apm_m0_exception_addr : RO; bitpos: [31:0]; default: 0; + * Exception addr + */ + uint32_t apm_m0_exception_addr:32; + }; + uint32_t val; +} lp_apm_m0_exception_info1_reg_t; + + +/** Group: APM interrupt enable register */ +/** Type of apm_int_en register + * APM interrupt enable register + */ +typedef union { + struct { + /** apm_m0_apm_int_en : R/W; bitpos: [0]; default: 0; + * APM M0 interrupt enable + */ + uint32_t apm_m0_apm_int_en:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} lp_apm_int_en_reg_t; + + +/** Group: clock gating register */ +/** Type of apm_clock_gate register + * clock gating register + */ +typedef union { + struct { + /** apm_clk_en : R/W; bitpos: [0]; default: 1; + * reg_clk_en + */ + uint32_t apm_clk_en:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} lp_apm_clock_gate_reg_t; + + +/** Group: Version register */ +/** Type of apm_date register + * Version register + */ +typedef union { + struct { + /** apm_date : R/W; bitpos: [27:0]; default: 35680864; + * reg_date + */ + uint32_t apm_date:28; + uint32_t reserved_28:4; + }; + uint32_t val; +} lp_apm_date_reg_t; + + +typedef struct { + volatile lp_apm_region_filter_en_reg_t apm_region_filter_en; + volatile lp_apm_region0_addr_start_reg_t apm_region0_addr_start; + volatile lp_apm_region0_addr_end_reg_t apm_region0_addr_end; + volatile lp_apm_region0_pms_attr_reg_t apm_region0_pms_attr; + volatile lp_apm_region1_addr_start_reg_t apm_region1_addr_start; + volatile lp_apm_region1_addr_end_reg_t apm_region1_addr_end; + volatile lp_apm_region1_pms_attr_reg_t apm_region1_pms_attr; + uint32_t reserved_01c[42]; + volatile lp_apm_func_ctrl_reg_t apm_func_ctrl; + volatile lp_apm_m0_status_reg_t apm_m0_status; + volatile lp_apm_m0_status_clr_reg_t apm_m0_status_clr; + volatile lp_apm_m0_exception_info0_reg_t apm_m0_exception_info0; + volatile lp_apm_m0_exception_info1_reg_t apm_m0_exception_info1; + uint32_t reserved_0d8[4]; + volatile lp_apm_int_en_reg_t apm_int_en; + volatile lp_apm_clock_gate_reg_t apm_clock_gate; + uint32_t reserved_0f0[3]; + volatile lp_apm_date_reg_t apm_date; +} lp_apm_dev_t; + +extern lp_apm_dev_t LP_APM; + +#ifndef __cplusplus +_Static_assert(sizeof(lp_apm_dev_t) == 0x100, "Invalid size of lp_apm_dev_t structure"); +#endif + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32h21/register/soc/lp_clkrst_reg.h b/components/soc/esp32h21/register/soc/lp_clkrst_reg.h new file mode 100644 index 00000000000..a1c3f6dfe5d --- /dev/null +++ b/components/soc/esp32h21/register/soc/lp_clkrst_reg.h @@ -0,0 +1,431 @@ +/** + * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#include "soc/soc.h" +#ifdef __cplusplus +extern "C" { +#endif + +/** LP_CLKRST_LP_CLK_CONF_REG register + * need_des + */ +#define LP_CLKRST_LP_CLK_CONF_REG (DR_REG_LP_CLKRST_BASE + 0x0) +/** LP_CLKRST_SLOW_CLK_SEL : R/W; bitpos: [1:0]; default: 0; + * need_des + */ +#define LP_CLKRST_SLOW_CLK_SEL 0x00000003U +#define LP_CLKRST_SLOW_CLK_SEL_M (LP_CLKRST_SLOW_CLK_SEL_V << LP_CLKRST_SLOW_CLK_SEL_S) +#define LP_CLKRST_SLOW_CLK_SEL_V 0x00000003U +#define LP_CLKRST_SLOW_CLK_SEL_S 0 +/** LP_CLKRST_FAST_CLK_SEL : R/W; bitpos: [3:2]; default: 1; + * need_des + */ +#define LP_CLKRST_FAST_CLK_SEL 0x00000003U +#define LP_CLKRST_FAST_CLK_SEL_M (LP_CLKRST_FAST_CLK_SEL_V << LP_CLKRST_FAST_CLK_SEL_S) +#define LP_CLKRST_FAST_CLK_SEL_V 0x00000003U +#define LP_CLKRST_FAST_CLK_SEL_S 2 +/** LP_CLKRST_LP_PERI_DIV_NUM : R/W; bitpos: [11:4]; default: 0; + * need_des + */ +#define LP_CLKRST_LP_PERI_DIV_NUM 0x000000FFU +#define LP_CLKRST_LP_PERI_DIV_NUM_M (LP_CLKRST_LP_PERI_DIV_NUM_V << LP_CLKRST_LP_PERI_DIV_NUM_S) +#define LP_CLKRST_LP_PERI_DIV_NUM_V 0x000000FFU +#define LP_CLKRST_LP_PERI_DIV_NUM_S 4 + +/** LP_CLKRST_LP_CLK_PO_EN_REG register + * need_des + */ +#define LP_CLKRST_LP_CLK_PO_EN_REG (DR_REG_LP_CLKRST_BASE + 0x4) +/** LP_CLKRST_AON_SLOW_OEN : R/W; bitpos: [0]; default: 1; + * need_des + */ +#define LP_CLKRST_AON_SLOW_OEN (BIT(0)) +#define LP_CLKRST_AON_SLOW_OEN_M (LP_CLKRST_AON_SLOW_OEN_V << LP_CLKRST_AON_SLOW_OEN_S) +#define LP_CLKRST_AON_SLOW_OEN_V 0x00000001U +#define LP_CLKRST_AON_SLOW_OEN_S 0 +/** LP_CLKRST_AON_FAST_OEN : R/W; bitpos: [1]; default: 1; + * need_des + */ +#define LP_CLKRST_AON_FAST_OEN (BIT(1)) +#define LP_CLKRST_AON_FAST_OEN_M (LP_CLKRST_AON_FAST_OEN_V << LP_CLKRST_AON_FAST_OEN_S) +#define LP_CLKRST_AON_FAST_OEN_V 0x00000001U +#define LP_CLKRST_AON_FAST_OEN_S 1 +/** LP_CLKRST_SOSC_OEN : R/W; bitpos: [2]; default: 1; + * need_des + */ +#define LP_CLKRST_SOSC_OEN (BIT(2)) +#define LP_CLKRST_SOSC_OEN_M (LP_CLKRST_SOSC_OEN_V << LP_CLKRST_SOSC_OEN_S) +#define LP_CLKRST_SOSC_OEN_V 0x00000001U +#define LP_CLKRST_SOSC_OEN_S 2 +/** LP_CLKRST_FOSC_OEN : R/W; bitpos: [3]; default: 1; + * need_des + */ +#define LP_CLKRST_FOSC_OEN (BIT(3)) +#define LP_CLKRST_FOSC_OEN_M (LP_CLKRST_FOSC_OEN_V << LP_CLKRST_FOSC_OEN_S) +#define LP_CLKRST_FOSC_OEN_V 0x00000001U +#define LP_CLKRST_FOSC_OEN_S 3 +/** LP_CLKRST_OSC32K_OEN : R/W; bitpos: [4]; default: 1; + * need_des + */ +#define LP_CLKRST_OSC32K_OEN (BIT(4)) +#define LP_CLKRST_OSC32K_OEN_M (LP_CLKRST_OSC32K_OEN_V << LP_CLKRST_OSC32K_OEN_S) +#define LP_CLKRST_OSC32K_OEN_V 0x00000001U +#define LP_CLKRST_OSC32K_OEN_S 4 +/** LP_CLKRST_XTAL32K_OEN : R/W; bitpos: [5]; default: 1; + * need_des + */ +#define LP_CLKRST_XTAL32K_OEN (BIT(5)) +#define LP_CLKRST_XTAL32K_OEN_M (LP_CLKRST_XTAL32K_OEN_V << LP_CLKRST_XTAL32K_OEN_S) +#define LP_CLKRST_XTAL32K_OEN_V 0x00000001U +#define LP_CLKRST_XTAL32K_OEN_S 5 +/** LP_CLKRST_CORE_EFUSE_OEN : R/W; bitpos: [6]; default: 1; + * need_des + */ +#define LP_CLKRST_CORE_EFUSE_OEN (BIT(6)) +#define LP_CLKRST_CORE_EFUSE_OEN_M (LP_CLKRST_CORE_EFUSE_OEN_V << LP_CLKRST_CORE_EFUSE_OEN_S) +#define LP_CLKRST_CORE_EFUSE_OEN_V 0x00000001U +#define LP_CLKRST_CORE_EFUSE_OEN_S 6 +/** LP_CLKRST_SLOW_OEN : R/W; bitpos: [7]; default: 1; + * need_des + */ +#define LP_CLKRST_SLOW_OEN (BIT(7)) +#define LP_CLKRST_SLOW_OEN_M (LP_CLKRST_SLOW_OEN_V << LP_CLKRST_SLOW_OEN_S) +#define LP_CLKRST_SLOW_OEN_V 0x00000001U +#define LP_CLKRST_SLOW_OEN_S 7 +/** LP_CLKRST_FAST_OEN : R/W; bitpos: [8]; default: 1; + * need_des + */ +#define LP_CLKRST_FAST_OEN (BIT(8)) +#define LP_CLKRST_FAST_OEN_M (LP_CLKRST_FAST_OEN_V << LP_CLKRST_FAST_OEN_S) +#define LP_CLKRST_FAST_OEN_V 0x00000001U +#define LP_CLKRST_FAST_OEN_S 8 +/** LP_CLKRST_RNG_OEN : R/W; bitpos: [9]; default: 1; + * need_des + */ +#define LP_CLKRST_RNG_OEN (BIT(9)) +#define LP_CLKRST_RNG_OEN_M (LP_CLKRST_RNG_OEN_V << LP_CLKRST_RNG_OEN_S) +#define LP_CLKRST_RNG_OEN_V 0x00000001U +#define LP_CLKRST_RNG_OEN_S 9 +/** LP_CLKRST_LPBUS_OEN : R/W; bitpos: [10]; default: 1; + * need_des + */ +#define LP_CLKRST_LPBUS_OEN (BIT(10)) +#define LP_CLKRST_LPBUS_OEN_M (LP_CLKRST_LPBUS_OEN_V << LP_CLKRST_LPBUS_OEN_S) +#define LP_CLKRST_LPBUS_OEN_V 0x00000001U +#define LP_CLKRST_LPBUS_OEN_S 10 + +/** LP_CLKRST_LP_CLK_EN_REG register + * need_des + */ +#define LP_CLKRST_LP_CLK_EN_REG (DR_REG_LP_CLKRST_BASE + 0x8) +/** LP_CLKRST_FAST_ORI_GATE : R/W; bitpos: [31]; default: 0; + * need_des + */ +#define LP_CLKRST_FAST_ORI_GATE (BIT(31)) +#define LP_CLKRST_FAST_ORI_GATE_M (LP_CLKRST_FAST_ORI_GATE_V << LP_CLKRST_FAST_ORI_GATE_S) +#define LP_CLKRST_FAST_ORI_GATE_V 0x00000001U +#define LP_CLKRST_FAST_ORI_GATE_S 31 + +/** LP_CLKRST_LP_RST_EN_REG register + * need_des + */ +#define LP_CLKRST_LP_RST_EN_REG (DR_REG_LP_CLKRST_BASE + 0xc) +/** LP_CLKRST_AON_EFUSE_CORE_RESET_EN : R/W; bitpos: [28]; default: 0; + * need_des + */ +#define LP_CLKRST_AON_EFUSE_CORE_RESET_EN (BIT(28)) +#define LP_CLKRST_AON_EFUSE_CORE_RESET_EN_M (LP_CLKRST_AON_EFUSE_CORE_RESET_EN_V << LP_CLKRST_AON_EFUSE_CORE_RESET_EN_S) +#define LP_CLKRST_AON_EFUSE_CORE_RESET_EN_V 0x00000001U +#define LP_CLKRST_AON_EFUSE_CORE_RESET_EN_S 28 +/** LP_CLKRST_LP_TIMER_RESET_EN : R/W; bitpos: [29]; default: 0; + * need_des + */ +#define LP_CLKRST_LP_TIMER_RESET_EN (BIT(29)) +#define LP_CLKRST_LP_TIMER_RESET_EN_M (LP_CLKRST_LP_TIMER_RESET_EN_V << LP_CLKRST_LP_TIMER_RESET_EN_S) +#define LP_CLKRST_LP_TIMER_RESET_EN_V 0x00000001U +#define LP_CLKRST_LP_TIMER_RESET_EN_S 29 +/** LP_CLKRST_WDT_RESET_EN : R/W; bitpos: [30]; default: 0; + * need_des + */ +#define LP_CLKRST_WDT_RESET_EN (BIT(30)) +#define LP_CLKRST_WDT_RESET_EN_M (LP_CLKRST_WDT_RESET_EN_V << LP_CLKRST_WDT_RESET_EN_S) +#define LP_CLKRST_WDT_RESET_EN_V 0x00000001U +#define LP_CLKRST_WDT_RESET_EN_S 30 +/** LP_CLKRST_ANA_PERI_RESET_EN : R/W; bitpos: [31]; default: 0; + * need_des + */ +#define LP_CLKRST_ANA_PERI_RESET_EN (BIT(31)) +#define LP_CLKRST_ANA_PERI_RESET_EN_M (LP_CLKRST_ANA_PERI_RESET_EN_V << LP_CLKRST_ANA_PERI_RESET_EN_S) +#define LP_CLKRST_ANA_PERI_RESET_EN_V 0x00000001U +#define LP_CLKRST_ANA_PERI_RESET_EN_S 31 + +/** LP_CLKRST_RESET_CAUSE_REG register + * need_des + */ +#define LP_CLKRST_RESET_CAUSE_REG (DR_REG_LP_CLKRST_BASE + 0x10) +/** LP_CLKRST_RESET_CAUSE : RO; bitpos: [4:0]; default: 0; + * need_des + */ +#define LP_CLKRST_RESET_CAUSE 0x0000001FU +#define LP_CLKRST_RESET_CAUSE_M (LP_CLKRST_RESET_CAUSE_V << LP_CLKRST_RESET_CAUSE_S) +#define LP_CLKRST_RESET_CAUSE_V 0x0000001FU +#define LP_CLKRST_RESET_CAUSE_S 0 +/** LP_CLKRST_CORE0_RESET_FLAG : RO; bitpos: [5]; default: 1; + * need_des + */ +#define LP_CLKRST_CORE0_RESET_FLAG (BIT(5)) +#define LP_CLKRST_CORE0_RESET_FLAG_M (LP_CLKRST_CORE0_RESET_FLAG_V << LP_CLKRST_CORE0_RESET_FLAG_S) +#define LP_CLKRST_CORE0_RESET_FLAG_V 0x00000001U +#define LP_CLKRST_CORE0_RESET_FLAG_S 5 +/** LP_CLKRST_CORE0_RESET_CAUSE_CLR : WT; bitpos: [29]; default: 0; + * need_des + */ +#define LP_CLKRST_CORE0_RESET_CAUSE_CLR (BIT(29)) +#define LP_CLKRST_CORE0_RESET_CAUSE_CLR_M (LP_CLKRST_CORE0_RESET_CAUSE_CLR_V << LP_CLKRST_CORE0_RESET_CAUSE_CLR_S) +#define LP_CLKRST_CORE0_RESET_CAUSE_CLR_V 0x00000001U +#define LP_CLKRST_CORE0_RESET_CAUSE_CLR_S 29 +/** LP_CLKRST_CORE0_RESET_FLAG_SET : WT; bitpos: [30]; default: 0; + * need_des + */ +#define LP_CLKRST_CORE0_RESET_FLAG_SET (BIT(30)) +#define LP_CLKRST_CORE0_RESET_FLAG_SET_M (LP_CLKRST_CORE0_RESET_FLAG_SET_V << LP_CLKRST_CORE0_RESET_FLAG_SET_S) +#define LP_CLKRST_CORE0_RESET_FLAG_SET_V 0x00000001U +#define LP_CLKRST_CORE0_RESET_FLAG_SET_S 30 +/** LP_CLKRST_CORE0_RESET_FLAG_CLR : WT; bitpos: [31]; default: 0; + * need_des + */ +#define LP_CLKRST_CORE0_RESET_FLAG_CLR (BIT(31)) +#define LP_CLKRST_CORE0_RESET_FLAG_CLR_M (LP_CLKRST_CORE0_RESET_FLAG_CLR_V << LP_CLKRST_CORE0_RESET_FLAG_CLR_S) +#define LP_CLKRST_CORE0_RESET_FLAG_CLR_V 0x00000001U +#define LP_CLKRST_CORE0_RESET_FLAG_CLR_S 31 + +/** LP_CLKRST_CPU_RESET_REG register + * need_des + */ +#define LP_CLKRST_CPU_RESET_REG (DR_REG_LP_CLKRST_BASE + 0x14) +/** LP_CLKRST_RTC_WDT_CPU_RESET_LENGTH : R/W; bitpos: [24:22]; default: 1; + * need_des + */ +#define LP_CLKRST_RTC_WDT_CPU_RESET_LENGTH 0x00000007U +#define LP_CLKRST_RTC_WDT_CPU_RESET_LENGTH_M (LP_CLKRST_RTC_WDT_CPU_RESET_LENGTH_V << LP_CLKRST_RTC_WDT_CPU_RESET_LENGTH_S) +#define LP_CLKRST_RTC_WDT_CPU_RESET_LENGTH_V 0x00000007U +#define LP_CLKRST_RTC_WDT_CPU_RESET_LENGTH_S 22 +/** LP_CLKRST_RTC_WDT_CPU_RESET_EN : R/W; bitpos: [25]; default: 0; + * need_des + */ +#define LP_CLKRST_RTC_WDT_CPU_RESET_EN (BIT(25)) +#define LP_CLKRST_RTC_WDT_CPU_RESET_EN_M (LP_CLKRST_RTC_WDT_CPU_RESET_EN_V << LP_CLKRST_RTC_WDT_CPU_RESET_EN_S) +#define LP_CLKRST_RTC_WDT_CPU_RESET_EN_V 0x00000001U +#define LP_CLKRST_RTC_WDT_CPU_RESET_EN_S 25 +/** LP_CLKRST_CPU_STALL_WAIT : R/W; bitpos: [30:26]; default: 1; + * need_des + */ +#define LP_CLKRST_CPU_STALL_WAIT 0x0000001FU +#define LP_CLKRST_CPU_STALL_WAIT_M (LP_CLKRST_CPU_STALL_WAIT_V << LP_CLKRST_CPU_STALL_WAIT_S) +#define LP_CLKRST_CPU_STALL_WAIT_V 0x0000001FU +#define LP_CLKRST_CPU_STALL_WAIT_S 26 +/** LP_CLKRST_CPU_STALL_EN : R/W; bitpos: [31]; default: 0; + * need_des + */ +#define LP_CLKRST_CPU_STALL_EN (BIT(31)) +#define LP_CLKRST_CPU_STALL_EN_M (LP_CLKRST_CPU_STALL_EN_V << LP_CLKRST_CPU_STALL_EN_S) +#define LP_CLKRST_CPU_STALL_EN_V 0x00000001U +#define LP_CLKRST_CPU_STALL_EN_S 31 + +/** LP_CLKRST_FOSC_CNTL_REG register + * need_des + */ +#define LP_CLKRST_FOSC_CNTL_REG (DR_REG_LP_CLKRST_BASE + 0x18) +/** LP_CLKRST_FOSC_DFREQ : R/W; bitpos: [31:22]; default: 600; + * need_des + */ +#define LP_CLKRST_FOSC_DFREQ 0x000003FFU +#define LP_CLKRST_FOSC_DFREQ_M (LP_CLKRST_FOSC_DFREQ_V << LP_CLKRST_FOSC_DFREQ_S) +#define LP_CLKRST_FOSC_DFREQ_V 0x000003FFU +#define LP_CLKRST_FOSC_DFREQ_S 22 + +/** LP_CLKRST_RC32K_CNTL_REG register + * need_des + */ +#define LP_CLKRST_RC32K_CNTL_REG (DR_REG_LP_CLKRST_BASE + 0x1c) +/** LP_CLKRST_RC32K_DFREQ : R/W; bitpos: [31:22]; default: 650; + * need_des + */ +#define LP_CLKRST_RC32K_DFREQ 0x000003FFU +#define LP_CLKRST_RC32K_DFREQ_M (LP_CLKRST_RC32K_DFREQ_V << LP_CLKRST_RC32K_DFREQ_S) +#define LP_CLKRST_RC32K_DFREQ_V 0x000003FFU +#define LP_CLKRST_RC32K_DFREQ_S 22 + +/** LP_CLKRST_CLK_TO_HP_REG register + * need_des + */ +#define LP_CLKRST_CLK_TO_HP_REG (DR_REG_LP_CLKRST_BASE + 0x20) +/** LP_CLKRST_ICG_HP_XTAL32K : R/W; bitpos: [28]; default: 1; + * need_des + */ +#define LP_CLKRST_ICG_HP_XTAL32K (BIT(28)) +#define LP_CLKRST_ICG_HP_XTAL32K_M (LP_CLKRST_ICG_HP_XTAL32K_V << LP_CLKRST_ICG_HP_XTAL32K_S) +#define LP_CLKRST_ICG_HP_XTAL32K_V 0x00000001U +#define LP_CLKRST_ICG_HP_XTAL32K_S 28 +/** LP_CLKRST_ICG_HP_SOSC : R/W; bitpos: [29]; default: 1; + * need_des + */ +#define LP_CLKRST_ICG_HP_SOSC (BIT(29)) +#define LP_CLKRST_ICG_HP_SOSC_M (LP_CLKRST_ICG_HP_SOSC_V << LP_CLKRST_ICG_HP_SOSC_S) +#define LP_CLKRST_ICG_HP_SOSC_V 0x00000001U +#define LP_CLKRST_ICG_HP_SOSC_S 29 +/** LP_CLKRST_ICG_HP_OSC32K : R/W; bitpos: [30]; default: 1; + * need_des + */ +#define LP_CLKRST_ICG_HP_OSC32K (BIT(30)) +#define LP_CLKRST_ICG_HP_OSC32K_M (LP_CLKRST_ICG_HP_OSC32K_V << LP_CLKRST_ICG_HP_OSC32K_S) +#define LP_CLKRST_ICG_HP_OSC32K_V 0x00000001U +#define LP_CLKRST_ICG_HP_OSC32K_S 30 +/** LP_CLKRST_ICG_HP_FOSC : R/W; bitpos: [31]; default: 1; + * need_des + */ +#define LP_CLKRST_ICG_HP_FOSC (BIT(31)) +#define LP_CLKRST_ICG_HP_FOSC_M (LP_CLKRST_ICG_HP_FOSC_V << LP_CLKRST_ICG_HP_FOSC_S) +#define LP_CLKRST_ICG_HP_FOSC_V 0x00000001U +#define LP_CLKRST_ICG_HP_FOSC_S 31 + +/** LP_CLKRST_LPMEM_FORCE_REG register + * need_des + */ +#define LP_CLKRST_LPMEM_FORCE_REG (DR_REG_LP_CLKRST_BASE + 0x24) +/** LP_CLKRST_LPMEM_CLK_FORCE_ON : R/W; bitpos: [31]; default: 0; + * need_des + */ +#define LP_CLKRST_LPMEM_CLK_FORCE_ON (BIT(31)) +#define LP_CLKRST_LPMEM_CLK_FORCE_ON_M (LP_CLKRST_LPMEM_CLK_FORCE_ON_V << LP_CLKRST_LPMEM_CLK_FORCE_ON_S) +#define LP_CLKRST_LPMEM_CLK_FORCE_ON_V 0x00000001U +#define LP_CLKRST_LPMEM_CLK_FORCE_ON_S 31 + +/** LP_CLKRST_LPPERI_REG register + * need_des + */ +#define LP_CLKRST_LPPERI_REG (DR_REG_LP_CLKRST_BASE + 0x28) +/** LP_CLKRST_LP_BLETIMER_DIV_NUM : R/W; bitpos: [23:12]; default: 0; + * need_des + */ +#define LP_CLKRST_LP_BLETIMER_DIV_NUM 0x00000FFFU +#define LP_CLKRST_LP_BLETIMER_DIV_NUM_M (LP_CLKRST_LP_BLETIMER_DIV_NUM_V << LP_CLKRST_LP_BLETIMER_DIV_NUM_S) +#define LP_CLKRST_LP_BLETIMER_DIV_NUM_V 0x00000FFFU +#define LP_CLKRST_LP_BLETIMER_DIV_NUM_S 12 +/** LP_CLKRST_LP_BLETIMER_32K_SEL : R/W; bitpos: [25:24]; default: 0; + * need_des + */ +#define LP_CLKRST_LP_BLETIMER_32K_SEL 0x00000003U +#define LP_CLKRST_LP_BLETIMER_32K_SEL_M (LP_CLKRST_LP_BLETIMER_32K_SEL_V << LP_CLKRST_LP_BLETIMER_32K_SEL_S) +#define LP_CLKRST_LP_BLETIMER_32K_SEL_V 0x00000003U +#define LP_CLKRST_LP_BLETIMER_32K_SEL_S 24 +/** LP_CLKRST_LP_SEL_OSC_SLOW : R/W; bitpos: [26]; default: 0; + * need_des + */ +#define LP_CLKRST_LP_SEL_OSC_SLOW (BIT(26)) +#define LP_CLKRST_LP_SEL_OSC_SLOW_M (LP_CLKRST_LP_SEL_OSC_SLOW_V << LP_CLKRST_LP_SEL_OSC_SLOW_S) +#define LP_CLKRST_LP_SEL_OSC_SLOW_V 0x00000001U +#define LP_CLKRST_LP_SEL_OSC_SLOW_S 26 +/** LP_CLKRST_LP_SEL_OSC_FAST : R/W; bitpos: [27]; default: 0; + * need_des + */ +#define LP_CLKRST_LP_SEL_OSC_FAST (BIT(27)) +#define LP_CLKRST_LP_SEL_OSC_FAST_M (LP_CLKRST_LP_SEL_OSC_FAST_V << LP_CLKRST_LP_SEL_OSC_FAST_S) +#define LP_CLKRST_LP_SEL_OSC_FAST_V 0x00000001U +#define LP_CLKRST_LP_SEL_OSC_FAST_S 27 +/** LP_CLKRST_LP_SEL_XTAL : R/W; bitpos: [28]; default: 0; + * need_des + */ +#define LP_CLKRST_LP_SEL_XTAL (BIT(28)) +#define LP_CLKRST_LP_SEL_XTAL_M (LP_CLKRST_LP_SEL_XTAL_V << LP_CLKRST_LP_SEL_XTAL_S) +#define LP_CLKRST_LP_SEL_XTAL_V 0x00000001U +#define LP_CLKRST_LP_SEL_XTAL_S 28 +/** LP_CLKRST_LP_SEL_XTAL32K : R/W; bitpos: [29]; default: 0; + * need_des + */ +#define LP_CLKRST_LP_SEL_XTAL32K (BIT(29)) +#define LP_CLKRST_LP_SEL_XTAL32K_M (LP_CLKRST_LP_SEL_XTAL32K_V << LP_CLKRST_LP_SEL_XTAL32K_S) +#define LP_CLKRST_LP_SEL_XTAL32K_V 0x00000001U +#define LP_CLKRST_LP_SEL_XTAL32K_S 29 +/** LP_CLKRST_LP_I2C_CLK_SEL : R/W; bitpos: [30]; default: 0; + * need_des + */ +#define LP_CLKRST_LP_I2C_CLK_SEL (BIT(30)) +#define LP_CLKRST_LP_I2C_CLK_SEL_M (LP_CLKRST_LP_I2C_CLK_SEL_V << LP_CLKRST_LP_I2C_CLK_SEL_S) +#define LP_CLKRST_LP_I2C_CLK_SEL_V 0x00000001U +#define LP_CLKRST_LP_I2C_CLK_SEL_S 30 +/** LP_CLKRST_LP_UART_CLK_SEL : R/W; bitpos: [31]; default: 0; + * need_des + */ +#define LP_CLKRST_LP_UART_CLK_SEL (BIT(31)) +#define LP_CLKRST_LP_UART_CLK_SEL_M (LP_CLKRST_LP_UART_CLK_SEL_V << LP_CLKRST_LP_UART_CLK_SEL_S) +#define LP_CLKRST_LP_UART_CLK_SEL_V 0x00000001U +#define LP_CLKRST_LP_UART_CLK_SEL_S 31 + +/** LP_CLKRST_XTAL32K_REG register + * need_des + */ +#define LP_CLKRST_XTAL32K_REG (DR_REG_LP_CLKRST_BASE + 0x2c) +/** LP_CLKRST_RTC_SEL_POWER_XTAL32K : R/W; bitpos: [21]; default: 0; + * need_des + */ +#define LP_CLKRST_RTC_SEL_POWER_XTAL32K (BIT(21)) +#define LP_CLKRST_RTC_SEL_POWER_XTAL32K_M (LP_CLKRST_RTC_SEL_POWER_XTAL32K_V << LP_CLKRST_RTC_SEL_POWER_XTAL32K_S) +#define LP_CLKRST_RTC_SEL_POWER_XTAL32K_V 0x00000001U +#define LP_CLKRST_RTC_SEL_POWER_XTAL32K_S 21 +/** LP_CLKRST_DRES_XTAL32K : R/W; bitpos: [24:22]; default: 3; + * need_des + */ +#define LP_CLKRST_DRES_XTAL32K 0x00000007U +#define LP_CLKRST_DRES_XTAL32K_M (LP_CLKRST_DRES_XTAL32K_V << LP_CLKRST_DRES_XTAL32K_S) +#define LP_CLKRST_DRES_XTAL32K_V 0x00000007U +#define LP_CLKRST_DRES_XTAL32K_S 22 +/** LP_CLKRST_DGM_XTAL32K : R/W; bitpos: [27:25]; default: 3; + * need_des + */ +#define LP_CLKRST_DGM_XTAL32K 0x00000007U +#define LP_CLKRST_DGM_XTAL32K_M (LP_CLKRST_DGM_XTAL32K_V << LP_CLKRST_DGM_XTAL32K_S) +#define LP_CLKRST_DGM_XTAL32K_V 0x00000007U +#define LP_CLKRST_DGM_XTAL32K_S 25 +/** LP_CLKRST_DBUF_XTAL32K : R/W; bitpos: [28]; default: 0; + * need_des + */ +#define LP_CLKRST_DBUF_XTAL32K (BIT(28)) +#define LP_CLKRST_DBUF_XTAL32K_M (LP_CLKRST_DBUF_XTAL32K_V << LP_CLKRST_DBUF_XTAL32K_S) +#define LP_CLKRST_DBUF_XTAL32K_V 0x00000001U +#define LP_CLKRST_DBUF_XTAL32K_S 28 +/** LP_CLKRST_DAC_XTAL32K : R/W; bitpos: [31:29]; default: 3; + * need_des + */ +#define LP_CLKRST_DAC_XTAL32K 0x00000007U +#define LP_CLKRST_DAC_XTAL32K_M (LP_CLKRST_DAC_XTAL32K_V << LP_CLKRST_DAC_XTAL32K_S) +#define LP_CLKRST_DAC_XTAL32K_V 0x00000007U +#define LP_CLKRST_DAC_XTAL32K_S 29 + +/** LP_CLKRST_DATE_REG register + * need_des + */ +#define LP_CLKRST_DATE_REG (DR_REG_LP_CLKRST_BASE + 0x3fc) +/** LP_CLKRST_CLKRST_DATE : R/W; bitpos: [30:0]; default: 37782064; + * need_des + */ +#define LP_CLKRST_CLKRST_DATE 0x7FFFFFFFU +#define LP_CLKRST_CLKRST_DATE_M (LP_CLKRST_CLKRST_DATE_V << LP_CLKRST_CLKRST_DATE_S) +#define LP_CLKRST_CLKRST_DATE_V 0x7FFFFFFFU +#define LP_CLKRST_CLKRST_DATE_S 0 +/** LP_CLKRST_CLK_EN : R/W; bitpos: [31]; default: 0; + * need_des + */ +#define LP_CLKRST_CLK_EN (BIT(31)) +#define LP_CLKRST_CLK_EN_M (LP_CLKRST_CLK_EN_V << LP_CLKRST_CLK_EN_S) +#define LP_CLKRST_CLK_EN_V 0x00000001U +#define LP_CLKRST_CLK_EN_S 31 + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32h21/register/soc/lp_clkrst_struct.h b/components/soc/esp32h21/register/soc/lp_clkrst_struct.h new file mode 100644 index 00000000000..4e5754ae466 --- /dev/null +++ b/components/soc/esp32h21/register/soc/lp_clkrst_struct.h @@ -0,0 +1,369 @@ +/** + * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#ifdef __cplusplus +extern "C" { +#endif + +/** Group: configure_register */ +/** Type of clkrst_lp_clk_conf register + * need_des + */ +typedef union { + struct { + /** clkrst_slow_clk_sel : R/W; bitpos: [1:0]; default: 0; + * need_des + */ + uint32_t clkrst_slow_clk_sel:2; + /** clkrst_fast_clk_sel : R/W; bitpos: [3:2]; default: 1; + * need_des + */ + uint32_t clkrst_fast_clk_sel:2; + /** clkrst_lp_peri_div_num : R/W; bitpos: [11:4]; default: 0; + * need_des + */ + uint32_t clkrst_lp_peri_div_num:8; + uint32_t reserved_12:20; + }; + uint32_t val; +} lp_clkrst_lp_clk_conf_reg_t; + +/** Type of clkrst_lp_clk_po_en register + * need_des + */ +typedef union { + struct { + /** clkrst_aon_slow_oen : R/W; bitpos: [0]; default: 1; + * need_des + */ + uint32_t clkrst_aon_slow_oen:1; + /** clkrst_aon_fast_oen : R/W; bitpos: [1]; default: 1; + * need_des + */ + uint32_t clkrst_aon_fast_oen:1; + /** clkrst_sosc_oen : R/W; bitpos: [2]; default: 1; + * need_des + */ + uint32_t clkrst_sosc_oen:1; + /** clkrst_fosc_oen : R/W; bitpos: [3]; default: 1; + * need_des + */ + uint32_t clkrst_fosc_oen:1; + /** clkrst_osc32k_oen : R/W; bitpos: [4]; default: 1; + * need_des + */ + uint32_t clkrst_osc32k_oen:1; + /** clkrst_xtal32k_oen : R/W; bitpos: [5]; default: 1; + * need_des + */ + uint32_t clkrst_xtal32k_oen:1; + /** clkrst_core_efuse_oen : R/W; bitpos: [6]; default: 1; + * need_des + */ + uint32_t clkrst_core_efuse_oen:1; + /** clkrst_slow_oen : R/W; bitpos: [7]; default: 1; + * need_des + */ + uint32_t clkrst_slow_oen:1; + /** clkrst_fast_oen : R/W; bitpos: [8]; default: 1; + * need_des + */ + uint32_t clkrst_fast_oen:1; + /** clkrst_rng_oen : R/W; bitpos: [9]; default: 1; + * need_des + */ + uint32_t clkrst_rng_oen:1; + /** clkrst_lpbus_oen : R/W; bitpos: [10]; default: 1; + * need_des + */ + uint32_t clkrst_lpbus_oen:1; + uint32_t reserved_11:21; + }; + uint32_t val; +} lp_clkrst_lp_clk_po_en_reg_t; + +/** Type of clkrst_lp_clk_en register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:31; + /** clkrst_fast_ori_gate : R/W; bitpos: [31]; default: 0; + * need_des + */ + uint32_t clkrst_fast_ori_gate:1; + }; + uint32_t val; +} lp_clkrst_lp_clk_en_reg_t; + +/** Type of clkrst_lp_rst_en register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:28; + /** clkrst_aon_efuse_core_reset_en : R/W; bitpos: [28]; default: 0; + * need_des + */ + uint32_t clkrst_aon_efuse_core_reset_en:1; + /** clkrst_lp_timer_reset_en : R/W; bitpos: [29]; default: 0; + * need_des + */ + uint32_t clkrst_lp_timer_reset_en:1; + /** clkrst_wdt_reset_en : R/W; bitpos: [30]; default: 0; + * need_des + */ + uint32_t clkrst_wdt_reset_en:1; + /** clkrst_ana_peri_reset_en : R/W; bitpos: [31]; default: 0; + * need_des + */ + uint32_t clkrst_ana_peri_reset_en:1; + }; + uint32_t val; +} lp_clkrst_lp_rst_en_reg_t; + +/** Type of clkrst_reset_cause register + * need_des + */ +typedef union { + struct { + /** clkrst_reset_cause : RO; bitpos: [4:0]; default: 0; + * need_des + */ + uint32_t clkrst_reset_cause:5; + /** clkrst_core0_reset_flag : RO; bitpos: [5]; default: 1; + * need_des + */ + uint32_t clkrst_core0_reset_flag:1; + uint32_t reserved_6:23; + /** clkrst_core0_reset_cause_clr : WT; bitpos: [29]; default: 0; + * need_des + */ + uint32_t clkrst_core0_reset_cause_clr:1; + /** clkrst_core0_reset_flag_set : WT; bitpos: [30]; default: 0; + * need_des + */ + uint32_t clkrst_core0_reset_flag_set:1; + /** clkrst_core0_reset_flag_clr : WT; bitpos: [31]; default: 0; + * need_des + */ + uint32_t clkrst_core0_reset_flag_clr:1; + }; + uint32_t val; +} lp_clkrst_reset_cause_reg_t; + +/** Type of clkrst_cpu_reset register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:22; + /** clkrst_rtc_wdt_cpu_reset_length : R/W; bitpos: [24:22]; default: 1; + * need_des + */ + uint32_t clkrst_rtc_wdt_cpu_reset_length:3; + /** clkrst_rtc_wdt_cpu_reset_en : R/W; bitpos: [25]; default: 0; + * need_des + */ + uint32_t clkrst_rtc_wdt_cpu_reset_en:1; + /** clkrst_cpu_stall_wait : R/W; bitpos: [30:26]; default: 1; + * need_des + */ + uint32_t clkrst_cpu_stall_wait:5; + /** clkrst_cpu_stall_en : R/W; bitpos: [31]; default: 0; + * need_des + */ + uint32_t clkrst_cpu_stall_en:1; + }; + uint32_t val; +} lp_clkrst_cpu_reset_reg_t; + +/** Type of clkrst_fosc_cntl register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:22; + /** clkrst_fosc_dfreq : R/W; bitpos: [31:22]; default: 600; + * need_des + */ + uint32_t clkrst_fosc_dfreq:10; + }; + uint32_t val; +} lp_clkrst_fosc_cntl_reg_t; + +/** Type of clkrst_rc32k_cntl register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:22; + /** clkrst_rc32k_dfreq : R/W; bitpos: [31:22]; default: 650; + * need_des + */ + uint32_t clkrst_rc32k_dfreq:10; + }; + uint32_t val; +} lp_clkrst_rc32k_cntl_reg_t; + +/** Type of clkrst_clk_to_hp register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:28; + /** clkrst_icg_hp_xtal32k : R/W; bitpos: [28]; default: 1; + * need_des + */ + uint32_t clkrst_icg_hp_xtal32k:1; + /** clkrst_icg_hp_sosc : R/W; bitpos: [29]; default: 1; + * need_des + */ + uint32_t clkrst_icg_hp_sosc:1; + /** clkrst_icg_hp_osc32k : R/W; bitpos: [30]; default: 1; + * need_des + */ + uint32_t clkrst_icg_hp_osc32k:1; + /** clkrst_icg_hp_fosc : R/W; bitpos: [31]; default: 1; + * need_des + */ + uint32_t clkrst_icg_hp_fosc:1; + }; + uint32_t val; +} lp_clkrst_clk_to_hp_reg_t; + +/** Type of clkrst_lpmem_force register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:31; + /** clkrst_lpmem_clk_force_on : R/W; bitpos: [31]; default: 0; + * need_des + */ + uint32_t clkrst_lpmem_clk_force_on:1; + }; + uint32_t val; +} lp_clkrst_lpmem_force_reg_t; + +/** Type of clkrst_lpperi register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:12; + /** clkrst_lp_bletimer_div_num : R/W; bitpos: [23:12]; default: 0; + * need_des + */ + uint32_t clkrst_lp_bletimer_div_num:12; + /** clkrst_lp_bletimer_32k_sel : R/W; bitpos: [25:24]; default: 0; + * need_des + */ + uint32_t clkrst_lp_bletimer_32k_sel:2; + /** clkrst_lp_sel_osc_slow : R/W; bitpos: [26]; default: 0; + * need_des + */ + uint32_t clkrst_lp_sel_osc_slow:1; + /** clkrst_lp_sel_osc_fast : R/W; bitpos: [27]; default: 0; + * need_des + */ + uint32_t clkrst_lp_sel_osc_fast:1; + /** clkrst_lp_sel_xtal : R/W; bitpos: [28]; default: 0; + * need_des + */ + uint32_t clkrst_lp_sel_xtal:1; + /** clkrst_lp_sel_xtal32k : R/W; bitpos: [29]; default: 0; + * need_des + */ + uint32_t clkrst_lp_sel_xtal32k:1; + /** clkrst_lp_i2c_clk_sel : R/W; bitpos: [30]; default: 0; + * need_des + */ + uint32_t clkrst_lp_i2c_clk_sel:1; + /** clkrst_lp_uart_clk_sel : R/W; bitpos: [31]; default: 0; + * need_des + */ + uint32_t clkrst_lp_uart_clk_sel:1; + }; + uint32_t val; +} lp_clkrst_lpperi_reg_t; + +/** Type of clkrst_xtal32k register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:21; + /** clkrst_rtc_sel_power_xtal32k : R/W; bitpos: [21]; default: 0; + * need_des + */ + uint32_t clkrst_rtc_sel_power_xtal32k:1; + /** clkrst_dres_xtal32k : R/W; bitpos: [24:22]; default: 3; + * need_des + */ + uint32_t clkrst_dres_xtal32k:3; + /** clkrst_dgm_xtal32k : R/W; bitpos: [27:25]; default: 3; + * need_des + */ + uint32_t clkrst_dgm_xtal32k:3; + /** clkrst_dbuf_xtal32k : R/W; bitpos: [28]; default: 0; + * need_des + */ + uint32_t clkrst_dbuf_xtal32k:1; + /** clkrst_dac_xtal32k : R/W; bitpos: [31:29]; default: 3; + * need_des + */ + uint32_t clkrst_dac_xtal32k:3; + }; + uint32_t val; +} lp_clkrst_xtal32k_reg_t; + +/** Type of clkrst_date register + * need_des + */ +typedef union { + struct { + /** clkrst_clkrst_date : R/W; bitpos: [30:0]; default: 37782064; + * need_des + */ + uint32_t clkrst_clkrst_date:31; + /** clkrst_clk_en : R/W; bitpos: [31]; default: 0; + * need_des + */ + uint32_t clkrst_clk_en:1; + }; + uint32_t val; +} lp_clkrst_date_reg_t; + + +typedef struct { + volatile lp_clkrst_lp_clk_conf_reg_t lp_clk_conf; + volatile lp_clkrst_lp_clk_po_en_reg_t lp_clk_po_en; + volatile lp_clkrst_lp_clk_en_reg_t lp_clk_en; + volatile lp_clkrst_lp_rst_en_reg_t lp_rst_en; + volatile lp_clkrst_reset_cause_reg_t reset_cause; + volatile lp_clkrst_cpu_reset_reg_t cpu_reset; + volatile lp_clkrst_fosc_cntl_reg_t fosc_cntl; + volatile lp_clkrst_rc32k_cntl_reg_t rc32k_cntl; + volatile lp_clkrst_clk_to_hp_reg_t clk_to_hp; + volatile lp_clkrst_lpmem_force_reg_t lpmem_force; + volatile lp_clkrst_lpperi_reg_t lpperi; + volatile lp_clkrst_xtal32k_reg_t xtal32k; + uint32_t reserved_030[243]; + volatile lp_clkrst_date_reg_t date; +} lp_clkrst_dev_t; + +extern lp_clkrst_dev_t LP_CLKRST; + +#ifndef __cplusplus +_Static_assert(sizeof(lp_clkrst_dev_t) == 0x400, "Invalid size of lp_clkrst_dev_t structure"); +#endif + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32h21/register/soc/lp_peri_reg.h b/components/soc/esp32h21/register/soc/lp_peri_reg.h new file mode 100644 index 00000000000..593e87e2e10 --- /dev/null +++ b/components/soc/esp32h21/register/soc/lp_peri_reg.h @@ -0,0 +1,388 @@ +/** + * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#include "soc/soc.h" +#ifdef __cplusplus +extern "C" { +#endif + +/** LPPERI_CLK_EN_REG register + * need_des + */ +#define LPPERI_CLK_EN_REG (DR_REG_LPPERI_BASE + 0x0) +/** LPPERI_RNG_CK_EN : R/W; bitpos: [24]; default: 1; + * need_des + */ +#define LPPERI_RNG_CK_EN (BIT(24)) +#define LPPERI_RNG_CK_EN_M (LPPERI_RNG_CK_EN_V << LPPERI_RNG_CK_EN_S) +#define LPPERI_RNG_CK_EN_V 0x00000001U +#define LPPERI_RNG_CK_EN_S 24 +/** LPPERI_OTP_DBG_CK_EN : R/W; bitpos: [25]; default: 1; + * need_des + */ +#define LPPERI_OTP_DBG_CK_EN (BIT(25)) +#define LPPERI_OTP_DBG_CK_EN_M (LPPERI_OTP_DBG_CK_EN_V << LPPERI_OTP_DBG_CK_EN_S) +#define LPPERI_OTP_DBG_CK_EN_V 0x00000001U +#define LPPERI_OTP_DBG_CK_EN_S 25 +/** LPPERI_LP_UART_CK_EN : R/W; bitpos: [26]; default: 1; + * need_des + */ +#define LPPERI_LP_UART_CK_EN (BIT(26)) +#define LPPERI_LP_UART_CK_EN_M (LPPERI_LP_UART_CK_EN_V << LPPERI_LP_UART_CK_EN_S) +#define LPPERI_LP_UART_CK_EN_V 0x00000001U +#define LPPERI_LP_UART_CK_EN_S 26 +/** LPPERI_LP_IO_CK_EN : R/W; bitpos: [27]; default: 1; + * need_des + */ +#define LPPERI_LP_IO_CK_EN (BIT(27)) +#define LPPERI_LP_IO_CK_EN_M (LPPERI_LP_IO_CK_EN_V << LPPERI_LP_IO_CK_EN_S) +#define LPPERI_LP_IO_CK_EN_V 0x00000001U +#define LPPERI_LP_IO_CK_EN_S 27 +/** LPPERI_LP_EXT_I2C_CK_EN : R/W; bitpos: [28]; default: 1; + * need_des + */ +#define LPPERI_LP_EXT_I2C_CK_EN (BIT(28)) +#define LPPERI_LP_EXT_I2C_CK_EN_M (LPPERI_LP_EXT_I2C_CK_EN_V << LPPERI_LP_EXT_I2C_CK_EN_S) +#define LPPERI_LP_EXT_I2C_CK_EN_V 0x00000001U +#define LPPERI_LP_EXT_I2C_CK_EN_S 28 +/** LPPERI_LP_ANA_I2C_CK_EN : R/W; bitpos: [29]; default: 1; + * need_des + */ +#define LPPERI_LP_ANA_I2C_CK_EN (BIT(29)) +#define LPPERI_LP_ANA_I2C_CK_EN_M (LPPERI_LP_ANA_I2C_CK_EN_V << LPPERI_LP_ANA_I2C_CK_EN_S) +#define LPPERI_LP_ANA_I2C_CK_EN_V 0x00000001U +#define LPPERI_LP_ANA_I2C_CK_EN_S 29 +/** LPPERI_EFUSE_CK_EN : R/W; bitpos: [30]; default: 1; + * need_des + */ +#define LPPERI_EFUSE_CK_EN (BIT(30)) +#define LPPERI_EFUSE_CK_EN_M (LPPERI_EFUSE_CK_EN_V << LPPERI_EFUSE_CK_EN_S) +#define LPPERI_EFUSE_CK_EN_V 0x00000001U +#define LPPERI_EFUSE_CK_EN_S 30 +/** LPPERI_LP_CPU_CK_EN : R/W; bitpos: [31]; default: 0; + * need_des + */ +#define LPPERI_LP_CPU_CK_EN (BIT(31)) +#define LPPERI_LP_CPU_CK_EN_M (LPPERI_LP_CPU_CK_EN_V << LPPERI_LP_CPU_CK_EN_S) +#define LPPERI_LP_CPU_CK_EN_V 0x00000001U +#define LPPERI_LP_CPU_CK_EN_S 31 + +/** LPPERI_RESET_EN_REG register + * need_des + */ +#define LPPERI_RESET_EN_REG (DR_REG_LPPERI_BASE + 0x4) +/** LPPERI_BUS_RESET_EN : WT; bitpos: [23]; default: 0; + * need_des + */ +#define LPPERI_BUS_RESET_EN (BIT(23)) +#define LPPERI_BUS_RESET_EN_M (LPPERI_BUS_RESET_EN_V << LPPERI_BUS_RESET_EN_S) +#define LPPERI_BUS_RESET_EN_V 0x00000001U +#define LPPERI_BUS_RESET_EN_S 23 +/** LPPERI_LP_BLE_TIMER_RESET_EN : R/W; bitpos: [24]; default: 0; + * need_des + */ +#define LPPERI_LP_BLE_TIMER_RESET_EN (BIT(24)) +#define LPPERI_LP_BLE_TIMER_RESET_EN_M (LPPERI_LP_BLE_TIMER_RESET_EN_V << LPPERI_LP_BLE_TIMER_RESET_EN_S) +#define LPPERI_LP_BLE_TIMER_RESET_EN_V 0x00000001U +#define LPPERI_LP_BLE_TIMER_RESET_EN_S 24 +/** LPPERI_OTP_DBG_RESET_EN : R/W; bitpos: [25]; default: 0; + * need_des + */ +#define LPPERI_OTP_DBG_RESET_EN (BIT(25)) +#define LPPERI_OTP_DBG_RESET_EN_M (LPPERI_OTP_DBG_RESET_EN_V << LPPERI_OTP_DBG_RESET_EN_S) +#define LPPERI_OTP_DBG_RESET_EN_V 0x00000001U +#define LPPERI_OTP_DBG_RESET_EN_S 25 +/** LPPERI_LP_UART_RESET_EN : R/W; bitpos: [26]; default: 0; + * need_des + */ +#define LPPERI_LP_UART_RESET_EN (BIT(26)) +#define LPPERI_LP_UART_RESET_EN_M (LPPERI_LP_UART_RESET_EN_V << LPPERI_LP_UART_RESET_EN_S) +#define LPPERI_LP_UART_RESET_EN_V 0x00000001U +#define LPPERI_LP_UART_RESET_EN_S 26 +/** LPPERI_LP_IO_RESET_EN : R/W; bitpos: [27]; default: 0; + * need_des + */ +#define LPPERI_LP_IO_RESET_EN (BIT(27)) +#define LPPERI_LP_IO_RESET_EN_M (LPPERI_LP_IO_RESET_EN_V << LPPERI_LP_IO_RESET_EN_S) +#define LPPERI_LP_IO_RESET_EN_V 0x00000001U +#define LPPERI_LP_IO_RESET_EN_S 27 +/** LPPERI_LP_EXT_I2C_RESET_EN : R/W; bitpos: [28]; default: 0; + * need_des + */ +#define LPPERI_LP_EXT_I2C_RESET_EN (BIT(28)) +#define LPPERI_LP_EXT_I2C_RESET_EN_M (LPPERI_LP_EXT_I2C_RESET_EN_V << LPPERI_LP_EXT_I2C_RESET_EN_S) +#define LPPERI_LP_EXT_I2C_RESET_EN_V 0x00000001U +#define LPPERI_LP_EXT_I2C_RESET_EN_S 28 +/** LPPERI_LP_ANA_I2C_RESET_EN : R/W; bitpos: [29]; default: 0; + * need_des + */ +#define LPPERI_LP_ANA_I2C_RESET_EN (BIT(29)) +#define LPPERI_LP_ANA_I2C_RESET_EN_M (LPPERI_LP_ANA_I2C_RESET_EN_V << LPPERI_LP_ANA_I2C_RESET_EN_S) +#define LPPERI_LP_ANA_I2C_RESET_EN_V 0x00000001U +#define LPPERI_LP_ANA_I2C_RESET_EN_S 29 +/** LPPERI_EFUSE_RESET_EN : R/W; bitpos: [30]; default: 0; + * need_des + */ +#define LPPERI_EFUSE_RESET_EN (BIT(30)) +#define LPPERI_EFUSE_RESET_EN_M (LPPERI_EFUSE_RESET_EN_V << LPPERI_EFUSE_RESET_EN_S) +#define LPPERI_EFUSE_RESET_EN_V 0x00000001U +#define LPPERI_EFUSE_RESET_EN_S 30 +/** LPPERI_LP_CPU_RESET_EN : WT; bitpos: [31]; default: 0; + * need_des + */ +#define LPPERI_LP_CPU_RESET_EN (BIT(31)) +#define LPPERI_LP_CPU_RESET_EN_M (LPPERI_LP_CPU_RESET_EN_V << LPPERI_LP_CPU_RESET_EN_S) +#define LPPERI_LP_CPU_RESET_EN_V 0x00000001U +#define LPPERI_LP_CPU_RESET_EN_S 31 + +/** LPPERI_RNG_CFG_REG register + * need_des + */ +#define LPPERI_RNG_CFG_REG (DR_REG_LPPERI_BASE + 0x8) +/** LPPERI_RNG_SAMPLE_ENABLE : R/W; bitpos: [0]; default: 0; + * need des + */ +#define LPPERI_RNG_SAMPLE_ENABLE (BIT(0)) +#define LPPERI_RNG_SAMPLE_ENABLE_M (LPPERI_RNG_SAMPLE_ENABLE_V << LPPERI_RNG_SAMPLE_ENABLE_S) +#define LPPERI_RNG_SAMPLE_ENABLE_V 0x00000001U +#define LPPERI_RNG_SAMPLE_ENABLE_S 0 +/** LPPERI_RNG_TIMER_PSCALE : R/W; bitpos: [8:1]; default: 255; + * need des + */ +#define LPPERI_RNG_TIMER_PSCALE 0x000000FFU +#define LPPERI_RNG_TIMER_PSCALE_M (LPPERI_RNG_TIMER_PSCALE_V << LPPERI_RNG_TIMER_PSCALE_S) +#define LPPERI_RNG_TIMER_PSCALE_V 0x000000FFU +#define LPPERI_RNG_TIMER_PSCALE_S 1 +/** LPPERI_RNG_TIMER_EN : R/W; bitpos: [9]; default: 1; + * need des + */ +#define LPPERI_RNG_TIMER_EN (BIT(9)) +#define LPPERI_RNG_TIMER_EN_M (LPPERI_RNG_TIMER_EN_V << LPPERI_RNG_TIMER_EN_S) +#define LPPERI_RNG_TIMER_EN_V 0x00000001U +#define LPPERI_RNG_TIMER_EN_S 9 +/** LPPERI_RTC_TIMER_EN : R/W; bitpos: [11:10]; default: 3; + * need des + */ +#define LPPERI_RTC_TIMER_EN 0x00000003U +#define LPPERI_RTC_TIMER_EN_M (LPPERI_RTC_TIMER_EN_V << LPPERI_RTC_TIMER_EN_S) +#define LPPERI_RTC_TIMER_EN_V 0x00000003U +#define LPPERI_RTC_TIMER_EN_S 10 +/** LPPERI_RNG_SAMPLE_CNT : RO; bitpos: [31:24]; default: 0; + * need des + */ +#define LPPERI_RNG_SAMPLE_CNT 0x000000FFU +#define LPPERI_RNG_SAMPLE_CNT_M (LPPERI_RNG_SAMPLE_CNT_V << LPPERI_RNG_SAMPLE_CNT_S) +#define LPPERI_RNG_SAMPLE_CNT_V 0x000000FFU +#define LPPERI_RNG_SAMPLE_CNT_S 24 + +/** LPPERI_RNG_DATA_REG register + * need_des + */ +#define LPPERI_RNG_DATA_REG (DR_REG_LPPERI_BASE + 0xc) +/** LPPERI_RND_DATA : RO; bitpos: [31:0]; default: 0; + * need_des + */ +#define LPPERI_RND_DATA 0xFFFFFFFFU +#define LPPERI_RND_DATA_M (LPPERI_RND_DATA_V << LPPERI_RND_DATA_S) +#define LPPERI_RND_DATA_V 0xFFFFFFFFU +#define LPPERI_RND_DATA_S 0 + +/** LPPERI_CPU_REG register + * need_des + */ +#define LPPERI_CPU_REG (DR_REG_LPPERI_BASE + 0x10) +/** LPPERI_LPCORE_DBGM_UNAVALIABLE : R/W; bitpos: [31]; default: 1; + * need_des + */ +#define LPPERI_LPCORE_DBGM_UNAVALIABLE (BIT(31)) +#define LPPERI_LPCORE_DBGM_UNAVALIABLE_M (LPPERI_LPCORE_DBGM_UNAVALIABLE_V << LPPERI_LPCORE_DBGM_UNAVALIABLE_S) +#define LPPERI_LPCORE_DBGM_UNAVALIABLE_V 0x00000001U +#define LPPERI_LPCORE_DBGM_UNAVALIABLE_S 31 + +/** LPPERI_BUS_TIMEOUT_REG register + * need_des + */ +#define LPPERI_BUS_TIMEOUT_REG (DR_REG_LPPERI_BASE + 0x14) +/** LPPERI_LP_PERI_TIMEOUT_THRES : R/W; bitpos: [29:14]; default: 65535; + * need_des + */ +#define LPPERI_LP_PERI_TIMEOUT_THRES 0x0000FFFFU +#define LPPERI_LP_PERI_TIMEOUT_THRES_M (LPPERI_LP_PERI_TIMEOUT_THRES_V << LPPERI_LP_PERI_TIMEOUT_THRES_S) +#define LPPERI_LP_PERI_TIMEOUT_THRES_V 0x0000FFFFU +#define LPPERI_LP_PERI_TIMEOUT_THRES_S 14 +/** LPPERI_LP_PERI_TIMEOUT_INT_CLEAR : WT; bitpos: [30]; default: 0; + * need_des + */ +#define LPPERI_LP_PERI_TIMEOUT_INT_CLEAR (BIT(30)) +#define LPPERI_LP_PERI_TIMEOUT_INT_CLEAR_M (LPPERI_LP_PERI_TIMEOUT_INT_CLEAR_V << LPPERI_LP_PERI_TIMEOUT_INT_CLEAR_S) +#define LPPERI_LP_PERI_TIMEOUT_INT_CLEAR_V 0x00000001U +#define LPPERI_LP_PERI_TIMEOUT_INT_CLEAR_S 30 +/** LPPERI_LP_PERI_TIMEOUT_PROTECT_EN : R/W; bitpos: [31]; default: 1; + * need_des + */ +#define LPPERI_LP_PERI_TIMEOUT_PROTECT_EN (BIT(31)) +#define LPPERI_LP_PERI_TIMEOUT_PROTECT_EN_M (LPPERI_LP_PERI_TIMEOUT_PROTECT_EN_V << LPPERI_LP_PERI_TIMEOUT_PROTECT_EN_S) +#define LPPERI_LP_PERI_TIMEOUT_PROTECT_EN_V 0x00000001U +#define LPPERI_LP_PERI_TIMEOUT_PROTECT_EN_S 31 + +/** LPPERI_BUS_TIMEOUT_ADDR_REG register + * need_des + */ +#define LPPERI_BUS_TIMEOUT_ADDR_REG (DR_REG_LPPERI_BASE + 0x18) +/** LPPERI_LP_PERI_TIMEOUT_ADDR : RO; bitpos: [31:0]; default: 0; + * need_des + */ +#define LPPERI_LP_PERI_TIMEOUT_ADDR 0xFFFFFFFFU +#define LPPERI_LP_PERI_TIMEOUT_ADDR_M (LPPERI_LP_PERI_TIMEOUT_ADDR_V << LPPERI_LP_PERI_TIMEOUT_ADDR_S) +#define LPPERI_LP_PERI_TIMEOUT_ADDR_V 0xFFFFFFFFU +#define LPPERI_LP_PERI_TIMEOUT_ADDR_S 0 + +/** LPPERI_BUS_TIMEOUT_UID_REG register + * need_des + */ +#define LPPERI_BUS_TIMEOUT_UID_REG (DR_REG_LPPERI_BASE + 0x1c) +/** LPPERI_LP_PERI_TIMEOUT_UID : RO; bitpos: [6:0]; default: 0; + * need_des + */ +#define LPPERI_LP_PERI_TIMEOUT_UID 0x0000007FU +#define LPPERI_LP_PERI_TIMEOUT_UID_M (LPPERI_LP_PERI_TIMEOUT_UID_V << LPPERI_LP_PERI_TIMEOUT_UID_S) +#define LPPERI_LP_PERI_TIMEOUT_UID_V 0x0000007FU +#define LPPERI_LP_PERI_TIMEOUT_UID_S 0 + +/** LPPERI_MEM_CTRL_REG register + * need_des + */ +#define LPPERI_MEM_CTRL_REG (DR_REG_LPPERI_BASE + 0x20) +/** LPPERI_UART_WAKEUP_FLAG_CLR : WT; bitpos: [0]; default: 0; + * need_des + */ +#define LPPERI_UART_WAKEUP_FLAG_CLR (BIT(0)) +#define LPPERI_UART_WAKEUP_FLAG_CLR_M (LPPERI_UART_WAKEUP_FLAG_CLR_V << LPPERI_UART_WAKEUP_FLAG_CLR_S) +#define LPPERI_UART_WAKEUP_FLAG_CLR_V 0x00000001U +#define LPPERI_UART_WAKEUP_FLAG_CLR_S 0 +/** LPPERI_UART_WAKEUP_FLAG : R/WTC/SS; bitpos: [1]; default: 0; + * need_des + */ +#define LPPERI_UART_WAKEUP_FLAG (BIT(1)) +#define LPPERI_UART_WAKEUP_FLAG_M (LPPERI_UART_WAKEUP_FLAG_V << LPPERI_UART_WAKEUP_FLAG_S) +#define LPPERI_UART_WAKEUP_FLAG_V 0x00000001U +#define LPPERI_UART_WAKEUP_FLAG_S 1 +/** LPPERI_UART_WAKEUP_EN : R/W; bitpos: [29]; default: 0; + * need_des + */ +#define LPPERI_UART_WAKEUP_EN (BIT(29)) +#define LPPERI_UART_WAKEUP_EN_M (LPPERI_UART_WAKEUP_EN_V << LPPERI_UART_WAKEUP_EN_S) +#define LPPERI_UART_WAKEUP_EN_V 0x00000001U +#define LPPERI_UART_WAKEUP_EN_S 29 +/** LPPERI_UART_MEM_FORCE_PD : R/W; bitpos: [30]; default: 0; + * need_des + */ +#define LPPERI_UART_MEM_FORCE_PD (BIT(30)) +#define LPPERI_UART_MEM_FORCE_PD_M (LPPERI_UART_MEM_FORCE_PD_V << LPPERI_UART_MEM_FORCE_PD_S) +#define LPPERI_UART_MEM_FORCE_PD_V 0x00000001U +#define LPPERI_UART_MEM_FORCE_PD_S 30 +/** LPPERI_UART_MEM_FORCE_PU : R/W; bitpos: [31]; default: 1; + * need_des + */ +#define LPPERI_UART_MEM_FORCE_PU (BIT(31)) +#define LPPERI_UART_MEM_FORCE_PU_M (LPPERI_UART_MEM_FORCE_PU_V << LPPERI_UART_MEM_FORCE_PU_S) +#define LPPERI_UART_MEM_FORCE_PU_V 0x00000001U +#define LPPERI_UART_MEM_FORCE_PU_S 31 + +/** LPPERI_INTERRUPT_SOURCE_REG register + * need_des + */ +#define LPPERI_INTERRUPT_SOURCE_REG (DR_REG_LPPERI_BASE + 0x24) +/** LPPERI_LP_INTERRUPT_SOURCE : RO; bitpos: [5:0]; default: 0; + * BIT5~BIT0: pmu_lp_int, modem_lp_int, lp_timer_lp_int, lp_uart_int, lp_i2c_int, + * lp_io_int + */ +#define LPPERI_LP_INTERRUPT_SOURCE 0x0000003FU +#define LPPERI_LP_INTERRUPT_SOURCE_M (LPPERI_LP_INTERRUPT_SOURCE_V << LPPERI_LP_INTERRUPT_SOURCE_S) +#define LPPERI_LP_INTERRUPT_SOURCE_V 0x0000003FU +#define LPPERI_LP_INTERRUPT_SOURCE_S 0 + +/** LPPERI_DEBUG_SEL0_REG register + * need des + */ +#define LPPERI_DEBUG_SEL0_REG (DR_REG_LPPERI_BASE + 0x28) +/** LPPERI_DEBUG_SEL0 : R/W; bitpos: [6:0]; default: 0; + * need des + */ +#define LPPERI_DEBUG_SEL0 0x0000007FU +#define LPPERI_DEBUG_SEL0_M (LPPERI_DEBUG_SEL0_V << LPPERI_DEBUG_SEL0_S) +#define LPPERI_DEBUG_SEL0_V 0x0000007FU +#define LPPERI_DEBUG_SEL0_S 0 +/** LPPERI_DEBUG_SEL1 : R/W; bitpos: [13:7]; default: 0; + * need des + */ +#define LPPERI_DEBUG_SEL1 0x0000007FU +#define LPPERI_DEBUG_SEL1_M (LPPERI_DEBUG_SEL1_V << LPPERI_DEBUG_SEL1_S) +#define LPPERI_DEBUG_SEL1_V 0x0000007FU +#define LPPERI_DEBUG_SEL1_S 7 +/** LPPERI_DEBUG_SEL2 : R/W; bitpos: [20:14]; default: 0; + * need des + */ +#define LPPERI_DEBUG_SEL2 0x0000007FU +#define LPPERI_DEBUG_SEL2_M (LPPERI_DEBUG_SEL2_V << LPPERI_DEBUG_SEL2_S) +#define LPPERI_DEBUG_SEL2_V 0x0000007FU +#define LPPERI_DEBUG_SEL2_S 14 +/** LPPERI_DEBUG_SEL3 : R/W; bitpos: [27:21]; default: 0; + * need des + */ +#define LPPERI_DEBUG_SEL3 0x0000007FU +#define LPPERI_DEBUG_SEL3_M (LPPERI_DEBUG_SEL3_V << LPPERI_DEBUG_SEL3_S) +#define LPPERI_DEBUG_SEL3_V 0x0000007FU +#define LPPERI_DEBUG_SEL3_S 21 + +/** LPPERI_DEBUG_SEL1_REG register + * need des + */ +#define LPPERI_DEBUG_SEL1_REG (DR_REG_LPPERI_BASE + 0x2c) +/** LPPERI_DEBUG_SEL4 : R/W; bitpos: [6:0]; default: 0; + * need des + */ +#define LPPERI_DEBUG_SEL4 0x0000007FU +#define LPPERI_DEBUG_SEL4_M (LPPERI_DEBUG_SEL4_V << LPPERI_DEBUG_SEL4_S) +#define LPPERI_DEBUG_SEL4_V 0x0000007FU +#define LPPERI_DEBUG_SEL4_S 0 + +/** LPPERI_RNG_DATA_SYNC_REG register + * rng result sync register + */ +#define LPPERI_RNG_DATA_SYNC_REG (DR_REG_LPPERI_BASE + 0x30) +/** LPPERI_RND_SYNC_DATA : RO; bitpos: [31:0]; default: 0; + * get rng sync result + */ +#define LPPERI_RND_SYNC_DATA 0xFFFFFFFFU +#define LPPERI_RND_SYNC_DATA_M (LPPERI_RND_SYNC_DATA_V << LPPERI_RND_SYNC_DATA_S) +#define LPPERI_RND_SYNC_DATA_V 0xFFFFFFFFU +#define LPPERI_RND_SYNC_DATA_S 0 + +/** LPPERI_DATE_REG register + * need_des + */ +#define LPPERI_DATE_REG (DR_REG_LPPERI_BASE + 0x3fc) +/** LPPERI_LPPERI_DATE : R/W; bitpos: [30:0]; default: 37781793; + * need_des + */ +#define LPPERI_LPPERI_DATE 0x7FFFFFFFU +#define LPPERI_LPPERI_DATE_M (LPPERI_LPPERI_DATE_V << LPPERI_LPPERI_DATE_S) +#define LPPERI_LPPERI_DATE_V 0x7FFFFFFFU +#define LPPERI_LPPERI_DATE_S 0 +/** LPPERI_CLK_EN : R/W; bitpos: [31]; default: 0; + * need_des + */ +#define LPPERI_CLK_EN (BIT(31)) +#define LPPERI_CLK_EN_M (LPPERI_CLK_EN_V << LPPERI_CLK_EN_S) +#define LPPERI_CLK_EN_V 0x00000001U +#define LPPERI_CLK_EN_S 31 + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32h21/register/soc/lp_peri_struct.h b/components/soc/esp32h21/register/soc/lp_peri_struct.h new file mode 100644 index 00000000000..4ccec691b91 --- /dev/null +++ b/components/soc/esp32h21/register/soc/lp_peri_struct.h @@ -0,0 +1,352 @@ +/** + * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#ifdef __cplusplus +extern "C" { +#endif + +/** Group: configure_register */ +/** Type of clk_en register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:24; + /** rng_ck_en : R/W; bitpos: [24]; default: 1; + * need_des + */ + uint32_t rng_ck_en:1; + /** otp_dbg_ck_en : R/W; bitpos: [25]; default: 1; + * need_des + */ + uint32_t otp_dbg_ck_en:1; + /** lp_uart_ck_en : R/W; bitpos: [26]; default: 1; + * need_des + */ + uint32_t lp_uart_ck_en:1; + /** lp_io_ck_en : R/W; bitpos: [27]; default: 1; + * need_des + */ + uint32_t lp_io_ck_en:1; + /** lp_ext_i2c_ck_en : R/W; bitpos: [28]; default: 1; + * need_des + */ + uint32_t lp_ext_i2c_ck_en:1; + /** lp_ana_i2c_ck_en : R/W; bitpos: [29]; default: 1; + * need_des + */ + uint32_t lp_ana_i2c_ck_en:1; + /** efuse_ck_en : R/W; bitpos: [30]; default: 1; + * need_des + */ + uint32_t efuse_ck_en:1; + /** lp_cpu_ck_en : R/W; bitpos: [31]; default: 0; + * need_des + */ + uint32_t lp_cpu_ck_en:1; + }; + uint32_t val; +} lpperi_clk_en_reg_t; + +/** Type of reset_en register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:23; + /** bus_reset_en : WT; bitpos: [23]; default: 0; + * need_des + */ + uint32_t bus_reset_en:1; + /** lp_ble_timer_reset_en : R/W; bitpos: [24]; default: 0; + * need_des + */ + uint32_t lp_ble_timer_reset_en:1; + /** otp_dbg_reset_en : R/W; bitpos: [25]; default: 0; + * need_des + */ + uint32_t otp_dbg_reset_en:1; + /** lp_uart_reset_en : R/W; bitpos: [26]; default: 0; + * need_des + */ + uint32_t lp_uart_reset_en:1; + /** lp_io_reset_en : R/W; bitpos: [27]; default: 0; + * need_des + */ + uint32_t lp_io_reset_en:1; + /** lp_ext_i2c_reset_en : R/W; bitpos: [28]; default: 0; + * need_des + */ + uint32_t lp_ext_i2c_reset_en:1; + /** lp_ana_i2c_reset_en : R/W; bitpos: [29]; default: 0; + * need_des + */ + uint32_t lp_ana_i2c_reset_en:1; + /** efuse_reset_en : R/W; bitpos: [30]; default: 0; + * need_des + */ + uint32_t efuse_reset_en:1; + /** lp_cpu_reset_en : WT; bitpos: [31]; default: 0; + * need_des + */ + uint32_t lp_cpu_reset_en:1; + }; + uint32_t val; +} lpperi_reset_en_reg_t; + +/** Type of rng_cfg register + * need_des + */ +typedef union { + struct { + /** rng_sample_enable : R/W; bitpos: [0]; default: 0; + * need des + */ + uint32_t rng_sample_enable:1; + /** rng_timer_pscale : R/W; bitpos: [8:1]; default: 255; + * need des + */ + uint32_t rng_timer_pscale:8; + /** rng_timer_en : R/W; bitpos: [9]; default: 1; + * need des + */ + uint32_t rng_timer_en:1; + /** rtc_timer_en : R/W; bitpos: [11:10]; default: 3; + * need des + */ + uint32_t rtc_timer_en:2; + uint32_t reserved_12:12; + /** rng_sample_cnt : RO; bitpos: [31:24]; default: 0; + * need des + */ + uint32_t rng_sample_cnt:8; + }; + uint32_t val; +} lpperi_rng_cfg_reg_t; + +/** Type of rng_data register + * need_des + */ +typedef union { + struct { + /** rnd_data : RO; bitpos: [31:0]; default: 0; + * need_des + */ + uint32_t rnd_data:32; + }; + uint32_t val; +} lpperi_rng_data_reg_t; + +/** Type of cpu register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:31; + /** lpcore_dbgm_unavaliable : R/W; bitpos: [31]; default: 1; + * need_des + */ + uint32_t lpcore_dbgm_unavaliable:1; + }; + uint32_t val; +} lpperi_cpu_reg_t; + +/** Type of bus_timeout register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:14; + /** lp_peri_timeout_thres : R/W; bitpos: [29:14]; default: 65535; + * need_des + */ + uint32_t lp_peri_timeout_thres:16; + /** lp_peri_timeout_int_clear : WT; bitpos: [30]; default: 0; + * need_des + */ + uint32_t lp_peri_timeout_int_clear:1; + /** lp_peri_timeout_protect_en : R/W; bitpos: [31]; default: 1; + * need_des + */ + uint32_t lp_peri_timeout_protect_en:1; + }; + uint32_t val; +} lpperi_bus_timeout_reg_t; + +/** Type of bus_timeout_addr register + * need_des + */ +typedef union { + struct { + /** lp_peri_timeout_addr : RO; bitpos: [31:0]; default: 0; + * need_des + */ + uint32_t lp_peri_timeout_addr:32; + }; + uint32_t val; +} lpperi_bus_timeout_addr_reg_t; + +/** Type of bus_timeout_uid register + * need_des + */ +typedef union { + struct { + /** lp_peri_timeout_uid : RO; bitpos: [6:0]; default: 0; + * need_des + */ + uint32_t lp_peri_timeout_uid:7; + uint32_t reserved_7:25; + }; + uint32_t val; +} lpperi_bus_timeout_uid_reg_t; + +/** Type of mem_ctrl register + * need_des + */ +typedef union { + struct { + /** uart_wakeup_flag_clr : WT; bitpos: [0]; default: 0; + * need_des + */ + uint32_t uart_wakeup_flag_clr:1; + /** uart_wakeup_flag : R/WTC/SS; bitpos: [1]; default: 0; + * need_des + */ + uint32_t uart_wakeup_flag:1; + uint32_t reserved_2:27; + /** uart_wakeup_en : R/W; bitpos: [29]; default: 0; + * need_des + */ + uint32_t uart_wakeup_en:1; + /** uart_mem_force_pd : R/W; bitpos: [30]; default: 0; + * need_des + */ + uint32_t uart_mem_force_pd:1; + /** uart_mem_force_pu : R/W; bitpos: [31]; default: 1; + * need_des + */ + uint32_t uart_mem_force_pu:1; + }; + uint32_t val; +} lpperi_mem_ctrl_reg_t; + +/** Type of interrupt_source register + * need_des + */ +typedef union { + struct { + /** lp_interrupt_source : RO; bitpos: [5:0]; default: 0; + * BIT5~BIT0: pmu_lp_int, modem_lp_int, lp_timer_lp_int, lp_uart_int, lp_i2c_int, + * lp_io_int + */ + uint32_t lp_interrupt_source:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} lpperi_interrupt_source_reg_t; + +/** Type of debug_sel0 register + * need des + */ +typedef union { + struct { + /** debug_sel0 : R/W; bitpos: [6:0]; default: 0; + * need des + */ + uint32_t debug_sel0:7; + /** debug_sel1 : R/W; bitpos: [13:7]; default: 0; + * need des + */ + uint32_t debug_sel1:7; + /** debug_sel2 : R/W; bitpos: [20:14]; default: 0; + * need des + */ + uint32_t debug_sel2:7; + /** debug_sel3 : R/W; bitpos: [27:21]; default: 0; + * need des + */ + uint32_t debug_sel3:7; + uint32_t reserved_28:4; + }; + uint32_t val; +} lpperi_debug_sel0_reg_t; + +/** Type of debug_sel1 register + * need des + */ +typedef union { + struct { + /** debug_sel4 : R/W; bitpos: [6:0]; default: 0; + * need des + */ + uint32_t debug_sel4:7; + uint32_t reserved_7:25; + }; + uint32_t val; +} lpperi_debug_sel1_reg_t; + +/** Type of rng_data_sync register + * rng result sync register + */ +typedef union { + struct { + /** rnd_sync_data : RO; bitpos: [31:0]; default: 0; + * get rng sync result + */ + uint32_t rnd_sync_data:32; + }; + uint32_t val; +} lpperi_rng_data_sync_reg_t; + + +/** Group: Version register */ +/** Type of date register + * need_des + */ +typedef union { + struct { + /** lpperi_date : R/W; bitpos: [30:0]; default: 37781793; + * need_des + */ + uint32_t lpperi_date:31; + /** clk_en : R/W; bitpos: [31]; default: 0; + * need_des + */ + uint32_t clk_en:1; + }; + uint32_t val; +} lpperi_date_reg_t; + + +typedef struct { + volatile lpperi_clk_en_reg_t clk_en; + volatile lpperi_reset_en_reg_t reset_en; + volatile lpperi_rng_cfg_reg_t rng_cfg; + volatile lpperi_rng_data_reg_t rng_data; + volatile lpperi_cpu_reg_t cpu; + volatile lpperi_bus_timeout_reg_t bus_timeout; + volatile lpperi_bus_timeout_addr_reg_t bus_timeout_addr; + volatile lpperi_bus_timeout_uid_reg_t bus_timeout_uid; + volatile lpperi_mem_ctrl_reg_t mem_ctrl; + volatile lpperi_interrupt_source_reg_t interrupt_source; + volatile lpperi_debug_sel0_reg_t debug_sel0; + volatile lpperi_debug_sel1_reg_t debug_sel1; + volatile lpperi_rng_data_sync_reg_t rng_data_sync; + uint32_t reserved_034[242]; + volatile lpperi_date_reg_t date; +} lpperi_dev_t; + +extern lpperi_dev_t LPPERI; + +#ifndef __cplusplus +_Static_assert(sizeof(lpperi_dev_t) == 0x400, "Invalid size of lpperi_dev_t structure"); +#endif + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32h21/register/soc/lp_wdt_reg.h b/components/soc/esp32h21/register/soc/lp_wdt_reg.h new file mode 100644 index 00000000000..d2b4cf0022a --- /dev/null +++ b/components/soc/esp32h21/register/soc/lp_wdt_reg.h @@ -0,0 +1,350 @@ +/** + * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#include "soc/soc.h" +#ifdef __cplusplus +extern "C" { +#endif + +/** LP_WDT_CONFIG0_REG register + * need_des + */ +#define LP_WDT_CONFIG0_REG (DR_REG_LP_WDT_BASE + 0x0) +/** LP_WDT_WDT_PAUSE_IN_SLP : R/W; bitpos: [9]; default: 1; + * need_des + */ +#define LP_WDT_WDT_PAUSE_IN_SLP (BIT(9)) +#define LP_WDT_WDT_PAUSE_IN_SLP_M (LP_WDT_WDT_PAUSE_IN_SLP_V << LP_WDT_WDT_PAUSE_IN_SLP_S) +#define LP_WDT_WDT_PAUSE_IN_SLP_V 0x00000001U +#define LP_WDT_WDT_PAUSE_IN_SLP_S 9 +/** LP_WDT_WDT_APPCPU_RESET_EN : R/W; bitpos: [10]; default: 0; + * need_des + */ +#define LP_WDT_WDT_APPCPU_RESET_EN (BIT(10)) +#define LP_WDT_WDT_APPCPU_RESET_EN_M (LP_WDT_WDT_APPCPU_RESET_EN_V << LP_WDT_WDT_APPCPU_RESET_EN_S) +#define LP_WDT_WDT_APPCPU_RESET_EN_V 0x00000001U +#define LP_WDT_WDT_APPCPU_RESET_EN_S 10 +/** LP_WDT_WDT_PROCPU_RESET_EN : R/W; bitpos: [11]; default: 0; + * need_des + */ +#define LP_WDT_WDT_PROCPU_RESET_EN (BIT(11)) +#define LP_WDT_WDT_PROCPU_RESET_EN_M (LP_WDT_WDT_PROCPU_RESET_EN_V << LP_WDT_WDT_PROCPU_RESET_EN_S) +#define LP_WDT_WDT_PROCPU_RESET_EN_V 0x00000001U +#define LP_WDT_WDT_PROCPU_RESET_EN_S 11 +/** LP_WDT_WDT_FLASHBOOT_MOD_EN : R/W; bitpos: [12]; default: 1; + * need_des + */ +#define LP_WDT_WDT_FLASHBOOT_MOD_EN (BIT(12)) +#define LP_WDT_WDT_FLASHBOOT_MOD_EN_M (LP_WDT_WDT_FLASHBOOT_MOD_EN_V << LP_WDT_WDT_FLASHBOOT_MOD_EN_S) +#define LP_WDT_WDT_FLASHBOOT_MOD_EN_V 0x00000001U +#define LP_WDT_WDT_FLASHBOOT_MOD_EN_S 12 +/** LP_WDT_WDT_SYS_RESET_LENGTH : R/W; bitpos: [15:13]; default: 1; + * need_des + */ +#define LP_WDT_WDT_SYS_RESET_LENGTH 0x00000007U +#define LP_WDT_WDT_SYS_RESET_LENGTH_M (LP_WDT_WDT_SYS_RESET_LENGTH_V << LP_WDT_WDT_SYS_RESET_LENGTH_S) +#define LP_WDT_WDT_SYS_RESET_LENGTH_V 0x00000007U +#define LP_WDT_WDT_SYS_RESET_LENGTH_S 13 +/** LP_WDT_WDT_CPU_RESET_LENGTH : R/W; bitpos: [18:16]; default: 1; + * need_des + */ +#define LP_WDT_WDT_CPU_RESET_LENGTH 0x00000007U +#define LP_WDT_WDT_CPU_RESET_LENGTH_M (LP_WDT_WDT_CPU_RESET_LENGTH_V << LP_WDT_WDT_CPU_RESET_LENGTH_S) +#define LP_WDT_WDT_CPU_RESET_LENGTH_V 0x00000007U +#define LP_WDT_WDT_CPU_RESET_LENGTH_S 16 +/** LP_WDT_WDT_STG3 : R/W; bitpos: [21:19]; default: 0; + * need_des + */ +#define LP_WDT_WDT_STG3 0x00000007U +#define LP_WDT_WDT_STG3_M (LP_WDT_WDT_STG3_V << LP_WDT_WDT_STG3_S) +#define LP_WDT_WDT_STG3_V 0x00000007U +#define LP_WDT_WDT_STG3_S 19 +/** LP_WDT_WDT_STG2 : R/W; bitpos: [24:22]; default: 0; + * need_des + */ +#define LP_WDT_WDT_STG2 0x00000007U +#define LP_WDT_WDT_STG2_M (LP_WDT_WDT_STG2_V << LP_WDT_WDT_STG2_S) +#define LP_WDT_WDT_STG2_V 0x00000007U +#define LP_WDT_WDT_STG2_S 22 +/** LP_WDT_WDT_STG1 : R/W; bitpos: [27:25]; default: 0; + * need_des + */ +#define LP_WDT_WDT_STG1 0x00000007U +#define LP_WDT_WDT_STG1_M (LP_WDT_WDT_STG1_V << LP_WDT_WDT_STG1_S) +#define LP_WDT_WDT_STG1_V 0x00000007U +#define LP_WDT_WDT_STG1_S 25 +/** LP_WDT_WDT_STG0 : R/W; bitpos: [30:28]; default: 0; + * need_des + */ +#define LP_WDT_WDT_STG0 0x00000007U +#define LP_WDT_WDT_STG0_M (LP_WDT_WDT_STG0_V << LP_WDT_WDT_STG0_S) +#define LP_WDT_WDT_STG0_V 0x00000007U +#define LP_WDT_WDT_STG0_S 28 +/** LP_WDT_WDT_EN : R/W; bitpos: [31]; default: 0; + * need_des + */ +#define LP_WDT_WDT_EN (BIT(31)) +#define LP_WDT_WDT_EN_M (LP_WDT_WDT_EN_V << LP_WDT_WDT_EN_S) +#define LP_WDT_WDT_EN_V 0x00000001U +#define LP_WDT_WDT_EN_S 31 + +/** LP_WDT_CONFIG1_REG register + * need_des + */ +#define LP_WDT_CONFIG1_REG (DR_REG_LP_WDT_BASE + 0x4) +/** LP_WDT_WDT_STG0_HOLD : R/W; bitpos: [31:0]; default: 200000; + * need_des + */ +#define LP_WDT_WDT_STG0_HOLD 0xFFFFFFFFU +#define LP_WDT_WDT_STG0_HOLD_M (LP_WDT_WDT_STG0_HOLD_V << LP_WDT_WDT_STG0_HOLD_S) +#define LP_WDT_WDT_STG0_HOLD_V 0xFFFFFFFFU +#define LP_WDT_WDT_STG0_HOLD_S 0 + +/** LP_WDT_CONFIG2_REG register + * need_des + */ +#define LP_WDT_CONFIG2_REG (DR_REG_LP_WDT_BASE + 0x8) +/** LP_WDT_WDT_STG1_HOLD : R/W; bitpos: [31:0]; default: 80000; + * need_des + */ +#define LP_WDT_WDT_STG1_HOLD 0xFFFFFFFFU +#define LP_WDT_WDT_STG1_HOLD_M (LP_WDT_WDT_STG1_HOLD_V << LP_WDT_WDT_STG1_HOLD_S) +#define LP_WDT_WDT_STG1_HOLD_V 0xFFFFFFFFU +#define LP_WDT_WDT_STG1_HOLD_S 0 + +/** LP_WDT_CONFIG3_REG register + * need_des + */ +#define LP_WDT_CONFIG3_REG (DR_REG_LP_WDT_BASE + 0xc) +/** LP_WDT_WDT_STG2_HOLD : R/W; bitpos: [31:0]; default: 4095; + * need_des + */ +#define LP_WDT_WDT_STG2_HOLD 0xFFFFFFFFU +#define LP_WDT_WDT_STG2_HOLD_M (LP_WDT_WDT_STG2_HOLD_V << LP_WDT_WDT_STG2_HOLD_S) +#define LP_WDT_WDT_STG2_HOLD_V 0xFFFFFFFFU +#define LP_WDT_WDT_STG2_HOLD_S 0 + +/** LP_WDT_CONFIG4_REG register + * need_des + */ +#define LP_WDT_CONFIG4_REG (DR_REG_LP_WDT_BASE + 0x10) +/** LP_WDT_WDT_STG3_HOLD : R/W; bitpos: [31:0]; default: 4095; + * need_des + */ +#define LP_WDT_WDT_STG3_HOLD 0xFFFFFFFFU +#define LP_WDT_WDT_STG3_HOLD_M (LP_WDT_WDT_STG3_HOLD_V << LP_WDT_WDT_STG3_HOLD_S) +#define LP_WDT_WDT_STG3_HOLD_V 0xFFFFFFFFU +#define LP_WDT_WDT_STG3_HOLD_S 0 + +/** LP_WDT_CONFIG5_REG register + * need_des + */ +#define LP_WDT_CONFIG5_REG (DR_REG_LP_WDT_BASE + 0x14) +/** LP_WDT_CHIP_RESET_TARGET : R/W; bitpos: [7:0]; default: 255; + * need_des + */ +#define LP_WDT_CHIP_RESET_TARGET 0x000000FFU +#define LP_WDT_CHIP_RESET_TARGET_M (LP_WDT_CHIP_RESET_TARGET_V << LP_WDT_CHIP_RESET_TARGET_S) +#define LP_WDT_CHIP_RESET_TARGET_V 0x000000FFU +#define LP_WDT_CHIP_RESET_TARGET_S 0 +/** LP_WDT_CHIP_RESET_EN : R/W; bitpos: [8]; default: 0; + * need_des + */ +#define LP_WDT_CHIP_RESET_EN (BIT(8)) +#define LP_WDT_CHIP_RESET_EN_M (LP_WDT_CHIP_RESET_EN_V << LP_WDT_CHIP_RESET_EN_S) +#define LP_WDT_CHIP_RESET_EN_V 0x00000001U +#define LP_WDT_CHIP_RESET_EN_S 8 +/** LP_WDT_CHIP_RESET_KEY : R/W; bitpos: [16:9]; default: 0; + * need_des + */ +#define LP_WDT_CHIP_RESET_KEY 0x000000FFU +#define LP_WDT_CHIP_RESET_KEY_M (LP_WDT_CHIP_RESET_KEY_V << LP_WDT_CHIP_RESET_KEY_S) +#define LP_WDT_CHIP_RESET_KEY_V 0x000000FFU +#define LP_WDT_CHIP_RESET_KEY_S 9 + +/** LP_WDT_FEED_REG register + * need_des + */ +#define LP_WDT_FEED_REG (DR_REG_LP_WDT_BASE + 0x18) +/** LP_WDT_RTC_WDT_FEED : WT; bitpos: [31]; default: 0; + * need_des + */ +#define LP_WDT_RTC_WDT_FEED (BIT(31)) +#define LP_WDT_RTC_WDT_FEED_M (LP_WDT_RTC_WDT_FEED_V << LP_WDT_RTC_WDT_FEED_S) +#define LP_WDT_RTC_WDT_FEED_V 0x00000001U +#define LP_WDT_RTC_WDT_FEED_S 31 + +/** LP_WDT_WPROTECT_REG register + * need_des + */ +#define LP_WDT_WPROTECT_REG (DR_REG_LP_WDT_BASE + 0x1c) +/** LP_WDT_WDT_WKEY : R/W; bitpos: [31:0]; default: 0; + * need_des + */ +#define LP_WDT_WDT_WKEY 0xFFFFFFFFU +#define LP_WDT_WDT_WKEY_M (LP_WDT_WDT_WKEY_V << LP_WDT_WDT_WKEY_S) +#define LP_WDT_WDT_WKEY_V 0xFFFFFFFFU +#define LP_WDT_WDT_WKEY_S 0 + +/** LP_WDT_SWD_CONFIG_REG register + * need_des + */ +#define LP_WDT_SWD_CONFIG_REG (DR_REG_LP_WDT_BASE + 0x20) +/** LP_WDT_SWD_RESET_FLAG : RO; bitpos: [0]; default: 0; + * need_des + */ +#define LP_WDT_SWD_RESET_FLAG (BIT(0)) +#define LP_WDT_SWD_RESET_FLAG_M (LP_WDT_SWD_RESET_FLAG_V << LP_WDT_SWD_RESET_FLAG_S) +#define LP_WDT_SWD_RESET_FLAG_V 0x00000001U +#define LP_WDT_SWD_RESET_FLAG_S 0 +/** LP_WDT_SWD_AUTO_FEED_EN : R/W; bitpos: [18]; default: 0; + * need_des + */ +#define LP_WDT_SWD_AUTO_FEED_EN (BIT(18)) +#define LP_WDT_SWD_AUTO_FEED_EN_M (LP_WDT_SWD_AUTO_FEED_EN_V << LP_WDT_SWD_AUTO_FEED_EN_S) +#define LP_WDT_SWD_AUTO_FEED_EN_V 0x00000001U +#define LP_WDT_SWD_AUTO_FEED_EN_S 18 +/** LP_WDT_SWD_RST_FLAG_CLR : WT; bitpos: [19]; default: 0; + * need_des + */ +#define LP_WDT_SWD_RST_FLAG_CLR (BIT(19)) +#define LP_WDT_SWD_RST_FLAG_CLR_M (LP_WDT_SWD_RST_FLAG_CLR_V << LP_WDT_SWD_RST_FLAG_CLR_S) +#define LP_WDT_SWD_RST_FLAG_CLR_V 0x00000001U +#define LP_WDT_SWD_RST_FLAG_CLR_S 19 +/** LP_WDT_SWD_SIGNAL_WIDTH : R/W; bitpos: [29:20]; default: 300; + * need_des + */ +#define LP_WDT_SWD_SIGNAL_WIDTH 0x000003FFU +#define LP_WDT_SWD_SIGNAL_WIDTH_M (LP_WDT_SWD_SIGNAL_WIDTH_V << LP_WDT_SWD_SIGNAL_WIDTH_S) +#define LP_WDT_SWD_SIGNAL_WIDTH_V 0x000003FFU +#define LP_WDT_SWD_SIGNAL_WIDTH_S 20 +/** LP_WDT_SWD_DISABLE : R/W; bitpos: [30]; default: 0; + * need_des + */ +#define LP_WDT_SWD_DISABLE (BIT(30)) +#define LP_WDT_SWD_DISABLE_M (LP_WDT_SWD_DISABLE_V << LP_WDT_SWD_DISABLE_S) +#define LP_WDT_SWD_DISABLE_V 0x00000001U +#define LP_WDT_SWD_DISABLE_S 30 +/** LP_WDT_SWD_FEED : WT; bitpos: [31]; default: 0; + * need_des + */ +#define LP_WDT_SWD_FEED (BIT(31)) +#define LP_WDT_SWD_FEED_M (LP_WDT_SWD_FEED_V << LP_WDT_SWD_FEED_S) +#define LP_WDT_SWD_FEED_V 0x00000001U +#define LP_WDT_SWD_FEED_S 31 + +/** LP_WDT_SWD_WPROTECT_REG register + * need_des + */ +#define LP_WDT_SWD_WPROTECT_REG (DR_REG_LP_WDT_BASE + 0x24) +/** LP_WDT_SWD_WKEY : R/W; bitpos: [31:0]; default: 0; + * need_des + */ +#define LP_WDT_SWD_WKEY 0xFFFFFFFFU +#define LP_WDT_SWD_WKEY_M (LP_WDT_SWD_WKEY_V << LP_WDT_SWD_WKEY_S) +#define LP_WDT_SWD_WKEY_V 0xFFFFFFFFU +#define LP_WDT_SWD_WKEY_S 0 + +/** LP_WDT_INT_RAW_REG register + * need_des + */ +#define LP_WDT_INT_RAW_REG (DR_REG_LP_WDT_BASE + 0x28) +/** LP_WDT_SUPER_WDT_INT_RAW : R/WTC/SS; bitpos: [30]; default: 0; + * need_des + */ +#define LP_WDT_SUPER_WDT_INT_RAW (BIT(30)) +#define LP_WDT_SUPER_WDT_INT_RAW_M (LP_WDT_SUPER_WDT_INT_RAW_V << LP_WDT_SUPER_WDT_INT_RAW_S) +#define LP_WDT_SUPER_WDT_INT_RAW_V 0x00000001U +#define LP_WDT_SUPER_WDT_INT_RAW_S 30 +/** LP_WDT_LP_WDT_INT_RAW : R/WTC/SS; bitpos: [31]; default: 0; + * need_des + */ +#define LP_WDT_LP_WDT_INT_RAW (BIT(31)) +#define LP_WDT_LP_WDT_INT_RAW_M (LP_WDT_LP_WDT_INT_RAW_V << LP_WDT_LP_WDT_INT_RAW_S) +#define LP_WDT_LP_WDT_INT_RAW_V 0x00000001U +#define LP_WDT_LP_WDT_INT_RAW_S 31 + +/** LP_WDT_INT_ST_REG register + * need_des + */ +#define LP_WDT_INT_ST_REG (DR_REG_LP_WDT_BASE + 0x2c) +/** LP_WDT_SUPER_WDT_INT_ST : RO; bitpos: [30]; default: 0; + * need_des + */ +#define LP_WDT_SUPER_WDT_INT_ST (BIT(30)) +#define LP_WDT_SUPER_WDT_INT_ST_M (LP_WDT_SUPER_WDT_INT_ST_V << LP_WDT_SUPER_WDT_INT_ST_S) +#define LP_WDT_SUPER_WDT_INT_ST_V 0x00000001U +#define LP_WDT_SUPER_WDT_INT_ST_S 30 +/** LP_WDT_LP_WDT_INT_ST : RO; bitpos: [31]; default: 0; + * need_des + */ +#define LP_WDT_LP_WDT_INT_ST (BIT(31)) +#define LP_WDT_LP_WDT_INT_ST_M (LP_WDT_LP_WDT_INT_ST_V << LP_WDT_LP_WDT_INT_ST_S) +#define LP_WDT_LP_WDT_INT_ST_V 0x00000001U +#define LP_WDT_LP_WDT_INT_ST_S 31 + +/** LP_WDT_INT_ENA_REG register + * need_des + */ +#define LP_WDT_INT_ENA_REG (DR_REG_LP_WDT_BASE + 0x30) +/** LP_WDT_SUPER_WDT_INT_ENA : R/W; bitpos: [30]; default: 0; + * need_des + */ +#define LP_WDT_SUPER_WDT_INT_ENA (BIT(30)) +#define LP_WDT_SUPER_WDT_INT_ENA_M (LP_WDT_SUPER_WDT_INT_ENA_V << LP_WDT_SUPER_WDT_INT_ENA_S) +#define LP_WDT_SUPER_WDT_INT_ENA_V 0x00000001U +#define LP_WDT_SUPER_WDT_INT_ENA_S 30 +/** LP_WDT_LP_WDT_INT_ENA : R/W; bitpos: [31]; default: 0; + * need_des + */ +#define LP_WDT_LP_WDT_INT_ENA (BIT(31)) +#define LP_WDT_LP_WDT_INT_ENA_M (LP_WDT_LP_WDT_INT_ENA_V << LP_WDT_LP_WDT_INT_ENA_S) +#define LP_WDT_LP_WDT_INT_ENA_V 0x00000001U +#define LP_WDT_LP_WDT_INT_ENA_S 31 + +/** LP_WDT_INT_CLR_REG register + * need_des + */ +#define LP_WDT_INT_CLR_REG (DR_REG_LP_WDT_BASE + 0x34) +/** LP_WDT_SUPER_WDT_INT_CLR : WT; bitpos: [30]; default: 0; + * need_des + */ +#define LP_WDT_SUPER_WDT_INT_CLR (BIT(30)) +#define LP_WDT_SUPER_WDT_INT_CLR_M (LP_WDT_SUPER_WDT_INT_CLR_V << LP_WDT_SUPER_WDT_INT_CLR_S) +#define LP_WDT_SUPER_WDT_INT_CLR_V 0x00000001U +#define LP_WDT_SUPER_WDT_INT_CLR_S 30 +/** LP_WDT_LP_WDT_INT_CLR : WT; bitpos: [31]; default: 0; + * need_des + */ +#define LP_WDT_LP_WDT_INT_CLR (BIT(31)) +#define LP_WDT_LP_WDT_INT_CLR_M (LP_WDT_LP_WDT_INT_CLR_V << LP_WDT_LP_WDT_INT_CLR_S) +#define LP_WDT_LP_WDT_INT_CLR_V 0x00000001U +#define LP_WDT_LP_WDT_INT_CLR_S 31 + +/** LP_WDT_DATE_REG register + * need_des + */ +#define LP_WDT_DATE_REG (DR_REG_LP_WDT_BASE + 0x3fc) +/** LP_WDT_LP_WDT_DATE : R/W; bitpos: [30:0]; default: 34676864; + * need_des + */ +#define LP_WDT_LP_WDT_DATE 0x7FFFFFFFU +#define LP_WDT_LP_WDT_DATE_M (LP_WDT_LP_WDT_DATE_V << LP_WDT_LP_WDT_DATE_S) +#define LP_WDT_LP_WDT_DATE_V 0x7FFFFFFFU +#define LP_WDT_LP_WDT_DATE_S 0 +/** LP_WDT_CLK_EN : R/W; bitpos: [31]; default: 0; + * need_des + */ +#define LP_WDT_CLK_EN (BIT(31)) +#define LP_WDT_CLK_EN_M (LP_WDT_CLK_EN_V << LP_WDT_CLK_EN_S) +#define LP_WDT_CLK_EN_V 0x00000001U +#define LP_WDT_CLK_EN_S 31 + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32h21/register/soc/lp_wdt_struct.h b/components/soc/esp32h21/register/soc/lp_wdt_struct.h new file mode 100644 index 00000000000..4c010e18e90 --- /dev/null +++ b/components/soc/esp32h21/register/soc/lp_wdt_struct.h @@ -0,0 +1,333 @@ +/** + * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#ifdef __cplusplus +extern "C" { +#endif + +/** Group: configure_register */ +/** Type of wdt_config0 register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:9; + /** wdt_wdt_pause_in_slp : R/W; bitpos: [9]; default: 1; + * need_des + */ + uint32_t wdt_wdt_pause_in_slp:1; + /** wdt_wdt_appcpu_reset_en : R/W; bitpos: [10]; default: 0; + * need_des + */ + uint32_t wdt_wdt_appcpu_reset_en:1; + /** wdt_wdt_procpu_reset_en : R/W; bitpos: [11]; default: 0; + * need_des + */ + uint32_t wdt_wdt_procpu_reset_en:1; + /** wdt_wdt_flashboot_mod_en : R/W; bitpos: [12]; default: 1; + * need_des + */ + uint32_t wdt_wdt_flashboot_mod_en:1; + /** wdt_wdt_sys_reset_length : R/W; bitpos: [15:13]; default: 1; + * need_des + */ + uint32_t wdt_wdt_sys_reset_length:3; + /** wdt_wdt_cpu_reset_length : R/W; bitpos: [18:16]; default: 1; + * need_des + */ + uint32_t wdt_wdt_cpu_reset_length:3; + /** wdt_wdt_stg3 : R/W; bitpos: [21:19]; default: 0; + * need_des + */ + uint32_t wdt_wdt_stg3:3; + /** wdt_wdt_stg2 : R/W; bitpos: [24:22]; default: 0; + * need_des + */ + uint32_t wdt_wdt_stg2:3; + /** wdt_wdt_stg1 : R/W; bitpos: [27:25]; default: 0; + * need_des + */ + uint32_t wdt_wdt_stg1:3; + /** wdt_wdt_stg0 : R/W; bitpos: [30:28]; default: 0; + * need_des + */ + uint32_t wdt_wdt_stg0:3; + /** wdt_wdt_en : R/W; bitpos: [31]; default: 0; + * need_des + */ + uint32_t wdt_wdt_en:1; + }; + uint32_t val; +} lp_wdt_config0_reg_t; + +/** Type of wdt_config1 register + * need_des + */ +typedef union { + struct { + /** wdt_wdt_stg0_hold : R/W; bitpos: [31:0]; default: 200000; + * need_des + */ + uint32_t wdt_wdt_stg0_hold:32; + }; + uint32_t val; +} lp_wdt_config1_reg_t; + +/** Type of wdt_config2 register + * need_des + */ +typedef union { + struct { + /** wdt_wdt_stg1_hold : R/W; bitpos: [31:0]; default: 80000; + * need_des + */ + uint32_t wdt_wdt_stg1_hold:32; + }; + uint32_t val; +} lp_wdt_config2_reg_t; + +/** Type of wdt_config3 register + * need_des + */ +typedef union { + struct { + /** wdt_wdt_stg2_hold : R/W; bitpos: [31:0]; default: 4095; + * need_des + */ + uint32_t wdt_wdt_stg2_hold:32; + }; + uint32_t val; +} lp_wdt_config3_reg_t; + +/** Type of wdt_config4 register + * need_des + */ +typedef union { + struct { + /** wdt_wdt_stg3_hold : R/W; bitpos: [31:0]; default: 4095; + * need_des + */ + uint32_t wdt_wdt_stg3_hold:32; + }; + uint32_t val; +} lp_wdt_config4_reg_t; + +/** Type of wdt_config5 register + * need_des + */ +typedef union { + struct { + /** wdt_chip_reset_target : R/W; bitpos: [7:0]; default: 255; + * need_des + */ + uint32_t wdt_chip_reset_target:8; + /** wdt_chip_reset_en : R/W; bitpos: [8]; default: 0; + * need_des + */ + uint32_t wdt_chip_reset_en:1; + /** wdt_chip_reset_key : R/W; bitpos: [16:9]; default: 0; + * need_des + */ + uint32_t wdt_chip_reset_key:8; + uint32_t reserved_17:15; + }; + uint32_t val; +} lp_wdt_config5_reg_t; + +/** Type of wdt_feed register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:31; + /** wdt_rtc_wdt_feed : WT; bitpos: [31]; default: 0; + * need_des + */ + uint32_t wdt_rtc_wdt_feed:1; + }; + uint32_t val; +} lp_wdt_feed_reg_t; + +/** Type of wdt_wprotect register + * need_des + */ +typedef union { + struct { + /** wdt_wdt_wkey : R/W; bitpos: [31:0]; default: 0; + * need_des + */ + uint32_t wdt_wdt_wkey:32; + }; + uint32_t val; +} lp_wdt_wprotect_reg_t; + +/** Type of wdt_swd_config register + * need_des + */ +typedef union { + struct { + /** wdt_swd_reset_flag : RO; bitpos: [0]; default: 0; + * need_des + */ + uint32_t wdt_swd_reset_flag:1; + uint32_t reserved_1:17; + /** wdt_swd_auto_feed_en : R/W; bitpos: [18]; default: 0; + * need_des + */ + uint32_t wdt_swd_auto_feed_en:1; + /** wdt_swd_rst_flag_clr : WT; bitpos: [19]; default: 0; + * need_des + */ + uint32_t wdt_swd_rst_flag_clr:1; + /** wdt_swd_signal_width : R/W; bitpos: [29:20]; default: 300; + * need_des + */ + uint32_t wdt_swd_signal_width:10; + /** wdt_swd_disable : R/W; bitpos: [30]; default: 0; + * need_des + */ + uint32_t wdt_swd_disable:1; + /** wdt_swd_feed : WT; bitpos: [31]; default: 0; + * need_des + */ + uint32_t wdt_swd_feed:1; + }; + uint32_t val; +} lp_wdt_swd_config_reg_t; + +/** Type of wdt_swd_wprotect register + * need_des + */ +typedef union { + struct { + /** wdt_swd_wkey : R/W; bitpos: [31:0]; default: 0; + * need_des + */ + uint32_t wdt_swd_wkey:32; + }; + uint32_t val; +} lp_wdt_swd_wprotect_reg_t; + +/** Type of wdt_int_raw register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:30; + /** wdt_super_wdt_int_raw : R/WTC/SS; bitpos: [30]; default: 0; + * need_des + */ + uint32_t wdt_super_wdt_int_raw:1; + /** wdt_lp_wdt_int_raw : R/WTC/SS; bitpos: [31]; default: 0; + * need_des + */ + uint32_t wdt_lp_wdt_int_raw:1; + }; + uint32_t val; +} lp_wdt_int_raw_reg_t; + +/** Type of wdt_int_st register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:30; + /** wdt_super_wdt_int_st : RO; bitpos: [30]; default: 0; + * need_des + */ + uint32_t wdt_super_wdt_int_st:1; + /** wdt_lp_wdt_int_st : RO; bitpos: [31]; default: 0; + * need_des + */ + uint32_t wdt_lp_wdt_int_st:1; + }; + uint32_t val; +} lp_wdt_int_st_reg_t; + +/** Type of wdt_int_ena register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:30; + /** wdt_super_wdt_int_ena : R/W; bitpos: [30]; default: 0; + * need_des + */ + uint32_t wdt_super_wdt_int_ena:1; + /** wdt_lp_wdt_int_ena : R/W; bitpos: [31]; default: 0; + * need_des + */ + uint32_t wdt_lp_wdt_int_ena:1; + }; + uint32_t val; +} lp_wdt_int_ena_reg_t; + +/** Type of wdt_int_clr register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:30; + /** wdt_super_wdt_int_clr : WT; bitpos: [30]; default: 0; + * need_des + */ + uint32_t wdt_super_wdt_int_clr:1; + /** wdt_lp_wdt_int_clr : WT; bitpos: [31]; default: 0; + * need_des + */ + uint32_t wdt_lp_wdt_int_clr:1; + }; + uint32_t val; +} lp_wdt_int_clr_reg_t; + +/** Type of wdt_date register + * need_des + */ +typedef union { + struct { + /** wdt_lp_wdt_date : R/W; bitpos: [30:0]; default: 34676864; + * need_des + */ + uint32_t wdt_lp_wdt_date:31; + /** wdt_clk_en : R/W; bitpos: [31]; default: 0; + * need_des + */ + uint32_t wdt_clk_en:1; + }; + uint32_t val; +} lp_wdt_date_reg_t; + + +typedef struct { + volatile lp_wdt_config0_reg_t wdt_config0; + volatile lp_wdt_config1_reg_t wdt_config1; + volatile lp_wdt_config2_reg_t wdt_config2; + volatile lp_wdt_config3_reg_t wdt_config3; + volatile lp_wdt_config4_reg_t wdt_config4; + volatile lp_wdt_config5_reg_t wdt_config5; + volatile lp_wdt_feed_reg_t wdt_feed; + volatile lp_wdt_wprotect_reg_t wdt_wprotect; + volatile lp_wdt_swd_config_reg_t wdt_swd_config; + volatile lp_wdt_swd_wprotect_reg_t wdt_swd_wprotect; + volatile lp_wdt_int_raw_reg_t wdt_int_raw; + volatile lp_wdt_int_st_reg_t wdt_int_st; + volatile lp_wdt_int_ena_reg_t wdt_int_ena; + volatile lp_wdt_int_clr_reg_t wdt_int_clr; + uint32_t reserved_038[241]; + volatile lp_wdt_date_reg_t wdt_date; +} lp_wdt_dev_t; + +extern lp_wdt_dev_t LP_WDT; + +#ifndef __cplusplus +_Static_assert(sizeof(lp_wdt_dev_t) == 0x400, "Invalid size of lp_wdt_dev_t structure"); +#endif + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32h21/register/soc/reg_base.h b/components/soc/esp32h21/register/soc/reg_base.h new file mode 100644 index 00000000000..9a3a45bb950 --- /dev/null +++ b/components/soc/esp32h21/register/soc/reg_base.h @@ -0,0 +1,59 @@ +/* + * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#pragma once + +#define DR_REG_UART0_BASE 0x60000000 +#define DR_REG_UART1_BASE 0x60001000 +#define DR_REG_SPIMEM0_BASE 0x60002000 +#define DR_REG_SPIMEM1_BASE 0x60003000 +#define DR_REG_I2C0_BASE 0x60004000 +#define DR_REG_I2C1_BASE 0x60005000 +#define DR_REG_UHCI0_BASE 0x60006000 +#define DR_REG_RMT_BASE 0x60007000 +#define DR_REG_LEDC_BASE 0x60008000 +#define DR_REG_TIMERG0_BASE 0x60009000 +#define DR_REG_TIMERG1_BASE 0x6000A000 +#define DR_REG_SYSTIMER_BASE 0x6000B000 +#define DR_REG_TWAI_BASE 0x6000C000 +#define DR_REG_I2S0_BASE 0x6000D000 +#define DR_REG_APB_SARADC_BASE 0x6000E000 +#define DR_REG_USB_SERIAL_JTAG_BASE 0x6000F000 +#define DR_REG_INTMTX_BASE 0x60010000 +#define DR_REG_PCNT_BASE 0x60012000 +#define DR_REG_SOC_ETM_BASE 0x60013000 +#define DR_REG_MCPWM0_BASE 0x60014000 +#define DR_REG_PARL_IO_BASE 0x60015000 +#define DR_REG_PVT_BASE 0x60019000 +#define DR_REG_GDMA_BASE 0x60080000 +#define DR_REG_GPSPI2_BASE 0x60081000 +#define DR_REG_AES_BASE 0x60088000 +#define DR_REG_SHA_BASE 0x60089000 +#define DR_REG_RSA_BASE 0x6008A000 +#define DR_REG_ECC_BASE 0x6008B000 +#define DR_REG_DS_BASE 0x6008C000 +#define DR_REG_HMAC_BASE 0x6008D000 +#define DR_REG_ECDSA_BASE 0x6008E000 +#define DR_REG_IO_MUX_BASE 0x60090000 +#define DR_REG_GPIO_BASE 0x60091000 +#define DR_REG_GPIO_EXT_BASE 0x60091e00 +#define DR_REG_MEM_MONITOR_BASE 0x60092000 +#define DR_REG_PAU_BASE 0x60093000 +#define DR_REG_HP_SYSTEM_BASE 0x60095000 +#define DR_REG_PCR_BASE 0x60096000 +#define DR_REG_TEE_BASE 0x60098000 +#define DR_REG_HP_APM_BASE 0x60099000 +#define DR_REG_LP_APM0_BASE 0x60099800 +#define DR_REG_PMU_BASE 0x600B0000 +#define DR_REG_LP_CLKRST_BASE 0x600B0400 +#define DR_REG_LP_TIMER_BASE 0x600B0C00 +#define DR_REG_LP_AON_BASE 0x600B1000 +#define DR_REG_LP_WDT_BASE 0x600B1C00 +#define DR_REG_LPPERI_BASE 0x600B2800 +#define DR_REG_LP_ANA_PERI_BASE 0x600B2C00 +#define DR_REG_LP_TIMER_BASE 0x600B3000 +#define DR_REG_LP_APM_BASE 0x600B3800 +#define DR_REG_EFUSE_BASE 0x600B4000 From 0cae6d526c0e7b63c313c5726a815b25ae93f65f Mon Sep 17 00:00:00 2001 From: laokaiyao Date: Fri, 6 Dec 2024 15:35:18 +0800 Subject: [PATCH 020/118] feat(ana_cmpr): support analog comparator on C61 --- .../test_apps/analog_comparator/README.md | 4 +- .../analog_comparator/pytest_ana_cmpr.py | 1 + .../hal/esp32c61/include/hal/ana_cmpr_ll.h | 169 ++++++++++++++++++ .../hal/esp32p4/include/hal/ana_cmpr_ll.h | 1 - components/soc/esp32c61/ana_cmpr_periph.c | 26 +++ .../esp32c61/include/soc/Kconfig.soc_caps.in | 16 ++ .../esp32c61/include/soc/ana_cmpr_channel.h | 10 ++ .../esp32c61/include/soc/ana_cmpr_struct.h | 36 ++++ .../soc/esp32c61/include/soc/clk_tree_defs.h | 17 ++ .../soc/esp32c61/include/soc/soc_caps.h | 6 + docs/docs_not_updated/esp32c61.txt | 1 - .../en/api-reference/peripherals/ana_cmpr.rst | 23 ++- .../api-reference/peripherals/ana_cmpr.rst | 23 ++- .../peripherals/analog_comparator/README.md | 4 +- .../pytest_ana_cmpr_example.py | 1 + 15 files changed, 308 insertions(+), 30 deletions(-) create mode 100644 components/hal/esp32c61/include/hal/ana_cmpr_ll.h create mode 100644 components/soc/esp32c61/ana_cmpr_periph.c create mode 100644 components/soc/esp32c61/include/soc/ana_cmpr_channel.h create mode 100644 components/soc/esp32c61/include/soc/ana_cmpr_struct.h diff --git a/components/esp_driver_ana_cmpr/test_apps/analog_comparator/README.md b/components/esp_driver_ana_cmpr/test_apps/analog_comparator/README.md index bde3cf8e738..522583ae5b4 100644 --- a/components/esp_driver_ana_cmpr/test_apps/analog_comparator/README.md +++ b/components/esp_driver_ana_cmpr/test_apps/analog_comparator/README.md @@ -1,2 +1,2 @@ -| Supported Targets | ESP32-H2 | ESP32-P4 | -| ----------------- | -------- | -------- | +| Supported Targets | ESP32-C61 | ESP32-H2 | ESP32-P4 | +| ----------------- | --------- | -------- | -------- | diff --git a/components/esp_driver_ana_cmpr/test_apps/analog_comparator/pytest_ana_cmpr.py b/components/esp_driver_ana_cmpr/test_apps/analog_comparator/pytest_ana_cmpr.py index 020ff3713ee..4bbc66b8a1d 100644 --- a/components/esp_driver_ana_cmpr/test_apps/analog_comparator/pytest_ana_cmpr.py +++ b/components/esp_driver_ana_cmpr/test_apps/analog_comparator/pytest_ana_cmpr.py @@ -6,6 +6,7 @@ @pytest.mark.esp32h2 @pytest.mark.esp32p4 +@pytest.mark.esp32c61 @pytest.mark.generic @pytest.mark.parametrize( 'config', diff --git a/components/hal/esp32c61/include/hal/ana_cmpr_ll.h b/components/hal/esp32c61/include/hal/ana_cmpr_ll.h new file mode 100644 index 00000000000..73e99c56717 --- /dev/null +++ b/components/hal/esp32c61/include/hal/ana_cmpr_ll.h @@ -0,0 +1,169 @@ +/* + * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#pragma once + +#include +#include "hal/misc.h" +#include "hal/assert.h" +#include "soc/ana_cmpr_struct.h" +#include "soc/soc_etm_source.h" + +#ifdef __cplusplus +extern "C" { +#endif + +#define ANALOG_CMPR_LL_GET_HW(unit) (&ANALOG_CMPR[unit]) +#define ANALOG_CMPR_LL_GET_UNIT(hw) (0) +#define ANALOG_CMPR_LL_EVENT_CROSS (1 << 0) + +#define ANALOG_CMPR_LL_NEG_CROSS_MASK(unit) (1UL << ((int)unit * 3)) +#define ANALOG_CMPR_LL_POS_CROSS_MASK(unit) (1UL << ((int)unit * 3 + 1)) + +#define ANALOG_CMPR_LL_ETM_SOURCE(unit, type) (GPIO_EVT_ZERO_DET_POS0 + (unit) * 2 + (type)) + + +/** + * @brief Enable analog comparator + * + * @param hw Analog comparator register base address + * @param en True to enable, False to disable + */ +static inline void analog_cmpr_ll_enable(analog_cmpr_dev_t *hw, bool en) +{ + hw->pad_comp_config->xpd_comp_0 = en; +} + +/** + * @brief Set the voltage of the internal reference + * + * @param hw Analog comparator register base address + * @param volt_level The voltage level of the internal reference, range [0.0V, 0.7VDD], step 0.1VDD + */ +__attribute__((always_inline)) +static inline void analog_cmpr_ll_set_internal_ref_voltage(analog_cmpr_dev_t *hw, uint32_t volt_level) +{ + hw->pad_comp_config->dref_comp_0 = volt_level; +} + +/** + * @brief Get the voltage of the internal reference + * + * @param hw Analog comparator register base address + * @return The voltage of the internal reference + */ +static inline float analog_cmpr_ll_get_internal_ref_voltage(analog_cmpr_dev_t *hw) +{ + return hw->pad_comp_config->dref_comp_0 * 0.1F; +} + +/** + * @brief The reference voltage comes from internal or external + * + * @note Also see `analog_cmpr_ll_set_internal_ref_voltage` to use the internal reference voltage + * + * @param hw Analog comparator register base address + * @param ref_src reference source, 0 for internal, 1 for external GPIO pad (GPIO10) + */ +static inline void analog_cmpr_ll_set_ref_source(analog_cmpr_dev_t *hw, uint32_t ref_src) +{ + hw->pad_comp_config->mode_comp_0 = ref_src; +} + +/** + * @brief Get the interrupt mask by trigger type + * + * @param hw Analog comparator register base address + * @param type The type of cross interrupt + * - 0: disable interrupt + * - 1: enable positive cross interrupt (input analog goes from low to high and across the reference voltage) + * - 2: enable negative cross interrupt (input analog goes from high to low and across the reference voltage) + * - 3: enable any positive or negative cross interrupt + * @return interrupt mask + */ +__attribute__((always_inline)) +static inline uint32_t analog_cmpr_ll_get_intr_mask_by_type(analog_cmpr_dev_t *hw, uint8_t type) +{ + uint32_t unit = ANALOG_CMPR_LL_GET_UNIT(hw); + uint32_t mask = 0; + if (type & 0x01) { + mask |= ANALOG_CMPR_LL_POS_CROSS_MASK(unit); + } + if (type & 0x02) { + mask |= ANALOG_CMPR_LL_NEG_CROSS_MASK(unit); + } + return mask; +} + +/** + * @brief Set the debounce cycle for the cross detection + * + * @note When the comparator detects a cross, it will wait for the debounce cycle to make sure the cross is stable. + * + * @param hw Analog comparator register base address + * @param cycle The debounce cycle + */ +__attribute__((always_inline)) +static inline void analog_cmpr_ll_set_debounce_cycle(analog_cmpr_dev_t *hw, uint32_t cycle) +{ + hw->pad_comp_filter->zero_det_filter_cnt_0 = cycle; +} + +/** + * @brief Enable comparator interrupt + * + * @param hw Analog comparator register base address + * @param mask Interrupt mask + * @param enable True to enable, False to disable + */ +static inline void analog_cmpr_ll_enable_intr(analog_cmpr_dev_t *hw, uint32_t mask, bool enable) +{ + uint32_t val = hw->int_ena->val; + if (enable) { + val |= mask; + } else { + val &= ~mask; + } + hw->int_ena->val = val; +} + +/** + * @brief Get comparator interrupt status + * + * @param hw Analog comparator register base address + */ +__attribute__((always_inline)) +static inline uint32_t analog_cmpr_ll_get_intr_status(analog_cmpr_dev_t *hw) +{ + return hw->int_st->val; +} + +/** + * @brief Clear comparator interrupt status + * + * @param hw Analog comparator register base address + * @param mask Interrupt status word + */ +__attribute__((always_inline)) +static inline void analog_cmpr_ll_clear_intr(analog_cmpr_dev_t *hw, uint32_t mask) +{ + hw->int_clr->val = mask; +} + +/** + * @brief Get the interrupt status register address + * + * @param hw Analog comparator register base address + * @return The interrupt status register address + */ +static inline volatile void *analog_cmpr_ll_get_intr_status_reg(analog_cmpr_dev_t *hw) +{ + return hw->int_st; +} + +#ifdef __cplusplus +} +#endif diff --git a/components/hal/esp32p4/include/hal/ana_cmpr_ll.h b/components/hal/esp32p4/include/hal/ana_cmpr_ll.h index d1075ed64ac..b0ada6928e4 100644 --- a/components/hal/esp32p4/include/hal/ana_cmpr_ll.h +++ b/components/hal/esp32p4/include/hal/ana_cmpr_ll.h @@ -19,7 +19,6 @@ extern "C" { #define ANALOG_CMPR_LL_GET_HW(unit) (&ANALOG_CMPR[unit]) #define ANALOG_CMPR_LL_GET_UNIT(hw) ((hw) == (&ANALOG_CMPR[0]) ? 0 : 1) #define ANALOG_CMPR_LL_EVENT_CROSS (1 << 0) -#define ANALOG_CMPR_LL_ETM_EVENTS_PER_UNIT (2) #define ANALOG_CMPR_LL_NEG_CROSS_MASK(unit) (1UL << ((int)unit * 3)) #define ANALOG_CMPR_LL_POS_CROSS_MASK(unit) (1UL << ((int)unit * 3 + 1)) diff --git a/components/soc/esp32c61/ana_cmpr_periph.c b/components/soc/esp32c61/ana_cmpr_periph.c new file mode 100644 index 00000000000..ccacfdf622c --- /dev/null +++ b/components/soc/esp32c61/ana_cmpr_periph.c @@ -0,0 +1,26 @@ +/* + * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include "soc/ana_cmpr_periph.h" +#include "soc/ana_cmpr_struct.h" + +const ana_cmpr_periph_t ana_cmpr_periph[SOC_ANA_CMPR_NUM] = { + [0] = { + .src_gpio = ANA_CMPR0_SRC_GPIO, + .ext_ref_gpio = ANA_CMPR0_EXT_REF_GPIO, + .intr_src = ETS_GPIO_INTERRUPT_EXT_SOURCE, + }, +}; + +analog_cmpr_dev_t ANALOG_CMPR[SOC_ANA_CMPR_NUM] = { + [0] = { + .pad_comp_config = &GPIO_EXT.pad_comp_config_0, + .pad_comp_filter = &GPIO_EXT.pad_comp_filter_0, + .int_st = &GPIO_EXT.int_st, + .int_ena = &GPIO_EXT.int_ena, + .int_clr = &GPIO_EXT.int_clr, + }, +}; diff --git a/components/soc/esp32c61/include/soc/Kconfig.soc_caps.in b/components/soc/esp32c61/include/soc/Kconfig.soc_caps.in index 32f1de140ef..be07f2aa398 100644 --- a/components/soc/esp32c61/include/soc/Kconfig.soc_caps.in +++ b/components/soc/esp32c61/include/soc/Kconfig.soc_caps.in @@ -7,6 +7,10 @@ config SOC_ADC_SUPPORTED bool default y +config SOC_ANA_CMPR_SUPPORTED + bool + default y + config SOC_DEDICATED_GPIO_SUPPORTED bool default y @@ -471,6 +475,18 @@ config SOC_DEDIC_PERIPH_ALWAYS_ENABLE bool default y +config SOC_ANA_CMPR_NUM + int + default 1 + +config SOC_ANA_CMPR_CAN_DISTINGUISH_EDGE + bool + default y + +config SOC_ANA_CMPR_SUPPORT_ETM + bool + default y + config SOC_I2C_NUM int default 1 diff --git a/components/soc/esp32c61/include/soc/ana_cmpr_channel.h b/components/soc/esp32c61/include/soc/ana_cmpr_channel.h new file mode 100644 index 00000000000..f51632ab0f5 --- /dev/null +++ b/components/soc/esp32c61/include/soc/ana_cmpr_channel.h @@ -0,0 +1,10 @@ +/* + * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#pragma once + +#define ANA_CMPR0_EXT_REF_GPIO 8 /*!< The GPIO that can be used as external reference voltage */ +#define ANA_CMPR0_SRC_GPIO 9 /*!< The GPIO that used for inputting the source signal to compare */ diff --git a/components/soc/esp32c61/include/soc/ana_cmpr_struct.h b/components/soc/esp32c61/include/soc/ana_cmpr_struct.h new file mode 100644 index 00000000000..ef3fbe3824e --- /dev/null +++ b/components/soc/esp32c61/include/soc/ana_cmpr_struct.h @@ -0,0 +1,36 @@ +/** + * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/* NOTE: this file is created manually for compatibility */ + +#pragma once + +#include +#include "soc/gpio_ext_struct.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @brief The Analog Comparator Device struct + * @note The field in it are register pointers, which point to the physical address + * of the corresponding configuration register + * @note see 'ana_cmpr_periph.c' for the device instance + */ +typedef struct { + volatile gpio_ext_pad_comp_config_0_reg_t *pad_comp_config; + volatile gpio_ext_pad_comp_filter_0_reg_t *pad_comp_filter; + volatile gpio_ext_int_st_reg_t *int_st; + volatile gpio_ext_int_ena_reg_t *int_ena; + volatile gpio_ext_int_clr_reg_t *int_clr; +} analog_cmpr_dev_t; + +extern analog_cmpr_dev_t ANALOG_CMPR[1]; + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32c61/include/soc/clk_tree_defs.h b/components/soc/esp32c61/include/soc/clk_tree_defs.h index fec2e781d5b..6d7ab501f43 100644 --- a/components/soc/esp32c61/include/soc/clk_tree_defs.h +++ b/components/soc/esp32c61/include/soc/clk_tree_defs.h @@ -278,6 +278,23 @@ typedef enum { GLITCH_FILTER_CLK_SRC_DEFAULT = SOC_MOD_CLK_PLL_F80M, /*!< Select PLL_F80M clock as the default clock choice */ } soc_periph_glitch_filter_clk_src_t; +///////////////////////////////////////////////////Analog Comparator//////////////////////////////////////////////////// + +/** + * @brief Array initializer for all supported clock sources of Analog Comparator + */ +#define SOC_ANA_CMPR_CLKS {SOC_MOD_CLK_PLL_F80M, SOC_MOD_CLK_RC_FAST, SOC_MOD_CLK_XTAL} + +/** + * @brief Analog Comparator clock source + */ +typedef enum { + ANA_CMPR_CLK_SRC_XTAL = SOC_MOD_CLK_XTAL, /*!< Select XTAL clock as the source clock */ + ANA_CMPR_CLK_SRC_RC_FAST = SOC_MOD_CLK_RC_FAST, /*!< Select RC_FAST clock as the source clock */ + ANA_CMPR_CLK_SRC_PLL_F80M = SOC_MOD_CLK_PLL_F80M, /*!< Select PLL_F80M clock as the source clock */ + ANA_CMPR_CLK_SRC_DEFAULT = SOC_MOD_CLK_PLL_F80M, /*!< Select PLL_F80M as the default clock choice */ +} soc_periph_ana_cmpr_clk_src_t; + //////////////////////////////////////////////////ADC/////////////////////////////////////////////////////////////////// /** diff --git a/components/soc/esp32c61/include/soc/soc_caps.h b/components/soc/esp32c61/include/soc/soc_caps.h index af95d3232cb..9fc484e819f 100644 --- a/components/soc/esp32c61/include/soc/soc_caps.h +++ b/components/soc/esp32c61/include/soc/soc_caps.h @@ -18,6 +18,7 @@ /*-------------------------- COMMON CAPS ---------------------------------------*/ #define SOC_ADC_SUPPORTED 1 +#define SOC_ANA_CMPR_SUPPORTED 1 #define SOC_DEDICATED_GPIO_SUPPORTED 1 #define SOC_UART_SUPPORTED 1 #define SOC_GDMA_SUPPORTED 1 @@ -211,6 +212,11 @@ #define SOC_DEDIC_GPIO_IN_CHANNELS_NUM (8) /*!< 8 inward channels on each CPU core */ #define SOC_DEDIC_PERIPH_ALWAYS_ENABLE (1) /*!< The dedicated GPIO (a.k.a. fast GPIO) is featured by some customized CPU instructions, which is always enabled */ +/*------------------------- Analog Comparator CAPS ---------------------------*/ +#define SOC_ANA_CMPR_NUM (1U) +#define SOC_ANA_CMPR_CAN_DISTINGUISH_EDGE (1) // Support positive/negative/any cross interrupt +#define SOC_ANA_CMPR_SUPPORT_ETM (1) + /*-------------------------- I2C CAPS ----------------------------------------*/ // ESP32-C61 has 1 I2C #define SOC_I2C_NUM (1U) diff --git a/docs/docs_not_updated/esp32c61.txt b/docs/docs_not_updated/esp32c61.txt index a6f5015cbba..06f5fabaca5 100644 --- a/docs/docs_not_updated/esp32c61.txt +++ b/docs/docs_not_updated/esp32c61.txt @@ -45,7 +45,6 @@ api-reference/peripherals/usb_device.rst api-reference/peripherals/dac.rst api-reference/peripherals/touch_element.rst api-reference/peripherals/ppa.rst -api-reference/peripherals/ana_cmpr.rst api-reference/peripherals/camera_driver.rst api-reference/peripherals/spi_features.rst api-reference/peripherals/sdio_slave.rst diff --git a/docs/en/api-reference/peripherals/ana_cmpr.rst b/docs/en/api-reference/peripherals/ana_cmpr.rst index 44d9a34b44b..a8954edbbcd 100644 --- a/docs/en/api-reference/peripherals/ana_cmpr.rst +++ b/docs/en/api-reference/peripherals/ana_cmpr.rst @@ -3,8 +3,8 @@ Analog Comparator :link_to_translation:`zh_CN:[中文]` -{IDF_TARGET_ANA_CMPR_SRC_CHAN0: default="NOT UPDATED", esp32h2="GPIO11", esp32p4="GPIO52"} -{IDF_TARGET_ANA_CMPR_EXT_REF_CHAN0: default="NOT UPDATED", esp32h2="GPIO10", esp32p4="GPIO51"} +{IDF_TARGET_ANA_CMPR_SRC_CHAN0: default="NOT UPDATED", esp32h2="GPIO11", esp32p4="GPIO52", esp32c61="GPIO9"} +{IDF_TARGET_ANA_CMPR_EXT_REF_CHAN0: default="NOT UPDATED", esp32h2="GPIO10", esp32p4="GPIO51", esp32c61="GPIO8"} {IDF_TARGET_ANA_CMPR_SRC_CHAN1: default="NOT UPDATED", esp32p4="GPIO54"} {IDF_TARGET_ANA_CMPR_EXT_REF_CHAN1: default="NOT UPDATED", esp32p4="GPIO53"} @@ -36,17 +36,16 @@ Functional Overview The following sections of this document cover the typical steps to install and operate an analog comparator unit: -- :ref:`anacmpr-resource-allocation` - covers which parameters should be set up to get a unit handle and how to recycle the resources when it finishes working. -- :ref:`anacmpr-further-configurations` - covers the other configurations that might need to specify and what they are used for. -- :ref:`anacmpr-enable-and-disable-unit` - covers how to enable and disable the unit. -- :ref:`anacmpr-power-management` - describes how different source clock selections can affect power consumption. -- :ref:`anacmpr-iram-safe` - lists which functions are supposed to work even when the cache is disabled. -- :ref:`anacmpr-thread-safety` - lists which APIs are guaranteed to be thread safe by the driver. -- :ref:`anacmpr-kconfig-options` - lists the supported Kconfig options that can be used to make a different effect on driver behavior. +.. list:: -.. only:: SOC_ANA_CMPR_SUPPORT_ETM - - - :ref:`anacmpr-etm-events` - covers how to create an analog comparator cross event. + - :ref:`anacmpr-resource-allocation` - covers which parameters should be set up to get a unit handle and how to recycle the resources when it finishes working. + - :ref:`anacmpr-further-configurations` - covers the other configurations that might need to specify and what they are used for. + - :ref:`anacmpr-enable-and-disable-unit` - covers how to enable and disable the unit. + - :ref:`anacmpr-power-management` - describes how different source clock selections can affect power consumption. + - :ref:`anacmpr-iram-safe` - lists which functions are supposed to work even when the cache is disabled. + - :ref:`anacmpr-thread-safety` - lists which APIs are guaranteed to be thread safe by the driver. + - :ref:`anacmpr-kconfig-options` - lists the supported Kconfig options that can be used to make a different effect on driver behavior. + :SOC_ANA_CMPR_SUPPORT_ETM: - :ref:`anacmpr-etm-events` - covers how to create an analog comparator cross event. .. _anacmpr-resource-allocation: diff --git a/docs/zh_CN/api-reference/peripherals/ana_cmpr.rst b/docs/zh_CN/api-reference/peripherals/ana_cmpr.rst index 136f0f834d4..d529b3f2cb0 100644 --- a/docs/zh_CN/api-reference/peripherals/ana_cmpr.rst +++ b/docs/zh_CN/api-reference/peripherals/ana_cmpr.rst @@ -3,8 +3,8 @@ :link_to_translation:`en:[English]` -{IDF_TARGET_ANA_CMPR_SRC_CHAN0: default="未更新", esp32h2="GPIO11", esp32p4="GPIO52"} -{IDF_TARGET_ANA_CMPR_EXT_REF_CHAN0: default="未更新", esp32h2="GPIO10", esp32p4="GPIO51"} +{IDF_TARGET_ANA_CMPR_SRC_CHAN0: default="未更新", esp32h2="GPIO11", esp32p4="GPIO52", esp32c61="GPIO9"} +{IDF_TARGET_ANA_CMPR_EXT_REF_CHAN0: default="未更新", esp32h2="GPIO10", esp32p4="GPIO51", esp32c61="GPIO8"} {IDF_TARGET_ANA_CMPR_SRC_CHAN1: default="未更新", esp32p4="GPIO54"} {IDF_TARGET_ANA_CMPR_EXT_REF_CHAN1: default="未更新", esp32p4="GPIO53"} @@ -36,17 +36,16 @@ 本文中的以下章节涵盖了安装及操作模拟比较器单元的基本步骤： -- :ref:`anacmpr-resource-allocation` - 涵盖了应设置哪些参数以获取单元句柄，以及完成工作后如何回收资源。 -- :ref:`anacmpr-further-configurations` - 涵盖了可能需要指定的其他配置及其用途。 -- :ref:`anacmpr-enable-and-disable-unit` - 涵盖了如何启用和禁用单元。 -- :ref:`anacmpr-power-management` - 描述了不同时钟源对功耗的影响。 -- :ref:`anacmpr-iram-safe` - 列出了在 cache 被禁用时也能起效的函数。 -- :ref:`anacmpr-thread-safety` - 列出了驱动程序中线程安全的 API。 -- :ref:`anacmpr-kconfig-options` - 列出了支持的 Kconfig 选项，这些选项可以对驱动程序产生不同影响。 +.. list:: -.. only:: SOC_ANA_CMPR_SUPPORT_ETM - - - :ref:`anacmpr-etm-events` - 介绍了如何创建一个模拟比较器跨越事件。 + - :ref:`anacmpr-resource-allocation` - 涵盖了应设置哪些参数以获取单元句柄，以及完成工作后如何回收资源。 + - :ref:`anacmpr-further-configurations` - 涵盖了可能需要指定的其他配置及其用途。 + - :ref:`anacmpr-enable-and-disable-unit` - 涵盖了如何启用和禁用单元。 + - :ref:`anacmpr-power-management` - 描述了不同时钟源对功耗的影响。 + - :ref:`anacmpr-iram-safe` - 列出了在 cache 被禁用时也能起效的函数。 + - :ref:`anacmpr-thread-safety` - 列出了驱动程序中线程安全的 API。 + - :ref:`anacmpr-kconfig-options` - 列出了支持的 Kconfig 选项，这些选项可以对驱动程序产生不同影响。 + :SOC_ANA_CMPR_SUPPORT_ETM: - :ref:`anacmpr-etm-events` - 介绍了如何创建一个模拟比较器跨越事件。 .. _anacmpr-resource-allocation: diff --git a/examples/peripherals/analog_comparator/README.md b/examples/peripherals/analog_comparator/README.md index 330b1dcc0e3..eb664cf6daf 100644 --- a/examples/peripherals/analog_comparator/README.md +++ b/examples/peripherals/analog_comparator/README.md @@ -1,5 +1,5 @@ -| Supported Targets | ESP32-H2 | ESP32-P4 | -| ----------------- | -------- | -------- | +| Supported Targets | ESP32-C61 | ESP32-H2 | ESP32-P4 | +| ----------------- | --------- | -------- | -------- | # Analog Comparator Example diff --git a/examples/peripherals/analog_comparator/pytest_ana_cmpr_example.py b/examples/peripherals/analog_comparator/pytest_ana_cmpr_example.py index 0c7b5c2b025..1f21a6f845b 100644 --- a/examples/peripherals/analog_comparator/pytest_ana_cmpr_example.py +++ b/examples/peripherals/analog_comparator/pytest_ana_cmpr_example.py @@ -6,6 +6,7 @@ @pytest.mark.esp32h2 @pytest.mark.esp32p4 +@pytest.mark.esp32c61 @pytest.mark.generic @pytest.mark.parametrize( 'config', From 7064ad8abb92d34c9cbe5b834e0fd327c5add986 Mon Sep 17 00:00:00 2001 From: Sudeep Mohanty Date: Mon, 9 Dec 2024 09:30:04 +0530 Subject: [PATCH 021/118] docs(esp_ringbuf): Fixed incorrect documentation for xRingBufferSendComplete() Closes https://github.com/espressif/esp-idf/issues/14990 --- docs/en/api-reference/system/freertos_additions.rst | 2 +- docs/zh_CN/api-reference/system/freertos_additions.rst | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/docs/en/api-reference/system/freertos_additions.rst b/docs/en/api-reference/system/freertos_additions.rst index a4e8ea8f110..11de9a32cf8 100644 --- a/docs/en/api-reference/system/freertos_additions.rst +++ b/docs/en/api-reference/system/freertos_additions.rst @@ -111,7 +111,7 @@ The following example demonstrates the usage of :cpp:func:`xRingbufferSendAcquir .buf = item->buf, }; //Actually send to the ring buffer for consumer to use - res = xRingbufferSendComplete(buf_handle, &item); + res = xRingbufferSendComplete(buf_handle, (void *)item); if (res != pdTRUE) { printf("Failed to send item\n"); } diff --git a/docs/zh_CN/api-reference/system/freertos_additions.rst b/docs/zh_CN/api-reference/system/freertos_additions.rst index eb2f0f41b46..d9f6b754741 100644 --- a/docs/zh_CN/api-reference/system/freertos_additions.rst +++ b/docs/zh_CN/api-reference/system/freertos_additions.rst @@ -111,7 +111,7 @@ ESP-IDF 环形 buffer 是一个典型的 FIFO buffer，支持任意大小的数 .buf = item->buf, }; //实际发送到环形 buffer 以供使用 - res = xRingbufferSendComplete(buf_handle, &item); + res = xRingbufferSendComplete(buf_handle, (void *)item); if (res != pdTRUE) { printf("Failed to send item\n"); } From a995a5339b8251dd300f5095466f3bf48056f18c Mon Sep 17 00:00:00 2001 From: Guillaume Souchere Date: Thu, 7 Nov 2024 13:23:27 +0100 Subject: [PATCH 022/118] fix(heap): MALLOC_CAP_EXEC does not allocate in RTC IRAM This commit fixes the issue when trying to allocate memory with the MALLOC_CAP_EXEC in RTC memory. Prior to the fix, the heap allocator was returning an address in RTC DRAM. To fix this issue: - modified memory_layout.c of the concerned targets to fill the iram_address field in the rtc entry of the soc_memory_region array properly. - modified heap component related functions to return IRAM address when an allocation in RTC memory with MALLOC_CAP_EXEC is requested. Closes https://github.com/espressif/esp-idf/issues/14835 --- .../include/bootloader_memory_utils.h | 24 +++++++++++++++++-- .../esp_hw_support/include/esp_memory_utils.h | 24 +++++++++++++++++-- components/heap/heap_caps_base.c | 16 +++++++++---- components/heap/port/esp32s2/memory_layout.c | 8 +++---- 4 files changed, 59 insertions(+), 13 deletions(-) diff --git a/components/bootloader_support/include/bootloader_memory_utils.h b/components/bootloader_support/include/bootloader_memory_utils.h index adbf72a275f..e77e4cc8aab 100644 --- a/components/bootloader_support/include/bootloader_memory_utils.h +++ b/components/bootloader_support/include/bootloader_memory_utils.h @@ -28,7 +28,12 @@ extern "C" { */ __attribute__((always_inline)) inline static bool esp_dram_match_iram(void) { - return (SOC_DRAM_LOW == SOC_IRAM_LOW && SOC_DRAM_HIGH == SOC_IRAM_HIGH); + bool dram_match_iram = (SOC_DRAM_LOW == SOC_IRAM_LOW) && + (SOC_DRAM_HIGH == SOC_IRAM_HIGH); +#if SOC_RTC_FAST_MEM_SUPPORTED + dram_match_iram &= (SOC_RTC_IRAM_LOW == SOC_RTC_DRAM_LOW); +#endif + return dram_match_iram; } /** @@ -97,7 +102,7 @@ inline static bool esp_ptr_in_diram_iram(const void *p) { */ __attribute__((always_inline)) inline static bool esp_ptr_in_rtc_iram_fast(const void *p) { -#if SOC_RTC_FAST_MEM_SUPPORTED +#if SOC_RTC_FAST_MEM_SUPPORTED && (SOC_RTC_IRAM_LOW != SOC_RTC_DRAM_LOW) return ((intptr_t)p >= SOC_RTC_IRAM_LOW && (intptr_t)p < SOC_RTC_IRAM_HIGH); #else return false; @@ -151,6 +156,21 @@ inline static void * esp_ptr_diram_dram_to_iram(const void *p) { #endif } +/* Convert a RTC DRAM pointer to equivalent word address in RTC IRAM + + - Address must be word aligned + - Address must pass esp_ptr_in_rtc_dram_fast() test, or result will be invalid pointer +*/ +__attribute__((always_inline)) +inline static void * esp_ptr_rtc_dram_to_iram(const void *p) { + intptr_t ptr = (intptr_t)p; +#if SOC_RTC_FAST_MEM_SUPPORTED && (SOC_RTC_IRAM_LOW != SOC_RTC_DRAM_LOW) + return (void *) ( SOC_RTC_IRAM_LOW + (ptr - SOC_RTC_DRAM_LOW) ); +#else + return (void *) ptr; +#endif +} + /* Convert a D/IRAM IRAM pointer to equivalent word address in DRAM - Address must be word aligned diff --git a/components/esp_hw_support/include/esp_memory_utils.h b/components/esp_hw_support/include/esp_memory_utils.h index d17d6f26965..de0cea32c45 100644 --- a/components/esp_hw_support/include/esp_memory_utils.h +++ b/components/esp_hw_support/include/esp_memory_utils.h @@ -27,7 +27,12 @@ extern "C" { */ __attribute__((always_inline)) inline static bool esp_dram_match_iram(void) { - return (SOC_DRAM_LOW == SOC_IRAM_LOW && SOC_DRAM_HIGH == SOC_IRAM_HIGH); + bool dram_match_iram = (SOC_DRAM_LOW == SOC_IRAM_LOW) && + (SOC_DRAM_HIGH == SOC_IRAM_HIGH); +#if SOC_RTC_FAST_MEM_SUPPORTED + dram_match_iram &= (SOC_RTC_IRAM_LOW == SOC_RTC_DRAM_LOW); +#endif + return dram_match_iram; } /** @@ -96,7 +101,7 @@ inline static bool esp_ptr_in_diram_iram(const void *p) { */ __attribute__((always_inline)) inline static bool esp_ptr_in_rtc_iram_fast(const void *p) { -#if SOC_RTC_FAST_MEM_SUPPORTED +#if SOC_RTC_FAST_MEM_SUPPORTED && (SOC_RTC_IRAM_LOW != SOC_RTC_DRAM_LOW) return ((intptr_t)p >= SOC_RTC_IRAM_LOW && (intptr_t)p < SOC_RTC_IRAM_HIGH); #else return false; @@ -150,6 +155,21 @@ inline static void * esp_ptr_diram_dram_to_iram(const void *p) { #endif } +/* Convert a RTC DRAM pointer to equivalent word address in RTC IRAM + + - Address must be word aligned + - Address must pass esp_ptr_in_rtc_dram_fast() test, or result will be invalid pointer +*/ +__attribute__((always_inline)) +inline static void * esp_ptr_rtc_dram_to_iram(const void *p) { + intptr_t ptr = (intptr_t)p; +#if SOC_RTC_FAST_MEM_SUPPORTED && (SOC_RTC_IRAM_LOW != SOC_RTC_DRAM_LOW) + return (void *) ( SOC_RTC_IRAM_LOW + (ptr - SOC_RTC_DRAM_LOW) ); +#else + return (void *) ptr; +#endif +} + /* Convert a D/IRAM IRAM pointer to equivalent word address in DRAM - Address must be word aligned diff --git a/components/heap/heap_caps_base.c b/components/heap/heap_caps_base.c index e8947907008..b7da26f1797 100644 --- a/components/heap/heap_caps_base.c +++ b/components/heap/heap_caps_base.c @@ -38,14 +38,19 @@ HEAP_IRAM_ATTR static void *dram_alloc_to_iram_addr(void *addr, size_t len) { uintptr_t dstart = (uintptr_t)addr; //First word uintptr_t dend __attribute__((unused)) = dstart + len - 4; //Last word - assert(esp_ptr_in_diram_dram((void *)dstart)); - assert(esp_ptr_in_diram_dram((void *)dend)); + assert(esp_ptr_in_diram_dram((void *)dstart) || esp_ptr_in_rtc_dram_fast((void *)dstart)); + assert(esp_ptr_in_diram_dram((void *)dend) || esp_ptr_in_rtc_dram_fast((void *)dend)); assert((dstart & 3) == 0); assert((dend & 3) == 0); #if SOC_DIRAM_INVERTED // We want the word before the result to hold the DRAM address uint32_t *iptr = esp_ptr_diram_dram_to_iram((void *)dend); #else - uint32_t *iptr = esp_ptr_diram_dram_to_iram((void *)dstart); + uint32_t *iptr = NULL; + if (esp_ptr_in_rtc_dram_fast((void *)dstart)) { + iptr = esp_ptr_rtc_dram_to_iram((void *)dstart); + } else { + iptr = esp_ptr_diram_dram_to_iram((void *)dstart); + } #endif *iptr = dstart; return iptr + 1; @@ -57,7 +62,7 @@ HEAP_IRAM_ATTR void heap_caps_free( void *ptr) return; } - if (esp_ptr_in_diram_iram(ptr)) { + if (esp_ptr_in_diram_iram(ptr) || esp_ptr_in_rtc_iram_fast(ptr)) { //Memory allocated here is actually allocated in the DRAM alias region and //cannot be de-allocated as usual. dram_alloc_to_iram_addr stores a pointer to //the equivalent DRAM address, though; free that. @@ -132,7 +137,8 @@ HEAP_IRAM_ATTR NOINLINE_ATTR void *heap_caps_aligned_alloc_base(size_t alignment //This heap can satisfy all the requested capabilities. See if we can grab some memory using it. // If MALLOC_CAP_EXEC is requested but the DRAM and IRAM are on the same addresses (like on esp32c6) // proceed as for a default allocation. - if ((caps & MALLOC_CAP_EXEC) && !esp_dram_match_iram() && esp_ptr_in_diram_dram((void *)heap->start)) { + if (((caps & MALLOC_CAP_EXEC) && !esp_dram_match_iram()) && + (esp_ptr_in_diram_dram((void *)heap->start) || esp_ptr_in_rtc_dram_fast((void *)heap->start))) { //This is special, insofar that what we're going to get back is a DRAM address. If so, //we need to 'invert' it (lowest address in DRAM == highest address in IRAM and vice-versa) and //add a pointer to the DRAM equivalent before the address we're going to return. diff --git a/components/heap/port/esp32s2/memory_layout.c b/components/heap/port/esp32s2/memory_layout.c index 813e4940504..e64ebe80aaf 100644 --- a/components/heap/port/esp32s2/memory_layout.c +++ b/components/heap/port/esp32s2/memory_layout.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2010-2023 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2010-2024 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -51,11 +51,11 @@ enum { /** * Defined the attributes and allocation priority of each memory on the chip, * The heap allocator will traverse all types of memory types in column High Priority Matching and match the specified caps at first, - * if no memory caps matched or the allocation is failed, it will go to columns Medium Priorty Matching and Low Priority Matching + * if no memory caps matched or the allocation is failed, it will go to columns Medium Priority Matching and Low Priority Matching * in turn to continue matching. */ const soc_memory_type_desc_t soc_memory_types[] = { - /* Mem Type Name | High Priority Matching | Medium Priorty Matching | Low Priority Matching */ + /* Mem Type Name | High Priority Matching | Medium Priority Matching | Low Priority Matching */ [SOC_MEMORY_TYPE_DIRAM] = { "RAM", { MALLOC_DIRAM_BASE_CAPS, 0, 0 }}, //TODO, in fact, part of them support EDMA, to be supported. [SOC_MEMORY_TYPE_SPIRAM] = { "SPIRAM", { MALLOC_CAP_SPIRAM, ESP32S2_MEM_COMMON_CAPS, 0 }}, @@ -113,7 +113,7 @@ const soc_memory_region_t soc_memory_regions[] = { { 0x3FFF8000, 0x4000, SOC_MEMORY_TYPE_DIRAM, 0x40068000, false}, //Block 20, can be used for MAC dump, can be used as trace memory { 0x3FFFC000, 0x4000, SOC_MEMORY_TYPE_DIRAM, 0x4006C000, true}, //Block 21, can be used for MAC dump, can be used as trace memory, used for startup stack #ifdef CONFIG_ESP_SYSTEM_ALLOW_RTC_FAST_MEM_AS_HEAP - { SOC_RTC_DRAM_LOW, 0x2000, SOC_MEMORY_TYPE_RTCRAM, 0, false}, //RTC Fast Memory + { SOC_RTC_DRAM_LOW, 0x2000, SOC_MEMORY_TYPE_RTCRAM, SOC_RTC_IRAM_LOW, false}, //RTC Fast Memory #endif }; From 5acb9c9b5f889b1e6fa57c791e825dbc8c6326f7 Mon Sep 17 00:00:00 2001 From: zhanghaipeng Date: Mon, 9 Dec 2024 16:07:29 +0800 Subject: [PATCH 023/118] fix(blufi): Fixed crash issue in Blufi example during prepare write operation --- .../esp/blufi/bluedroid_host/esp_blufi.c | 37 ++++++++++++------- .../btc/profile/esp/blufi/include/blufi_int.h | 2 + 2 files changed, 26 insertions(+), 13 deletions(-) diff --git a/components/bt/common/btc/profile/esp/blufi/bluedroid_host/esp_blufi.c b/components/bt/common/btc/profile/esp/blufi/bluedroid_host/esp_blufi.c index 47022992e43..f0c0aa4a03a 100644 --- a/components/bt/common/btc/profile/esp/blufi/bluedroid_host/esp_blufi.c +++ b/components/bt/common/btc/profile/esp/blufi/bluedroid_host/esp_blufi.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2015-2022 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2015-2024 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -160,20 +160,31 @@ static void blufi_profile_cb(tBTA_GATTS_EVT event, tBTA_GATTS *p_data) if (p_data->req_data.p_data->write_req.is_prep) { tBTA_GATT_STATUS status = GATT_SUCCESS; - if (blufi_env.prepare_buf == NULL) { - blufi_env.prepare_buf = osi_malloc(BLUFI_PREPAIR_BUF_MAX_SIZE); - blufi_env.prepare_len = 0; - if (blufi_env.prepare_buf == NULL) { - BLUFI_TRACE_ERROR("Blufi prep no mem\n"); - status = GATT_NO_RESOURCES; + do { + if (p_data->req_data.p_data->write_req.offset > BLUFI_PREPARE_BUF_MAX_SIZE) { + status = ESP_GATT_INVALID_OFFSET; + break; } - } else { - if (p_data->req_data.p_data->write_req.offset > BLUFI_PREPAIR_BUF_MAX_SIZE) { - status = GATT_INVALID_OFFSET; - } else if ((p_data->req_data.p_data->write_req.offset + p_data->req_data.p_data->write_req.len) > BLUFI_PREPAIR_BUF_MAX_SIZE) { - status = GATT_INVALID_ATTR_LEN; + + if ((p_data->req_data.p_data->write_req.offset + p_data->req_data.p_data->write_req.len) > BLUFI_PREPARE_BUF_MAX_SIZE) { + status = ESP_GATT_INVALID_ATTR_LEN; + break; } - } + + if (blufi_env.prepare_buf == NULL) { + if (p_data->req_data.p_data->write_req.offset != 0) { + status = GATT_INVALID_OFFSET; + break; + } + blufi_env.prepare_buf = osi_malloc(BLUFI_PREPARE_BUF_MAX_SIZE); + blufi_env.prepare_len = 0; + if (blufi_env.prepare_buf == NULL) { + BLUFI_TRACE_ERROR("Blufi prep no mem\n"); + status = GATT_NO_RESOURCES; + break; + } + } + } while (0); memset(&rsp, 0, sizeof(tGATTS_RSP)); rsp.attr_value.handle = p_data->req_data.p_data->write_req.handle; diff --git a/components/bt/common/btc/profile/esp/blufi/include/blufi_int.h b/components/bt/common/btc/profile/esp/blufi/include/blufi_int.h index e85ad73d860..a7f4f292884 100644 --- a/components/bt/common/btc/profile/esp/blufi/include/blufi_int.h +++ b/components/bt/common/btc/profile/esp/blufi/include/blufi_int.h @@ -36,7 +36,9 @@ typedef struct { UINT32 trans_id; UINT8 congest; UINT16 frag_size; +// Deprecated: This macro will be removed in the future #define BLUFI_PREPAIR_BUF_MAX_SIZE 1024 +#define BLUFI_PREPARE_BUF_MAX_SIZE 1024 uint8_t *prepare_buf; int prepare_len; /* Control reference */ From 58f2dd5a6621b280cb9be07028e82f1010408dd9 Mon Sep 17 00:00:00 2001 From: Ivan Grokhotkov Date: Mon, 9 Dec 2024 10:51:19 +0100 Subject: [PATCH 024/118] fix(protocol_examples_common): don't override MAC address for openeth The intention of the code block was to set MAC address for SPI Ethernet modules, however !CONFIG_EXAMPLE_USE_INTERNAL_ETHERNET also affected the case of CONFIG_EXAMPLE_USE_OPENETH. This commit corrects the code to match the original intention. Related to https://github.com/espressif/qemu/issues/107 --- .../protocol_examples_common/eth_connect.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/examples/common_components/protocol_examples_common/eth_connect.c b/examples/common_components/protocol_examples_common/eth_connect.c index 86e856527c2..0cd105621dc 100644 --- a/examples/common_components/protocol_examples_common/eth_connect.c +++ b/examples/common_components/protocol_examples_common/eth_connect.c @@ -154,7 +154,8 @@ static esp_netif_t *eth_start(void) // Install Ethernet driver esp_eth_config_t config = ETH_DEFAULT_CONFIG(s_mac, s_phy); ESP_ERROR_CHECK(esp_eth_driver_install(&config, &s_eth_handle)); -#if !CONFIG_EXAMPLE_USE_INTERNAL_ETHERNET + +#if CONFIG_EXAMPLE_USE_SPI_ETHERNET /* The SPI Ethernet module might doesn't have a burned factory MAC address, we cat to set it manually. We set the ESP_MAC_ETH mac address as the default, if you want to use ESP_MAC_EFUSE_CUSTOM mac address, please enable the configuration: `ESP_MAC_USE_CUSTOM_MAC_AS_BASE_MAC` @@ -162,7 +163,8 @@ static esp_netif_t *eth_start(void) uint8_t eth_mac[6] = {0}; ESP_ERROR_CHECK(esp_read_mac(eth_mac, ESP_MAC_ETH)); ESP_ERROR_CHECK(esp_eth_ioctl(s_eth_handle, ETH_CMD_S_MAC_ADDR, eth_mac)); -#endif +#endif // CONFIG_EXAMPLE_USE_SPI_ETHERNET + // combine driver with netif s_eth_glue = esp_eth_new_netif_glue(s_eth_handle); esp_netif_attach(netif, s_eth_glue); From d681fb8949ba0ce71aa3a45de0f1d3adee9293b6 Mon Sep 17 00:00:00 2001 From: Sumeet Singh Date: Mon, 9 Dec 2024 16:00:16 +0530 Subject: [PATCH 025/118] fix(nimble): update csfc max size to max_bonds to fix invalid nvs overflow event --- components/bt/host/nimble/port/include/esp_nimble_cfg.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/components/bt/host/nimble/port/include/esp_nimble_cfg.h b/components/bt/host/nimble/port/include/esp_nimble_cfg.h index 98fe9475a01..6db93500be1 100644 --- a/components/bt/host/nimble/port/include/esp_nimble_cfg.h +++ b/components/bt/host/nimble/port/include/esp_nimble_cfg.h @@ -996,7 +996,7 @@ #endif #ifndef MYNEWT_VAL_BLE_STORE_MAX_CSFCS -#define MYNEWT_VAL_BLE_STORE_MAX_CSFCS (CONFIG_BT_NIMBLE_MAX_CONNECTIONS) +#define MYNEWT_VAL_BLE_STORE_MAX_CSFCS CONFIG_BT_NIMBLE_MAX_BONDS #endif #ifdef CONFIG_BT_NIMBLE_MAX_EADS From 58c1d3972073993f93765a32119925ef32deffe2 Mon Sep 17 00:00:00 2001 From: yinqingzhao Date: Fri, 6 Dec 2024 19:41:25 +0800 Subject: [PATCH 026/118] fix(wifi): expend bit width of channel in rxctrl --- components/esp_wifi/include/esp_wifi_he_types.h | 6 +++--- components/esp_wifi/lib | 2 +- 2 files changed, 4 insertions(+), 4 deletions(-) diff --git a/components/esp_wifi/include/esp_wifi_he_types.h b/components/esp_wifi/include/esp_wifi_he_types.h index e2fe9c9f755..f5ac859fb7b 100644 --- a/components/esp_wifi/include/esp_wifi_he_types.h +++ b/components/esp_wifi/include/esp_wifi_he_types.h @@ -204,9 +204,9 @@ typedef struct { unsigned : 1; /**< reserved */ unsigned : 1; /**< reserved */ unsigned : 1; /**< reserved */ - unsigned channel: 4; /**< the primary channel */ - unsigned second: 4; /**< the second channel if in HT40 */ - unsigned : 12; /**< reserved */ + unsigned channel: 8; /**< the primary channel */ + unsigned second: 8; /**< the second channel if in HT40 */ + unsigned : 4; /**< reserved */ unsigned : 4; /**< reserved */ unsigned : 1; /**< reserved */ unsigned : 7; /**< reserved */ diff --git a/components/esp_wifi/lib b/components/esp_wifi/lib index 5c7ffad5b09..df42b857ede 160000 --- a/components/esp_wifi/lib +++ b/components/esp_wifi/lib @@ -1 +1 @@ -Subproject commit 5c7ffad5b09d600e6677512de45a4db107cf7142 +Subproject commit df42b857ede33d672362fdc5e0178f5d2bd91595 From f6c776d6c6a3a910df62d3fe9ae1b5584e4fda3b Mon Sep 17 00:00:00 2001 From: Chen Jichang Date: Thu, 5 Dec 2024 18:51:31 +0800 Subject: [PATCH 027/118] feat(legacy_driver): add kconfig to skip legacy confilct check --- components/driver/Kconfig | 59 ++++++++++++++++++- components/driver/deprecated/adc_dma_legacy.c | 2 + components/driver/deprecated/adc_legacy.c | 2 + .../driver/deprecated/dac_common_legacy.c | 2 + components/driver/deprecated/i2s_legacy.c | 2 + components/driver/deprecated/mcpwm_legacy.c | 2 + components/driver/deprecated/pcnt_legacy.c | 2 + components/driver/deprecated/rmt_legacy.c | 2 + .../deprecated/rtc_temperature_legacy.c | 2 + .../driver/deprecated/sigma_delta_legacy.c | 20 ++++++- components/driver/deprecated/timer_legacy.c | 2 + components/driver/i2c/i2c.c | 2 + .../touch_sensor/esp32s2/touch_sensor.c | 2 + .../touch_sensor/esp32s3/touch_sensor.c | 2 + 14 files changed, 101 insertions(+), 2 deletions(-) diff --git a/components/driver/Kconfig b/components/driver/Kconfig index 2698ac746aa..c0784d9b3f4 100644 --- a/components/driver/Kconfig +++ b/components/driver/Kconfig @@ -22,6 +22,11 @@ menu "Driver Configurations" If you want to continue using the legacy driver, and don't want to see related deprecation warnings, you can enable this option. + config ADC_SKIP_LEGACY_CONFLICT_CHECK + bool "Skip legacy conflict check" + default n + help + This configuration option allows the user to bypass the conflict check mechanism with legacy code. menu "Legacy ADC Calibration Configuration" config ADC_CAL_EFUSE_TP_ENABLE @@ -72,6 +77,12 @@ menu "Driver Configurations" Whether to suppress the deprecation warnings when using legacy dac driver (driver/dac.h). If you want to continue using the legacy driver, and don't want to see related deprecation warnings, you can enable this option. + + config DAC_SKIP_LEGACY_CONFLICT_CHECK + bool "Skip legacy conflict check" + default n + help + This configuration option allows the user to bypass the conflict check mechanism with legacy code. endmenu # Legacy DAC Driver Configurations menu "Legacy MCPWM Driver Configurations" @@ -83,6 +94,12 @@ menu "Driver Configurations" Whether to suppress the deprecation warnings when using legacy MCPWM driver (driver/mcpwm.h). If you want to continue using the legacy driver, and don't want to see related deprecation warnings, you can enable this option. + + config MCPWM_SKIP_LEGACY_CONFLICT_CHECK + bool "Skip legacy conflict check" + default n + help + This configuration option allows the user to bypass the conflict check mechanism with legacy code. endmenu # Legacy MCPWM Driver Configurations menu "Legacy Timer Group Driver Configurations" @@ -95,6 +112,11 @@ menu "Driver Configurations" If you want to continue using the legacy driver, and don't want to see related deprecation warnings, you can enable this option. + config GPTIMER_SKIP_LEGACY_CONFLICT_CHECK + bool "Skip legacy conflict check" + default n + help + This configuration option allows the user to bypass the conflict check mechanism with legacy code. endmenu # Legacy Timer Group Driver Configurations menu "Legacy RMT Driver Configurations" @@ -106,6 +128,12 @@ menu "Driver Configurations" Whether to suppress the deprecation warnings when using legacy rmt driver (driver/rmt.h). If you want to continue using the legacy driver, and don't want to see related deprecation warnings, you can enable this option. + + config RMT_SKIP_LEGACY_CONFLICT_CHECK + bool "Skip legacy conflict check" + default n + help + This configuration option allows the user to bypass the conflict check mechanism with legacy code. endmenu # Legacy RMT Driver Configurations menu "Legacy I2S Driver Configurations" @@ -117,6 +145,12 @@ menu "Driver Configurations" Whether to suppress the deprecation warnings when using legacy i2s driver (driver/i2s.h). If you want to continue using the legacy driver, and don't want to see related deprecation warnings, you can enable this option. + + config I2S_SKIP_LEGACY_CONFLICT_CHECK + bool "Skip legacy conflict check" + default n + help + This configuration option allows the user to bypass the conflict check mechanism with legacy code. endmenu # Legacy I2S Driver Configurationss menu "Legacy PCNT Driver Configurations" @@ -128,6 +162,12 @@ menu "Driver Configurations" whether to suppress the deprecation warnings when using legacy PCNT driver (driver/pcnt.h). If you want to continue using the legacy driver, and don't want to see related deprecation warnings, you can enable this option. + + config PCNT_SKIP_LEGACY_CONFLICT_CHECK + bool "Skip legacy conflict check" + default n + help + This configuration option allows the user to bypass the conflict check mechanism with legacy code. endmenu # Legacy PCNT Driver Configurationss menu "Legacy SDM Driver Configurations" @@ -139,6 +179,12 @@ menu "Driver Configurations" whether to suppress the deprecation warnings when using legacy SDM driver (driver/sigmadelta.h). If you want to continue using the legacy driver, and don't want to see related deprecation warnings, you can enable this option. + + config SDM_SKIP_LEGACY_CONFLICT_CHECK + bool "Skip legacy conflict check" + default n + help + This configuration option allows the user to bypass the conflict check mechanism with legacy code. endmenu # Legacy SDM Driver Configurationss menu "Legacy Temperature Sensor Driver Configurations" @@ -150,6 +196,12 @@ menu "Driver Configurations" whether to suppress the deprecation warnings when using legacy temperature sensor driver (driver/temp_sensor.h). If you want to continue using the legacy driver, and don't want to see related deprecation warnings, you can enable this option. + + config TEMP_SENSOR_SKIP_LEGACY_CONFLICT_CHECK + bool "Skip legacy conflict check" + default n + help + This configuration option allows the user to bypass the conflict check mechanism with legacy code. endmenu # Legacy Temperature Sensor Driver Configurationss menu "Legacy Touch Sensor Driver Configurations" @@ -161,6 +213,11 @@ menu "Driver Configurations" whether to suppress the deprecation warnings when using legacy touch sensor driver (driver/touch_sensor.h). If you want to continue using the legacy driver, and don't want to see related deprecation warnings, you can enable this option. - endmenu # Legacy Touch Sensor Driver Configurationss + config TOUCH_SKIP_LEGACY_CONFLICT_CHECK + bool "Skip legacy conflict check" + default n + help + This configuration option allows the user to bypass the conflict check mechanism with legacy code. + endmenu # Legacy Touch Sensor Driver Configurationss endmenu # Driver configurations diff --git a/components/driver/deprecated/adc_dma_legacy.c b/components/driver/deprecated/adc_dma_legacy.c index a85a043714d..9c7800e0fc3 100644 --- a/components/driver/deprecated/adc_dma_legacy.c +++ b/components/driver/deprecated/adc_dma_legacy.c @@ -631,6 +631,7 @@ esp_err_t adc_digi_controller_configure(const adc_digi_configuration_t *config) return ESP_OK; } +#if !CONFIG_ADC_SKIP_LEGACY_CONFLICT_CHECK /** * @brief This function will be called during start up, to check that adc_continuous driver is not running along with the legacy adc_continuous driver */ @@ -646,6 +647,7 @@ static void check_adc_continuous_driver_conflict(void) } ESP_EARLY_LOGW(ADC_TAG, "legacy driver is deprecated, please migrate to `esp_adc/adc_continuous.h`"); } +#endif //CONFIG_ADC_SKIP_LEGACY_CONFLICT_CHECK #if SOC_ADC_CALIBRATION_V1_SUPPORTED /*--------------------------------------------------------------- diff --git a/components/driver/deprecated/adc_legacy.c b/components/driver/deprecated/adc_legacy.c index afca5a6d91e..da6f018c49a 100644 --- a/components/driver/deprecated/adc_legacy.c +++ b/components/driver/deprecated/adc_legacy.c @@ -922,6 +922,7 @@ static esp_err_t adc_hal_convert(adc_unit_t adc_n, int channel, uint32_t clk_src return ESP_OK; } +#if !CONFIG_ADC_SKIP_LEGACY_CONFLICT_CHECK /** * @brief This function will be called during start up, to check that adc_oneshot driver is not running along with the legacy adc oneshot driver */ @@ -937,6 +938,7 @@ static void check_adc_oneshot_driver_conflict(void) } ESP_EARLY_LOGW(ADC_TAG, "legacy driver is deprecated, please migrate to `esp_adc/adc_oneshot.h`"); } +#endif //CONFIG_ADC_SKIP_LEGACY_CONFLICT_CHECK #if SOC_ADC_CALIBRATION_V1_SUPPORTED /*--------------------------------------------------------------- diff --git a/components/driver/deprecated/dac_common_legacy.c b/components/driver/deprecated/dac_common_legacy.c index 0a990c286d2..603363e42f0 100644 --- a/components/driver/deprecated/dac_common_legacy.c +++ b/components/driver/deprecated/dac_common_legacy.c @@ -128,6 +128,7 @@ esp_err_t dac_cw_generator_config(dac_cw_config_t *cw) return ESP_OK; } +#if !CONFIG_DAC_SKIP_LEGACY_CONFLICT_CHECK /** * @brief This function will be called during start up, to check that this legacy DAC driver is not running along with the new driver */ @@ -143,3 +144,4 @@ static void check_dac_legacy_driver_conflict(void) } ESP_EARLY_LOGW(TAG, "legacy driver is deprecated, please migrate to `driver/dac_oneshot.h`, `driver/dac_cosine.h` or `driver/dac_continuous.h` instead"); } +#endif //CONFIG_DAC_SKIP_LEGACY_CONFLICT_CHECK diff --git a/components/driver/deprecated/i2s_legacy.c b/components/driver/deprecated/i2s_legacy.c index 0d76a78a5c1..3310316e2b6 100644 --- a/components/driver/deprecated/i2s_legacy.c +++ b/components/driver/deprecated/i2s_legacy.c @@ -1981,6 +1981,7 @@ esp_err_t i2s_set_pin(i2s_port_t i2s_num, const i2s_pin_config_t *pin) return ESP_OK; } +#if !CONFIG_I2S_SKIP_LEGACY_CONFLICT_CHECK /** * @brief This function will be called during start up, to check that the new i2s driver is not running along with the legacy i2s driver */ @@ -1994,3 +1995,4 @@ static __attribute__((constructor)) void check_i2s_driver_conflict(void) } ESP_EARLY_LOGW(TAG, "legacy i2s driver is deprecated, please migrate to use driver/i2s_std.h, driver/i2s_pdm.h or driver/i2s_tdm.h"); } +#endif //CONFIG_I2S_SKIP_LEGACY_CONFLICT_CHECK diff --git a/components/driver/deprecated/mcpwm_legacy.c b/components/driver/deprecated/mcpwm_legacy.c index 625895c7413..94723decdda 100644 --- a/components/driver/deprecated/mcpwm_legacy.c +++ b/components/driver/deprecated/mcpwm_legacy.c @@ -1053,6 +1053,7 @@ esp_err_t mcpwm_set_timer_sync_output(mcpwm_unit_t mcpwm_num, mcpwm_timer_t time return ESP_OK; } +#if !CONFIG_MCPWM_SKIP_LEGACY_CONFLICT_CHECK /** * @brief This function will be called during start up, to check that this legacy mcpwm driver is not running along with the new MCPWM driver */ @@ -1068,3 +1069,4 @@ static void check_mcpwm_driver_conflict(void) } ESP_EARLY_LOGW(TAG, "legacy driver is deprecated, please migrate to `driver/mcpwm_prelude.h`"); } +#endif //CONFIG_MCPWM_SKIP_LEGACY_CONFLICT_CHECK diff --git a/components/driver/deprecated/pcnt_legacy.c b/components/driver/deprecated/pcnt_legacy.c index 2cb09efb7ae..749182a7286 100644 --- a/components/driver/deprecated/pcnt_legacy.c +++ b/components/driver/deprecated/pcnt_legacy.c @@ -555,6 +555,7 @@ void pcnt_isr_service_uninstall(void) _pcnt_isr_service_uninstall(PCNT_PORT_0); } +#if !CONFIG_PCNT_SKIP_LEGACY_CONFLICT_CHECK /** * @brief This function will be called during start up, to check that pulse_cnt driver is not running along with the legacy pcnt driver */ @@ -570,3 +571,4 @@ static void check_pcnt_driver_conflict(void) } ESP_EARLY_LOGW(TAG, "legacy driver is deprecated, please migrate to `driver/pulse_cnt.h`"); } +#endif //CONFIG_PCNT_SKIP_LEGACY_CONFLICT_CHECK diff --git a/components/driver/deprecated/rmt_legacy.c b/components/driver/deprecated/rmt_legacy.c index d3c319d0395..baff30aa46b 100644 --- a/components/driver/deprecated/rmt_legacy.c +++ b/components/driver/deprecated/rmt_legacy.c @@ -1398,6 +1398,7 @@ esp_err_t rmt_enable_tx_loop_autostop(rmt_channel_t channel, bool en) } #endif +#if !CONFIG_RMT_SKIP_LEGACY_CONFLICT_CHECK /** * @brief This function will be called during start up, to check that this legacy RMT driver is not running along with the new driver */ @@ -1413,3 +1414,4 @@ static void check_rmt_legacy_driver_conflict(void) } ESP_EARLY_LOGW(TAG, "legacy driver is deprecated, please migrate to `driver/rmt_tx.h` and/or `driver/rmt_rx.h`"); } +#endif //CONFIG_RMT_SKIP_LEGACY_CONFLICT_CHECK diff --git a/components/driver/deprecated/rtc_temperature_legacy.c b/components/driver/deprecated/rtc_temperature_legacy.c index 7433867a019..4af803e02ba 100644 --- a/components/driver/deprecated/rtc_temperature_legacy.c +++ b/components/driver/deprecated/rtc_temperature_legacy.c @@ -158,6 +158,7 @@ esp_err_t temp_sensor_read_celsius(float *celsius) return ESP_OK; } +#if !CONFIG_TEMP_SENSOR_SKIP_LEGACY_CONFLICT_CHECK /** * @brief This function will be called during start up, to check that this legacy temp sensor driver is not running along with the new driver */ @@ -173,3 +174,4 @@ static void check_legacy_temp_sensor_driver_conflict(void) } ESP_EARLY_LOGW(TAG, "legacy driver is deprecated, please migrate to `driver/temperature_sensor.h`"); } +#endif //CONFIG_TEMP_SENSOR_SKIP_LEGACY_CONFLICT_CHECK diff --git a/components/driver/deprecated/sigma_delta_legacy.c b/components/driver/deprecated/sigma_delta_legacy.c index 55bd049087c..0b631ce0023 100644 --- a/components/driver/deprecated/sigma_delta_legacy.c +++ b/components/driver/deprecated/sigma_delta_legacy.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2015-2021 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2015-2024 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -129,3 +129,21 @@ esp_err_t sigmadelta_config(const sigmadelta_config_t *config) } return _sigmadelta_config(SIGMADELTA_PORT_0, config); } + +#if !CONFIG_SDM_SKIP_LEGACY_CONFLICT_CHECK +/** + * @brief This function will be called during start up, to check that sdm driver is not running along with the legacy sdm driver + */ +__attribute__((constructor)) +static void check_sdm_driver_conflict(void) +{ + // This function was declared as weak here. sdm driver has one implementation. + // So if sdm driver is not linked in, then `sdm_new_channel` should be NULL at runtime. + extern __attribute__((weak)) esp_err_t sdm_new_channel(const void *config, void **ret_unit); + if ((void *)sdm_new_channel != NULL) { + ESP_EARLY_LOGE(TAG, "CONFLICT! driver_ng is not allowed to be used with the legacy driver"); + abort(); + } + ESP_EARLY_LOGW(TAG, "legacy driver is deprecated, please migrate to `driver/sdm.h`"); +} +#endif //CONFIG_PCNT_SKIP_LEGACY_CONFLICT_CHECK diff --git a/components/driver/deprecated/timer_legacy.c b/components/driver/deprecated/timer_legacy.c index 2ee334bbeb9..5b692f04e9c 100644 --- a/components/driver/deprecated/timer_legacy.c +++ b/components/driver/deprecated/timer_legacy.c @@ -468,6 +468,7 @@ bool IRAM_ATTR timer_group_get_auto_reload_in_isr(timer_group_t group_num, timer return p_timer_obj[group_num][timer_num]->auto_reload_en; } +#if !CONFIG_GPTIMER_SKIP_LEGACY_CONFLICT_CHECK /** * @brief This function will be called during start up, to check that this legacy timer group driver is not running along with the gptimer driver */ @@ -483,3 +484,4 @@ static void check_legacy_timer_driver_conflict(void) } ESP_EARLY_LOGW(TIMER_TAG, "legacy driver is deprecated, please migrate to `driver/gptimer.h`"); } +#endif //CONFIG_GPTIMER_SKIP_LEGACY_CONFLICT_CHECK diff --git a/components/driver/i2c/i2c.c b/components/driver/i2c/i2c.c index dc60a43f6e7..e27fe6df378 100644 --- a/components/driver/i2c/i2c.c +++ b/components/driver/i2c/i2c.c @@ -1705,6 +1705,7 @@ int i2c_slave_read_buffer(i2c_port_t i2c_num, uint8_t *data, size_t max_size, Ti } #endif +#if !CONFIG_I2C_SKIP_LEGACY_CONFLICT_CHECK /** * @brief This function will be called during start up, to check that this legacy i2c driver is not running along with the new I2C driver */ @@ -1720,3 +1721,4 @@ static void check_i2c_driver_conflict(void) } ESP_EARLY_LOGW(I2C_TAG, "This driver is an old driver, please migrate your application code to adapt `driver/i2c_master.h`"); } +#endif //CONFIG_I2C_SKIP_LEGACY_CONFLICT_CHECK diff --git a/components/driver/touch_sensor/esp32s2/touch_sensor.c b/components/driver/touch_sensor/esp32s2/touch_sensor.c index 2c46fa1eb3c..f4ef21d5af6 100644 --- a/components/driver/touch_sensor/esp32s2/touch_sensor.c +++ b/components/driver/touch_sensor/esp32s2/touch_sensor.c @@ -685,6 +685,7 @@ esp_err_t touch_pad_sleep_channel_set_work_time(uint16_t sleep_cycle, uint16_t m return ESP_OK; } +#if !CONFIG_TOUCH_SKIP_LEGACY_CONFLICT_CHECK /** * @brief This function will be called during start up, to check that the new touch driver is not running along with the legacy touch driver */ @@ -698,3 +699,4 @@ static __attribute__((constructor)) void check_touch_driver_conflict(void) } ESP_EARLY_LOGW("legacy_touch_driver", "legacy touch driver is deprecated, please migrate to use driver/touch_sens.h"); } +#endif //CONFIG_TOUCH_SKIP_LEGACY_CONFLICT_CHECK diff --git a/components/driver/touch_sensor/esp32s3/touch_sensor.c b/components/driver/touch_sensor/esp32s3/touch_sensor.c index e29091618e3..cec9222fa6e 100644 --- a/components/driver/touch_sensor/esp32s3/touch_sensor.c +++ b/components/driver/touch_sensor/esp32s3/touch_sensor.c @@ -657,6 +657,7 @@ esp_err_t touch_pad_sleep_channel_set_work_time(uint16_t sleep_cycle, uint16_t m return ESP_OK; } +#if !CONFIG_TOUCH_SKIP_LEGACY_CONFLICT_CHECK /** * @brief This function will be called during start up, to check that the new touch driver is not running along with the legacy touch driver */ @@ -670,3 +671,4 @@ static __attribute__((constructor)) void check_touch_driver_conflict(void) } ESP_EARLY_LOGW("legacy_touch_driver", "legacy touch driver is deprecated, please migrate to use driver/touch_sens.h"); } +#endif //CONFIG_TOUCH_SKIP_LEGACY_CONFLICT_CHECK From 966f61ef6e4bafbb67c494490dbccec328d60c32 Mon Sep 17 00:00:00 2001 From: Alexey Lapshin Date: Mon, 9 Dec 2024 12:45:23 +0700 Subject: [PATCH 028/118] fix(spi): fix deprecation warnings --- components/hal/esp32/include/hal/spi_types.h | 6 +++--- components/hal/esp32s2/include/hal/spi_types.h | 6 +++--- 2 files changed, 6 insertions(+), 6 deletions(-) diff --git a/components/hal/esp32/include/hal/spi_types.h b/components/hal/esp32/include/hal/spi_types.h index 4fbc89e9d0e..8798bb43a82 100644 --- a/components/hal/esp32/include/hal/spi_types.h +++ b/components/hal/esp32/include/hal/spi_types.h @@ -12,9 +12,9 @@ extern "C" { #endif -#define SPI_HOST _Pragma ("GCC warning \"SPI_HOST is deprecated in favor of SPI1_HOST\"") SPI1_HOST -#define HSPI_HOST _Pragma ("GCC warning \"HSPI_HOST is deprecated in favor of SPI2_HOST\"") SPI2_HOST -#define VSPI_HOST _Pragma ("GCC warning \"VSPI_HOST is deprecated in favor of SPI3_HOST\"") SPI3_HOST +#define SPI_HOST SPI1_HOST +#define HSPI_HOST SPI2_HOST +#define VSPI_HOST SPI3_HOST #ifdef __cplusplus } diff --git a/components/hal/esp32s2/include/hal/spi_types.h b/components/hal/esp32s2/include/hal/spi_types.h index 777138775d8..25577edb6c0 100644 --- a/components/hal/esp32s2/include/hal/spi_types.h +++ b/components/hal/esp32s2/include/hal/spi_types.h @@ -12,9 +12,9 @@ extern "C" { #endif -#define SPI_HOST _Pragma ("GCC warning \"SPI_HOST is deprecated in favor of SPI1_HOST\"") SPI1_HOST -#define FSPI_HOST _Pragma ("GCC warning \"FSPI_HOST is deprecated in favor of SPI2_HOST\"") SPI2_HOST -#define HSPI_HOST _Pragma ("GCC warning \"HSPI_HOST is deprecated in favor of SPI3_HOST\"") SPI3_HOST +#define SPI_HOST SPI1_HOST +#define FSPI_HOST SPI2_HOST +#define HSPI_HOST SPI3_HOST #ifdef __cplusplus } From 3646021d5b94b08351883128e02686e4adb24a57 Mon Sep 17 00:00:00 2001 From: WanqQixiang Date: Tue, 10 Dec 2024 11:29:49 +0800 Subject: [PATCH 029/118] fix(openthread): Disable Border Agent features by default --- .../openthread-core-esp32x-ftd-config.h | 20 +++++++++---------- 1 file changed, 10 insertions(+), 10 deletions(-) diff --git a/components/openthread/private_include/openthread-core-esp32x-ftd-config.h b/components/openthread/private_include/openthread-core-esp32x-ftd-config.h index 8f0ffdc9967..8a2012dc336 100644 --- a/components/openthread/private_include/openthread-core-esp32x-ftd-config.h +++ b/components/openthread/private_include/openthread-core-esp32x-ftd-config.h @@ -370,6 +370,16 @@ /*----The following options set fixed default values but can be overridden by the user header file.----*/ #if CONFIG_OPENTHREAD_BORDER_ROUTER +/** + * @def OPENTHREAD_CONFIG_BORDER_AGENT_ENABLE + * + * Define to 1 to enable Border Agent support. + * + */ +#ifndef OPENTHREAD_CONFIG_BORDER_AGENT_ENABLE +#define OPENTHREAD_CONFIG_BORDER_AGENT_ENABLE 1 +#endif + /** * @def OPENTHREAD_CONFIG_BORDER_AGENT_ID_ENABLE * @@ -451,16 +461,6 @@ #define OPENTHREAD_CONFIG_BORDER_ROUTER_ENABLE 1 #endif -/** - * @def OPENTHREAD_CONFIG_BORDER_AGENT_ENABLE - * - * Define to 1 to enable Border Agent support. - * - */ -#ifndef OPENTHREAD_CONFIG_BORDER_AGENT_ENABLE -#define OPENTHREAD_CONFIG_BORDER_AGENT_ENABLE 1 -#endif - #if !CONFIG_OPENTHREAD_RADIO_NATIVE /** * @def OPENTHREAD_SPINEL_CONFIG_COMPATIBILITY_ERROR_CALLBACK_ENABLE From 5c32d4c22a0907de28e43066b7eb0528317abc3d Mon Sep 17 00:00:00 2001 From: Armando Date: Tue, 10 Dec 2024 15:29:21 +0800 Subject: [PATCH 030/118] fix(mspi): fix init stuck when flash qio and xip_psram condition Closes https://github.com/espressif/esp-idf/issues/14979 --- .../mspi_timing_tuning/mspi_timing_by_flash_delay.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/components/esp_hw_support/mspi_timing_tuning/mspi_timing_by_flash_delay.c b/components/esp_hw_support/mspi_timing_tuning/mspi_timing_by_flash_delay.c index 2f66ecec6a1..b3cc9a3199f 100644 --- a/components/esp_hw_support/mspi_timing_tuning/mspi_timing_by_flash_delay.c +++ b/components/esp_hw_support/mspi_timing_tuning/mspi_timing_by_flash_delay.c @@ -167,7 +167,7 @@ void mspi_timing_flash_config_set_tuning_regs(bool control_both_mspi) //Won't touch SPI1 registers } -#if CONFIG_ESPTOOLPY_FLASHMODE_QIO +#if MSPI_TIMING_FLASH_NEEDS_TUNING && CONFIG_ESPTOOLPY_FLASHMODE_QIO mspi_timing_ll_set_flash_user_dummy(MSPI_TIMING_LL_MSPI_ID_0, 7); #endif From f2eca886d07655ac2b156ccd8e3cdd5cf2b23612 Mon Sep 17 00:00:00 2001 From: muhaidong Date: Tue, 10 Dec 2024 16:22:57 +0800 Subject: [PATCH 031/118] fix(phy): fixed calibration warning infomation inaccurate issue Closes https://github.com/espressif/esp-idf/issues/14963 --- components/esp_phy/include/esp_private/phy.h | 2 +- components/esp_phy/src/phy_init.c | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/components/esp_phy/include/esp_private/phy.h b/components/esp_phy/include/esp_private/phy.h index 5d3864f56a4..f8a848dcb4c 100644 --- a/components/esp_phy/include/esp_private/phy.h +++ b/components/esp_phy/include/esp_private/phy.h @@ -37,7 +37,7 @@ void phy_get_romfunc_addr(void); * @param[in] init_data Initialization parameters to be used by the PHY * @param[inout] cal_data As input, calibration data previously obtained. As output, will contain new calibration data. * @param[in] cal_mode RF calibration mode - * @return ESP_CAL_DATA_CHECK_FAIL if calibration data checksum fails, other values are reserved for future use + * @return ESP_CAL_DATA_CHECK_FAIL if the calibration data checksum fails or if the calibration data is outdated, other values are reserved for future use */ int register_chipv7_phy(const esp_phy_init_data_t* init_data, esp_phy_calibration_data_t *cal_data, esp_phy_calibration_mode_t cal_mode); diff --git a/components/esp_phy/src/phy_init.c b/components/esp_phy/src/phy_init.c index 9f85684d897..bc8d28bf3fc 100644 --- a/components/esp_phy/src/phy_init.c +++ b/components/esp_phy/src/phy_init.c @@ -929,7 +929,7 @@ void esp_phy_load_cal_and_init(void) memcpy(cal_data->mac, sta_mac, 6); esp_err_t ret = register_chipv7_phy(init_data, cal_data, calibration_mode); if (ret == ESP_CAL_DATA_CHECK_FAIL) { - ESP_LOGW(TAG, "saving new calibration data because of checksum failure, mode(%d)", calibration_mode); + ESP_LOGI(TAG, "Saving new calibration data due to checksum failure or outdated calibration data, mode(%d)", calibration_mode); } if ((calibration_mode != PHY_RF_CAL_NONE) && ((err != ESP_OK) || (ret == ESP_CAL_DATA_CHECK_FAIL))) { From 9c228007d73c29c3a12657e87676144204c7352e Mon Sep 17 00:00:00 2001 From: muhaidong Date: Tue, 10 Dec 2024 19:27:14 +0800 Subject: [PATCH 032/118] fix(wifi): fixed blufi connect wep or wpa ap fail issue --- .../bluetooth/blufi/main/Kconfig.projbuild | 26 +++++++++++++++++++ .../bluetooth/blufi/main/blufi_example_main.c | 19 ++++++++++++++ 2 files changed, 45 insertions(+) diff --git a/examples/bluetooth/blufi/main/Kconfig.projbuild b/examples/bluetooth/blufi/main/Kconfig.projbuild index 3ede60cb2e5..b8fe9f1957d 100644 --- a/examples/bluetooth/blufi/main/Kconfig.projbuild +++ b/examples/bluetooth/blufi/main/Kconfig.projbuild @@ -7,4 +7,30 @@ menu "Example Configuration" help WiFi connection maximum retry, from 0 to 255. + choice EXAMPLE_WIFI_SCAN_AUTH_MODE_THRESHOLD + prompt "WiFi Scan auth mode threshold" + default ESP_WIFI_AUTH_WPA2_PSK + help + The weakest authmode to accept in the scan mode. + This value defaults to ESP_WIFI_AUTH_WPA2_PSK in case password is present and ESP_WIFI_AUTH_OPEN is used. + Please select ESP_WIFI_AUTH_WEP/ESP_WIFI_AUTH_WPA_PSK in case AP is operating in WEP/WPA mode. + + config ESP_WIFI_AUTH_OPEN + bool "OPEN" + config ESP_WIFI_AUTH_WEP + bool "WEP" + config ESP_WIFI_AUTH_WPA_PSK + bool "WPA PSK" + config ESP_WIFI_AUTH_WPA2_PSK + bool "WPA2 PSK" + config ESP_WIFI_AUTH_WPA_WPA2_PSK + bool "WPA/WPA2 PSK" + config ESP_WIFI_AUTH_WPA3_PSK + bool "WPA3 PSK" + config ESP_WIFI_AUTH_WPA2_WPA3_PSK + bool "WPA2/WPA3 PSK" + config ESP_WIFI_AUTH_WAPI_PSK + bool "WAPI PSK" + endchoice + endmenu diff --git a/examples/bluetooth/blufi/main/blufi_example_main.c b/examples/bluetooth/blufi/main/blufi_example_main.c index c14c03a64e0..982158558b0 100644 --- a/examples/bluetooth/blufi/main/blufi_example_main.c +++ b/examples/bluetooth/blufi/main/blufi_example_main.c @@ -37,6 +37,24 @@ #define EXAMPLE_INVALID_REASON 255 #define EXAMPLE_INVALID_RSSI -128 +#if CONFIG_ESP_WIFI_AUTH_OPEN +#define EXAMPLE_WIFI_SCAN_AUTH_MODE_THRESHOLD WIFI_AUTH_OPEN +#elif CONFIG_ESP_WIFI_AUTH_WEP +#define EXAMPLE_WIFI_SCAN_AUTH_MODE_THRESHOLD WIFI_AUTH_WEP +#elif CONFIG_ESP_WIFI_AUTH_WPA_PSK +#define EXAMPLE_WIFI_SCAN_AUTH_MODE_THRESHOLD WIFI_AUTH_WPA_PSK +#elif CONFIG_ESP_WIFI_AUTH_WPA2_PSK +#define EXAMPLE_WIFI_SCAN_AUTH_MODE_THRESHOLD WIFI_AUTH_WPA2_PSK +#elif CONFIG_ESP_WIFI_AUTH_WPA_WPA2_PSK +#define EXAMPLE_WIFI_SCAN_AUTH_MODE_THRESHOLD WIFI_AUTH_WPA_WPA2_PSK +#elif CONFIG_ESP_WIFI_AUTH_WPA3_PSK +#define EXAMPLE_WIFI_SCAN_AUTH_MODE_THRESHOLD WIFI_AUTH_WPA3_PSK +#elif CONFIG_ESP_WIFI_AUTH_WPA2_WPA3_PSK +#define EXAMPLE_WIFI_SCAN_AUTH_MODE_THRESHOLD WIFI_AUTH_WPA2_WPA3_PSK +#elif CONFIG_ESP_WIFI_AUTH_WAPI_PSK +#define EXAMPLE_WIFI_SCAN_AUTH_MODE_THRESHOLD WIFI_AUTH_WAPI_PSK +#endif + static void example_event_callback(esp_blufi_cb_event_t event, esp_blufi_cb_param_t *param); #define WIFI_LIST_NUM 10 @@ -372,6 +390,7 @@ static void example_event_callback(esp_blufi_cb_event_t event, esp_blufi_cb_para case ESP_BLUFI_EVENT_RECV_STA_PASSWD: strncpy((char *)sta_config.sta.password, (char *)param->sta_passwd.passwd, param->sta_passwd.passwd_len); sta_config.sta.password[param->sta_passwd.passwd_len] = '\0'; + sta_config.sta.threshold.authmode = EXAMPLE_WIFI_SCAN_AUTH_MODE_THRESHOLD; esp_wifi_set_config(WIFI_IF_STA, &sta_config); BLUFI_INFO("Recv STA PASSWORD %s\n", sta_config.sta.password); break; From 6d06f5fe441182a20d9d251d49353812e6d8a3f0 Mon Sep 17 00:00:00 2001 From: Ivan Grokhotkov Date: Mon, 9 Dec 2024 11:00:48 +0100 Subject: [PATCH 033/118] fix(esp_eth): fix openeth driver to consider MAC address set in QEMU Openeth driver did not consider the possibility that the MAC address was specified when launching QEMU, and would always overwrite that address with the address obtained from esp_read_mac. When running QEMU, setting the MAC address via QEMU arguments is more convenient than crafting an eFuse file with the correct MAC address. This change modifies openeth driver to first check if an address has been set in QEMU and uses it if so. Otherwise it falls back to the address obtained from esp_read_mac. As part of this change, also removed the unnecessary variable emac_opencores_t::addr, the address is only kept in the registers of the emulated peripheral now. For full effect this also requires changes in QEMU, see https://github.com/espressif/qemu/issues/107 for background. Without changes in QEMU, this commit keeps the same behavior. --- .../esp_eth/src/openeth/esp_eth_mac_openeth.c | 31 ++++++++++++++----- 1 file changed, 24 insertions(+), 7 deletions(-) diff --git a/components/esp_eth/src/openeth/esp_eth_mac_openeth.c b/components/esp_eth/src/openeth/esp_eth_mac_openeth.c index 0cf8d914423..2883a64680f 100644 --- a/components/esp_eth/src/openeth/esp_eth_mac_openeth.c +++ b/components/esp_eth/src/openeth/esp_eth_mac_openeth.c @@ -38,7 +38,6 @@ typedef struct { TaskHandle_t rx_task_hdl; int cur_rx_desc; int cur_tx_desc; - uint8_t addr[6]; uint8_t *rx_buf[RX_BUF_COUNT]; uint8_t *tx_buf[TX_BUF_COUNT]; } emac_opencores_t; @@ -143,8 +142,6 @@ static esp_err_t emac_opencores_set_addr(esp_eth_mac_t *mac, uint8_t *addr) ESP_LOGV(TAG, "%s: " MACSTR, __func__, MAC2STR(addr)); esp_err_t ret = ESP_OK; ESP_GOTO_ON_FALSE(addr, ESP_ERR_INVALID_ARG, err, TAG, "can't set mac addr to null"); - emac_opencores_t *emac = __containerof(mac, emac_opencores_t, parent); - memcpy(emac->addr, addr, 6); const uint8_t mac0[4] = {addr[5], addr[4], addr[3], addr[2]}; const uint8_t mac1[4] = {addr[1], addr[0]}; uint32_t mac0_u32, mac1_u32; @@ -162,8 +159,17 @@ static esp_err_t emac_opencores_get_addr(esp_eth_mac_t *mac, uint8_t *addr) ESP_LOGV(TAG, "%s: " MACSTR, __func__, MAC2STR(addr)); esp_err_t ret = ESP_OK; ESP_GOTO_ON_FALSE(addr, ESP_ERR_INVALID_ARG, err, TAG, "can't set mac addr to null"); - emac_opencores_t *emac = __containerof(mac, emac_opencores_t, parent); - memcpy(addr, emac->addr, 6); + uint32_t mac0_u32 = REG_READ(OPENETH_MAC_ADDR0_REG); + uint32_t mac1_u32 = REG_READ(OPENETH_MAC_ADDR1_REG); + const uint8_t mac_addr[ETH_ADDR_LEN] = { + (mac1_u32 >> 8) & 0xFF, + mac1_u32 & 0xFF, + (mac0_u32 >> 24) & 0xFF, + (mac0_u32 >> 16) & 0xFF, + (mac0_u32 >> 8) & 0xFF, + mac0_u32 & 0xFF, + }; + memcpy(addr, mac_addr, ETH_ADDR_LEN); return ESP_OK; err: return ret; @@ -288,7 +294,6 @@ static esp_err_t emac_opencores_init(esp_eth_mac_t *mac) emac_opencores_t *emac = __containerof(mac, emac_opencores_t, parent); esp_eth_mediator_t *eth = emac->eth; ESP_GOTO_ON_ERROR(eth->on_state_changed(eth, ETH_STATE_LLINIT, NULL), err, TAG, "lowlevel init failed"); - ESP_GOTO_ON_ERROR(esp_read_mac(emac->addr, ESP_MAC_ETH), err, TAG, "fetch ethernet mac address failed"); // Sanity check if (REG_READ(OPENETH_MODER_REG) != OPENETH_MODER_DEFAULT) { @@ -299,7 +304,19 @@ static esp_err_t emac_opencores_init(esp_eth_mac_t *mac) // Initialize the MAC openeth_reset(); openeth_set_tx_desc_cnt(TX_BUF_COUNT); - emac_opencores_set_addr(mac, emac->addr); + + // Check if MAC address has been set in QEMU + uint8_t mac_addr[ETH_ADDR_LEN]; + emac_opencores_get_addr(mac, mac_addr); + const uint8_t zero_mac[ETH_ADDR_LEN] = {0}; + if (memcmp(mac_addr, zero_mac, ETH_ADDR_LEN) != 0) { + ESP_LOGD(TAG, "Using MAC address " MACSTR " set in QEMU", MAC2STR(mac_addr)); + } else { + // Fall back to the default MAC address + ESP_GOTO_ON_ERROR(esp_read_mac(mac_addr, ESP_MAC_ETH), err, TAG, "fetch ethernet mac address failed"); + ESP_LOGD(TAG, "Using MAC address " MACSTR " from esp_read_mac", MAC2STR(mac_addr)); + emac_opencores_set_addr(mac, mac_addr); + } return ESP_OK; err: From 72f46b82a11fd2669cbacd688afe8a28150f68fd Mon Sep 17 00:00:00 2001 From: luoxu Date: Wed, 11 Dec 2024 11:29:05 +0800 Subject: [PATCH 034/118] fix(ble_mesh): compile bug fixed for ble mesh on ble 5.0 --- components/bt/esp_ble_mesh/core/bluedroid_host/adapter.c | 3 ++- components/bt/esp_ble_mesh/core/nimble_host/adapter.c | 3 +-- 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/components/bt/esp_ble_mesh/core/bluedroid_host/adapter.c b/components/bt/esp_ble_mesh/core/bluedroid_host/adapter.c index 6bc2d1d64ef..5664c9b6ccf 100644 --- a/components/bt/esp_ble_mesh/core/bluedroid_host/adapter.c +++ b/components/bt/esp_ble_mesh/core/bluedroid_host/adapter.c @@ -656,7 +656,8 @@ int bt_le_ext_adv_start(const uint8_t inst_id, * not smaller than 10ms, then we will use a random adv interval between * [interval / 2, interval] for them. */ - if (adv_type == BLE_MESH_ADV_NONCONN_IND && interval >= 16) { + if (ext_adv_params.type == BTA_DM_BLE_GAP_SET_EXT_ADV_PROP_LEGACY_NONCONN + && interval >= 16) { interval >>= 1; interval += (bt_mesh_get_rand() % (interval + 1)); diff --git a/components/bt/esp_ble_mesh/core/nimble_host/adapter.c b/components/bt/esp_ble_mesh/core/nimble_host/adapter.c index cafa20156f1..4816f29af0d 100644 --- a/components/bt/esp_ble_mesh/core/nimble_host/adapter.c +++ b/components/bt/esp_ble_mesh/core/nimble_host/adapter.c @@ -1207,8 +1207,7 @@ int bt_le_ext_adv_start(const uint8_t inst_id, * not smaller than 10ms, then we will use a random adv interval between * [interval / 2, interval] for them. */ - if (adv_params.conn_mode == BLE_GAP_CONN_MODE_NON && - adv_params.disc_mode == BLE_GAP_DISC_MODE_NON && interval >= 16) { + if (adv_params.legacy_pdu && interval >= 16) { interval >>= 1; interval += (bt_mesh_get_rand() % (interval + 1)); From 2b2d56306b82fc14c3c02d4077fda6b2b1e7cac0 Mon Sep 17 00:00:00 2001 From: Armando Date: Wed, 11 Dec 2024 11:41:03 +0800 Subject: [PATCH 035/118] change(lp_i2s): coverity: remove not necessary null pointer check --- components/esp_driver_i2s/lp_i2s.c | 8 +++----- 1 file changed, 3 insertions(+), 5 deletions(-) diff --git a/components/esp_driver_i2s/lp_i2s.c b/components/esp_driver_i2s/lp_i2s.c index 82284bdd463..2c465661706 100644 --- a/components/esp_driver_i2s/lp_i2s.c +++ b/components/esp_driver_i2s/lp_i2s.c @@ -116,11 +116,9 @@ esp_err_t lp_i2s_new_channel(const lp_i2s_chan_config_t *chan_cfg, lp_i2s_chan_h return ESP_OK; err0: - if (ctlr->rx_chan) { - vSemaphoreDeleteWithCaps(ctlr->rx_chan->semphr); - free(ctlr->rx_chan); - ctlr->rx_chan = NULL; - } + vSemaphoreDeleteWithCaps(ctlr->rx_chan->semphr); + free(ctlr->rx_chan); + ctlr->rx_chan = NULL; err1: /* if the controller object has no channel, find the corresponding global object and destroy it */ From 6d1160b2e61a3e782699cb14fb0f70c05b121b30 Mon Sep 17 00:00:00 2001 From: chenjianhua Date: Wed, 6 Nov 2024 14:52:04 +0800 Subject: [PATCH 036/118] feat(bt/bluedroid): Added config for saving BLE bonding keys to NVS --- components/bt/host/bluedroid/Kconfig.in | 7 +++++++ components/bt/host/bluedroid/btc/core/btc_dm.c | 13 +++++++++---- .../common/include/common/bluedroid_user_config.h | 6 ++++++ .../bluedroid/common/include/common/bt_target.h | 6 ++++++ 4 files changed, 28 insertions(+), 4 deletions(-) diff --git a/components/bt/host/bluedroid/Kconfig.in b/components/bt/host/bluedroid/Kconfig.in index 2c6412d862f..99d85eedcd0 100644 --- a/components/bt/host/bluedroid/Kconfig.in +++ b/components/bt/host/bluedroid/Kconfig.in @@ -381,6 +381,13 @@ config BT_BLE_SMP_ID_RESET_ENABLE of a previously paired peer to be used to determine whether a device with which it previously shared an IRK is within range. +config BT_BLE_SMP_BOND_NVS_FLASH + bool "Save SMP bonding keys to nvs flash" + depends on BT_BLE_SMP_ENABLE + default y + help + This select can save SMP bonding keys to nvs flash + config BT_STACK_NO_LOG bool "Disable BT debug logs (minimize bin size)" depends on BT_BLUEDROID_ENABLED diff --git a/components/bt/host/bluedroid/btc/core/btc_dm.c b/components/bt/host/bluedroid/btc/core/btc_dm.c index 52dbd77c181..c50d8884744 100644 --- a/components/bt/host/bluedroid/btc/core/btc_dm.c +++ b/components/bt/host/bluedroid/btc/core/btc_dm.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2015-2023 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2015-2024 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -182,11 +182,12 @@ static void btc_dm_remove_ble_bonding_keys(void) btc_storage_remove_ble_bonding_keys(&bd_addr); } +#if BLE_SMP_BOND_NVS_FLASH static void btc_dm_save_ble_bonding_keys(void) { if (!(btc_dm_cb.pairing_cb.ble.is_penc_key_rcvd || btc_dm_cb.pairing_cb.ble.is_pid_key_rcvd || btc_dm_cb.pairing_cb.ble.is_pcsrk_key_rcvd || - btc_dm_cb.pairing_cb.ble.is_lenc_key_rcvd || btc_dm_cb.pairing_cb.ble.is_lcsrk_key_rcvd || btc_dm_cb.pairing_cb.ble.is_lidk_key_rcvd)) { - return ; + btc_dm_cb.pairing_cb.ble.is_lenc_key_rcvd || btc_dm_cb.pairing_cb.ble.is_lcsrk_key_rcvd || btc_dm_cb.pairing_cb.ble.is_lidk_key_rcvd)) { + return; } bt_bdaddr_t bd_addr; @@ -244,13 +245,13 @@ static void btc_dm_save_ble_bonding_keys(void) btc_dm_cb.pairing_cb.ble.is_lidk_key_rcvd = false; } } +#endif static void btc_dm_ble_auth_cmpl_evt (tBTA_DM_AUTH_CMPL *p_auth_cmpl) { /* Save link key, if not temporary */ BTC_TRACE_DEBUG("%s, status = %d", __func__, p_auth_cmpl->success); bt_status_t status = BT_STATUS_FAIL; - int addr_type; bt_bdaddr_t bdaddr; bdcpy(bdaddr.address, p_auth_cmpl->bd_addr); bdcpy(btc_dm_cb.pairing_cb.bd_addr, p_auth_cmpl->bd_addr); @@ -266,6 +267,9 @@ static void btc_dm_ble_auth_cmpl_evt (tBTA_DM_AUTH_CMPL *p_auth_cmpl) return; } +#if BLE_SMP_BOND_NVS_FLASH + int addr_type; + if (btc_dm_cb.pairing_cb.ble.is_pid_key_rcvd) { // delete unused section in NVS btc_storage_remove_unused_sections(p_auth_cmpl->bd_addr, &btc_dm_cb.pairing_cb.ble.pid_key); @@ -276,6 +280,7 @@ static void btc_dm_ble_auth_cmpl_evt (tBTA_DM_AUTH_CMPL *p_auth_cmpl) } btc_storage_set_ble_dev_auth_mode(&bdaddr, p_auth_cmpl->auth_mode, true); btc_dm_save_ble_bonding_keys(); +#endif } else { /*Map the HCI fail reason to bt status */ switch (p_auth_cmpl->fail_reason) { diff --git a/components/bt/host/bluedroid/common/include/common/bluedroid_user_config.h b/components/bt/host/bluedroid/common/include/common/bluedroid_user_config.h index 9cf478c4f61..2f109219d53 100644 --- a/components/bt/host/bluedroid/common/include/common/bluedroid_user_config.h +++ b/components/bt/host/bluedroid/common/include/common/bluedroid_user_config.h @@ -270,6 +270,12 @@ #define UC_BT_BLE_SMP_ID_RESET_ENABLE FALSE #endif +#ifdef CONFIG_BT_BLE_SMP_BOND_NVS_FLASH +#define UC_BT_BLE_SMP_BOND_NVS_FLASH CONFIG_BT_BLE_SMP_BOND_NVS_FLASH +#else +#define UC_BT_BLE_SMP_BOND_NVS_FLASH FALSE +#endif + //Device Name Maximum Length #ifdef CONFIG_BT_MAX_DEVICE_NAME_LEN #define UC_MAX_LOC_BD_NAME_LEN CONFIG_BT_MAX_DEVICE_NAME_LEN diff --git a/components/bt/host/bluedroid/common/include/common/bt_target.h b/components/bt/host/bluedroid/common/include/common/bt_target.h index 239433620b2..31423356944 100644 --- a/components/bt/host/bluedroid/common/include/common/bt_target.h +++ b/components/bt/host/bluedroid/common/include/common/bt_target.h @@ -326,6 +326,12 @@ #define BLE_SMP_ID_RESET_ENABLE FALSE #endif +#if (UC_BT_BLE_SMP_BOND_NVS_FLASH) +#define BLE_SMP_BOND_NVS_FLASH TRUE +#else +#define BLE_SMP_BOND_NVS_FLASH FALSE +#endif + #ifdef UC_BTDM_BLE_ADV_REPORT_FLOW_CTRL_SUPP #define BLE_ADV_REPORT_FLOW_CONTROL (UC_BTDM_BLE_ADV_REPORT_FLOW_CTRL_SUPP && BLE_INCLUDED) #endif /* UC_BTDM_BLE_ADV_REPORT_FLOW_CTRL_SUPP */ From 23455ea9c209c431a05bbaf8fed94335571cb713 Mon Sep 17 00:00:00 2001 From: chenjianhua Date: Mon, 25 Nov 2024 19:15:13 +0800 Subject: [PATCH 037/118] fix(bt/bluedroid): Fixed failure to get host status when host is not enabled --- components/bt/host/bluedroid/btc/core/btc_main.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/components/bt/host/bluedroid/btc/core/btc_main.c b/components/bt/host/bluedroid/btc/core/btc_main.c index de90708e6bb..5fe01627fce 100644 --- a/components/bt/host/bluedroid/btc/core/btc_main.c +++ b/components/bt/host/bluedroid/btc/core/btc_main.c @@ -122,6 +122,11 @@ uint32_t btc_get_ble_status(void) { uint32_t status = BTC_BLE_STATUS_IDLE; + if (esp_bluedroid_get_status() != ESP_BLUEDROID_STATUS_ENABLED) { + BTC_TRACE_ERROR("%s Bluedroid not enabled", __func__); + return status; + } + #if (BLE_INCLUDED == TRUE) // Number of active advertising extern uint8_t btm_ble_adv_active_count(void); From 6528ab59713b30a1e49498977fe6c365fb25a22e Mon Sep 17 00:00:00 2001 From: Armando Date: Tue, 3 Dec 2024 12:13:00 +0800 Subject: [PATCH 038/118] refactor(mspi): refactor mspi clock src settings --- .../src/bootloader_flash_config_esp32c5.c | 2 +- .../src/bootloader_flash_config_esp32c61.c | 2 +- .../src/bootloader_flash_config_esp32p4.c | 6 +- .../mspi_timing_tuning/mspi_timing_tuning.c | 22 ++------ .../port/esp32p4/mspi_timing_config.c | 2 +- .../esp32/include/hal/mspi_timing_tuning_ll.h | 7 +++ .../include/hal/mspi_timing_tuning_ll.h | 7 +++ .../include/hal/mspi_timing_tuning_ll.h | 7 +++ .../include/hal/mspi_timing_tuning_ll.h | 17 +++--- .../include/hal/mspi_timing_tuning_ll.h | 7 +++ .../include/hal/mspi_timing_tuning_ll.h | 17 +++--- .../include/hal/mspi_timing_tuning_ll.h | 55 +++++++++++++++++++ .../hal/esp32h2/include/hal/spimem_flash_ll.h | 21 ------- .../include/hal/mspi_timing_tuning_ll.h | 50 +++++++++++++++-- .../hal/esp32p4/include/hal/spimem_flash_ll.h | 53 ------------------ .../include/hal/mspi_timing_tuning_ll.h | 7 +++ .../esp32c5/include/soc/Kconfig.soc_caps.in | 4 -- .../soc/esp32c5/include/soc/clk_tree_defs.h | 18 +++--- components/soc/esp32c5/include/soc/soc_caps.h | 1 - .../esp32c61/include/soc/Kconfig.soc_caps.in | 4 -- .../soc/esp32c61/include/soc/clk_tree_defs.h | 20 +++---- .../soc/esp32c61/include/soc/soc_caps.h | 1 - .../esp32h2/include/soc/Kconfig.soc_caps.in | 4 -- .../soc/esp32h2/include/soc/clk_tree_defs.h | 22 ++++---- components/soc/esp32h2/include/soc/soc_caps.h | 1 - 25 files changed, 196 insertions(+), 161 deletions(-) create mode 100644 components/hal/esp32/include/hal/mspi_timing_tuning_ll.h create mode 100644 components/hal/esp32c2/include/hal/mspi_timing_tuning_ll.h create mode 100644 components/hal/esp32c3/include/hal/mspi_timing_tuning_ll.h create mode 100644 components/hal/esp32c6/include/hal/mspi_timing_tuning_ll.h create mode 100644 components/hal/esp32h2/include/hal/mspi_timing_tuning_ll.h create mode 100644 components/hal/esp32s2/include/hal/mspi_timing_tuning_ll.h diff --git a/components/bootloader_support/bootloader_flash/src/bootloader_flash_config_esp32c5.c b/components/bootloader_support/bootloader_flash/src/bootloader_flash_config_esp32c5.c index 01e471ba04b..e79463dd4d6 100644 --- a/components/bootloader_support/bootloader_flash/src/bootloader_flash_config_esp32c5.c +++ b/components/bootloader_support/bootloader_flash/src/bootloader_flash_config_esp32c5.c @@ -53,7 +53,7 @@ void IRAM_ATTR bootloader_init_mspi_clock(void) // Set source mspi pll clock as 80M in bootloader stage. // SPLL clock on C5 is 480MHz , and mspi_pll needs 80MHz // in this stage, set divider as 6 - mspi_ll_clock_src_sel(MSPI_CLK_SRC_SPLL); + _mspi_timing_ll_set_flash_clk_src(0, FLASH_CLK_SRC_SPLL); mspi_ll_fast_set_hs_divider(6); } diff --git a/components/bootloader_support/bootloader_flash/src/bootloader_flash_config_esp32c61.c b/components/bootloader_support/bootloader_flash/src/bootloader_flash_config_esp32c61.c index 6ef110e10d7..63cba4e72e4 100644 --- a/components/bootloader_support/bootloader_flash/src/bootloader_flash_config_esp32c61.c +++ b/components/bootloader_support/bootloader_flash/src/bootloader_flash_config_esp32c61.c @@ -51,7 +51,7 @@ void IRAM_ATTR bootloader_init_mspi_clock(void) // Set source mspi pll clock as 80M in bootloader stage. // SPLL clock on C61 is 480MHz , and mspi_pll needs 80MHz // in this stage, set divider as 6 - mspi_ll_clock_src_sel(MSPI_CLK_SRC_SPLL); + _mspi_timing_ll_set_flash_clk_src(0, FLASH_CLK_SRC_DEFAULT); mspi_ll_fast_set_hs_divider(6); } diff --git a/components/bootloader_support/bootloader_flash/src/bootloader_flash_config_esp32p4.c b/components/bootloader_support/bootloader_flash/src/bootloader_flash_config_esp32p4.c index a89f176b06c..e696108fd68 100644 --- a/components/bootloader_support/bootloader_flash/src/bootloader_flash_config_esp32p4.c +++ b/components/bootloader_support/bootloader_flash/src/bootloader_flash_config_esp32p4.c @@ -19,7 +19,7 @@ #include "bootloader_init.h" #include "hal/mmu_hal.h" #include "hal/mmu_ll.h" -#include "hal/spimem_flash_ll.h" +#include "hal/mspi_timing_tuning_ll.h" #include "hal/cache_hal.h" #include "hal/cache_ll.h" #include "esp_private/bootloader_flash_internal.h" @@ -44,8 +44,8 @@ void IRAM_ATTR bootloader_flash_cs_timing_config(void) void IRAM_ATTR bootloader_init_mspi_clock(void) { - _spimem_flash_ll_select_clk_source(0, FLASH_CLK_SRC_SPLL); - _spimem_ctrlr_ll_set_core_clock(0, 6); + _mspi_timing_ll_set_flash_clk_src(0, FLASH_CLK_SRC_SPLL); + _mspi_timing_ll_set_flash_core_clock(0, 80); } void IRAM_ATTR bootloader_flash_clock_config(const esp_image_header_t *pfhdr) diff --git a/components/esp_hw_support/mspi_timing_tuning/mspi_timing_tuning.c b/components/esp_hw_support/mspi_timing_tuning/mspi_timing_tuning.c index 3374e2ab91b..af47eedb9c8 100644 --- a/components/esp_hw_support/mspi_timing_tuning/mspi_timing_tuning.c +++ b/components/esp_hw_support/mspi_timing_tuning/mspi_timing_tuning.c @@ -16,6 +16,7 @@ #include "hal/spi_flash_hal.h" #include "hal/cache_hal.h" #include "hal/cache_ll.h" +#include "hal/mspi_timing_tuning_ll.h" #include "esp_private/mspi_timing_tuning.h" #include "esp_private/mspi_timing_config.h" #include "mspi_timing_by_mspi_delay.h" @@ -23,16 +24,11 @@ #include "mspi_timing_by_flash_delay.h" #if SOC_MEMSPI_TIMING_TUNING_BY_MSPI_DELAY || SOC_MEMSPI_TIMING_TUNING_BY_DQS || SOC_MEMSPI_TIMING_TUNING_BY_FLASH_DELAY #include "mspi_timing_tuning_configs.h" -#include "hal/mspi_timing_tuning_ll.h" #endif #if SOC_MEMSPI_CLK_SRC_IS_INDEPENDENT #include "hal/spimem_flash_ll.h" #endif -#if CONFIG_IDF_TARGET_ESP32C5 || CONFIG_IDF_TARGET_ESP32C61 // TODO: IDF-10464 -#include "hal/mspi_timing_tuning_ll.h" -#endif - #if SOC_CACHE_INTERNAL_MEM_VIA_L1CACHE #include "esp_ipc_isr.h" #endif @@ -469,13 +465,9 @@ void mspi_timing_psram_tuning(void) *----------------------------------------------------------------------------*/ void mspi_timing_enter_low_speed_mode(bool control_spi1) { -#if SOC_MEMSPI_FLASH_CLK_SRC_IS_INDEPENDENT -#if CONFIG_IDF_TARGET_ESP32C5 || CONFIG_IDF_TARGET_ESP32C61 // TODO: IDF-10464 - mspi_ll_clock_src_sel(MSPI_CLK_SRC_XTAL); -#else - spimem_flash_ll_set_clock_source(MSPI_CLK_SRC_ROM_DEFAULT); +#if MSPI_TIMING_LL_FLASH_CLK_SRC_CHANGEABLE + _mspi_timing_ll_set_flash_clk_src(0, FLASH_CLK_SRC_ROM_DEFAULT); #endif -#endif //SOC_MEMSPI_FLASH_CLK_SRC_IS_INDEPENDENT #if SOC_SPI_MEM_SUPPORT_TIMING_TUNING /** @@ -509,13 +501,9 @@ void mspi_timing_enter_low_speed_mode(bool control_spi1) */ void mspi_timing_enter_high_speed_mode(bool control_spi1) { -#if SOC_MEMSPI_FLASH_CLK_SRC_IS_INDEPENDENT -#if CONFIG_IDF_TARGET_ESP32C5 || CONFIG_IDF_TARGET_ESP32C61// TODO: IDF-10464 - mspi_ll_clock_src_sel(MSPI_CLK_SRC_SPLL); -#else - spimem_flash_ll_set_clock_source(MSPI_CLK_SRC_DEFAULT); +#if MSPI_TIMING_LL_FLASH_CLK_SRC_CHANGEABLE + _mspi_timing_ll_set_flash_clk_src(0, FLASH_CLK_SRC_DEFAULT); #endif -#endif //SOC_MEMSPI_FLASH_CLK_SRC_IS_INDEPENDENT #if SOC_SPI_MEM_SUPPORT_TIMING_TUNING /** diff --git a/components/esp_hw_support/mspi_timing_tuning/port/esp32p4/mspi_timing_config.c b/components/esp_hw_support/mspi_timing_tuning/port/esp32p4/mspi_timing_config.c index 230e2c072a2..c76fcb5b326 100644 --- a/components/esp_hw_support/mspi_timing_tuning/port/esp32p4/mspi_timing_config.c +++ b/components/esp_hw_support/mspi_timing_tuning/port/esp32p4/mspi_timing_config.c @@ -40,7 +40,7 @@ void mspi_timing_config_set_flash_clock(uint32_t flash_freq_mhz, mspi_timing_spe #if MSPI_TIMING_FLASH_NEEDS_TUNING assert(HP_SYS_CLKRST.peri_clk_ctrl00.reg_flash_clk_src_sel == 1); - uint32_t core_clock_mhz = MSPI_TIMING_SPLL_FREQ_MHZ / MSPI_TIMING_LL_FLASH_CORE_CLK_DIV; + uint32_t core_clock_mhz = MSPI_TIMING_SPLL_FREQ_MHZ / MSPI_TIMING_LL_HP_FLASH_CORE_CLK_DIV; assert(core_clock_mhz == 120); uint32_t freqdiv = core_clock_mhz / flash_freq_mhz; diff --git a/components/hal/esp32/include/hal/mspi_timing_tuning_ll.h b/components/hal/esp32/include/hal/mspi_timing_tuning_ll.h new file mode 100644 index 00000000000..e351c867a19 --- /dev/null +++ b/components/hal/esp32/include/hal/mspi_timing_tuning_ll.h @@ -0,0 +1,7 @@ +/* + * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +//For compatibility diff --git a/components/hal/esp32c2/include/hal/mspi_timing_tuning_ll.h b/components/hal/esp32c2/include/hal/mspi_timing_tuning_ll.h new file mode 100644 index 00000000000..e351c867a19 --- /dev/null +++ b/components/hal/esp32c2/include/hal/mspi_timing_tuning_ll.h @@ -0,0 +1,7 @@ +/* + * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +//For compatibility diff --git a/components/hal/esp32c3/include/hal/mspi_timing_tuning_ll.h b/components/hal/esp32c3/include/hal/mspi_timing_tuning_ll.h new file mode 100644 index 00000000000..e351c867a19 --- /dev/null +++ b/components/hal/esp32c3/include/hal/mspi_timing_tuning_ll.h @@ -0,0 +1,7 @@ +/* + * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +//For compatibility diff --git a/components/hal/esp32c5/include/hal/mspi_timing_tuning_ll.h b/components/hal/esp32c5/include/hal/mspi_timing_tuning_ll.h index 2d4416657fb..e84e456ccb7 100644 --- a/components/hal/esp32c5/include/hal/mspi_timing_tuning_ll.h +++ b/components/hal/esp32c5/include/hal/mspi_timing_tuning_ll.h @@ -21,21 +21,24 @@ extern "C" { /************************** MSPI pll clock configurations **************************/ -/** - * @brief Select mspi clock source +/* + * @brief Select FLASH clock source * - * @param clk_src the clock source of mspi clock + * @param mspi_id mspi_id + * @param clk_src clock source, see valid sources in type `soc_periph_flash_clk_src_t` */ -static inline __attribute__((always_inline)) void mspi_ll_clock_src_sel(soc_periph_mspi_clk_src_t clk_src) +__attribute__((always_inline)) +static inline void _mspi_timing_ll_set_flash_clk_src(uint32_t mspi_id, soc_periph_flash_clk_src_t clk_src) { + HAL_ASSERT(mspi_id == 0); switch (clk_src) { - case MSPI_CLK_SRC_XTAL: + case FLASH_CLK_SRC_XTAL: PCR.mspi_clk_conf.mspi_func_clk_sel = 0; break; - case MSPI_CLK_SRC_RC_FAST: + case FLASH_CLK_SRC_RC_FAST: PCR.mspi_clk_conf.mspi_func_clk_sel = 1; break; - case MSPI_CLK_SRC_SPLL: + case FLASH_CLK_SRC_SPLL: PCR.mspi_clk_conf.mspi_func_clk_sel = 2; break; default: diff --git a/components/hal/esp32c6/include/hal/mspi_timing_tuning_ll.h b/components/hal/esp32c6/include/hal/mspi_timing_tuning_ll.h new file mode 100644 index 00000000000..e351c867a19 --- /dev/null +++ b/components/hal/esp32c6/include/hal/mspi_timing_tuning_ll.h @@ -0,0 +1,7 @@ +/* + * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +//For compatibility diff --git a/components/hal/esp32c61/include/hal/mspi_timing_tuning_ll.h b/components/hal/esp32c61/include/hal/mspi_timing_tuning_ll.h index 9a01d99830e..93ae05e2a4d 100644 --- a/components/hal/esp32c61/include/hal/mspi_timing_tuning_ll.h +++ b/components/hal/esp32c61/include/hal/mspi_timing_tuning_ll.h @@ -21,21 +21,24 @@ extern "C" { /************************** MSPI pll clock configurations **************************/ -/** - * @brief Select mspi clock source +/* + * @brief Select FLASH clock source * - * @param clk_src the clock source of mspi clock + * @param mspi_id mspi_id + * @param clk_src clock source, see valid sources in type `soc_periph_flash_clk_src_t` */ -static inline __attribute__((always_inline)) void mspi_ll_clock_src_sel(soc_periph_mspi_clk_src_t clk_src) +__attribute__((always_inline)) +static inline void _mspi_timing_ll_set_flash_clk_src(uint32_t mspi_id, soc_periph_flash_clk_src_t clk_src) { + HAL_ASSERT(mspi_id == 0); switch (clk_src) { - case MSPI_CLK_SRC_XTAL: + case FLASH_CLK_SRC_XTAL: PCR.mspi_clk_conf.mspi_func_clk_sel = 0; break; - case MSPI_CLK_SRC_RC_FAST: + case FLASH_CLK_SRC_RC_FAST: PCR.mspi_clk_conf.mspi_func_clk_sel = 1; break; - case MSPI_CLK_SRC_SPLL: + case FLASH_CLK_SRC_SPLL: PCR.mspi_clk_conf.mspi_func_clk_sel = 2; break; default: diff --git a/components/hal/esp32h2/include/hal/mspi_timing_tuning_ll.h b/components/hal/esp32h2/include/hal/mspi_timing_tuning_ll.h new file mode 100644 index 00000000000..7684e1b5b95 --- /dev/null +++ b/components/hal/esp32h2/include/hal/mspi_timing_tuning_ll.h @@ -0,0 +1,55 @@ +/* + * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#pragma once + +#include +#include +#include "soc/soc.h" +#include "soc/clk_tree_defs.h" +#include "soc/pcr_struct.h" +#include "hal/misc.h" +#include "hal/assert.h" + +#ifdef __cplusplus +extern "C" { +#endif + +//Timing tuning not applied, and flash has its own clock source. Can change flash clock source +#define MSPI_TIMING_LL_FLASH_CLK_SRC_CHANGEABLE 1 + +/************************** MSPI pll clock configurations **************************/ +/* + * @brief Select FLASH clock source + * + * @param mspi_id mspi_id + * @param clk_src clock source, see valid sources in type `soc_periph_flash_clk_src_t` + */ +__attribute__((always_inline)) +static inline void _mspi_timing_ll_set_flash_clk_src(uint32_t mspi_id, soc_periph_flash_clk_src_t clk_src) +{ + HAL_ASSERT(mspi_id == 0); + switch (clk_src) { + case FLASH_CLK_SRC_XTAL: + PCR.mspi_conf.mspi_clk_sel = 0; + break; + case FLASH_CLK_SRC_RC_FAST: + PCR.mspi_conf.mspi_clk_sel = 1; + break; + case FLASH_CLK_SRC_PLL_F64M: + PCR.mspi_conf.mspi_clk_sel = 2; + break; + case FLASH_CLK_SRC_PLL_F48M: + PCR.mspi_conf.mspi_clk_sel = 3; + break; + default: + HAL_ASSERT(false); + } +} + +#ifdef __cplusplus +} +#endif diff --git a/components/hal/esp32h2/include/hal/spimem_flash_ll.h b/components/hal/esp32h2/include/hal/spimem_flash_ll.h index feaf317f74d..94e7b655652 100644 --- a/components/hal/esp32h2/include/hal/spimem_flash_ll.h +++ b/components/hal/esp32h2/include/hal/spimem_flash_ll.h @@ -474,27 +474,6 @@ static inline void spimem_flash_ll_set_read_mode(spi_mem_dev_t *dev, esp_flash_i dev->ctrl.val = ctrl.val; } -__attribute__((always_inline)) -static inline void spimem_flash_ll_set_clock_source(soc_periph_mspi_clk_src_t clk_src) -{ - switch (clk_src) { - case MSPI_CLK_SRC_XTAL: - PCR.mspi_conf.mspi_clk_sel = 0; - break; - case MSPI_CLK_SRC_RC_FAST: - PCR.mspi_conf.mspi_clk_sel = 1; - break; - case MSPI_CLK_SRC_PLL_F64M: - PCR.mspi_conf.mspi_clk_sel = 2; - break; - case MSPI_CLK_SRC_PLL_F48M: - PCR.mspi_conf.mspi_clk_sel = 3; - break; - default: - HAL_ASSERT(false); - } -} - /** * Set clock frequency to work at. * diff --git a/components/hal/esp32p4/include/hal/mspi_timing_tuning_ll.h b/components/hal/esp32p4/include/hal/mspi_timing_tuning_ll.h index 9d83a7ccb22..2fd090a4af0 100644 --- a/components/hal/esp32p4/include/hal/mspi_timing_tuning_ll.h +++ b/components/hal/esp32p4/include/hal/mspi_timing_tuning_ll.h @@ -23,6 +23,7 @@ #include "soc/hp_sys_clkrst_struct.h" #include "soc/spi_mem_c_reg.h" #include "soc/spi1_mem_c_reg.h" +#include "soc/clk_tree_defs.h" #ifdef __cplusplus extern "C" { @@ -31,7 +32,8 @@ extern "C" { #define MSPI_TIMING_LL_MSPI_ID_0 0 #define MSPI_TIMING_LL_MSPI_ID_1 1 -#define MSPI_TIMING_LL_FLASH_CORE_CLK_DIV 4 +#define MSPI_TIMING_LL_HP_FLASH_CORE_CLK_DIV 4 +#define MSPI_TIMING_LL_LP_FLASH_CORE_CLK_DIV 6 #define MSPI_TIMING_LL_FLASH_FDUMMY_RIN_SUPPORTED 1 #define MSPI_TIMING_LL_FLASH_OCT_MASK (SPI_MEM_C_FCMD_OCT | SPI_MEM_C_FADDR_OCT | SPI_MEM_C_FDIN_OCT | SPI_MEM_C_FDOUT_OCT) @@ -238,6 +240,41 @@ static inline void mspi_timing_ll_pin_drv_set(uint8_t drv) /*--------------------------------------------------------------- Flash tuning ---------------------------------------------------------------*/ +/* + * @brief Select FLASH clock source + * + * @param mspi_id mspi_id + * @param clk_src clock source, see valid sources in type `soc_periph_flash_clk_src_t` + */ +__attribute__((always_inline)) +static inline void _mspi_timing_ll_set_flash_clk_src(uint32_t mspi_id, soc_periph_flash_clk_src_t clk_src) +{ + HAL_ASSERT(mspi_id == MSPI_TIMING_LL_MSPI_ID_0); + uint32_t clk_val = 0; + switch (clk_src) { + case FLASH_CLK_SRC_XTAL: + clk_val = 0; + break; + case FLASH_CLK_SRC_SPLL: + clk_val = 1; + break; + case FLASH_CLK_SRC_CPLL: + clk_val = 2; + break; + default: + HAL_ASSERT(false); + break; + } + + HP_SYS_CLKRST.soc_clk_ctrl0.reg_flash_sys_clk_en = 1; + HP_SYS_CLKRST.peri_clk_ctrl00.reg_flash_pll_clk_en = 1; + HP_SYS_CLKRST.peri_clk_ctrl00.reg_flash_clk_src_sel = clk_val; +} + +/// use a macro to wrap the function, force the caller to use it in a critical section +/// the critical section needs to declare the __DECLARE_RCC_ATOMIC_ENV variable in advance +#define mspi_timing_ll_set_flash_clk_src(...) (void)__DECLARE_RCC_ATOMIC_ENV; _mspi_timing_ll_set_flash_clk_src(__VA_ARGS__) + /** * Set MSPI Flash core clock * @@ -247,12 +284,15 @@ static inline void mspi_timing_ll_pin_drv_set(uint8_t drv) __attribute__((always_inline)) static inline void _mspi_timing_ll_set_flash_core_clock(int spi_num, uint32_t core_clk_mhz) { - (void)spi_num; + HAL_ASSERT(spi_num == MSPI_TIMING_LL_MSPI_ID_0); if (core_clk_mhz == 120) { - HAL_FORCE_MODIFY_U32_REG_FIELD(HP_SYS_CLKRST.peri_clk_ctrl00, reg_flash_core_clk_div_num, (MSPI_TIMING_LL_FLASH_CORE_CLK_DIV - 1)); + HAL_FORCE_MODIFY_U32_REG_FIELD(HP_SYS_CLKRST.peri_clk_ctrl00, reg_flash_core_clk_div_num, (MSPI_TIMING_LL_HP_FLASH_CORE_CLK_DIV - 1)); + HP_SYS_CLKRST.peri_clk_ctrl00.reg_flash_core_clk_en = 1; + } else if (core_clk_mhz == 80) { + HAL_FORCE_MODIFY_U32_REG_FIELD(HP_SYS_CLKRST.peri_clk_ctrl00, reg_flash_core_clk_div_num, (MSPI_TIMING_LL_LP_FLASH_CORE_CLK_DIV - 1)); HP_SYS_CLKRST.peri_clk_ctrl00.reg_flash_core_clk_en = 1; } else { - //ESP32P4 flash timing tuning is based on SPLL==480MHz, flash_core_clock==120MHz. We add assertion here to ensure this + //ESP32P4 flash timing tuning is based on SPLL==480MHz, flash_core_clock==120MHz / 80MHz. We add assertion here to ensure this HAL_ASSERT(false); } } @@ -297,7 +337,7 @@ static inline void mspi_timing_ll_set_flash_clock(uint8_t spi_num, uint32_t freq __attribute__((always_inline)) static inline void mspi_timinng_ll_enable_flash_timing_adjust_clk(uint8_t spi_num) { - (void)spi_num; + HAL_ASSERT(spi_num == MSPI_TIMING_LL_MSPI_ID_0); REG_GET_BIT(SPI_MEM_C_TIMING_CALI_REG, SPI_MEM_C_TIMING_CLK_ENA); } diff --git a/components/hal/esp32p4/include/hal/spimem_flash_ll.h b/components/hal/esp32p4/include/hal/spimem_flash_ll.h index d76bef60e5c..fec3f1294bf 100644 --- a/components/hal/esp32p4/include/hal/spimem_flash_ll.h +++ b/components/hal/esp32p4/include/hal/spimem_flash_ll.h @@ -733,59 +733,6 @@ static inline void spimem_flash_ll_set_dummy_out(spi_mem_dev_t *dev, uint32_t ou dev->ctrl.wp_reg = out_lev; } -/* - * @brief Select FLASH clock source - * - * @param mspi_id mspi_id - * @param clk_src clock source, see valid sources in type `soc_periph_flash_clk_src_t` - */ -__attribute__((always_inline)) -static inline void _spimem_flash_ll_select_clk_source(uint32_t mspi_id, soc_periph_flash_clk_src_t clk_src) -{ - (void)mspi_id; - uint32_t clk_val = 0; - switch (clk_src) { - case FLASH_CLK_SRC_XTAL: - clk_val = 0; - break; - case FLASH_CLK_SRC_SPLL: - clk_val = 1; - break; - case FLASH_CLK_SRC_CPLL: - clk_val = 2; - break; - default: - HAL_ASSERT(false); - break; - } - - HP_SYS_CLKRST.soc_clk_ctrl0.reg_flash_sys_clk_en = 1; - HP_SYS_CLKRST.peri_clk_ctrl00.reg_flash_pll_clk_en = 1; - HP_SYS_CLKRST.peri_clk_ctrl00.reg_flash_clk_src_sel = clk_val; -} - -/// use a macro to wrap the function, force the caller to use it in a critical section -/// the critical section needs to declare the __DECLARE_RCC_ATOMIC_ENV variable in advance -#define spimem_flash_ll_select_clk_source(...) (void)__DECLARE_RCC_ATOMIC_ENV; _spimem_flash_ll_select_clk_source(__VA_ARGS__) - -/** - * @brief Set FLASH core clock - * - * @param mspi_id mspi_id - * @param freqdiv Divider value - */ -__attribute__((always_inline)) -static inline void _spimem_ctrlr_ll_set_core_clock(uint8_t mspi_id, uint32_t freqdiv) -{ - (void)mspi_id; - HP_SYS_CLKRST.peri_clk_ctrl00.reg_flash_core_clk_en = 1; - HAL_FORCE_MODIFY_U32_REG_FIELD(HP_SYS_CLKRST.peri_clk_ctrl00, reg_flash_core_clk_div_num, freqdiv - 1); -} - -/// use a macro to wrap the function, force the caller to use it in a critical section -/// the critical section needs to declare the __DECLARE_RCC_ATOMIC_ENV variable in advance -#define spimem_ctrlr_ll_set_core_clock(...) (void)__DECLARE_RCC_ATOMIC_ENV; _spimem_ctrlr_ll_set_core_clock(__VA_ARGS__) - /** * @brief Disable FLASH MSPI clock * diff --git a/components/hal/esp32s2/include/hal/mspi_timing_tuning_ll.h b/components/hal/esp32s2/include/hal/mspi_timing_tuning_ll.h new file mode 100644 index 00000000000..e351c867a19 --- /dev/null +++ b/components/hal/esp32s2/include/hal/mspi_timing_tuning_ll.h @@ -0,0 +1,7 @@ +/* + * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +//For compatibility diff --git a/components/soc/esp32c5/include/soc/Kconfig.soc_caps.in b/components/soc/esp32c5/include/soc/Kconfig.soc_caps.in index bf586f05872..7340e9d4c83 100644 --- a/components/soc/esp32c5/include/soc/Kconfig.soc_caps.in +++ b/components/soc/esp32c5/include/soc/Kconfig.soc_caps.in @@ -1131,10 +1131,6 @@ config SOC_MEMSPI_SRC_FREQ_20M_SUPPORTED bool default y -config SOC_MEMSPI_FLASH_CLK_SRC_IS_INDEPENDENT - bool - default y - config SOC_SYSTIMER_COUNTER_NUM int default 2 diff --git a/components/soc/esp32c5/include/soc/clk_tree_defs.h b/components/soc/esp32c5/include/soc/clk_tree_defs.h index 2f7d2e97176..e3510ca9b80 100644 --- a/components/soc/esp32c5/include/soc/clk_tree_defs.h +++ b/components/soc/esp32c5/include/soc/clk_tree_defs.h @@ -488,20 +488,20 @@ typedef enum { PARLIO_CLK_SRC_DEFAULT = SOC_MOD_CLK_PLL_F240M, /*!< Select PLL_F240M as the default clock choice */ } soc_periph_parlio_clk_src_t; -//////////////////////////////////////////////////MSPI/////////////////////////////////////////////////////////////////// +//////////////////////////////////////////////////FLASH/////////////////////////////////////////////////////////////////// /** - * @brief Array initializer for all supported clock sources of MSPI digital controller + * @brief Array initializer for all supported clock sources of FLASH MSPI controller */ -#define SOC_MSPI_CLKS {SOC_MOD_CLK_XTAL, SOC_MOD_CLK_RC_FAST, SOC_MOD_CLK_SPLL} +#define SOC_FLASH_CLKS {SOC_MOD_CLK_XTAL, SOC_MOD_CLK_RC_FAST, SOC_MOD_CLK_SPLL} /** - * @brief MSPI digital controller clock source + * @brief FLASH MSPI controller clock source */ typedef enum { - MSPI_CLK_SRC_XTAL = SOC_MOD_CLK_XTAL, /*!< Select XTAL as the source clock */ - MSPI_CLK_SRC_RC_FAST = SOC_MOD_CLK_RC_FAST, /*!< Select RC_FAST as the source clock */ - MSPI_CLK_SRC_SPLL = SOC_MOD_CLK_SPLL, /*!< Select SPLL as the source clock */ - MSPI_CLK_SRC_ROM_DEFAULT = SOC_MOD_CLK_XTAL, /*!< Select XTAL as ROM default clock source */ -} soc_periph_mspi_clk_src_t; + FLASH_CLK_SRC_XTAL = SOC_MOD_CLK_XTAL, /*!< Select XTAL as the source clock */ + FLASH_CLK_SRC_RC_FAST = SOC_MOD_CLK_RC_FAST, /*!< Select RC_FAST as the source clock */ + FLASH_CLK_SRC_SPLL = SOC_MOD_CLK_SPLL, /*!< Select SPLL as the source clock */ + FLASH_CLK_SRC_ROM_DEFAULT = SOC_MOD_CLK_XTAL, /*!< Select XTAL as ROM default clock source */ +} soc_periph_flash_clk_src_t; //////////////////////////////////////////////CLOCK OUTPUT/////////////////////////////////////////////////////////// typedef enum { // TODO diff --git a/components/soc/esp32c5/include/soc/soc_caps.h b/components/soc/esp32c5/include/soc/soc_caps.h index d1323aff172..b0f70abec79 100644 --- a/components/soc/esp32c5/include/soc/soc_caps.h +++ b/components/soc/esp32c5/include/soc/soc_caps.h @@ -461,7 +461,6 @@ #define SOC_MEMSPI_SRC_FREQ_80M_SUPPORTED 1 #define SOC_MEMSPI_SRC_FREQ_40M_SUPPORTED 1 #define SOC_MEMSPI_SRC_FREQ_20M_SUPPORTED 1 -#define SOC_MEMSPI_FLASH_CLK_SRC_IS_INDEPENDENT 1 /*-------------------------- SYSTIMER CAPS ----------------------------------*/ // TODO: [ESP32C5] IDF-8707 diff --git a/components/soc/esp32c61/include/soc/Kconfig.soc_caps.in b/components/soc/esp32c61/include/soc/Kconfig.soc_caps.in index be07f2aa398..8acc53c2a5b 100644 --- a/components/soc/esp32c61/include/soc/Kconfig.soc_caps.in +++ b/components/soc/esp32c61/include/soc/Kconfig.soc_caps.in @@ -815,10 +815,6 @@ config SOC_MEMSPI_SRC_FREQ_20M_SUPPORTED bool default y -config SOC_MEMSPI_FLASH_CLK_SRC_IS_INDEPENDENT - bool - default y - config SOC_SYSTIMER_COUNTER_NUM int default 2 diff --git a/components/soc/esp32c61/include/soc/clk_tree_defs.h b/components/soc/esp32c61/include/soc/clk_tree_defs.h index 6d7ab501f43..787bdd2914d 100644 --- a/components/soc/esp32c61/include/soc/clk_tree_defs.h +++ b/components/soc/esp32c61/include/soc/clk_tree_defs.h @@ -348,21 +348,21 @@ typedef enum { LEDC_USE_RTC8M_CLK __attribute__((deprecated("please use 'LEDC_USE_RC_FAST_CLK' instead"))) = LEDC_USE_RC_FAST_CLK, /*!< Alias of 'LEDC_USE_RC_FAST_CLK' */ } soc_periph_ledc_clk_src_legacy_t; -//////////////////////////////////////////////////MSPI/////////////////////////////////////////////////////////////////// +//////////////////////////////////////////////////FLASH/////////////////////////////////////////////////////////////////// /** - * @brief Array initializer for all supported clock sources of MSPI digital controller + * @brief Array initializer for all supported clock sources of FLASH MSPI controller */ -#define SOC_MSPI_CLKS {SOC_MOD_CLK_XTAL, SOC_MOD_CLK_RC_FAST, SOC_MOD_CLK_SPLL} +#define SOC_FLASH_CLKS {SOC_MOD_CLK_XTAL, SOC_MOD_CLK_RC_FAST, SOC_MOD_CLK_SPLL} /** - * @brief MSPI digital controller clock source + * @brief FLASH MSPI controller clock source */ typedef enum { - MSPI_CLK_SRC_XTAL = SOC_MOD_CLK_XTAL, /*!< Select XTAL as the source clock */ - MSPI_CLK_SRC_RC_FAST = SOC_MOD_CLK_RC_FAST, /*!< Select RC_FAST as the source clock */ - MSPI_CLK_SRC_SPLL = SOC_MOD_CLK_SPLL, /*!< Select SPLL as the source clock */ - MSPI_CLK_SRC_DEFAULT = SOC_MOD_CLK_SPLL, /*!< Select PLL_F64M as the default clock choice */ - MSPI_CLK_SRC_ROM_DEFAULT = SOC_MOD_CLK_XTAL, /*!< Select XTAL as ROM default clock source */ -} soc_periph_mspi_clk_src_t; + FLASH_CLK_SRC_XTAL = SOC_MOD_CLK_XTAL, /*!< Select XTAL as the source clock */ + FLASH_CLK_SRC_RC_FAST = SOC_MOD_CLK_RC_FAST, /*!< Select RC_FAST as the source clock */ + FLASH_CLK_SRC_SPLL = SOC_MOD_CLK_SPLL, /*!< Select SPLL as the source clock */ + FLASH_CLK_SRC_DEFAULT = SOC_MOD_CLK_SPLL, /*!< Select PLL_F64M as the default clock choice */ + FLASH_CLK_SRC_ROM_DEFAULT = SOC_MOD_CLK_XTAL, /*!< Select XTAL as ROM default clock source */ +} soc_periph_flash_clk_src_t; //////////////////////////////////////////////CLOCK OUTPUT/////////////////////////////////////////////////////////// typedef enum { diff --git a/components/soc/esp32c61/include/soc/soc_caps.h b/components/soc/esp32c61/include/soc/soc_caps.h index 9fc484e819f..6ba4252340d 100644 --- a/components/soc/esp32c61/include/soc/soc_caps.h +++ b/components/soc/esp32c61/include/soc/soc_caps.h @@ -345,7 +345,6 @@ #define SOC_MEMSPI_SRC_FREQ_80M_SUPPORTED 1 #define SOC_MEMSPI_SRC_FREQ_40M_SUPPORTED 1 #define SOC_MEMSPI_SRC_FREQ_20M_SUPPORTED 1 -#define SOC_MEMSPI_FLASH_CLK_SRC_IS_INDEPENDENT 1 /*-------------------------- SYSTIMER CAPS ----------------------------------*/ #define SOC_SYSTIMER_COUNTER_NUM 2 // Number of counter units diff --git a/components/soc/esp32h2/include/soc/Kconfig.soc_caps.in b/components/soc/esp32h2/include/soc/Kconfig.soc_caps.in index 23ab08014f9..7bcb8ff90c9 100644 --- a/components/soc/esp32h2/include/soc/Kconfig.soc_caps.in +++ b/components/soc/esp32h2/include/soc/Kconfig.soc_caps.in @@ -1107,10 +1107,6 @@ config SOC_MEMSPI_SRC_FREQ_16M_SUPPORTED bool default y -config SOC_MEMSPI_FLASH_CLK_SRC_IS_INDEPENDENT - bool - default y - config SOC_SYSTIMER_COUNTER_NUM int default 2 diff --git a/components/soc/esp32h2/include/soc/clk_tree_defs.h b/components/soc/esp32h2/include/soc/clk_tree_defs.h index aba0a914c97..acf45c685dc 100644 --- a/components/soc/esp32h2/include/soc/clk_tree_defs.h +++ b/components/soc/esp32h2/include/soc/clk_tree_defs.h @@ -482,22 +482,22 @@ typedef enum { PARLIO_CLK_SRC_DEFAULT = SOC_MOD_CLK_PLL_F96M, /*!< Select PLL_F96M as the default clock choice */ } soc_periph_parlio_clk_src_t; -//////////////////////////////////////////////////MSPI/////////////////////////////////////////////////////////////////// +//////////////////////////////////////////////////FLASH/////////////////////////////////////////////////////////////////// /** - * @brief Array initializer for all supported clock sources of MSPI digital controller + * @brief Array initializer for all supported clock sources of FLASH MSPI controller */ -#define SOC_MSPI_CLKS {SOC_MOD_CLK_XTAL, SOC_MOD_CLK_RC_FAST, SOC_MOD_CLK_PLL_F64M, SOC_MOD_CLK_PLL_F48M} +#define SOC_FLASH_CLKS {SOC_MOD_CLK_XTAL, SOC_MOD_CLK_RC_FAST, SOC_MOD_CLK_PLL_F64M, SOC_MOD_CLK_PLL_F48M} /** - * @brief MSPI digital controller clock source + * @brief FLASH MSPI controller clock source */ typedef enum { - MSPI_CLK_SRC_XTAL = SOC_MOD_CLK_XTAL, /*!< Select XTAL as the source clock */ - MSPI_CLK_SRC_RC_FAST = SOC_MOD_CLK_RC_FAST, /*!< Select RC_FAST as the source clock */ - MSPI_CLK_SRC_PLL_F64M = SOC_MOD_CLK_PLL_F64M, /*!< Select PLL_F64M as the source clock */ - MSPI_CLK_SRC_PLL_F48M = SOC_MOD_CLK_PLL_F48M, /*!< Select PLL_F48M as the source clock */ - MSPI_CLK_SRC_DEFAULT = SOC_MOD_CLK_PLL_F64M, /*!< Select PLL_F64M as the default clock choice */ - MSPI_CLK_SRC_ROM_DEFAULT = SOC_MOD_CLK_XTAL, /*!< Select XTAL as ROM default clock source */ -} soc_periph_mspi_clk_src_t; + FLASH_CLK_SRC_XTAL = SOC_MOD_CLK_XTAL, /*!< Select XTAL as the source clock */ + FLASH_CLK_SRC_RC_FAST = SOC_MOD_CLK_RC_FAST, /*!< Select RC_FAST as the source clock */ + FLASH_CLK_SRC_PLL_F64M = SOC_MOD_CLK_PLL_F64M, /*!< Select PLL_F64M as the source clock */ + FLASH_CLK_SRC_PLL_F48M = SOC_MOD_CLK_PLL_F48M, /*!< Select PLL_F48M as the source clock */ + FLASH_CLK_SRC_DEFAULT = SOC_MOD_CLK_PLL_F64M, /*!< Select PLL_F64M as the default clock choice */ + FLASH_CLK_SRC_ROM_DEFAULT = SOC_MOD_CLK_XTAL, /*!< Select XTAL as ROM default clock source */ +} soc_periph_flash_clk_src_t; //////////////////////////////////////////////CLOCK OUTPUT/////////////////////////////////////////////////////////// typedef enum { diff --git a/components/soc/esp32h2/include/soc/soc_caps.h b/components/soc/esp32h2/include/soc/soc_caps.h index c4de9c97a7d..ff5cd542763 100644 --- a/components/soc/esp32h2/include/soc/soc_caps.h +++ b/components/soc/esp32h2/include/soc/soc_caps.h @@ -431,7 +431,6 @@ #define SOC_MEMSPI_SRC_FREQ_64M_SUPPORTED 1 #define SOC_MEMSPI_SRC_FREQ_32M_SUPPORTED 1 #define SOC_MEMSPI_SRC_FREQ_16M_SUPPORTED 1 -#define SOC_MEMSPI_FLASH_CLK_SRC_IS_INDEPENDENT 1 /*-------------------------- SYSTIMER CAPS ----------------------------------*/ #define SOC_SYSTIMER_COUNTER_NUM 2 // Number of counter units From bf86ab392632b54b35fc9d8111f7b13aabdc7e16 Mon Sep 17 00:00:00 2001 From: Tomas Rezucha Date: Tue, 10 Dec 2024 11:32:24 +0100 Subject: [PATCH 039/118] feat(dfu): Enable DFU on ESP32-P4 --- docs/conf_common.py | 3 +- docs/docs_not_updated/esp32p4.txt | 1 - docs/en/api-guides/dfu.rst | 54 +++++++++++++++++++------------ docs/en/api-guides/index.rst | 2 +- docs/zh_CN/api-guides/index.rst | 2 +- tools/idf_py_actions/dfu_ext.py | 9 ++++-- 6 files changed, 42 insertions(+), 29 deletions(-) diff --git a/docs/conf_common.py b/docs/conf_common.py index 9bcfa2ac16f..151ba312d73 100644 --- a/docs/conf_common.py +++ b/docs/conf_common.py @@ -137,7 +137,6 @@ DSI_LCD_DOCS = ['api-reference/peripherals/lcd/dsi_lcd.rst'] PARLIO_LCD_DOCS = ['api-reference/peripherals/lcd/parl_lcd.rst'] -# TODO: Merge this back with `USB_DOCS` IDF-9919 IDF-9920 IDF-9133 USB_OTG_DFU_DOCS = ['api-guides/dfu.rst'] USB_OTG_CONSOLE_DOCS = ['api-guides/usb-otg-console.rst'] @@ -247,7 +246,7 @@ ESP32P4_DOCS = ['api-reference/system/ipc.rst', 'api-reference/peripherals/cap_touch_sens.rst', - 'api-reference/peripherals/sd_pullup_requirements.rst'] + 'api-reference/peripherals/sd_pullup_requirements.rst'] + USB_OTG_DFU_DOCS # format: {tag needed to include: documents to included}, tags are parsed from sdkconfig and peripheral_caps.h headers conditional_include_dict = {'SOC_BT_SUPPORTED':BT_DOCS, diff --git a/docs/docs_not_updated/esp32p4.txt b/docs/docs_not_updated/esp32p4.txt index dc5c69dde7a..f4553fef4d5 100644 --- a/docs/docs_not_updated/esp32p4.txt +++ b/docs/docs_not_updated/esp32p4.txt @@ -1,6 +1,5 @@ api-guides/partition-tables.rst api-guides/usb-otg-console.rst -api-guides/dfu.rst api-reference/peripherals/adc_calibration.rst api-reference/peripherals/parlio.rst api-reference/peripherals/sd_pullup_requirements.rst diff --git a/docs/en/api-guides/dfu.rst b/docs/en/api-guides/dfu.rst index 2ad2befb48f..e9322781c04 100644 --- a/docs/en/api-guides/dfu.rst +++ b/docs/en/api-guides/dfu.rst @@ -3,7 +3,19 @@ Device Firmware Upgrade via USB :link_to_translation:`zh_CN:[中文]` -Typically, the firmware of the {IDF_TARGET_NAME} is flashed via the chip's serial port. However, flashing via the serial port requires a USB to serial converter chip (e.g., CP210x or FTDI) to be connected to the {IDF_TARGET_NAME} (see :doc:`Establish Serial Connection with {IDF_TARGET_NAME} <../get-started/establish-serial-connection>` for more details). The {IDF_TARGET_NAME} contains a USB OTG peripheral making it possible to connect the {IDF_TARGET_NAME} to the host directly via USB (thus not requiring a USB to serial converter chip). +.. only:: not SOC_USB_SERIAL_JTAG_SUPPORTED + + Typically, the firmware of the {IDF_TARGET_NAME} is flashed via the chip's serial port. However, flashing via the serial port requires a USB to serial converter chip (e.g., CP210x or FTDI) to be connected to the {IDF_TARGET_NAME} (see :doc:`Establish Serial Connection with {IDF_TARGET_NAME} <../get-started/establish-serial-connection>` for more details). The {IDF_TARGET_NAME} contains a USB OTG peripheral making it possible to connect the {IDF_TARGET_NAME} to the host directly via USB (thus not requiring a USB to serial converter chip). + +.. only:: SOC_USB_SERIAL_JTAG_SUPPORTED + + Typically, the firmware of the {IDF_TARGET_NAME} is flashed via the chip's serial port or USB_SERIAL_JTAG (see :doc:`Establish Serial Connection with {IDF_TARGET_NAME} <../get-started/establish-serial-connection>` for more details). The {IDF_TARGET_NAME} also contains a USB OTG peripheral making it possible to connect the {IDF_TARGET_NAME} to the host directly via USB Device Firmware Upgrade. + +.. only:: esp32s3 + + By default, the :doc:`USB_SERIAL_JTAG ` module is connected to the {IDF_TARGET_NAME}'s internal USB PHY, while the USB OTG peripheral can be used only if an external USB PHY is connected. Since DFU is provided via the USB OTG peripheral, it cannot be used through the internal PHY in this configuration. + + However, users can permanently switch the internal USB PHY to work with USB OTG peripheral instead of USB_SERIAL_JTAG by burning the ``USB_PHY_SEL`` eFuse. See *{IDF_TARGET_NAME} Technical Reference Manual* [`PDF <{IDF_TARGET_TRM_EN_URL}>`__] for more details about USB_SERIAL_JTAG and USB OTG. Device Firmware Upgrade (DFU) is a mechanism for upgrading the firmware of the {IDF_TARGET_NAME} directly via the Universal Serial Bus (USB). However, enabling Secure Boot or flash encryption disables the USB-OTG USB stack in the ROM, disallowing updates via the serial emulation or DFU on that port. @@ -15,40 +27,40 @@ Device Firmware Upgrade (DFU) is a mechanism for upgrading the firmware of the { USB Connection -------------- -The necessary connections for the {IDF_TARGET_NAME}'s internal USB PHY (transceiver) are shown in the following table: +.. only:: esp32p4 -.. list-table:: - :header-rows: 1 - :widths: 25 20 + The {IDF_TARGET_NAME} routes the USB D+ and D- signals to their dedicated pins. For USB device functionality, these pins must be connected to the USB bus (e.g., via a Micro-B port, USB-C port, or directly to standard-A plug). - * - GPIO - - USB +.. only:: esp32s2 or esp32s3 - * - 20 - - D+ (green) + The necessary connections for the {IDF_TARGET_NAME}'s internal USB PHY (transceiver) are shown in the following table: - * - 19 - - D- (white) + .. list-table:: + :header-rows: 1 + :widths: 25 20 - * - GND - - GND (black) + * - GPIO + - USB - * - +5V - - +5V (red) + * - 20 + - D+ (green) -.. warning:: + * - 19 + - D- (white) - Some cables are wired up with non-standard colors and some drivers are able to work with swapped D+ and D- connections. Please try to swap the cables connecting to D+ and D- if your device is not detected. + * - GND + - GND (black) -.. only:: esp32s3 + * - +5V + - +5V (red) - By default, the :doc:`USB_SERIAL_JTAG ` module is connected to the {IDF_TARGET_NAME}'s internal USB PHY, while the USB OTG peripheral can be used only if an external USB PHY is connected. Since DFU is provided via the USB OTG peripheral, it cannot be used through the internal PHY in this configuration. +.. warning:: - However, users can permanently switch the internal USB PHY to work with USB OTG peripheral instead of USB_SERIAL_JTAG by burning the ``USB_PHY_SEL`` eFuse. See *{IDF_TARGET_NAME} Technical Reference Manual* [`PDF <{IDF_TARGET_TRM_EN_URL}>`__] for more details about USB_SERIAL_JTAG and USB OTG. + Some cables are wired up with non-standard colors and some drivers are able to work with swapped D+ and D- connections. Please try to swap the cables connecting to D+ and D- if your device is not detected. .. note:: - The {IDF_TARGET_NAME} chip needs to be in bootloader mode before it can be detected as a DFU device and flash. This can be achieved by pulling GPIO0 down (e.g., pressing the BOOT button), pulling RESET down for a moment, and releasing GPIO0. + The {IDF_TARGET_NAME} chip needs to be in bootloader mode before it can be detected as a DFU device and flash. Please refer to `Boot Mode Selection `_ for more information about how to enter bootloader mode. .. _api_guide_dfu_build: diff --git a/docs/en/api-guides/index.rst b/docs/en/api-guides/index.rst index e9ad8c6941e..4ca6af42b76 100644 --- a/docs/en/api-guides/index.rst +++ b/docs/en/api-guides/index.rst @@ -19,7 +19,7 @@ API Guides core_dump current-consumption-measurement-modules :ESP_ROM_SUPPORT_DEEP_SLEEP_WAKEUP_STUB: deep-sleep-stub - :SOC_USB_OTG_SUPPORTED and not esp32p4: dfu + :SOC_USB_OTG_SUPPORTED: dfu error-handling :SOC_WIFI_MESH_SUPPORT: esp-wifi-mesh :SOC_SPIRAM_SUPPORTED: external-ram diff --git a/docs/zh_CN/api-guides/index.rst b/docs/zh_CN/api-guides/index.rst index c8eccdc5e25..1bd85bc267c 100644 --- a/docs/zh_CN/api-guides/index.rst +++ b/docs/zh_CN/api-guides/index.rst @@ -19,7 +19,7 @@ API 指南 core_dump current-consumption-measurement-modules :ESP_ROM_SUPPORT_DEEP_SLEEP_WAKEUP_STUB: deep-sleep-stub - :SOC_USB_OTG_SUPPORTED and not esp32p4: dfu + :SOC_USB_OTG_SUPPORTED: dfu error-handling :SOC_WIFI_MESH_SUPPORT: esp-wifi-mesh :SOC_SPIRAM_SUPPORTED: external-ram diff --git a/tools/idf_py_actions/dfu_ext.py b/tools/idf_py_actions/dfu_ext.py index 4f0b36105b0..4c72f6db829 100644 --- a/tools/idf_py_actions/dfu_ext.py +++ b/tools/idf_py_actions/dfu_ext.py @@ -1,15 +1,18 @@ -# SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD +# SPDX-FileCopyrightText: 2022-2024 Espressif Systems (Shanghai) CO LTD # SPDX-License-Identifier: Apache-2.0 from typing import Dict from click.core import Context from idf_py_actions.errors import FatalError -from idf_py_actions.tools import PropertyDict, ensure_build_directory, is_target_supported, run_target +from idf_py_actions.tools import ensure_build_directory +from idf_py_actions.tools import is_target_supported +from idf_py_actions.tools import PropertyDict +from idf_py_actions.tools import run_target def action_extensions(base_actions: Dict, project_path: str) -> Dict: - SUPPORTED_TARGETS = ['esp32s2', 'esp32s3'] + SUPPORTED_TARGETS = ['esp32s2', 'esp32s3', 'esp32p4'] def dfu_target(target_name: str, ctx: Context, args: PropertyDict, part_size: str) -> None: ensure_build_directory(args, ctx.info_name) From d518d110c0ea1cbf37e0367db84846efcdf6bea4 Mon Sep 17 00:00:00 2001 From: Zhang Shuxian Date: Wed, 4 Dec 2024 17:55:18 +0800 Subject: [PATCH 040/118] docs: Review the CN translation for Picolibc --- docs/en/COPYRIGHT.rst | 4 +++- docs/en/api-guides/performance/ram-usage.rst | 12 +++++----- docs/en/api-guides/performance/size.rst | 2 +- docs/zh_CN/COPYRIGHT.rst | 4 ++-- docs/zh_CN/api-guides/c.rst | 4 ++-- docs/zh_CN/api-guides/lwip.rst | 2 +- .../api-guides/performance/ram-usage.rst | 22 +++++++++---------- docs/zh_CN/api-guides/performance/size.rst | 8 +++---- .../api-reference/system/system_time.rst | 2 +- 9 files changed, 31 insertions(+), 29 deletions(-) diff --git a/docs/en/COPYRIGHT.rst b/docs/en/COPYRIGHT.rst index 1082cc860a5..bf9ad5fad3c 100644 --- a/docs/en/COPYRIGHT.rst +++ b/docs/en/COPYRIGHT.rst @@ -19,7 +19,9 @@ Firmware Components These third party libraries can be included into the application (firmware) produced by ESP-IDF. -* :component:`Newlib ` is licensed under the BSD License and is Copyright of various parties, as described in :component_file:`COPYING.NEWLIB `. If :ref:`CONFIG_LIBC_PICOLIBC` is enabled, see also :component_file:`COPYING.picolibc `. +* :component:`Newlib ` is licensed under the BSD License, with copyright held by the respective parties, as described in :component_file:`COPYING.NEWLIB `. If :ref:`CONFIG_LIBC_PICOLIBC` is enabled, see also :component_file:`COPYING.picolibc `. + +:component:`Picolibc ` is licensed under the BSD License, with copyright held by the respective parties, as described in :component_file:`COPYING.picolibc `. * :component:`Xtensa header files ` are Copyright (C) 2013 Tensilica Inc and are licensed under the MIT License as reproduced in the individual header files. diff --git a/docs/en/api-guides/performance/ram-usage.rst b/docs/en/api-guides/performance/ram-usage.rst index 98eddd5df1d..9cac6312744 100644 --- a/docs/en/api-guides/performance/ram-usage.rst +++ b/docs/en/api-guides/performance/ram-usage.rst @@ -57,10 +57,10 @@ Configuration Options for Stack Overflow Detection .. only:: SOC_ASSIST_DEBUG_SUPPORTED - Hardware Stack Guard - ~~~~~~~~~~~~~~~~~~~~ + Hardware Stack Guard + ~~~~~~~~~~~~~~~~~~~~ - The Hardware Stack Guard is a reliable method for detecting stack overflow. This method uses the hardware's Debug Assistant module to monitor the CPU's stack pointer register. A panic is immediately triggered if the stack pointer register goes beyond the bounds of the current stack (see :ref:`Hardware-Stack-Guard` for more details). The Hardware Stack Guard can be enabled via the :ref:`CONFIG_ESP_SYSTEM_HW_STACK_GUARD` option. + The Hardware Stack Guard is a reliable method for detecting stack overflow. This method uses the hardware's Debug Assistant module to monitor the CPU's stack pointer register. A panic is immediately triggered if the stack pointer register goes beyond the bounds of the current stack (see :ref:`Hardware-Stack-Guard` for more details). The Hardware Stack Guard can be enabled via the :ref:`CONFIG_ESP_SYSTEM_HW_STACK_GUARD` option. End of Stack Watchpoint ~~~~~~~~~~~~~~~~~~~~~~~ @@ -74,11 +74,11 @@ The Stack Canary Bytes feature adds a set of magic bytes at the end of each task .. note:: - When using the End of Stack Watchpoint or Stack Canary Bytes, it is possible that a stack pointer skips over the watchpoint or canary bytes on a stack overflow and corrupts another region of RAM instead. Thus, these methods cannot detect all stack overflows. + When using the End of Stack Watchpoint or Stack Canary Bytes, it is possible that a stack pointer skips over the watchpoint or canary bytes on a stack overflow and corrupts another region of RAM instead. Thus, these methods cannot detect all stack overflows. - .. only:: SOC_ASSIST_DEBUG_SUPPORTED + .. only:: SOC_ASSIST_DEBUG_SUPPORTED - Recommended and default option is :ref:`CONFIG_ESP_SYSTEM_HW_STACK_GUARD` which avoids this disadvantage. + Recommended and default option is :ref:`CONFIG_ESP_SYSTEM_HW_STACK_GUARD` which avoids this disadvantage. Run-time Methods to Determine Stack Size ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ diff --git a/docs/en/api-guides/performance/size.rst b/docs/en/api-guides/performance/size.rst index 9cbaa162439..d48b699d263 100644 --- a/docs/en/api-guides/performance/size.rst +++ b/docs/en/api-guides/performance/size.rst @@ -158,7 +158,7 @@ Picolibc instead of Newlib By default, ESP-IDF uses the Newlib C library, and it also has experimental support for the Picolibc C library. -Picolibc C library provides smaller ``printf``-family functions and can reduce the binary size by up to 30 KB, depending on your application. +Picolibc C library provides smaller ``printf`` family functions and can reduce the binary size by up to 30 KB, depending on your application. To switch to linking against the Picolibc C library, please enable the configuration options :ref:`CONFIG_IDF_EXPERIMENTAL_FEATURES` and :ref:`CONFIG_LIBC_PICOLIBC`. diff --git a/docs/zh_CN/COPYRIGHT.rst b/docs/zh_CN/COPYRIGHT.rst index cbd82840d07..c614804a536 100644 --- a/docs/zh_CN/COPYRIGHT.rst +++ b/docs/zh_CN/COPYRIGHT.rst @@ -19,9 +19,9 @@ 以下这些第三方库包含在 ESP-IDF 生成的应用程序（固件）中。 -* :component:`Newlib ` 经 BSD 许可证许可，版权归各方所有，如 :component_file:`COPYING.NEWLIB ` 中所述。如果启用了 :ref:`CONFIG_LIBC_PICOLIBC`，另请参阅 :component_file:`COPYING.picolibc `。 +* 如 :component_file:`COPYING.NEWLIB ` 中所述， :component:`Newlib ` 经 BSD 许可证许可，版权归各方所有。如启用了 :ref:`CONFIG_LIBC_PICOLIBC`，请参阅 :component_file:`COPYING.picolibc `。 -* :component:`Picolibc ` 经 BSD 许可证许可，版权归各方所有，如 :component_file:`COPYING.picolibc ` 中所述。 +* 如 :component_file:`COPYING.picolibc ` 中所述， :component:`Picolibc ` 经 BSD 许可证许可，版权归各方所有。 * :component:`Xtensa 头文件 ` 版权归 2013 Tensilica 公司所有，并根据各头文件中复制的 MIT 许可证进行许可。 diff --git a/docs/zh_CN/api-guides/c.rst b/docs/zh_CN/api-guides/c.rst index 76ee9f24668..ed7a304db94 100644 --- a/docs/zh_CN/api-guides/c.rst +++ b/docs/zh_CN/api-guides/c.rst @@ -3,14 +3,14 @@ C 支持 :link_to_translation:`en:[English]` -ESP-IDF 主要使用 C 语言编写，并提供 C API。ESP-IDF 可以使用以下 C 标准库实现之一： +ESP-IDF 主要使用 C 语言编写，并提供 C API。ESP-IDF 可以使用以下 C 标准函数库的实现之一： - `Newlib `_ (默认) - `Picolibc `_ (通过 :ref:`CONFIG_LIBC_PICOLIBC` Kconfig 选项启用) Newlib 的版本号记录在 :component_file:`newlib/sbom.yml` 文件中。 -一般来说，除非在下面的 :ref:`unsupported_c_features` 中特别说明，当前使用的编译器（目前是 GCC）支持的所有 C 语言功能在 ESP-IDF 中均可使用。 +一般来说，除非在 :ref:`unsupported_c_features` 特别说明，当前编译器（目前是 GCC）支持的所有 C 语言功能在 ESP-IDF 中均可使用。 .. _c_version: diff --git a/docs/zh_CN/api-guides/lwip.rst b/docs/zh_CN/api-guides/lwip.rst index dc88ee7c131..d47f3ad4845 100644 --- a/docs/zh_CN/api-guides/lwip.rst +++ b/docs/zh_CN/api-guides/lwip.rst @@ -173,7 +173,7 @@ BSD 套接字的相关参考资料十分丰富，包括但不限于： 套接字错误原因代码 ++++++++++++++++++++++++ -以下是常见错误代码列表。有关标准 POSIX/C 错误代码的详细列表，请参阅 `newlib errno.h `_ 和特定平台扩展 :component_file:`newlib/platform_include/sys/errno.h`。 +以下是常见错误代码列表。获取标准 POSIX/C 错误代码的详细列表，请参阅 `newlib errno.h `_ 和特定平台扩展 :component_file:`newlib/platform_include/sys/errno.h`。 .. list-table:: :header-rows: 1 diff --git a/docs/zh_CN/api-guides/performance/ram-usage.rst b/docs/zh_CN/api-guides/performance/ram-usage.rst index dff7f3285d1..f0c72ce2278 100644 --- a/docs/zh_CN/api-guides/performance/ram-usage.rst +++ b/docs/zh_CN/api-guides/performance/ram-usage.rst @@ -7,7 +7,7 @@ 固件应用程序的可用 RAM 在某些情况下可能处于低水平，甚至完全耗尽。为此，应调整这些情况下固件应用程序的内存使用情况。 -固件应用程序通常需要为内部 RAM 保留备用空间，用于应对非常规情况，或在后续版本的更新中，适应 RAM 使用需求的变化。 +固件通常需要为内部 RAM 保留备用空间，用于应对非常规情况，或在后续版本的更新中，适应 RAM 使用需求的变化。 背景 ---------- @@ -57,28 +57,28 @@ ESP-IDF 包含一系列堆 API，可以在运行时测量空闲堆内存，请 .. only:: SOC_ASSIST_DEBUG_SUPPORTED - 硬件栈保护 - ~~~~~~~~~~~~ + 硬件栈保护 + ~~~~~~~~~~~~ - 硬件栈保护是一种检测栈溢出的可靠方法，通过硬件的辅助调试模块来监视 CPU 的栈指针寄存器。如果栈指针寄存器超出了当前栈的边界，则立即触发紧急情况提示（更多详细信息，请参阅 :ref:`Hardware-Stack-Guard`）。可以通过 :ref:`CONFIG_ESP_SYSTEM_HW_STACK_GUARD` 选项启用硬件栈保护。 + 硬件栈保护是一种检测栈溢出的可靠方法，通过硬件的辅助调试模块来监视 CPU 的栈指针寄存器。如果栈指针寄存器超出了当前栈的边界，则立即触发紧急情况提示（更多详细信息，请参阅 :ref:`Hardware-Stack-Guard`）。可以通过 :ref:`CONFIG_ESP_SYSTEM_HW_STACK_GUARD` 选项启用硬件栈保护。 栈末尾监视点 ~~~~~~~~~~~~~~ 栈末尾监视点将 CPU 监视点放置在当前栈的末尾。如果该字被覆盖（例如栈溢出），则会立即触发紧急情况提示。在未使用调试器的监视点时，可以设置 :ref:`CONFIG_FREERTOS_WATCHPOINT_END_OF_STACK` 选项，启用栈末尾监视点功能。 -栈金丝雀字节 -~~~~~~~~~~~~~~ +栈 canary 字节 +~~~~~~~~~~~~~~~~~ -栈金丝雀字节功能在每个任务的栈末尾添加一组魔术字节，并在每次上下文切换时检查这些字节是否已更改。如果这些魔术字节被覆盖，则会触发紧急情况提示。可以通过 :ref:`CONFIG_FREERTOS_CHECK_STACKOVERFLOW` 选项启用栈金丝雀字节功能。 +栈 canary 字节功能在每个任务的栈末尾添加一组魔术字节，并在每次上下文切换时检查这些字节是否已更改。如果这些魔术字节被覆盖，则会触发紧急情况提示。可以通过 :ref:`CONFIG_FREERTOS_CHECK_STACKOVERFLOW` 选项启用栈 canary 字节功能。 .. note:: - 使用栈末尾监视点或栈金丝雀字节时，栈指针可能在栈溢出时跳过监视点或金丝雀字节，损坏 RAM 的其他区域。因此，上述方法并不能检测所有的栈溢出。 + 使用栈末尾监视点或栈 canary 字节时，栈指针可能在栈溢出时跳过监视点或 canary 字节，损坏 RAM 的其他区域。因此，上述方法并不能检测所有的栈溢出。 - .. only:: SOC_ASSIST_DEBUG_SUPPORTED + .. only:: SOC_ASSIST_DEBUG_SUPPORTED - 推荐启用默认选项 :ref:`CONFIG_ESP_SYSTEM_HW_STACK_GUARD`，避免这个缺点。 + 推荐启用默认选项 :ref:`CONFIG_ESP_SYSTEM_HW_STACK_GUARD`，避免这个缺点。 任务运行时确定栈内存大小的方法 ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ @@ -96,7 +96,7 @@ ESP-IDF 包含一系列堆 API，可以在运行时测量空闲堆内存，请 - 避免占用过多栈内存的函数。字符串格式化函数（如 ``printf()``）会使用大量栈内存，如果任务不调用这类函数，通常可以减小其占用的栈内存。 - - :ref:`picolibc-instead-of-newlib` 可以显著减少 ``printf()`` 调用的堆栈使用量。 + - 使用实验性的选项 :ref:`picolibc-instead-of-newlib` 可以显著减少 ``printf()`` 调用的堆栈使用量。 - 启用 :ref:`newlib-nano-formatting`，可以在任务调用 ``printf()`` 或其他 C 语言字符串格式化函数时，减少这类任务的栈内存使用量。 - 避免在栈上分配大型变量。在 C 语言声明的默认作用域中，任何分配为自动变量的大型结构体或数组都会占用栈内存。要优化这些变量占用的栈内存大小，可以使用静态分配，或仅在需要时从堆中动态分配。 diff --git a/docs/zh_CN/api-guides/performance/size.rst b/docs/zh_CN/api-guides/performance/size.rst index de8cd04b85c..a609b638bcd 100644 --- a/docs/zh_CN/api-guides/performance/size.rst +++ b/docs/zh_CN/api-guides/performance/size.rst @@ -158,9 +158,9 @@ lwIP IPv4 默认情况下，ESP-IDF 使用 Newlib C 库，同时也对 Picolibc C 库提供实验性支持。 -Picolibc C 库提供了更小的 ``printf`` 系列函数，并且根据您的应用程序，可以将二进制文件大小最多减少 30 KB。 +Picolibc C 库提供了更精简的 ``printf`` 系列函数，并且根据应用程序，可以将二进制文件大小减少最多 30 KB。 -要切换为链接到 Picolibc C 库，请启用以下配置选项：:ref:CONFIG_IDF_EXPERIMENTAL_FEATURES 和 :ref:`CONFIG_LIBC_PICOLIBC`。 +如需切换链接到 Picolibc C 库，请启用配置选项 :ref:`CONFIG_IDF_EXPERIMENTAL_FEATURES` 和 :ref:`CONFIG_LIBC_PICOLIBC`。 .. _newlib-nano-formatting: @@ -171,13 +171,13 @@ ESP-IDF 的 I/O 函数（ ``printf()`` 和 ``scanf()`` 等）默认使用 Newlib .. only:: CONFIG_ESP_ROM_HAS_NEWLIB_NANO_FORMAT - 启用配置选项 :ref:`CONFIG_LIBC_NEWLIB_NANO_FORMAT` 将使 Newlib 切换到 Nano 格式化模式。这种模式的代码量更小，并且大部分内容被编译到了 {IDF_TARGET_NAME} 的 ROM 中，因此不需要将其添加至二进制文件中。 + 启用配置选项 :ref:`CONFIG_LIBC_NEWLIB_NANO_FORMAT` 将 Newlib 切换到 Nano 格式化模式。从而减小了代码体积，同时大部分内容被编译到 {IDF_TARGET_NAME} 的 ROM 中，因此不需要将其添加至二进制文件中。 具体的二进制文件大小差异取决于固件使用的功能，但通常为 25 KB 到 50 KB。 .. only:: CONFIG_ESP_ROM_HAS_NEWLIB_NORMAL_FORMAT - 禁用配置选项 :ref:`CONFIG_LIBC_NEWLIB_NANO_FORMAT` 将切换 Newlib 到“完整”格式化模式。这将减小二进制文件的大小，因为 {IDF_TARGET_NAME} 的 ROM 中已存有完整格式化版本的函数，因此不需要将其添加至二进制文件中。 + 禁用配置选项 :ref:`CONFIG_LIBC_NEWLIB_NANO_FORMAT` 将 Newlib 切换到完整格式化模式。从而减小二进制文件的大小，因为 {IDF_TARGET_NAME} 的 ROM 中已存有完整格式化版本的函数，因此无需将其添加至二进制文件中。 启用 Nano 格式化会减少调用 ``printf()`` 或其他字符串格式化函数的堆栈使用量，参阅 :ref:`optimize-stack-sizes`。 diff --git a/docs/zh_CN/api-reference/system/system_time.rst b/docs/zh_CN/api-reference/system/system_time.rst index 9abf7a8040d..f70989db5ab 100644 --- a/docs/zh_CN/api-reference/system/system_time.rst +++ b/docs/zh_CN/api-reference/system/system_time.rst @@ -26,7 +26,7 @@ - 高分辨率定时器 - 无 -默认时钟源的时间精度最高，建议使用该配置。此外，用户也可以通过配置选项 :ref:`CONFIG_LIBC_TIME_SYSCALL` 来选择其他时钟源。 +默认时钟源的时间精度最高，建议使用该配置。此外，你可以通过配置选项 :ref:`CONFIG_LIBC_TIME_SYSCALL` 来选择其他时钟源。 .. _rtc-clock-source-choice: From dd07504ea5bd451db612c802afdc8b3104a4faf5 Mon Sep 17 00:00:00 2001 From: Chen Jichang Date: Mon, 9 Dec 2024 19:05:04 +0800 Subject: [PATCH 041/118] feat(pcnt): support step_notify on esp32h2 eco5 --- components/esp_driver_pcnt/src/pulse_cnt.c | 7 +- .../test_apps/pulse_cnt/main/test_pulse_cnt.c | 280 +++++++++--------- components/hal/esp32c5/include/hal/pcnt_ll.h | 10 + components/hal/esp32h2/include/hal/pcnt_ll.h | 61 +++- .../esp32h2/include/soc/Kconfig.soc_caps.in | 4 + components/soc/esp32h2/include/soc/soc_caps.h | 1 + .../soc/esp32h2/register/soc/pcnt_struct.h | 53 +++- 7 files changed, 270 insertions(+), 146 deletions(-) diff --git a/components/esp_driver_pcnt/src/pulse_cnt.c b/components/esp_driver_pcnt/src/pulse_cnt.c index e2accb936fc..2dc6e5e2eb9 100644 --- a/components/esp_driver_pcnt/src/pulse_cnt.c +++ b/components/esp_driver_pcnt/src/pulse_cnt.c @@ -667,8 +667,10 @@ esp_err_t pcnt_unit_remove_watch_point(pcnt_unit_handle_t unit, int watch_point) #if SOC_PCNT_SUPPORT_STEP_NOTIFY esp_err_t pcnt_unit_add_watch_step(pcnt_unit_handle_t unit, int step_interval) { - pcnt_group_t *group = NULL; - + pcnt_group_t *group = unit->group; + if (!pcnt_ll_is_step_notify_supported(group->group_id)) { + ESP_RETURN_ON_FALSE(false, ESP_ERR_NOT_SUPPORTED, TAG, "watch step is not supported by this chip revision"); + } ESP_RETURN_ON_FALSE(unit, ESP_ERR_INVALID_ARG, TAG, "invalid argument"); ESP_RETURN_ON_FALSE((step_interval > 0 && unit->flags.en_step_notify_up) || (step_interval < 0 && unit->flags.en_step_notify_down), ESP_ERR_INVALID_ARG, TAG, "invalid step interval"); @@ -677,7 +679,6 @@ esp_err_t pcnt_unit_add_watch_step(pcnt_unit_handle_t unit, int step_interval) ESP_RETURN_ON_FALSE(unit->step_interval == 0, ESP_ERR_INVALID_STATE, TAG, "watch step has been set to %d already", unit->step_interval); - group = unit->group; unit->step_interval = step_interval; pcnt_ll_set_step_value(group->hal.dev, unit->unit_id, step_interval); // different units are mixing in the same register, so we use the group's spinlock here diff --git a/components/esp_driver_pcnt/test_apps/pulse_cnt/main/test_pulse_cnt.c b/components/esp_driver_pcnt/test_apps/pulse_cnt/main/test_pulse_cnt.c index 61952df1a27..51c09a11223 100644 --- a/components/esp_driver_pcnt/test_apps/pulse_cnt/main/test_pulse_cnt.c +++ b/components/esp_driver_pcnt/test_apps/pulse_cnt/main/test_pulse_cnt.c @@ -14,6 +14,7 @@ #include "soc/soc_caps.h" #include "esp_attr.h" #include "test_pulse_cnt_board.h" +#include "hal/pcnt_ll.h" TEST_CASE("pcnt_unit_install_uninstall", "[pcnt]") { @@ -677,145 +678,148 @@ TEST_CASE("pcnt overflow accumulation", "[pcnt]") #if SOC_PCNT_SUPPORT_STEP_NOTIFY TEST_CASE("pcnt_step_notify_event", "[pcnt]") { - test_gpio_init_for_simulation(TEST_PCNT_GPIO_A); - test_gpio_init_for_simulation(TEST_PCNT_GPIO_B); - - pcnt_unit_config_t unit_config = { - .low_limit = -100, - .high_limit = 100, - .flags = { - .en_step_notify_down = true, - }, - }; - - printf("install pcnt unit\r\n"); - pcnt_unit_handle_t unit = NULL; - TEST_ESP_OK(pcnt_new_unit(&unit_config, &unit)); - pcnt_glitch_filter_config_t filter_config = { - .max_glitch_ns = 1000, - }; - TEST_ESP_OK(pcnt_unit_set_glitch_filter(unit, &filter_config)); - - printf("install two pcnt channels with different edge/level action\r\n"); - pcnt_chan_config_t channel_config = { - .edge_gpio_num = TEST_PCNT_GPIO_A, - .level_gpio_num = TEST_PCNT_GPIO_B, - }; - pcnt_channel_handle_t channelA = NULL; - TEST_ESP_OK(pcnt_new_channel(unit, &channel_config, &channelA)); - TEST_ESP_OK(pcnt_channel_set_edge_action(channelA, PCNT_CHANNEL_EDGE_ACTION_DECREASE, PCNT_CHANNEL_EDGE_ACTION_INCREASE)); - TEST_ESP_OK(pcnt_channel_set_level_action(channelA, PCNT_CHANNEL_LEVEL_ACTION_KEEP, PCNT_CHANNEL_LEVEL_ACTION_INVERSE)); - // switch edge gpio and level gpio, the assign to another channel in the same unit - pcnt_channel_handle_t channelB = NULL; - channel_config.edge_gpio_num = TEST_PCNT_GPIO_B; - channel_config.level_gpio_num = TEST_PCNT_GPIO_A; - TEST_ESP_OK(pcnt_new_channel(unit, &channel_config, &channelB)); - TEST_ESP_OK(pcnt_channel_set_edge_action(channelB, PCNT_CHANNEL_EDGE_ACTION_INCREASE, PCNT_CHANNEL_EDGE_ACTION_DECREASE)); - TEST_ESP_OK(pcnt_channel_set_level_action(channelB, PCNT_CHANNEL_LEVEL_ACTION_KEEP, PCNT_CHANNEL_LEVEL_ACTION_INVERSE)); - - // ensure the simulation signal in a stable state - TEST_ESP_OK(gpio_set_level(TEST_PCNT_GPIO_A, 1)); - TEST_ESP_OK(gpio_set_level(TEST_PCNT_GPIO_B, 1)); - - pcnt_event_callbacks_t cbs = { - .on_reach = test_pcnt_quadrature_reach_watch_point, - }; - test_pcnt_quadrature_context_t user_data = { - .index = 0, - .triggered_watch_values = {0}, - }; - TEST_ESP_OK(pcnt_unit_register_event_callbacks(unit, &cbs, &user_data)); - - printf("add watch step and point\r\n"); - TEST_ASSERT_EQUAL(ESP_ERR_INVALID_ARG, pcnt_unit_add_watch_step(unit, 0)); - TEST_ASSERT_EQUAL(ESP_ERR_INVALID_ARG, pcnt_unit_add_watch_step(unit, 20)); - TEST_ASSERT_EQUAL(ESP_ERR_INVALID_ARG, pcnt_unit_add_watch_step(unit, -120)); - TEST_ESP_OK(pcnt_unit_add_watch_step(unit, -25)); - TEST_ASSERT_EQUAL(ESP_ERR_INVALID_STATE, pcnt_unit_add_watch_step(unit, -100)); - TEST_ESP_OK(pcnt_unit_add_watch_point(unit, -100)); - TEST_ESP_OK(pcnt_unit_add_watch_point(unit, 0)); - TEST_ESP_OK(pcnt_unit_add_watch_point(unit, -50)); - TEST_ESP_OK(pcnt_unit_add_watch_point(unit, 11)); - - TEST_ESP_OK(pcnt_unit_enable(unit)); - TEST_ESP_OK(pcnt_unit_start(unit)); - - printf("simulating quadrature signals and count down\r\n"); - test_gpio_simulate_quadrature_signals(TEST_PCNT_GPIO_A, TEST_PCNT_GPIO_B, 25); // 25*(-4) = -100 -> 0 - - int count_value; - TEST_ESP_OK(pcnt_unit_get_count(unit, &count_value)); - printf("counter stopped at %d\r\n", count_value); - - for (int i = 0 ; i < user_data.index; i++) { - printf("%d:%d\r\n", i, user_data.triggered_watch_values[i]); - } - TEST_ASSERT_EQUAL(0, count_value); - TEST_ASSERT_EQUAL(5, user_data.index); - TEST_ASSERT_EQUAL(-25, user_data.triggered_watch_values[0]); // step point (-25*1) - TEST_ASSERT_EQUAL(-50, user_data.triggered_watch_values[1]); // step point && watch point - TEST_ASSERT_EQUAL(-75, user_data.triggered_watch_values[2]); // step point (-25*3) - TEST_ASSERT_EQUAL(-100, user_data.triggered_watch_values[3]);// step point && watch point - TEST_ASSERT_EQUAL(0, user_data.triggered_watch_values[4]); // watch point (overflow zero cross) - - printf("simulating quadrature signals and count up\r\n"); - user_data.index = 0; - test_gpio_simulate_quadrature_signals(TEST_PCNT_GPIO_B, TEST_PCNT_GPIO_A, 3); // 0+3*4 = 12 - TEST_ESP_OK(pcnt_unit_get_count(unit, &count_value)); - printf("counter stopped at %d\r\n", count_value); - for (int i = 0 ; i < user_data.index; i++) { - printf("%d:%d\r\n", i, user_data.triggered_watch_values[i]); - } - TEST_ASSERT_EQUAL(12, count_value); - TEST_ASSERT_EQUAL(1, user_data.index); - TEST_ASSERT_EQUAL(11, user_data.triggered_watch_values[0]); // watch point - - printf("simulating quadrature signals and count down again\r\n"); - user_data.index = 0; - test_gpio_simulate_quadrature_signals(TEST_PCNT_GPIO_A, TEST_PCNT_GPIO_B, 13); // 12-13*4 = -40 - TEST_ESP_OK(pcnt_unit_get_count(unit, &count_value)); - printf("counter stopped at %d\r\n", count_value); - for (int i = 0 ; i < user_data.index; i++) { - printf("%d:%d\r\n", i, user_data.triggered_watch_values[i]); + if (pcnt_ll_is_step_notify_supported(0)) { // for ESP32H2, only support in chip version v1.2 and above + test_gpio_init_for_simulation(TEST_PCNT_GPIO_A); + test_gpio_init_for_simulation(TEST_PCNT_GPIO_B); + + pcnt_unit_config_t unit_config = { + .low_limit = -100, + .high_limit = 100, + .flags = { + .en_step_notify_down = true, + }, + }; + + printf("install pcnt unit\r\n"); + pcnt_unit_handle_t unit = NULL; + TEST_ESP_OK(pcnt_new_unit(&unit_config, &unit)); + pcnt_glitch_filter_config_t filter_config = { + .max_glitch_ns = 1000, + }; + TEST_ESP_OK(pcnt_unit_set_glitch_filter(unit, &filter_config)); + + printf("install two pcnt channels with different edge/level action\r\n"); + pcnt_chan_config_t channel_config = { + .edge_gpio_num = TEST_PCNT_GPIO_A, + .level_gpio_num = TEST_PCNT_GPIO_B, + }; + pcnt_channel_handle_t channelA = NULL; + TEST_ESP_OK(pcnt_new_channel(unit, &channel_config, &channelA)); + TEST_ESP_OK(pcnt_channel_set_edge_action(channelA, PCNT_CHANNEL_EDGE_ACTION_DECREASE, PCNT_CHANNEL_EDGE_ACTION_INCREASE)); + TEST_ESP_OK(pcnt_channel_set_level_action(channelA, PCNT_CHANNEL_LEVEL_ACTION_KEEP, PCNT_CHANNEL_LEVEL_ACTION_INVERSE)); + // switch edge gpio and level gpio, the assign to another channel in the same unit + pcnt_channel_handle_t channelB = NULL; + channel_config.edge_gpio_num = TEST_PCNT_GPIO_B; + channel_config.level_gpio_num = TEST_PCNT_GPIO_A; + TEST_ESP_OK(pcnt_new_channel(unit, &channel_config, &channelB)); + TEST_ESP_OK(pcnt_channel_set_edge_action(channelB, PCNT_CHANNEL_EDGE_ACTION_INCREASE, PCNT_CHANNEL_EDGE_ACTION_DECREASE)); + TEST_ESP_OK(pcnt_channel_set_level_action(channelB, PCNT_CHANNEL_LEVEL_ACTION_KEEP, PCNT_CHANNEL_LEVEL_ACTION_INVERSE)); + + // ensure the simulation signal in a stable state + TEST_ESP_OK(gpio_set_level(TEST_PCNT_GPIO_A, 1)); + TEST_ESP_OK(gpio_set_level(TEST_PCNT_GPIO_B, 1)); + + pcnt_event_callbacks_t cbs = { + .on_reach = test_pcnt_quadrature_reach_watch_point, + }; + test_pcnt_quadrature_context_t user_data = { + .index = 0, + .triggered_watch_values = {0}, + }; + TEST_ESP_OK(pcnt_unit_register_event_callbacks(unit, &cbs, &user_data)); + + printf("add watch step and point\r\n"); + TEST_ASSERT_EQUAL(ESP_ERR_INVALID_ARG, pcnt_unit_add_watch_step(unit, 0)); + TEST_ASSERT_EQUAL(ESP_ERR_INVALID_ARG, pcnt_unit_add_watch_step(unit, 20)); + TEST_ASSERT_EQUAL(ESP_ERR_INVALID_ARG, pcnt_unit_add_watch_step(unit, -120)); + TEST_ESP_OK(pcnt_unit_add_watch_step(unit, -25)); + TEST_ASSERT_EQUAL(ESP_ERR_INVALID_STATE, pcnt_unit_add_watch_step(unit, -100)); + TEST_ESP_OK(pcnt_unit_add_watch_point(unit, -100)); + TEST_ESP_OK(pcnt_unit_add_watch_point(unit, 0)); + TEST_ESP_OK(pcnt_unit_add_watch_point(unit, -50)); + TEST_ESP_OK(pcnt_unit_add_watch_point(unit, 11)); + + TEST_ESP_OK(pcnt_unit_enable(unit)); + TEST_ESP_OK(pcnt_unit_start(unit)); + + printf("simulating quadrature signals and count down\r\n"); + test_gpio_simulate_quadrature_signals(TEST_PCNT_GPIO_A, TEST_PCNT_GPIO_B, 25); // 25*(-4) = -100 -> 0 + + int count_value; + TEST_ESP_OK(pcnt_unit_get_count(unit, &count_value)); + printf("counter stopped at %d\r\n", count_value); + + for (int i = 0 ; i < user_data.index; i++) { + printf("%d:%d\r\n", i, user_data.triggered_watch_values[i]); + } + TEST_ASSERT_EQUAL(0, count_value); + TEST_ASSERT_EQUAL(5, user_data.index); + TEST_ASSERT_EQUAL(-25, user_data.triggered_watch_values[0]); // step point (-25*1) + TEST_ASSERT_EQUAL(-50, user_data.triggered_watch_values[1]); // step point && watch point + TEST_ASSERT_EQUAL(-75, user_data.triggered_watch_values[2]); // step point (-25*3) + TEST_ASSERT_EQUAL(-100, user_data.triggered_watch_values[3]);// step point && watch point + TEST_ASSERT_EQUAL(0, user_data.triggered_watch_values[4]); // watch point (overflow zero cross) + + printf("simulating quadrature signals and count up\r\n"); + user_data.index = 0; + test_gpio_simulate_quadrature_signals(TEST_PCNT_GPIO_B, TEST_PCNT_GPIO_A, 3); // 0+3*4 = 12 + TEST_ESP_OK(pcnt_unit_get_count(unit, &count_value)); + printf("counter stopped at %d\r\n", count_value); + for (int i = 0 ; i < user_data.index; i++) { + printf("%d:%d\r\n", i, user_data.triggered_watch_values[i]); + } + TEST_ASSERT_EQUAL(12, count_value); + TEST_ASSERT_EQUAL(1, user_data.index); + TEST_ASSERT_EQUAL(11, user_data.triggered_watch_values[0]); // watch point + + printf("simulating quadrature signals and count down again\r\n"); + user_data.index = 0; + test_gpio_simulate_quadrature_signals(TEST_PCNT_GPIO_A, TEST_PCNT_GPIO_B, 13); // 12-13*4 = -40 + TEST_ESP_OK(pcnt_unit_get_count(unit, &count_value)); + printf("counter stopped at %d\r\n", count_value); + for (int i = 0 ; i < user_data.index; i++) { + printf("%d:%d\r\n", i, user_data.triggered_watch_values[i]); + } + TEST_ASSERT_EQUAL(-40, count_value); + TEST_ASSERT_EQUAL(3, user_data.index); + TEST_ASSERT_EQUAL(11, user_data.triggered_watch_values[0]); // watch point + TEST_ASSERT_EQUAL(0, user_data.triggered_watch_values[1]); // watch point (zero cross) + TEST_ASSERT_EQUAL(-25, user_data.triggered_watch_values[2]);// step point (-25*1) + + // before change step interval, the next step point should be -25-25=-50 + printf("change step interval\r\n"); + TEST_ESP_OK(pcnt_unit_remove_watch_step(unit)); + TEST_ESP_OK(pcnt_unit_add_watch_step(unit, -20)); + // but after change, the next step point is -25-20=-45 (-25 is the last active step point) + + printf("simulating quadrature signals and count down\r\n"); + user_data.index = 0; + test_gpio_simulate_quadrature_signals(TEST_PCNT_GPIO_A, TEST_PCNT_GPIO_B, 20); // -40+20*(-4) = -120 -> -20 + TEST_ESP_OK(pcnt_unit_get_count(unit, &count_value)); + printf("counter stopped at %d\r\n", count_value); + + for (int i = 0 ; i < user_data.index; i++) { + printf("%d:%d\r\n", i, user_data.triggered_watch_values[i]); + } + TEST_ASSERT_EQUAL(-20, count_value); + TEST_ASSERT_EQUAL(7, user_data.index); + TEST_ASSERT_EQUAL(-45, user_data.triggered_watch_values[0]); // watch step + TEST_ASSERT_EQUAL(-50, user_data.triggered_watch_values[1]); // watch point + TEST_ASSERT_EQUAL(-65, user_data.triggered_watch_values[2]); // step point (-45-20) + TEST_ASSERT_EQUAL(-85, user_data.triggered_watch_values[3]); // step point (-65-20) + TEST_ASSERT_EQUAL(-100, user_data.triggered_watch_values[4]);// step && watch point + TEST_ASSERT_EQUAL(0, user_data.triggered_watch_values[5]); // watch point (overflow) + TEST_ASSERT_EQUAL(-20, user_data.triggered_watch_values[6]); // step point (0-20) + + printf("remove step_notify and uninstall channels\r\n"); + TEST_ESP_OK(pcnt_unit_remove_watch_step(unit)); + TEST_ASSERT_EQUAL(ESP_ERR_INVALID_STATE, pcnt_unit_remove_watch_step(unit)); + TEST_ESP_OK(pcnt_del_channel(channelA)); + TEST_ESP_OK(pcnt_del_channel(channelB)); + TEST_ESP_OK(pcnt_unit_stop(unit)); + TEST_ESP_OK(pcnt_unit_disable(unit)); + TEST_ESP_OK(pcnt_del_unit(unit)); } - TEST_ASSERT_EQUAL(-40, count_value); - TEST_ASSERT_EQUAL(3, user_data.index); - TEST_ASSERT_EQUAL(11, user_data.triggered_watch_values[0]); // watch point - TEST_ASSERT_EQUAL(0, user_data.triggered_watch_values[1]); // watch point (zero cross) - TEST_ASSERT_EQUAL(-25, user_data.triggered_watch_values[2]);// step point (-25*1) - - // before change step interval, the next step point should be -25-25=-50 - printf("change step interval\r\n"); - TEST_ESP_OK(pcnt_unit_remove_watch_step(unit)); - TEST_ESP_OK(pcnt_unit_add_watch_step(unit, -20)); - // but after change, the next step point is -25-20=-45 (-25 is the last active step point) - printf("simulating quadrature signals and count down\r\n"); - user_data.index = 0; - test_gpio_simulate_quadrature_signals(TEST_PCNT_GPIO_A, TEST_PCNT_GPIO_B, 20); // -40+20*(-4) = -120 -> -20 - TEST_ESP_OK(pcnt_unit_get_count(unit, &count_value)); - printf("counter stopped at %d\r\n", count_value); - - for (int i = 0 ; i < user_data.index; i++) { - printf("%d:%d\r\n", i, user_data.triggered_watch_values[i]); - } - TEST_ASSERT_EQUAL(-20, count_value); - TEST_ASSERT_EQUAL(7, user_data.index); - TEST_ASSERT_EQUAL(-45, user_data.triggered_watch_values[0]); // watch step - TEST_ASSERT_EQUAL(-50, user_data.triggered_watch_values[1]); // watch point - TEST_ASSERT_EQUAL(-65, user_data.triggered_watch_values[2]); // step point (-45-20) - TEST_ASSERT_EQUAL(-85, user_data.triggered_watch_values[3]); // step point (-65-20) - TEST_ASSERT_EQUAL(-100, user_data.triggered_watch_values[4]);// step && watch point - TEST_ASSERT_EQUAL(0, user_data.triggered_watch_values[5]); // watch point (overflow) - TEST_ASSERT_EQUAL(-20, user_data.triggered_watch_values[6]); // step point (0-20) - - printf("remove step_notify and uninstall channels\r\n"); - TEST_ESP_OK(pcnt_unit_remove_watch_step(unit)); - TEST_ASSERT_EQUAL(ESP_ERR_INVALID_STATE, pcnt_unit_remove_watch_step(unit)); - TEST_ESP_OK(pcnt_del_channel(channelA)); - TEST_ESP_OK(pcnt_del_channel(channelB)); - TEST_ESP_OK(pcnt_unit_stop(unit)); - TEST_ESP_OK(pcnt_unit_disable(unit)); - TEST_ESP_OK(pcnt_del_unit(unit)); } #endif // SOC_PCNT_SUPPORT_STEP_NOTIFY diff --git a/components/hal/esp32c5/include/hal/pcnt_ll.h b/components/hal/esp32c5/include/hal/pcnt_ll.h index a1de9bd8de5..491303725cb 100644 --- a/components/hal/esp32c5/include/hal/pcnt_ll.h +++ b/components/hal/esp32c5/include/hal/pcnt_ll.h @@ -497,6 +497,16 @@ static inline void pcnt_ll_reset_register(int group_id) PCR.pcnt_conf.pcnt_rst_en = 0; } +/** + * @brief Check if the step notify is supported + */ +static inline bool pcnt_ll_is_step_notify_supported(int group_id) +{ + (void)group_id; + return true; +} + + #ifdef __cplusplus } #endif diff --git a/components/hal/esp32h2/include/hal/pcnt_ll.h b/components/hal/esp32h2/include/hal/pcnt_ll.h index 23fc40f6729..f8b21a1642b 100644 --- a/components/hal/esp32h2/include/hal/pcnt_ll.h +++ b/components/hal/esp32h2/include/hal/pcnt_ll.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2022-2024 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -19,6 +19,9 @@ #include #include "soc/pcnt_struct.h" #include "hal/pcnt_types.h" +#include "hal/misc.h" +#include "hal/efuse_hal.h" +#include "soc/chip_revision.h" #include "soc/pcr_struct.h" #ifdef __cplusplus @@ -40,6 +43,12 @@ typedef enum { PCNT_LL_WATCH_EVENT_MAX } pcnt_ll_watch_event_id_t; +typedef enum { + PCNT_LL_STEP_EVENT_REACH_LIMIT = PCNT_LL_WATCH_EVENT_MAX, + PCNT_LL_STEP_EVENT_REACH_INTERVAL +} pcnt_ll_step_event_id_t; + +#define PCNT_LL_STEP_NOTIFY_DIR_LIMIT 1 #define PCNT_LL_WATCH_EVENT_MASK ((1 << PCNT_LL_WATCH_EVENT_MAX) - 1) #define PCNT_LL_UNIT_WATCH_EVENT(unit_id) (1 << (unit_id)) @@ -137,6 +146,46 @@ static inline void pcnt_ll_clear_count(pcnt_dev_t *hw, uint32_t unit) hw->ctrl.val &= ~(1 << (2 * unit)); } +/** + * @brief Enable PCNT step comparator event + * + * @param hw Peripheral PCNT hardware instance address. + * @param unit PCNT unit number + * @param enable true to enable, false to disable + */ +static inline void pcnt_ll_enable_step_notify(pcnt_dev_t *hw, uint32_t unit, bool enable) +{ + if (enable) { + hw->ctrl.val |= 1 << (8 + unit); + } else { + hw->ctrl.val &= ~(1 << (8 + unit)); + } +} + +/** + * @brief Set PCNT step value + * + * @param hw Peripheral PCNT hardware instance address. + * @param unit PCNT unit number + * @param value PCNT step value + */ +static inline void pcnt_ll_set_step_value(pcnt_dev_t *hw, uint32_t unit, int value) +{ + HAL_FORCE_MODIFY_U32_REG_FIELD(hw->change_conf_unit[3 - unit], cnt_step, value); +} + +/** + * @brief Set PCNT step limit value + * + * @param hw Peripheral PCNT hardware instance address. + * @param unit PCNT unit number + * @param value PCNT step limit value + */ +static inline void pcnt_ll_set_step_limit_value(pcnt_dev_t *hw, uint32_t unit, int value) +{ + HAL_FORCE_MODIFY_U32_REG_FIELD(hw->change_conf_unit[3 - unit], cnt_step_lim, value); +} + /** * @brief Enable PCNT interrupt for PCNT unit * @note Each PCNT unit has five watch point events that share the same interrupt bit. @@ -458,6 +507,16 @@ static inline void pcnt_ll_reset_register(int group_id) PCR.pcnt_conf.pcnt_rst_en = 0; } +/** + * @brief Check if the step notify is supported + */ +static inline bool pcnt_ll_is_step_notify_supported(int group_id) +{ + (void)group_id; + return ESP_CHIP_REV_ABOVE(efuse_hal_chip_revision(), 102); +} + + #ifdef __cplusplus } #endif diff --git a/components/soc/esp32h2/include/soc/Kconfig.soc_caps.in b/components/soc/esp32h2/include/soc/Kconfig.soc_caps.in index 23ab08014f9..b482ef074e7 100644 --- a/components/soc/esp32h2/include/soc/Kconfig.soc_caps.in +++ b/components/soc/esp32h2/include/soc/Kconfig.soc_caps.in @@ -775,6 +775,10 @@ config SOC_PCNT_SUPPORT_RUNTIME_THRES_UPDATE bool default y +config SOC_PCNT_SUPPORT_STEP_NOTIFY + bool + default y + config SOC_PCNT_SUPPORT_SLEEP_RETENTION bool default y diff --git a/components/soc/esp32h2/include/soc/soc_caps.h b/components/soc/esp32h2/include/soc/soc_caps.h index c4de9c97a7d..f50dc3819c6 100644 --- a/components/soc/esp32h2/include/soc/soc_caps.h +++ b/components/soc/esp32h2/include/soc/soc_caps.h @@ -305,6 +305,7 @@ #define SOC_PCNT_CHANNELS_PER_UNIT 2 #define SOC_PCNT_THRES_POINT_PER_UNIT 2 #define SOC_PCNT_SUPPORT_RUNTIME_THRES_UPDATE 1 +#define SOC_PCNT_SUPPORT_STEP_NOTIFY 1 /*!< Only avliable in chip version above 1.2*/ #define SOC_PCNT_SUPPORT_SLEEP_RETENTION 1 /*!< The sleep retention feature can help back up PCNT registers before sleep */ /*--------------------------- RMT CAPS ---------------------------------------*/ diff --git a/components/soc/esp32h2/register/soc/pcnt_struct.h b/components/soc/esp32h2/register/soc/pcnt_struct.h index 4c372320c56..b67c3aedb9f 100644 --- a/components/soc/esp32h2/register/soc/pcnt_struct.h +++ b/components/soc/esp32h2/register/soc/pcnt_struct.h @@ -1,5 +1,5 @@ /** - * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2022-2024 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -181,7 +181,23 @@ typedef union { * Set this bit to freeze unit 3's counter. */ uint32_t cnt_pause_u3:1; - uint32_t reserved_8:8; + /** dalta_change_en_u0 : R/W; bitpos: [8]; default: 0; + * Configures this bit to enable unit 0's step comparator. + */ + uint32_t dalta_change_en_u0:1; + /** dalta_change_en_u1 : R/W; bitpos: [9]; default: 0; + * Configures this bit to enable unit 1's step comparator. + */ + uint32_t dalta_change_en_u1:1; + /** dalta_change_en_u2 : R/W; bitpos: [10]; default: 0; + * Configures this bit to enable unit 2's step comparator. + */ + uint32_t dalta_change_en_u2:1; + /** dalta_change_en_u3 : R/W; bitpos: [11]; default: 0; + * Configures this bit to enable unit 3's step comparator. + */ + uint32_t dalta_change_en_u3:1; + uint32_t reserved_12:4; /** clk_en : R/W; bitpos: [16]; default: 0; * The registers clock gate enable signal of PCNT module. 1: the registers can be read * and written by application. 0: the registers can not be read or written by @@ -193,6 +209,22 @@ typedef union { uint32_t val; } pcnt_ctrl_reg_t; +/** Type of change_conf register + * Configuration register for unit $n's step value. + */ +typedef union { + struct { + /** cnt_step : R/W; bitpos: [15:0]; default: 0; + * Configures the step value for unit n. + */ + uint32_t cnt_step:16; + /** cnt_step_lim : R/W; bitpos: [31:16]; default: 0; + * Configures the step limit value for unit n. + */ + uint32_t cnt_step_lim:16; + }; + uint32_t val; +} pcnt_un_change_conf_reg_t; /** Group: Status Register */ /** Type of un_cnt register @@ -250,7 +282,19 @@ typedef union { * valid. 0: others */ uint32_t cnt_thr_zero_lat:1; - uint32_t reserved_7:25; + /** cnt_thr_step_lim_lat_un : RO; bitpos: [7]; default: 0; + * The latched value of step counter limit event of PCNT_Un when step counter event + * interrupt is valid. 1: the current pulse counter equals to reg_cnt_step_lim and + * step counter event is valid. 0: others + */ + uint32_t cnt_thr_step_lim_lat_un:1; + /** cnt_thr_step_lat_un : RO; bitpos: [8]; default: 0; + * The latched value of step counter event of PCNT_Un when step counter event + * interrupt is valid. 1: the current pulse counter increment equals to reg_cnt_step + * and step counter event is valid. 0: others + */ + uint32_t cnt_thr_step_lat_un:1; + uint32_t reserved_7:23; }; uint32_t val; } pcnt_un_status_reg_t; @@ -389,7 +433,8 @@ typedef struct pcnt_dev_t { volatile pcnt_int_clr_reg_t int_clr; volatile pcnt_un_status_reg_t status_unit[4]; volatile pcnt_ctrl_reg_t ctrl; - uint32_t reserved_064[38]; + volatile pcnt_un_change_conf_reg_t change_conf_unit[4]; // Note the unit order is 3210 + uint32_t reserved_064[34]; volatile pcnt_date_reg_t date; } pcnt_dev_t; From d5ccc60eb0b9e871ef5670d053dede820d3fb7ba Mon Sep 17 00:00:00 2001 From: "nilesh.kale" Date: Wed, 11 Dec 2024 14:31:15 +0530 Subject: [PATCH 042/118] feat(esp_http_server): add support to handle HTTP 1.0 requests This commit adds support to handle HTTP/1.0 requests alongside HTTP/1.1 for legacy compliance purposes. --- components/esp_http_server/include/esp_http_server.h | 2 +- components/esp_http_server/src/httpd_parse.c | 4 ++-- 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/components/esp_http_server/include/esp_http_server.h b/components/esp_http_server/include/esp_http_server.h index d6b6e7709aa..a6165835082 100644 --- a/components/esp_http_server/include/esp_http_server.h +++ b/components/esp_http_server/include/esp_http_server.h @@ -569,7 +569,7 @@ typedef enum { */ HTTPD_501_METHOD_NOT_IMPLEMENTED, - /* When HTTP version is not 1.1 */ + /* When HTTP version is not 1.1 or 1.0*/ HTTPD_505_VERSION_NOT_SUPPORTED, /* Returned when http_parser halts parsing due to incorrect diff --git a/components/esp_http_server/src/httpd_parse.c b/components/esp_http_server/src/httpd_parse.c index 2fbc37f3eb8..9cd2e26f0a6 100644 --- a/components/esp_http_server/src/httpd_parse.c +++ b/components/esp_http_server/src/httpd_parse.c @@ -85,8 +85,8 @@ static esp_err_t verify_url (http_parser *parser) strlcpy((char *)r->uri, at, (length + 1)); ESP_LOGD(TAG, LOG_FMT("received URI = %s"), r->uri); - /* Make sure version is HTTP/1.1 */ - if (!((parser->http_major == 1) && (parser->http_minor == 1))) { + /* Make sure version is HTTP/1.1 or HTTP/1.0 (legacy compliance purpose) */ + if (!((parser->http_major == 1) && ((parser->http_minor == 0) || (parser->http_minor == 1)))) { ESP_LOGW(TAG, LOG_FMT("unsupported HTTP version = %d.%d"), parser->http_major, parser->http_minor); parser_data->error = HTTPD_505_VERSION_NOT_SUPPORTED; From 54ea9e40ca081e6a43254caff9d26fbe7f24de79 Mon Sep 17 00:00:00 2001 From: wanckl Date: Wed, 11 Dec 2024 19:04:31 +0800 Subject: [PATCH 043/118] fix(esp_adc): wrap monitor test cases --- components/esp_adc/test_apps/adc/main/test_adc.c | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/components/esp_adc/test_apps/adc/main/test_adc.c b/components/esp_adc/test_apps/adc/main/test_adc.c index 0180710d0e2..32e20659c2b 100644 --- a/components/esp_adc/test_apps/adc/main/test_adc.c +++ b/components/esp_adc/test_apps/adc/main/test_adc.c @@ -397,6 +397,7 @@ TEST_CASE("ADC continuous monitor init_deinit", "[adc]") TEST_ESP_OK(adc_continuous_deinit(handle)); } +#if SOC_ADC_CALIBRATION_V1_SUPPORTED #define TEST_ADC_CHANNEL ADC_CHANNEL_0 static uint32_t m1h_cnt, m1l_cnt; @@ -443,9 +444,9 @@ TEST_CASE("ADC continuous monitor functionary", "[adc]") #if CONFIG_IDF_TARGET_ESP32S2 .h_threshold = -1, //S2 support only one threshold for one monitor #else - .h_threshold = 3000, + .h_threshold = ADC_TEST_HIGH_VAL_DMA - (ADC_TEST_HIGH_VAL_DMA - ADC_TEST_LOW_VAL) / 4, #endif - .l_threshold = 1000, + .l_threshold = ADC_TEST_LOW_VAL + (ADC_TEST_HIGH_VAL_DMA - ADC_TEST_LOW_VAL) / 4, }; adc_monitor_evt_cbs_t monitor_cb = { #if !CONFIG_IDF_TARGET_ESP32S2 @@ -496,5 +497,5 @@ TEST_CASE("ADC continuous monitor functionary", "[adc]") TEST_ESP_OK(adc_del_continuous_monitor(monitor_handle)); TEST_ESP_OK(adc_continuous_deinit(handle)); } - +#endif //SOC_ADC_CALIBRATION_V1_SUPPORTED #endif //SOC_ADC_MONITOR_SUPPORTED && CONFIG_SOC_ADC_DMA_SUPPORTED From c711541e2be15d283c6220a4bd89862c89cd6668 Mon Sep 17 00:00:00 2001 From: Tan Yan Quan Date: Tue, 3 Dec 2024 20:00:31 +0800 Subject: [PATCH 044/118] feat(802.15.4): add some documentation for txrx statistics and debug record --- .../components/cmd_ieee802154_debug/README.md | 124 +++++++++++++++++- .../cmd_ieee802154_debug/ieee802154_debug.c | 1 + 2 files changed, 120 insertions(+), 5 deletions(-) diff --git a/examples/ieee802154/components/cmd_ieee802154_debug/README.md b/examples/ieee802154/components/cmd_ieee802154_debug/README.md index 1393266cc9c..eb37d6139ba 100644 --- a/examples/ieee802154/components/cmd_ieee802154_debug/README.md +++ b/examples/ieee802154/components/cmd_ieee802154_debug/README.md @@ -1,13 +1,27 @@ | Supported Targets | ESP32-C5 | ESP32-C6 | ESP32-H2 | | ----------------- | -------- | -------- | -------- | -# IEEE802.15.4 RX Buffer Statistics Component +# IEEE802.15.4 Debug Component -This component is used to consolidate the RX buffer statistics for IEEE802.15.4. The use of this component is demonstrated in the `ieee802154_cli` example, but can be similarly implemented for other stack examples (e.g. Zigbee / Thread). +This component is used to enable several debug features, including: +- Consolidate the RX buffer statistics for IEEE802.15.4 +- Consolidate the TX / RX statistics for IEEE802.15.4 +- Print the recorded events for IEEE802.15.4 + +The use of this component is demonstrated in the `ieee802154_cli` example below, but can be similarly implemented in examples (e.g. Zigbee / Thread) for other protocol stacks. ## How to use component -In addition to the necessary configurations described in the `ieee802154_cli` example, some additional steps are required for configuring the board to enable the RX buffer statistics component. +In addition to the necessary configurations described in the `ieee802154_cli` example, some additional steps are required for configuring the board to enable the IEEE802.15.4 Debug component. + +This component should be added as a dependency in `idf_component.yml`: +``` +dependencies: + cmd_ieee802154_debug: + path: ${IDF_PATH}/examples/ieee802154/components/cmd_ieee802154_debug +``` + +The `register_ieee802154_debug_cmd()` function should be called upon initialization to register the commands to be used in the cli. To enable this function, use: ``` idf.py menuconfig @@ -16,7 +30,15 @@ idf.py menuconfig This component can be enabled through the menuconfig: ``` -Component config → IEEE 802.15.4 → IEEE802154 Enable → Enable IEEE802154 Debug → Rx buffer statistic +Component config → IEEE 802.15.4 → IEEE802154 Enable → Enable IEEE802154 Debug +``` + +The commands can be independently enabled / disabled using: + +``` +Enable IEEE802154 Debug → Rx buffer statistic +Enable IEEE802154 Debug → Record the information with IEEE802154 state and event +Enable IEEE802154 Debug → Enable record tx/rx packets information for debugging ``` ### Build, Flash, and Run @@ -31,9 +53,48 @@ Now you'll get an IEEE802.15.4 command line shell. ## IEEE802.15.4 Command List -In addition to the commands available in the `ieee802154_cli` example, enabling this component provides a new command: +In addition to the commands available in the `ieee802154_cli` example, enabling this component provides the following new commands: +- [record](#record) - [rxbufstat](#rxbufstat) +- [txrxstat](#txrxstat) + +### record +#### record -p +Print the recorded IEEE802154 state/event/cmd etc. + +```bash +ieee802154> record -p +W (130811) ieee802154: Print the record event, current event index: 14 +W (130811) ieee802154: index 0: event: 0x1000, RX_SFD_DONE, state: RX, timestamp: 90951226 +... +W (130921) ieee802154: index 13: event: 0x 2, RX_DONE, state: RX, timestamp: 109182378 +W (130931) ieee802154: index 14: event: 0x 0, Multi events, state: DISABLE, timestamp: 0 +... +W (131061) ieee802154: index 29: event: 0x 0, Multi events, state: DISABLE, timestamp: 0 +W (131071) ieee802154: Print the record event done. +W (131071) ieee802154: Print the record state, current state index: 9 +W (131081) ieee802154: index 0: line: 794, state: IDLE, timestamp: 114737 +W (131091) ieee802154: index 1: line: 354, state: RX, timestamp: 90578575 +... +W (131131) ieee802154: index 7: line: 354, state: RX, timestamp: 109215261 +W (131141) ieee802154: index 8: line: 1038, state: SLEEP, timestamp: 112782354 +W (131141) ieee802154: index 9: line: , state: DISABLE, timestamp: 0 +W (131151) ieee802154: Print the record state done. +W (131161) ieee802154: Print the record cmd, current cmd index: 8 +W (131161) ieee802154: index 0: line: 352, cmd: rx, timestamp: 90578559 +... +W (131211) ieee802154: index 7: line: 204, cmd: stop, timestamp: 112782331 +W (131221) ieee802154: index 8: line: , cmd: , timestamp: 0 +W (131221) ieee802154: index 9: line: , cmd: , timestamp: 0 +W (131231) ieee802154: Print the record cmd done. +W (131241) ieee802154: Print the record abort, current abort index: 0 +W (131241) ieee802154: index 0: rx abort: 0, RSVD, timestamp: 0 +... +W (131301) ieee802154: index 9: rx abort: 0, RSVD, timestamp: 0 +W (131311) ieee802154: Print the record abort done. + +``` ### rxbufstat #### rxbufstat -p @@ -65,4 +126,57 @@ Clear the rx buffer statistics. ```bash > rxbufstat -c I (7971) i154cmd: clear the rx buffer statistics +``` + +### txrxstat +#### txrxstat -p +Print a summary table of rx buffer statistics. + +```bash +ieee802154> txrxstat -p +W (115381) ieee802154: +--------------------+-----------------------------------+--------------------------------------------------+ +W (115381) ieee802154: | |Done: 0 0.00%|Success: 0 0.00%| +W (115391) ieee802154: + + +--------------------------------------------------+ +W (115401) ieee802154: | | |tx_direct_num: 0 0.00%| +W (115411) ieee802154: + + +--------------------------------------------------+ +W (115431) ieee802154: | | |tx_deferred_num: 0 0.00%| +W (115451) ieee802154: + +-----------------------------------+--------------------------------------------------+ +W (115461) ieee802154: | | |rx_ack_coex_break: 0 0.00%| +W (115471) ieee802154: + + +--------------------------------------------------+ +W (115481) ieee802154: | | |rx_ack_timeout: 0 0.00%| +W (115491) ieee802154: + + +--------------------------------------------------+ +W (115501) ieee802154: |TX: 0 |Abort 0 0.00%|tx_coex_break: 0 0.00%| +W (115511) ieee802154: + + +--------------------------------------------------+ +W (115531) ieee802154: | | |tx_security_error: 0 0.00%| +W (115541) ieee802154: + + +--------------------------------------------------+ +W (115551) ieee802154: | | |cca_failed: 0 0.00%| +W (115561) ieee802154: + + +--------------------------------------------------+ +W (115571) ieee802154: | | |cca_busy: 0 0.00%| +W (115581) ieee802154: +--------------------+-----------------------------------+--------------------------------------------------+ +W (115591) ieee802154: | |Done: 6 |Success: 6 | +W (115611) ieee802154: + +-----------------------------------+--------------------------------------------------+ +W (115621) ieee802154: | | |tx_ack_coex_break: 0 | +W (115631) ieee802154: + + +--------------------------------------------------+ +W (115641) ieee802154: | | |sfd_timeout: 14 | +W (115651) ieee802154: + + +--------------------------------------------------+ +W (115661) ieee802154: | | |crc_error: 1 | +W (115671) ieee802154: + + +--------------------------------------------------+ +W (115691) ieee802154: |RX |Abort 17 |filter_fail: 0 | +W (115701) ieee802154: + + +--------------------------------------------------+ +W (115711) ieee802154: | | |no_rss: 0 | +W (115721) ieee802154: + + +--------------------------------------------------+ +W (115731) ieee802154: | | |rx_coex_break: 0 | +W (115741) ieee802154: + + +--------------------------------------------------+ +W (115751) ieee802154: | | |rx_restart: 2 | +W (115771) ieee802154: + + +--------------------------------------------------+ +W (115781) ieee802154: | | |ed_abort: 0 | +W (115791) ieee802154: +--------------------+-----------------------------------+--------------------------------------------------+ +``` + +#### txrxstat -c +Clear the rx buffer statistics. + +```bash +> txrxstat -c +I (7971) i154cmd: clear the txrx statistics ``` \ No newline at end of file diff --git a/examples/ieee802154/components/cmd_ieee802154_debug/ieee802154_debug.c b/examples/ieee802154/components/cmd_ieee802154_debug/ieee802154_debug.c index b97a53050c5..c3664159c0c 100644 --- a/examples/ieee802154/components/cmd_ieee802154_debug/ieee802154_debug.c +++ b/examples/ieee802154/components/cmd_ieee802154_debug/ieee802154_debug.c @@ -107,6 +107,7 @@ static int process_txrx_statistic(int argc, char **argv) } if (txrx_stat_args.clear->count) { esp_ieee802154_txrx_statistic_clear(); + ESP_LOGI(TAG, "clear the txrx statistics"); } if (!txrx_stat_args.print->count && !txrx_stat_args.clear->count) { ESP_LOGE(TAG, "no valid arguments"); From 3d0688942c8cad8fcf0a427d151c9d9721dc6f5b Mon Sep 17 00:00:00 2001 From: WanqQixiang Date: Tue, 12 Nov 2024 14:39:14 +0800 Subject: [PATCH 045/118] feat(protocol_examples_common): Add Thread connect to support Thread for the protocol examples --- .../protocol_examples_common/CMakeLists.txt | 10 +- .../Kconfig.projbuild | 78 ++++++++++- .../protocol_examples_common/README.md | 10 +- .../protocol_examples_common/connect.c | 16 ++- .../include/example_common_private.h | 4 +- .../include/protocol_examples_common.h | 7 + .../include/protocol_examples_thread_config.h | 105 ++++++++++++++ .../protocol_examples_common/thread_connect.c | 130 ++++++++++++++++++ .../protocols/sntp/sdkconfig.defaults.esp32h2 | 4 + 9 files changed, 354 insertions(+), 10 deletions(-) create mode 100644 examples/common_components/protocol_examples_common/include/protocol_examples_thread_config.h create mode 100644 examples/common_components/protocol_examples_common/thread_connect.c create mode 100644 examples/protocols/sntp/sdkconfig.defaults.esp32h2 diff --git a/examples/common_components/protocol_examples_common/CMakeLists.txt b/examples/common_components/protocol_examples_common/CMakeLists.txt index 1af6081ddfe..8d0501a9b1b 100644 --- a/examples/common_components/protocol_examples_common/CMakeLists.txt +++ b/examples/common_components/protocol_examples_common/CMakeLists.txt @@ -22,6 +22,10 @@ if(CONFIG_EXAMPLE_CONNECT_ETHERNET) list(APPEND srcs "eth_connect.c") endif() +if(CONFIG_EXAMPLE_CONNECT_THREAD) + list(APPEND srcs "thread_connect.c") +endif() + if(CONFIG_EXAMPLE_CONNECT_PPP) list(APPEND srcs "ppp_connect.c") endif() @@ -29,7 +33,7 @@ endif() idf_component_register(SRCS "${srcs}" INCLUDE_DIRS "include" - PRIV_REQUIRES esp_netif esp_driver_gpio esp_driver_uart esp_wifi vfs console esp_eth) + PRIV_REQUIRES esp_netif esp_driver_gpio esp_driver_uart esp_wifi vfs console esp_eth openthread) if(CONFIG_EXAMPLE_PROVIDE_WIFI_CONSOLE_CMD) idf_component_optional_requires(PRIVATE console) @@ -39,6 +43,10 @@ if(CONFIG_EXAMPLE_CONNECT_ETHERNET) idf_component_optional_requires(PUBLIC esp_eth) endif() +if(CONFIG_EXAMPLE_CONNECT_THREAD) + idf_component_optional_requires(PRIVATE openthread) +endif() + if(CONFIG_EXAMPLE_CONNECT_PPP) idf_component_optional_requires(PRIVATE esp_tinyusb espressif__esp_tinyusb) endif() diff --git a/examples/common_components/protocol_examples_common/Kconfig.projbuild b/examples/common_components/protocol_examples_common/Kconfig.projbuild index 50a973bffcc..f9ccbfb5699 100644 --- a/examples/common_components/protocol_examples_common/Kconfig.projbuild +++ b/examples/common_components/protocol_examples_common/Kconfig.projbuild @@ -7,7 +7,7 @@ menu "Example Connection Configuration" depends on !IDF_TARGET_LINUX && (SOC_WIFI_SUPPORTED || ESP_WIFI_REMOTE_ENABLED || ESP_HOST_WIFI_ENABLED) default y if SOC_WIFI_SUPPORTED help - Protocol examples can use Wi-Fi and/or Ethernet to connect to the network. + Protocol examples can use Wi-Fi, Ethernet and/or Thread to connect to the network. Choose this option to connect with WiFi if EXAMPLE_CONNECT_WIFI @@ -119,9 +119,9 @@ menu "Example Connection Configuration" config EXAMPLE_CONNECT_ETHERNET bool "connect using Ethernet interface" depends on !IDF_TARGET_LINUX - default y if !EXAMPLE_CONNECT_WIFI + default y if !EXAMPLE_CONNECT_WIFI && !EXAMPLE_CONNECT_THREAD help - Protocol examples can use Wi-Fi and/or Ethernet to connect to the network. + Protocol examples can use Wi-Fi, Ethernet and/or Thread to connect to the network. Choose this option to connect with Ethernet if EXAMPLE_CONNECT_ETHERNET @@ -381,13 +381,83 @@ menu "Example Connection Configuration" endif # EXAMPLE_CONNECT_PPP + config EXAMPLE_CONNECT_THREAD + bool "Connect using Thread interface" + depends on !IDF_TARGET_LINUX && OPENTHREAD_ENABLED + default y if SOC_IEEE802154_SUPPORTED + select EXAMPLE_CONNECT_IPV6 + help + Protocol examples can use Wi-Fi, Ethernet and/or Thread to connect to the network. + Choose this option to connect with Thread. + The operational active dataset of the Thread network can be configured in openthread + component at '->Components->OpenThread->Thread Core Features->Thread Operational Dataset' + + if EXAMPLE_CONNECT_THREAD + config EXAMPLE_THREAD_TASK_STACK_SIZE + int "Example Thread task stack size" + default 8192 + help + Thread task stack size + + menu "Radio Spinel Options" + depends on OPENTHREAD_RADIO_SPINEL_UART || OPENTHREAD_RADIO_SPINEL_SPI + + config EXAMPLE_THREAD_UART_RX_PIN + depends on OPENTHREAD_RADIO_SPINEL_UART + int "Uart Rx Pin" + default 17 + + config EXAMPLE_THREAD_UART_TX_PIN + depends on OPENTHREAD_RADIO_SPINEL_UART + int "Uart Tx pin" + default 18 + + config EXAMPLE_THREAD_UART_BAUD + depends on OPENTHREAD_RADIO_SPINEL_UART + int "Uart baud rate" + default 460800 + + config EXAMPLE_THREAD_UART_PORT + depends on OPENTHREAD_RADIO_SPINEL_UART + int "Uart port" + default 1 + + config EXAMPLE_THREAD_SPI_CS_PIN + depends on OPENTHREAD_RADIO_SPINEL_SPI + int "SPI CS Pin" + default 10 + + config EXAMPLE_THREAD_SPI_SCLK_PIN + depends on OPENTHREAD_RADIO_SPINEL_SPI + int "SPI SCLK Pin" + default 12 + + config EXAMPLE_THREAD_SPI_MISO_PIN + depends on OPENTHREAD_RADIO_SPINEL_SPI + int "SPI MISO Pin" + default 13 + + config EXAMPLE_THREAD_SPI_MOSI_PIN + depends on OPENTHREAD_RADIO_SPINEL_SPI + int "SPI MOSI Pin" + default 11 + + config EXAMPLE_THREAD_SPI_INTR_PIN + depends on OPENTHREAD_RADIO_SPINEL_SPI + int "SPI Interrupt Pin" + default 8 + endmenu + + endif + config EXAMPLE_CONNECT_IPV4 bool depends on LWIP_IPV4 + default n if EXAMPLE_CONNECT_THREAD default y config EXAMPLE_CONNECT_IPV6 - depends on EXAMPLE_CONNECT_WIFI || EXAMPLE_CONNECT_ETHERNET || EXAMPLE_CONNECT_PPP + depends on EXAMPLE_CONNECT_WIFI || EXAMPLE_CONNECT_ETHERNET || EXAMPLE_CONNECT_PPP || EXAMPLE_CONNECT_THREAD bool "Obtain IPv6 address" default y select LWIP_IPV6 diff --git a/examples/common_components/protocol_examples_common/README.md b/examples/common_components/protocol_examples_common/README.md index f80d6b2fa8e..00111dbfc5e 100644 --- a/examples/common_components/protocol_examples_common/README.md +++ b/examples/common_components/protocol_examples_common/README.md @@ -4,7 +4,7 @@ This component implements the most common connection methods for ESP32 boards. I ## How to use this component -Choose the preferred interface (WiFi, Ethernet, PPPoS) to connect to the network and configure the interface. +Choose the preferred interface (WiFi, Ethernet, Thread, PPPoS) to connect to the network and configure the interface. It is possible to enable multiple interfaces simultaneously making the connection phase to block until all the chosen interfaces acquire IP addresses. It is also possible to disable all interfaces, skipping the connection phase altogether. @@ -23,6 +23,14 @@ Choose WiFi connection method (for chipsets that support it) and configure basic Choose Ethernet connection if your board supports it. The most common settings is using Espressif Ethernet Kit, which is also the recommended HW for this selection. You can also select an SPI ethernet device (if your chipset doesn't support internal EMAC or if you prefer). It is also possible to use OpenCores Ethernet MAC if you're running the example under QEMU. +### Thread + +Choose Thread connection if your board supports IEEE802.15.4 native radio or works with [OpenThread RCP](../../openthread/ot_rcp/README.md). You can configure the Thread network at menuconfig '->Components->OpenThread->Thread Core Features->Thread Operational Dataset'. + +If the Thread end-device joins a Thread network with a Thread Border Router that has the NAT64 feature enabled, the end-device can access the Internet with the standard DNS APIs after configuring the following properties: +* Enable DNS64 client ('->Components->OpenThread->Thread Core Features->Enable DNS64 client') +* Enable custom DNS external resolve Hook ('->Components->LWIP->Hooks->DNS external resolve Hook->Custom implementation') + ### PPP Point to point connection method creates a simple IP tunnel to the counterpart device (running PPP server), typically a Linux machine with pppd service. We currently support only PPP over Serial (using UART or USB CDC). This is useful for simple testing of networking layers, but with some additional configuration on the server side, we could simulate standard model of internet connectivity. The PPP server could be also represented by a cellular modem device with pre-configured connectivity and already switched to PPP mode (this setup is not very flexible though, so we suggest using a standard modem library implementing commands and modes, e.g. [esp_modem](https://components.espressif.com/component/espressif/esp_modem) ). diff --git a/examples/common_components/protocol_examples_common/connect.c b/examples/common_components/protocol_examples_common/connect.c index f6aa9bbee8e..65fa2b85681 100644 --- a/examples/common_components/protocol_examples_common/connect.c +++ b/examples/common_components/protocol_examples_common/connect.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2022-2024 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Unlicense OR CC0-1.0 */ @@ -35,7 +35,7 @@ const char *example_ipv6_addr_types_to_str[6] = { /** * @brief Checks the netif description if it contains specified prefix. - * All netifs created withing common connect component are prefixed with the module TAG, + * All netifs created within common connect component are prefixed with the module TAG, * so it returns true if the specified netif is owned by this module */ bool example_is_our_netif(const char *prefix, esp_netif_t *netif) @@ -61,7 +61,7 @@ static esp_err_t print_all_ips_tcpip(void* ctx) while ((netif = esp_netif_next_unsafe(netif)) != NULL) { if (example_is_our_netif(prefix, netif)) { ESP_LOGI(TAG, "Connected to %s", esp_netif_get_desc(netif)); -#if CONFIG_LWIP_IPV4 +#if CONFIG_EXAMPLE_CONNECT_IPV4 esp_netif_ip_info_t ip; ESP_ERROR_CHECK(esp_netif_get_ip_info(netif, &ip)); @@ -101,6 +101,12 @@ esp_err_t example_connect(void) } ESP_ERROR_CHECK(esp_register_shutdown_handler(&example_wifi_shutdown)); #endif +#if CONFIG_EXAMPLE_CONNECT_THREAD + if (example_thread_connect() != ESP_OK) { + return ESP_FAIL; + } + ESP_ERROR_CHECK(esp_register_shutdown_handler(&example_thread_shutdown)); +#endif #if CONFIG_EXAMPLE_CONNECT_PPP if (example_ppp_connect() != ESP_OK) { return ESP_FAIL; @@ -116,6 +122,10 @@ esp_err_t example_connect(void) example_print_all_netif_ips(EXAMPLE_NETIF_DESC_STA); #endif +#if CONFIG_EXAMPLE_CONNECT_THREAD + example_print_all_netif_ips(EXAMPLE_NETIF_DESC_THREAD); +#endif + #if CONFIG_EXAMPLE_CONNECT_PPP example_print_all_netif_ips(EXAMPLE_NETIF_DESC_PPP); #endif diff --git a/examples/common_components/protocol_examples_common/include/example_common_private.h b/examples/common_components/protocol_examples_common/include/example_common_private.h index 8a0b880ecbd..ad6ef537e42 100644 --- a/examples/common_components/protocol_examples_common/include/example_common_private.h +++ b/examples/common_components/protocol_examples_common/include/example_common_private.h @@ -3,7 +3,7 @@ * * SPDX-License-Identifier: Unlicense OR CC0-1.0 */ -/* Private Funtions of protocol example common */ +/* Private Functions of protocol example common */ #pragma once @@ -45,6 +45,8 @@ void example_wifi_shutdown(void); esp_err_t example_wifi_connect(void); void example_ethernet_shutdown(void); esp_err_t example_ethernet_connect(void); +void example_thread_shutdown(void); +esp_err_t example_thread_connect(void); esp_err_t example_ppp_connect(void); void example_ppp_start(void); void example_ppp_shutdown(void); diff --git a/examples/common_components/protocol_examples_common/include/protocol_examples_common.h b/examples/common_components/protocol_examples_common/include/protocol_examples_common.h index b23f452acc7..54e2c07a11e 100644 --- a/examples/common_components/protocol_examples_common/include/protocol_examples_common.h +++ b/examples/common_components/protocol_examples_common/include/protocol_examples_common.h @@ -31,6 +31,10 @@ extern "C" { #define EXAMPLE_NETIF_DESC_ETH "example_netif_eth" #endif +#if CONFIG_EXAMPLE_CONNECT_THREAD +#define EXAMPLE_NETIF_DESC_THREAD "example_netif_thread" +#endif + #if CONFIG_EXAMPLE_CONNECT_PPP #define EXAMPLE_NETIF_DESC_PPP "example_netif_ppp" #endif @@ -74,6 +78,9 @@ extern "C" { #elif CONFIG_EXAMPLE_CONNECT_WIFI #define EXAMPLE_INTERFACE get_example_netif_from_desc(EXAMPLE_NETIF_DESC_STA) #define get_example_netif() get_example_netif_from_desc(EXAMPLE_NETIF_DESC_STA) +#elif CONFIG_EXAMPLE_CONNECT_THREAD +#define EXAMPLE_INTERFACE get_example_netif_from_desc(EXAMPLE_NETIF_DESC_THREAD) +#define get_example_netif() get_example_netif_from_desc(EXAMPLE_NETIF_DESC_THREAD) #elif CONFIG_EXAMPLE_CONNECT_PPP #define EXAMPLE_INTERFACE get_example_netif_from_desc(EXAMPLE_NETIF_DESC_PPP) #define get_example_netif() get_example_netif_from_desc(EXAMPLE_NETIF_DESC_PPP) diff --git a/examples/common_components/protocol_examples_common/include/protocol_examples_thread_config.h b/examples/common_components/protocol_examples_common/include/protocol_examples_thread_config.h new file mode 100644 index 00000000000..306a9270cbf --- /dev/null +++ b/examples/common_components/protocol_examples_common/include/protocol_examples_thread_config.h @@ -0,0 +1,105 @@ +/* + * Thread configurations for protocol examples + * + * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Unlicense OR CC0-1.0 + */ +#pragma once + +#include + +#include + +#ifdef CONFIG_OPENTHREAD_RADIO_NATIVE +#define ESP_OPENTHREAD_DEFAULT_RADIO_CONFIG() \ + { \ + .radio_mode = RADIO_MODE_NATIVE, \ + } + +#elif defined(CONFIG_OPENTHREAD_RADIO_SPINEL_UART) +#define ESP_OPENTHREAD_DEFAULT_RADIO_CONFIG() \ + { \ + .radio_mode = RADIO_MODE_UART_RCP, \ + .radio_uart_config = \ + { \ + .port = CONFIG_EXAMPLE_THREAD_UART_PORT, \ + .uart_config = \ + { \ + .baud_rate = CONFIG_EXAMPLE_THREAD_UART_BAUD, \ + .data_bits = UART_DATA_8_BITS, \ + .parity = UART_PARITY_DISABLE, \ + .stop_bits = UART_STOP_BITS_1, \ + .flow_ctrl = UART_HW_FLOWCTRL_DISABLE, \ + .rx_flow_ctrl_thresh = 0, \ + .source_clk = UART_SCLK_DEFAULT, \ + }, \ + .rx_pin = CONFIG_EXAMPLE_THREAD_UART_RX_PIN, \ + .tx_pin = CONFIG_EXAMPLE_THREAD_UART_TX_PIN, \ + }, \ + } +#elif defined(CONFIG_OPENTHREAD_RADIO_SPINEL_SPI) +#define ESP_OPENTHREAD_DEFAULT_RADIO_CONFIG() \ + { \ + .radio_mode = RADIO_MODE_SPI_RCP, \ + .radio_spi_config = \ + { \ + .host_device = SPI2_HOST, \ + .dma_channel = 2, \ + .spi_interface = \ + { \ + .mosi_io_num = CONFIG_EXAMPLE_THREAD_SPI_MOSI_PIN, \ + .miso_io_num = CONFIG_EXAMPLE_THREAD_SPI_MISO_PIN, \ + .sclk_io_num = CONFIG_EXAMPLE_THREAD_SPI_SCLK_PIN, \ + .quadwp_io_num = -1, \ + .quadhd_io_num = -1, \ + }, \ + .spi_device = \ + { \ + .cs_ena_pretrans = 2, \ + .input_delay_ns = 100, \ + .mode = 0, \ + .clock_speed_hz = 2500 * 1000, \ + .spics_io_num = CONFIG_EXAMPLE_THREAD_SPI_CS_PIN, \ + .queue_size = 5, \ + }, \ + .intr_pin = CONFIG_EXAMPLE_THREAD_SPI_INTR_PIN, \ + }, \ + } +#endif + +#if CONFIG_OPENTHREAD_CONSOLE_TYPE_UART +#define ESP_OPENTHREAD_DEFAULT_HOST_CONFIG() \ + { \ + .host_connection_mode = HOST_CONNECTION_MODE_CLI_UART, \ + .host_uart_config = \ + { \ + .port = 0, \ + .uart_config = \ + { \ + .baud_rate = 115200, \ + .data_bits = UART_DATA_8_BITS, \ + .parity = UART_PARITY_DISABLE, \ + .stop_bits = UART_STOP_BITS_1, \ + .flow_ctrl = UART_HW_FLOWCTRL_DISABLE, \ + .rx_flow_ctrl_thresh = 0, \ + .source_clk = UART_SCLK_DEFAULT, \ + }, \ + .rx_pin = UART_PIN_NO_CHANGE, \ + .tx_pin = UART_PIN_NO_CHANGE, \ + }, \ + } +#elif CONFIG_OPENTHREAD_CONSOLE_TYPE_USB_SERIAL_JTAG +#define ESP_OPENTHREAD_DEFAULT_HOST_CONFIG() \ + { \ + .host_connection_mode = HOST_CONNECTION_MODE_CLI_USB, \ + .host_usb_config = USB_SERIAL_JTAG_DRIVER_CONFIG_DEFAULT(), \ + } +#endif + +#define ESP_OPENTHREAD_DEFAULT_PORT_CONFIG() \ + { \ + .storage_partition_name = "nvs", \ + .netif_queue_size = 10, \ + .task_queue_size = 10, \ + } diff --git a/examples/common_components/protocol_examples_common/thread_connect.c b/examples/common_components/protocol_examples_common/thread_connect.c new file mode 100644 index 00000000000..f4dae26e56f --- /dev/null +++ b/examples/common_components/protocol_examples_common/thread_connect.c @@ -0,0 +1,130 @@ +/* + * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Unlicense OR CC0-1.0 + */ + +#include "esp_err.h" +#include "esp_event.h" +#include "esp_event_base.h" +#include "esp_vfs_eventfd.h" +#include "example_common_private.h" +#include "protocol_examples_common.h" +#include "protocol_examples_thread_config.h" +#include "esp_log.h" +#include + +#include +#include +#include +#include +#include +#include +#include + +static TaskHandle_t s_ot_task_handle = NULL; +static esp_netif_t *s_openthread_netif = NULL; +static SemaphoreHandle_t s_semph_thread_attached = NULL; +static SemaphoreHandle_t s_semph_thread_set_dns_server = NULL; +static const char *TAG = "example_connect"; + +static void thread_event_handler(void* arg, esp_event_base_t event_base, int32_t event_id, + void* event_data) +{ + if (event_base == OPENTHREAD_EVENT) { + if (event_id == OPENTHREAD_EVENT_ATTACHED) { + xSemaphoreGive(s_semph_thread_attached); + } else if (event_id == OPENTHREAD_EVENT_SET_DNS_SERVER) { + xSemaphoreGive(s_semph_thread_set_dns_server); + } + } +} + +static void ot_task_worker(void *aContext) +{ + esp_openthread_platform_config_t config = { + .radio_config = ESP_OPENTHREAD_DEFAULT_RADIO_CONFIG(), + .host_config = ESP_OPENTHREAD_DEFAULT_HOST_CONFIG(), + .port_config = ESP_OPENTHREAD_DEFAULT_PORT_CONFIG(), + }; + + esp_netif_inherent_config_t esp_netif_config = ESP_NETIF_INHERENT_DEFAULT_OPENTHREAD(); + esp_netif_config.if_desc = EXAMPLE_NETIF_DESC_THREAD; + esp_netif_config_t cfg = { + .base = &esp_netif_config, + .stack = &g_esp_netif_netstack_default_openthread, + }; + s_openthread_netif = esp_netif_new(&cfg); + assert(s_openthread_netif != NULL); + + // Initialize the OpenThread stack + ESP_ERROR_CHECK(esp_openthread_init(&config)); + ESP_ERROR_CHECK(esp_netif_attach(s_openthread_netif, esp_openthread_netif_glue_init(&config))); + esp_openthread_lock_acquire(portMAX_DELAY); + (void)otLoggingSetLevel(CONFIG_LOG_DEFAULT_LEVEL); + esp_openthread_cli_init(); + esp_openthread_cli_create_task(); + otOperationalDatasetTlvs dataset; + otError error = otDatasetGetActiveTlvs(esp_openthread_get_instance(), &dataset); + if (error != OT_ERROR_NONE) { + ESP_ERROR_CHECK(esp_openthread_auto_start(NULL)); + } else { + ESP_ERROR_CHECK(esp_openthread_auto_start(&dataset)); + } + esp_openthread_lock_release(); + + // Run the main loop + esp_openthread_launch_mainloop(); + + // Clean up + esp_openthread_netif_glue_deinit(); + esp_netif_destroy(s_openthread_netif); + esp_vfs_eventfd_unregister(); + vTaskDelete(NULL); +} + +/* tear down connection, release resources */ +void example_thread_shutdown(void) +{ + vTaskDelete(s_ot_task_handle); + esp_openthread_netif_glue_deinit(); + esp_netif_destroy(s_openthread_netif); + esp_vfs_eventfd_unregister(); + vSemaphoreDelete(s_semph_thread_set_dns_server); + vSemaphoreDelete(s_semph_thread_attached); +} + +esp_err_t example_thread_connect(void) +{ + s_semph_thread_attached = xSemaphoreCreateBinary(); + if (s_semph_thread_attached == NULL) { + return ESP_ERR_NO_MEM; + } + s_semph_thread_set_dns_server = xSemaphoreCreateBinary(); + if (s_semph_thread_set_dns_server == NULL) { + vSemaphoreDelete(s_semph_thread_attached); + return ESP_ERR_NO_MEM; + } + // 4 eventfds might be used for Thread + // * netif + // * ot task queue + // * radio driver + // * border router + esp_vfs_eventfd_config_t eventfd_config = { + .max_fds = 4, + }; + esp_vfs_eventfd_register(&eventfd_config); + ESP_ERROR_CHECK(esp_event_handler_register(OPENTHREAD_EVENT, ESP_EVENT_ANY_ID, thread_event_handler, NULL)); + if (xTaskCreate(ot_task_worker, "ot_br_main", CONFIG_EXAMPLE_THREAD_TASK_STACK_SIZE, NULL, 5, &s_ot_task_handle) != pdPASS) { + vSemaphoreDelete(s_semph_thread_attached); + vSemaphoreDelete(s_semph_thread_set_dns_server); + ESP_LOGE(TAG, "Failed to create openthread task"); + return ESP_FAIL; + } + xSemaphoreTake(s_semph_thread_attached, portMAX_DELAY); + // Wait 1s for the Thread device to set its DNS server with the NAT64 prefix. + if (xSemaphoreTake(s_semph_thread_set_dns_server, 1000 / portTICK_PERIOD_MS) != pdPASS) { + ESP_LOGW(TAG, "DNS server is not set for the Thread device, might be unable to access the Internet"); + } + return ESP_OK; +} diff --git a/examples/protocols/sntp/sdkconfig.defaults.esp32h2 b/examples/protocols/sntp/sdkconfig.defaults.esp32h2 new file mode 100644 index 00000000000..326bcafa250 --- /dev/null +++ b/examples/protocols/sntp/sdkconfig.defaults.esp32h2 @@ -0,0 +1,4 @@ +CONFIG_IDF_TARGET="esp32h2" +CONFIG_MBEDTLS_CMAC_C=y +CONFIG_OPENTHREAD_ENABLED=y +CONFIG_OPENTHREAD_DNS64_CLIENT=y From 96e627d9a1ca196787cf910ca85e199bd1f5da16 Mon Sep 17 00:00:00 2001 From: Frantisek Hrbata Date: Fri, 6 Dec 2024 13:33:07 +0100 Subject: [PATCH 046/118] ci(autocomplete): add test for file autocompletion Merge Request !31081 introduced support for file autocompletion. This adds a basic test for README files autocompletion in the root directory of the esp-idf repository. Signed-off-by: Frantisek Hrbata --- .../ci/test_autocomplete/test_autocomplete.py | 63 +++++++++++++++---- 1 file changed, 51 insertions(+), 12 deletions(-) diff --git a/tools/ci/test_autocomplete/test_autocomplete.py b/tools/ci/test_autocomplete/test_autocomplete.py index 49fe24be62e..96e12e6b9ac 100755 --- a/tools/ci/test_autocomplete/test_autocomplete.py +++ b/tools/ci/test_autocomplete/test_autocomplete.py @@ -1,5 +1,5 @@ #!/usr/bin/env python -# SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD +# SPDX-FileCopyrightText: 2022-2024 Espressif Systems (Shanghai) CO LTD # SPDX-License-Identifier: Apache-2.0 import collections import os @@ -7,13 +7,49 @@ import pexpect -Test = collections.namedtuple('Test', ['name', 'term', 'pattern', 'ext']) +Test = collections.namedtuple('Test', ['name', 'shell', 'term', 'prefix', 'pattern', 'ext']) +IDF_PATH = os.environ['IDF_PATH'] -TESTS = (Test('fish', 'vt100', 'all.*app.*app-flash.*bootloader.*', 'fish'), - Test('bash', 'xterm-256color', 'all.*app.*app-flash.*bootloader.*bootloader-flash.*build-system-targets.*clean.*', 'sh'), - Test('zsh', '', 'all.*app.*app-flash.*bootloader.*bootloader-flash.*build-system-targets.*clean.*', 'sh')) - +TESTS = ( + Test('base', + 'fish', + 'vt100', + '', + 'all.*app.*app-flash.*bootloader.*', + 'fish'), + Test('base', + 'bash', + 'xterm-256color', + '', + 'all.*app.*app-flash.*bootloader.*bootloader-flash.*build-system-targets.*clean.*', + 'sh'), + Test('base', + 'zsh', + '', + '', + 'all.*app.*app-flash.*bootloader.*bootloader-flash.*build-system-targets.*clean.*', + 'sh'), + # Tests for file autocompletion + Test('file', + 'fish', + 'vt100', + f'@{IDF_PATH}/README', + '.*README.*md.*', + 'fish'), + Test('file', + 'bash', + 'xterm-256color', + f'@{IDF_PATH}/README', + '.*README.*md.*', + 'sh'), + Test('file', + 'zsh', + '', + f'@{IDF_PATH}/README', + '.*README.*md.*', + 'sh') +) # Additional positional arguments for all child.expect() calls are constant so we can rely on the order and print message # about which pattern was matched @@ -34,19 +70,22 @@ def get_fail_msg(pproc: pexpect.spawn, msg: str, index: int) -> str: class UTTest(unittest.TestCase): def test_shell(self) -> None: - idf_path = os.environ['IDF_PATH'] env = os.environ.copy() for test in TESTS: with self.subTest(): - with open(os.path.join(idf_path, f'{test.name}.out'), 'wb') as o: + with open(os.path.join(IDF_PATH, f'{test.shell}.{test.name}.out'), 'wb') as o: env['TERM'] = test.term - with pexpect.spawn(f'{test.name} -i', env=env, logfile=o, timeout=200) as pproc: - pproc.sendline(f'. {idf_path}/export.{test.ext}') + with pexpect.spawn(f'{test.shell} -i', env=env, logfile=o, timeout=200) as pproc: + if test.shell == 'bash': + # The @-argument autocomplete works reliably in bash only + # if @ is not included in COMP_WORDBREAKS. + pproc.sendline('COMP_WORDBREAKS=${COMP_WORDBREAKS//@/}') + pproc.sendline(f'. {IDF_PATH}/export.{test.ext}') i = pproc.expect(['Go to the project directory and run.*idf\\.py build', *pargs]) self.assertEqual(i, 0, get_fail_msg(pproc, 'Export was not successful!', i)) - pproc.send('idf.py \t\t') + pproc.send(f'idf.py {test.prefix}\t\t') i = pproc.expect([test.pattern, *pargs], timeout=100) - self.assertEqual(i, 0, get_fail_msg(pproc, f'Autocompletion for idf.py failed in {test.name}!', i)) + self.assertEqual(i, 0, get_fail_msg(pproc, f'Autocompletion for idf.py failed in {test.shell}!', i)) if __name__ == '__main__': From a8de16b13d18153100fea3c4d10b410167538478 Mon Sep 17 00:00:00 2001 From: Frantisek Hrbata Date: Wed, 11 Dec 2024 11:09:01 +0100 Subject: [PATCH 047/118] fix(autocomplete): handle @-argument autocompletion in bash Enable @-argument completion only if '@' is not present in COMP_WORDBREAKS. When '@' is included, the @-argument is not considered part of the completion word, causing @-argument completion to function unreliably in bash. Signed-off-by: Frantisek Hrbata --- tools/export_utils/shell_types.py | 1 + tools/idf.py | 8 +++++++- 2 files changed, 8 insertions(+), 1 deletion(-) diff --git a/tools/export_utils/shell_types.py b/tools/export_utils/shell_types.py index d2e34606723..8918eb5d8e3 100644 --- a/tools/export_utils/shell_types.py +++ b/tools/export_utils/shell_types.py @@ -126,6 +126,7 @@ def autocompletion(self) -> str: then echo "$WARNING_MSG" fi + export IDF_PY_COMP_WORDBREAKS="$COMP_WORDBREAKS" fi """) diff --git a/tools/idf.py b/tools/idf.py index 14730df1e1e..200a557d947 100755 --- a/tools/idf.py +++ b/tools/idf.py @@ -454,7 +454,13 @@ def get_command(self, ctx: click.core.Context, name: str) -> Optional[Action]: return None def shell_complete(self, ctx: click.core.Context, incomplete: str) -> List[CompletionItem]: - if incomplete.startswith('@'): + # Enable @-argument completion in bash only if @ is not present in + # COMP_WORDBREAKS. When @ is included, the @-argument is not considered + # part of the completion word, causing @-argument completion to function + # unreliably in bash. + complete_file = ('bash' not in os.environ.get('_IDF.PY_COMPLETE', '') or + '@' not in os.environ.get('IDF_PY_COMP_WORDBREAKS', '')) + if incomplete.startswith('@') and complete_file: path_prefix = incomplete[1:] candidates = glob.glob(path_prefix + '*') result = [CompletionItem(f'@{c}') for c in candidates] From c896eb611e5b3fcc3717fb6911594832fb8e20b3 Mon Sep 17 00:00:00 2001 From: laokaiyao Date: Tue, 10 Dec 2024 16:28:42 +0800 Subject: [PATCH 048/118] refactor(i2s): refactor i2s examples common dependencies Closes https://github.com/espressif/esp-idf/issues/14751 Make the common I2S dependencies as an example common component, so that to avoid slash & backslash issue on windows when use absolute include path. --- .../peripherals/i2s/i2s_basic/i2s_pdm/main/CMakeLists.txt | 4 ++-- .../peripherals/i2s/i2s_basic/i2s_pdm/main/idf_component.yml | 3 +++ .../peripherals/i2s/i2s_basic/i2s_std/main/CMakeLists.txt | 4 ++-- .../peripherals/i2s/i2s_basic/i2s_std/main/idf_component.yml | 3 +++ .../peripherals/i2s/i2s_basic/i2s_tdm/main/CMakeLists.txt | 4 ++-- .../peripherals/i2s/i2s_basic/i2s_tdm/main/idf_component.yml | 3 +++ .../i2s/i2s_codec/i2s_es7210_tdm/main/CMakeLists.txt | 4 ++-- .../i2s/i2s_codec/i2s_es7210_tdm/main/idf_component.yml | 2 ++ .../i2s/i2s_codec/i2s_es8311/main/idf_component.yml | 2 ++ examples/peripherals/i2s/i2s_examples_common/CMakeLists.txt | 2 ++ .../i2s/{common => i2s_examples_common}/format_wav.h | 0 .../i2s/{common => i2s_examples_common}/i2s_example_pins.h | 0 examples/peripherals/i2s/i2s_recorder/main/CMakeLists.txt | 4 ++-- examples/peripherals/i2s/i2s_recorder/main/idf_component.yml | 3 +++ 14 files changed, 28 insertions(+), 10 deletions(-) create mode 100644 examples/peripherals/i2s/i2s_basic/i2s_pdm/main/idf_component.yml create mode 100644 examples/peripherals/i2s/i2s_basic/i2s_std/main/idf_component.yml create mode 100644 examples/peripherals/i2s/i2s_basic/i2s_tdm/main/idf_component.yml create mode 100644 examples/peripherals/i2s/i2s_examples_common/CMakeLists.txt rename examples/peripherals/i2s/{common => i2s_examples_common}/format_wav.h (100%) rename examples/peripherals/i2s/{common => i2s_examples_common}/i2s_example_pins.h (100%) create mode 100644 examples/peripherals/i2s/i2s_recorder/main/idf_component.yml diff --git a/examples/peripherals/i2s/i2s_basic/i2s_pdm/main/CMakeLists.txt b/examples/peripherals/i2s/i2s_basic/i2s_pdm/main/CMakeLists.txt index 09146f7753a..e7ac2619216 100644 --- a/examples/peripherals/i2s/i2s_basic/i2s_pdm/main/CMakeLists.txt +++ b/examples/peripherals/i2s/i2s_basic/i2s_pdm/main/CMakeLists.txt @@ -9,5 +9,5 @@ if(CONFIG_SOC_I2S_SUPPORTS_PDM_RX AND CONFIG_EXAMPLE_PDM_RX) endif() idf_component_register(SRCS "${srcs}" - PRIV_REQUIRES esp_driver_i2s esp_driver_gpio - INCLUDE_DIRS "." "$ENV{IDF_PATH}/examples/peripherals/i2s/common") + PRIV_REQUIRES esp_driver_i2s esp_driver_gpio i2s_examples_common + INCLUDE_DIRS ".") diff --git a/examples/peripherals/i2s/i2s_basic/i2s_pdm/main/idf_component.yml b/examples/peripherals/i2s/i2s_basic/i2s_pdm/main/idf_component.yml new file mode 100644 index 00000000000..804fe8e427e --- /dev/null +++ b/examples/peripherals/i2s/i2s_basic/i2s_pdm/main/idf_component.yml @@ -0,0 +1,3 @@ +dependencies: + i2s_examples_common: + path: ${IDF_PATH}/examples/peripherals/i2s/i2s_examples_common diff --git a/examples/peripherals/i2s/i2s_basic/i2s_std/main/CMakeLists.txt b/examples/peripherals/i2s/i2s_basic/i2s_std/main/CMakeLists.txt index c5b175d06ab..359c4a75dd4 100644 --- a/examples/peripherals/i2s/i2s_basic/i2s_std/main/CMakeLists.txt +++ b/examples/peripherals/i2s/i2s_basic/i2s_std/main/CMakeLists.txt @@ -1,3 +1,3 @@ idf_component_register(SRCS "i2s_std_example_main.c" - PRIV_REQUIRES esp_driver_i2s esp_driver_gpio - INCLUDE_DIRS "." "$ENV{IDF_PATH}/examples/peripherals/i2s/common") + PRIV_REQUIRES esp_driver_i2s esp_driver_gpio i2s_examples_common + INCLUDE_DIRS ".") diff --git a/examples/peripherals/i2s/i2s_basic/i2s_std/main/idf_component.yml b/examples/peripherals/i2s/i2s_basic/i2s_std/main/idf_component.yml new file mode 100644 index 00000000000..804fe8e427e --- /dev/null +++ b/examples/peripherals/i2s/i2s_basic/i2s_std/main/idf_component.yml @@ -0,0 +1,3 @@ +dependencies: + i2s_examples_common: + path: ${IDF_PATH}/examples/peripherals/i2s/i2s_examples_common diff --git a/examples/peripherals/i2s/i2s_basic/i2s_tdm/main/CMakeLists.txt b/examples/peripherals/i2s/i2s_basic/i2s_tdm/main/CMakeLists.txt index 8f5c82b4631..0eee02cd787 100644 --- a/examples/peripherals/i2s/i2s_basic/i2s_tdm/main/CMakeLists.txt +++ b/examples/peripherals/i2s/i2s_basic/i2s_tdm/main/CMakeLists.txt @@ -1,3 +1,3 @@ idf_component_register(SRCS "i2s_tdm_example_main.c" - PRIV_REQUIRES esp_driver_i2s esp_driver_gpio - INCLUDE_DIRS "." "$ENV{IDF_PATH}/examples/peripherals/i2s/common") + PRIV_REQUIRES esp_driver_i2s esp_driver_gpio i2s_examples_common + INCLUDE_DIRS ".") diff --git a/examples/peripherals/i2s/i2s_basic/i2s_tdm/main/idf_component.yml b/examples/peripherals/i2s/i2s_basic/i2s_tdm/main/idf_component.yml new file mode 100644 index 00000000000..804fe8e427e --- /dev/null +++ b/examples/peripherals/i2s/i2s_basic/i2s_tdm/main/idf_component.yml @@ -0,0 +1,3 @@ +dependencies: + i2s_examples_common: + path: ${IDF_PATH}/examples/peripherals/i2s/i2s_examples_common diff --git a/examples/peripherals/i2s/i2s_codec/i2s_es7210_tdm/main/CMakeLists.txt b/examples/peripherals/i2s/i2s_codec/i2s_es7210_tdm/main/CMakeLists.txt index 0241da8899b..c90803d430e 100644 --- a/examples/peripherals/i2s/i2s_codec/i2s_es7210_tdm/main/CMakeLists.txt +++ b/examples/peripherals/i2s/i2s_codec/i2s_es7210_tdm/main/CMakeLists.txt @@ -1,4 +1,4 @@ idf_component_register(SRCS "i2s_es7210_record_example.c" - PRIV_REQUIRES esp_driver_i2s esp_driver_gpio fatfs - INCLUDE_DIRS "$ENV{IDF_PATH}/examples/peripherals/i2s/common" + PRIV_REQUIRES esp_driver_i2s esp_driver_gpio fatfs i2s_examples_common + INCLUDE_DIRS ) diff --git a/examples/peripherals/i2s/i2s_codec/i2s_es7210_tdm/main/idf_component.yml b/examples/peripherals/i2s/i2s_codec/i2s_es7210_tdm/main/idf_component.yml index da0e4186c83..287056bd515 100644 --- a/examples/peripherals/i2s/i2s_codec/i2s_es7210_tdm/main/idf_component.yml +++ b/examples/peripherals/i2s/i2s_codec/i2s_es7210_tdm/main/idf_component.yml @@ -15,3 +15,5 @@ dependencies: # # `public` flag doesn't have an effect dependencies of the `main` component. # # All dependencies of `main` are public by default. # public: true + i2s_examples_common: + path: ${IDF_PATH}/examples/peripherals/i2s/i2s_examples_common diff --git a/examples/peripherals/i2s/i2s_codec/i2s_es8311/main/idf_component.yml b/examples/peripherals/i2s/i2s_codec/i2s_es8311/main/idf_component.yml index ca449b2d626..2091fa5dddf 100644 --- a/examples/peripherals/i2s/i2s_codec/i2s_es8311/main/idf_component.yml +++ b/examples/peripherals/i2s/i2s_codec/i2s_es8311/main/idf_component.yml @@ -16,3 +16,5 @@ dependencies: # version: "^1" # rules: # - if: "target in [esp32s3]" + i2s_examples_common: + path: ${IDF_PATH}/examples/peripherals/i2s/i2s_examples_common diff --git a/examples/peripherals/i2s/i2s_examples_common/CMakeLists.txt b/examples/peripherals/i2s/i2s_examples_common/CMakeLists.txt new file mode 100644 index 00000000000..404dbefdc4a --- /dev/null +++ b/examples/peripherals/i2s/i2s_examples_common/CMakeLists.txt @@ -0,0 +1,2 @@ +# register I2S common dependencies as a component +idf_component_register(INCLUDE_DIRS ".") diff --git a/examples/peripherals/i2s/common/format_wav.h b/examples/peripherals/i2s/i2s_examples_common/format_wav.h similarity index 100% rename from examples/peripherals/i2s/common/format_wav.h rename to examples/peripherals/i2s/i2s_examples_common/format_wav.h diff --git a/examples/peripherals/i2s/common/i2s_example_pins.h b/examples/peripherals/i2s/i2s_examples_common/i2s_example_pins.h similarity index 100% rename from examples/peripherals/i2s/common/i2s_example_pins.h rename to examples/peripherals/i2s/i2s_examples_common/i2s_example_pins.h diff --git a/examples/peripherals/i2s/i2s_recorder/main/CMakeLists.txt b/examples/peripherals/i2s/i2s_recorder/main/CMakeLists.txt index 805f8fee955..0776d102b50 100644 --- a/examples/peripherals/i2s/i2s_recorder/main/CMakeLists.txt +++ b/examples/peripherals/i2s/i2s_recorder/main/CMakeLists.txt @@ -1,3 +1,3 @@ idf_component_register(SRCS "i2s_recorder_main.c" - PRIV_REQUIRES esp_driver_i2s fatfs - INCLUDE_DIRS "$ENV{IDF_PATH}/examples/peripherals/i2s/common") + PRIV_REQUIRES esp_driver_i2s fatfs i2s_examples_common + INCLUDE_DIRS) diff --git a/examples/peripherals/i2s/i2s_recorder/main/idf_component.yml b/examples/peripherals/i2s/i2s_recorder/main/idf_component.yml new file mode 100644 index 00000000000..804fe8e427e --- /dev/null +++ b/examples/peripherals/i2s/i2s_recorder/main/idf_component.yml @@ -0,0 +1,3 @@ +dependencies: + i2s_examples_common: + path: ${IDF_PATH}/examples/peripherals/i2s/i2s_examples_common From b48b43880af220683f81d54c7fcfbd825fd7d63e Mon Sep 17 00:00:00 2001 From: laokaiyao Date: Tue, 10 Dec 2024 10:43:48 +0800 Subject: [PATCH 049/118] feat(ana_cmpr): support analog comparator on C5 --- .../test_apps/analog_comparator/README.md | 4 +- .../analog_comparator/pytest_ana_cmpr.py | 1 + .../hal/esp32c5/include/hal/ana_cmpr_ll.h | 169 ++++++++++++++++++ components/soc/esp32c5/ana_cmpr_periph.c | 26 +++ .../esp32c5/include/soc/Kconfig.soc_caps.in | 16 ++ .../esp32c5/include/soc/ana_cmpr_channel.h | 10 ++ .../soc/esp32c5/include/soc/ana_cmpr_struct.h | 36 ++++ .../soc/esp32c5/include/soc/clk_tree_defs.h | 17 ++ components/soc/esp32c5/include/soc/soc_caps.h | 6 + docs/docs_not_updated/esp32c5.txt | 1 - .../en/api-reference/peripherals/ana_cmpr.rst | 4 +- .../api-reference/peripherals/ana_cmpr.rst | 4 +- .../peripherals/analog_comparator/README.md | 4 +- .../pytest_ana_cmpr_example.py | 1 + 14 files changed, 290 insertions(+), 9 deletions(-) create mode 100644 components/hal/esp32c5/include/hal/ana_cmpr_ll.h create mode 100644 components/soc/esp32c5/ana_cmpr_periph.c create mode 100644 components/soc/esp32c5/include/soc/ana_cmpr_channel.h create mode 100644 components/soc/esp32c5/include/soc/ana_cmpr_struct.h diff --git a/components/esp_driver_ana_cmpr/test_apps/analog_comparator/README.md b/components/esp_driver_ana_cmpr/test_apps/analog_comparator/README.md index 522583ae5b4..fcf05f5c01d 100644 --- a/components/esp_driver_ana_cmpr/test_apps/analog_comparator/README.md +++ b/components/esp_driver_ana_cmpr/test_apps/analog_comparator/README.md @@ -1,2 +1,2 @@ -| Supported Targets | ESP32-C61 | ESP32-H2 | ESP32-P4 | -| ----------------- | --------- | -------- | -------- | +| Supported Targets | ESP32-C5 | ESP32-C61 | ESP32-H2 | ESP32-P4 | +| ----------------- | -------- | --------- | -------- | -------- | diff --git a/components/esp_driver_ana_cmpr/test_apps/analog_comparator/pytest_ana_cmpr.py b/components/esp_driver_ana_cmpr/test_apps/analog_comparator/pytest_ana_cmpr.py index 4bbc66b8a1d..d9eeb38699d 100644 --- a/components/esp_driver_ana_cmpr/test_apps/analog_comparator/pytest_ana_cmpr.py +++ b/components/esp_driver_ana_cmpr/test_apps/analog_comparator/pytest_ana_cmpr.py @@ -6,6 +6,7 @@ @pytest.mark.esp32h2 @pytest.mark.esp32p4 +@pytest.mark.esp32c5 @pytest.mark.esp32c61 @pytest.mark.generic @pytest.mark.parametrize( diff --git a/components/hal/esp32c5/include/hal/ana_cmpr_ll.h b/components/hal/esp32c5/include/hal/ana_cmpr_ll.h new file mode 100644 index 00000000000..73e99c56717 --- /dev/null +++ b/components/hal/esp32c5/include/hal/ana_cmpr_ll.h @@ -0,0 +1,169 @@ +/* + * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#pragma once + +#include +#include "hal/misc.h" +#include "hal/assert.h" +#include "soc/ana_cmpr_struct.h" +#include "soc/soc_etm_source.h" + +#ifdef __cplusplus +extern "C" { +#endif + +#define ANALOG_CMPR_LL_GET_HW(unit) (&ANALOG_CMPR[unit]) +#define ANALOG_CMPR_LL_GET_UNIT(hw) (0) +#define ANALOG_CMPR_LL_EVENT_CROSS (1 << 0) + +#define ANALOG_CMPR_LL_NEG_CROSS_MASK(unit) (1UL << ((int)unit * 3)) +#define ANALOG_CMPR_LL_POS_CROSS_MASK(unit) (1UL << ((int)unit * 3 + 1)) + +#define ANALOG_CMPR_LL_ETM_SOURCE(unit, type) (GPIO_EVT_ZERO_DET_POS0 + (unit) * 2 + (type)) + + +/** + * @brief Enable analog comparator + * + * @param hw Analog comparator register base address + * @param en True to enable, False to disable + */ +static inline void analog_cmpr_ll_enable(analog_cmpr_dev_t *hw, bool en) +{ + hw->pad_comp_config->xpd_comp_0 = en; +} + +/** + * @brief Set the voltage of the internal reference + * + * @param hw Analog comparator register base address + * @param volt_level The voltage level of the internal reference, range [0.0V, 0.7VDD], step 0.1VDD + */ +__attribute__((always_inline)) +static inline void analog_cmpr_ll_set_internal_ref_voltage(analog_cmpr_dev_t *hw, uint32_t volt_level) +{ + hw->pad_comp_config->dref_comp_0 = volt_level; +} + +/** + * @brief Get the voltage of the internal reference + * + * @param hw Analog comparator register base address + * @return The voltage of the internal reference + */ +static inline float analog_cmpr_ll_get_internal_ref_voltage(analog_cmpr_dev_t *hw) +{ + return hw->pad_comp_config->dref_comp_0 * 0.1F; +} + +/** + * @brief The reference voltage comes from internal or external + * + * @note Also see `analog_cmpr_ll_set_internal_ref_voltage` to use the internal reference voltage + * + * @param hw Analog comparator register base address + * @param ref_src reference source, 0 for internal, 1 for external GPIO pad (GPIO10) + */ +static inline void analog_cmpr_ll_set_ref_source(analog_cmpr_dev_t *hw, uint32_t ref_src) +{ + hw->pad_comp_config->mode_comp_0 = ref_src; +} + +/** + * @brief Get the interrupt mask by trigger type + * + * @param hw Analog comparator register base address + * @param type The type of cross interrupt + * - 0: disable interrupt + * - 1: enable positive cross interrupt (input analog goes from low to high and across the reference voltage) + * - 2: enable negative cross interrupt (input analog goes from high to low and across the reference voltage) + * - 3: enable any positive or negative cross interrupt + * @return interrupt mask + */ +__attribute__((always_inline)) +static inline uint32_t analog_cmpr_ll_get_intr_mask_by_type(analog_cmpr_dev_t *hw, uint8_t type) +{ + uint32_t unit = ANALOG_CMPR_LL_GET_UNIT(hw); + uint32_t mask = 0; + if (type & 0x01) { + mask |= ANALOG_CMPR_LL_POS_CROSS_MASK(unit); + } + if (type & 0x02) { + mask |= ANALOG_CMPR_LL_NEG_CROSS_MASK(unit); + } + return mask; +} + +/** + * @brief Set the debounce cycle for the cross detection + * + * @note When the comparator detects a cross, it will wait for the debounce cycle to make sure the cross is stable. + * + * @param hw Analog comparator register base address + * @param cycle The debounce cycle + */ +__attribute__((always_inline)) +static inline void analog_cmpr_ll_set_debounce_cycle(analog_cmpr_dev_t *hw, uint32_t cycle) +{ + hw->pad_comp_filter->zero_det_filter_cnt_0 = cycle; +} + +/** + * @brief Enable comparator interrupt + * + * @param hw Analog comparator register base address + * @param mask Interrupt mask + * @param enable True to enable, False to disable + */ +static inline void analog_cmpr_ll_enable_intr(analog_cmpr_dev_t *hw, uint32_t mask, bool enable) +{ + uint32_t val = hw->int_ena->val; + if (enable) { + val |= mask; + } else { + val &= ~mask; + } + hw->int_ena->val = val; +} + +/** + * @brief Get comparator interrupt status + * + * @param hw Analog comparator register base address + */ +__attribute__((always_inline)) +static inline uint32_t analog_cmpr_ll_get_intr_status(analog_cmpr_dev_t *hw) +{ + return hw->int_st->val; +} + +/** + * @brief Clear comparator interrupt status + * + * @param hw Analog comparator register base address + * @param mask Interrupt status word + */ +__attribute__((always_inline)) +static inline void analog_cmpr_ll_clear_intr(analog_cmpr_dev_t *hw, uint32_t mask) +{ + hw->int_clr->val = mask; +} + +/** + * @brief Get the interrupt status register address + * + * @param hw Analog comparator register base address + * @return The interrupt status register address + */ +static inline volatile void *analog_cmpr_ll_get_intr_status_reg(analog_cmpr_dev_t *hw) +{ + return hw->int_st; +} + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32c5/ana_cmpr_periph.c b/components/soc/esp32c5/ana_cmpr_periph.c new file mode 100644 index 00000000000..eac077a33f7 --- /dev/null +++ b/components/soc/esp32c5/ana_cmpr_periph.c @@ -0,0 +1,26 @@ +/* + * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include "soc/ana_cmpr_periph.h" +#include "soc/ana_cmpr_struct.h" + +const ana_cmpr_periph_t ana_cmpr_periph[SOC_ANA_CMPR_NUM] = { + [0] = { + .src_gpio = ANA_CMPR0_SRC_GPIO, + .ext_ref_gpio = ANA_CMPR0_EXT_REF_GPIO, + .intr_src = ETS_GPIO_NMI_SOURCE, + }, +}; + +analog_cmpr_dev_t ANALOG_CMPR[SOC_ANA_CMPR_NUM] = { + [0] = { + .pad_comp_config = &GPIO_EXT.pad_comp_config_0, + .pad_comp_filter = &GPIO_EXT.pad_comp_filter_0, + .int_st = &GPIO_EXT.int_st, + .int_ena = &GPIO_EXT.int_ena, + .int_clr = &GPIO_EXT.int_clr, + }, +}; diff --git a/components/soc/esp32c5/include/soc/Kconfig.soc_caps.in b/components/soc/esp32c5/include/soc/Kconfig.soc_caps.in index 7340e9d4c83..c4c928d957e 100644 --- a/components/soc/esp32c5/include/soc/Kconfig.soc_caps.in +++ b/components/soc/esp32c5/include/soc/Kconfig.soc_caps.in @@ -7,6 +7,10 @@ config SOC_ADC_SUPPORTED bool default y +config SOC_ANA_CMPR_SUPPORTED + bool + default y + config SOC_DEDICATED_GPIO_SUPPORTED bool default y @@ -571,6 +575,18 @@ config SOC_DEDIC_PERIPH_ALWAYS_ENABLE bool default y +config SOC_ANA_CMPR_NUM + int + default 1 + +config SOC_ANA_CMPR_CAN_DISTINGUISH_EDGE + bool + default y + +config SOC_ANA_CMPR_SUPPORT_ETM + bool + default y + config SOC_I2C_NUM int default 2 diff --git a/components/soc/esp32c5/include/soc/ana_cmpr_channel.h b/components/soc/esp32c5/include/soc/ana_cmpr_channel.h new file mode 100644 index 00000000000..f51632ab0f5 --- /dev/null +++ b/components/soc/esp32c5/include/soc/ana_cmpr_channel.h @@ -0,0 +1,10 @@ +/* + * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#pragma once + +#define ANA_CMPR0_EXT_REF_GPIO 8 /*!< The GPIO that can be used as external reference voltage */ +#define ANA_CMPR0_SRC_GPIO 9 /*!< The GPIO that used for inputting the source signal to compare */ diff --git a/components/soc/esp32c5/include/soc/ana_cmpr_struct.h b/components/soc/esp32c5/include/soc/ana_cmpr_struct.h new file mode 100644 index 00000000000..ef3fbe3824e --- /dev/null +++ b/components/soc/esp32c5/include/soc/ana_cmpr_struct.h @@ -0,0 +1,36 @@ +/** + * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/* NOTE: this file is created manually for compatibility */ + +#pragma once + +#include +#include "soc/gpio_ext_struct.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @brief The Analog Comparator Device struct + * @note The field in it are register pointers, which point to the physical address + * of the corresponding configuration register + * @note see 'ana_cmpr_periph.c' for the device instance + */ +typedef struct { + volatile gpio_ext_pad_comp_config_0_reg_t *pad_comp_config; + volatile gpio_ext_pad_comp_filter_0_reg_t *pad_comp_filter; + volatile gpio_ext_int_st_reg_t *int_st; + volatile gpio_ext_int_ena_reg_t *int_ena; + volatile gpio_ext_int_clr_reg_t *int_clr; +} analog_cmpr_dev_t; + +extern analog_cmpr_dev_t ANALOG_CMPR[1]; + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32c5/include/soc/clk_tree_defs.h b/components/soc/esp32c5/include/soc/clk_tree_defs.h index e3510ca9b80..759202ee2c2 100644 --- a/components/soc/esp32c5/include/soc/clk_tree_defs.h +++ b/components/soc/esp32c5/include/soc/clk_tree_defs.h @@ -402,6 +402,23 @@ typedef enum { GLITCH_FILTER_CLK_SRC_DEFAULT = SOC_MOD_CLK_PLL_F80M, /*!< Select PLL_F80M clock as the default clock choice */ } soc_periph_glitch_filter_clk_src_t; +///////////////////////////////////////////////////Analog Comparator//////////////////////////////////////////////////// + +/** + * @brief Array initializer for all supported clock sources of Analog Comparator + */ +#define SOC_ANA_CMPR_CLKS {SOC_MOD_CLK_PLL_F80M, SOC_MOD_CLK_RC_FAST, SOC_MOD_CLK_XTAL} + +/** + * @brief Analog Comparator clock source + */ +typedef enum { + ANA_CMPR_CLK_SRC_XTAL = SOC_MOD_CLK_XTAL, /*!< Select XTAL clock as the source clock */ + ANA_CMPR_CLK_SRC_RC_FAST = SOC_MOD_CLK_RC_FAST, /*!< Select RC_FAST clock as the source clock */ + ANA_CMPR_CLK_SRC_PLL_F80M = SOC_MOD_CLK_PLL_F80M, /*!< Select PLL_F80M clock as the source clock */ + ANA_CMPR_CLK_SRC_DEFAULT = SOC_MOD_CLK_PLL_F80M, /*!< Select PLL_F80M as the default clock choice */ +} soc_periph_ana_cmpr_clk_src_t; + //////////////////////////////////////////////////TWAI////////////////////////////////////////////////////////////////// /** diff --git a/components/soc/esp32c5/include/soc/soc_caps.h b/components/soc/esp32c5/include/soc/soc_caps.h index b0f70abec79..62b0c0af0d8 100644 --- a/components/soc/esp32c5/include/soc/soc_caps.h +++ b/components/soc/esp32c5/include/soc/soc_caps.h @@ -18,6 +18,7 @@ /*-------------------------- COMMON CAPS ---------------------------------------*/ #define SOC_ADC_SUPPORTED 1 +#define SOC_ANA_CMPR_SUPPORTED 1 #define SOC_DEDICATED_GPIO_SUPPORTED 1 #define SOC_UART_SUPPORTED 1 #define SOC_GDMA_SUPPORTED 1 @@ -251,6 +252,11 @@ #define SOC_DEDIC_GPIO_IN_CHANNELS_NUM (8) /*!< 8 inward channels on each CPU core */ #define SOC_DEDIC_PERIPH_ALWAYS_ENABLE (1) /*!< The dedicated GPIO (a.k.a. fast GPIO) is featured by some customized CPU instructions, which is always enabled */ +/*------------------------- Analog Comparator CAPS ---------------------------*/ +#define SOC_ANA_CMPR_NUM (1U) +#define SOC_ANA_CMPR_CAN_DISTINGUISH_EDGE (1) // Support positive/negative/any cross interrupt +#define SOC_ANA_CMPR_SUPPORT_ETM (1) + /*-------------------------- I2C CAPS ----------------------------------------*/ #define SOC_I2C_NUM (2U) #define SOC_HP_I2C_NUM (1U) diff --git a/docs/docs_not_updated/esp32c5.txt b/docs/docs_not_updated/esp32c5.txt index 7a8cf3a65db..908fdf5f517 100644 --- a/docs/docs_not_updated/esp32c5.txt +++ b/docs/docs_not_updated/esp32c5.txt @@ -27,7 +27,6 @@ api-reference/peripherals/twai.rst api-reference/peripherals/gptimer.rst api-reference/peripherals/touch_element.rst api-reference/peripherals/lcd.rst -api-reference/peripherals/ana_cmpr.rst api-reference/peripherals/spi_features.rst api-reference/peripherals/touch_pad.rst api-reference/peripherals/adc_calibration.rst diff --git a/docs/en/api-reference/peripherals/ana_cmpr.rst b/docs/en/api-reference/peripherals/ana_cmpr.rst index a8954edbbcd..49c23db4fe4 100644 --- a/docs/en/api-reference/peripherals/ana_cmpr.rst +++ b/docs/en/api-reference/peripherals/ana_cmpr.rst @@ -3,8 +3,8 @@ Analog Comparator :link_to_translation:`zh_CN:[中文]` -{IDF_TARGET_ANA_CMPR_SRC_CHAN0: default="NOT UPDATED", esp32h2="GPIO11", esp32p4="GPIO52", esp32c61="GPIO9"} -{IDF_TARGET_ANA_CMPR_EXT_REF_CHAN0: default="NOT UPDATED", esp32h2="GPIO10", esp32p4="GPIO51", esp32c61="GPIO8"} +{IDF_TARGET_ANA_CMPR_SRC_CHAN0: default="NOT UPDATED", esp32h2="GPIO11", esp32p4="GPIO52", esp32c5="GPIO9", esp32c61="GPIO9"} +{IDF_TARGET_ANA_CMPR_EXT_REF_CHAN0: default="NOT UPDATED", esp32h2="GPIO10", esp32p4="GPIO51", esp32c5="GPIO8", esp32c61="GPIO8"} {IDF_TARGET_ANA_CMPR_SRC_CHAN1: default="NOT UPDATED", esp32p4="GPIO54"} {IDF_TARGET_ANA_CMPR_EXT_REF_CHAN1: default="NOT UPDATED", esp32p4="GPIO53"} diff --git a/docs/zh_CN/api-reference/peripherals/ana_cmpr.rst b/docs/zh_CN/api-reference/peripherals/ana_cmpr.rst index d529b3f2cb0..1f7f776ef6b 100644 --- a/docs/zh_CN/api-reference/peripherals/ana_cmpr.rst +++ b/docs/zh_CN/api-reference/peripherals/ana_cmpr.rst @@ -3,8 +3,8 @@ :link_to_translation:`en:[English]` -{IDF_TARGET_ANA_CMPR_SRC_CHAN0: default="未更新", esp32h2="GPIO11", esp32p4="GPIO52", esp32c61="GPIO9"} -{IDF_TARGET_ANA_CMPR_EXT_REF_CHAN0: default="未更新", esp32h2="GPIO10", esp32p4="GPIO51", esp32c61="GPIO8"} +{IDF_TARGET_ANA_CMPR_SRC_CHAN0: default="未更新", esp32h2="GPIO11", esp32p4="GPIO52", esp32c5="GPIO9", esp32c61="GPIO9"} +{IDF_TARGET_ANA_CMPR_EXT_REF_CHAN0: default="未更新", esp32h2="GPIO10", esp32p4="GPIO51", esp32c5="GPIO8", esp32c61="GPIO8"} {IDF_TARGET_ANA_CMPR_SRC_CHAN1: default="未更新", esp32p4="GPIO54"} {IDF_TARGET_ANA_CMPR_EXT_REF_CHAN1: default="未更新", esp32p4="GPIO53"} diff --git a/examples/peripherals/analog_comparator/README.md b/examples/peripherals/analog_comparator/README.md index eb664cf6daf..c0f5fb6a77e 100644 --- a/examples/peripherals/analog_comparator/README.md +++ b/examples/peripherals/analog_comparator/README.md @@ -1,5 +1,5 @@ -| Supported Targets | ESP32-C61 | ESP32-H2 | ESP32-P4 | -| ----------------- | --------- | -------- | -------- | +| Supported Targets | ESP32-C5 | ESP32-C61 | ESP32-H2 | ESP32-P4 | +| ----------------- | -------- | --------- | -------- | -------- | # Analog Comparator Example diff --git a/examples/peripherals/analog_comparator/pytest_ana_cmpr_example.py b/examples/peripherals/analog_comparator/pytest_ana_cmpr_example.py index 1f21a6f845b..e9196eb6f86 100644 --- a/examples/peripherals/analog_comparator/pytest_ana_cmpr_example.py +++ b/examples/peripherals/analog_comparator/pytest_ana_cmpr_example.py @@ -6,6 +6,7 @@ @pytest.mark.esp32h2 @pytest.mark.esp32p4 +@pytest.mark.esp32c5 @pytest.mark.esp32c61 @pytest.mark.generic @pytest.mark.parametrize( From f731a536949222e45e86694d4c55f31e8f972b54 Mon Sep 17 00:00:00 2001 From: laokaiyao Date: Tue, 10 Dec 2024 12:05:46 +0800 Subject: [PATCH 050/118] refactor(ana_cmpr): use enum types in ll --- .../include/driver/ana_cmpr_types.h | 29 +------------ .../hal/esp32c5/include/hal/ana_cmpr_ll.h | 5 ++- .../hal/esp32c61/include/hal/ana_cmpr_ll.h | 5 ++- .../hal/esp32h2/include/hal/ana_cmpr_ll.h | 7 ++-- .../hal/esp32p4/include/hal/ana_cmpr_ll.h | 7 ++-- components/hal/include/hal/ana_cmpr_types.h | 41 +++++++++++++++++++ components/soc/esp32c5/ana_cmpr_periph.c | 2 +- .../soc/esp32c5/include/soc/interrupts.h | 2 +- components/soc/esp32c5/interrupts.c | 2 +- 9 files changed, 60 insertions(+), 40 deletions(-) create mode 100644 components/hal/include/hal/ana_cmpr_types.h diff --git a/components/esp_driver_ana_cmpr/include/driver/ana_cmpr_types.h b/components/esp_driver_ana_cmpr/include/driver/ana_cmpr_types.h index 19747433630..497ba310a9e 100644 --- a/components/esp_driver_ana_cmpr/include/driver/ana_cmpr_types.h +++ b/components/esp_driver_ana_cmpr/include/driver/ana_cmpr_types.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2023-2024 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -9,6 +9,7 @@ #include #include "soc/soc_caps.h" #include "soc/clk_tree_defs.h" +#include "hal/ana_cmpr_types.h" #ifdef __cplusplus extern "C" { @@ -40,32 +41,6 @@ typedef enum { ANA_CMPR_EXT_REF_CHAN, /*!< Analog Comparator external reference channel, which is used as the reference signal */ } ana_cmpr_channel_type_t; -/** - * @brief Analog comparator interrupt type - * - */ -typedef enum { - ANA_CMPR_CROSS_DISABLE, /*!< Disable the cross event interrupt */ - ANA_CMPR_CROSS_POS, /*!< Positive cross can trigger event interrupt */ - ANA_CMPR_CROSS_NEG, /*!< Negative cross can trigger event interrupt */ - ANA_CMPR_CROSS_ANY, /*!< Any cross can trigger event interrupt */ -} ana_cmpr_cross_type_t; - -/** - * @brief Analog comparator internal reference voltage - * - */ -typedef enum { - ANA_CMPR_REF_VOLT_0_PCT_VDD, /*!< Internal reference voltage equals to 0% VDD */ - ANA_CMPR_REF_VOLT_10_PCT_VDD, /*!< Internal reference voltage equals to 10% VDD */ - ANA_CMPR_REF_VOLT_20_PCT_VDD, /*!< Internal reference voltage equals to 20% VDD */ - ANA_CMPR_REF_VOLT_30_PCT_VDD, /*!< Internal reference voltage equals to 30% VDD */ - ANA_CMPR_REF_VOLT_40_PCT_VDD, /*!< Internal reference voltage equals to 40% VDD */ - ANA_CMPR_REF_VOLT_50_PCT_VDD, /*!< Internal reference voltage equals to 50% VDD */ - ANA_CMPR_REF_VOLT_60_PCT_VDD, /*!< Internal reference voltage equals to 60% VDD */ - ANA_CMPR_REF_VOLT_70_PCT_VDD, /*!< Internal reference voltage equals to 70% VDD */ -} ana_cmpr_ref_voltage_t; - /** * @brief Analog comparator unit handle * diff --git a/components/hal/esp32c5/include/hal/ana_cmpr_ll.h b/components/hal/esp32c5/include/hal/ana_cmpr_ll.h index 73e99c56717..24326ebb853 100644 --- a/components/hal/esp32c5/include/hal/ana_cmpr_ll.h +++ b/components/hal/esp32c5/include/hal/ana_cmpr_ll.h @@ -9,6 +9,7 @@ #include #include "hal/misc.h" #include "hal/assert.h" +#include "hal/ana_cmpr_types.h" #include "soc/ana_cmpr_struct.h" #include "soc/soc_etm_source.h" @@ -68,7 +69,7 @@ static inline float analog_cmpr_ll_get_internal_ref_voltage(analog_cmpr_dev_t *h * @param hw Analog comparator register base address * @param ref_src reference source, 0 for internal, 1 for external GPIO pad (GPIO10) */ -static inline void analog_cmpr_ll_set_ref_source(analog_cmpr_dev_t *hw, uint32_t ref_src) +static inline void analog_cmpr_ll_set_ref_source(analog_cmpr_dev_t *hw, ana_cmpr_ref_voltage_t ref_src) { hw->pad_comp_config->mode_comp_0 = ref_src; } @@ -85,7 +86,7 @@ static inline void analog_cmpr_ll_set_ref_source(analog_cmpr_dev_t *hw, uint32_t * @return interrupt mask */ __attribute__((always_inline)) -static inline uint32_t analog_cmpr_ll_get_intr_mask_by_type(analog_cmpr_dev_t *hw, uint8_t type) +static inline uint32_t analog_cmpr_ll_get_intr_mask_by_type(analog_cmpr_dev_t *hw, ana_cmpr_cross_type_t type) { uint32_t unit = ANALOG_CMPR_LL_GET_UNIT(hw); uint32_t mask = 0; diff --git a/components/hal/esp32c61/include/hal/ana_cmpr_ll.h b/components/hal/esp32c61/include/hal/ana_cmpr_ll.h index 73e99c56717..24326ebb853 100644 --- a/components/hal/esp32c61/include/hal/ana_cmpr_ll.h +++ b/components/hal/esp32c61/include/hal/ana_cmpr_ll.h @@ -9,6 +9,7 @@ #include #include "hal/misc.h" #include "hal/assert.h" +#include "hal/ana_cmpr_types.h" #include "soc/ana_cmpr_struct.h" #include "soc/soc_etm_source.h" @@ -68,7 +69,7 @@ static inline float analog_cmpr_ll_get_internal_ref_voltage(analog_cmpr_dev_t *h * @param hw Analog comparator register base address * @param ref_src reference source, 0 for internal, 1 for external GPIO pad (GPIO10) */ -static inline void analog_cmpr_ll_set_ref_source(analog_cmpr_dev_t *hw, uint32_t ref_src) +static inline void analog_cmpr_ll_set_ref_source(analog_cmpr_dev_t *hw, ana_cmpr_ref_voltage_t ref_src) { hw->pad_comp_config->mode_comp_0 = ref_src; } @@ -85,7 +86,7 @@ static inline void analog_cmpr_ll_set_ref_source(analog_cmpr_dev_t *hw, uint32_t * @return interrupt mask */ __attribute__((always_inline)) -static inline uint32_t analog_cmpr_ll_get_intr_mask_by_type(analog_cmpr_dev_t *hw, uint8_t type) +static inline uint32_t analog_cmpr_ll_get_intr_mask_by_type(analog_cmpr_dev_t *hw, ana_cmpr_cross_type_t type) { uint32_t unit = ANALOG_CMPR_LL_GET_UNIT(hw); uint32_t mask = 0; diff --git a/components/hal/esp32h2/include/hal/ana_cmpr_ll.h b/components/hal/esp32h2/include/hal/ana_cmpr_ll.h index c75fc5ddc5b..3ac8787c1fa 100644 --- a/components/hal/esp32h2/include/hal/ana_cmpr_ll.h +++ b/components/hal/esp32h2/include/hal/ana_cmpr_ll.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2023-2024 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -9,6 +9,7 @@ #include #include "hal/misc.h" #include "hal/assert.h" +#include "hal/ana_cmpr_types.h" #include "soc/ana_cmpr_struct.h" #define ANALOG_CMPR_LL_GET_HW(unit) (&ANALOG_CMPR[unit]) @@ -60,7 +61,7 @@ static inline uint32_t analog_cmpr_ll_get_internal_ref_voltage(analog_cmpr_dev_t * @param hw Analog comparator register base address * @param ref_src reference source, 0 for internal, 1 for external GPIO pad (GPIO10) */ -static inline void analog_cmpr_ll_set_ref_source(analog_cmpr_dev_t *hw, uint32_t ref_src) +static inline void analog_cmpr_ll_set_ref_source(analog_cmpr_dev_t *hw, ana_cmpr_ref_voltage_t ref_src) { hw->pad_comp_config->mode_comp = ref_src; } @@ -91,7 +92,7 @@ static inline void analog_cmpr_ll_set_cross_type(analog_cmpr_dev_t *hw, uint8_t * @return interrupt mask */ __attribute__((always_inline)) -static inline uint32_t analog_cmpr_ll_get_intr_mask_by_type(analog_cmpr_dev_t *hw, uint8_t type) +static inline uint32_t analog_cmpr_ll_get_intr_mask_by_type(analog_cmpr_dev_t *hw, ana_cmpr_cross_type_t type) { (void)type; return ANALOG_CMPR_LL_EVENT_CROSS; diff --git a/components/hal/esp32p4/include/hal/ana_cmpr_ll.h b/components/hal/esp32p4/include/hal/ana_cmpr_ll.h index b0ada6928e4..32a5835b5a6 100644 --- a/components/hal/esp32p4/include/hal/ana_cmpr_ll.h +++ b/components/hal/esp32p4/include/hal/ana_cmpr_ll.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2023-2024 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -9,6 +9,7 @@ #include #include "hal/misc.h" #include "hal/assert.h" +#include "hal/ana_cmpr_types.h" #include "soc/ana_cmpr_struct.h" #include "soc/soc_etm_source.h" @@ -68,7 +69,7 @@ static inline float analog_cmpr_ll_get_internal_ref_voltage(analog_cmpr_dev_t *h * @param hw Analog comparator register base address * @param ref_src reference source, 0 for internal, 1 for external GPIO pad (GPIO10) */ -static inline void analog_cmpr_ll_set_ref_source(analog_cmpr_dev_t *hw, uint32_t ref_src) +static inline void analog_cmpr_ll_set_ref_source(analog_cmpr_dev_t *hw, ana_cmpr_ref_voltage_t ref_src) { hw->pad_comp_config->mode_comp = ref_src; } @@ -85,7 +86,7 @@ static inline void analog_cmpr_ll_set_ref_source(analog_cmpr_dev_t *hw, uint32_t * @return interrupt mask */ __attribute__((always_inline)) -static inline uint32_t analog_cmpr_ll_get_intr_mask_by_type(analog_cmpr_dev_t *hw, uint8_t type) +static inline uint32_t analog_cmpr_ll_get_intr_mask_by_type(analog_cmpr_dev_t *hw, ana_cmpr_cross_type_t type) { uint32_t unit = ANALOG_CMPR_LL_GET_UNIT(hw); uint32_t mask = 0; diff --git a/components/hal/include/hal/ana_cmpr_types.h b/components/hal/include/hal/ana_cmpr_types.h new file mode 100644 index 00000000000..e37764a3e13 --- /dev/null +++ b/components/hal/include/hal/ana_cmpr_types.h @@ -0,0 +1,41 @@ +/* + * SPDX-FileCopyrightText: 2023-2024 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#pragma once + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @brief Analog comparator interrupt type + * + */ +typedef enum { + ANA_CMPR_CROSS_DISABLE, /*!< Disable the cross event interrupt */ + ANA_CMPR_CROSS_POS, /*!< Positive cross can trigger event interrupt */ + ANA_CMPR_CROSS_NEG, /*!< Negative cross can trigger event interrupt */ + ANA_CMPR_CROSS_ANY, /*!< Any cross can trigger event interrupt */ +} ana_cmpr_cross_type_t; + +/** + * @brief Analog comparator internal reference voltage + * + */ +typedef enum { + ANA_CMPR_REF_VOLT_0_PCT_VDD, /*!< Internal reference voltage equals to 0% VDD */ + ANA_CMPR_REF_VOLT_10_PCT_VDD, /*!< Internal reference voltage equals to 10% VDD */ + ANA_CMPR_REF_VOLT_20_PCT_VDD, /*!< Internal reference voltage equals to 20% VDD */ + ANA_CMPR_REF_VOLT_30_PCT_VDD, /*!< Internal reference voltage equals to 30% VDD */ + ANA_CMPR_REF_VOLT_40_PCT_VDD, /*!< Internal reference voltage equals to 40% VDD */ + ANA_CMPR_REF_VOLT_50_PCT_VDD, /*!< Internal reference voltage equals to 50% VDD */ + ANA_CMPR_REF_VOLT_60_PCT_VDD, /*!< Internal reference voltage equals to 60% VDD */ + ANA_CMPR_REF_VOLT_70_PCT_VDD, /*!< Internal reference voltage equals to 70% VDD */ +} ana_cmpr_ref_voltage_t; + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32c5/ana_cmpr_periph.c b/components/soc/esp32c5/ana_cmpr_periph.c index eac077a33f7..9ff18e4329e 100644 --- a/components/soc/esp32c5/ana_cmpr_periph.c +++ b/components/soc/esp32c5/ana_cmpr_periph.c @@ -11,7 +11,7 @@ const ana_cmpr_periph_t ana_cmpr_periph[SOC_ANA_CMPR_NUM] = { [0] = { .src_gpio = ANA_CMPR0_SRC_GPIO, .ext_ref_gpio = ANA_CMPR0_EXT_REF_GPIO, - .intr_src = ETS_GPIO_NMI_SOURCE, + .intr_src = ETS_GPIO_EXT_SOURCE, }, }; diff --git a/components/soc/esp32c5/include/soc/interrupts.h b/components/soc/esp32c5/include/soc/interrupts.h index 5eb272ae64f..860800c016b 100644 --- a/components/soc/esp32c5/include/soc/interrupts.h +++ b/components/soc/esp32c5/include/soc/interrupts.h @@ -47,7 +47,7 @@ typedef enum { ETS_CACHE_INTR_SOURCE, ETS_CPU_PERI_TIMEOUT_INTR_SOURCE, ETS_GPIO_INTR_SOURCE, /**< interrupt of GPIO, level*/ - ETS_GPIO_NMI_SOURCE, /**< interrupt of GPIO, NMI*/ + ETS_GPIO_EXT_SOURCE, /**< interrupt of GPIO, EXT (analog comparator)*/ ETS_PAU_INTR_SOURCE, ETS_HP_PERI_TIMEOUT_INTR_SOURCE, ETS_MODEM_PERI_TIMEOUT_INTR_SOURCE, diff --git a/components/soc/esp32c5/interrupts.c b/components/soc/esp32c5/interrupts.c index 23421b66278..6b2682b3030 100644 --- a/components/soc/esp32c5/interrupts.c +++ b/components/soc/esp32c5/interrupts.c @@ -39,7 +39,7 @@ const char *const esp_isr_names[] = { [ETS_CACHE_INTR_SOURCE] = "CACHE", [ETS_CPU_PERI_TIMEOUT_INTR_SOURCE] = "CPU_PERI_TIMEOUT", [ETS_GPIO_INTR_SOURCE] = "GPIO_INTR", - [ETS_GPIO_NMI_SOURCE] = "GPIO_NMI", + [ETS_GPIO_EXT_SOURCE] = "GPIO_EXT", [ETS_PAU_INTR_SOURCE] = "PAU", [ETS_HP_PERI_TIMEOUT_INTR_SOURCE] = "HP_PERI_TIMEOUT", [ETS_MODEM_PERI_TIMEOUT_INTR_SOURCE] = "MODEM_PERI_TIMEOUT", From a7622efd0c99dc069ada98d89bee8e253f8518f8 Mon Sep 17 00:00:00 2001 From: Luo Xu Date: Wed, 11 Dec 2024 15:23:25 +0800 Subject: [PATCH 051/118] feat(ble_mesh): select BT_NIMBLE_HIGH_DUTY_ADV_ITVL (cherry picked from commit 6faf0a59fdcf063d40fc1000a209341318131185) Co-authored-by: luoxu --- components/bt/esp_ble_mesh/Kconfig.in | 1 + 1 file changed, 1 insertion(+) diff --git a/components/bt/esp_ble_mesh/Kconfig.in b/components/bt/esp_ble_mesh/Kconfig.in index f2e2cc18b69..a6895aa9134 100644 --- a/components/bt/esp_ble_mesh/Kconfig.in +++ b/components/bt/esp_ble_mesh/Kconfig.in @@ -15,6 +15,7 @@ if BLE_MESH config BLE_MESH_RANDOM_ADV_INTERVAL bool "Support using random adv interval for mesh packets" select BT_BLE_HIGH_DUTY_ADV_INTERVAL if BT_BLUEDROID_ENABLED + select BT_NIMBLE_HIGH_DUTY_ADV_ITVL if BT_NIMBLE_ENABLED default n help Enable this option to allow using random advertising interval From 4784b5aad86b6e06399c1f3b35e58108d983f7e6 Mon Sep 17 00:00:00 2001 From: zhangyanjiao Date: Wed, 11 Dec 2024 17:56:01 +0800 Subject: [PATCH 052/118] fix(wifi): Added CVE-2024-53845 to vulnerabilities list --- docs/en/security/vulnerabilities.rst | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/docs/en/security/vulnerabilities.rst b/docs/en/security/vulnerabilities.rst index 00d87aad5ff..6cda3b51d01 100644 --- a/docs/en/security/vulnerabilities.rst +++ b/docs/en/security/vulnerabilities.rst @@ -10,6 +10,17 @@ This page briefly lists all of the vulnerabilities that are discovered and fixed CVE-2024 -------- +CVE-2024-53845 +~~~~~~~~~~~~~~ + +AES/CBC Constant IV Vulnerability in ESPTouch v2 + +* Espressif Advisory: NA (Published on GitHub) +* Impact: Applicable for ESP-IDF +* Resolution: Please see advisory for details +* Advisory pointer: `GHSA-wm57-466g-mhrr`_ + + CVE-2024-30949 ~~~~~~~~~~~~~~ @@ -183,3 +194,4 @@ Security Advisory Concerning Wi-Fi Authentication Bypass .. _`AR2024-003`: https://www.espressif.com/sites/default/files/advisory_downloads/AR2024-003%20Security%20Advisory%20for%20PEAP%20Phase-2%20authentication%20EN.pdf .. _`GHSA-22x6-3756-pfp8` : https://github.com/espressif/esp-idf/security/advisories/GHSA-22x6-3756-pfp8 .. _`GHSA-7f7f-jj2q-28wm` : https://github.com/espressif/esp-idf/security/advisories/GHSA-7f7f-jj2q-28wm +.. _`GHSA-wm57-466g-mhrr` : https://github.com/espressif/esp-idf/security/advisories/GHSA-wm57-466g-mhrr From b85e54a8847c96d5a3a57952a2d5194e1f79bf6e Mon Sep 17 00:00:00 2001 From: "wangtao@espressif.com" Date: Thu, 12 Dec 2024 14:49:24 +0800 Subject: [PATCH 053/118] fix(wifi): fix esp32c2 ld issue --- components/esp_rom/esp32c2/ld/esp32c2.rom.eco4.ld | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/components/esp_rom/esp32c2/ld/esp32c2.rom.eco4.ld b/components/esp_rom/esp32c2/ld/esp32c2.rom.eco4.ld index 2f2d980d66a..9b2aec62657 100644 --- a/components/esp_rom/esp32c2/ld/esp32c2.rom.eco4.ld +++ b/components/esp_rom/esp32c2/ld/esp32c2.rom.eco4.ld @@ -108,7 +108,7 @@ ieee80211_output_do = 0x4000210c; ieee80211_send_nulldata = 0x40002110; //ieee80211_setup_robust_mgmtframe = 0x40002114; //ieee80211_mgmt_output = 0x40002118; -ieee80211_send_deauth = 0x40002120; +//ieee80211_send_deauth_no_bss = 0x40002120; //ieee80211_tx_mgt_cb = 0x4000212c; sta_rx_csa = 0x40002134; /*sta_send_sa_query_req = 0x40002138; From 5e8c07a7022e01408177d32e10ba91c6a5263904 Mon Sep 17 00:00:00 2001 From: Armando Date: Thu, 12 Dec 2024 15:50:48 +0800 Subject: [PATCH 054/118] fix(sdmmc): fixed wrong emmc test (should be sdmmc) --- .../components/sdmmc_tests/sdmmc_test_various_cmds.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/components/esp_driver_sdmmc/test_apps/sdmmc/components/sdmmc_tests/sdmmc_test_various_cmds.c b/components/esp_driver_sdmmc/test_apps/sdmmc/components/sdmmc_tests/sdmmc_test_various_cmds.c index 85b1a999126..a2dd5a2b3fe 100644 --- a/components/esp_driver_sdmmc/test_apps/sdmmc/components/sdmmc_tests/sdmmc_test_various_cmds.c +++ b/components/esp_driver_sdmmc/test_apps/sdmmc/components/sdmmc_tests/sdmmc_test_various_cmds.c @@ -52,10 +52,10 @@ static void sdmmc_write_sectors_cmd25_error_test_acmd22(sdmmc_card_t* card, uint ESP_LOGI(TAG, "%s: ACMD22 successfully written %zu blocks out of %zu", __func__, sucessfully_written_blocks, block_count); } -static void do_one_mmc_acmd22_test(int slot, int width, int freq_khz, int ddr) +static void do_one_sdmmc_acmd22_test(int slot, int width, int freq_khz, int ddr) { sdmmc_card_t card; - sdmmc_test_sd_skip_if_board_incompatible(slot, width, freq_khz, ddr, IS_EMMC); + sdmmc_test_sd_skip_if_board_incompatible(slot, width, freq_khz, ddr, NO_EMMC); sdmmc_test_sd_begin(slot, width, freq_khz, ddr, &card); sdmmc_card_print_info(stdout, &card); sdmmc_write_sectors_cmd25_error_test_acmd22(&card, 4096 * 4); @@ -64,10 +64,10 @@ static void do_one_mmc_acmd22_test(int slot, int width, int freq_khz, int ddr) TEST_CASE("send ACMD22 after writing multiple blocks to check real number of successfully written blocks, slot 0, 1-bit", "[sdmmc]") { - do_one_mmc_acmd22_test(SLOT_0, 1, SDMMC_FREQ_HIGHSPEED, NO_DDR); + do_one_sdmmc_acmd22_test(SLOT_0, 1, SDMMC_FREQ_HIGHSPEED, NO_DDR); } TEST_CASE("send ACMD22 after writing multiple blocks to check real number of successfully written blocks, slot 1, 1-bit", "[sdmmc]") { - do_one_mmc_acmd22_test(SLOT_1, 1, SDMMC_FREQ_HIGHSPEED, NO_DDR); + do_one_sdmmc_acmd22_test(SLOT_1, 1, SDMMC_FREQ_HIGHSPEED, NO_DDR); } From 86e5039fc96a9bb06cf05618439a3c3fa63929c7 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Tom=C3=A1=C5=A1=20Rohl=C3=ADnek?= Date: Thu, 28 Nov 2024 15:20:12 +0100 Subject: [PATCH 055/118] feat(storage/vfs): make all member pointer of vfs_ops struct const --- components/vfs/include/esp_vfs_ops.h | 239 ++++++++++++++++++--------- components/vfs/vfs.c | 12 +- 2 files changed, 168 insertions(+), 83 deletions(-) diff --git a/components/vfs/include/esp_vfs_ops.h b/components/vfs/include/esp_vfs_ops.h index 63f03508f24..2875b8c3e2c 100644 --- a/components/vfs/include/esp_vfs_ops.h +++ b/components/vfs/include/esp_vfs_ops.h @@ -50,76 +50,110 @@ typedef struct void *sem; /*!< semaphore instance */ } esp_vfs_select_sem_t; + #ifdef CONFIG_VFS_SUPPORT_DIR +typedef int (*esp_vfs_stat_ctx_op_t) (void *ctx, const char *path, struct stat *st); /*!< stat with context pointer */ +typedef int (*esp_vfs_stat_op_t) ( const char *path, struct stat *st); /*!< stat without context pointer */ +typedef int (*esp_vfs_link_ctx_op_t) (void *ctx, const char *n1, const char *n2); /*!< link with context pointer */ +typedef int (*esp_vfs_link_op_t) ( const char *n1, const char *n2); /*!< link without context pointer */ +typedef int (*esp_vfs_unlink_ctx_op_t) (void *ctx, const char *path); /*!< unlink with context pointer */ +typedef int (*esp_vfs_unlink_op_t) ( const char *path); /*!< unlink without context pointer */ +typedef int (*esp_vfs_rename_ctx_op_t) (void *ctx, const char *src, const char *dst); /*!< rename with context pointer */ +typedef int (*esp_vfs_rename_op_t) ( const char *src, const char *dst); /*!< rename without context pointer */ +typedef DIR* (*esp_vfs_opendir_ctx_op_t) (void *ctx, const char *name); /*!< opendir with context pointer */ +typedef DIR* (*esp_vfs_opendir_op_t) ( const char *name); /*!< opendir without context pointer */ +typedef struct dirent* (*esp_vfs_readdir_ctx_op_t) (void *ctx, DIR *pdir); /*!< readdir with context pointer */ +typedef struct dirent* (*esp_vfs_readdir_op_t) ( DIR *pdir); /*!< readdir without context pointer */ +typedef int (*esp_vfs_readdir_r_ctx_op_t) (void *ctx, DIR *pdir, struct dirent *entry, struct dirent **out); /*!< readdir_r with context pointer */ +typedef int (*esp_vfs_readdir_r_op_t) ( DIR *pdir, struct dirent *entry, struct dirent **out); /*!< readdir_r without context pointer */ +typedef long (*esp_vfs_telldir_ctx_op_t) (void *ctx, DIR *pdir); /*!< telldir with context pointer */ +typedef long (*esp_vfs_telldir_op_t) ( DIR *pdir); /*!< telldir without context pointer */ +typedef void (*esp_vfs_seekdir_ctx_op_t) (void *ctx, DIR *pdir, long offset); /*!< seekdir with context pointer */ +typedef void (*esp_vfs_seekdir_op_t) ( DIR *pdir, long offset); /*!< seekdir without context pointer */ +typedef int (*esp_vfs_closedir_ctx_op_t) (void *ctx, DIR *pdir); /*!< closedir with context pointer */ +typedef int (*esp_vfs_closedir_op_t) ( DIR *pdir); /*!< closedir without context pointer */ +typedef int (*esp_vfs_mkdir_ctx_op_t) (void *ctx, const char *name, mode_t mode); /*!< mkdir with context pointer */ +typedef int (*esp_vfs_mkdir_op_t) ( const char *name, mode_t mode); /*!< mkdir without context pointer */ +typedef int (*esp_vfs_rmdir_ctx_op_t) (void *ctx, const char *name); /*!< rmdir with context pointer */ +typedef int (*esp_vfs_rmdir_op_t) ( const char *name); /*!< rmdir without context pointer */ +typedef int (*esp_vfs_access_ctx_op_t) (void *ctx, const char *path, int amode); /*!< access with context pointer */ +typedef int (*esp_vfs_access_op_t) ( const char *path, int amode); /*!< access without context pointer */ +typedef int (*esp_vfs_truncate_ctx_op_t) (void *ctx, const char *path, off_t length); /*!< truncate with context pointer */ +typedef int (*esp_vfs_truncate_op_t) ( const char *path, off_t length); /*!< truncate without context pointer */ +typedef int (*esp_vfs_ftruncate_ctx_op_t) (void *ctx, int fd, off_t length); /*!< ftruncate with context pointer */ +typedef int (*esp_vfs_ftruncate_op_t) ( int fd, off_t length); /*!< ftruncate without context pointer */ +typedef int (*esp_vfs_utime_ctx_op_t) (void *ctx, const char *path, const struct utimbuf *times); /*!< utime with context pointer */ +typedef int (*esp_vfs_utime_op_t) ( const char *path, const struct utimbuf *times); /*!< utime without context pointer */ + /** * @brief Struct containing function pointers to directory related functionality. * */ typedef struct { union { - int (*stat_p)(void* ctx, const char * path, struct stat * st); /*!< stat with context pointer */ - int (*stat)(const char * path, struct stat * st); /*!< stat without context pointer */ + const esp_vfs_stat_ctx_op_t stat_p; /*!< stat with context pointer */ + const esp_vfs_stat_op_t stat; /*!< stat without context pointer */ }; union { - int (*link_p)(void* ctx, const char* n1, const char* n2); /*!< link with context pointer */ - int (*link)(const char* n1, const char* n2); /*!< link without context pointer */ + const esp_vfs_link_ctx_op_t link_p; /*!< link with context pointer */ + const esp_vfs_link_op_t link; /*!< link without context pointer */ }; union { - int (*unlink_p)(void* ctx, const char *path); /*!< unlink with context pointer */ - int (*unlink)(const char *path); /*!< unlink without context pointer */ + const esp_vfs_unlink_ctx_op_t unlink_p; /*!< unlink with context pointer */ + const esp_vfs_unlink_op_t unlink; /*!< unlink without context pointer */ }; union { - int (*rename_p)(void* ctx, const char *src, const char *dst); /*!< rename with context pointer */ - int (*rename)(const char *src, const char *dst); /*!< rename without context pointer */ + const esp_vfs_rename_ctx_op_t rename_p; /*!< rename with context pointer */ + const esp_vfs_rename_op_t rename; /*!< rename without context pointer */ }; union { - DIR* (*opendir_p)(void* ctx, const char* name); /*!< opendir with context pointer */ - DIR* (*opendir)(const char* name); /*!< opendir without context pointer */ + const esp_vfs_opendir_ctx_op_t opendir_p; /*!< opendir with context pointer */ + const esp_vfs_opendir_op_t opendir; /*!< opendir without context pointer */ }; union { - struct dirent* (*readdir_p)(void* ctx, DIR* pdir); /*!< readdir with context pointer */ - struct dirent* (*readdir)(DIR* pdir); /*!< readdir without context pointer */ + const esp_vfs_readdir_ctx_op_t readdir_p; /*!< readdir with context pointer */ + const esp_vfs_readdir_op_t readdir; /*!< readdir without context pointer */ }; union { - int (*readdir_r_p)(void* ctx, DIR* pdir, struct dirent* entry, struct dirent** out_dirent); /*!< readdir_r with context pointer */ - int (*readdir_r)(DIR* pdir, struct dirent* entry, struct dirent** out_dirent); /*!< readdir_r without context pointer */ + const esp_vfs_readdir_r_ctx_op_t readdir_r_p; /*!< readdir_r with context pointer */ + const esp_vfs_readdir_r_op_t readdir_r; /*!< readdir_r without context pointer */ }; union { - long (*telldir_p)(void* ctx, DIR* pdir); /*!< telldir with context pointer */ - long (*telldir)(DIR* pdir); /*!< telldir without context pointer */ + const esp_vfs_telldir_ctx_op_t telldir_p; /*!< telldir with context pointer */ + const esp_vfs_telldir_op_t telldir; /*!< telldir without context pointer */ }; union { - void (*seekdir_p)(void* ctx, DIR* pdir, long offset); /*!< seekdir with context pointer */ - void (*seekdir)(DIR* pdir, long offset); /*!< seekdir without context pointer */ + const esp_vfs_seekdir_ctx_op_t seekdir_p; /*!< seekdir with context pointer */ + const esp_vfs_seekdir_op_t seekdir; /*!< seekdir without context pointer */ }; union { - int (*closedir_p)(void* ctx, DIR* pdir); /*!< closedir with context pointer */ - int (*closedir)(DIR* pdir); /*!< closedir without context pointer */ + const esp_vfs_closedir_ctx_op_t closedir_p; /*!< closedir with context pointer */ + const esp_vfs_closedir_op_t closedir; /*!< closedir without context pointer */ }; union { - int (*mkdir_p)(void* ctx, const char* name, mode_t mode); /*!< mkdir with context pointer */ - int (*mkdir)(const char* name, mode_t mode); /*!< mkdir without context pointer */ + const esp_vfs_mkdir_ctx_op_t mkdir_p; /*!< mkdir with context pointer */ + const esp_vfs_mkdir_op_t mkdir; /*!< mkdir without context pointer */ }; union { - int (*rmdir_p)(void* ctx, const char* name); /*!< rmdir with context pointer */ - int (*rmdir)(const char* name); /*!< rmdir without context pointer */ + const esp_vfs_rmdir_ctx_op_t rmdir_p; /*!< rmdir with context pointer */ + const esp_vfs_rmdir_op_t rmdir; /*!< rmdir without context pointer */ }; union { - int (*access_p)(void* ctx, const char *path, int amode); /*!< access with context pointer */ - int (*access)(const char *path, int amode); /*!< access without context pointer */ + const esp_vfs_access_ctx_op_t access_p; /*!< access with context pointer */ + const esp_vfs_access_op_t access; /*!< access without context pointer */ }; union { - int (*truncate_p)(void* ctx, const char *path, off_t length); /*!< truncate with context pointer */ - int (*truncate)(const char *path, off_t length); /*!< truncate without context pointer */ + const esp_vfs_truncate_ctx_op_t truncate_p; /*!< truncate with context pointer */ + const esp_vfs_truncate_op_t truncate; /*!< truncate without context pointer */ }; union { - int (*ftruncate_p)(void* ctx, int fd, off_t length); /*!< ftruncate with context pointer */ - int (*ftruncate)(int fd, off_t length); /*!< ftruncate without context pointer */ + const esp_vfs_ftruncate_ctx_op_t ftruncate_p; /*!< ftruncate with context pointer */ + const esp_vfs_ftruncate_op_t ftruncate; /*!< ftruncate without context pointer */ }; union { - int (*utime_p)(void* ctx, const char *path, const struct utimbuf *times); /*!< utime with context pointer */ - int (*utime)(const char *path, const struct utimbuf *times); /*!< utime without context pointer */ + const esp_vfs_utime_ctx_op_t utime_p; /*!< utime with context pointer */ + const esp_vfs_utime_op_t utime; /*!< utime without context pointer */ }; } esp_vfs_dir_ops_t; @@ -127,38 +161,53 @@ typedef struct { #ifdef CONFIG_VFS_SUPPORT_TERMIOS +typedef int (*esp_vfs_tcsetattr_ctx_op_t) (void *ctx, int fd, int optional_actions, const struct termios *p); /*!< tcsetattr with context pointer */ +typedef int (*esp_vfs_tcsetattr_op_t) ( int fd, int optional_actions, const struct termios *p); /*!< tcsetattr without context pointer */ +typedef int (*esp_vfs_tcgetattr_ctx_op_t) (void *ctx, int fd, struct termios *p); /*!< tcgetattr with context pointer */ +typedef int (*esp_vfs_tcgetattr_op_t) ( int fd, struct termios *p); /*!< tcgetattr without context pointer */ +typedef int (*esp_vfs_tcdrain_ctx_op_t) (void *ctx, int fd); /*!< tcdrain with context pointer */ +typedef int (*esp_vfs_tcdrain_op_t) ( int fd); /*!< tcdrain without context pointer */ +typedef int (*esp_vfs_tcflush_ctx_op_t) (void *ctx, int fd, int select); /*!< tcflush with context pointer */ +typedef int (*esp_vfs_tcflush_op_t) ( int fd, int select); /*!< tcflush without context pointer */ +typedef int (*esp_vfs_tcflow_ctx_op_t) (void *ctx, int fd, int action); /*!< tcflow with context pointer */ +typedef int (*esp_vfs_tcflow_op_t) ( int fd, int action); /*!< tcflow without context pointer */ +typedef pid_t (*esp_vfs_tcgetsid_ctx_op_t) (void *ctx, int fd); /*!< tcgetsid with context pointer */ +typedef pid_t (*esp_vfs_tcgetsid_op_t) ( int fd); /*!< tcgetsid without context pointer */ +typedef int (*esp_vfs_tcsendbreak_ctx_op_t) (void *ctx, int fd, int duration); /*!< tcsendbreak with context pointer */ +typedef int (*esp_vfs_tcsendbreak_op_t) ( int fd, int duration); /*!< tcsendbreak without context pointer */ + /** * @brief Struct containing function pointers to termios related functionality. * */ typedef struct { union { - int (*tcsetattr_p)(void *ctx, int fd, int optional_actions, const struct termios *p); /*!< tcsetattr with context pointer */ - int (*tcsetattr)(int fd, int optional_actions, const struct termios *p); /*!< tcsetattr without context pointer */ + const esp_vfs_tcsetattr_ctx_op_t tcsetattr_p; /*!< tcsetattr with context pointer */ + const esp_vfs_tcsetattr_op_t tcsetattr; /*!< tcsetattr without context pointer */ }; union { - int (*tcgetattr_p)(void *ctx, int fd, struct termios *p); /*!< tcgetattr with context pointer */ - int (*tcgetattr)(int fd, struct termios *p); /*!< tcgetattr without context pointer */ + const esp_vfs_tcgetattr_ctx_op_t tcgetattr_p; /*!< tcgetattr with context pointer */ + const esp_vfs_tcgetattr_op_t tcgetattr; /*!< tcgetattr without context pointer */ }; union { - int (*tcdrain_p)(void *ctx, int fd); /*!< tcdrain with context pointer */ - int (*tcdrain)(int fd); /*!< tcdrain without context pointer */ + const esp_vfs_tcdrain_ctx_op_t tcdrain_p; /*!< tcdrain with context pointer */ + const esp_vfs_tcdrain_op_t tcdrain; /*!< tcdrain without context pointer */ }; union { - int (*tcflush_p)(void *ctx, int fd, int select); /*!< tcflush with context pointer */ - int (*tcflush)(int fd, int select); /*!< tcflush without context pointer */ + const esp_vfs_tcflush_ctx_op_t tcflush_p; /*!< tcflush with context pointer */ + const esp_vfs_tcflush_op_t tcflush; /*!< tcflush without context pointer */ }; union { - int (*tcflow_p)(void *ctx, int fd, int action); /*!< tcflow with context pointer */ - int (*tcflow)(int fd, int action); /*!< tcflow without context pointer */ + const esp_vfs_tcflow_ctx_op_t tcflow_p; /*!< tcflow with context pointer */ + const esp_vfs_tcflow_op_t tcflow; /*!< tcflow without context pointer */ }; union { - pid_t (*tcgetsid_p)(void *ctx, int fd); /*!< tcgetsid with context pointer */ - pid_t (*tcgetsid)(int fd); /*!< tcgetsid without context pointer */ + const esp_vfs_tcgetsid_ctx_op_t tcgetsid_p; /*!< tcgetsid with context pointer */ + const esp_vfs_tcgetsid_op_t tcgetsid; /*!< tcgetsid without context pointer */ }; union { - int (*tcsendbreak_p)(void *ctx, int fd, int duration); /*!< tcsendbreak with context pointer */ - int (*tcsendbreak)(int fd, int duration); /*!< tcsendbreak without context pointer */ + const esp_vfs_tcsendbreak_ctx_op_t tcsendbreak_p; /*!< tcsendbreak with context pointer */ + const esp_vfs_tcsendbreak_op_t tcsendbreak; /*!< tcsendbreak without context pointer */ }; } esp_vfs_termios_ops_t; @@ -166,92 +215,122 @@ typedef struct { #ifdef CONFIG_VFS_SUPPORT_SELECT +typedef esp_err_t (*esp_vfs_start_select_op_t) (int nfds, fd_set *readfds, fd_set *writefds, fd_set *exceptfds, esp_vfs_select_sem_t sem, void **end_select_args); +typedef int (*esp_vfs_socket_select_op_t) (int nfds, fd_set *readfds, fd_set *writefds, fd_set *errorfds, struct timeval *timeout); +typedef void (*esp_vfs_stop_socket_select_op_t) (void *sem); +typedef void (*esp_vfs_stop_socket_select_isr_op_t) (void *sem, BaseType_t *woken); +typedef void* (*esp_vfs_get_socket_select_semaphore_op_t) (void); +typedef esp_err_t (*esp_vfs_end_select_op_t) (void *end_select_args); + /** * @brief Struct containing function pointers to select related functionality. * */ typedef struct { /** start_select is called for setting up synchronous I/O multiplexing of the desired file descriptors in the given VFS */ - esp_err_t (*start_select)(int nfds, fd_set *readfds, fd_set *writefds, fd_set *exceptfds, esp_vfs_select_sem_t sem, void **end_select_args); + const esp_vfs_start_select_op_t start_select; /** socket select function for socket FDs with the functionality of POSIX select(); this should be set only for the socket VFS */ - int (*socket_select)(int nfds, fd_set *readfds, fd_set *writefds, fd_set *errorfds, struct timeval *timeout); + const esp_vfs_socket_select_op_t socket_select; /** called by VFS to interrupt the socket_select call when select is activated from a non-socket VFS driver; set only for the socket driver */ - void (*stop_socket_select)(void *sem); + const esp_vfs_stop_socket_select_op_t stop_socket_select; /** stop_socket_select which can be called from ISR; set only for the socket driver */ - void (*stop_socket_select_isr)(void *sem, BaseType_t *woken); + const esp_vfs_stop_socket_select_isr_op_t stop_socket_select_isr; /** end_select is called to stop the I/O multiplexing and deinitialize the environment created by start_select for the given VFS */ - void* (*get_socket_select_semaphore)(void); + const esp_vfs_get_socket_select_semaphore_op_t get_socket_select_semaphore; /** get_socket_select_semaphore returns semaphore allocated in the socket driver; set only for the socket driver */ - esp_err_t (*end_select)(void *end_select_args); + const esp_vfs_end_select_op_t end_select; } esp_vfs_select_ops_t; #endif // CONFIG_VFS_SUPPORT_SELECT +typedef ssize_t (*esp_vfs_write_ctx_op_t) (void *ctx, int fd, const void *data, size_t size); /*!< Write with context pointer */ +typedef ssize_t (*esp_vfs_write_op_t) ( int fd, const void *data, size_t size); /*!< Write without context pointer */ +typedef off_t (*esp_vfs_lseek_ctx_op_t) (void *ctx, int fd, off_t size, int mode); /*!< Seek with context pointer */ +typedef off_t (*esp_vfs_lseek_op_t) ( int fd, off_t size, int mode); /*!< Seek without context pointer */ +typedef ssize_t (*esp_vfs_read_ctx_op_t) (void *ctx, int fd, void *dst, size_t size); /*!< Read with context pointer */ +typedef ssize_t (*esp_vfs_read_op_t) ( int fd, void *dst, size_t size); /*!< Read without context pointer */ +typedef ssize_t (*esp_vfs_pread_ctx_op_t) (void *ctx, int fd, void *dst, size_t size, off_t offset); /*!< pread with context pointer */ +typedef ssize_t (*esp_vfs_pread_op_t) ( int fd, void *dst, size_t size, off_t offset); /*!< pread without context pointer */ +typedef ssize_t (*esp_vfs_pwrite_ctx_op_t) (void *ctx, int fd, const void *src, size_t size, off_t offset); /*!< pwrite with context pointer */ +typedef ssize_t (*esp_vfs_pwrite_op_t) ( int fd, const void *src, size_t size, off_t offset); /*!< pwrite without context pointer */ +typedef int (*esp_vfs_open_ctx_op_t) (void *ctx, const char *path, int flags, int mode); /*!< open with context pointer */ +typedef int (*esp_vfs_open_op_t) ( const char *path, int flags, int mode); /*!< open without context pointer */ +typedef int (*esp_vfs_close_ctx_op_t) (void *ctx, int fd); /*!< close with context pointer */ +typedef int (*esp_vfs_close_op_t) ( int fd); /*!< close without context pointer */ +typedef int (*esp_vfs_fstat_ctx_op_t) (void *ctx, int fd, struct stat *st); /*!< fstat with context pointer */ +typedef int (*esp_vfs_fstat_op_t) ( int fd, struct stat *st); /*!< fstat without context pointer */ +typedef int (*esp_vfs_fcntl_ctx_op_t) (void *ctx, int fd, int cmd, int arg); /*!< fcntl with context pointer */ +typedef int (*esp_vfs_fcntl_op_t) ( int fd, int cmd, int arg); /*!< fcntl without context pointer */ +typedef int (*esp_vfs_ioctl_ctx_op_t) (void *ctx, int fd, int cmd, va_list args); /*!< ioctl with context pointer */ +typedef int (*esp_vfs_ioctl_op_t) ( int fd, int cmd, va_list args); /*!< ioctl without context pointer */ +typedef int (*esp_vfs_fsync_ctx_op_t) (void *ctx, int fd); /*!< fsync with context pointer */ +typedef int (*esp_vfs_fsync_op_t) ( int fd); /*!< fsync without context pointer */ + /** * @brief Main struct of the minified vfs API, containing basic function pointers as well as pointers to the other subcomponents. * */ typedef struct { union { - ssize_t (*write_p)(void* p, int fd, const void * data, size_t size); /*!< Write with context pointer */ - ssize_t (*write)(int fd, const void * data, size_t size); /*!< Write without context pointer */ + const esp_vfs_write_ctx_op_t write_p; /*!< Write with context pointer */ + const esp_vfs_write_op_t write; /*!< Write without context pointer */ }; union { - off_t (*lseek_p)(void* p, int fd, off_t size, int mode); /*!< Seek with context pointer */ - off_t (*lseek)(int fd, off_t size, int mode); /*!< Seek without context pointer */ + const esp_vfs_lseek_ctx_op_t lseek_p; /*!< Seek with context pointer */ + const esp_vfs_lseek_op_t lseek; /*!< Seek without context pointer */ }; union { - ssize_t (*read_p)(void* ctx, int fd, void * dst, size_t size); /*!< Read with context pointer */ - ssize_t (*read)(int fd, void * dst, size_t size); /*!< Read without context pointer */ + const esp_vfs_read_ctx_op_t read_p; /*!< Read with context pointer */ + const esp_vfs_read_op_t read; /*!< Read without context pointer */ }; union { - ssize_t (*pread_p)(void *ctx, int fd, void * dst, size_t size, off_t offset); /*!< pread with context pointer */ - ssize_t (*pread)(int fd, void * dst, size_t size, off_t offset); /*!< pread without context pointer */ + const esp_vfs_pread_ctx_op_t pread_p; /*!< pread with context pointer */ + const esp_vfs_pread_op_t pread; /*!< pread without context pointer */ }; union { - ssize_t (*pwrite_p)(void *ctx, int fd, const void *src, size_t size, off_t offset); /*!< pwrite with context pointer */ - ssize_t (*pwrite)(int fd, const void *src, size_t size, off_t offset); /*!< pwrite without context pointer */ + const esp_vfs_pwrite_ctx_op_t pwrite_p; /*!< pwrite with context pointer */ + const esp_vfs_pwrite_op_t pwrite; /*!< pwrite without context pointer */ }; union { - int (*open_p)(void* ctx, const char * path, int flags, int mode); /*!< open with context pointer */ - int (*open)(const char * path, int flags, int mode); /*!< open without context pointer */ + const esp_vfs_open_ctx_op_t open_p; /*!< open with context pointer */ + const esp_vfs_open_op_t open; /*!< open without context pointer */ }; union { - int (*close_p)(void* ctx, int fd); /*!< close with context pointer */ - int (*close)(int fd); /*!< close without context pointer */ + const esp_vfs_close_ctx_op_t close_p; /*!< close with context pointer */ + const esp_vfs_close_op_t close; /*!< close without context pointer */ }; union { - int (*fstat_p)(void* ctx, int fd, struct stat * st); /*!< fstat with context pointer */ - int (*fstat)(int fd, struct stat * st); /*!< fstat without context pointer */ + const esp_vfs_fstat_ctx_op_t fstat_p; /*!< fstat with context pointer */ + const esp_vfs_fstat_op_t fstat; /*!< fstat without context pointer */ }; union { - int (*fcntl_p)(void* ctx, int fd, int cmd, int arg); /*!< fcntl with context pointer */ - int (*fcntl)(int fd, int cmd, int arg); /*!< fcntl without context pointer */ + const esp_vfs_fcntl_ctx_op_t fcntl_p; /*!< fcntl with context pointer */ + const esp_vfs_fcntl_op_t fcntl; /*!< fcntl without context pointer */ }; union { - int (*ioctl_p)(void* ctx, int fd, int cmd, va_list args); /*!< ioctl with context pointer */ - int (*ioctl)(int fd, int cmd, va_list args); /*!< ioctl without context pointer */ + const esp_vfs_ioctl_ctx_op_t ioctl_p; /*!< ioctl with context pointer */ + const esp_vfs_ioctl_op_t ioctl; /*!< ioctl without context pointer */ }; union { - int (*fsync_p)(void* ctx, int fd); /*!< fsync with context pointer */ - int (*fsync)(int fd); /*!< fsync without context pointer */ + const esp_vfs_fsync_ctx_op_t fsync_p; /*!< fsync with context pointer */ + const esp_vfs_fsync_op_t fsync; /*!< fsync without context pointer */ }; #ifdef CONFIG_VFS_SUPPORT_DIR - const esp_vfs_dir_ops_t *dir; /*!< pointer to the dir subcomponent */ + const esp_vfs_dir_ops_t *const dir; /*!< pointer to the dir subcomponent */ #endif #ifdef CONFIG_VFS_SUPPORT_TERMIOS - const esp_vfs_termios_ops_t *termios; /*!< pointer to the termios subcomponent */ + const esp_vfs_termios_ops_t *const termios; /*!< pointer to the termios subcomponent */ #endif #if CONFIG_VFS_SUPPORT_SELECT || defined __DOXYGEN__ - const esp_vfs_select_ops_t *select; /*!< pointer to the select subcomponent */ + const esp_vfs_select_ops_t *const select; /*!< pointer to the select subcomponent */ #endif } esp_vfs_fs_ops_t; @@ -285,18 +364,18 @@ typedef struct { * @return ESP_OK if successful, ESP_ERR_NO_MEM if too many FSes are * registered. */ -esp_err_t esp_vfs_register_fs(const char* base_path, const esp_vfs_fs_ops_t* vfs, int flags, void* ctx); +esp_err_t esp_vfs_register_fs(const char *base_path, const esp_vfs_fs_ops_t *vfs, int flags, void *ctx); /** * Analog of esp_vfs_register_with_id which accepts esp_vfs_fs_ops_t instead. * */ -esp_err_t esp_vfs_register_fs_with_id(const esp_vfs_fs_ops_t* vfs, int flags, void* ctx, esp_vfs_id_t* id); +esp_err_t esp_vfs_register_fs_with_id(const esp_vfs_fs_ops_t *vfs, int flags, void *ctx, esp_vfs_id_t *id); /** * Alias for esp_vfs_unregister for naming consistency */ -esp_err_t esp_vfs_unregister_fs(const char* base_path); +esp_err_t esp_vfs_unregister_fs(const char *base_path); /** * Alias for esp_vfs_unregister_with_id for naming consistency diff --git a/components/vfs/vfs.c b/components/vfs/vfs.c index 52a8dfe31c4..ecd1bb2dea2 100644 --- a/components/vfs/vfs.c +++ b/components/vfs/vfs.c @@ -144,7 +144,7 @@ static esp_vfs_fs_ops_t *esp_minify_vfs(const esp_vfs_t * const vfs, vfs_compone #ifdef CONFIG_VFS_SUPPORT_DIR // If the dir functions are not implemented, we don't need to convert them if (proxy.dir != NULL) { - *(proxy.dir) = (esp_vfs_dir_ops_t) { + esp_vfs_dir_ops_t tmp = { .stat = vfs->stat, .link = vfs->link, .unlink = vfs->unlink, @@ -162,13 +162,15 @@ static esp_vfs_fs_ops_t *esp_minify_vfs(const esp_vfs_t * const vfs, vfs_compone .ftruncate = vfs->ftruncate, .utime = vfs->utime, }; + + memcpy(proxy.dir, &tmp, sizeof(esp_vfs_dir_ops_t)); } #endif // CONFIG_VFS_SUPPORT_DIR #ifdef CONFIG_VFS_SUPPORT_TERMIOS // If the termios functions are not implemented, we don't need to convert them if (proxy.termios != NULL) { - *(proxy.termios) = (esp_vfs_termios_ops_t) { + esp_vfs_termios_ops_t tmp = { .tcsetattr = vfs->tcsetattr, .tcgetattr = vfs->tcgetattr, .tcdrain = vfs->tcdrain, @@ -177,13 +179,15 @@ static esp_vfs_fs_ops_t *esp_minify_vfs(const esp_vfs_t * const vfs, vfs_compone .tcgetsid = vfs->tcgetsid, .tcsendbreak = vfs->tcsendbreak, }; + + memcpy(proxy.termios, &tmp, sizeof(esp_vfs_termios_ops_t)); } #endif // CONFIG_VFS_SUPPORT_TERMIOS #ifdef CONFIG_VFS_SUPPORT_SELECT // If the select functions are not implemented, we don't need to convert them if (proxy.select != NULL) { - *(proxy.select) = (esp_vfs_select_ops_t) { + esp_vfs_select_ops_t tmp = { .start_select = vfs->start_select, .socket_select = vfs->socket_select, .stop_socket_select = vfs->stop_socket_select, @@ -191,6 +195,8 @@ static esp_vfs_fs_ops_t *esp_minify_vfs(const esp_vfs_t * const vfs, vfs_compone .get_socket_select_semaphore = vfs->get_socket_select_semaphore, .end_select = vfs->end_select, }; + + memcpy(proxy.select, &tmp, sizeof(esp_vfs_select_ops_t)); } #endif // CONFIG_VFS_SUPPORT_SELECT From c5ab71e3db1507dd915c1c848b2567e2c5447914 Mon Sep 17 00:00:00 2001 From: Song Ruo Jing Date: Thu, 12 Dec 2024 20:45:06 +0800 Subject: [PATCH 056/118] fix(esp_system): still gate hp periph clk on core/system reset for power saving Leaving only hp periph clk source should not be gated on core/system reset --- components/esp_system/port/soc/esp32p4/clk.c | 28 +++++++++++++------- 1 file changed, 18 insertions(+), 10 deletions(-) diff --git a/components/esp_system/port/soc/esp32p4/clk.c b/components/esp_system/port/soc/esp32p4/clk.c index 3bc99c44409..ecaa791fc85 100644 --- a/components/esp_system/port/soc/esp32p4/clk.c +++ b/components/esp_system/port/soc/esp32p4/clk.c @@ -244,9 +244,13 @@ __attribute__((weak)) void esp_perip_clk_init(void) } soc_reset_reason_t rst_reason = esp_rom_get_reset_reason(0); - // HP related clock control - if ((rst_reason == RESET_REASON_CHIP_POWER_ON) || (rst_reason == RESET_REASON_CORE_PMU_PWR_DOWN)) { + // HP modules related clock control + if ((rst_reason == RESET_REASON_CHIP_POWER_ON) || (rst_reason == RESET_REASON_CORE_PMU_PWR_DOWN) + || (rst_reason == RESET_REASON_SYS_BROWN_OUT) || (rst_reason == RESET_REASON_SYS_RWDT) || (rst_reason == RESET_REASON_SYS_SUPER_WDT) + || (rst_reason == RESET_REASON_CORE_SW) || (rst_reason == RESET_REASON_CORE_MWDT) || (rst_reason == RESET_REASON_CORE_RWDT) || (rst_reason == RESET_REASON_CORE_PWR_GLITCH) || (rst_reason == RESET_REASON_CORE_EFUSE_CRC) || (rst_reason == RESET_REASON_CORE_USB_JTAG) || (rst_reason == RESET_REASON_CORE_USB_UART) + ) { // hp_sys_clkrst register gets reset only if chip reset or pmu powers down hp + // but at core reset and above, we will also disable HP modules' clock gating to save power consumption _gdma_ll_enable_bus_clock(0, false); _gdma_ll_enable_bus_clock(1, false); _pau_ll_enable_bus_clock(false); @@ -303,14 +307,6 @@ __attribute__((weak)) void esp_perip_clk_init(void) _psram_ctrlr_ll_enable_module_clock(PSRAM_CTRLR_LL_MSPI_ID_2, false); #endif - REG_CLR_BIT(HP_SYS_CLKRST_REF_CLK_CTRL1_REG, HP_SYS_CLKRST_REG_REF_50M_CLK_EN); - REG_CLR_BIT(HP_SYS_CLKRST_REF_CLK_CTRL1_REG, HP_SYS_CLKRST_REG_REF_25M_CLK_EN); - // 240M CLK is for Key Management use, should not be gated - REG_CLR_BIT(HP_SYS_CLKRST_REF_CLK_CTRL2_REG, HP_SYS_CLKRST_REG_REF_160M_CLK_EN); - REG_CLR_BIT(HP_SYS_CLKRST_REF_CLK_CTRL2_REG, HP_SYS_CLKRST_REG_REF_120M_CLK_EN); - REG_CLR_BIT(HP_SYS_CLKRST_REF_CLK_CTRL2_REG, HP_SYS_CLKRST_REG_REF_80M_CLK_EN); - REG_CLR_BIT(HP_SYS_CLKRST_REF_CLK_CTRL2_REG, HP_SYS_CLKRST_REG_REF_20M_CLK_EN); - _spi_ll_enable_bus_clock(SPI2_HOST, false); _spi_ll_enable_bus_clock(SPI3_HOST, false); _spi_ll_enable_clock(SPI2_HOST, false); @@ -357,6 +353,18 @@ __attribute__((weak)) void esp_perip_clk_init(void) #endif } + // HP modules' clock source gating control + if ((rst_reason == RESET_REASON_CHIP_POWER_ON) || (rst_reason == RESET_REASON_CORE_PMU_PWR_DOWN)) { + // Only safe to disable these clock source gatings if all HP modules clock configurations has been reset + REG_CLR_BIT(HP_SYS_CLKRST_REF_CLK_CTRL1_REG, HP_SYS_CLKRST_REG_REF_50M_CLK_EN); + REG_CLR_BIT(HP_SYS_CLKRST_REF_CLK_CTRL1_REG, HP_SYS_CLKRST_REG_REF_25M_CLK_EN); + // 240M CLK is for Key Management use, should not be gated + REG_CLR_BIT(HP_SYS_CLKRST_REF_CLK_CTRL2_REG, HP_SYS_CLKRST_REG_REF_160M_CLK_EN); + REG_CLR_BIT(HP_SYS_CLKRST_REF_CLK_CTRL2_REG, HP_SYS_CLKRST_REG_REF_120M_CLK_EN); + REG_CLR_BIT(HP_SYS_CLKRST_REF_CLK_CTRL2_REG, HP_SYS_CLKRST_REG_REF_80M_CLK_EN); + REG_CLR_BIT(HP_SYS_CLKRST_REF_CLK_CTRL2_REG, HP_SYS_CLKRST_REG_REF_20M_CLK_EN); + } + // LP related clock control if ((rst_reason == RESET_REASON_CHIP_POWER_ON) || (rst_reason == RESET_REASON_SYS_SUPER_WDT) \ || (rst_reason == RESET_REASON_SYS_RWDT) || (rst_reason == RESET_REASON_SYS_BROWN_OUT)) { From c0954cf0b280332ef4d0c1f17a68196d17da5e05 Mon Sep 17 00:00:00 2001 From: Frantisek Hrbata Date: Tue, 10 Dec 2024 08:48:43 +0100 Subject: [PATCH 057/118] fix(tools): honor IDF_PYTHON_ENV_PATH value The active.py script is currently clearing the IDF_PYTHON_ENV_PATH, preventing it from being set to a custom location for the python virtual environment directory. Although the install script checks to ensure that an existing python virtual environment is not overwritten with one for a different ESP-IDF version than it was originally created for, we should still permit setting a custom path for the python virtual environment. Closes https://github.com/espressif/esp-idf/issues/15006 Signed-off-by: Frantisek Hrbata --- tools/activate.py | 9 +++++---- 1 file changed, 5 insertions(+), 4 deletions(-) diff --git a/tools/activate.py b/tools/activate.py index a23ca1883e4..7c325705fb2 100755 --- a/tools/activate.py +++ b/tools/activate.py @@ -29,7 +29,6 @@ def die(msg: str) -> None: # Get ESP-IDF venv python path idf_tools.g.idf_path = idf_path -os.environ['IDF_PYTHON_ENV_PATH'] = '' # let idf_tools get the pyenv path idf_tools.g.idf_tools_path = os.environ.get('IDF_TOOLS_PATH') or os.path.expanduser(idf_tools.IDF_TOOLS_PATH_DEFAULT) idf_python_env_path, idf_python_export_path, virtualenv_python, idf_version = idf_tools.get_python_env_path() @@ -39,10 +38,12 @@ def die(msg: str) -> None: os.environ['ESP_IDF_VERSION'] = idf_version if not os.path.exists(virtualenv_python): - die(f'ESP-IDF Python virtual environment not found. Please run the install script to set it up before proceeding.') + die((f'ESP-IDF Python virtual environment "{virtualenv_python}" ' + f'not found. Please run the install script to set it up before ' + f'proceeding.')) try: run([virtualenv_python, os.path.join(idf_path, 'tools', 'export_utils', 'activate_venv.py')] + sys.argv[1:], check=True, env=os.environ.copy()) -except (OSError, SubprocessError): - die('\n'.join(['Activation script failed', +except (OSError, SubprocessError) as e: + die('\n'.join(['Activation script failed', str(e), 'To view detailed debug information, set ESP_IDF_EXPORT_DEBUG=1 and run the export script again.'])) From 819703c442dc964904a4aa79357ee0f4d38435b5 Mon Sep 17 00:00:00 2001 From: Aleksei Apaseev Date: Fri, 13 Dec 2024 11:22:53 +0800 Subject: [PATCH 058/118] ci: add app_path to log_minimum_free_heap_size to allow better identification of the app based on its path --- conftest.py | 2 ++ 1 file changed, 2 insertions(+) diff --git a/conftest.py b/conftest.py index af6d356a0e6..d26b135c9b6 100644 --- a/conftest.py +++ b/conftest.py @@ -362,11 +362,13 @@ def real_func() -> None: res = dut.expect(r'Minimum free heap size: (\d+) bytes') logging.info( '\n------ heap size info ------\n' + '[app_path] {}\n' '[app_name] {}\n' '[config_name] {}\n' '[target] {}\n' '[minimum_free_heap_size] {} Bytes\n' '------ heap size end ------'.format( + dut.app.app_path, os.path.basename(dut.app.app_path), config, dut.target, From 0a8f808cd2d5c450cc31856a8507c2cfe8615ab3 Mon Sep 17 00:00:00 2001 From: zhanghaipeng Date: Wed, 27 Nov 2024 17:08:24 +0800 Subject: [PATCH 059/118] fix(bt): Update bt lib for ESP32-C3 and ESP32-S3(555b0a2) - Check Access Address when receive connection request PDU - Fix issue with BLE5.0 duplicate scan for chained packets --- components/bt/controller/esp32c3/Kconfig.in | 7 +++++++ components/bt/controller/esp32c3/bt.c | 4 ++++ components/bt/controller/lib_esp32c3_family | 2 +- components/bt/include/esp32c3/include/esp_bt.h | 8 ++++++++ 4 files changed, 20 insertions(+), 1 deletion(-) diff --git a/components/bt/controller/esp32c3/Kconfig.in b/components/bt/controller/esp32c3/Kconfig.in index cfaa75b60d3..76756fdbcb4 100644 --- a/components/bt/controller/esp32c3/Kconfig.in +++ b/components/bt/controller/esp32c3/Kconfig.in @@ -550,3 +550,10 @@ config BT_CTRL_BLE_SECURITY_ENABLE depends on BT_CTRL_RUN_IN_FLASH_ONLY && BT_CONTROLLER_ONLY bool "Enable BLE security feature" default y +config BT_CTRL_CHECK_CONNECT_IND_ACCESS_ADDRESS + bool "Enable enhanced Access Address check in CONNECT_IND" + default n + help + Enabling this option will add stricter verification of the Access Address in the CONNECT_IND PDU. + This improves security by ensuring that only connection requests with valid Access Addresses are accepted. + If disabled, only basic checks are applied, improving compatibility. diff --git a/components/bt/controller/esp32c3/bt.c b/components/bt/controller/esp32c3/bt.c index 2ab73319a3d..19eea2ee87a 100644 --- a/components/bt/controller/esp32c3/bt.c +++ b/components/bt/controller/esp32c3/bt.c @@ -275,6 +275,7 @@ extern void ets_backup_dma_copy(uint32_t reg, uint32_t mem_addr, uint32_t num, b #endif extern void btdm_cca_feature_enable(void); +extern void btdm_aa_check_enhance_enable(void); extern uint32_t _bt_bss_start; extern uint32_t _bt_bss_end; @@ -964,6 +965,9 @@ static void btdm_funcs_table_ready_wrapper(void) #if BT_BLE_CCA_MODE == 2 btdm_cca_feature_enable(); #endif +#if BLE_CTRL_CHECK_CONNECT_IND_ACCESS_ADDRESS_ENABLED + btdm_aa_check_enhance_enable(); +#endif } bool bt_async_wakeup_request(void) diff --git a/components/bt/controller/lib_esp32c3_family b/components/bt/controller/lib_esp32c3_family index d23ae97bb91..c57c0b11c3c 160000 --- a/components/bt/controller/lib_esp32c3_family +++ b/components/bt/controller/lib_esp32c3_family @@ -1 +1 @@ -Subproject commit d23ae97bb91d66e08c58bfaabaeed0a5ba7b7b5d +Subproject commit c57c0b11c3c0065a16b66685715100a189ef9b27 diff --git a/components/bt/include/esp32c3/include/esp_bt.h b/components/bt/include/esp32c3/include/esp_bt.h index b9d1963a1cb..d40a654bf3e 100644 --- a/components/bt/include/esp32c3/include/esp_bt.h +++ b/components/bt/include/esp32c3/include/esp_bt.h @@ -317,6 +317,12 @@ typedef void (* esp_bt_hci_tl_callback_t) (void *arg, uint8_t status); #define BT_CTRL_BLE_SCAN (1) #endif // (BT_CTRL_RUN_IN_FLASH_ONLY == 1) +#ifdef CONFIG_BT_CTRL_CHECK_CONNECT_IND_ACCESS_ADDRESS +#define BLE_CTRL_CHECK_CONNECT_IND_ACCESS_ADDRESS_ENABLED CONFIG_BT_CTRL_CHECK_CONNECT_IND_ACCESS_ADDRESS +#else +#define BLE_CTRL_CHECK_CONNECT_IND_ACCESS_ADDRESS_ENABLED 0 +#endif + #define BT_CONTROLLER_INIT_CONFIG_DEFAULT() { \ .magic = ESP_BT_CTRL_CONFIG_MAGIC_VAL, \ .version = ESP_BT_CTRL_CONFIG_VERSION, \ @@ -362,6 +368,7 @@ typedef void (* esp_bt_hci_tl_callback_t) (void *arg, uint8_t status); .qa_test = BT_CTRL_BLE_TEST, \ .master_en = BT_CTRL_BLE_MASTER, \ .scan_en = BT_CTRL_BLE_SCAN, \ + .ble_aa_check = BLE_CTRL_CHECK_CONNECT_IND_ACCESS_ADDRESS_ENABLED, \ } #else @@ -486,6 +493,7 @@ typedef struct { bool qa_test; /*!< In the flash mode, True if the QA test feature is enabled; false otherwise (default). Configurable in menuconfig.*/ bool master_en; /*!< In the flash mode, True if the master feature is enabled (default); false otherwise. Configurable in menuconfig.*/ bool scan_en; /*!< In the flash mode, True if the scan feature is enabled (default); false otherwise. Configurable in menuconfig.*/ + bool ble_aa_check; /*!< True if adds a verification step for the Access Address within the CONNECT_IND PDU; false otherwise. Configurable in menuconfig */ } esp_bt_controller_config_t; /** From 001247a29aff75a00356cdd022a316d666915e1d Mon Sep 17 00:00:00 2001 From: Espressif BOT Date: Wed, 27 Nov 2024 10:00:35 +0800 Subject: [PATCH 060/118] change(mbedtls/crt_bundle): Update esp_crt_bundle certificates --- .../mbedtls/esp_crt_bundle/cacrt_all.pem | 32 ++++++++++++++++++- .../esp_crt_bundle/cacrt_deprecated.pem | 2 +- .../protocols/esp_crt_bundle.rst | 2 +- .../protocols/esp_crt_bundle.rst | 2 +- 4 files changed, 34 insertions(+), 4 deletions(-) diff --git a/components/mbedtls/esp_crt_bundle/cacrt_all.pem b/components/mbedtls/esp_crt_bundle/cacrt_all.pem index f2c24a589d9..eb11b2fd1a8 100644 --- a/components/mbedtls/esp_crt_bundle/cacrt_all.pem +++ b/components/mbedtls/esp_crt_bundle/cacrt_all.pem @@ -1,7 +1,7 @@ ## ## Bundle of CA Root Certificates ## -## Certificate data from Mozilla as of: Tue Sep 24 03:12:04 2024 GMT +## Certificate data from Mozilla as of: Tue Nov 26 13:58:25 2024 GMT ## ## Find updated versions here: https://curl.se/docs/caextract.html ## @@ -2602,6 +2602,36 @@ vLtoURMMA/cVi4RguYv/Uo7njLwcAjA8+RHUjE7AwWHCFUyqqx0LMV87HOIAl0Qx5v5zli/altP+ CAezNIm8BZ/3Hobui3A= -----END CERTIFICATE----- +GLOBALTRUST 2020 +================ +-----BEGIN CERTIFICATE----- +MIIFgjCCA2qgAwIBAgILWku9WvtPilv6ZeUwDQYJKoZIhvcNAQELBQAwTTELMAkGA1UEBhMCQVQx +IzAhBgNVBAoTGmUtY29tbWVyY2UgbW9uaXRvcmluZyBHbWJIMRkwFwYDVQQDExBHTE9CQUxUUlVT +VCAyMDIwMB4XDTIwMDIxMDAwMDAwMFoXDTQwMDYxMDAwMDAwMFowTTELMAkGA1UEBhMCQVQxIzAh +BgNVBAoTGmUtY29tbWVyY2UgbW9uaXRvcmluZyBHbWJIMRkwFwYDVQQDExBHTE9CQUxUUlVTVCAy +MDIwMIICIjANBgkqhkiG9w0BAQEFAAOCAg8AMIICCgKCAgEAri5WrRsc7/aVj6B3GyvTY4+ETUWi +D59bRatZe1E0+eyLinjF3WuvvcTfk0Uev5E4C64OFudBc/jbu9G4UeDLgztzOG53ig9ZYybNpyrO +VPu44sB8R85gfD+yc/LAGbaKkoc1DZAoouQVBGM+uq/ufF7MpotQsjj3QWPKzv9pj2gOlTblzLmM +CcpL3TGQlsjMH/1WljTbjhzqLL6FLmPdqqmV0/0plRPwyJiT2S0WR5ARg6I6IqIoV6Lr/sCMKKCm +fecqQjuCgGOlYx8ZzHyyZqjC0203b+J+BlHZRYQfEs4kUmSFC0iAToexIiIwquuuvuAC4EDosEKA +A1GqtH6qRNdDYfOiaxaJSaSjpCuKAsR49GiKweR6NrFvG5Ybd0mN1MkGco/PU+PcF4UgStyYJ9OR +JitHHmkHr96i5OTUawuzXnzUJIBHKWk7buis/UDr2O1xcSvy6Fgd60GXIsUf1DnQJ4+H4xj04KlG +DfV0OoIu0G4skaMxXDtG6nsEEFZegB31pWXogvziB4xiRfUg3kZwhqG8k9MedKZssCz3AwyIDMvU +clOGvGBG85hqwvG/Q/lwIHfKN0F5VVJjjVsSn8VoxIidrPIwq7ejMZdnrY8XD2zHc+0klGvIg5rQ +mjdJBKuxFshsSUktq6HQjJLyQUp5ISXbY9e2nKd+Qmn7OmMCAwEAAaNjMGEwDwYDVR0TAQH/BAUw +AwEB/zAOBgNVHQ8BAf8EBAMCAQYwHQYDVR0OBBYEFNwuH9FhN3nkq9XVsxJxaD1qaJwiMB8GA1Ud +IwQYMBaAFNwuH9FhN3nkq9XVsxJxaD1qaJwiMA0GCSqGSIb3DQEBCwUAA4ICAQCR8EICaEDuw2jA +VC/f7GLDw56KoDEoqoOOpFaWEhCGVrqXctJUMHytGdUdaG/7FELYjQ7ztdGl4wJCXtzoRlgHNQIw +4Lx0SsFDKv/bGtCwr2zD/cuz9X9tAy5ZVp0tLTWMstZDFyySCstd6IwPS3BD0IL/qMy/pJTAvoe9 +iuOTe8aPmxadJ2W8esVCgmxcB9CpwYhgROmYhRZf+I/KARDOJcP5YBugxZfD0yyIMaK9MOzQ0MAS +8cE54+X1+NZK3TTN+2/BT+MAi1bikvcoskJ3ciNnxz8RFbLEAwW+uxF7Cr+obuf/WEPPm2eggAe2 +HcqtbepBEX4tdJP7wry+UUTF72glJ4DjyKDUEuzZpTcdN3y0kcra1LGWge9oXHYQSa9+pTeAsRxS +vTOBTI/53WXZFM2KJVj04sWDpQmQ1GwUY7VA3+vA/MRYfg0UFodUJ25W5HCEuGwyEn6CMUO+1918 +oa2u1qsgEu8KwxCMSZY13At1XrFP1U80DhEgB3VDRemjEdqso5nCtnkn4rnvyOL2NSl6dPrFf4IF +YqYK6miyeUcGbvJXqBUzxvd4Sj1Ce2t+/vdG6tHrju+IaFvowdlxfv1k7/9nR4hYJS8+hge9+6jl +gqispdNpQ80xiEmEU5LAsTkbOYMBMMTyqfrQA71yN2BWHzZ8vTmR9W0Nv3vXkg== +-----END CERTIFICATE----- + ANF Secure Server Root CA ========================= -----BEGIN CERTIFICATE----- diff --git a/components/mbedtls/esp_crt_bundle/cacrt_deprecated.pem b/components/mbedtls/esp_crt_bundle/cacrt_deprecated.pem index 064870c235d..662fd9e0bb0 100644 --- a/components/mbedtls/esp_crt_bundle/cacrt_deprecated.pem +++ b/components/mbedtls/esp_crt_bundle/cacrt_deprecated.pem @@ -7,7 +7,7 @@ ## These certificates might be removed from ESP-IDF during every major release. -## The current deprecated certificate bundle is up-to-date with the Mozilla cert bundle (cacrt_all.pem) dated Tue Sep 24 03:12:04 2024 GMT +## The current deprecated certificate bundle is up-to-date with the Mozilla cert bundle (cacrt_all.pem) dated Tue Nov 26 13:58:25 2024 GMT Hongkong Post Root CA 1 diff --git a/docs/en/api-reference/protocols/esp_crt_bundle.rst b/docs/en/api-reference/protocols/esp_crt_bundle.rst index e807d1bba8a..528dcf440ff 100644 --- a/docs/en/api-reference/protocols/esp_crt_bundle.rst +++ b/docs/en/api-reference/protocols/esp_crt_bundle.rst @@ -16,7 +16,7 @@ The bundle comes with the complete list of root certificates from Mozilla's NSS When generating the bundle you may choose between: - * The full root certificate bundle from Mozilla, containing more than 130 certificates. The current bundle was updated Tue Sep 24 03:12:04 2024 GMT. + * The full root certificate bundle from Mozilla, containing more than 130 certificates. The current bundle was updated Tue Nov 26 13:58:25 2024 GMT. * A pre-selected filter list of the name of the most commonly used root certificates, reducing the amount of certificates to around 41 while still having around 90% absolute usage coverage and 99% market share coverage according to SSL certificate authorities statistics. In addition, it is possible to specify a path to a certificate file or a directory containing certificates which then will be added to the generated bundle. diff --git a/docs/zh_CN/api-reference/protocols/esp_crt_bundle.rst b/docs/zh_CN/api-reference/protocols/esp_crt_bundle.rst index 2fdb0d4c4ad..122cb1d8882 100644 --- a/docs/zh_CN/api-reference/protocols/esp_crt_bundle.rst +++ b/docs/zh_CN/api-reference/protocols/esp_crt_bundle.rst @@ -16,7 +16,7 @@ ESP x509 证书包 API 提供了一种简便的方法，帮助你安装自定义 生成证书包时，你需选择： -* 来自 Mozilla 的完整根证书包，包含超过 130 份证书。目前提供的证书包更新于 2024 年 9 月 24 日，星期二，03:12:04 (GMT)。 +* 来自 Mozilla 的完整根证书包，包含超过 130 份证书。目前提供的证书包更新于 2024 年 11 月 26 日，星期一, 13:58:25 (GMT)。 * 一组预先筛选的常用根证书。其中仅包含约 41 份证书，但根据 SSL 证书颁发机构统计数据，其绝对使用率约达到 90%，市场覆盖率约达 99%。 此外，还可指定证书文件的路径或包含证书的目录，将其他证书添加到生成的证书包中。 From d051a2a39de4699cdc919d467890ce8f216ef607 Mon Sep 17 00:00:00 2001 From: xuzhekai Date: Wed, 30 Oct 2024 17:38:15 +0800 Subject: [PATCH 061/118] feat(bt/bluedroid): Added BLE get started examples for Bluedroid --- .../bluedroid/Bluedroid_Beacon/CMakeLists.txt | 6 + .../bluedroid/Bluedroid_Beacon/README.md | 249 +++++++++ .../Bluedroid_Beacon/main/CMakeLists.txt | 2 + .../bluedroid/Bluedroid_Beacon/main/main.c | 177 ++++++ .../Bluedroid_Beacon/sdkconfig.defaults | 8 + .../sdkconfig.defaults.esp32c2 | 10 + .../sdkconfig.defaults.esp32c3 | 7 + .../sdkconfig.defaults.esp32s3 | 7 + .../Bluedroid_Connection/CMakeLists.txt | 6 + .../bluedroid/Bluedroid_Connection/README.md | 169 ++++++ .../Bluedroid_Connection/main/CMakeLists.txt | 2 + .../main/Kconfig.projbuild | 14 + .../Bluedroid_Connection/main/main.c | 180 ++++++ .../Bluedroid_Connection/sdkconfig.defaults | 8 + .../sdkconfig.defaults.esp32c2 | 9 + .../sdkconfig.defaults.esp32c3 | 7 + .../sdkconfig.defaults.esp32s3 | 7 + .../Bluedroid_GATT_Server/CMakeLists.txt | 6 + .../bluedroid/Bluedroid_GATT_Server/README.md | 325 +++++++++++ .../Bluedroid_GATT_Server/main/CMakeLists.txt | 4 + .../main/Kconfig.projbuild | 54 ++ .../main/idf_component.yml | 17 + .../main/include/heart_rate.h | 18 + .../Bluedroid_GATT_Server/main/include/led.h | 23 + .../Bluedroid_GATT_Server/main/main.c | 515 ++++++++++++++++++ .../main/src/heart_rate_mock.c | 17 + .../Bluedroid_GATT_Server/main/src/led.c | 98 ++++ .../Bluedroid_GATT_Server/sdkconfig.defaults | 8 + .../sdkconfig.defaults.esp32 | 2 + .../sdkconfig.defaults.esp32c2 | 12 + .../sdkconfig.defaults.esp32c3 | 7 + .../sdkconfig.defaults.esp32c5 | 10 + .../sdkconfig.defaults.esp32s3 | 10 + 33 files changed, 1994 insertions(+) create mode 100644 examples/bluetooth/ble_get_started/bluedroid/Bluedroid_Beacon/CMakeLists.txt create mode 100644 examples/bluetooth/ble_get_started/bluedroid/Bluedroid_Beacon/README.md create mode 100644 examples/bluetooth/ble_get_started/bluedroid/Bluedroid_Beacon/main/CMakeLists.txt create mode 100644 examples/bluetooth/ble_get_started/bluedroid/Bluedroid_Beacon/main/main.c create mode 100644 examples/bluetooth/ble_get_started/bluedroid/Bluedroid_Beacon/sdkconfig.defaults create mode 100644 examples/bluetooth/ble_get_started/bluedroid/Bluedroid_Beacon/sdkconfig.defaults.esp32c2 create mode 100644 examples/bluetooth/ble_get_started/bluedroid/Bluedroid_Beacon/sdkconfig.defaults.esp32c3 create mode 100644 examples/bluetooth/ble_get_started/bluedroid/Bluedroid_Beacon/sdkconfig.defaults.esp32s3 create mode 100644 examples/bluetooth/ble_get_started/bluedroid/Bluedroid_Connection/CMakeLists.txt create mode 100644 examples/bluetooth/ble_get_started/bluedroid/Bluedroid_Connection/README.md create mode 100644 examples/bluetooth/ble_get_started/bluedroid/Bluedroid_Connection/main/CMakeLists.txt create mode 100644 examples/bluetooth/ble_get_started/bluedroid/Bluedroid_Connection/main/Kconfig.projbuild create mode 100644 examples/bluetooth/ble_get_started/bluedroid/Bluedroid_Connection/main/main.c create mode 100644 examples/bluetooth/ble_get_started/bluedroid/Bluedroid_Connection/sdkconfig.defaults create mode 100644 examples/bluetooth/ble_get_started/bluedroid/Bluedroid_Connection/sdkconfig.defaults.esp32c2 create mode 100644 examples/bluetooth/ble_get_started/bluedroid/Bluedroid_Connection/sdkconfig.defaults.esp32c3 create mode 100644 examples/bluetooth/ble_get_started/bluedroid/Bluedroid_Connection/sdkconfig.defaults.esp32s3 create mode 100644 examples/bluetooth/ble_get_started/bluedroid/Bluedroid_GATT_Server/CMakeLists.txt create mode 100644 examples/bluetooth/ble_get_started/bluedroid/Bluedroid_GATT_Server/README.md create mode 100644 examples/bluetooth/ble_get_started/bluedroid/Bluedroid_GATT_Server/main/CMakeLists.txt create mode 100644 examples/bluetooth/ble_get_started/bluedroid/Bluedroid_GATT_Server/main/Kconfig.projbuild create mode 100644 examples/bluetooth/ble_get_started/bluedroid/Bluedroid_GATT_Server/main/idf_component.yml create mode 100644 examples/bluetooth/ble_get_started/bluedroid/Bluedroid_GATT_Server/main/include/heart_rate.h create mode 100644 examples/bluetooth/ble_get_started/bluedroid/Bluedroid_GATT_Server/main/include/led.h create mode 100644 examples/bluetooth/ble_get_started/bluedroid/Bluedroid_GATT_Server/main/main.c create mode 100644 examples/bluetooth/ble_get_started/bluedroid/Bluedroid_GATT_Server/main/src/heart_rate_mock.c create mode 100644 examples/bluetooth/ble_get_started/bluedroid/Bluedroid_GATT_Server/main/src/led.c create mode 100644 examples/bluetooth/ble_get_started/bluedroid/Bluedroid_GATT_Server/sdkconfig.defaults create mode 100644 examples/bluetooth/ble_get_started/bluedroid/Bluedroid_GATT_Server/sdkconfig.defaults.esp32 create mode 100644 examples/bluetooth/ble_get_started/bluedroid/Bluedroid_GATT_Server/sdkconfig.defaults.esp32c2 create mode 100644 examples/bluetooth/ble_get_started/bluedroid/Bluedroid_GATT_Server/sdkconfig.defaults.esp32c3 create mode 100644 examples/bluetooth/ble_get_started/bluedroid/Bluedroid_GATT_Server/sdkconfig.defaults.esp32c5 create mode 100644 examples/bluetooth/ble_get_started/bluedroid/Bluedroid_GATT_Server/sdkconfig.defaults.esp32s3 diff --git a/examples/bluetooth/ble_get_started/bluedroid/Bluedroid_Beacon/CMakeLists.txt b/examples/bluetooth/ble_get_started/bluedroid/Bluedroid_Beacon/CMakeLists.txt new file mode 100644 index 00000000000..eca268b9abc --- /dev/null +++ b/examples/bluetooth/ble_get_started/bluedroid/Bluedroid_Beacon/CMakeLists.txt @@ -0,0 +1,6 @@ +# The following lines of boilerplate have to be in your project's CMakeLists +# in this exact order for cmake to work correctly +cmake_minimum_required(VERSION 3.16) + +include($ENV{IDF_PATH}/tools/cmake/project.cmake) +project(bluedroid_beacon) diff --git a/examples/bluetooth/ble_get_started/bluedroid/Bluedroid_Beacon/README.md b/examples/bluetooth/ble_get_started/bluedroid/Bluedroid_Beacon/README.md new file mode 100644 index 00000000000..f86c4c7302b --- /dev/null +++ b/examples/bluetooth/ble_get_started/bluedroid/Bluedroid_Beacon/README.md @@ -0,0 +1,249 @@ +| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-H2 | ESP32-S3 | +| ----------------- | ----- | -------- | -------- | -------- | -------- | --------- | -------- | -------- | + +# Bluedroid Beacon Example + +## Overview + +This is a pretty simple example, aiming to introduce + +1. How to initialize Bluedroid stack +2. How to configure advertisement and scan response data +3. How to start advertising as a non-connectable beacon + +It uses ESP32's Bluetooth controller and Bluedroid host stack. + +To test this demo, any BLE scanner application can be used. + +## Try It Yourself + +### Set Target + +Before project configuration and build, be sure to set the correct chip target using: + +``` shell +idf.py set-target +``` + +For example, if you're using ESP32, then input + +``` Shell +idf.py set-target esp32 +``` + +### Build and Flash + +Run the following command to build, flash and monitor the project. + +``` Shell +idf.py -p flash monitor +``` + +For example, if the corresponding serial port is `/dev/ttyACM0`, then it goes + +``` Shell +idf.py -p /dev/ttyACM0 flash monitor +``` + +(To exit the serial monitor, type ``Ctrl-]``.) + +See the [Getting Started Guide](https://idf.espressif.com/) for full steps to configure and use ESP-IDF to build projects. + +## Code Explained + +### Overview + +1. Initialize NVS flash, Bluedroid host stack and GAP service; configure Bluedroid host stack and start Bluedroid host task thread +2. Set advertisement and scan response data, then configure advertising parameters and start advertising + +### Entry Point + +`app_main` in `main.c` is the entry point of all ESP32 applications. In general, application initialization should be done here. + +First, call `nvs_flash_init`, `esp_bt_controller_init` and `esp_bt_controller_enable` functions to initialize NVS flash as well as the BT controller. + +``` C +void app_main(void) { + esp_err_t ret; + + //initialize NVS + ret = nvs_flash_init(); + if (ret == ESP_ERR_NVS_NO_FREE_PAGES || ret == ESP_ERR_NVS_NEW_VERSION_FOUND) { + ESP_ERROR_CHECK(nvs_flash_erase()); + ret = nvs_flash_init(); + } + ESP_ERROR_CHECK(ret); + ESP_ERROR_CHECK(esp_bt_controller_mem_release(ESP_BT_MODE_CLASSIC_BT)); + + esp_bt_controller_config_t bt_cfg = BT_CONTROLLER_INIT_CONFIG_DEFAULT(); + ret = esp_bt_controller_init(&bt_cfg); + if (ret) { + ESP_LOGE(DEMO_TAG, "%s initialize controller failed: %s", __func__, esp_err_to_name(ret)); + return; + } + + ret = esp_bt_controller_enable(ESP_BT_MODE_BLE); + if (ret) { + ESP_LOGE(DEMO_TAG, "%s enable controller failed: %s", __func__, esp_err_to_name(ret)); + return; + } + ... +} +``` + +Then, call `esp_bluedroid_init` and `esp_bluedroid_enable` function to initialize Bluedroid host stack. + +``` C +void app_main(void) { + ... + + ret = esp_bluedroid_init(); + if (ret) { + ESP_LOGE(DEMO_TAG, "%s init bluetooth failed: %s", __func__, esp_err_to_name(ret)); + return; + } + + ret = esp_bluedroid_enable(); + if (ret) { + ESP_LOGE(DEMO_TAG, "%s enable bluetooth failed: %s", __func__, esp_err_to_name(ret)); + return; + } + + ... +} +``` + +After that, call `esp_ble_gap_register_callback` to register `esp_gap_cb` function as GAP service callback function. From then on all GAP events will be handled by `esp_gap_cb` function. + +``` C +void app_main(void) { + ... + + ret = esp_ble_gap_register_callback(esp_gap_cb); + if (ret) { + ESP_LOGE(DEMO_TAG, "gap register error, error code = %x", ret); + return; + } + + ... +} +``` + +### Start Advertising + +As a beacon device, we're going to start advertising and send scan response if a scan request is received. To make it happen, we need to set advertisement and scan response data before advertising starts. So the following are what we do: + +1. Initialize advertisement and scan response fields structs `adv_raw_data` and `scan_rsp_raw_data`, as well as advertising parameters struct `adv_params`. +2. Set advertising parameters based on your requirements. + 1. advertising interval is set to 20 ms. + 2. advertising PDU is set to `ADV_SCAN_IND`. + 3. advertising address type is public address. + 4. advertising channel is set to all channels. Channels 37, 38 and 39 will all be used for advertising. +3. Set advertising raw data and scan response raw data. + +``` C +static esp_ble_adv_params_t adv_params = { + .adv_int_min = 0x20, // 20ms + .adv_int_max = 0x20, // 20ms + .adv_type = ADV_TYPE_SCAN_IND, + .own_addr_type = BLE_ADDR_TYPE_PUBLIC, + .channel_map = ADV_CHNL_ALL, + .adv_filter_policy = ADV_FILTER_ALLOW_SCAN_ANY_CON_ANY, +}; + +//configure raw data for advertising packet +static uint8_t adv_raw_data[] = { + 0x02, ESP_BLE_AD_TYPE_FLAG, 0x06, + 0x11, ESP_BLE_AD_TYPE_NAME_CMPL, 'B', 'l', 'u', 'e', 'd', 'r', 'o', 'i', 'd', '_', 'B', 'e', 'a', 'c', 'o', 'n', + 0x02, ESP_BLE_AD_TYPE_TX_PWR, 0x09, + 0x03, ESP_BLE_AD_TYPE_APPEARANCE, 0x00,0x02, + 0x02, ESP_BLE_AD_TYPE_LE_ROLE, 0x00, +}; + +static uint8_t scan_rsp_raw_data[] = { + 0x08, ESP_BLE_AD_TYPE_LE_DEV_ADDR, 0x46, 0xF5, 0x06, 0xBD, 0xF5, 0xF0, 0x00, + 0x11, ESP_BLE_AD_TYPE_URI, 0x17, 0x2F, 0x2F, 0x65, 0x73, 0x70, 0x72, 0x65, 0x73, 0x73, 0x69, 0x66, 0x2E, 0x63, 0x6F, 0x6D, +}; + +``` +4. Config advertising raw data with `esp_ble_gap_config_adv_data_raw`. Set device address in response raw data and call `esp_ble_gap_config_scan_rsp_data_raw` to configure advertising raw data. + 1. Since `AdvData` in advertisement packet **should not be longer than 31 bytes**, additional information must be placed in scan response packet + 2. We put the official website link of espressif into URI field + 3. Take care of endianness of device address + +``` C +void app_main(void) { + ... + + adv_config_done |= ADV_CONFIG_FLAG; + adv_config_done |= SCAN_RSP_CONFIG_FLAG; + ret = esp_ble_gap_config_adv_data_raw(adv_raw_data, sizeof(adv_raw_data)); + if (ret) { + ESP_LOGE(DEMO_TAG, "config adv data failed, error code = %x", ret); + return; + } + + ret = esp_ble_gap_get_local_used_addr(local_addr, &local_addr_type); + if (ret) { + ESP_LOGE(DEMO_TAG, "get local used address failed, error code = %x", ret); + return; + } + + scan_rsp_raw_data[2] = local_addr[5]; + scan_rsp_raw_data[3] = local_addr[4]; + scan_rsp_raw_data[4] = local_addr[3]; + scan_rsp_raw_data[5] = local_addr[2]; + scan_rsp_raw_data[6] = local_addr[1]; + scan_rsp_raw_data[7] = local_addr[0]; + ret = esp_ble_gap_config_scan_rsp_data_raw(scan_rsp_raw_data, sizeof(scan_rsp_raw_data)); + if (ret) { + ESP_LOGE(DEMO_TAG, "config scan rsp data failed, error code = %x", ret); + } +} +``` + +4. When both advertising raw data and scan response raw data are successfully set, start advertising by calling `esp_ble_gap_start_advertising` + +``` C +static void esp_gap_cb(esp_gap_ble_cb_event_t event, esp_ble_gap_cb_param_t *param) +{ + ... + case ESP_GAP_BLE_ADV_DATA_RAW_SET_COMPLETE_EVT: + ESP_LOGI(DEMO_TAG, "Advertising data raw set, status %d", param->adv_data_raw_cmpl.status); + adv_config_done &= (~ADV_CONFIG_FLAG); + if (adv_config_done == 0) { + esp_ble_gap_start_advertising(&adv_params); + } + break; + case ESP_GAP_BLE_SCAN_RSP_DATA_RAW_SET_COMPLETE_EVT: + ESP_LOGI(DEMO_TAG, "Scan response data raw set, status %d", param->scan_rsp_data_raw_cmpl.status); + adv_config_done &= (~SCAN_RSP_CONFIG_FLAG); + if (adv_config_done == 0) { + esp_ble_gap_start_advertising(&adv_params); + } + break; +} +``` + +5. If advertising has been successfully enabled, you should receive `ESP_GAP_BLE_ADV_START_COMPLETE_EVT` GAP event. +``` C +static void esp_gap_cb(esp_gap_ble_cb_event_t event, esp_ble_gap_cb_param_t *param) +{ + ... + case ESP_GAP_BLE_ADV_START_COMPLETE_EVT: + if (param->adv_start_cmpl.status != ESP_BT_STATUS_SUCCESS) { + ESP_LOGE(DEMO_TAG, "Advertising start failed, status %d", param->adv_start_cmpl.status); + break; + } + ESP_LOGI(DEMO_TAG, "Advertising start successfully"); + break; +} +``` + +### Observation + +If everything goes well, you should be able to see `Bluedroid_Beacon` on a BLE scanner device, broadcasting a lot of information including an URI of "https://espressif.com" (The official website of espressif), which is exactly what we expect. + +## Troubleshooting + +For any technical queries, please file an [issue](https://github.com/espressif/esp-idf/issues) on GitHub. We will get back to you soon. diff --git a/examples/bluetooth/ble_get_started/bluedroid/Bluedroid_Beacon/main/CMakeLists.txt b/examples/bluetooth/ble_get_started/bluedroid/Bluedroid_Beacon/main/CMakeLists.txt new file mode 100644 index 00000000000..cf2c455cb50 --- /dev/null +++ b/examples/bluetooth/ble_get_started/bluedroid/Bluedroid_Beacon/main/CMakeLists.txt @@ -0,0 +1,2 @@ +idf_component_register(SRCS "main.c" + INCLUDE_DIRS ".") diff --git a/examples/bluetooth/ble_get_started/bluedroid/Bluedroid_Beacon/main/main.c b/examples/bluetooth/ble_get_started/bluedroid/Bluedroid_Beacon/main/main.c new file mode 100644 index 00000000000..39a163b03e7 --- /dev/null +++ b/examples/bluetooth/ble_get_started/bluedroid/Bluedroid_Beacon/main/main.c @@ -0,0 +1,177 @@ +/* + * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Unlicense OR CC0-1.0 + */ +#include +#include +#include +#include +#include "nvs_flash.h" + +#include "esp_bt.h" +#include "esp_gap_ble_api.h" +#include "esp_gattc_api.h" +#include "esp_gatt_defs.h" +#include "esp_bt_main.h" +#include "esp_log.h" +#include "esp_system.h" +#include "esp_bt_defs.h" +#include "freertos/FreeRTOS.h" + +#define ADV_CONFIG_FLAG (1 << 0) +#define SCAN_RSP_CONFIG_FLAG (1 << 1) +#define URI_PREFIX_HTTPS (0x17) + +static void esp_gap_cb(esp_gap_ble_cb_event_t event, esp_ble_gap_cb_param_t *param); + +static const char *DEMO_TAG = "BLE_BEACON"; +static const char device_name[] = "Bluedroid_Beacon"; + +static uint8_t adv_config_done = 0; +static esp_bd_addr_t local_addr; +static uint8_t local_addr_type; + +static esp_ble_adv_params_t adv_params = { + .adv_int_min = 0x20, // 20ms + .adv_int_max = 0x20, // 20ms + .adv_type = ADV_TYPE_SCAN_IND, + .own_addr_type = BLE_ADDR_TYPE_PUBLIC, + .channel_map = ADV_CHNL_ALL, + .adv_filter_policy = ADV_FILTER_ALLOW_SCAN_ANY_CON_ANY, +}; + +//configure raw data for advertising packet +static uint8_t adv_raw_data[] = { + 0x02, ESP_BLE_AD_TYPE_FLAG, 0x06, + 0x11, ESP_BLE_AD_TYPE_NAME_CMPL, 'B', 'l', 'u', 'e', 'd', 'r', 'o', 'i', 'd', '_', 'B', 'e', 'a', 'c', 'o', 'n', + 0x02, ESP_BLE_AD_TYPE_TX_PWR, 0x09, + 0x03, ESP_BLE_AD_TYPE_APPEARANCE, 0x00,0x02, + 0x02, ESP_BLE_AD_TYPE_LE_ROLE, 0x00, +}; + +static uint8_t scan_rsp_raw_data[] = { + 0x08, ESP_BLE_AD_TYPE_LE_DEV_ADDR, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x11, ESP_BLE_AD_TYPE_URI, URI_PREFIX_HTTPS, '/', '/', 'e', 's', 'p', 'r', 'e', 's', 's', 'i', 'f', '.', 'c', 'o', 'm', +}; + +void app_main(void) +{ + esp_err_t ret; + + //initialize NVS + ret = nvs_flash_init(); + if (ret == ESP_ERR_NVS_NO_FREE_PAGES || ret == ESP_ERR_NVS_NEW_VERSION_FOUND) { + ESP_ERROR_CHECK(nvs_flash_erase()); + ret = nvs_flash_init(); + } + ESP_ERROR_CHECK(ret); + + ESP_ERROR_CHECK(esp_bt_controller_mem_release(ESP_BT_MODE_CLASSIC_BT)); + + esp_bt_controller_config_t bt_cfg = BT_CONTROLLER_INIT_CONFIG_DEFAULT(); + ret = esp_bt_controller_init(&bt_cfg); + if (ret) { + ESP_LOGE(DEMO_TAG, "%s initialize controller failed: %s", __func__, esp_err_to_name(ret)); + return; + } + + ret = esp_bt_controller_enable(ESP_BT_MODE_BLE); + if (ret) { + ESP_LOGE(DEMO_TAG, "%s enable controller failed: %s", __func__, esp_err_to_name(ret)); + return; + } + + ret = esp_bluedroid_init(); + if (ret) { + ESP_LOGE(DEMO_TAG, "%s init bluetooth failed: %s", __func__, esp_err_to_name(ret)); + return; + } + + ret = esp_bluedroid_enable(); + if (ret) { + ESP_LOGE(DEMO_TAG, "%s enable bluetooth failed: %s", __func__, esp_err_to_name(ret)); + return; + } + + ret = esp_ble_gap_register_callback(esp_gap_cb); + if (ret) { + ESP_LOGE(DEMO_TAG, "gap register error, error code = %x", ret); + return; + } + + ret = esp_ble_gap_set_device_name(device_name); + if (ret) { + ESP_LOGE(DEMO_TAG, "set device name error, error code = %x", ret); + return; + } + + //config adv data + adv_config_done |= ADV_CONFIG_FLAG; + adv_config_done |= SCAN_RSP_CONFIG_FLAG; + ret = esp_ble_gap_config_adv_data_raw(adv_raw_data, sizeof(adv_raw_data)); + if (ret) { + ESP_LOGE(DEMO_TAG, "config adv data failed, error code = %x", ret); + return; + } + + ret = esp_ble_gap_get_local_used_addr(local_addr, &local_addr_type); + if (ret) { + ESP_LOGE(DEMO_TAG, "get local used address failed, error code = %x", ret); + return; + } + + scan_rsp_raw_data[2] = local_addr[5]; + scan_rsp_raw_data[3] = local_addr[4]; + scan_rsp_raw_data[4] = local_addr[3]; + scan_rsp_raw_data[5] = local_addr[2]; + scan_rsp_raw_data[6] = local_addr[1]; + scan_rsp_raw_data[7] = local_addr[0]; + ret = esp_ble_gap_config_scan_rsp_data_raw(scan_rsp_raw_data, sizeof(scan_rsp_raw_data)); + if (ret) { + ESP_LOGE(DEMO_TAG, "config scan rsp data failed, error code = %x", ret); + } +} + +static void esp_gap_cb(esp_gap_ble_cb_event_t event, esp_ble_gap_cb_param_t *param) +{ + switch (event) { + case ESP_GAP_BLE_ADV_DATA_SET_COMPLETE_EVT: + ESP_LOGI(DEMO_TAG, "Advertising data set, status %d", param->adv_data_cmpl.status); + adv_config_done &= (~ADV_CONFIG_FLAG); + if (adv_config_done == 0) { + esp_ble_gap_start_advertising(&adv_params); + } + break; + case ESP_GAP_BLE_ADV_DATA_RAW_SET_COMPLETE_EVT: + ESP_LOGI(DEMO_TAG, "Advertising data raw set, status %d", param->adv_data_raw_cmpl.status); + adv_config_done &= (~ADV_CONFIG_FLAG); + if (adv_config_done == 0) { + esp_ble_gap_start_advertising(&adv_params); + } + break; + case ESP_GAP_BLE_SCAN_RSP_DATA_SET_COMPLETE_EVT: + ESP_LOGI(DEMO_TAG, "Scan response data set, status %d", param->scan_rsp_data_cmpl.status); + adv_config_done &= (~SCAN_RSP_CONFIG_FLAG); + if (adv_config_done == 0) { + esp_ble_gap_start_advertising(&adv_params); + } + break; + case ESP_GAP_BLE_SCAN_RSP_DATA_RAW_SET_COMPLETE_EVT: + ESP_LOGI(DEMO_TAG, "Scan response data raw set, status %d", param->scan_rsp_data_raw_cmpl.status); + adv_config_done &= (~SCAN_RSP_CONFIG_FLAG); + if (adv_config_done == 0) { + esp_ble_gap_start_advertising(&adv_params); + } + break; + case ESP_GAP_BLE_ADV_START_COMPLETE_EVT: + if (param->adv_start_cmpl.status != ESP_BT_STATUS_SUCCESS) { + ESP_LOGE(DEMO_TAG, "Advertising start failed, status %d", param->adv_start_cmpl.status); + break; + } + ESP_LOGI(DEMO_TAG, "Advertising start successfully"); + break; + default: + break; + } +} diff --git a/examples/bluetooth/ble_get_started/bluedroid/Bluedroid_Beacon/sdkconfig.defaults b/examples/bluetooth/ble_get_started/bluedroid/Bluedroid_Beacon/sdkconfig.defaults new file mode 100644 index 00000000000..73d84284854 --- /dev/null +++ b/examples/bluetooth/ble_get_started/bluedroid/Bluedroid_Beacon/sdkconfig.defaults @@ -0,0 +1,8 @@ +# This file was generated using idf.py save-defconfig. It can be edited manually. +# Espressif IoT Development Framework (ESP-IDF) Project Minimal Configuration +# +CONFIG_BT_ENABLED=y +CONFIG_BT_BLE_50_FEATURES_SUPPORTED=n +CONFIG_BT_BLE_42_FEATURES_SUPPORTED=y +# CONFIG_BT_LE_50_FEATURE_SUPPORT is not used on ESP32, ESP32-C3 and ESP32-S3. +# CONFIG_BT_LE_50_FEATURE_SUPPORT is not set diff --git a/examples/bluetooth/ble_get_started/bluedroid/Bluedroid_Beacon/sdkconfig.defaults.esp32c2 b/examples/bluetooth/ble_get_started/bluedroid/Bluedroid_Beacon/sdkconfig.defaults.esp32c2 new file mode 100644 index 00000000000..0b64f8ea4a6 --- /dev/null +++ b/examples/bluetooth/ble_get_started/bluedroid/Bluedroid_Beacon/sdkconfig.defaults.esp32c2 @@ -0,0 +1,10 @@ +# This file was generated using idf.py save-defconfig. It can be edited manually. +# Espressif IoT Development Framework (ESP-IDF) Project Minimal Configuration +# +CONFIG_IDF_TARGET="esp32c2" +CONFIG_BT_ENABLED=y +# CONFIG_BT_BLE_50_FEATURES_SUPPORTED is not set +CONFIG_BT_BLE_42_FEATURES_SUPPORTED=y +# CONFIG_BT_LE_50_FEATURE_SUPPORT is not set +CONFIG_BT_LE_HCI_EVT_BUF_SIZE=257 +CONFIG_XTAL_FREQ_26=y diff --git a/examples/bluetooth/ble_get_started/bluedroid/Bluedroid_Beacon/sdkconfig.defaults.esp32c3 b/examples/bluetooth/ble_get_started/bluedroid/Bluedroid_Beacon/sdkconfig.defaults.esp32c3 new file mode 100644 index 00000000000..0ad7bbc0aeb --- /dev/null +++ b/examples/bluetooth/ble_get_started/bluedroid/Bluedroid_Beacon/sdkconfig.defaults.esp32c3 @@ -0,0 +1,7 @@ +# This file was generated using idf.py save-defconfig. It can be edited manually. +# Espressif IoT Development Framework (ESP-IDF) Project Minimal Configuration +# +CONFIG_IDF_TARGET="esp32c3" +CONFIG_BT_ENABLED=y +# CONFIG_BT_BLE_50_FEATURES_SUPPORTED is not set +CONFIG_BT_BLE_42_FEATURES_SUPPORTED=y diff --git a/examples/bluetooth/ble_get_started/bluedroid/Bluedroid_Beacon/sdkconfig.defaults.esp32s3 b/examples/bluetooth/ble_get_started/bluedroid/Bluedroid_Beacon/sdkconfig.defaults.esp32s3 new file mode 100644 index 00000000000..2a50f1657bf --- /dev/null +++ b/examples/bluetooth/ble_get_started/bluedroid/Bluedroid_Beacon/sdkconfig.defaults.esp32s3 @@ -0,0 +1,7 @@ +# This file was generated using idf.py save-defconfig. It can be edited manually. +# Espressif IoT Development Framework (ESP-IDF) Project Minimal Configuration +# +CONFIG_IDF_TARGET="esp32s3" +CONFIG_BT_ENABLED=y +# CONFIG_BT_BLE_50_FEATURES_SUPPORTED is not set +CONFIG_BT_BLE_42_FEATURES_SUPPORTED=y diff --git a/examples/bluetooth/ble_get_started/bluedroid/Bluedroid_Connection/CMakeLists.txt b/examples/bluetooth/ble_get_started/bluedroid/Bluedroid_Connection/CMakeLists.txt new file mode 100644 index 00000000000..24a79e64d81 --- /dev/null +++ b/examples/bluetooth/ble_get_started/bluedroid/Bluedroid_Connection/CMakeLists.txt @@ -0,0 +1,6 @@ +# The following lines of boilerplate have to be in your project's CMakeLists +# in this exact order for cmake to work correctly +cmake_minimum_required(VERSION 3.16) + +include($ENV{IDF_PATH}/tools/cmake/project.cmake) +project(bluedroid_connection) diff --git a/examples/bluetooth/ble_get_started/bluedroid/Bluedroid_Connection/README.md b/examples/bluetooth/ble_get_started/bluedroid/Bluedroid_Connection/README.md new file mode 100644 index 00000000000..ced37511d46 --- /dev/null +++ b/examples/bluetooth/ble_get_started/bluedroid/Bluedroid_Connection/README.md @@ -0,0 +1,169 @@ +| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-H2 | ESP32-S3 | +| ----------------- | ----- | -------- | -------- | -------- | -------- | --------- | -------- | -------- | + +# Bluedroid Connection Example + +## Overview + +This example is extended from Bluedroid Beacon Example, and further introduces + +1. How to advertise as a connectable peripheral device +2. How to capture GAP events and handle them +3. How to update connection parameters + +It uses ESP32's Bluetooth controller and Bluedroid host stack. + +To test this demo, any BLE scanner application can be used. + +## Try It Yourself + +### Set Target + +Before project configuration and build, be sure to set the correct chip target using: + +``` shell +idf.py set-target +``` + +For example, if you're using ESP32, then input + +``` Shell +idf.py set-target esp32 +``` + +### Build and Flash + +Run the following command to build, flash and monitor the project. + +``` Shell +idf.py -p flash monitor +``` + +For example, if the corresponding serial port is `/dev/ttyACM0`, then it goes + +``` Shell +idf.py -p /dev/ttyACM0 flash monitor +``` + +(To exit the serial monitor, type ``Ctrl-]``.) + +See the [Getting Started Guide](https://idf.espressif.com/) for full steps to configure and use ESP-IDF to build projects. + +## Code Explained + +### Overview + +1. Initialize NVS flash, Bluedroid host stack, GAP and GATT service; configure Bluedroid Host stack +2. Set advertisement and scan response data, then configure advertising parameters and start advertising +3. On connect event + 1. Print out connection descriptions + 2. Update connection parameters +4. On connection update event + 1. Print out connection descriptions +5. On disconnect event + 1. Print out connection descriptions + +### Entry Point + +Please refer to the Bluedroid Beacon Example for details. + +### Start Advertising + +Please refer to the Bluedroid Beacon Example for details. + +### On GAP & GATT Events + +To keep it simple, we're interested in 1 GAP event and 3 GATT events at the moment + +- `ESP_GATTS_REG_EVT` - GATT service registered event +- `ESP_GATTS_CONNECT_EVT` - GATT connection event +- `ESP_GAP_BLE_UPDATE_CONN_PARAMS_EVT` - Connection update event +- `ESP_GATTS_DISCONNECT_EVT` - GATT disconnection event + +#### Register GATT service + +In `app_main`, we register `gatts_event_handler` function as the callback function for all GATT services by calling `esp_ble_gatts_register_callback`. Then, we need to register a GATT server application with application ID 0 by calling `esp_ble_gatts_app_register` + +``` C +void app_main(void) +{ + ... + ret = esp_ble_gap_register_callback(esp_gap_cb); + if (ret) { + ESP_LOGE(CONN_TAG, "%s gap register failed, error code = %x", __func__, ret); + return; + } + + ret = esp_ble_gatts_register_callback(gatts_event_handler); + if (ret) { + ESP_LOGE(CONN_TAG, "%s gatts register failed, error code = %x", __func__, ret); + return; + } + ... +} +``` +#### Connect Event + +When the device is connected to a peer device, a connect event will be passed to `gatts_event_handler` by Bluedroid host stack. Once connection has been established, we will call `esp_ble_gap_update_conn_params` to update connection parameters. +``` C +static void gatts_event_handler(esp_gatts_cb_event_t event, esp_gatt_if_t gatts_if, esp_ble_gatts_cb_param_t *param) +{ + ... + case ESP_GATTS_CONNECT_EVT: + esp_ble_conn_update_params_t conn_params = {0}; + memcpy(conn_params.bda, param->connect.remote_bda, sizeof(esp_bd_addr_t)); + conn_params.latency = 0; + conn_params.max_int = 0x20; + conn_params.min_int = 0x10; + conn_params.timeout = 400; + ESP_LOGI(CONN_TAG, "Connected, conn_id %u, remote "ESP_BD_ADDR_STR"", + param->connect.conn_id, ESP_BD_ADDR_HEX(param->connect.remote_bda)); + esp_ble_gap_update_conn_params(&conn_params); + break; + ... +} +``` + +#### Connection Update Event + +When connection parameters are updated, an `ESP_GAP_BLE_UPDATE_CONN_PARAMS_EVT` will be passed to `esp_gap_cb` by Bluedroid host stack. +``` C +static void esp_gap_cb(esp_gap_ble_cb_event_t event, esp_ble_gap_cb_param_t *param) +{ + ... + case ESP_GAP_BLE_UPDATE_CONN_PARAMS_EVT: + ESP_LOGI(CONN_TAG, "Connection params update, status %d, conn_int %d, latency %d, timeout %d", + param->update_conn_params.status, + param->update_conn_params.conn_int, + param->update_conn_params.latency, + param->update_conn_params.timeout); + break; + ... +} +``` +#### Disconnect Event + +On `ESP_GATTS_DISCONNECT_EVT`, we simply + +1. Print out disconnect reason and connection descriptor +2. Re-start advertising + +``` C +static void gatts_event_handler(esp_gatts_cb_event_t event, esp_gatt_if_t gatts_if, esp_ble_gatts_cb_param_t *param) +{ + ... + case ESP_GATTS_DISCONNECT_EVT: + ESP_LOGI(CONN_TAG, "Disconnected, remote "ESP_BD_ADDR_STR", reason 0x%02x", + ESP_BD_ADDR_HEX(param->disconnect.remote_bda), param->disconnect.reason); + esp_ble_gap_start_advertising(&adv_params); + break; + ... +} +``` +## Observation + +If everything goes well, except for what we have seen in Bluedroid Beacon example, you should be able to connect to and disconnect from the device successfully. + +## Troubleshooting + +For any technical queries, please file an [issue](https://github.com/espressif/esp-idf/issues) on GitHub. We will get back to you soon. \ No newline at end of file diff --git a/examples/bluetooth/ble_get_started/bluedroid/Bluedroid_Connection/main/CMakeLists.txt b/examples/bluetooth/ble_get_started/bluedroid/Bluedroid_Connection/main/CMakeLists.txt new file mode 100644 index 00000000000..cf2c455cb50 --- /dev/null +++ b/examples/bluetooth/ble_get_started/bluedroid/Bluedroid_Connection/main/CMakeLists.txt @@ -0,0 +1,2 @@ +idf_component_register(SRCS "main.c" + INCLUDE_DIRS ".") diff --git a/examples/bluetooth/ble_get_started/bluedroid/Bluedroid_Connection/main/Kconfig.projbuild b/examples/bluetooth/ble_get_started/bluedroid/Bluedroid_Connection/main/Kconfig.projbuild new file mode 100644 index 00000000000..b597b63196f --- /dev/null +++ b/examples/bluetooth/ble_get_started/bluedroid/Bluedroid_Connection/main/Kconfig.projbuild @@ -0,0 +1,14 @@ +menu "Example 'GATT SERVER' Config" + + config EXAMPLE_SET_RAW_ADV_DATA + bool "Use raw data for advertising packets and scan response data" + help + If this config item is set, raw binary data will be used to generate advertising & scan response data. + This option uses the esp_ble_gap_config_adv_data_raw() and esp_ble_gap_config_scan_rsp_data_raw() + functions. + + If this config item is unset, advertising & scan response data is provided via a higher-level + esp_ble_adv_data_t structure. The lower layer will generate the BLE packets. This option has higher + overhead at runtime. + +endmenu diff --git a/examples/bluetooth/ble_get_started/bluedroid/Bluedroid_Connection/main/main.c b/examples/bluetooth/ble_get_started/bluedroid/Bluedroid_Connection/main/main.c new file mode 100644 index 00000000000..07c6489e260 --- /dev/null +++ b/examples/bluetooth/ble_get_started/bluedroid/Bluedroid_Connection/main/main.c @@ -0,0 +1,180 @@ +/* + * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Unlicense OR CC0-1.0 + */ +#include +#include +#include +#include +#include "freertos/FreeRTOS.h" +#include "freertos/task.h" +#include "freertos/event_groups.h" +#include "esp_system.h" +#include "esp_log.h" +#include "nvs_flash.h" +#include "esp_bt.h" + +#include "esp_gap_ble_api.h" +#include "esp_gatts_api.h" +#include "esp_bt_defs.h" +#include "esp_bt_main.h" +#include "esp_bt_device.h" +#include "esp_gatt_common_api.h" + +#define APP_ID_PLACEHOLDER 0 + +static void esp_gap_cb(esp_gap_ble_cb_event_t event, esp_ble_gap_cb_param_t *param); +static void gatts_event_handler(esp_gatts_cb_event_t event, esp_gatt_if_t gatts_if, esp_ble_gatts_cb_param_t *param); + +static const char *CONN_TAG = "CONN_DEMO"; +static const char device_name[] = "Bluedroid_Conn"; + +static esp_ble_adv_params_t adv_params = { + .adv_int_min = 0x20, // 20ms + .adv_int_max = 0x20, // 20ms + .adv_type = ADV_TYPE_IND, + .own_addr_type = BLE_ADDR_TYPE_PUBLIC, + .channel_map = ADV_CHNL_ALL, + .adv_filter_policy = ADV_FILTER_ALLOW_SCAN_ANY_CON_ANY, +}; + +static uint8_t adv_raw_data[] = { + 0x02, ESP_BLE_AD_TYPE_FLAG, 0x06, + 0x0F, ESP_BLE_AD_TYPE_NAME_CMPL, 'B', 'l', 'u', 'e', 'd', 'r', 'o', 'i', 'd', '_', 'C', 'o', 'n', 'n', + 0x02, ESP_BLE_AD_TYPE_TX_PWR, 0x09, +}; + +void app_main(void) +{ + esp_err_t ret; + + //initialize NVS + ret = nvs_flash_init(); + if (ret == ESP_ERR_NVS_NO_FREE_PAGES || ret == ESP_ERR_NVS_NEW_VERSION_FOUND) { + ESP_ERROR_CHECK(nvs_flash_erase()); + ret = nvs_flash_init(); + } + ESP_ERROR_CHECK( ret ); + + ESP_ERROR_CHECK(esp_bt_controller_mem_release(ESP_BT_MODE_CLASSIC_BT)); + esp_bt_controller_config_t bt_cfg = BT_CONTROLLER_INIT_CONFIG_DEFAULT(); + ret = esp_bt_controller_init(&bt_cfg); + if (ret) { + ESP_LOGE(CONN_TAG, "%s initialize controller failed: %s", __func__, esp_err_to_name(ret)); + return; + } + + ret = esp_bt_controller_enable(ESP_BT_MODE_BLE); + if (ret) { + ESP_LOGE(CONN_TAG, "%s enable controller failed: %s", __func__, esp_err_to_name(ret)); + return; + } + + ret = esp_bluedroid_init(); + if (ret) { + ESP_LOGE(CONN_TAG, "%s init bluetooth failed: %s", __func__, esp_err_to_name(ret)); + return; + } + + ret = esp_bluedroid_enable(); + if (ret) { + ESP_LOGE(CONN_TAG, "%s enable bluetooth failed: %s", __func__, esp_err_to_name(ret)); + return; + } + + ret = esp_ble_gap_register_callback(esp_gap_cb); + if (ret) { + ESP_LOGE(CONN_TAG, "%s gap register failed, error code = %x", __func__, ret); + return; + } + + ret = esp_ble_gatts_register_callback(gatts_event_handler); + if (ret) { + ESP_LOGE(CONN_TAG, "%s gatts register failed, error code = %x", __func__, ret); + return; + } + + ret = esp_ble_gatts_app_register(APP_ID_PLACEHOLDER); + if (ret) { + ESP_LOGE(CONN_TAG, "%s gatts app register failed, error code = %x", __func__, ret); + return; + } + + ret = esp_ble_gatt_set_local_mtu(500); + if (ret) { + ESP_LOGE(CONN_TAG, "set local MTU failed, error code = %x", ret); + return; + } + + ret = esp_ble_gap_set_device_name(device_name); + if (ret) { + ESP_LOGE(CONN_TAG, "set device name failed, error code = %x", ret); + return; + } + + ret = esp_ble_gap_config_adv_data_raw(adv_raw_data, sizeof(adv_raw_data)); + if (ret) { + ESP_LOGE(CONN_TAG, "config adv data failed, error code = %x", ret); + } +} + +static void esp_gap_cb(esp_gap_ble_cb_event_t event, esp_ble_gap_cb_param_t *param) +{ + switch (event) { + case ESP_GAP_BLE_ADV_DATA_RAW_SET_COMPLETE_EVT: + ESP_LOGI(CONN_TAG, "Advertising data set, status %d", param->adv_data_raw_cmpl.status); + esp_ble_gap_start_advertising(&adv_params); + break; + case ESP_GAP_BLE_ADV_START_COMPLETE_EVT: + if (param->adv_start_cmpl.status != ESP_BT_STATUS_SUCCESS) { + ESP_LOGE(CONN_TAG, "Advertising start failed, status %d", param->adv_start_cmpl.status); + break; + } + ESP_LOGI(CONN_TAG, "Advertising start successfully"); + break; + case ESP_GAP_BLE_ADV_STOP_COMPLETE_EVT: + if (param->adv_stop_cmpl.status != ESP_BT_STATUS_SUCCESS) { + ESP_LOGE(CONN_TAG, "Advertising stop failed, status %d", param->adv_stop_cmpl.status); + } + ESP_LOGI(CONN_TAG, "Advertising stop successfully"); + break; + case ESP_GAP_BLE_UPDATE_CONN_PARAMS_EVT: + ESP_LOGI(CONN_TAG, "Connection params update, status %d, conn_int %d, latency %d, timeout %d", + param->update_conn_params.status, + param->update_conn_params.conn_int, + param->update_conn_params.latency, + param->update_conn_params.timeout); + break; + default: + break; + } +} + +//because we only have one profile table in this demo, there is only one set of gatts evemt handler +static void gatts_event_handler(esp_gatts_cb_event_t event, esp_gatt_if_t gatts_if, esp_ble_gatts_cb_param_t *param) +{ + switch (event) { + case ESP_GATTS_REG_EVT: + ESP_LOGI(CONN_TAG, "GATT server register, status %d, app_id %d", param->reg.status, param->reg.app_id); + break; + case ESP_GATTS_CONNECT_EVT: + esp_ble_conn_update_params_t conn_params = {0}; + memcpy(conn_params.bda, param->connect.remote_bda, sizeof(esp_bd_addr_t)); + conn_params.latency = 0; + conn_params.max_int = 0x20; + conn_params.min_int = 0x10; + conn_params.timeout = 400; + ESP_LOGI(CONN_TAG, "Connected, conn_id %u, remote "ESP_BD_ADDR_STR"", + param->connect.conn_id, ESP_BD_ADDR_HEX(param->connect.remote_bda)); + esp_ble_gap_update_conn_params(&conn_params); + break; + case ESP_GATTS_DISCONNECT_EVT: + ESP_LOGI(CONN_TAG, "Disconnected, remote "ESP_BD_ADDR_STR", reason 0x%02x", + ESP_BD_ADDR_HEX(param->disconnect.remote_bda), param->disconnect.reason); + esp_ble_gap_start_advertising(&adv_params); + break; + default: + break; + } +} diff --git a/examples/bluetooth/ble_get_started/bluedroid/Bluedroid_Connection/sdkconfig.defaults b/examples/bluetooth/ble_get_started/bluedroid/Bluedroid_Connection/sdkconfig.defaults new file mode 100644 index 00000000000..73d84284854 --- /dev/null +++ b/examples/bluetooth/ble_get_started/bluedroid/Bluedroid_Connection/sdkconfig.defaults @@ -0,0 +1,8 @@ +# This file was generated using idf.py save-defconfig. It can be edited manually. +# Espressif IoT Development Framework (ESP-IDF) Project Minimal Configuration +# +CONFIG_BT_ENABLED=y +CONFIG_BT_BLE_50_FEATURES_SUPPORTED=n +CONFIG_BT_BLE_42_FEATURES_SUPPORTED=y +# CONFIG_BT_LE_50_FEATURE_SUPPORT is not used on ESP32, ESP32-C3 and ESP32-S3. +# CONFIG_BT_LE_50_FEATURE_SUPPORT is not set diff --git a/examples/bluetooth/ble_get_started/bluedroid/Bluedroid_Connection/sdkconfig.defaults.esp32c2 b/examples/bluetooth/ble_get_started/bluedroid/Bluedroid_Connection/sdkconfig.defaults.esp32c2 new file mode 100644 index 00000000000..be57b48006c --- /dev/null +++ b/examples/bluetooth/ble_get_started/bluedroid/Bluedroid_Connection/sdkconfig.defaults.esp32c2 @@ -0,0 +1,9 @@ +# Override some defaults so BT stack is enabled +# by default in this example +CONFIG_IDF_TARGET="esp32c2" +CONFIG_BT_ENABLED=y +# CONFIG_BT_BLE_50_FEATURES_SUPPORTED is not set +CONFIG_BT_BLE_42_FEATURES_SUPPORTED=y +# CONFIG_BT_LE_50_FEATURE_SUPPORT is not set +CONFIG_BT_LE_HCI_EVT_BUF_SIZE=257 +CONFIG_XTAL_FREQ_26=y diff --git a/examples/bluetooth/ble_get_started/bluedroid/Bluedroid_Connection/sdkconfig.defaults.esp32c3 b/examples/bluetooth/ble_get_started/bluedroid/Bluedroid_Connection/sdkconfig.defaults.esp32c3 new file mode 100644 index 00000000000..0ad7bbc0aeb --- /dev/null +++ b/examples/bluetooth/ble_get_started/bluedroid/Bluedroid_Connection/sdkconfig.defaults.esp32c3 @@ -0,0 +1,7 @@ +# This file was generated using idf.py save-defconfig. It can be edited manually. +# Espressif IoT Development Framework (ESP-IDF) Project Minimal Configuration +# +CONFIG_IDF_TARGET="esp32c3" +CONFIG_BT_ENABLED=y +# CONFIG_BT_BLE_50_FEATURES_SUPPORTED is not set +CONFIG_BT_BLE_42_FEATURES_SUPPORTED=y diff --git a/examples/bluetooth/ble_get_started/bluedroid/Bluedroid_Connection/sdkconfig.defaults.esp32s3 b/examples/bluetooth/ble_get_started/bluedroid/Bluedroid_Connection/sdkconfig.defaults.esp32s3 new file mode 100644 index 00000000000..2a50f1657bf --- /dev/null +++ b/examples/bluetooth/ble_get_started/bluedroid/Bluedroid_Connection/sdkconfig.defaults.esp32s3 @@ -0,0 +1,7 @@ +# This file was generated using idf.py save-defconfig. It can be edited manually. +# Espressif IoT Development Framework (ESP-IDF) Project Minimal Configuration +# +CONFIG_IDF_TARGET="esp32s3" +CONFIG_BT_ENABLED=y +# CONFIG_BT_BLE_50_FEATURES_SUPPORTED is not set +CONFIG_BT_BLE_42_FEATURES_SUPPORTED=y diff --git a/examples/bluetooth/ble_get_started/bluedroid/Bluedroid_GATT_Server/CMakeLists.txt b/examples/bluetooth/ble_get_started/bluedroid/Bluedroid_GATT_Server/CMakeLists.txt new file mode 100644 index 00000000000..c4b8cc75f8c --- /dev/null +++ b/examples/bluetooth/ble_get_started/bluedroid/Bluedroid_GATT_Server/CMakeLists.txt @@ -0,0 +1,6 @@ +# The following lines of boilerplate have to be in your project's CMakeLists +# in this exact order for cmake to work correctly +cmake_minimum_required(VERSION 3.16) + +include($ENV{IDF_PATH}/tools/cmake/project.cmake) +project(bluedroid_gatt_server) diff --git a/examples/bluetooth/ble_get_started/bluedroid/Bluedroid_GATT_Server/README.md b/examples/bluetooth/ble_get_started/bluedroid/Bluedroid_GATT_Server/README.md new file mode 100644 index 00000000000..96b33a5a9b7 --- /dev/null +++ b/examples/bluetooth/ble_get_started/bluedroid/Bluedroid_GATT_Server/README.md @@ -0,0 +1,325 @@ +| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-H2 | ESP32-S3 | +| ----------------- | ----- | -------- | -------- | -------- | -------- | --------- | -------- | -------- | + +# Bluedroid GATT Server Example + +## Overview + +This example is extended from Bluedroid Connection Example, and further introduces + +1. How to implement a GATT server +2. How to handle characteristic access requests + 1. Write access demonstrated by LED control + 2. Read and indicate access demonstrated by heart rate measurement(mocked) + +It uses ESP32's Bluetooth controller and Bluedroid host stack. + +To test this demo, any BLE scanner application can be used. + +## Try It Yourself + +### Set Target + +Before project configuration and build, be sure to set the correct chip target using: + +``` shell +idf.py set-target +``` + +For example, if you're using ESP32, then input + +``` Shell +idf.py set-target esp32 +``` + +### Build and Flash + +Run the following command to build, flash and monitor the project. + +``` Shell +idf.py -p flash monitor +``` + +For example, if the corresponding serial port is `/dev/ttyACM0`, then it goes + +``` Shell +idf.py -p /dev/ttyACM0 flash monitor +``` + +(To exit the serial monitor, type ``Ctrl-]``.) + +See the [Getting Started Guide](https://idf.espressif.com/) for full steps to configure and use ESP-IDF to build projects. + +## Code Explained + +### Overview + +1. Initialization + 1. Initialize LED, NVS flash, Bluedroid Host stack, GAP service + 2. Initialize GATT service and register primary services and characteristics + 3. Start heart rate update task thread +2. Wait for Bluedroid host stack to start advertising; wait for connection event to come +3. After connection established, wait for GATT characteristics access events to come + 1. On write LED event, turn on or off the LED accordingly + 2. On read heart rate event, send out current heart rate measurement value + 3. On indicate heart rate event, enable heart rate indication + +### Entry Point + +In this example, we have two GATT service profiles, the heart rate profile and the LED control profile. The heart rate profile is used to mock a heart rate measurement, and the LED control profile is used to control the LED on the ESP32 board. Thus, we need to register two application IDs in total for two GATT service profiles. + +``` C +void app_main(void) +{ + ... + ret = esp_ble_gatts_app_register(HEART_PROFILE_APP_ID); + if (ret) { + ESP_LOGE(GATTS_TAG, "app register error, error code = %x", ret); + return; + } + + ret = esp_ble_gatts_app_register(AUTO_IO_PROFILE_APP_ID); + if (ret) { + ESP_LOGE(GATTS_TAG, "app register error, error code = %x", ret); + return; + } + ... +} +``` + +Then, after Bluedroid host task has been initialized, we'll create another task defined in `heart_rate_task` to update heart rate measurement mock value and send indication if enabled. + +### GATT Services + +In this example, there are two GATT primary services defined + +- Heart rate service with a UUID of `0x180D` +- Automation IO service with a UUID of `0x1815` + +The characteristics and characteristic descriptors are added sequentially triggered by GATT events. + +After the heart rate service has been successfully initialized, we will start a task to mock a heart rate measurement in one second interval. This measurement will be updated to the heart rate measurement characteristic value. + +``` C +static void heart_gatts_profile_event_handler(esp_gatts_cb_event_t event, esp_gatt_if_t gatts_if, esp_ble_gatts_cb_param_t *param) +{ + ... + case ESP_GATTS_REG_EVT: + ESP_LOGI(GATTS_TAG, "GATT server register, status %d, app_id %d", param->reg.status, param->reg.app_id); + gl_profile_tab[HEART_PROFILE_APP_ID].service_id.is_primary = true; + gl_profile_tab[HEART_PROFILE_APP_ID].service_id.id.inst_id = 0x00; + gl_profile_tab[HEART_PROFILE_APP_ID].service_id.id.uuid.len = ESP_UUID_LEN_16; + gl_profile_tab[HEART_PROFILE_APP_ID].service_id.id.uuid.uuid.uuid16 = HEART_RATE_SVC_UUID; + + //config adv data + esp_err_t ret = esp_ble_gap_config_adv_data(&adv_data); + if(ret){ + ESP_LOGE(GATTS_TAG, "config adv data failed, error code = %x", ret); + break; + } + + esp_ble_gatts_create_service(gatts_if, &gl_profile_tab[HEART_PROFILE_APP_ID].service_id, HEART_NUM_HANDLE); + break; + case ESP_GATTS_CREATE_EVT: + //service has been created, now add characteristic declaration + ESP_LOGI(GATTS_TAG, "Service create, status %d, service_handle %d", param->create.status, param->create.service_handle); + gl_profile_tab[HEART_PROFILE_APP_ID].service_handle = param->create.service_handle; + gl_profile_tab[HEART_PROFILE_APP_ID].char_uuid.len = ESP_UUID_LEN_16; + gl_profile_tab[HEART_PROFILE_APP_ID].char_uuid.uuid.uuid16 = HEART_RATE_CHAR_UUID; + esp_ble_gatts_start_service(gl_profile_tab[HEART_PROFILE_APP_ID].service_handle); + heart_property = ESP_GATT_CHAR_PROP_BIT_READ | ESP_GATT_CHAR_PROP_BIT_INDICATE; + ret = esp_ble_gatts_add_char(gl_profile_tab[HEART_PROFILE_APP_ID].service_handle, &gl_profile_tab[HEART_PROFILE_APP_ID].char_uuid, + ESP_GATT_PERM_READ, + heart_property, + &heart_rate_attr, NULL); + if (ret) { + ESP_LOGE(GATTS_TAG, "add char failed, error code = %x", ret); + } + break; + case ESP_GATTS_ADD_CHAR_EVT: + ESP_LOGI(GATTS_TAG, "Characteristic add, status %d, attr_handle %d, char_uuid %x", + param->add_char.status, param->add_char.attr_handle, param->add_char.char_uuid.uuid.uuid16); + gl_profile_tab[HEART_PROFILE_APP_ID].char_handle = param->add_char.attr_handle; + gl_profile_tab[HEART_PROFILE_APP_ID].descr_uuid.len = ESP_UUID_LEN_16; + gl_profile_tab[HEART_PROFILE_APP_ID].descr_uuid.uuid.uuid16 = ESP_GATT_UUID_CHAR_CLIENT_CONFIG; + ESP_LOGI(GATTS_TAG, "heart rate char handle %d", param->add_char.attr_handle); + ret = esp_ble_gatts_add_char_descr(gl_profile_tab[HEART_PROFILE_APP_ID].service_handle, &gl_profile_tab[HEART_PROFILE_APP_ID].descr_uuid, + ESP_GATT_PERM_READ | ESP_GATT_PERM_WRITE, NULL, NULL); + break; + case ESP_GATTS_ADD_CHAR_DESCR_EVT: + ESP_LOGI(GATTS_TAG, "Descriptor add, status %d, attr_handle %u", + param->add_char_descr.status, param->add_char_descr.attr_handle); + gl_profile_tab[HEART_PROFILE_APP_ID].descr_handle = param->add_char_descr.attr_handle; + xTaskCreate(heart_rate_task, "Heart Rate", 2 * 1024, NULL, 5, NULL); + break; + ... +} + +static void auto_io_gatts_profile_event_handler(esp_gatts_cb_event_t event, esp_gatt_if_t gatts_if, esp_ble_gatts_cb_param_t *param) +{ + ... + case ESP_GATTS_REG_EVT: + ESP_LOGI(GATTS_TAG, "GATT server register, status %d, app_id %d", param->reg.status, param->reg.app_id); + gl_profile_tab[AUTO_IO_PROFILE_APP_ID].service_id.is_primary = true; + gl_profile_tab[AUTO_IO_PROFILE_APP_ID].service_id.id.inst_id = 0x00; + gl_profile_tab[AUTO_IO_PROFILE_APP_ID].service_id.id.uuid.len = ESP_UUID_LEN_16; + gl_profile_tab[AUTO_IO_PROFILE_APP_ID].service_id.id.uuid.uuid.uuid16 = AUTO_IO_SVC_UUID; + esp_ble_gatts_create_service(gatts_if, &gl_profile_tab[AUTO_IO_PROFILE_APP_ID].service_id, AUTO_IO_NUM_HANDLE); + break; + case ESP_GATTS_CREATE_EVT: + //service has been created, now add characteristic declaration + ESP_LOGI(GATTS_TAG, "Service create, status %d, service_handle %d", param->create.status, param->create.service_handle); + gl_profile_tab[AUTO_IO_PROFILE_APP_ID].service_handle = param->create.service_handle; + gl_profile_tab[AUTO_IO_PROFILE_APP_ID].char_uuid.len = ESP_UUID_LEN_128; + memcpy(gl_profile_tab[AUTO_IO_PROFILE_APP_ID].char_uuid.uuid.uuid128, led_chr_uuid, ESP_UUID_LEN_128); + + esp_ble_gatts_start_service(gl_profile_tab[AUTO_IO_PROFILE_APP_ID].service_handle); + auto_io_property = ESP_GATT_CHAR_PROP_BIT_WRITE ; + esp_err_t ret = esp_ble_gatts_add_char(gl_profile_tab[AUTO_IO_PROFILE_APP_ID].service_handle, &gl_profile_tab[AUTO_IO_PROFILE_APP_ID].char_uuid, + ESP_GATT_PERM_READ | ESP_GATT_PERM_WRITE , + auto_io_property, + &led_status_attr, NULL); + if (ret) { + ESP_LOGE(GATTS_TAG, "add char failed, error code = %x", ret); + } + break; + case ESP_GATTS_ADD_CHAR_EVT: + ESP_LOGI(GATTS_TAG, "Characteristic add, status %d, attr_handle %d, char_uuid %x", + param->add_char.status, param->add_char.attr_handle, param->add_char.char_uuid.uuid.uuid16); + gl_profile_tab[AUTO_IO_PROFILE_APP_ID].char_handle = param->add_char.attr_handle; + break; + case ESP_GATTS_ADD_CHAR_DESCR_EVT: + ESP_LOGI(GATTS_TAG, "Descriptor add, status %d", param->add_char_descr.status); + gl_profile_tab[AUTO_IO_PROFILE_APP_ID].descr_handle = param->add_char_descr.attr_handle; + break; + ... +} +``` + +#### Automation IO Service + +Under automation IO service, there's a LED characteristic, with a vendor-specific 128-bit UUID `led_chr_uuid` and read/write permission. + +When a value is written to the characteristic, Bluedroid Host will trigger an `ESP_GATTS_WRITE_EVT`. If the written value is `1`, the LED will be turned on. Otherwise, the LED will be turned off. + +``` C +static void auto_io_gatts_profile_event_handler(esp_gatts_cb_event_t event, esp_gatt_if_t gatts_if, esp_ble_gatts_cb_param_t *param) +{ + ... + case ESP_GATTS_WRITE_EVT: + ESP_LOGI(GATTS_TAG, "Characteristic write, value len %u, value ", param->write.len); + ESP_LOG_BUFFER_HEX(GATTS_TAG, param->write.value, param->write.len); + if (param->write.value[0]) { + ESP_LOGI(GATTS_TAG, "LED ON!"); + led_on(); + } else { + ESP_LOGI(GATTS_TAG, "LED OFF!"); + led_off(); + } + example_write_event_env(gatts_if, param); + break; + ... +} + +void example_write_event_env(esp_gatt_if_t gatts_if, esp_ble_gatts_cb_param_t *param) +{ + esp_gatt_status_t status = ESP_GATT_OK; + if (param->write.need_rsp) { + esp_ble_gatts_send_response(gatts_if, param->write.conn_id, param->write.trans_id, status, NULL); + } +} + +``` + + +#### Heart Rate Service +Under heart rate service, there's a heart rate measurement characteristic, with a standard UUID `0x2A37` and read/indicate permission. Under the heart rate characteristic, there is also a characteristic client config descriptor with UUID `0x2902` with read/write permissions. This descriptor is used to control whether the characteristic should be notified/indicated or not. + +All read and write requests to the heart rate service will be handled by calling `heart_gatts_profile_event_handler`. + 1. When an `ESP_GATTS_READ_EVT` occurs, we will send a response to the client identified by the connection id with the latest heart rate measurement mock value. + 2. When an `ESP_GATTS_WRITE_EVT` occurs, we will first determine if the write target is the characteristic client config descriptor. If it is, we will update the notify/indicate flag of the heart rate characteristic. + 3. If the indicate flag is set, whenever there's an update on the charatertistic value, we will send an indication containing the heart rate measurement data to the client identified by the connection id. + +``` C + +static void heart_gatts_profile_event_handler(esp_gatts_cb_event_t event, esp_gatt_if_t gatts_if, esp_ble_gatts_cb_param_t *param) +{ + ... + case ESP_GATTS_READ_EVT: + ESP_LOGI(GATTS_TAG, "Characteristic read"); + esp_gatt_rsp_t rsp; + memset(&rsp, 0, sizeof(esp_gatt_rsp_t)); + rsp.attr_value.handle = param->read.handle; + rsp.attr_value.len = 2; + memcpy(rsp.attr_value.value, heart_rate_val, sizeof(heart_rate_val)); + esp_ble_gatts_send_response(gatts_if, param->read.conn_id, param->read.trans_id, ESP_GATT_OK, &rsp); + break; + case ESP_GATTS_WRITE_EVT: + ESP_LOGI(GATTS_TAG, "Characteristic write, value len %u, value ", param->write.len); + ESP_LOG_BUFFER_HEX(GATTS_TAG, param->write.value, param->write.len); + + if (gl_profile_tab[HEART_PROFILE_APP_ID].descr_handle == param->write.handle && param->write.len == 2){ + uint16_t descr_value = param->write.value[1]<<8 | param->write.value[0]; + if (descr_value == 0x0001){ + if (heart_property & ESP_GATT_CHAR_PROP_BIT_NOTIFY){ + ESP_LOGI(GATTS_TAG, "Notification enable"); + uint8_t notify_data[15]; + for (int i = 0; i < sizeof(notify_data); ++i) + { + notify_data[i] = i%0xff; + } + //the size of notify_data[] need less than MTU size + esp_ble_gatts_send_indicate(gatts_if, param->write.conn_id, gl_profile_tab[HEART_PROFILE_APP_ID].char_handle, + sizeof(notify_data), notify_data, false); + } + }else if (descr_value == 0x0002){ + if (heart_property & ESP_GATT_CHAR_PROP_BIT_INDICATE){ + ESP_LOGI(GATTS_TAG, "Indication enable"); + indicate_enabled = true; + uint8_t indicate_data[15]; + for (int i = 0; i < sizeof(indicate_data); ++i) + { + indicate_data[i] = i%0xff; + } + //the size of indicate_data[] need less than MTU size + esp_ble_gatts_send_indicate(gatts_if, param->write.conn_id, gl_profile_tab[HEART_PROFILE_APP_ID].char_handle, + sizeof(indicate_data), indicate_data, true); + } + } + else if (descr_value == 0x0000) { + indicate_enabled = false; + ESP_LOGI(GATTS_TAG, "Notification/Indication disable"); + } else { + ESP_LOGE(GATTS_TAG, "Unknown descriptor value"); + ESP_LOG_BUFFER_HEX(GATTS_TAG, param->write.value, param->write.len); + } + } + example_write_event_env(gatts_if, param); + break; + case ESP_GATTS_SET_ATTR_VAL_EVT: + ESP_LOGI(GATTS_TAG, "Attribute value set, status %d", param->set_attr_val.status); + if(indicate_enabled){ + uint8_t indicate_data[2] = {0}; + memcpy(indicate_data, heart_rate_val, sizeof(heart_rate_val)); + esp_ble_gatts_send_indicate(gatts_if, gl_profile_tab[HEART_PROFILE_APP_ID].conn_id, gl_profile_tab[HEART_PROFILE_APP_ID].char_handle, sizeof(indicate_data), indicate_data, true); + } + break; + ... +} +``` +## Observation + +If everything goes well, you should be able to see 4 services when connected to ESP32, including + +- Generic Access Service +- Generic Attribute Service +- Heart Rate Service +- Automation IO Service + +Click on Automation IO Service, you should be able to see LED characteristic. Click on upload button, you should be able to write `ON` or `OFF` value. Send it to the device, LED will be turned on or off following your instruction. + +Click on Heart Rate Service, you should be able to see Heart Rate Measurement characteristic. Click on download button, you should be able to see the latest heart rate measurement mock value, and it should be consistent with what is shown on serial output. Click on subscribe button, you should be able to see the heart rate measurement mock value updated every second. + +## Troubleshooting + +For any technical queries, please file an [issue](https://github.com/espressif/esp-idf/issues) on GitHub. We will get back to you soon. \ No newline at end of file diff --git a/examples/bluetooth/ble_get_started/bluedroid/Bluedroid_GATT_Server/main/CMakeLists.txt b/examples/bluetooth/ble_get_started/bluedroid/Bluedroid_GATT_Server/main/CMakeLists.txt new file mode 100644 index 00000000000..58411132997 --- /dev/null +++ b/examples/bluetooth/ble_get_started/bluedroid/Bluedroid_GATT_Server/main/CMakeLists.txt @@ -0,0 +1,4 @@ +file(GLOB_RECURSE srcs "main.c" "src/*.c") + +idf_component_register(SRCS "${srcs}" + INCLUDE_DIRS "./include") diff --git a/examples/bluetooth/ble_get_started/bluedroid/Bluedroid_GATT_Server/main/Kconfig.projbuild b/examples/bluetooth/ble_get_started/bluedroid/Bluedroid_GATT_Server/main/Kconfig.projbuild new file mode 100644 index 00000000000..5afb570a0b0 --- /dev/null +++ b/examples/bluetooth/ble_get_started/bluedroid/Bluedroid_GATT_Server/main/Kconfig.projbuild @@ -0,0 +1,54 @@ +menu "Example 'GATT SERVER' Config" + + config EXAMPLE_SET_RAW_ADV_DATA + bool "Use raw data for advertising packets and scan response data" + help + If this config item is set, raw binary data will be used to generate advertising & scan response data. + This option uses the esp_ble_gap_config_adv_data_raw() and esp_ble_gap_config_scan_rsp_data_raw() + functions. + + If this config item is unset, advertising & scan response data is provided via a higher-level + esp_ble_adv_data_t structure. The lower layer will generate the BLE packets. This option has higher + overhead at runtime. + + orsource "$IDF_PATH/examples/common_components/env_caps/$IDF_TARGET/Kconfig.env_caps" + + choice EXAMPLE_BLINK_LED + prompt "Blink LED type" + default EXAMPLE_BLINK_LED_STRIP + help + Select the LED type. A normal level controlled LED or an addressable LED strip. + The default selection is based on the Espressif DevKit boards. + You can change the default selection according to your board. + + config EXAMPLE_BLINK_LED_GPIO + bool "GPIO" + config EXAMPLE_BLINK_LED_STRIP + bool "LED strip" + endchoice + + choice EXAMPLE_BLINK_LED_STRIP_BACKEND + depends on EXAMPLE_BLINK_LED_STRIP + prompt "LED strip backend peripheral" + default EXAMPLE_BLINK_LED_STRIP_BACKEND_RMT if SOC_RMT_SUPPORTED + default EXAMPLE_BLINK_LED_STRIP_BACKEND_SPI + help + Select the backend peripheral to drive the LED strip. + + config EXAMPLE_BLINK_LED_STRIP_BACKEND_RMT + depends on SOC_RMT_SUPPORTED + bool "RMT" + config EXAMPLE_BLINK_LED_STRIP_BACKEND_SPI + bool "SPI" + endchoice + + config EXAMPLE_BLINK_GPIO + int "Blink GPIO number" + range ENV_GPIO_RANGE_MIN ENV_GPIO_OUT_RANGE_MAX + default 8 + help + GPIO number (IOxx) to blink on and off the LED. + Some GPIOs are used for other purposes (flash connections, etc.) and cannot be used to blink. + + +endmenu diff --git a/examples/bluetooth/ble_get_started/bluedroid/Bluedroid_GATT_Server/main/idf_component.yml b/examples/bluetooth/ble_get_started/bluedroid/Bluedroid_GATT_Server/main/idf_component.yml new file mode 100644 index 00000000000..fbf50c7abf5 --- /dev/null +++ b/examples/bluetooth/ble_get_started/bluedroid/Bluedroid_GATT_Server/main/idf_component.yml @@ -0,0 +1,17 @@ +## IDF Component Manager Manifest File +dependencies: + espressif/led_strip: "*" + ## Required IDF version + idf: + version: ">=4.1.0" + # # Put list of dependencies here + # # For components maintained by Espressif: + # component: "~1.0.0" + # # For 3rd party components: + # username/component: ">=1.0.0,<2.0.0" + # username2/component2: + # version: "~1.0.0" + # # For transient dependencies `public` flag can be set. + # # `public` flag doesn't have an effect dependencies of the `main` component. + # # All dependencies of `main` are public by default. + # public: true diff --git a/examples/bluetooth/ble_get_started/bluedroid/Bluedroid_GATT_Server/main/include/heart_rate.h b/examples/bluetooth/ble_get_started/bluedroid/Bluedroid_GATT_Server/main/include/heart_rate.h new file mode 100644 index 00000000000..eed37a7e0dd --- /dev/null +++ b/examples/bluetooth/ble_get_started/bluedroid/Bluedroid_GATT_Server/main/include/heart_rate.h @@ -0,0 +1,18 @@ +/* + * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Unlicense OR CC0-1.0 + */ +#ifndef HEART_RATE_H +#define HEART_RATE_H + +#include + +/* Defines */ +#define HEART_RATE_TASK_PERIOD (1000 / portTICK_PERIOD_MS) + +/* Public function declarations */ +uint8_t get_heart_rate(void); +void update_heart_rate(void); + +#endif // HEART_RATE_H diff --git a/examples/bluetooth/ble_get_started/bluedroid/Bluedroid_GATT_Server/main/include/led.h b/examples/bluetooth/ble_get_started/bluedroid/Bluedroid_GATT_Server/main/include/led.h new file mode 100644 index 00000000000..973578f65cc --- /dev/null +++ b/examples/bluetooth/ble_get_started/bluedroid/Bluedroid_GATT_Server/main/include/led.h @@ -0,0 +1,23 @@ +/* + * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Unlicense OR CC0-1.0 + */ +#ifndef LED_H +#define LED_H + +/* Includes */ +/* ESP APIs */ +#include "driver/gpio.h" +#include "led_strip.h" + +/* Defines */ +#define BLINK_GPIO CONFIG_EXAMPLE_BLINK_GPIO + +/* Public function declarations */ +uint8_t get_led_state(void); +void led_on(void); +void led_off(void); +void led_init(void); + +#endif // LED_H diff --git a/examples/bluetooth/ble_get_started/bluedroid/Bluedroid_GATT_Server/main/main.c b/examples/bluetooth/ble_get_started/bluedroid/Bluedroid_GATT_Server/main/main.c new file mode 100644 index 00000000000..07e19e6b247 --- /dev/null +++ b/examples/bluetooth/ble_get_started/bluedroid/Bluedroid_GATT_Server/main/main.c @@ -0,0 +1,515 @@ +/* + * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Unlicense OR CC0-1.0 + */ + +#include +#include +#include +#include +#include "freertos/FreeRTOS.h" +#include "freertos/task.h" +#include "esp_system.h" +#include "esp_log.h" +#include "nvs_flash.h" +#include "esp_bt.h" + +#include "esp_gap_ble_api.h" +#include "esp_gatts_api.h" +#include "esp_bt_defs.h" +#include "esp_bt_main.h" +#include "esp_bt_device.h" +#include "esp_gatt_common_api.h" +#include "heart_rate.h" +#include "led.h" + +#define PROFILE_NUM 2 +#define HEART_PROFILE_APP_ID 0 +#define AUTO_IO_PROFILE_APP_ID 1 +#define HEART_RATE_SVC_UUID 0x180D +#define HEART_RATE_CHAR_UUID 0x2A37 +#define HEART_NUM_HANDLE 4 +#define AUTO_IO_SVC_UUID 0x1815 +#define AUTO_IO_NUM_HANDLE 3 + +#define ADV_CONFIG_FLAG (1 << 0) +#define SCAN_RSP_CONFIG_FLAG (1 << 1) + +struct gatts_profile_inst { + esp_gatts_cb_t gatts_cb; + uint16_t gatts_if; + uint16_t app_id; + uint16_t conn_id; + uint16_t service_handle; + esp_gatt_srvc_id_t service_id; + uint16_t char_handle; + esp_bt_uuid_t char_uuid; + esp_gatt_perm_t perm; + esp_gatt_char_prop_t property; + uint16_t descr_handle; + esp_bt_uuid_t descr_uuid; +}; + +///Declare the static function +static void heart_gatts_profile_event_handler(esp_gatts_cb_event_t event, esp_gatt_if_t gatts_if, esp_ble_gatts_cb_param_t *param); +static void auto_io_gatts_profile_event_handler(esp_gatts_cb_event_t event, esp_gatt_if_t gatts_if, esp_ble_gatts_cb_param_t *param); +static void example_write_event_env(esp_gatt_if_t gatts_if, esp_ble_gatts_cb_param_t *param); + +static const char *GATTS_TAG = "GATTS_DEMO"; +static esp_gatt_char_prop_t heart_property = 0; +static esp_gatt_char_prop_t auto_io_property = 0; +static uint8_t heart_rate_val[2] = {0}; +static uint8_t led_status[2] = {0}; +static bool indicate_enabled = false; +static bool hrs_create_cmpl = false; // Heart Rate Service +static uint8_t adv_config_done = 0; + +static esp_attr_value_t heart_rate_attr = { + .attr_max_len = 2, + .attr_len = sizeof(heart_rate_val), + .attr_value = heart_rate_val, +}; + +static esp_attr_value_t led_status_attr = { + .attr_max_len = 2, + .attr_len = sizeof(led_status), + .attr_value = led_status, +}; + +static const uint8_t led_chr_uuid[] = { + 0x23, 0xd1, 0xbc, 0xea, 0x5f, 0x78, 0x23, 0x15, 0xde, 0xef, 0x12, 0x12, 0x25, 0x15, 0x00, 0x00 +}; + +static esp_ble_adv_data_t adv_data = { + .set_scan_rsp = false, + .include_name = true, + .include_txpower = false, + .min_interval = 0x0006, + .max_interval = 0x0010, + .appearance = 0x00, + .manufacturer_len = 0, + .p_manufacturer_data = NULL, + .service_data_len = 0, + .p_service_data = NULL, + .service_uuid_len = 0, + .p_service_uuid = NULL, + .flag = (ESP_BLE_ADV_FLAG_GEN_DISC | ESP_BLE_ADV_FLAG_BREDR_NOT_SPT), +}; + +static esp_ble_adv_params_t adv_params = { + .adv_int_min = 0x20, // 20ms + .adv_int_max = 0x40, // 40ms + .adv_type = ADV_TYPE_IND, + .own_addr_type = BLE_ADDR_TYPE_PUBLIC, + .channel_map = ADV_CHNL_ALL, + .adv_filter_policy = ADV_FILTER_ALLOW_SCAN_ANY_CON_ANY, +}; + +static struct gatts_profile_inst gl_profile_tab[PROFILE_NUM] = { + [HEART_PROFILE_APP_ID] = { + .gatts_cb = heart_gatts_profile_event_handler, + .gatts_if = ESP_GATT_IF_NONE, /* Not get the gatt_if, so initial is ESP_GATT_IF_NONE */ + }, + [AUTO_IO_PROFILE_APP_ID] = { + .gatts_cb = auto_io_gatts_profile_event_handler, + .gatts_if = ESP_GATT_IF_NONE, /* Not get the gatt_if, so initial is ESP_GATT_IF_NONE */ + }, +}; + +static void heart_rate_task(void* param) +{ + ESP_LOGI(GATTS_TAG, "Heart Rate Task Start"); + + while (1) { + if (hrs_create_cmpl) { + update_heart_rate(); + ESP_LOGI(GATTS_TAG, "Heart Rate updated to %d", get_heart_rate()); + + heart_rate_val[1] = get_heart_rate(); + esp_ble_gatts_set_attr_value(gl_profile_tab[HEART_PROFILE_APP_ID].char_handle, 2, heart_rate_val); + } + + vTaskDelay(1000 / portTICK_PERIOD_MS); + } +} + +static void gap_event_handler(esp_gap_ble_cb_event_t event, esp_ble_gap_cb_param_t *param) +{ + switch (event) { + case ESP_GAP_BLE_ADV_DATA_SET_COMPLETE_EVT: + ESP_LOGI(GATTS_TAG, "Advertising data set, status %d", param->adv_data_cmpl.status); + adv_config_done &= (~ADV_CONFIG_FLAG); + if (adv_config_done == 0) { + esp_ble_gap_start_advertising(&adv_params); + } + break; + case ESP_GAP_BLE_SCAN_RSP_DATA_SET_COMPLETE_EVT: + ESP_LOGI(GATTS_TAG, "Scan response data set, status %d", param->scan_rsp_data_cmpl.status); + adv_config_done &= (~SCAN_RSP_CONFIG_FLAG); + if (adv_config_done == 0) { + esp_ble_gap_start_advertising(&adv_params); + } + break; + case ESP_GAP_BLE_ADV_START_COMPLETE_EVT: + if (param->adv_start_cmpl.status != ESP_BT_STATUS_SUCCESS) { + ESP_LOGE(GATTS_TAG, "Advertising start failed, status %d", param->adv_start_cmpl.status); + break; + } + ESP_LOGI(GATTS_TAG, "Advertising start successfully"); + break; + case ESP_GAP_BLE_UPDATE_CONN_PARAMS_EVT: + ESP_LOGI(GATTS_TAG, "Connection params update, status %d, conn_int %d, latency %d, timeout %d", + param->update_conn_params.status, + param->update_conn_params.conn_int, + param->update_conn_params.latency, + param->update_conn_params.timeout); + break; + case ESP_GAP_BLE_SET_PKT_LENGTH_COMPLETE_EVT: + ESP_LOGI(GATTS_TAG, "Packet length update, status %d, rx %d, tx %d", + param->pkt_data_length_cmpl.status, + param->pkt_data_length_cmpl.params.rx_len, + param->pkt_data_length_cmpl.params.tx_len); + break; + default: + break; + } +} + +static void heart_gatts_profile_event_handler(esp_gatts_cb_event_t event, esp_gatt_if_t gatts_if, esp_ble_gatts_cb_param_t *param) +{ + switch (event) { + case ESP_GATTS_REG_EVT: + ESP_LOGI(GATTS_TAG, "GATT server register, status %d, app_id %d", param->reg.status, param->reg.app_id); + gl_profile_tab[HEART_PROFILE_APP_ID].service_id.is_primary = true; + gl_profile_tab[HEART_PROFILE_APP_ID].service_id.id.inst_id = 0x00; + gl_profile_tab[HEART_PROFILE_APP_ID].service_id.id.uuid.len = ESP_UUID_LEN_16; + gl_profile_tab[HEART_PROFILE_APP_ID].service_id.id.uuid.uuid.uuid16 = HEART_RATE_SVC_UUID; + + //config adv data + esp_err_t ret = esp_ble_gap_config_adv_data(&adv_data); + if (ret) { + ESP_LOGE(GATTS_TAG, "config adv data failed, error code = %x", ret); + break; + } + + esp_ble_gatts_create_service(gatts_if, &gl_profile_tab[HEART_PROFILE_APP_ID].service_id, HEART_NUM_HANDLE); + break; + case ESP_GATTS_CREATE_EVT: + //service has been created, now add characteristic declaration + ESP_LOGI(GATTS_TAG, "Service create, status %d, service_handle %d", param->create.status, param->create.service_handle); + gl_profile_tab[HEART_PROFILE_APP_ID].service_handle = param->create.service_handle; + gl_profile_tab[HEART_PROFILE_APP_ID].char_uuid.len = ESP_UUID_LEN_16; + gl_profile_tab[HEART_PROFILE_APP_ID].char_uuid.uuid.uuid16 = HEART_RATE_CHAR_UUID; + esp_ble_gatts_start_service(gl_profile_tab[HEART_PROFILE_APP_ID].service_handle); + heart_property = ESP_GATT_CHAR_PROP_BIT_READ | ESP_GATT_CHAR_PROP_BIT_INDICATE; + ret = esp_ble_gatts_add_char(gl_profile_tab[HEART_PROFILE_APP_ID].service_handle, &gl_profile_tab[HEART_PROFILE_APP_ID].char_uuid, + ESP_GATT_PERM_READ, + heart_property, + &heart_rate_attr, NULL); + if (ret) { + ESP_LOGE(GATTS_TAG, "add char failed, error code = %x", ret); + } + break; + case ESP_GATTS_ADD_CHAR_EVT: + ESP_LOGI(GATTS_TAG, "Characteristic add, status %d, attr_handle %d, char_uuid %x", + param->add_char.status, param->add_char.attr_handle, param->add_char.char_uuid.uuid.uuid16); + gl_profile_tab[HEART_PROFILE_APP_ID].char_handle = param->add_char.attr_handle; + gl_profile_tab[HEART_PROFILE_APP_ID].descr_uuid.len = ESP_UUID_LEN_16; + gl_profile_tab[HEART_PROFILE_APP_ID].descr_uuid.uuid.uuid16 = ESP_GATT_UUID_CHAR_CLIENT_CONFIG; + ESP_LOGI(GATTS_TAG, "heart rate char handle %d", param->add_char.attr_handle); + ret = esp_ble_gatts_add_char_descr(gl_profile_tab[HEART_PROFILE_APP_ID].service_handle, &gl_profile_tab[HEART_PROFILE_APP_ID].descr_uuid, + ESP_GATT_PERM_READ | ESP_GATT_PERM_WRITE, NULL, NULL); + break; + case ESP_GATTS_ADD_CHAR_DESCR_EVT: + ESP_LOGI(GATTS_TAG, "Descriptor add, status %d, attr_handle %u", + param->add_char_descr.status, param->add_char_descr.attr_handle); + gl_profile_tab[HEART_PROFILE_APP_ID].descr_handle = param->add_char_descr.attr_handle; + hrs_create_cmpl = true; + break; + case ESP_GATTS_READ_EVT: + ESP_LOGI(GATTS_TAG, "Characteristic read"); + esp_gatt_rsp_t rsp; + memset(&rsp, 0, sizeof(esp_gatt_rsp_t)); + rsp.attr_value.handle = param->read.handle; + rsp.attr_value.len = 2; + memcpy(rsp.attr_value.value, heart_rate_val, sizeof(heart_rate_val)); + esp_ble_gatts_send_response(gatts_if, param->read.conn_id, param->read.trans_id, ESP_GATT_OK, &rsp); + break; + case ESP_GATTS_WRITE_EVT: + ESP_LOGI(GATTS_TAG, "Characteristic write, value len %u, value ", param->write.len); + ESP_LOG_BUFFER_HEX(GATTS_TAG, param->write.value, param->write.len); + + if (gl_profile_tab[HEART_PROFILE_APP_ID].descr_handle == param->write.handle && param->write.len == 2) { + uint16_t descr_value = param->write.value[1]<<8 | param->write.value[0]; + if (descr_value == 0x0001) { + if (heart_property & ESP_GATT_CHAR_PROP_BIT_NOTIFY) { + ESP_LOGI(GATTS_TAG, "Notification enable"); + uint8_t notify_data[15]; + for (int i = 0; i < sizeof(notify_data); i++) { + notify_data[i] = i%0xff; + } + //the size of notify_data[] need less than MTU size + esp_ble_gatts_send_indicate(gatts_if, param->write.conn_id, gl_profile_tab[HEART_PROFILE_APP_ID].char_handle, + sizeof(notify_data), notify_data, false); + } + } else if (descr_value == 0x0002) { + if (heart_property & ESP_GATT_CHAR_PROP_BIT_INDICATE) { + ESP_LOGI(GATTS_TAG, "Indication enable"); + indicate_enabled = true; + uint8_t indicate_data[15]; + for (int i = 0; i < sizeof(indicate_data); i++) { + indicate_data[i] = i%0xff; + } + //the size of indicate_data[] need less than MTU size + esp_ble_gatts_send_indicate(gatts_if, param->write.conn_id, gl_profile_tab[HEART_PROFILE_APP_ID].char_handle, + sizeof(indicate_data), indicate_data, true); + } + } else if (descr_value == 0x0000) { + indicate_enabled = false; + ESP_LOGI(GATTS_TAG, "Notification/Indication disable"); + } else { + ESP_LOGE(GATTS_TAG, "Invalid descriptor value"); + ESP_LOG_BUFFER_HEX(GATTS_TAG, param->write.value, param->write.len); + } + } + example_write_event_env(gatts_if, param); + break; + case ESP_GATTS_DELETE_EVT: + break; + case ESP_GATTS_START_EVT: + ESP_LOGI(GATTS_TAG, "Service start, status %d, service_handle %d", param->start.status, param->start.service_handle); + break; + case ESP_GATTS_STOP_EVT: + break; + case ESP_GATTS_CONNECT_EVT: + ESP_LOGI(GATTS_TAG, "Connected, conn_id %u, remote "ESP_BD_ADDR_STR"", + param->connect.conn_id, ESP_BD_ADDR_HEX(param->connect.remote_bda)); + gl_profile_tab[HEART_PROFILE_APP_ID].conn_id = param->connect.conn_id; + break; + case ESP_GATTS_DISCONNECT_EVT: + ESP_LOGI(GATTS_TAG, "Disconnected, remote "ESP_BD_ADDR_STR", reason 0x%02x", + ESP_BD_ADDR_HEX(param->disconnect.remote_bda), param->disconnect.reason); + indicate_enabled = false; + esp_ble_gap_start_advertising(&adv_params); + break; + case ESP_GATTS_CONF_EVT: + ESP_LOGI(GATTS_TAG, "Confirm receive, status %d, attr_handle %d", param->conf.status, param->conf.handle); + if (param->conf.status != ESP_GATT_OK) { + ESP_LOG_BUFFER_HEX(GATTS_TAG, param->conf.value, param->conf.len); + } + break; + case ESP_GATTS_SET_ATTR_VAL_EVT: + ESP_LOGI(GATTS_TAG, "Attribute value set, status %d", param->set_attr_val.status); + if (indicate_enabled) { + uint8_t indicate_data[2] = {0}; + memcpy(indicate_data, heart_rate_val, sizeof(heart_rate_val)); + esp_ble_gatts_send_indicate(gatts_if, gl_profile_tab[HEART_PROFILE_APP_ID].conn_id, gl_profile_tab[HEART_PROFILE_APP_ID].char_handle, sizeof(indicate_data), indicate_data, true); + } + break; + default: + break; + } +} + +static void auto_io_gatts_profile_event_handler(esp_gatts_cb_event_t event, esp_gatt_if_t gatts_if, esp_ble_gatts_cb_param_t *param) +{ + switch (event) { + case ESP_GATTS_REG_EVT: + ESP_LOGI(GATTS_TAG, "GATT server register, status %d, app_id %d", param->reg.status, param->reg.app_id); + gl_profile_tab[AUTO_IO_PROFILE_APP_ID].service_id.is_primary = true; + gl_profile_tab[AUTO_IO_PROFILE_APP_ID].service_id.id.inst_id = 0x00; + gl_profile_tab[AUTO_IO_PROFILE_APP_ID].service_id.id.uuid.len = ESP_UUID_LEN_16; + gl_profile_tab[AUTO_IO_PROFILE_APP_ID].service_id.id.uuid.uuid.uuid16 = AUTO_IO_SVC_UUID; + esp_ble_gatts_create_service(gatts_if, &gl_profile_tab[AUTO_IO_PROFILE_APP_ID].service_id, AUTO_IO_NUM_HANDLE); + break; + case ESP_GATTS_CREATE_EVT: + //service has been created, now add characteristic declaration + ESP_LOGI(GATTS_TAG, "Service create, status %d, service_handle %d", param->create.status, param->create.service_handle); + gl_profile_tab[AUTO_IO_PROFILE_APP_ID].service_handle = param->create.service_handle; + gl_profile_tab[AUTO_IO_PROFILE_APP_ID].char_uuid.len = ESP_UUID_LEN_128; + memcpy(gl_profile_tab[AUTO_IO_PROFILE_APP_ID].char_uuid.uuid.uuid128, led_chr_uuid, ESP_UUID_LEN_128); + + esp_ble_gatts_start_service(gl_profile_tab[AUTO_IO_PROFILE_APP_ID].service_handle); + auto_io_property = ESP_GATT_CHAR_PROP_BIT_WRITE ; + esp_err_t ret = esp_ble_gatts_add_char(gl_profile_tab[AUTO_IO_PROFILE_APP_ID].service_handle, &gl_profile_tab[AUTO_IO_PROFILE_APP_ID].char_uuid, + ESP_GATT_PERM_READ | ESP_GATT_PERM_WRITE , + auto_io_property, + &led_status_attr, NULL); + if (ret) { + ESP_LOGE(GATTS_TAG, "add char failed, error code = %x", ret); + } + break; + case ESP_GATTS_ADD_CHAR_EVT: + ESP_LOGI(GATTS_TAG, "Characteristic add, status %d, attr_handle %d, char_uuid %x", + param->add_char.status, param->add_char.attr_handle, param->add_char.char_uuid.uuid.uuid16); + gl_profile_tab[AUTO_IO_PROFILE_APP_ID].char_handle = param->add_char.attr_handle; + break; + case ESP_GATTS_ADD_CHAR_DESCR_EVT: + ESP_LOGI(GATTS_TAG, "Descriptor add, status %d", param->add_char_descr.status); + gl_profile_tab[AUTO_IO_PROFILE_APP_ID].descr_handle = param->add_char_descr.attr_handle; + break; + case ESP_GATTS_READ_EVT: + ESP_LOGI(GATTS_TAG, "Characteristic read"); + esp_gatt_rsp_t rsp; + memset(&rsp, 0, sizeof(esp_gatt_rsp_t)); + + rsp.attr_value.handle = param->read.handle; + rsp.attr_value.len = 1; + rsp.attr_value.value[0] = 0x02; + esp_ble_gatts_send_response(gatts_if, param->read.conn_id, param->read.trans_id, ESP_GATT_OK, &rsp); + break; + case ESP_GATTS_WRITE_EVT: + ESP_LOGI(GATTS_TAG, "Characteristic write, value len %u, value ", param->write.len); + ESP_LOG_BUFFER_HEX(GATTS_TAG, param->write.value, param->write.len); + if (param->write.value[0]) { + ESP_LOGI(GATTS_TAG, "LED ON!"); + led_on(); + } else { + ESP_LOGI(GATTS_TAG, "LED OFF!"); + led_off(); + } + example_write_event_env(gatts_if, param); + break; + case ESP_GATTS_DELETE_EVT: + break; + case ESP_GATTS_START_EVT: + ESP_LOGI(GATTS_TAG, "Service start, status %d, service_handle %d", param->start.status, param->start.service_handle); + break; + case ESP_GATTS_STOP_EVT: + break; + case ESP_GATTS_CONNECT_EVT: + esp_ble_conn_update_params_t conn_params = {0}; + memcpy(conn_params.bda, param->connect.remote_bda, sizeof(esp_bd_addr_t)); + conn_params.latency = 0; + conn_params.max_int = 0x20; + conn_params.min_int = 0x10; + conn_params.timeout = 400; + ESP_LOGI(GATTS_TAG, "Connected, conn_id %u, remote "ESP_BD_ADDR_STR"", + param->connect.conn_id, ESP_BD_ADDR_HEX(param->connect.remote_bda)); + gl_profile_tab[AUTO_IO_PROFILE_APP_ID].conn_id = param->connect.conn_id; + esp_ble_gap_update_conn_params(&conn_params); + break; + case ESP_GATTS_DISCONNECT_EVT: + ESP_LOGI(GATTS_TAG, "Disconnected, remote "ESP_BD_ADDR_STR", reason 0x%02x", + ESP_BD_ADDR_HEX(param->disconnect.remote_bda), param->disconnect.reason); + break; + case ESP_GATTS_CONF_EVT: + ESP_LOGI(GATTS_TAG, "Confirm receive, status %d, attr_handle %d", param->conf.status, param->conf.handle); + if (param->conf.status != ESP_GATT_OK) { + ESP_LOG_BUFFER_HEX(GATTS_TAG, param->conf.value, param->conf.len); + } + break; + default: + break; + } +} + +static void gatts_event_handler(esp_gatts_cb_event_t event, esp_gatt_if_t gatts_if, esp_ble_gatts_cb_param_t *param) +{ + if (event == ESP_GATTS_REG_EVT) { + if (param->reg.status == ESP_GATT_OK) { + gl_profile_tab[param->reg.app_id].gatts_if = gatts_if; + + } else { + ESP_LOGI(GATTS_TAG, "Reg app failed, app_id %04x, status %d", + param->reg.app_id, + param->reg.status); + return; + } + } + + //gatts_if registered complete, call cb handlers + do { + int idx; + for (idx = 0; idx < PROFILE_NUM; idx++) { + if (gatts_if == ESP_GATT_IF_NONE || /* ESP_GATT_IF_NONE, not specify a certain gatt_if, need to call every profile cb function */ + gatts_if == gl_profile_tab[idx].gatts_if) { + if (gl_profile_tab[idx].gatts_cb) { + gl_profile_tab[idx].gatts_cb(event, gatts_if, param); + } + } + } + } while(0); +} + + +void app_main(void) +{ + esp_err_t ret; + + led_init(); + + ret = nvs_flash_init(); + if (ret == ESP_ERR_NVS_NO_FREE_PAGES || ret == ESP_ERR_NVS_NEW_VERSION_FOUND) { + ESP_ERROR_CHECK(nvs_flash_erase()); + ret = nvs_flash_init(); + } + ESP_ERROR_CHECK(ret); + + ESP_ERROR_CHECK(esp_bt_controller_mem_release(ESP_BT_MODE_CLASSIC_BT)); + + esp_bt_controller_config_t bt_cfg = BT_CONTROLLER_INIT_CONFIG_DEFAULT(); + ret = esp_bt_controller_init(&bt_cfg); + if (ret) { + ESP_LOGE(GATTS_TAG, "%s initialize controller failed: %s", __func__, esp_err_to_name(ret)); + return; + } + + ret = esp_bt_controller_enable(ESP_BT_MODE_BLE); + if (ret) { + ESP_LOGE(GATTS_TAG, "%s enable controller failed: %s", __func__, esp_err_to_name(ret)); + return; + } + + ret = esp_bluedroid_init(); + if (ret) { + ESP_LOGE(GATTS_TAG, "%s init bluetooth failed: %s", __func__, esp_err_to_name(ret)); + return; + } + + ret = esp_bluedroid_enable(); + if (ret) { + ESP_LOGE(GATTS_TAG, "%s enable bluetooth failed: %s", __func__, esp_err_to_name(ret)); + return; + } + + ret = esp_ble_gap_register_callback(gap_event_handler); + if (ret) { + ESP_LOGE(GATTS_TAG, "gap register error, error code = %x", ret); + return; + } + + ret = esp_ble_gatts_register_callback(gatts_event_handler); + if (ret) { + ESP_LOGE(GATTS_TAG, "gatts register error, error code = %x", ret); + return; + } + + ret = esp_ble_gatts_app_register(HEART_PROFILE_APP_ID); + if (ret) { + ESP_LOGE(GATTS_TAG, "app register error, error code = %x", ret); + return; + } + + ret = esp_ble_gatts_app_register(AUTO_IO_PROFILE_APP_ID); + if (ret) { + ESP_LOGE(GATTS_TAG, "app register error, error code = %x", ret); + return; + } + + ret = esp_ble_gatt_set_local_mtu(500); + if (ret) { + ESP_LOGE(GATTS_TAG, "set local MTU failed, error code = %x", ret); + } + + xTaskCreate(heart_rate_task, "Heart Rate", 2 * 1024, NULL, 5, NULL); +} + +void example_write_event_env(esp_gatt_if_t gatts_if, esp_ble_gatts_cb_param_t *param) +{ + esp_gatt_status_t status = ESP_GATT_OK; + if (param->write.need_rsp) { + esp_ble_gatts_send_response(gatts_if, param->write.conn_id, param->write.trans_id, status, NULL); + } +} diff --git a/examples/bluetooth/ble_get_started/bluedroid/Bluedroid_GATT_Server/main/src/heart_rate_mock.c b/examples/bluetooth/ble_get_started/bluedroid/Bluedroid_GATT_Server/main/src/heart_rate_mock.c new file mode 100644 index 00000000000..fe8aaf8c89a --- /dev/null +++ b/examples/bluetooth/ble_get_started/bluedroid/Bluedroid_GATT_Server/main/src/heart_rate_mock.c @@ -0,0 +1,17 @@ +/* + * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Unlicense OR CC0-1.0 + */ +/* Includes */ +#include "common.h" +#include "heart_rate.h" +#include "esp_random.h" + +/* Private variables */ +static uint8_t heart_rate; + +/* Public functions */ +uint8_t get_heart_rate(void) { return heart_rate; } + +void update_heart_rate(void) { heart_rate = 60 + (uint8_t)(esp_random() % 21); } diff --git a/examples/bluetooth/ble_get_started/bluedroid/Bluedroid_GATT_Server/main/src/led.c b/examples/bluetooth/ble_get_started/bluedroid/Bluedroid_GATT_Server/main/src/led.c new file mode 100644 index 00000000000..8a11d00b027 --- /dev/null +++ b/examples/bluetooth/ble_get_started/bluedroid/Bluedroid_GATT_Server/main/src/led.c @@ -0,0 +1,98 @@ +/* + * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Unlicense OR CC0-1.0 + */ +/* Includes */ +#include "led.h" +#include "common.h" + +/* Private variables */ +static uint8_t led_state; + +#ifdef CONFIG_EXAMPLE_BLINK_LED_STRIP +static led_strip_handle_t led_strip; +#endif + +/* Public functions */ +uint8_t get_led_state(void) +{ + return led_state; +} + +#ifdef CONFIG_EXAMPLE_BLINK_LED_STRIP + +void led_on(void) +{ + /* Set the LED pixel using RGB from 0 (0%) to 255 (100%) for each color */ + led_strip_set_pixel(led_strip, 0, 16, 16, 16); + + /* Refresh the strip to send data */ + led_strip_refresh(led_strip); + + /* Update LED state */ + led_state = true; +} + +void led_off(void) +{ + /* Set all LED off to clear all pixels */ + led_strip_clear(led_strip); + + /* Update LED state */ + led_state = false; +} + +void led_init(void) +{ + // ESP_LOGI(TAG, "example configured to blink addressable led!"); + /* LED strip initialization with the GPIO and pixels number*/ + led_strip_config_t strip_config = { + .strip_gpio_num = CONFIG_EXAMPLE_BLINK_GPIO, + .max_leds = 1, // at least one LED on board + }; +#if CONFIG_EXAMPLE_BLINK_LED_STRIP_BACKEND_RMT + led_strip_rmt_config_t rmt_config = { + .resolution_hz = 10 * 1000 * 1000, // 10MHz + .flags.with_dma = false, + }; + ESP_ERROR_CHECK( + led_strip_new_rmt_device(&strip_config, &rmt_config, &led_strip)); +#elif CONFIG_EXAMPLE_BLINK_LED_STRIP_BACKEND_SPI + led_strip_spi_config_t spi_config = { + .spi_bus = SPI2_HOST, + .flags.with_dma = true, + }; + ESP_ERROR_CHECK( + led_strip_new_spi_device(&strip_config, &spi_config, &led_strip)); +#else +#error "unsupported LED strip backend" +#endif + /* Set all LED off to clear all pixels */ + led_off(); +} + +#elif CONFIG_EXAMPLE_BLINK_LED_GPIO + +void led_on(void) +{ + gpio_set_level(CONFIG_EXAMPLE_BLINK_GPIO, false); +} + +void led_off(void) +{ + gpio_set_level(CONFIG_EXAMPLE_BLINK_GPIO, true); +} + +void led_init(void) +{ + // ESP_LOGI(TAG, "example configured to blink gpio led!"); + gpio_reset_pin(CONFIG_EXAMPLE_BLINK_GPIO); + /* Set the GPIO as a push/pull output */ + gpio_set_direction(CONFIG_EXAMPLE_BLINK_GPIO, GPIO_MODE_OUTPUT); + gpio_set_level(CONFIG_EXAMPLE_BLINK_GPIO, 1); +} + +#else +#error "unsupported LED type" +#endif diff --git a/examples/bluetooth/ble_get_started/bluedroid/Bluedroid_GATT_Server/sdkconfig.defaults b/examples/bluetooth/ble_get_started/bluedroid/Bluedroid_GATT_Server/sdkconfig.defaults new file mode 100644 index 00000000000..73d84284854 --- /dev/null +++ b/examples/bluetooth/ble_get_started/bluedroid/Bluedroid_GATT_Server/sdkconfig.defaults @@ -0,0 +1,8 @@ +# This file was generated using idf.py save-defconfig. It can be edited manually. +# Espressif IoT Development Framework (ESP-IDF) Project Minimal Configuration +# +CONFIG_BT_ENABLED=y +CONFIG_BT_BLE_50_FEATURES_SUPPORTED=n +CONFIG_BT_BLE_42_FEATURES_SUPPORTED=y +# CONFIG_BT_LE_50_FEATURE_SUPPORT is not used on ESP32, ESP32-C3 and ESP32-S3. +# CONFIG_BT_LE_50_FEATURE_SUPPORT is not set diff --git a/examples/bluetooth/ble_get_started/bluedroid/Bluedroid_GATT_Server/sdkconfig.defaults.esp32 b/examples/bluetooth/ble_get_started/bluedroid/Bluedroid_GATT_Server/sdkconfig.defaults.esp32 new file mode 100644 index 00000000000..555345909bc --- /dev/null +++ b/examples/bluetooth/ble_get_started/bluedroid/Bluedroid_GATT_Server/sdkconfig.defaults.esp32 @@ -0,0 +1,2 @@ +CONFIG_EXAMPLE_BLINK_GPIO=5 +CONFIG_EXAMPLE_BLINK_LED_STRIP=n diff --git a/examples/bluetooth/ble_get_started/bluedroid/Bluedroid_GATT_Server/sdkconfig.defaults.esp32c2 b/examples/bluetooth/ble_get_started/bluedroid/Bluedroid_GATT_Server/sdkconfig.defaults.esp32c2 new file mode 100644 index 00000000000..0e517bfb707 --- /dev/null +++ b/examples/bluetooth/ble_get_started/bluedroid/Bluedroid_GATT_Server/sdkconfig.defaults.esp32c2 @@ -0,0 +1,12 @@ +# Override some defaults so BT stack is enabled +# by default in this example +CONFIG_IDF_TARGET="esp32c2" +CONFIG_BT_ENABLED=y +# CONFIG_BT_BLE_50_FEATURES_SUPPORTED is not set +CONFIG_BT_BLE_42_FEATURES_SUPPORTED=y +# CONFIG_BT_LE_50_FEATURE_SUPPORT is not set +CONFIG_BT_LE_HCI_EVT_BUF_SIZE=257 +CONFIG_XTAL_FREQ_26=y +CONFIG_EXAMPLE_BLINK_LED_STRIP=n +CONFIG_EXAMPLE_BLINK_LED_GPIO=y +CONFIG_EXAMPLE_BLINK_GPIO=8 diff --git a/examples/bluetooth/ble_get_started/bluedroid/Bluedroid_GATT_Server/sdkconfig.defaults.esp32c3 b/examples/bluetooth/ble_get_started/bluedroid/Bluedroid_GATT_Server/sdkconfig.defaults.esp32c3 new file mode 100644 index 00000000000..0ad7bbc0aeb --- /dev/null +++ b/examples/bluetooth/ble_get_started/bluedroid/Bluedroid_GATT_Server/sdkconfig.defaults.esp32c3 @@ -0,0 +1,7 @@ +# This file was generated using idf.py save-defconfig. It can be edited manually. +# Espressif IoT Development Framework (ESP-IDF) Project Minimal Configuration +# +CONFIG_IDF_TARGET="esp32c3" +CONFIG_BT_ENABLED=y +# CONFIG_BT_BLE_50_FEATURES_SUPPORTED is not set +CONFIG_BT_BLE_42_FEATURES_SUPPORTED=y diff --git a/examples/bluetooth/ble_get_started/bluedroid/Bluedroid_GATT_Server/sdkconfig.defaults.esp32c5 b/examples/bluetooth/ble_get_started/bluedroid/Bluedroid_GATT_Server/sdkconfig.defaults.esp32c5 new file mode 100644 index 00000000000..b6bb7e3a602 --- /dev/null +++ b/examples/bluetooth/ble_get_started/bluedroid/Bluedroid_GATT_Server/sdkconfig.defaults.esp32c5 @@ -0,0 +1,10 @@ +# This file was generated using idf.py save-defconfig. It can be edited manually. +# Espressif IoT Development Framework (ESP-IDF) Project Minimal Configuration +# +CONFIG_IDF_TARGET="esp32c5" +CONFIG_BT_ENABLED=y +# CONFIG_BT_BLE_50_FEATURES_SUPPORTED is not set +CONFIG_BT_BLE_42_FEATURES_SUPPORTED=y +CONFIG_EXAMPLE_BLINK_LED_STRIP=y +CONFIG_EXAMPLE_BLINK_LED_GPIO=n +CONFIG_EXAMPLE_BLINK_GPIO=27 diff --git a/examples/bluetooth/ble_get_started/bluedroid/Bluedroid_GATT_Server/sdkconfig.defaults.esp32s3 b/examples/bluetooth/ble_get_started/bluedroid/Bluedroid_GATT_Server/sdkconfig.defaults.esp32s3 new file mode 100644 index 00000000000..a5b90fe8316 --- /dev/null +++ b/examples/bluetooth/ble_get_started/bluedroid/Bluedroid_GATT_Server/sdkconfig.defaults.esp32s3 @@ -0,0 +1,10 @@ +# This file was generated using idf.py save-defconfig. It can be edited manually. +# Espressif IoT Development Framework (ESP-IDF) Project Minimal Configuration +# +CONFIG_IDF_TARGET="esp32s3" +CONFIG_BT_ENABLED=y +# CONFIG_BT_BLE_50_FEATURES_SUPPORTED is not set +CONFIG_BT_BLE_42_FEATURES_SUPPORTED=y +CONFIG_EXAMPLE_BLINK_LED_STRIP=y +CONFIG_EXAMPLE_BLINK_LED_GPIO=n +CONFIG_EXAMPLE_BLINK_GPIO=38 From 5bd66eaa57dcecbdb7c9c3e8ac990feebebf1267 Mon Sep 17 00:00:00 2001 From: zwl Date: Thu, 5 Dec 2024 16:51:42 +0800 Subject: [PATCH 062/118] feat(ble): support some vendor hci commands on ESP32-C6 --- components/bt/controller/lib_esp32c6/esp32c6-bt-lib | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/components/bt/controller/lib_esp32c6/esp32c6-bt-lib b/components/bt/controller/lib_esp32c6/esp32c6-bt-lib index 2ac61ac611a..2c3b919de82 160000 --- a/components/bt/controller/lib_esp32c6/esp32c6-bt-lib +++ b/components/bt/controller/lib_esp32c6/esp32c6-bt-lib @@ -1 +1 @@ -Subproject commit 2ac61ac611a5e8776bd679440f6921859a89dcd6 +Subproject commit 2c3b919de82278768a98f66c02c63a148026a613 From 15203f9f3596e61a64046c6fa29d69217ad5c13e Mon Sep 17 00:00:00 2001 From: zwl Date: Thu, 5 Dec 2024 16:53:44 +0800 Subject: [PATCH 063/118] feat(ble): support some vendor hci commands on ESP32-H2 --- components/bt/controller/lib_esp32h2/esp32h2-bt-lib | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/components/bt/controller/lib_esp32h2/esp32h2-bt-lib b/components/bt/controller/lib_esp32h2/esp32h2-bt-lib index faf7470485f..59c26f308e1 160000 --- a/components/bt/controller/lib_esp32h2/esp32h2-bt-lib +++ b/components/bt/controller/lib_esp32h2/esp32h2-bt-lib @@ -1 +1 @@ -Subproject commit faf7470485f08b1657f2b8ec3ae7c762cff116e6 +Subproject commit 59c26f308e18809cc02351febcbecad542a365c9 From 6b01a56e094e3220265c37fabfb42bade8417c2b Mon Sep 17 00:00:00 2001 From: zwl Date: Thu, 5 Dec 2024 14:54:04 +0800 Subject: [PATCH 064/118] fix(ble): fixed the connect issue when rx error aa on ESP32-C2 --- components/bt/controller/esp32c2/Kconfig.in | 8 ++++++++ components/bt/controller/esp32c2/bt.c | 2 +- components/bt/controller/esp32c2/esp_bt_cfg.h | 6 ++++++ .../bt/controller/lib_esp32c2/esp32c2-bt-lib | 2 +- .../bt/include/esp32c2/include/esp_bt.h | 4 +++- .../esp32c2/ld/esp32c2.rom.ble-eco4.ld | 20 +++++++++---------- .../esp_rom/esp32c2/ld/esp32c2.rom.ble.ld | 6 +++--- 7 files changed, 32 insertions(+), 16 deletions(-) diff --git a/components/bt/controller/esp32c2/Kconfig.in b/components/bt/controller/esp32c2/Kconfig.in index ac61690f1d2..7ccde3047ea 100644 --- a/components/bt/controller/esp32c2/Kconfig.in +++ b/components/bt/controller/esp32c2/Kconfig.in @@ -659,3 +659,11 @@ config BT_LE_PLACE_CONN_RELATED_INTO_IRAM bool "Place the connection-related code into IRAM" depends on BT_CTRL_RUN_IN_FLASH_ONLY default n + +config BT_LE_CTRL_CHECK_CONNECT_IND_ACCESS_ADDRESS + bool "Enable enhanced Access Address check in CONNECT_IND" + default n + help + Enabling this option will add stricter verification of the Access Address in the CONNECT_IND PDU. + This improves security by ensuring that only connection requests with valid Access Addresses are accepted. + If disabled, only basic checks are applied, improving compatibility. diff --git a/components/bt/controller/esp32c2/bt.c b/components/bt/controller/esp32c2/bt.c index a57530d2e39..3be39c98386 100644 --- a/components/bt/controller/esp32c2/bt.c +++ b/components/bt/controller/esp32c2/bt.c @@ -199,7 +199,7 @@ static void esp_bt_ctrl_log_partition_get_and_erase_first_block(void); /* Local variable definition *************************************************************************** */ -#if CONFIG_ESP32C2_REV_MIN_FULL < 200 +#if (CONFIG_ESP32C2_REV_MIN_FULL < 200) && (!CONFIG_BT_CTRL_RUN_IN_FLASH_ONLY) void *g_ble_lll_rfmgmt_env_p; #endif /* Static variable declare */ diff --git a/components/bt/controller/esp32c2/esp_bt_cfg.h b/components/bt/controller/esp32c2/esp_bt_cfg.h index 1dbd5798573..a78eca6ace2 100644 --- a/components/bt/controller/esp32c2/esp_bt_cfg.h +++ b/components/bt/controller/esp32c2/esp_bt_cfg.h @@ -220,6 +220,12 @@ extern "C" { #define DEFAULT_BT_LE_COEX_PHY_CODED_TX_RX_TLIM_EFF CONFIG_BT_LE_COEX_PHY_CODED_TX_RX_TLIM_EFF +#ifdef CONFIG_BT_LE_CTRL_CHECK_CONNECT_IND_ACCESS_ADDRESS +#define DEFAULT_BT_LE_CTRL_CHECK_CONNECT_IND_ACCESS_ADDRESS (CONFIG_BT_LE_CTRL_CHECK_CONNECT_IND_ACCESS_ADDRESS) +#else +#define DEFAULT_BT_LE_CTRL_CHECK_CONNECT_IND_ACCESS_ADDRESS (0) +#endif + #ifdef CONFIG_BT_LE_HCI_INTERFACE_USE_UART #define HCI_UART_EN CONFIG_BT_LE_HCI_INTERFACE_USE_UART #else diff --git a/components/bt/controller/lib_esp32c2/esp32c2-bt-lib b/components/bt/controller/lib_esp32c2/esp32c2-bt-lib index d246fa87640..339d66ea3dc 160000 --- a/components/bt/controller/lib_esp32c2/esp32c2-bt-lib +++ b/components/bt/controller/lib_esp32c2/esp32c2-bt-lib @@ -1 +1 @@ -Subproject commit d246fa876402bcd9b16602dd0615c287ebc936bc +Subproject commit 339d66ea3dce6e97bee6ce41aa3d06761efcaad2 diff --git a/components/bt/include/esp32c2/include/esp_bt.h b/components/bt/include/esp32c2/include/esp_bt.h index 384d50f733d..6a5ce5a1d6a 100644 --- a/components/bt/include/esp32c2/include/esp_bt.h +++ b/components/bt/include/esp32c2/include/esp_bt.h @@ -167,7 +167,7 @@ esp_power_level_t esp_ble_tx_power_get_enhanced(esp_ble_enhanced_power_type_t po */ uint8_t esp_ble_get_chip_rev_version(void); -#define CONFIG_VERSION 0x20231124 +#define CONFIG_VERSION 0x20241121 #define CONFIG_MAGIC 0x5A5AA5A5 /** @@ -227,6 +227,7 @@ typedef struct { uint8_t version_num; /*!< Version number */ uint8_t ignore_wl_for_direct_adv; /*!< Ignore the white list for directed advertising */ uint8_t csa2_select; /*!< Select CSA#2 */ + uint8_t ble_aa_check; /*!< True if adds a verification step for the Access Address within the CONNECT_IND PDU; false otherwise. Configurable in menuconfig */ uint32_t config_magic; /*!< Configuration magic value */ } esp_bt_controller_config_t; @@ -273,6 +274,7 @@ typedef struct { .version_num = esp_ble_get_chip_rev_version(), \ .ignore_wl_for_direct_adv = 0, \ .csa2_select = DEFAULT_BT_LE_50_FEATURE_SUPPORT, \ + .ble_aa_check = DEFAULT_BT_LE_CTRL_CHECK_CONNECT_IND_ACCESS_ADDRESS, \ .config_magic = CONFIG_MAGIC, \ } diff --git a/components/esp_rom/esp32c2/ld/esp32c2.rom.ble-eco4.ld b/components/esp_rom/esp32c2/ld/esp32c2.rom.ble-eco4.ld index c244aed1880..77ebacca3ee 100644 --- a/components/esp_rom/esp32c2/ld/esp32c2.rom.ble-eco4.ld +++ b/components/esp_rom/esp32c2/ld/esp32c2.rom.ble-eco4.ld @@ -248,7 +248,7 @@ r_ble_ll_conn_set_global_chanmap = 0x40000e28; r_ble_ll_conn_set_phy = 0x40000e2c; r_ble_ll_conn_set_txpwr_by_handle = 0x40000e30; r_ble_ll_conn_set_unknown_rx_octets = 0x40000e34; -r_ble_ll_conn_slave_start = 0x40000e38; +//r_ble_ll_conn_slave_start = 0x40000e38; r_ble_ll_conn_sm_get = 0x40000e3c; r_ble_ll_conn_sm_new = 0x40000e40; r_ble_ll_conn_sm_npl_deinit = 0x40000e44; @@ -316,7 +316,7 @@ r_ble_ll_ctrl_version_ind_make = 0x40000f38; r_ble_ll_data_buffer_overflow = 0x40000f3c; r_ble_ll_deinit = 0x40000f40; r_ble_ll_disconn_comp_event_send = 0x40000f44; -r_ble_ll_env_init = 0x40000f48; +//r_ble_ll_env_init = 0x40000f48; r_ble_ll_event_comp_pkts = 0x40000f4c; r_ble_ll_event_dbuf_overflow = 0x40000f50; r_ble_ll_event_send = 0x40000f54; @@ -404,7 +404,7 @@ r_ble_ll_hci_vs_cmd_proc = 0x40001098; r_ble_ll_hci_vs_rd_static_addr = 0x4000109c; r_ble_ll_hw_err_timer_cb = 0x400010a0; r_ble_ll_hw_error = 0x400010a4; -r_ble_ll_init = 0x400010a8; +//r_ble_ll_init = 0x400010a8; r_ble_ll_init_alloc_conn_comp_ev = 0x400010ac; r_ble_ll_init_get_conn_comp_ev = 0x400010b0; r_ble_ll_init_rx_pkt_in = 0x400010b4; @@ -481,7 +481,7 @@ r_ble_ll_scan_can_chg_whitelist = 0x400011cc; r_ble_ll_scan_check_periodic_sync = 0x400011d0; r_ble_ll_scan_classify_filter_aux_init = 0x400011d4; r_ble_ll_scan_classify_filter_init = 0x400011d8; -r_ble_ll_scan_common_init = 0x400011dc; +//r_ble_ll_scan_common_init = 0x400011dc; r_ble_ll_scan_continue_en = 0x400011e0; r_ble_ll_scan_deinit = 0x400011e4; r_ble_ll_scan_dup_check_ext = 0x400011e8; @@ -492,7 +492,7 @@ r_ble_ll_scan_dup_update_ext = 0x400011f8; r_ble_ll_scan_dup_update_legacy = 0x400011fc; r_ble_ll_scan_enabled = 0x40001200; r_ble_ll_scan_end_adv_evt = 0x40001204; -r_ble_ll_scan_env_init = 0x40001208; +//r_ble_ll_scan_env_init = 0x40001208; r_ble_ll_scan_ext_initiator_start = 0x4000120c; r_ble_ll_scan_get_addr_data_from_legacy = 0x40001210; r_ble_ll_scan_get_addr_from_ext_adv = 0x40001214; @@ -514,7 +514,7 @@ r_ble_ll_scan_record_new_adv = 0x40001250; r_ble_ll_scan_refresh_nrpa = 0x40001254; r_ble_ll_scan_reset = 0x40001258; r_ble_ll_scan_rx_pkt_in = 0x4000125c; -r_ble_ll_scan_rx_pkt_in_on_aux = 0x40001260; +//r_ble_ll_scan_rx_pkt_in_on_aux = 0x40001260; r_ble_ll_scan_rx_pkt_in_on_legacy = 0x40001264; r_ble_ll_scan_rx_pkt_in_restore_addr_data = 0x40001268; r_ble_ll_scan_rxed = 0x4000126c; @@ -567,7 +567,7 @@ r_ble_ll_sync_list_size = 0x40001324; r_ble_ll_sync_lost_event = 0x40001328; r_ble_ll_sync_next_event = 0x4000132c; r_ble_ll_sync_on_list = 0x40001330; -r_ble_ll_sync_parse_ext_hdr = 0x40001334; +//r_ble_ll_sync_parse_ext_hdr = 0x40001334; r_ble_ll_sync_periodic_ind = 0x40001338; r_ble_ll_sync_phy_mode_to_aux_phy = 0x4000133c; r_ble_ll_sync_phy_mode_to_hci = 0x40001340; @@ -813,7 +813,7 @@ r_ble_lll_scan_rx_pkt_isr = 0x400016fc; r_ble_lll_scan_sched_next_aux = 0x40001700; r_ble_lll_scan_sched_remove = 0x40001704; r_ble_lll_scan_start = 0x40001708; -r_ble_lll_scan_start_rx = 0x4000170c; +//r_ble_lll_scan_start_rx = 0x4000170c; r_ble_lll_scan_stop = 0x40001710; r_ble_lll_scan_targeta_is_matched = 0x40001714; r_ble_lll_scan_timer_cb = 0x40001718; @@ -1049,7 +1049,7 @@ r_put_le32 = 0x40001ab4; r_put_le64 = 0x40001ab8; r_rtc0_timer_handler = 0x40001abc; r_sdkconfig_get_opts = 0x40001ac0; -r_sdkconfig_set_opts = 0x40001ac4; +//r_sdkconfig_set_opts = 0x40001ac4; r_sec_phy_valid = 0x40001ac8; r_swap_buf = 0x40001acc; r_swap_in_place = 0x40001ad0; @@ -1187,7 +1187,7 @@ r_ble_ll_trace_buffer_select = 0x40002f80; r_ble_ll_adv_vendor_hci_legacy_adv_clear = 0x40002f84; r_ble_ll_conn_is_lru_compare_with_sync = 0x40002f88; r_ble_ll_conn_rollback_last_unmapped_chan = 0x40002f8c; -r_ble_ll_hci_vs_csa_set = 0x40002f90; +//r_ble_ll_hci_vs_csa_set = 0x40002f90; r_ble_ll_hci_reset = 0x40002f94; r_ble_ll_adv_status_check = 0x40002f98; r_ble_ll_conn_status_check = 0x40002f9c; diff --git a/components/esp_rom/esp32c2/ld/esp32c2.rom.ble.ld b/components/esp_rom/esp32c2/ld/esp32c2.rom.ble.ld index 959cff0d7c6..52c45ef8174 100644 --- a/components/esp_rom/esp32c2/ld/esp32c2.rom.ble.ld +++ b/components/esp_rom/esp32c2/ld/esp32c2.rom.ble.ld @@ -387,7 +387,7 @@ r_ble_ll_scan_can_chg_whitelist = 0x400011cc; r_ble_ll_scan_check_periodic_sync = 0x400011d0; r_ble_ll_scan_classify_filter_aux_init = 0x400011d4; r_ble_ll_scan_classify_filter_init = 0x400011d8; -r_ble_ll_scan_common_init = 0x400011dc; +//r_ble_ll_scan_common_init = 0x400011dc; r_ble_ll_scan_continue_en = 0x400011e0; r_ble_ll_scan_dup_check_ext = 0x400011e8; r_ble_ll_scan_dup_check_legacy = 0x400011ec; @@ -640,7 +640,7 @@ r_ble_lll_scan_req_backoff = 0x400016ec; r_ble_lll_scan_sched_next_aux = 0x40001700; r_ble_lll_scan_sched_remove = 0x40001704; r_ble_lll_scan_start = 0x40001708; -r_ble_lll_scan_start_rx = 0x4000170c; +//r_ble_lll_scan_start_rx = 0x4000170c; r_ble_lll_scan_timer_cb = 0x40001718; r_ble_lll_sched_adv_new = 0x4000171c; r_ble_lll_sched_adv_resched_pdu = 0x40001720; @@ -838,7 +838,7 @@ r_put_le32 = 0x40001ab4; r_put_le64 = 0x40001ab8; r_rtc0_timer_handler = 0x40001abc; r_sdkconfig_get_opts = 0x40001ac0; -r_sdkconfig_set_opts = 0x40001ac4; +//r_sdkconfig_set_opts = 0x40001ac4; r_sec_phy_valid = 0x40001ac8; r_swap_buf = 0x40001acc; r_swap_in_place = 0x40001ad0; From 7d0d95b7d850ab51c7376509a8f19e6fddfca56c Mon Sep 17 00:00:00 2001 From: wuzhenghui Date: Thu, 12 Dec 2024 11:02:52 +0800 Subject: [PATCH 065/118] fix(esp_hw_support): fix mspi clock freq changed after lightsleep --- components/esp_hw_support/sleep_modes.c | 12 ++++++-- components/esp_pm/pm_impl.c | 28 ++++++++++--------- .../include/hal/mspi_timing_tuning_ll.h | 2 ++ 3 files changed, 26 insertions(+), 16 deletions(-) diff --git a/components/esp_hw_support/sleep_modes.c b/components/esp_hw_support/sleep_modes.c index c91df5b2adf..9b3c64f0670 100644 --- a/components/esp_hw_support/sleep_modes.c +++ b/components/esp_hw_support/sleep_modes.c @@ -58,12 +58,14 @@ #include "hal/cache_hal.h" #include "hal/cache_ll.h" +#include "hal/clk_tree_ll.h" #include "hal/wdt_hal.h" #include "hal/uart_hal.h" #if SOC_TOUCH_SENSOR_SUPPORTED #include "hal/touch_sensor_hal.h" #include "hal/touch_sens_hal.h" #endif +#include "hal/mspi_timing_tuning_ll.h" #include "sdkconfig.h" #include "esp_rom_uart.h" @@ -75,7 +77,9 @@ #include "esp_private/esp_clk.h" #include "esp_private/esp_task_wdt.h" #include "esp_private/sar_periph_ctrl.h" +#if MSPI_TIMING_LL_FLASH_CPU_CLK_SRC_BINDED #include "esp_private/mspi_timing_tuning.h" +#endif #ifdef CONFIG_IDF_TARGET_ESP32 #include "esp32/rom/cache.h" @@ -159,7 +163,7 @@ #define DEFAULT_SLEEP_OUT_OVERHEAD_US (318) #define DEFAULT_HARDWARE_OUT_OVERHEAD_US (56) #elif CONFIG_IDF_TARGET_ESP32C61 -#define DEFAULT_SLEEP_OUT_OVERHEAD_US (1148) //TODO: PM-231 +#define DEFAULT_SLEEP_OUT_OVERHEAD_US (318) #define DEFAULT_HARDWARE_OUT_OVERHEAD_US (107) #elif CONFIG_IDF_TARGET_ESP32H2 #define DEFAULT_SLEEP_OUT_OVERHEAD_US (118) @@ -795,8 +799,10 @@ static esp_err_t IRAM_ATTR esp_sleep_start(uint32_t pd_flags, esp_sleep_mode_t m } #endif +#if MSPI_TIMING_LL_FLASH_CPU_CLK_SRC_BINDED // Will switch to XTAL turn down MSPI speed mspi_timing_change_speed_mode_cache_safe(true); +#endif #if SOC_PM_RETENTION_SW_TRIGGER_REGDMA if (!deep_sleep && (pd_flags & PMU_SLEEP_PD_TOP)) { @@ -1132,8 +1138,8 @@ static esp_err_t IRAM_ATTR esp_sleep_start(uint32_t pd_flags, esp_sleep_mode_t m misc_modules_wake_prepare(pd_flags); } -#if SOC_SPI_MEM_SUPPORT_TIMING_TUNING - if (cpu_freq_config.source == SOC_CPU_CLK_SRC_PLL) { +#if MSPI_TIMING_LL_FLASH_CPU_CLK_SRC_BINDED + if (cpu_freq_config.source_freq_mhz > clk_ll_xtal_load_freq_mhz()) { // Turn up MSPI speed if switch to PLL mspi_timing_change_speed_mode_cache_safe(false); } diff --git a/components/esp_pm/pm_impl.c b/components/esp_pm/pm_impl.c index 11b562786d3..790a9c832d8 100644 --- a/components/esp_pm/pm_impl.c +++ b/components/esp_pm/pm_impl.c @@ -24,8 +24,11 @@ #include "esp_private/periph_ctrl.h" #include "soc/rtc.h" +#include "hal/clk_tree_ll.h" #include "hal/uart_ll.h" #include "hal/uart_types.h" +#include "hal/mspi_timing_tuning_ll.h" + #include "driver/gpio.h" #include "freertos/FreeRTOS.h" @@ -35,10 +38,6 @@ #include "xtensa/core-macros.h" #endif -#if SOC_SPI_MEM_SUPPORT_TIMING_TUNING -#include "esp_private/mspi_timing_tuning.h" -#endif - #include "esp_private/pm_impl.h" #include "esp_private/pm_trace.h" #include "esp_private/esp_timer_private.h" @@ -48,6 +47,9 @@ #include "esp_private/sleep_gpio.h" #include "esp_private/sleep_modem.h" #include "esp_private/uart_share_hw_ctrl.h" +#if MSPI_TIMING_LL_FLASH_CPU_CLK_SRC_BINDED +#include "esp_private/mspi_timing_tuning.h" +#endif #include "esp_sleep.h" #include "esp_memory_utils.h" @@ -665,16 +667,16 @@ static void IRAM_ATTR do_switch(pm_mode_t new_mode) if (switch_down) { on_freq_update(old_ticks_per_us, new_ticks_per_us); } -#if SOC_SPI_MEM_SUPPORT_TIMING_TUNING - if (new_config.source == SOC_CPU_CLK_SRC_PLL) { - rtc_clk_cpu_freq_set_config_fast(&new_config); - mspi_timing_change_speed_mode_cache_safe(false); - } else { - mspi_timing_change_speed_mode_cache_safe(true); - rtc_clk_cpu_freq_set_config_fast(&new_config); - } +#if MSPI_TIMING_LL_FLASH_CPU_CLK_SRC_BINDED + if (new_config.source_freq_mhz > clk_ll_xtal_load_freq_mhz()) { + rtc_clk_cpu_freq_set_config_fast(&new_config); + mspi_timing_change_speed_mode_cache_safe(false); + } else { + mspi_timing_change_speed_mode_cache_safe(true); + rtc_clk_cpu_freq_set_config_fast(&new_config); + } #else - rtc_clk_cpu_freq_set_config_fast(&new_config); + rtc_clk_cpu_freq_set_config_fast(&new_config); #endif if (!switch_down) { on_freq_update(old_ticks_per_us, new_ticks_per_us); diff --git a/components/hal/esp32s3/include/hal/mspi_timing_tuning_ll.h b/components/hal/esp32s3/include/hal/mspi_timing_tuning_ll.h index a47e4ffae44..6b3f18bcf6f 100644 --- a/components/hal/esp32s3/include/hal/mspi_timing_tuning_ll.h +++ b/components/hal/esp32s3/include/hal/mspi_timing_tuning_ll.h @@ -37,6 +37,8 @@ extern "C" { #define MSPI_TIMING_LL_CORE_CLOCK_MHZ_DEFAULT 80 +#define MSPI_TIMING_LL_FLASH_CPU_CLK_SRC_BINDED 1 + typedef enum { MSPI_TIMING_LL_FLASH_OPI_MODE = BIT(0), MSPI_TIMING_LL_FLASH_QIO_MODE = BIT(1), From fcdc5d02d4f97369f73bfa675ab72363e39c9531 Mon Sep 17 00:00:00 2001 From: wanckl Date: Thu, 28 Nov 2024 11:19:27 +0800 Subject: [PATCH 066/118] fix(driver_spi): fixed slave_hd driver transaction alignment check --- components/esp_driver_spi/src/gpspi/spi_master.c | 4 ++-- components/esp_driver_spi/src/gpspi/spi_slave.c | 4 ++-- components/esp_driver_spi/src/gpspi/spi_slave_hd.c | 4 ++-- .../esp_driver_spi/test_apps/param/main/test_spi_param.c | 6 ++++-- 4 files changed, 10 insertions(+), 8 deletions(-) diff --git a/components/esp_driver_spi/src/gpspi/spi_master.c b/components/esp_driver_spi/src/gpspi/spi_master.c index b447b40a5f0..d02426f0aa7 100644 --- a/components/esp_driver_spi/src/gpspi/spi_master.c +++ b/components/esp_driver_spi/src/gpspi/spi_master.c @@ -1143,7 +1143,7 @@ static SPI_MASTER_ISR_ATTR esp_err_t setup_priv_desc(spi_host_t *host, spi_trans if (send_ptr && bus_attr->dma_enabled) { if ((!esp_ptr_dma_capable(send_ptr) || tx_unaligned)) { - ESP_RETURN_ON_FALSE(!(trans_desc->flags & SPI_TRANS_DMA_BUFFER_ALIGN_MANUAL), ESP_ERR_INVALID_ARG, SPI_TAG, "Set flag SPI_TRANS_DMA_BUFFER_ALIGN_MANUAL but TX buffer addr&len not align to %d, or not dma_capable", alignment); + ESP_RETURN_ON_FALSE(!(trans_desc->flags & SPI_TRANS_DMA_BUFFER_ALIGN_MANUAL), ESP_ERR_INVALID_ARG, SPI_TAG, "Set flag SPI_TRANS_DMA_BUFFER_ALIGN_MANUAL but TX buffer addr&len not align to %d byte, or not dma_capable", alignment); //if txbuf in the desc not DMA-capable, or not bytes aligned to alignment, malloc a new one ESP_EARLY_LOGD(SPI_TAG, "Allocate TX buffer for DMA"); tx_byte_len = (tx_byte_len + alignment - 1) & (~(alignment - 1)); // up align alignment @@ -1163,7 +1163,7 @@ static SPI_MASTER_ISR_ATTR esp_err_t setup_priv_desc(spi_host_t *host, spi_trans if (rcv_ptr && bus_attr->dma_enabled) { if ((!esp_ptr_dma_capable(rcv_ptr) || rx_unaligned)) { - ESP_RETURN_ON_FALSE(!(trans_desc->flags & SPI_TRANS_DMA_BUFFER_ALIGN_MANUAL), ESP_ERR_INVALID_ARG, SPI_TAG, "Set flag SPI_TRANS_DMA_BUFFER_ALIGN_MANUAL but RX buffer addr&len not align to %d, or not dma_capable", alignment); + ESP_RETURN_ON_FALSE(!(trans_desc->flags & SPI_TRANS_DMA_BUFFER_ALIGN_MANUAL), ESP_ERR_INVALID_ARG, SPI_TAG, "Set flag SPI_TRANS_DMA_BUFFER_ALIGN_MANUAL but RX buffer addr&len not align to %d byte, or not dma_capable", alignment); //if rxbuf in the desc not DMA-capable, or not aligned to alignment, malloc a new one ESP_EARLY_LOGD(SPI_TAG, "Allocate RX buffer for DMA"); rx_byte_len = (rx_byte_len + alignment - 1) & (~(alignment - 1)); // up align alignment diff --git a/components/esp_driver_spi/src/gpspi/spi_slave.c b/components/esp_driver_spi/src/gpspi/spi_slave.c index 58d8b364864..ae9d6d8f8c8 100644 --- a/components/esp_driver_spi/src/gpspi/spi_slave.c +++ b/components/esp_driver_spi/src/gpspi/spi_slave.c @@ -381,7 +381,7 @@ static esp_err_t SPI_SLAVE_ISR_ATTR spi_slave_setup_priv_trans(spi_host_device_t if (spihost[host]->dma_enabled && trans->tx_buffer) { if ((!esp_ptr_dma_capable(trans->tx_buffer) || ((((uint32_t)trans->tx_buffer) | buffer_byte_len) & (alignment - 1)))) { - ESP_RETURN_ON_FALSE_ISR(trans->flags & SPI_SLAVE_TRANS_DMA_BUFFER_ALIGN_AUTO, ESP_ERR_INVALID_ARG, SPI_TAG, "TX buffer addr&len not align to %d, or not dma_capable", alignment); + ESP_RETURN_ON_FALSE_ISR(trans->flags & SPI_SLAVE_TRANS_DMA_BUFFER_ALIGN_AUTO, ESP_ERR_INVALID_ARG, SPI_TAG, "TX buffer addr&len not align to %d byte, or not dma_capable", alignment); //if txbuf in the desc not DMA-capable, or not align to "alignment", malloc a new one ESP_EARLY_LOGD(SPI_TAG, "Allocate TX buffer for DMA"); buffer_byte_len = (buffer_byte_len + alignment - 1) & (~(alignment - 1)); // up align to "alignment" @@ -398,7 +398,7 @@ static esp_err_t SPI_SLAVE_ISR_ATTR spi_slave_setup_priv_trans(spi_host_device_t } if (spihost[host]->dma_enabled && trans->rx_buffer) { if ((!esp_ptr_dma_capable(trans->rx_buffer) || ((((uint32_t)trans->rx_buffer) | (trans->length + 7) / 8) & (alignment - 1)))) { - ESP_RETURN_ON_FALSE_ISR(trans->flags & SPI_SLAVE_TRANS_DMA_BUFFER_ALIGN_AUTO, ESP_ERR_INVALID_ARG, SPI_TAG, "RX buffer addr&len not align to %d, or not dma_capable", alignment); + ESP_RETURN_ON_FALSE_ISR(trans->flags & SPI_SLAVE_TRANS_DMA_BUFFER_ALIGN_AUTO, ESP_ERR_INVALID_ARG, SPI_TAG, "RX buffer addr&len not align to %d byte, or not dma_capable", alignment); //if rxbuf in the desc not DMA-capable, or not align to "alignment", malloc a new one ESP_EARLY_LOGD(SPI_TAG, "Allocate RX buffer for DMA"); buffer_byte_len = (buffer_byte_len + alignment - 1) & (~(alignment - 1)); // up align to "alignment" diff --git a/components/esp_driver_spi/src/gpspi/spi_slave_hd.c b/components/esp_driver_spi/src/gpspi/spi_slave_hd.c index e16f4e86618..adf545d4ee6 100644 --- a/components/esp_driver_spi/src/gpspi/spi_slave_hd.c +++ b/components/esp_driver_spi/src/gpspi/spi_slave_hd.c @@ -648,8 +648,8 @@ static esp_err_t s_spi_slave_hd_setup_priv_trans(spi_host_device_t host, spi_sla uint16_t alignment = spihost[host]->internal_mem_align_size; uint32_t byte_len = orig_trans->len; - if (((uint32_t)orig_trans->data) | (byte_len & (alignment - 1))) { - ESP_RETURN_ON_FALSE(orig_trans->flags & SPI_SLAVE_HD_TRANS_DMA_BUFFER_ALIGN_AUTO, ESP_ERR_INVALID_ARG, TAG, "data buffer addr&len not align to %d, or not dma_capable", alignment); + if (((uint32_t)orig_trans->data | byte_len) & (alignment - 1)) { + ESP_RETURN_ON_FALSE(orig_trans->flags & SPI_SLAVE_HD_TRANS_DMA_BUFFER_ALIGN_AUTO, ESP_ERR_INVALID_ARG, TAG, "data buffer addr&len not align to %d byte, or not dma_capable", alignment); byte_len = (byte_len + alignment - 1) & (~(alignment - 1)); // up align to alignment ESP_LOGD(TAG, "Re-allocate %s buffer of len %" PRIu32 " for DMA", (chan == SPI_SLAVE_CHAN_TX) ? "TX" : "RX", byte_len); priv_trans->aligned_buffer = heap_caps_aligned_alloc(64, byte_len, MALLOC_CAP_DMA); diff --git a/components/esp_driver_spi/test_apps/param/main/test_spi_param.c b/components/esp_driver_spi/test_apps/param/main/test_spi_param.c index 2d097c34e56..9ce4e0348c9 100644 --- a/components/esp_driver_spi/test_apps/param/main/test_spi_param.c +++ b/components/esp_driver_spi/test_apps/param/main/test_spi_param.c @@ -1656,6 +1656,7 @@ static void test_master_hd_no_dma(void) uint32_t test_trans_len = SOC_SPI_MAXIMUM_BUFFER_SIZE; unity_wait_for_signal("Slave ready"); TEST_ESP_OK(essl_spi_rddma(dev0, master_receive, test_trans_len, -1, 0)); + unity_wait_for_signal("Slave ready"); TEST_ESP_OK(essl_spi_wrdma(dev0, master_send, test_trans_len, -1, 0)); ESP_LOG_BUFFER_HEX("master tx", master_send, test_trans_len); @@ -1703,11 +1704,12 @@ static void test_slave_hd_no_dma(void) .len = test_trans_len, .flags = SPI_SLAVE_HD_TRANS_DMA_BUFFER_ALIGN_AUTO, }; - unity_send_signal("Slave ready"); TEST_ESP_OK(spi_slave_hd_queue_trans(TEST_SPI_HOST, SPI_SLAVE_CHAN_TX, &slave_trans, portMAX_DELAY)); + unity_send_signal("Slave ready"); + TEST_ESP_OK(spi_slave_hd_get_trans_res(TEST_SPI_HOST, SPI_SLAVE_CHAN_TX, &ret_trans, portMAX_DELAY)); slave_trans.data = slave_receive; TEST_ESP_OK(spi_slave_hd_queue_trans(TEST_SPI_HOST, SPI_SLAVE_CHAN_RX, &slave_trans, portMAX_DELAY)); - TEST_ESP_OK(spi_slave_hd_get_trans_res(TEST_SPI_HOST, SPI_SLAVE_CHAN_TX, &ret_trans, portMAX_DELAY)); + unity_send_signal("Slave ready"); TEST_ESP_OK(spi_slave_hd_get_trans_res(TEST_SPI_HOST, SPI_SLAVE_CHAN_RX, &ret_trans, portMAX_DELAY)); ESP_LOG_BUFFER_HEX("slave tx", slave_send, test_trans_len); From 0610fa346021954f2f2bbb46703d9212c68434c5 Mon Sep 17 00:00:00 2001 From: wanckl Date: Thu, 28 Nov 2024 11:21:19 +0800 Subject: [PATCH 067/118] fix(driver_spi): fixed slave example error on esp32p4 --- .../peripherals/spi_slave/receiver/main/app_main.c | 9 ++++----- .../spi_slave_hd/append_mode/master/main/app_main.c | 2 +- .../spi_slave_hd/append_mode/slave/main/app_main.c | 4 ++-- .../segment_mode/seg_slave/main/app_main.c | 12 +++++++----- 4 files changed, 14 insertions(+), 13 deletions(-) diff --git a/examples/peripherals/spi_slave/receiver/main/app_main.c b/examples/peripherals/spi_slave/receiver/main/app_main.c index ff90a302c36..f0ee60854b7 100644 --- a/examples/peripherals/spi_slave/receiver/main/app_main.c +++ b/examples/peripherals/spi_slave/receiver/main/app_main.c @@ -96,11 +96,10 @@ void app_main(void) ret = spi_slave_initialize(RCV_HOST, &buscfg, &slvcfg, SPI_DMA_CH_AUTO); assert(ret == ESP_OK); - WORD_ALIGNED_ATTR char sendbuf[129] = ""; - WORD_ALIGNED_ATTR char recvbuf[129] = ""; - memset(recvbuf, 0, 33); - spi_slave_transaction_t t; - memset(&t, 0, sizeof(t)); + char *sendbuf = spi_bus_dma_memory_alloc(RCV_HOST, 129, 0); + char *recvbuf = spi_bus_dma_memory_alloc(RCV_HOST, 129, 0); + assert(sendbuf && recvbuf); + spi_slave_transaction_t t = {0}; while (1) { //Clear receive buffer, set send buffer to something sane diff --git a/examples/peripherals/spi_slave_hd/append_mode/master/main/app_main.c b/examples/peripherals/spi_slave_hd/append_mode/master/main/app_main.c index b16711641af..480921c9826 100644 --- a/examples/peripherals/spi_slave_hd/append_mode/master/main/app_main.c +++ b/examples/peripherals/spi_slave_hd/append_mode/master/main/app_main.c @@ -24,7 +24,7 @@ #define GPIO_CS 10 #define HOST_ID SPI2_HOST -#define TRANSACTION_LEN 16 +#define TRANSACTION_LEN 64 //The SPI transaction cycles in this example. You may change the cycle. e.g., use the ``sender`` and change it to a infinite loop #define EXAMPLE_CYCLES 10 diff --git a/examples/peripherals/spi_slave_hd/append_mode/slave/main/app_main.c b/examples/peripherals/spi_slave_hd/append_mode/slave/main/app_main.c index 49676693b3f..88065a994d9 100644 --- a/examples/peripherals/spi_slave_hd/append_mode/slave/main/app_main.c +++ b/examples/peripherals/spi_slave_hd/append_mode/slave/main/app_main.c @@ -25,7 +25,7 @@ #define HOST_ID SPI2_HOST #define QUEUE_SIZE 6 -#define TRANSACTION_LEN 16 +#define TRANSACTION_LEN 64 #define SYNC_REG_FROM_HOST (14 * 4) #define SYNC_REG_TO_HOST (15 * 4) @@ -72,7 +72,7 @@ static esp_err_t create_transaction_pool(uint8_t **data_buf, trans_link_t *trans { for (int i = 0; i < times; i++) { //malloc data buffers for transaction - data_buf[i] = heap_caps_calloc(1, TRANSACTION_LEN, MALLOC_CAP_DMA); + data_buf[i] = spi_bus_dma_memory_alloc(HOST_ID, TRANSACTION_LEN, 0); if (!data_buf[i]) { ESP_LOGI("Create pool:", "No enough memory"); return ESP_ERR_NO_MEM; diff --git a/examples/peripherals/spi_slave_hd/segment_mode/seg_slave/main/app_main.c b/examples/peripherals/spi_slave_hd/segment_mode/seg_slave/main/app_main.c index ad59703d6b9..e13c3b14990 100644 --- a/examples/peripherals/spi_slave_hd/segment_mode/seg_slave/main/app_main.c +++ b/examples/peripherals/spi_slave_hd/segment_mode/seg_slave/main/app_main.c @@ -198,7 +198,9 @@ void sender(void *arg) data_ready = get_tx_data(send_buf[descriptor_id], send_buf_size, &ready_data_size); if (data_ready) { slave_trans[descriptor_id].data = send_buf[descriptor_id]; - slave_trans[descriptor_id].len = ready_data_size; + slave_trans[descriptor_id].len = send_buf_size; + //To use dma, data buffer address and trans_len should byte align to hardware requirement, or using following flag for auto deal by driver. + slave_trans[descriptor_id].flags |= SPI_SLAVE_HD_TRANS_DMA_BUFFER_ALIGN_AUTO; //Due to the `queue_sent_cnt` and `queue_recv_cnt` logic above, we are sure there is space to send data, this will return ESP_OK immediately ESP_ERROR_CHECK(spi_slave_hd_queue_trans(SLAVE_HOST, SPI_SLAVE_CHAN_TX, &slave_trans[descriptor_id], portMAX_DELAY)); descriptor_id = (descriptor_id + 1) % QUEUE_SIZE; //descriptor_id will be: 0, 1, 2, ..., QUEUE_SIZE, 0, 1, .... @@ -234,7 +236,7 @@ void receiver(void *arg) uint8_t *recv_buf[QUEUE_SIZE]; spi_slave_hd_data_t slave_trans[QUEUE_SIZE]; for (int i = 0; i < QUEUE_SIZE; i++) { - recv_buf[i] = heap_caps_calloc(1, recv_buf_size, MALLOC_CAP_DMA); + recv_buf[i] = spi_bus_dma_memory_alloc(SLAVE_HOST, recv_buf_size, MALLOC_CAP_8BIT); if (!recv_buf[i]) { ESP_LOGE(TAG, "No enough memory!"); abort(); @@ -249,6 +251,7 @@ void receiver(void *arg) for (int i = 0; i < QUEUE_SIZE; i++) { slave_trans[descriptor_id].data = recv_buf[descriptor_id]; slave_trans[descriptor_id].len = recv_buf_size; + slave_trans[descriptor_id].flags |= SPI_SLAVE_HD_TRANS_DMA_BUFFER_ALIGN_AUTO; ESP_ERROR_CHECK(spi_slave_hd_queue_trans(SLAVE_HOST, SPI_SLAVE_CHAN_RX, &slave_trans[descriptor_id], portMAX_DELAY)); descriptor_id = (descriptor_id + 1) % QUEUE_SIZE; //descriptor_id will be: 0, 1, 2, ..., QUEUE_SIZE, 0, 1, .... } @@ -266,7 +269,6 @@ void receiver(void *arg) */ ESP_ERROR_CHECK(spi_slave_hd_get_trans_res(SLAVE_HOST, SPI_SLAVE_CHAN_RX, &ret_trans, portMAX_DELAY)); //Process the received data in your own code. Here we just print it out. - printf("%d bytes are received: \n%s\n", ret_trans->trans_len, ret_trans->data); memset(ret_trans->data, 0x0, recv_buf_size); /** @@ -288,10 +290,10 @@ void app_main(void) uint8_t init_value[SOC_SPI_MAXIMUM_BUFFER_SIZE] = {0x0}; spi_slave_hd_write_buffer(SLAVE_HOST, 0, init_value, SOC_SPI_MAXIMUM_BUFFER_SIZE); - static uint32_t send_buf_size = 5000; + static uint32_t send_buf_size = 4800; spi_slave_hd_write_buffer(SLAVE_HOST, SLAVE_MAX_TX_BUF_LEN_REG, (uint8_t *)&send_buf_size, sizeof(send_buf_size)); - static uint32_t recv_buf_size = 120; + static uint32_t recv_buf_size = 128; spi_slave_hd_write_buffer(SLAVE_HOST, SLAVE_MAX_RX_BUF_LEN_REG, (uint8_t *)&recv_buf_size, sizeof(recv_buf_size)); uint32_t slave_ready_flag = SLAVE_READY_FLAG; From 33b6da9d5a921a04ad2565da9950daa8438cd3f6 Mon Sep 17 00:00:00 2001 From: shenmengjing Date: Thu, 12 Dec 2024 16:13:09 +0800 Subject: [PATCH 068/118] docs: Update CN translation for libs-frameworks.rst --- docs/en/libraries-and-frameworks/libs-frameworks.rst | 2 +- docs/zh_CN/libraries-and-frameworks/libs-frameworks.rst | 2 ++ 2 files changed, 3 insertions(+), 1 deletion(-) diff --git a/docs/en/libraries-and-frameworks/libs-frameworks.rst b/docs/en/libraries-and-frameworks/libs-frameworks.rst index 5da641982e9..b52b9323926 100644 --- a/docs/en/libraries-and-frameworks/libs-frameworks.rst +++ b/docs/en/libraries-and-frameworks/libs-frameworks.rst @@ -98,7 +98,7 @@ ESP-Protocols components: * `esp_wifi_remote `_ is a Wi-Fi communication library that provides standard Wi-Fi API and networking of an external, Wi-Fi capable ESP32 chipset connected to the target device via a specified transport interface. See the :doc:`../api-guides/wifi-expansion`. -* `esp-extconn `_ is a Wi-Fi communication library that provides external wireless connectivity(Wi-Fi & Bluetooth) for ESP chips that do not have built-in wireless capabilities. See the :doc:`../api-guides/wifi-expansion`. +* `esp-extconn `_ is a Wi-Fi communication library that provides external wireless connectivity (Wi-Fi and Bluetooth) for ESP chips that do not have built-in wireless capabilities. See the :doc:`../api-guides/wifi-expansion`. ESP-BSP ------- diff --git a/docs/zh_CN/libraries-and-frameworks/libs-frameworks.rst b/docs/zh_CN/libraries-and-frameworks/libs-frameworks.rst index 9dc2d0492c4..9e31cf5a74e 100644 --- a/docs/zh_CN/libraries-and-frameworks/libs-frameworks.rst +++ b/docs/zh_CN/libraries-and-frameworks/libs-frameworks.rst @@ -98,6 +98,8 @@ ESP-Protocols 组件： * `esp_wifi_remote `_ 是一个 Wi-Fi 通信库，提供标准的 Wi-Fi API，并且能够借助指定的传输接口，帮助目标设备通过外部 ESP32 芯片实现 Wi-Fi 通信。详情请参阅 :doc:`../api-guides/wifi-expansion`。 +* `esp-extconn `_ 是一个 Wi-Fi 通信库，为不具备内置无线功能的 ESP 芯片提供外部无线连接（Wi-Fi 和蓝牙）。详情请参阅 :doc:`../api-guides/wifi-expansion`。 + ESP-BSP ------- From 07862cf93e955f54de36fa9356338f69dd26c698 Mon Sep 17 00:00:00 2001 From: gaoxu Date: Sat, 14 Dec 2024 17:08:19 +0800 Subject: [PATCH 069/118] feat(esp32h21): fix soc file and add soc files from verification branch (stage 2-3) --- .../test_apps/.build-test-rules.yml | 4 + .../esp32h21/include/soc/Kconfig.soc_caps.in | 692 ++++ .../soc/esp32h21/include/soc/boot_mode.h | 91 + .../soc/esp32h21/include/soc/clk_tree_defs.h | 266 ++ .../soc/esp32h21/include/soc/dport_access.h | 108 + .../soc/esp32h21/include/soc/efuse_defs.h | 17 + .../soc/esp32h21/include/soc/ext_mem_defs.h | 131 + .../soc/esp32h21/include/soc/gpio_num.h | 51 + .../soc/esp32h21/include/soc/gpio_pins.h | 20 + .../soc/esp32h21/include/soc/periph_defs.h | 67 + .../soc/esp32h21/include/soc/regi2c_bbpll.h | 35 + .../soc/esp32h21/include/soc/regi2c_bias.h | 26 + .../soc/esp32h21/include/soc/regi2c_defs.h | 34 + .../soc/esp32h21/include/soc/regi2c_lp_bias.h | 23 + .../soc/esp32h21/include/soc/regi2c_pmu.h | 52 + .../soc/esp32h21/include/soc/regi2c_saradc.h | 19 + .../soc/esp32h21/include/soc/reset_reasons.h | 53 + components/soc/esp32h21/include/soc/soc.h | 237 ++ .../soc/esp32h21/include/soc/soc_caps.h | 557 +++ .../soc/esp32h21/include/soc/soc_pins.h | 16 + .../soc/esp32h21/include/soc/spi_pins.h | 28 + .../soc/esp32h21/include/soc/uart_channel.h | 18 + .../soc/esp32h21/include/soc/uart_pins.h | 37 + .../soc/esp32h21/include/soc/wdev_reg.h | 13 + .../esp32h21/register/soc/assist_debug_reg.h | 64 +- .../soc/esp32h21/register/soc/efuse_reg.h | 2049 ++++++----- .../soc/esp32h21/register/soc/efuse_struct.h | 2591 +++++++++----- .../soc/esp32h21/register/soc/gdma_reg.h | 3161 +++++++++++++++++ .../soc/esp32h21/register/soc/gdma_struct.h | 1090 ++++++ .../esp32h21/register/soc/i2c_ana_mst_reg.h | 220 ++ .../register/soc/interrupt_matrix_reg.h | 1 - .../soc/esp32h21/register/soc/interrupt_reg.h | 24 + .../soc/esp32h21/register/soc/io_mux_reg.h | 365 ++ .../soc/esp32h21/register/soc/lp_timer_reg.h | 242 ++ .../esp32h21/register/soc/lp_timer_struct.h | 258 ++ .../soc/esp32h21/register/soc/lpperi_reg.h | 388 ++ .../soc/esp32h21/register/soc/lpperi_struct.h | 352 ++ .../soc/esp32h21/register/soc/pcr_struct.h | 4 +- .../soc/esp32h21/register/soc/plic_reg.h | 635 ++++ .../soc/esp32h21/register/soc/pmu_reg.h | 1432 +++----- .../soc/esp32h21/register/soc/pmu_struct.h | 3127 +++------------- .../soc/esp32h21/register/soc/spi1_mem_reg.h | 88 +- .../soc/esp32h21/register/soc/spi_mem_c_reg.h | 260 +- .../soc/esp32h21/register/soc/spi_struct.h | 221 +- .../soc/esp32h21/register/soc/system_reg.h | 11 + .../esp32h21/register/soc/systimer_struct.h | 231 +- .../register/soc/timer_group_struct.h | 21 +- .../soc/esp32h21/register/soc/uart_reg.h | 76 +- .../soc/esp32h21/register/soc/xts_aes_reg.h | 129 + 49 files changed, 13725 insertions(+), 5910 deletions(-) create mode 100644 components/soc/esp32h21/include/soc/Kconfig.soc_caps.in create mode 100644 components/soc/esp32h21/include/soc/boot_mode.h create mode 100644 components/soc/esp32h21/include/soc/clk_tree_defs.h create mode 100644 components/soc/esp32h21/include/soc/dport_access.h create mode 100644 components/soc/esp32h21/include/soc/efuse_defs.h create mode 100644 components/soc/esp32h21/include/soc/ext_mem_defs.h create mode 100644 components/soc/esp32h21/include/soc/gpio_num.h create mode 100644 components/soc/esp32h21/include/soc/gpio_pins.h create mode 100644 components/soc/esp32h21/include/soc/periph_defs.h create mode 100644 components/soc/esp32h21/include/soc/regi2c_bbpll.h create mode 100644 components/soc/esp32h21/include/soc/regi2c_bias.h create mode 100644 components/soc/esp32h21/include/soc/regi2c_defs.h create mode 100644 components/soc/esp32h21/include/soc/regi2c_lp_bias.h create mode 100644 components/soc/esp32h21/include/soc/regi2c_pmu.h create mode 100644 components/soc/esp32h21/include/soc/regi2c_saradc.h create mode 100644 components/soc/esp32h21/include/soc/reset_reasons.h create mode 100644 components/soc/esp32h21/include/soc/soc.h create mode 100644 components/soc/esp32h21/include/soc/soc_caps.h create mode 100644 components/soc/esp32h21/include/soc/soc_pins.h create mode 100644 components/soc/esp32h21/include/soc/spi_pins.h create mode 100644 components/soc/esp32h21/include/soc/uart_channel.h create mode 100644 components/soc/esp32h21/include/soc/uart_pins.h create mode 100644 components/soc/esp32h21/include/soc/wdev_reg.h create mode 100644 components/soc/esp32h21/register/soc/gdma_reg.h create mode 100644 components/soc/esp32h21/register/soc/gdma_struct.h create mode 100644 components/soc/esp32h21/register/soc/i2c_ana_mst_reg.h create mode 100644 components/soc/esp32h21/register/soc/interrupt_reg.h create mode 100644 components/soc/esp32h21/register/soc/io_mux_reg.h create mode 100644 components/soc/esp32h21/register/soc/lp_timer_reg.h create mode 100644 components/soc/esp32h21/register/soc/lp_timer_struct.h create mode 100644 components/soc/esp32h21/register/soc/lpperi_reg.h create mode 100644 components/soc/esp32h21/register/soc/lpperi_struct.h create mode 100644 components/soc/esp32h21/register/soc/plic_reg.h create mode 100644 components/soc/esp32h21/register/soc/system_reg.h create mode 100644 components/soc/esp32h21/register/soc/xts_aes_reg.h diff --git a/components/bootloader_support/test_apps/.build-test-rules.yml b/components/bootloader_support/test_apps/.build-test-rules.yml index 1dbe91f9132..cfeda3b74de 100644 --- a/components/bootloader_support/test_apps/.build-test-rules.yml +++ b/components/bootloader_support/test_apps/.build-test-rules.yml @@ -4,3 +4,7 @@ components/bootloader_support/test_apps/rtc_custom_section: enable: - if: SOC_RTC_MEM_SUPPORTED == 1 reason: this feature is supported on chips that have RTC memory + disable: + - if: IDF_TARGET == "esp32h21" + temporary: true + reason: IDF-11534 diff --git a/components/soc/esp32h21/include/soc/Kconfig.soc_caps.in b/components/soc/esp32h21/include/soc/Kconfig.soc_caps.in new file mode 100644 index 00000000000..1804b910c14 --- /dev/null +++ b/components/soc/esp32h21/include/soc/Kconfig.soc_caps.in @@ -0,0 +1,692 @@ +##################################################### +# This file is auto-generated from SoC caps +# using gen_soc_caps_kconfig.py, do not edit manually +##################################################### + +config SOC_UART_SUPPORTED + bool + default y + +config SOC_EFUSE_KEY_PURPOSE_FIELD + bool + default y + +config SOC_EFUSE_SUPPORTED + bool + default y + +config SOC_RTC_MEM_SUPPORTED + bool + default y + +config SOC_SYSTIMER_SUPPORTED + bool + default y + +config SOC_FLASH_ENC_SUPPORTED + bool + default y + +config SOC_PMU_SUPPORTED + bool + default y + +config SOC_SPI_FLASH_SUPPORTED + bool + default y + +config SOC_XTAL_SUPPORT_32M + bool + default y + +config SOC_AES_SUPPORT_DMA + bool + default y + +config SOC_AES_GDMA + bool + default y + +config SOC_AES_SUPPORT_AES_128 + bool + default y + +config SOC_AES_SUPPORT_AES_256 + bool + default y + +config SOC_ADC_PERIPH_NUM + int + default 1 + +config SOC_ADC_MAX_CHANNEL_NUM + int + default 5 + +config SOC_ADC_ATTEN_NUM + int + default 4 + +config SOC_ADC_DIGI_CONTROLLER_NUM + int + default 1 + +config SOC_ADC_PATT_LEN_MAX + int + default 8 + +config SOC_ADC_DIGI_MAX_BITWIDTH + int + default 12 + +config SOC_ADC_DIGI_MIN_BITWIDTH + int + default 12 + +config SOC_ADC_DIGI_IIR_FILTER_NUM + int + default 2 + +config SOC_ADC_DIGI_MONITOR_NUM + int + default 2 + +config SOC_ADC_DIGI_RESULT_BYTES + int + default 4 + +config SOC_ADC_DIGI_DATA_BYTES_PER_CONV + int + default 4 + +config SOC_ADC_SAMPLE_FREQ_THRES_HIGH + int + default 83333 + +config SOC_ADC_SAMPLE_FREQ_THRES_LOW + int + default 611 + +config SOC_ADC_RTC_MIN_BITWIDTH + int + default 12 + +config SOC_ADC_RTC_MAX_BITWIDTH + int + default 12 + +config SOC_APB_BACKUP_DMA + bool + default n + +config SOC_BROWNOUT_RESET_SUPPORTED + bool + default y + +config SOC_SHARED_IDCACHE_SUPPORTED + bool + default y + +config SOC_CACHE_FREEZE_SUPPORTED + bool + default y + +config SOC_CPU_CORES_NUM + int + default 1 + +config SOC_CPU_INTR_NUM + int + default 32 + +config SOC_CPU_HAS_FLEXIBLE_INTC + bool + default y + +config SOC_INT_PLIC_SUPPORTED + bool + default y + +config SOC_CPU_HAS_CSR_PC + bool + default y + +config SOC_CPU_BREAKPOINTS_NUM + int + default 4 + +config SOC_CPU_WATCHPOINTS_NUM + int + default 4 + +config SOC_CPU_WATCHPOINT_MAX_REGION_SIZE + hex + default 0x80000000 + +config SOC_CPU_HAS_PMA + bool + default y + +config SOC_CPU_IDRAM_SPLIT_USING_PMP + bool + default y + +config SOC_CPU_PMP_REGION_GRANULARITY + int + default 4 + +config SOC_MMU_PERIPH_NUM + int + default 1 + +config SOC_MMU_LINEAR_ADDRESS_REGION_NUM + int + default 1 + +config SOC_MMU_DI_VADDR_SHARED + bool + default y + +config SOC_DS_SIGNATURE_MAX_BIT_LEN + int + default 3072 + +config SOC_DS_KEY_PARAM_MD_IV_LENGTH + int + default 16 + +config SOC_DS_KEY_CHECK_MAX_WAIT_US + int + default 1100 + +config SOC_AHB_GDMA_VERSION + int + default 1 + +config SOC_GDMA_NUM_GROUPS_MAX + int + default 1 + +config SOC_GDMA_PAIRS_PER_GROUP_MAX + int + default 3 + +config SOC_ETM_GROUPS + int + default 1 + +config SOC_ETM_CHANNELS_PER_GROUP + int + default 50 + +config SOC_GPIO_PORT + int + default 1 + +config SOC_GPIO_PIN_COUNT + int + default 28 + +config SOC_GPIO_SUPPORT_RTC_INDEPENDENT + bool + default y + +config SOC_LP_IO_CLOCK_IS_INDEPENDENT + bool + default y + +config SOC_GPIO_IN_RANGE_MAX + int + default 27 + +config SOC_GPIO_OUT_RANGE_MAX + int + default 27 + +config SOC_GPIO_VALID_DIGITAL_IO_PAD_MASK + hex + default 0x000000000FFF807F + +config SOC_GPIO_CLOCKOUT_BY_GPIO_MATRIX + bool + default y + +config SOC_CLOCKOUT_HAS_SOURCE_GATE + bool + default y + +config SOC_GPIO_CLOCKOUT_CHANNEL_NUM + int + default 3 + +config SOC_DEDIC_GPIO_OUT_CHANNELS_NUM + int + default 8 + +config SOC_DEDIC_GPIO_IN_CHANNELS_NUM + int + default 8 + +config SOC_DEDIC_PERIPH_ALWAYS_ENABLE + bool + default y + +config SOC_ANA_CMPR_NUM + int + default 1 + +config SOC_ANA_CMPR_INTR_SHARE_WITH_GPIO + bool + default y + +config SOC_MPI_MEM_BLOCKS_NUM + int + default 4 + +config SOC_MPI_OPERATIONS_NUM + int + default 3 + +config SOC_RSA_MAX_BIT_LEN + int + default 3072 + +config SOC_SHA_DMA_MAX_BUFFER_SIZE + int + default 3968 + +config SOC_SHA_SUPPORT_DMA + bool + default y + +config SOC_SHA_SUPPORT_RESUME + bool + default y + +config SOC_SHA_GDMA + bool + default y + +config SOC_SHA_SUPPORT_SHA1 + bool + default y + +config SOC_SHA_SUPPORT_SHA224 + bool + default y + +config SOC_SHA_SUPPORT_SHA256 + bool + default y + +config SOC_SPI_PERIPH_NUM + int + default 2 + +config SOC_SPI_MAX_CS_NUM + int + default 6 + +config SOC_SPI_MAXIMUM_BUFFER_SIZE + int + default 64 + +config SOC_SPI_SUPPORT_DDRCLK + bool + default y + +config SOC_SPI_SLAVE_SUPPORT_SEG_TRANS + bool + default y + +config SOC_SPI_SUPPORT_CD_SIG + bool + default y + +config SOC_SPI_SUPPORT_CONTINUOUS_TRANS + bool + default y + +config SOC_SPI_SUPPORT_SLAVE_HD_VER2 + bool + default y + +config SOC_SPI_SUPPORT_CLK_XTAL + bool + default y + +config SOC_SPI_SUPPORT_CLK_PLL_F48M + bool + default y + +config SOC_SPI_SUPPORT_CLK_RC_FAST + bool + default y + +config SOC_SPI_SCT_SUPPORTED + bool + default y + +config SOC_SPI_SCT_REG_NUM + int + default 14 + +config SOC_SPI_SCT_BUFFER_NUM_MAX + bool + default y + +config SOC_SPI_SCT_CONF_BITLEN_MAX + hex + default 0x3FFFA + +config SOC_MEMSPI_IS_INDEPENDENT + bool + default y + +config SOC_SPI_MAX_PRE_DIVIDER + int + default 16 + +config SOC_SPI_MEM_SUPPORT_AUTO_WAIT_IDLE + bool + default y + +config SOC_SPI_MEM_SUPPORT_AUTO_SUSPEND + bool + default y + +config SOC_SPI_MEM_SUPPORT_AUTO_RESUME + bool + default y + +config SOC_SPI_MEM_SUPPORT_IDLE_INTR + bool + default y + +config SOC_SPI_MEM_SUPPORT_SW_SUSPEND + bool + default y + +config SOC_SPI_MEM_SUPPORT_CHECK_SUS + bool + default y + +config SOC_SPI_MEM_SUPPORT_WRAP + bool + default y + +config SOC_MEMSPI_SRC_FREQ_64M_SUPPORTED + bool + default y + +config SOC_MEMSPI_SRC_FREQ_32M_SUPPORTED + bool + default y + +config SOC_MEMSPI_SRC_FREQ_16M_SUPPORTED + bool + default y + +config SOC_SYSTIMER_COUNTER_NUM + int + default 2 + +config SOC_SYSTIMER_ALARM_NUM + int + default 3 + +config SOC_SYSTIMER_BIT_WIDTH_LO + int + default 32 + +config SOC_SYSTIMER_BIT_WIDTH_HI + int + default 20 + +config SOC_SYSTIMER_FIXED_DIVIDER + bool + default y + +config SOC_SYSTIMER_SUPPORT_RC_FAST + bool + default y + +config SOC_SYSTIMER_INT_LEVEL + bool + default y + +config SOC_SYSTIMER_ALARM_MISS_COMPENSATE + bool + default y + +config SOC_LP_TIMER_BIT_WIDTH_LO + int + default 32 + +config SOC_LP_TIMER_BIT_WIDTH_HI + int + default 16 + +config SOC_TIMER_GROUPS + int + default 2 + +config SOC_TIMER_GROUP_TIMERS_PER_GROUP + int + default 1 + +config SOC_TIMER_GROUP_COUNTER_BIT_WIDTH + int + default 54 + +config SOC_TIMER_GROUP_SUPPORT_XTAL + bool + default y + +config SOC_TIMER_GROUP_SUPPORT_RC_FAST + bool + default y + +config SOC_TIMER_GROUP_TOTAL_TIMERS + int + default 2 + +config SOC_MWDT_SUPPORT_XTAL + bool + default y + +config SOC_EFUSE_DIS_PAD_JTAG + bool + default y + +config SOC_EFUSE_DIS_USB_JTAG + bool + default y + +config SOC_EFUSE_DIS_DIRECT_BOOT + bool + default y + +config SOC_EFUSE_SOFT_DIS_JTAG + bool + default y + +config SOC_EFUSE_DIS_ICACHE + bool + default y + +config SOC_EFUSE_BLOCK9_KEY_PURPOSE_QUIRK + bool + default y + +config SOC_EFUSE_ECDSA_USE_HARDWARE_K + bool + default y + +config SOC_EFUSE_ECDSA_KEY + bool + default y + +config SOC_SECURE_BOOT_V2_RSA + bool + default y + +config SOC_SECURE_BOOT_V2_ECC + bool + default y + +config SOC_EFUSE_SECURE_BOOT_KEY_DIGESTS + int + default 3 + +config SOC_EFUSE_REVOKE_BOOT_KEY_DIGESTS + bool + default y + +config SOC_SUPPORT_SECURE_BOOT_REVOKE_KEY + bool + default y + +config SOC_FLASH_ENCRYPTED_XTS_AES_BLOCK_MAX + int + default 64 + +config SOC_FLASH_ENCRYPTION_XTS_AES + bool + default y + +config SOC_FLASH_ENCRYPTION_XTS_AES_128 + bool + default y + +config SOC_APM_CTRL_FILTER_SUPPORTED + bool + default y + +config SOC_CRYPTO_DPA_PROTECTION_SUPPORTED + bool + default y + +config SOC_ECDSA_USES_MPI + bool + default y + +config SOC_UART_NUM + int + default 2 + +config SOC_UART_HP_NUM + int + default 2 + +config SOC_UART_FIFO_LEN + int + default 128 + +config SOC_UART_BITRATE_MAX + int + default 5000000 + +config SOC_UART_SUPPORT_RTC_CLK + bool + default y + +config SOC_UART_SUPPORT_XTAL_CLK + bool + default y + +config SOC_UART_SUPPORT_WAKEUP_INT + bool + default y + +config SOC_UART_SUPPORT_FSM_TX_WAIT_SEND + bool + default y + +config SOC_COEX_HW_PTI + bool + default y + +config SOC_EXTERNAL_COEX_ADVANCE + bool + default y + +config SOC_EXTERNAL_COEX_LEADER_TX_LINE + bool + default n + +config SOC_PHY_DIG_REGS_MEM_SIZE + int + default 21 + +config SOC_PM_SUPPORT_BT_WAKEUP + bool + default y + +config SOC_PM_SUPPORT_EXT1_WAKEUP + bool + default y + +config SOC_PM_SUPPORT_EXT1_WAKEUP_MODE_PER_PIN + bool + default y + +config SOC_PM_SUPPORT_CPU_PD + bool + default y + +config SOC_PM_SUPPORT_MODEM_PD + bool + default y + +config SOC_PM_SUPPORT_XTAL32K_PD + bool + default y + +config SOC_PM_SUPPORT_RC32K_PD + bool + default y + +config SOC_PM_SUPPORT_RC_FAST_PD + bool + default y + +config SOC_PM_SUPPORT_VDDSDIO_PD + bool + default y + +config SOC_PM_SUPPORT_TOP_PD + bool + default y + +config SOC_PM_PAU_LINK_NUM + int + default 4 + +config SOC_CLK_RC_FAST_SUPPORT_CALIBRATION + bool + default y + +config SOC_CLK_XTAL32K_SUPPORTED + bool + default y + +config SOC_CLK_OSC_SLOW_SUPPORTED + bool + default y + +config SOC_CLK_RC32K_SUPPORTED + bool + default y + +config SOC_CLK_LP_FAST_SUPPORT_LP_PLL + bool + default y + +config SOC_MODEM_CLOCK_IS_INDEPENDENT + bool + default y + +config SOC_RCC_IS_INDEPENDENT + bool + default y diff --git a/components/soc/esp32h21/include/soc/boot_mode.h b/components/soc/esp32h21/include/soc/boot_mode.h new file mode 100644 index 00000000000..6f4e3d408cd --- /dev/null +++ b/components/soc/esp32h21/include/soc/boot_mode.h @@ -0,0 +1,91 @@ +/* + * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef _SOC_BOOT_MODE_H_ +#define _SOC_BOOT_MODE_H_ + +#include "soc.h" + +/*SPI Boot*/ +#define IS_1XXX(v) (((v)&0x08)==0x08) + +/*Download Boot, SPI(or SDIO_V2)/UART0*/ +#define IS_00XX(v) (((v)&0x0c)==0x00) + +/*Download Boot, SDIO/UART0/UART1,FEI_FEO V2*/ +#define IS_0000(v) (((v)&0x0f)==0x00) + +/*Download Boot, SDIO/UART0/UART1,FEI_REO V2*/ +#define IS_0001(v) (((v)&0x0f)==0x01) + +/*Download Boot, SDIO/UART0/UART1,REI_FEO V2*/ +#define IS_0010(v) (((v)&0x0f)==0x02) + +/*Download Boot, SDIO/UART0/UART1,REI_REO V2*/ +#define IS_0011(v) (((v)&0x0f)==0x03) + +/*legacy SPI Boot*/ +#define IS_0100(v) (((v)&0x0f)==0x04) + +/*ATE/ANALOG Mode*/ +#define IS_0101(v) (((v)&0x0f)==0x05) + +/*SPI(or SDIO_V1) download Mode*/ +#define IS_0110(v) (((v)&0x0f)==0x06) + +/*Diagnostic Mode+UART0 download Mode*/ +#define IS_0111(v) (((v)&0x0f)==0x07) + +#define BOOT_MODE_GET() (GPIO_REG_READ(GPIO_STRAP_REG)) + +/*do not include download mode*/ +#define ETS_IS_UART_BOOT() IS_0111(BOOT_MODE_GET()) + +/*all spi boot including spi/legacy*/ +#define ETS_IS_FLASH_BOOT() (IS_1XXX(BOOT_MODE_GET()) || IS_0100(BOOT_MODE_GET())) + +/*all faster spi boot including spi*/ +#define ETS_IS_FAST_FLASH_BOOT() IS_1XXX(BOOT_MODE_GET()) + +#if SUPPORT_SDIO_DOWNLOAD + +/*all sdio V2 of failing edge input, failing edge output*/ +#define ETS_IS_SDIO_FEI_FEO_V2_BOOT() IS_0000(BOOT_MODE_GET()) + +/*all sdio V2 of failing edge input, raising edge output*/ +#define ETS_IS_SDIO_FEI_REO_V2_BOOT() IS_0001(BOOT_MODE_GET()) + +/*all sdio V2 of raising edge input, failing edge output*/ +#define ETS_IS_SDIO_REI_FEO_V2_BOOT() IS_0010(BOOT_MODE_GET()) + +/*all sdio V2 of raising edge input, raising edge output*/ +#define ETS_IS_SDIO_REI_REO_V2_BOOT() IS_0011(BOOT_MODE_GET()) + +/*all sdio V1 of raising edge input, failing edge output*/ +#define ETS_IS_SDIO_REI_FEO_V1_BOOT() IS_0110(BOOT_MODE_GET()) + +/*do not include joint download mode*/ +#define ETS_IS_SDIO_BOOT() IS_0110(BOOT_MODE_GET()) +#else + +/*do not include joint download mode*/ +#define ETS_IS_SPI_DOWNLOAD_BOOT() IS_0110(BOOT_MODE_GET()) + +#endif + +/*joint download boot*/ +#define ETS_IS_JOINT_DOWNLOAD_BOOT() IS_00XX(BOOT_MODE_GET()) + +/*ATE mode*/ +#define ETS_IS_ATE_BOOT() IS_0101(BOOT_MODE_GET()) + +/*used by ETS_IS_SDIO_UART_BOOT*/ +#define SEL_NO_BOOT 0 +#define SEL_SDIO_BOOT BIT0 +#define SEL_UART_BOOT BIT1 +#define SEL_SPI_SLAVE_BOOT BIT2 + +#endif /* _SOC_BOOT_MODE_H_ */ diff --git a/components/soc/esp32h21/include/soc/clk_tree_defs.h b/components/soc/esp32h21/include/soc/clk_tree_defs.h new file mode 100644 index 00000000000..cf93f787369 --- /dev/null +++ b/components/soc/esp32h21/include/soc/clk_tree_defs.h @@ -0,0 +1,266 @@ +/* + * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#ifdef __cplusplus +extern "C" { +#endif + +/* + ************************* ESP32H21 Root Clock Source **************************** + * 1) Internal 8MHz RC Oscillator: RC_FAST (usually referred as FOSC in TRM and reg. description) + * + * This RC oscillator generates a ~8.5MHz clock signal output as the RC_FAST_CLK. + * + * The exact frequency of RC_FAST_CLK can be computed in runtime through calibration. + * + * 2) External 32MHz Crystal Clock: XTAL + * + * 3) Internal 136kHz RC Oscillator: RC_SLOW (usually referred as SOSC in TRM or reg. description) + * + * This RC oscillator generates a ~136kHz clock signal output as the RC_SLOW_CLK. The exact frequency of this clock + * can be computed in runtime through calibration. + * + * 4) Internal 32kHz RC Oscillator: RC32K + * + * The exact frequency of this clock can be computed in runtime through calibration. + * + * 5) External 32kHz Crystal Clock (optional): XTAL32K + * + * The clock source for this XTAL32K_CLK should be a 32kHz crystal connecting to the XTAL_32K_P and XTAL_32K_N + * pins. + * + * XTAL32K_CLK can also be calibrated to get its exact frequency. + * + * 6) External Slow Clock (optional): OSC_SLOW + * + * A slow clock signal generated by an external circuit can be connected to GPIO13 to be the clock source for the + * RTC_SLOW_CLK. + * + * OSC_SLOW_CLK can also be calibrated to get its exact frequency. + */ + +/* With the default value of CK8M_DFREQ = 860, RC_FAST clock frequency is 8.5 MHz +/- 7% */ +#define SOC_CLK_RC_FAST_FREQ_APPROX 8500000 /*!< Approximate RC_FAST_CLK frequency in Hz */ +#define SOC_CLK_RC_SLOW_FREQ_APPROX 136000 /*!< Approximate RC_SLOW_CLK frequency in Hz */ +#define SOC_CLK_RC32K_FREQ_APPROX 32768 /*!< Approximate RC32K_CLK frequency in Hz */ +#define SOC_CLK_XTAL32K_FREQ_APPROX 32768 /*!< Approximate XTAL32K_CLK frequency in Hz */ +#define SOC_CLK_OSC_SLOW_FREQ_APPROX 32768 /*!< Approximate OSC_SLOW_CLK (external slow clock) frequency in Hz */ + +/** + * @brief CPU_CLK mux inputs, which are the supported clock sources for the CPU_CLK + * @note Enum values are matched with the register field values on purpose + */ +typedef enum { + SOC_CPU_CLK_SRC_XTAL = 0, /*!< Select XTAL_CLK as CPU_CLK source */ + SOC_CPU_CLK_SRC_PLL = 1, /*!< Select PLL_CLK as CPU_CLK source (PLL_CLK is one of the outputs of 32MHz crystal oscillator frequency multiplier, 96MHz) */ + SOC_CPU_CLK_SRC_RC_FAST = 2, /*!< Select RC_FAST_CLK as CPU_CLK source */ + SOC_CPU_CLK_SRC_FLASH_PLL = 3, /*!< Select FLASH_PLL_CLK as CPU_CLK source (FLASH_PLL_CLK is the other output of 32MHz crystal oscillator frequency multiplier, 64MHz) */ + SOC_CPU_CLK_SRC_INVALID, /*!< Invalid CPU_CLK source */ +} soc_cpu_clk_src_t; + +/** + * @brief RTC_SLOW_CLK mux inputs, which are the supported clock sources for the RTC_SLOW_CLK + * @note Enum values are matched with the register field values on purpose + */ +typedef enum { + SOC_RTC_SLOW_CLK_SRC_RC_SLOW = 0, /*!< Select RC_SLOW_CLK as RTC_SLOW_CLK source */ + SOC_RTC_SLOW_CLK_SRC_XTAL32K = 1, /*!< Select XTAL32K_CLK as RTC_SLOW_CLK source */ + SOC_RTC_SLOW_CLK_SRC_RC32K = 2, /*!< Select RC32K_CLK as RTC_SLOW_CLK source */ + SOC_RTC_SLOW_CLK_SRC_OSC_SLOW = 3, /*!< Select OSC_SLOW_CLK (external slow clock) as RTC_SLOW_CLK source */ + SOC_RTC_SLOW_CLK_SRC_INVALID, /*!< Invalid RTC_SLOW_CLK source */ +} soc_rtc_slow_clk_src_t; + +/** + * @brief RTC_FAST_CLK mux inputs, which are the supported clock sources for the RTC_FAST_CLK + * @note Enum values are matched with the register field values on purpose + */ +typedef enum { + SOC_RTC_FAST_CLK_SRC_RC_FAST = 0, /*!< Select RC_FAST_CLK as RTC_FAST_CLK source */ + SOC_RTC_FAST_CLK_SRC_XTAL_D2 = 1, /*!< Select XTAL_D2_CLK (may referred as XTAL_CLK_DIV_2) as RTC_FAST_CLK source */ + SOC_RTC_FAST_CLK_SRC_XTAL_DIV = SOC_RTC_FAST_CLK_SRC_XTAL_D2, /*!< Alias name for `SOC_RTC_FAST_CLK_SRC_XTAL_D2` */ + SOC_RTC_FAST_CLK_SRC_LP_PLL = 2, /*!< Select LP_PLL_CLK as RTC_FAST_CLK source (LP_PLL_CLK is a 8MHz clock sourced from RC32K or XTAL32K)*/ + SOC_RTC_FAST_CLK_SRC_INVALID, /*!< Invalid RTC_FAST_CLK source */ + + SOC_RTC_FAST_CLK_SRC_DEFAULT = SOC_RTC_FAST_CLK_SRC_XTAL_D2, /*!< XTAL_D2_CLK is the default clock source for RTC_FAST_CLK */ + +} soc_rtc_fast_clk_src_t; + +/** + * @brief LP_PLL_CLK mux inputs, which are the supported clock sources for the LP_PLL_CLK + * @note Enum values are matched with the register field values on purpose + */ +typedef enum { + SOC_LP_PLL_CLK_SRC_RC32K = 0, /*!< Select RC32K_CLK as LP_PLL_CLK source */ + SOC_LP_PLL_CLK_SRC_XTAL32K = 1, /*!< Select XTAL32K_CLK as LP_PLL_CLK source */ + SOC_LP_PLL_CLK_SRC_INVALID, /*!< Invalid LP_PLL_CLK source */ +} soc_lp_pll_clk_src_t; + +/** + * @brief Possible main XTAL frequency options on the target + * @note Enum values equal to the frequency value in MHz + * @note Not all frequency values listed here are supported in IDF. Please check SOC_XTAL_SUPPORT_XXX in soc_caps.h for + * the supported ones. + */ +typedef enum { + SOC_XTAL_FREQ_32M = 32, /*!< 32MHz XTAL */ +} soc_xtal_freq_t; + +// Naming convention: SOC_MOD_CLK_{[upstream]clock_name}_[attr] +// {[upstream]clock_name}: XTAL, (BB)PLL, etc. +// [attr] - optional: FAST, SLOW, D, F +/** + * @brief Supported clock sources for modules (CPU, peripherals, RTC, etc.) + * + * @note enum starts from 1, to save 0 for special purpose + */ +typedef enum { + // For CPU domain + SOC_MOD_CLK_CPU = 1, /*!< CPU_CLK can be sourced from XTAL, PLL, RC_FAST, or FLASH_PLL by configuring soc_cpu_clk_src_t */ + // For RTC domain + SOC_MOD_CLK_RTC_FAST, /*!< RTC_FAST_CLK can be sourced from XTAL_D2, RC_FAST, or LP_PLL by configuring soc_rtc_fast_clk_src_t */ + SOC_MOD_CLK_RTC_SLOW, /*!< RTC_SLOW_CLK can be sourced from RC_SLOW, XTAL32K, OSC_SLOW, or RC32K by configuring soc_rtc_slow_clk_src_t */ + // For digital domain: peripherals, WIFI, BLE + SOC_MOD_CLK_PLL_F48M, /*!< PLL_F48M_CLK is derived from PLL (clock gating + fixed divider of 2), it has a fixed frequency of 48MHz */ + SOC_MOD_CLK_PLL_F64M, /*!< PLL_F64M_CLK is derived from FLASH_PLL (clock gating), it has a fixed frequency of 64MHz */ + SOC_MOD_CLK_PLL_F96M, /*!< PLL_F96M_CLK is derived from PLL (clock gating), it has a fixed frequency of 96MHz */ + SOC_MOD_CLK_XTAL32K, /*!< XTAL32K_CLK comes from the external 32kHz crystal, passing a clock gating to the peripherals */ + SOC_MOD_CLK_RC_FAST, /*!< RC_FAST_CLK comes from the internal 8MHz rc oscillator, passing a clock gating to the peripherals */ + SOC_MOD_CLK_XTAL, /*!< XTAL_CLK comes from the external 32MHz crystal */ + SOC_MOD_CLK_INVALID, /*!< Indication of the end of the available module clock sources */ +} soc_module_clk_t; + +//////////////////////////////////////////////////SYSTIMER/////////////////////////////////////////////////////////////// + +/** + * @brief Type of SYSTIMER clock source + */ +typedef enum { + SYSTIMER_CLK_SRC_XTAL = SOC_MOD_CLK_XTAL, /*!< SYSTIMER source clock is XTAL */ + SYSTIMER_CLK_SRC_RC_FAST = SOC_MOD_CLK_RC_FAST, /*!< SYSTIMER source clock is RC_FAST */ + SYSTIMER_CLK_SRC_DEFAULT = SOC_MOD_CLK_XTAL, /*!< SYSTIMER source clock default choice is XTAL */ +} soc_periph_systimer_clk_src_t; + +//////////////////////////////////////////////////GPTimer/////////////////////////////////////////////////////////////// + +/** + * @brief Array initializer for all supported clock sources of GPTimer + * + * The following code can be used to iterate all possible clocks: + * @code{c} + * soc_periph_gptimer_clk_src_t gptimer_clks[] = (soc_periph_gptimer_clk_src_t)SOC_GPTIMER_CLKS; + * for (size_t i = 0; i< sizeof(gptimer_clks) / sizeof(gptimer_clks[0]); i++) { + * soc_periph_gptimer_clk_src_t clk = gptimer_clks[i]; + * // Test GPTimer with the clock `clk` + * } + * @endcode + */ +#define SOC_GPTIMER_CLKS {SOC_MOD_CLK_PLL_F48M, SOC_MOD_CLK_RC_FAST, SOC_MOD_CLK_XTAL} + +/** + * @brief Type of GPTimer clock source + */ +typedef enum { + GPTIMER_CLK_SRC_PLL_F48M = SOC_MOD_CLK_PLL_F48M, /*!< Select PLL_F48M as the source clock */ + GPTIMER_CLK_SRC_RC_FAST = SOC_MOD_CLK_RC_FAST, /*!< Select RC_FAST as the source clock */ + GPTIMER_CLK_SRC_XTAL = SOC_MOD_CLK_XTAL, /*!< Select XTAL as the source clock */ + GPTIMER_CLK_SRC_DEFAULT = SOC_MOD_CLK_PLL_F48M, /*!< Select PLL_F48M as the default choice */ +} soc_periph_gptimer_clk_src_t; + +/** + * @brief Type of Timer Group clock source, reserved for the legacy timer group driver + */ +typedef enum { + TIMER_SRC_CLK_PLL_F48M = SOC_MOD_CLK_PLL_F48M, /*!< Timer group clock source is PLL_F48M */ + TIMER_SRC_CLK_XTAL = SOC_MOD_CLK_XTAL, /*!< Timer group clock source is XTAL */ + TIMER_SRC_CLK_DEFAULT = SOC_MOD_CLK_PLL_F48M, /*!< Timer group clock source default choice is PLL_F48M */ +} soc_periph_tg_clk_src_legacy_t; + +///////////////////////////////////////////////////UART///////////////////////////////////////////////////////////////// + +/** + * @brief Array initializer for all supported clock sources of UART + */ +#define SOC_UART_CLKS {SOC_MOD_CLK_PLL_F48M, SOC_MOD_CLK_XTAL, SOC_MOD_CLK_RC_FAST} + +/** + * @brief Type of UART clock source, reserved for the legacy UART driver + */ +typedef enum { + UART_SCLK_PLL_F48M = SOC_MOD_CLK_PLL_F48M, /*!< UART source clock is PLL_F48M */ + UART_SCLK_RTC = SOC_MOD_CLK_RC_FAST, /*!< UART source clock is RC_FAST */ + UART_SCLK_XTAL = SOC_MOD_CLK_XTAL, /*!< UART source clock is XTAL */ + UART_SCLK_DEFAULT = SOC_MOD_CLK_PLL_F48M, /*!< UART source clock default choice is PLL_F48M */ +} soc_periph_uart_clk_src_legacy_t; + +/////////////////////////////////////////////////SPI//////////////////////////////////////////////////////////////////// + +/** + * @brief Array initializer for all supported clock sources of SPI + */ +#define SOC_SPI_CLKS {SOC_MOD_CLK_XTAL, SOC_MOD_CLK_RC_FAST, SOC_MOD_CLK_PLL_F48M} + +/** + * @brief Type of SPI clock source. + */ +typedef enum { + SPI_CLK_SRC_DEFAULT = SOC_MOD_CLK_PLL_F48M, /*!< Select PLL_48M as SPI source clock */ + SPI_CLK_SRC_PLL_F48M = SOC_MOD_CLK_PLL_F48M, /*!< Select PLL_48M as SPI source clock */ + SPI_CLK_SRC_XTAL = SOC_MOD_CLK_XTAL, /*!< Select XTAL as SPI source clock */ + SPI_CLK_SRC_RC_FAST = SOC_MOD_CLK_RC_FAST, /*!< Select RC_FAST as SPI source clock */ +} soc_periph_spi_clk_src_t; + +//////////////////////////////////////////////////MWDT///////////////////////////////////////////////////////////////// + +/** + * @brief Array initializer for all supported clock sources of MWDT + */ +#define SOC_MWDT_CLKS {SOC_MOD_CLK_XTAL, SOC_MOD_CLK_PLL_F48M, SOC_MOD_CLK_RC_FAST} + +/** + * @brief MWDT clock source + */ +typedef enum { + MWDT_CLK_SRC_XTAL = SOC_MOD_CLK_XTAL, /*!< Select XTAL as the source clock */ + MWDT_CLK_SRC_PLL_F48M = SOC_MOD_CLK_PLL_F48M, /*!< Select PLL fixed 48 MHz as the source clock */ + MWDT_CLK_SRC_RC_FAST = SOC_MOD_CLK_RC_FAST, /*!< Select RTC fast as the source clock */ + MWDT_CLK_SRC_DEFAULT = SOC_MOD_CLK_XTAL, /*!< Select PLL as the default clock choice */ +} soc_periph_mwdt_clk_src_t; + +//////////////////////////////////////////////////MSPI/////////////////////////////////////////////////////////////////// +/** + * @brief Array initializer for all supported clock sources of MSPI digital controller + */ +#define SOC_MSPI_CLKS {SOC_MOD_CLK_XTAL, SOC_MOD_CLK_RC_FAST, SOC_MOD_CLK_PLL_F64M, SOC_MOD_CLK_PLL_F48M} +/** + * @brief MSPI digital controller clock source + */ +typedef enum { + MSPI_CLK_SRC_XTAL = SOC_MOD_CLK_XTAL, /*!< Select XTAL as the source clock */ + MSPI_CLK_SRC_RC_FAST = SOC_MOD_CLK_RC_FAST, /*!< Select RC_FAST as the source clock */ + MSPI_CLK_SRC_PLL_F64M = SOC_MOD_CLK_PLL_F64M, /*!< Select PLL_F64M as the source clock */ + MSPI_CLK_SRC_PLL_F48M = SOC_MOD_CLK_PLL_F48M, /*!< Select PLL_F48M as the source clock */ + MSPI_CLK_SRC_DEFAULT = SOC_MOD_CLK_PLL_F64M, /*!< Select PLL_F64M as the default clock choice */ + MSPI_CLK_SRC_ROM_DEFAULT = SOC_MOD_CLK_XTAL, /*!< Select XTAL as ROM default clock source */ +} soc_periph_mspi_clk_src_t; + +//////////////////////////////////////////////CLOCK OUTPUT/////////////////////////////////////////////////////////// +typedef enum { + CLKOUT_SIG_XTAL = 5, /*!< Main crystal oscillator clock */ + CLKOUT_SIG_CPU = 16, /*!< CPU clock */ + CLKOUT_SIG_AHB = 17, /*!< AHB clock */ + CLKOUT_SIG_APB = 18, /*!< APB clock */ + CLKOUT_SIG_XTAL32K = 21, /*!< External 32kHz crystal clock */ + CLKOUT_SIG_EXT32K = 22, /*!< External slow clock input through XTAL_32K_P */ + CLKOUT_SIG_RC_FAST = 23, /*!< RC fast clock, about 17.5MHz */ + CLKOUT_SIG_RC_32K = 24, /*!< Internal slow RC oscillator */ + CLKOUT_SIG_RC_SLOW = 25, /*!< RC slow clock, depends on the RTC_CLK_SRC configuration */ + CLKOUT_SIG_INVALID = 0xFF, +} soc_clkout_sig_id_t; + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32h21/include/soc/dport_access.h b/components/soc/esp32h21/include/soc/dport_access.h new file mode 100644 index 00000000000..72eb538c6b0 --- /dev/null +++ b/components/soc/esp32h21/include/soc/dport_access.h @@ -0,0 +1,108 @@ +/* + * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#pragma once + +#include +#include "soc/soc.h" + +#ifdef __cplusplus +extern "C" { +#endif + +// Target does not have DPORT bus, so these macros are all same as the non-DPORT versions + +#define DPORT_INTERRUPT_DISABLE() +#define DPORT_INTERRUPT_RESTORE() + +/** + * @brief Read a sequence of DPORT registers to the buffer. + * + * @param[out] buff_out Contains the read data. + * @param[in] address Initial address for reading registers. + * @param[in] num_words The number of words. + */ +void esp_dport_access_read_buffer(uint32_t *buff_out, uint32_t address, uint32_t num_words); + +// _DPORT_REG_WRITE & DPORT_REG_WRITE are equivalent. +#define _DPORT_REG_READ(_r) (*(volatile uint32_t *)(_r)) +#define _DPORT_REG_WRITE(_r, _v) (*(volatile uint32_t *)(_r)) = (_v) + +// Write value to DPORT register (does not require protecting) +#define DPORT_REG_WRITE(_r, _v) _DPORT_REG_WRITE((_r), (_v)) + +#define DPORT_REG_READ(_r) _DPORT_REG_READ(_r) +#define DPORT_SEQUENCE_REG_READ(_r) _DPORT_REG_READ(_r) + +//get bit or get bits from register +#define DPORT_REG_GET_BIT(_r, _b) (DPORT_REG_READ(_r) & (_b)) + +//set bit or set bits to register +#define DPORT_REG_SET_BIT(_r, _b) DPORT_REG_WRITE((_r), (DPORT_REG_READ(_r)|(_b))) + +//clear bit or clear bits of register +#define DPORT_REG_CLR_BIT(_r, _b) DPORT_REG_WRITE((_r), (DPORT_REG_READ(_r) & (~(_b)))) + +//set bits of register controlled by mask +#define DPORT_REG_SET_BITS(_r, _b, _m) DPORT_REG_WRITE((_r), ((DPORT_REG_READ(_r) & (~(_m))) | ((_b) & (_m)))) + +//get field from register, uses field _S & _V to determine mask +#define DPORT_REG_GET_FIELD(_r, _f) ((DPORT_REG_READ(_r) >> (_f##_S)) & (_f##_V)) + +//set field to register, used when _f is not left shifted by _f##_S +#define DPORT_REG_SET_FIELD(_r, _f, _v) DPORT_REG_WRITE((_r), ((DPORT_REG_READ(_r) & (~((_f##_V) << (_f##_S))))|(((_v) & (_f##_V))<<(_f##_S)))) + +//get field value from a variable, used when _f is not left shifted by _f##_S +#define DPORT_VALUE_GET_FIELD(_r, _f) (((_r) >> (_f##_S)) & (_f)) + +//get field value from a variable, used when _f is left shifted by _f##_S +#define DPORT_VALUE_GET_FIELD2(_r, _f) (((_r) & (_f))>> (_f##_S)) + +//set field value to a variable, used when _f is not left shifted by _f##_S +#define DPORT_VALUE_SET_FIELD(_r, _f, _v) ((_r)=(((_r) & ~((_f) << (_f##_S)))|((_v)<<(_f##_S)))) + +//set field value to a variable, used when _f is left shifted by _f##_S +#define DPORT_VALUE_SET_FIELD2(_r, _f, _v) ((_r)=(((_r) & ~(_f))|((_v)<<(_f##_S)))) + +//generate a value from a field value, used when _f is not left shifted by _f##_S +#define DPORT_FIELD_TO_VALUE(_f, _v) (((_v)&(_f))<<_f##_S) + +//generate a value from a field value, used when _f is left shifted by _f##_S +#define DPORT_FIELD_TO_VALUE2(_f, _v) (((_v)<<_f##_S) & (_f)) + +//Register read macros with an underscore prefix access DPORT memory directly. In IDF apps, use the non-underscore versions to be SMP-safe. +#define _DPORT_READ_PERI_REG(addr) (*((volatile uint32_t *)(addr))) +#define _DPORT_WRITE_PERI_REG(addr, val) (*((volatile uint32_t *)(addr))) = (uint32_t)(val) +#define _DPORT_REG_SET_BIT(_r, _b) _DPORT_REG_WRITE((_r), (_DPORT_REG_READ(_r)|(_b))) +#define _DPORT_REG_CLR_BIT(_r, _b) _DPORT_REG_WRITE((_r), (_DPORT_REG_READ(_r) & (~(_b)))) + +#define DPORT_READ_PERI_REG(addr) _DPORT_READ_PERI_REG(addr) + +//write value to register +#define DPORT_WRITE_PERI_REG(addr, val) _DPORT_WRITE_PERI_REG((addr), (val)) + +//clear bits of register controlled by mask +#define DPORT_CLEAR_PERI_REG_MASK(reg, mask) DPORT_WRITE_PERI_REG((reg), (DPORT_READ_PERI_REG(reg)&(~(mask)))) + +//set bits of register controlled by mask +#define DPORT_SET_PERI_REG_MASK(reg, mask) DPORT_WRITE_PERI_REG((reg), (DPORT_READ_PERI_REG(reg)|(mask))) + +//get bits of register controlled by mask +#define DPORT_GET_PERI_REG_MASK(reg, mask) (DPORT_READ_PERI_REG(reg) & (mask)) + +//get bits of register controlled by highest bit and lowest bit +#define DPORT_GET_PERI_REG_BITS(reg, hipos,lowpos) ((DPORT_READ_PERI_REG(reg)>>(lowpos))&((1<<((hipos)-(lowpos)+1))-1)) + +//set bits of register controlled by mask and shift +#define DPORT_SET_PERI_REG_BITS(reg,bit_map,value,shift) DPORT_WRITE_PERI_REG((reg), ((DPORT_READ_PERI_REG(reg)&(~((bit_map)<<(shift))))|(((value) & bit_map)<<(shift)))) + +//get field of register +#define DPORT_GET_PERI_REG_BITS2(reg, mask,shift) ((DPORT_READ_PERI_REG(reg)>>(shift))&(mask)) +//}} + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32h21/include/soc/efuse_defs.h b/components/soc/esp32h21/include/soc/efuse_defs.h new file mode 100644 index 00000000000..48cc4ce65d9 --- /dev/null +++ b/components/soc/esp32h21/include/soc/efuse_defs.h @@ -0,0 +1,17 @@ +/** + * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#ifdef __cplusplus +extern "C" { +#endif + +#define EFUSE_WRITE_OP_CODE 0x5a5a +#define EFUSE_READ_OP_CODE 0x5aa5 + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32h21/include/soc/ext_mem_defs.h b/components/soc/esp32h21/include/soc/ext_mem_defs.h new file mode 100644 index 00000000000..1d4f57afbdb --- /dev/null +++ b/components/soc/esp32h21/include/soc/ext_mem_defs.h @@ -0,0 +1,131 @@ +/* + * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include "esp_bit_defs.h" + +#ifdef __cplusplus +extern "C" { +#endif + +#if !SOC_MMU_PAGE_SIZE +/** + * We define `SOC_MMU_PAGE_SIZE` in soc/CMakeLists.txt. + * Here we give a default definition, if SOC_MMU_PAGE_SIZE doesn't exist. This is to pass the check_public_headers.py + */ +#define SOC_MMU_PAGE_SIZE 0x10000 +#endif + +#define SOC_IRAM0_CACHE_ADDRESS_LOW 0x42000000 +#define SOC_IRAM0_CACHE_ADDRESS_HIGH (SOC_IRAM0_CACHE_ADDRESS_LOW + ((SOC_MMU_PAGE_SIZE) * SOC_MMU_ENTRY_NUM)) + +#define SOC_DRAM0_CACHE_ADDRESS_LOW SOC_IRAM0_CACHE_ADDRESS_LOW //I/D share the same vaddr range +#define SOC_DRAM0_CACHE_ADDRESS_HIGH SOC_IRAM0_CACHE_ADDRESS_HIGH //I/D share the same vaddr range + +#define SOC_IRAM_FLASH_ADDRESS_LOW SOC_IRAM0_CACHE_ADDRESS_LOW +#define SOC_IRAM_FLASH_ADDRESS_HIGH SOC_IRAM0_CACHE_ADDRESS_HIGH + +#define SOC_DRAM_FLASH_ADDRESS_LOW SOC_DRAM0_CACHE_ADDRESS_LOW +#define SOC_DRAM_FLASH_ADDRESS_HIGH SOC_DRAM0_CACHE_ADDRESS_HIGH + +#define SOC_BUS_SIZE(bus_name) (bus_name##_ADDRESS_HIGH - bus_name##_ADDRESS_LOW) +#define SOC_ADDRESS_IN_BUS(bus_name, vaddr) ((vaddr) >= bus_name##_ADDRESS_LOW && (vaddr) < bus_name##_ADDRESS_HIGH) + +#define SOC_ADDRESS_IN_IRAM0(vaddr) SOC_ADDRESS_IN_BUS(SOC_IRAM0, vaddr) +#define SOC_ADDRESS_IN_IRAM0_CACHE(vaddr) SOC_ADDRESS_IN_BUS(SOC_IRAM0_CACHE, vaddr) +#define SOC_ADDRESS_IN_DRAM0(vaddr) SOC_ADDRESS_IN_BUS(SOC_DRAM0, vaddr) +#define SOC_ADDRESS_IN_DRAM0_CACHE(vaddr) SOC_ADDRESS_IN_BUS(SOC_DRAM0_CACHE, vaddr) + +#define SOC_MMU_ACCESS_FLASH 0 +#define SOC_MMU_VALID BIT(9) +#define SOC_MMU_SENSITIVE BIT(10) +#define SOC_MMU_INVALID_MASK BIT(9) +#define SOC_MMU_INVALID 0 + +/** + * MMU entry valid bit mask for mapping value. For an entry: + * valid bit + value bits + * valid bit is BIT(9), so value bits are 0x1ff + */ +#define SOC_MMU_VALID_VAL_MASK 0x1ff +/** + * Max MMU available paddr page num. + * `SOC_MMU_MAX_PADDR_PAGE_NUM * SOC_MMU_PAGE_SIZE` means the max paddr address supported by the MMU. e.g.: + * 256 * 64KB, means MMU can support 16MB paddr at most + */ +#define SOC_MMU_MAX_PADDR_PAGE_NUM 256 +//MMU entry num +#define SOC_MMU_ENTRY_NUM 256 + +/** + * This is the mask used for mapping. e.g.: + * 0x4200_0000 & SOC_MMU_VADDR_MASK + */ +#define SOC_MMU_VADDR_MASK ((SOC_MMU_PAGE_SIZE) * SOC_MMU_ENTRY_NUM - 1) + +#define SOC_MMU_DBUS_VADDR_BASE 0x42000000 +#define SOC_MMU_IBUS_VADDR_BASE 0x42000000 + +/*------------------------------------------------------------------------------ + * MMU Linear Address + *----------------------------------------------------------------------------*/ +#if (SOC_MMU_PAGE_SIZE == 0x10000) +/** + * - 64KB MMU page size: the last 0xFFFF, which is the offset + * - 128 MMU entries, needs 0x7F to hold it. + * + * Therefore, 0x7F,FFFF + */ +#define SOC_MMU_LINEAR_ADDR_MASK 0x7FFFFF + +#elif (SOC_MMU_PAGE_SIZE == 0x8000) +/** + * - 32KB MMU page size: the last 0x7FFF, which is the offset + * - 128 MMU entries, needs 0x7F to hold it. + * + * Therefore, 0x3F,FFFF + */ +#define SOC_MMU_LINEAR_ADDR_MASK 0x3FFFFF + +#elif (SOC_MMU_PAGE_SIZE == 0x4000) +/** + * - 16KB MMU page size: the last 0x3FFF, which is the offset + * - 128 MMU entries, needs 0x7F to hold it. + * + * Therefore, 0x1F,FFFF + */ +#define SOC_MMU_LINEAR_ADDR_MASK 0x1FFFFF +#endif //SOC_MMU_PAGE_SIZE + +/** + * - If high linear address isn't 0, this means MMU can recognize these addresses + * - If high linear address is 0, this means MMU linear address range is equal or smaller than vaddr range. + * Under this condition, we use the max linear space. + */ +#define SOC_MMU_IRAM0_LINEAR_ADDRESS_LOW (SOC_IRAM0_CACHE_ADDRESS_LOW & SOC_MMU_LINEAR_ADDR_MASK) +#if ((SOC_IRAM0_CACHE_ADDRESS_HIGH & SOC_MMU_LINEAR_ADDR_MASK) > 0) +#define SOC_MMU_IRAM0_LINEAR_ADDRESS_HIGH (SOC_IRAM0_CACHE_ADDRESS_HIGH & SOC_MMU_LINEAR_ADDR_MASK) +#else +#define SOC_MMU_IRAM0_LINEAR_ADDRESS_HIGH (SOC_MMU_LINEAR_ADDR_MASK + 1) +#endif + +#define SOC_MMU_DRAM0_LINEAR_ADDRESS_LOW (SOC_DRAM0_CACHE_ADDRESS_LOW & SOC_MMU_LINEAR_ADDR_MASK) +#if ((SOC_DRAM0_CACHE_ADDRESS_HIGH & SOC_MMU_LINEAR_ADDR_MASK) > 0) +#define SOC_MMU_DRAM0_LINEAR_ADDRESS_HIGH (SOC_DRAM0_CACHE_ADDRESS_HIGH & SOC_MMU_LINEAR_ADDR_MASK) +#else +#define SOC_MMU_DRAM0_LINEAR_ADDRESS_HIGH (SOC_MMU_LINEAR_ADDR_MASK + 1) +#endif + +/** + * I/D share the MMU linear address range + */ +#ifndef __cplusplus +_Static_assert(SOC_MMU_IRAM0_LINEAR_ADDRESS_LOW == SOC_MMU_DRAM0_LINEAR_ADDRESS_LOW, "IRAM0 and DRAM0 linear address should be same"); +#endif + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32h21/include/soc/gpio_num.h b/components/soc/esp32h21/include/soc/gpio_num.h new file mode 100644 index 00000000000..68f53c62146 --- /dev/null +++ b/components/soc/esp32h21/include/soc/gpio_num.h @@ -0,0 +1,51 @@ +/* + * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#pragma once + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @brief GPIO number + */ +typedef enum { + GPIO_NUM_NC = -1, /*!< Use to signal not connected to S/W */ + GPIO_NUM_0 = 0, /*!< GPIO0, input and output */ + GPIO_NUM_1 = 1, /*!< GPIO1, input and output */ + GPIO_NUM_2 = 2, /*!< GPIO2, input and output */ + GPIO_NUM_3 = 3, /*!< GPIO3, input and output */ + GPIO_NUM_4 = 4, /*!< GPIO4, input and output */ + GPIO_NUM_5 = 5, /*!< GPIO5, input and output */ + GPIO_NUM_6 = 6, /*!< GPIO6, input and output */ + GPIO_NUM_7 = 7, /*!< GPIO7, input and output */ + GPIO_NUM_8 = 8, /*!< GPIO8, input and output */ + GPIO_NUM_9 = 9, /*!< GPIO9, input and output */ + GPIO_NUM_10 = 10, /*!< GPIO10, input and output */ + GPIO_NUM_11 = 11, /*!< GPIO11, input and output */ + GPIO_NUM_12 = 12, /*!< GPIO12, input and output */ + GPIO_NUM_13 = 13, /*!< GPIO13, input and output */ + GPIO_NUM_14 = 14, /*!< GPIO14, input and output */ + GPIO_NUM_15 = 15, /*!< GPIO15, input and output */ + GPIO_NUM_16 = 16, /*!< GPIO16, input and output */ + GPIO_NUM_17 = 17, /*!< GPIO17, input and output */ + GPIO_NUM_18 = 18, /*!< GPIO18, input and output */ + GPIO_NUM_19 = 19, /*!< GPIO19, input and output */ + GPIO_NUM_20 = 20, /*!< GPIO20, input and output */ + GPIO_NUM_21 = 21, /*!< GPIO21, input and output */ + GPIO_NUM_22 = 22, /*!< GPIO22, input and output */ + GPIO_NUM_23 = 23, /*!< GPIO23, input and output */ + GPIO_NUM_24 = 24, /*!< GPIO24, input and output */ + GPIO_NUM_25 = 25, /*!< GPIO25, input and output */ + GPIO_NUM_26 = 26, /*!< GPIO26, input and output */ + GPIO_NUM_27 = 27, /*!< GPIO27, input and output */ + GPIO_NUM_MAX, +} gpio_num_t; + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32h21/include/soc/gpio_pins.h b/components/soc/esp32h21/include/soc/gpio_pins.h new file mode 100644 index 00000000000..69bbf244a7d --- /dev/null +++ b/components/soc/esp32h21/include/soc/gpio_pins.h @@ -0,0 +1,20 @@ +/* + * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#pragma once + +#ifdef __cplusplus +extern "C" { +#endif + +//TODO: [ESP32H21] IDF-11611 +#define GPIO_MATRIX_CONST_ONE_INPUT (0x20) +#define GPIO_MATRIX_CONST_ZERO_INPUT (0x30) +#define GPIO_MATRIX_INVALID (0x3A) + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32h21/include/soc/periph_defs.h b/components/soc/esp32h21/include/soc/periph_defs.h new file mode 100644 index 00000000000..9044603a064 --- /dev/null +++ b/components/soc/esp32h21/include/soc/periph_defs.h @@ -0,0 +1,67 @@ +/* + * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#pragma once + +#include "soc/interrupts.h" + +#ifdef __cplusplus +extern "C" { +#endif + +// TODO: IDF-11855 +typedef enum { + PERIPH_LEDC_MODULE = 0, + PERIPH_UART0_MODULE, + PERIPH_UART1_MODULE, + PERIPH_USB_DEVICE_MODULE, + PERIPH_I2C0_MODULE, + PERIPH_I2C1_MODULE, + PERIPH_I2S1_MODULE, + PERIPH_TIMG0_MODULE, + PERIPH_TIMG1_MODULE, + PERIPH_UHCI0_MODULE, + PERIPH_RMT_MODULE, + PERIPH_PCNT_MODULE, + PERIPH_SPI_MODULE, //SPI1 + PERIPH_SPI2_MODULE, //SPI2 + PERIPH_TWAI0_MODULE, + PERIPH_RNG_MODULE, + PERIPH_RSA_MODULE, + PERIPH_AES_MODULE, + PERIPH_SHA_MODULE, + PERIPH_ECC_MODULE, + PERIPH_HMAC_MODULE, + PERIPH_DS_MODULE, + PERIPH_ECDSA_MODULE, + PERIPH_GDMA_MODULE, + PERIPH_MCPWM0_MODULE, + PERIPH_ETM_MODULE, + PERIPH_PARLIO_MODULE, + PERIPH_SYSTIMER_MODULE, + PERIPH_SARADC_MODULE, + PERIPH_TEMPSENSOR_MODULE, + PERIPH_ASSIST_DEBUG_MODULE, + /* Peripherals clock managed by the modem_clock driver must be listed last in the enumeration */ + PERIPH_BT_MODULE, + PERIPH_IEEE802154_MODULE, + PERIPH_COEX_MODULE, + PERIPH_PHY_MODULE, + PERIPH_ANA_I2C_MASTER_MODULE, + PERIPH_MODEM_ETM_MODULE, + PERIPH_MODEM_ADC_COMMON_FE_MODULE, + PERIPH_MODULE_MAX + /* !!! Don't append soc modules here !!! */ +} periph_module_t; + +#define PERIPH_MODEM_MODULE_MIN PERIPH_BT_MODULE +#define PERIPH_MODEM_MODULE_MAX PERIPH_MODEM_ADC_COMMON_FE_MODULE +#define PERIPH_MODEM_MODULE_NUM (PERIPH_MODEM_MODULE_MAX - PERIPH_MODEM_MODULE_MIN + 1) +#define IS_MODEM_MODULE(periph) ((periph>=PERIPH_MODEM_MODULE_MIN) && (periph<=PERIPH_MODEM_MODULE_MAX)) + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32h21/include/soc/regi2c_bbpll.h b/components/soc/esp32h21/include/soc/regi2c_bbpll.h new file mode 100644 index 00000000000..04b76a40e21 --- /dev/null +++ b/components/soc/esp32h21/include/soc/regi2c_bbpll.h @@ -0,0 +1,35 @@ +/* + * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#pragma once + +/** + * @file regi2c_bbpll.h + * @brief Register definitions for digital PLL (BBPLL) + * + * This file lists register fields of BBPLL, located on an internal configuration + * bus. These definitions are used via macros defined in regi2c_ctrl.h, by + * rtc_clk_cpu_freq_set function in rtc_clk.c. + */ + +#define I2C_BBPLL 0x66 +#define I2C_BBPLL_HOSTID 0 + +#define I2C_BBPLL_OC_REF_DIV 2 +#define I2C_BBPLL_OC_REF_DIV_MSB 3 +#define I2C_BBPLL_OC_REF_DIV_LSB 0 + +#define I2C_BBPLL_OC_DIV 3 +#define I2C_BBPLL_OC_DIV_MSB 5 +#define I2C_BBPLL_OC_DIV_LSB 0 + +#define I2C_BBPLL_OC_DHREF_SEL 5 +#define I2C_BBPLL_OC_DHREF_SEL_MSB 5 +#define I2C_BBPLL_OC_DHREF_SEL_LSB 4 + +#define I2C_BBPLL_OC_DLREF_SEL 5 +#define I2C_BBPLL_OC_DLREF_SEL_MSB 7 +#define I2C_BBPLL_OC_DLREF_SEL_LSB 6 diff --git a/components/soc/esp32h21/include/soc/regi2c_bias.h b/components/soc/esp32h21/include/soc/regi2c_bias.h new file mode 100644 index 00000000000..64ed52017bf --- /dev/null +++ b/components/soc/esp32h21/include/soc/regi2c_bias.h @@ -0,0 +1,26 @@ +/* + * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#pragma once + +/** + * @file regi2c_bias.h + * @brief Register definitions for bias + * + * This file lists register fields of BIAS. These definitions are used via macros defined in regi2c_ctrl.h, by + * bootloader_hardware_init function in bootloader_esp32h21.c. + */ + +#define I2C_BIAS 0X6A +#define I2C_BIAS_HOSTID 0 + +#define I2C_BIAS_DREG_0P8 0 +#define I2C_BIAS_DREG_0P8_MSB 7 +#define I2C_BIAS_DREG_0P8_LSB 4 + +#define I2C_BIAS_DREG_1P1_PVT 1 +#define I2C_BIAS_DREG_1P1_PVT_MSB 3 +#define I2C_BIAS_DREG_1P1_PVT_LSB 0 diff --git a/components/soc/esp32h21/include/soc/regi2c_defs.h b/components/soc/esp32h21/include/soc/regi2c_defs.h new file mode 100644 index 00000000000..d00fd070b45 --- /dev/null +++ b/components/soc/esp32h21/include/soc/regi2c_defs.h @@ -0,0 +1,34 @@ +/* + * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#pragma once + +#include "esp_bit_defs.h" + +/* Analog function control register */ +// I2C_MST_ANA_CONF0_REG +#define I2C_MST_BBPLL_STOP_FORCE_HIGH (BIT(2)) +#define I2C_MST_BBPLL_STOP_FORCE_LOW (BIT(3)) +#define I2C_MST_BBPLL_CAL_DONE (BIT(24)) + +// I2C_MST_ANA_CONF1_REG +#define ANA_CONFIG_S (8) +#define ANA_CONFIG_M (0x3FF) + +#define ANA_I2C_SAR_FORCE_PD BIT(18) +#define ANA_I2C_BBPLL_M BIT(17) /* Clear to enable BBPLL */ + +// I2C_MST_ANA_CONF2_REG +#define ANA_CONFIG2_M BIT(18) + +#define ANA_I2C_SAR_FORCE_PU BIT(16) + +/** + * Restore regi2c analog calibration related configuration registers. + * This is a workaround for calibration error when waking up from light sleep + */ +#define REGI2C_ANA_CALI_PD_WORKAROUND 1 +#define REGI2C_ANA_CALI_BYTE_NUM 8 diff --git a/components/soc/esp32h21/include/soc/regi2c_lp_bias.h b/components/soc/esp32h21/include/soc/regi2c_lp_bias.h new file mode 100644 index 00000000000..dea8e75263d --- /dev/null +++ b/components/soc/esp32h21/include/soc/regi2c_lp_bias.h @@ -0,0 +1,23 @@ +/* + * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#pragma once + +/** + * @file regi2c_lp_bias.h + * @brief Register definitions for analog to calibrate o_code for getting a more precise voltage. + * + * This file lists register fields of low power dbais, located on an internal configuration + * bus. These definitions are used via macros defined in regi2c_ctrl.h, by + * rtc_init function in rtc_init.c. + */ + +#define I2C_ULP 0x61 +#define I2C_ULP_HOSTID 0 + +#define I2C_ULP_IR_RESETB 0 +#define I2C_ULP_IR_RESETB_MSB 0 +#define I2C_ULP_IR_RESETB_LSB 0 diff --git a/components/soc/esp32h21/include/soc/regi2c_pmu.h b/components/soc/esp32h21/include/soc/regi2c_pmu.h new file mode 100644 index 00000000000..d6fabdb26e3 --- /dev/null +++ b/components/soc/esp32h21/include/soc/regi2c_pmu.h @@ -0,0 +1,52 @@ +/* + * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#pragma once + +/** + * @file regi2c_pmu.h + * @brief Register definitions for digital to get rtc voltage & digital voltage + * by setting rtc_dbias_Wak & dig_dbias_wak or by analog self-calibration. + */ + +#define I2C_PMU 0x6d +#define I2C_PMU_HOSTID 0 + +#define I2C_PMU_EN_I2C_RTC_DREG 8 +#define I2C_PMU_EN_I2C_RTC_DREG_MSB 0 +#define I2C_PMU_EN_I2C_RTC_DREG_LSB 0 + +#define I2C_PMU_EN_I2C_DIG_DREG 8 +#define I2C_PMU_EN_I2C_DIG_DREG_MSB 1 +#define I2C_PMU_EN_I2C_DIG_DREG_LSB 1 + +#define I2C_PMU_EN_I2C_RTC_DREG_SLP 8 +#define I2C_PMU_EN_I2C_RTC_DREG_SLP_MSB 2 +#define I2C_PMU_EN_I2C_RTC_DREG_SLP_LSB 2 + +#define I2C_PMU_EN_I2C_DIG_DREG_SLP 8 +#define I2C_PMU_EN_I2C_DIG_DREG_SLP_MSB 3 +#define I2C_PMU_EN_I2C_DIG_DREG_SLP_LSB 3 + +#define I2C_PMU_OR_XPD_RTC_REG 9 +#define I2C_PMU_OR_XPD_RTC_REG_MSB 4 +#define I2C_PMU_OR_XPD_RTC_REG_LSB 4 + +#define I2C_PMU_OR_XPD_DIG_REG 9 +#define I2C_PMU_OR_XPD_DIG_REG_MSB 5 +#define I2C_PMU_OR_XPD_DIG_REG_LSB 5 + +#define I2C_PMU_OC_SCK_DCAP 14 +#define I2C_PMU_OC_SCK_DCAP_MSB 7 +#define I2C_PMU_OC_SCK_DCAP_LSB 0 + +#define I2C_PMU_OR_XPD_TRX 15 +#define I2C_PMU_OR_XPD_TRX_MSB 2 +#define I2C_PMU_OR_XPD_TRX_LSB 2 + +#define I2C_PMU_SEL_PLL8M_REF 21 +#define I2C_PMU_SEL_PLL8M_REF_MSB 6 +#define I2C_PMU_SEL_PLL8M_REF_LSB 6 diff --git a/components/soc/esp32h21/include/soc/regi2c_saradc.h b/components/soc/esp32h21/include/soc/regi2c_saradc.h new file mode 100644 index 00000000000..ad40af74ae3 --- /dev/null +++ b/components/soc/esp32h21/include/soc/regi2c_saradc.h @@ -0,0 +1,19 @@ +/* + * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#pragma once + +/** + * @file regi2c_saradc.h + * @brief Register definitions for analog to calibrate initial code for getting a more precise voltage of SAR ADC. + * + * This file lists register fields of SAR, located on an internal configuration + * bus. These definitions are used via macros defined in regi2c_ctrl.h, by + * function in adc_ll.h. + */ + +#define I2C_SAR_ADC 0X69 +#define I2C_SAR_ADC_HOSTID 0 diff --git a/components/soc/esp32h21/include/soc/reset_reasons.h b/components/soc/esp32h21/include/soc/reset_reasons.h new file mode 100644 index 00000000000..039f95ba42d --- /dev/null +++ b/components/soc/esp32h21/include/soc/reset_reasons.h @@ -0,0 +1,53 @@ +/* + * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#pragma once + +//+-----------------------------------------------Terminology---------------------------------------------+ +//| | +//| CPU Reset: Reset CPU core only, once reset done, CPU will execute from reset vector | +//| | +//| Core Reset: Reset the whole digital system except RTC sub-system | +//| | +//| System Reset: Reset the whole digital system, including RTC sub-system | +//| | +//| Chip Reset: Reset the whole chip, including the analog part | +//| | +//+-------------------------------------------------------------------------------------------------------+ + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @brief Naming conventions: RESET_REASON_{reset level}_{reset reason} + * @note refer to TRM: chapter + */ +typedef enum { + RESET_REASON_CHIP_POWER_ON = 0x01, // Power on reset + RESET_REASON_CHIP_BROWN_OUT = 0x01, // VDD voltage is not stable and resets the chip + RESET_REASON_CORE_SW = 0x03, // Software resets the digital core by RTC_CNTL_SW_SYS_RST + RESET_REASON_CORE_DEEP_SLEEP = 0x05, // Deep sleep reset the digital core + RESET_REASON_CORE_MWDT0 = 0x07, // Main watch dog 0 resets digital core + RESET_REASON_CORE_MWDT1 = 0x08, // Main watch dog 1 resets digital core + RESET_REASON_CORE_RTC_WDT = 0x09, // RTC watch dog resets digital core + RESET_REASON_CPU0_MWDT0 = 0x0B, // Main watch dog 0 resets CPU 0 + RESET_REASON_CPU0_SW = 0x0C, // Software resets CPU 0 by RTC_CNTL_SW_PROCPU_RST + RESET_REASON_CPU0_RTC_WDT = 0x0D, // RTC watch dog resets CPU 0 + RESET_REASON_SYS_BROWN_OUT = 0x0F, // VDD voltage is not stable and resets the digital core + RESET_REASON_SYS_RTC_WDT = 0x10, // RTC watch dog resets digital core and rtc module + RESET_REASON_CPU0_MWDT1 = 0x11, // Main watch dog 1 resets CPU 0 + RESET_REASON_SYS_SUPER_WDT = 0x12, // Super watch dog resets the digital core and rtc module + RESET_REASON_CORE_EFUSE_CRC = 0x14, // eFuse CRC error resets the digital core + RESET_REASON_CORE_USB_UART = 0x15, // USB UART resets the digital core + RESET_REASON_CORE_USB_JTAG = 0x16, // USB JTAG resets the digital core + RESET_REASON_CORE_PWR_GLITCH = 0x17, // Glitch on power resets the digital core + RESET_REASON_CPU0_JTAG = 0x18, // JTAG resets the CPU 0 +} soc_reset_reason_t; + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32h21/include/soc/soc.h b/components/soc/esp32h21/include/soc/soc.h new file mode 100644 index 00000000000..7befaf79a85 --- /dev/null +++ b/components/soc/esp32h21/include/soc/soc.h @@ -0,0 +1,237 @@ +/* + * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#pragma once + +#ifndef __ASSEMBLER__ +#include +#include "esp_assert.h" +#endif + +#include "esp_bit_defs.h" +#include "reg_base.h" + +#define PRO_CPU_NUM (0) + +// TODO: IDF-11856 +#define DR_REG_UHCI_BASE(i) (DR_REG_UHCI0_BASE - (i) * 0x8000) +#define DR_REG_UART_BASE(i) (DR_REG_UART_BASE + (i) * 0x1000) +#define DR_REG_UART_AHB_BASE(i) (0x60000000 + (i) * 0x10000) +#define DR_UART_FIFO_AHB_REG(i) (REG_UART_AHB_BASE(i) + 0x0) +#define DR_REG_I2S_BASE(i) (DR_REG_I2S_BASE) // only one I2S on H21 +#define DR_REG_TIMG_BASE(i) (DR_REG_TIMERGROUP0_BASE + (i)*0x1000) +#define DR_REG_SPI_MEM_BASE(i) (DR_REG_SPI0_BASE + (i) * 0x1000) +#define DR_REG_SPI_BASE(i) (((i)==2) ? (DR_REG_SPI2_BASE) : (0)) // only one GPSPI +#define DR_REG_I2C_BASE(i) (DR_REG_I2C_EXT0_BASE + (i) * 0x1000) + +//Registers Operation {{ +#define ETS_UNCACHED_ADDR(addr) (addr) +#define ETS_CACHED_ADDR(addr) (addr) + +#ifndef __ASSEMBLER__ + +//write value to register +#define REG_WRITE(_r, _v) do { \ + (*(volatile uint32_t *)(_r)) = (_v); \ + } while(0) + +//read value from register +#define REG_READ(_r) ({ \ + (*(volatile uint32_t *)(_r)); \ + }) + +//get bit or get bits from register +#define REG_GET_BIT(_r, _b) ({ \ + (*(volatile uint32_t*)(_r) & (_b)); \ + }) + +//set bit or set bits to register +#define REG_SET_BIT(_r, _b) do { \ + *(volatile uint32_t*)(_r) = (*(volatile uint32_t*)(_r)) | (_b); \ + } while(0) + +//clear bit or clear bits of register +#define REG_CLR_BIT(_r, _b) do { \ + *(volatile uint32_t*)(_r) = (*(volatile uint32_t*)(_r)) & (~(_b)); \ + } while(0) + +//set bits of register controlled by mask +#define REG_SET_BITS(_r, _b, _m) do { \ + *(volatile uint32_t*)(_r) = (*(volatile uint32_t*)(_r) & ~(_m)) | ((_b) & (_m)); \ + } while(0) + +//get field from register, uses field _S & _V to determine mask +#define REG_GET_FIELD(_r, _f) ({ \ + ((REG_READ(_r) >> (_f##_S)) & (_f##_V)); \ + }) + +//set field of a register from variable, uses field _S & _V to determine mask +#define REG_SET_FIELD(_r, _f, _v) do { \ + REG_WRITE((_r),((REG_READ(_r) & ~((_f##_V) << (_f##_S)))|(((_v) & (_f##_V))<<(_f##_S)))); \ + } while(0) + +//get field value from a variable, used when _f is not left shifted by _f##_S +#define VALUE_GET_FIELD(_r, _f) (((_r) >> (_f##_S)) & (_f)) + +//get field value from a variable, used when _f is left shifted by _f##_S +#define VALUE_GET_FIELD2(_r, _f) (((_r) & (_f))>> (_f##_S)) + +//set field value to a variable, used when _f is not left shifted by _f##_S +#define VALUE_SET_FIELD(_r, _f, _v) ((_r)=(((_r) & ~((_f) << (_f##_S)))|((_v)<<(_f##_S)))) + +//set field value to a variable, used when _f is left shifted by _f##_S +#define VALUE_SET_FIELD2(_r, _f, _v) ((_r)=(((_r) & ~(_f))|((_v)<<(_f##_S)))) + +//generate a value from a field value, used when _f is not left shifted by _f##_S +#define FIELD_TO_VALUE(_f, _v) (((_v)&(_f))<<_f##_S) + +//generate a value from a field value, used when _f is left shifted by _f##_S +#define FIELD_TO_VALUE2(_f, _v) (((_v)<<_f##_S) & (_f)) + +//read value from register +#define READ_PERI_REG(addr) ({ \ + (*((volatile uint32_t *)ETS_UNCACHED_ADDR(addr))); \ + }) + +//write value to register +#define WRITE_PERI_REG(addr, val) do { \ + (*((volatile uint32_t *)ETS_UNCACHED_ADDR(addr))) = (uint32_t)(val); \ + } while(0) + +//clear bits of register controlled by mask +#define CLEAR_PERI_REG_MASK(reg, mask) do { \ + WRITE_PERI_REG((reg), (READ_PERI_REG(reg)&(~(mask)))); \ + } while(0) + +//set bits of register controlled by mask +#define SET_PERI_REG_MASK(reg, mask) do { \ + WRITE_PERI_REG((reg), (READ_PERI_REG(reg)|(mask))); \ + } while(0) + +//get bits of register controlled by mask +#define GET_PERI_REG_MASK(reg, mask) ({ \ + (READ_PERI_REG(reg) & (mask)); \ + }) + +//get bits of register controlled by highest bit and lowest bit +#define GET_PERI_REG_BITS(reg, hipos,lowpos) ({ \ + ((READ_PERI_REG(reg)>>(lowpos))&((1<<((hipos)-(lowpos)+1))-1)); \ + }) + +//set bits of register controlled by mask and shift +#define SET_PERI_REG_BITS(reg,bit_map,value,shift) do { \ + WRITE_PERI_REG((reg),(READ_PERI_REG(reg)&(~((bit_map)<<(shift))))|(((value) & (bit_map))<<(shift)) ); \ + } while(0) + +//get field of register +#define GET_PERI_REG_BITS2(reg, mask,shift) ({ \ + ((READ_PERI_REG(reg)>>(shift))&(mask)); \ + }) + +#endif /* !__ASSEMBLER__ */ +//}} + +//Periheral Clock {{ +#define CPU_CLK_FREQ_MHZ_BTLD (64) // The cpu clock frequency (in MHz) to set at 2nd stage bootloader system clock configuration +#define APB_CLK_FREQ ( 32*1000000 ) +#define MODEM_REQUIRED_MIN_APB_CLK_FREQ ( 32*1000000 ) +#define REF_CLK_FREQ ( 1000000 ) +//}} + +/* Overall memory map */ +/* Note: We should not use MACROs similar in cache_memory.h + * those are defined during run-time. But the MACROs here + * should be defined statically! + */ + +#define SOC_IROM_LOW 0x42000000 +#define SOC_IROM_HIGH 0x43000000 +#define SOC_DROM_LOW SOC_IROM_LOW +#define SOC_DROM_HIGH SOC_IROM_HIGH +#define SOC_IROM_MASK_LOW 0x40000000 +#define SOC_IROM_MASK_HIGH 0x40020000 +#define SOC_DROM_MASK_LOW 0x40000000 +#define SOC_DROM_MASK_HIGH 0x40020000 +#define SOC_IRAM_LOW 0x40800000 +#define SOC_IRAM_HIGH 0x40850000 +#define SOC_DRAM_LOW 0x40800000 +#define SOC_DRAM_HIGH 0x40850000 +#define SOC_RTC_IRAM_LOW 0x50000000 // ESP32-H21 only has 16k LP memory +#define SOC_RTC_IRAM_HIGH 0x50001000 +#define SOC_RTC_DRAM_LOW 0x50000000 +#define SOC_RTC_DRAM_HIGH 0x50001000 +#define SOC_RTC_DATA_LOW 0x50000000 +#define SOC_RTC_DATA_HIGH 0x50001000 + +//First and last words of the D/IRAM region, for both the DRAM address as well as the IRAM alias. +#define SOC_DIRAM_IRAM_LOW 0x40800000 +#define SOC_DIRAM_IRAM_HIGH 0x40850000 +#define SOC_DIRAM_DRAM_LOW 0x40800000 +#define SOC_DIRAM_DRAM_HIGH 0x40850000 + +#define MAP_DRAM_TO_IRAM(addr) (addr) +#define MAP_IRAM_TO_DRAM(addr) (addr) + +// Region of memory accessible via DMA. See esp_ptr_dma_capable(). +#define SOC_DMA_LOW 0x40800000 +#define SOC_DMA_HIGH 0x40850000 + +// Region of RAM that is byte-accessible. See esp_ptr_byte_accessible(). +#define SOC_BYTE_ACCESSIBLE_LOW 0x40800000 +#define SOC_BYTE_ACCESSIBLE_HIGH 0x40850000 + +//Region of memory that is internal, as in on the same silicon die as the ESP32 CPUs +//(excluding RTC data region, that's checked separately.) See esp_ptr_internal(). +#define SOC_MEM_INTERNAL_LOW 0x40800000 +#define SOC_MEM_INTERNAL_HIGH 0x40850000 +#define SOC_MEM_INTERNAL_LOW1 0x40800000 +#define SOC_MEM_INTERNAL_HIGH1 0x40850000 + +#define SOC_MAX_CONTIGUOUS_RAM_SIZE (SOC_IRAM_HIGH - SOC_IRAM_LOW) ///< Largest span of contiguous memory (DRAM or IRAM) in the address space + +// Region of address space that holds peripherals +#define SOC_PERIPHERAL_LOW 0x60000000 +#define SOC_PERIPHERAL_HIGH 0x60100000 + +// CPU sub-system region, contains interrupt config registers +#define SOC_CPU_SUBSYSTEM_LOW 0x20000000 +#define SOC_CPU_SUBSYSTEM_HIGH 0x30000000 + +//TODO: [ESP32H21] IDF-11857 +// Start (highest address) of ROM boot stack, only relevant during early boot +#define SOC_ROM_STACK_START 0x4084f380 +#define SOC_ROM_STACK_SIZE 0x2000 + +//On RISC-V CPUs, the interrupt sources are all external interrupts, whose type, source and priority are configured by SW. +//There is no HW NMI conception. SW should controlled the masked levels through INT_THRESH_REG. + +//CPU0 Interrupt numbers used in components/riscv/vectors.S. Change it's logic if modifying +#define ETS_T1_WDT_INUM 24 +#define ETS_CACHEERR_INUM 25 +#define ETS_MEMPROT_ERR_INUM 26 +#define ETS_ASSIST_DEBUG_INUM 27 // Note: this interrupt can be combined with others (e.g., CACHEERR), as we can identify its trigger is activated + +//CPU0 Max valid interrupt number +#define ETS_MAX_INUM 31 + +//CPU0 Interrupt number used in ROM, should be cancelled in SDK +#define ETS_SLC_INUM 1 +#define ETS_UART0_INUM 5 +#define ETS_UART1_INUM 5 +#define ETS_SPI2_INUM 1 +//CPU0 Interrupt number used in ROM code only when module init function called, should pay attention here. +#define ETS_GPIO_INUM 4 + +//Other interrupt number should be managed by the user + +//Invalid interrupt for number interrupt matrix +#define ETS_INVALID_INUM 0 + +//Interrupt medium level, used for INT WDT for example +#define SOC_INTERRUPT_LEVEL_MEDIUM 4 + +// Interrupt number for the Interrupt watchdog +#define ETS_INT_WDT_INUM (ETS_T1_WDT_INUM) diff --git a/components/soc/esp32h21/include/soc/soc_caps.h b/components/soc/esp32h21/include/soc/soc_caps.h new file mode 100644 index 00000000000..320d7a2c4c3 --- /dev/null +++ b/components/soc/esp32h21/include/soc/soc_caps.h @@ -0,0 +1,557 @@ +/* + * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/* + * These defines are parsed and imported as kconfig variables via the script + * `tools/gen_soc_caps_kconfig/gen_soc_caps_kconfig.py` + * + * If this file is changed the script will automatically run the script + * and generate the kconfig variables as part of the pre-commit hooks. + * + * It can also be run manually. For more information, see `${IDF_PATH}/tools/gen_soc_caps_kconfig/README.md` + */ + +#pragma once + +/*-------------------------- COMMON CAPS ---------------------------------------*/ +// #define SOC_ADC_SUPPORTED 1 //TODO: [ESP32H21] IDF-11589, IDF-11592 +// #define SOC_ANA_CMPR_SUPPORTED 1 +// #define SOC_DEDICATED_GPIO_SUPPORTED 1 //TODO: [ESP32H21] IDF-11621 +#define SOC_UART_SUPPORTED 1 //TODO: [ESP32H21] IDF-11618 +// #define SOC_GDMA_SUPPORTED 1 //TODO: [ESP32H21] IDF-11603 +// #define SOC_AHB_GDMA_SUPPORTED 1 //TODO: [ESP32H21] IDF-11603 +// #define SOC_GPTIMER_SUPPORTED 1 //TODO: [ESP32H21] IDF-11594 +// #define SOC_BT_SUPPORTED 1 +// #define SOC_IEEE802154_SUPPORTED 1 +// #define SOC_IEEE802154_BLE_ONLY 1 +// #define SOC_ASYNC_MEMCPY_SUPPORTED 1 +// #define SOC_USB_SERIAL_JTAG_SUPPORTED 1 //TODO: [ESP32H21] IDF-11616 +// #define SOC_TEMP_SENSOR_SUPPORTED 1 //TODO: [ESP32H21] IDF-11624 +// #define SOC_SUPPORTS_SECURE_DL_MODE 1 +// #define SOC_ULP_SUPPORTED 1 +#define SOC_EFUSE_KEY_PURPOSE_FIELD 1 +#define SOC_EFUSE_SUPPORTED 1 //TODO: [ESP32H21] IDF-11507 +// #define SOC_RTC_FAST_MEM_SUPPORTED 1 +#define SOC_RTC_MEM_SUPPORTED 1 //TODO: [ESP32H21] IDF-11548 +// #define SOC_I2S_SUPPORTED 1 //TODO: [ESP32H21] IDF-11606, IDF-11608 +// #define SOC_SDM_SUPPORTED 1 //TODO: [ESP32H21] IDF-11573 +// #define SOC_GPSPI_SUPPORTED 1 //TODO: [ESP32H21] IDF-11583, IDF-11584, IDF-11587 +// #define SOC_LEDC_SUPPORTED 1 //TODO: [ESP32H21] IDF-11568 +// #define SOC_I2C_SUPPORTED 1 //TODO: [ESP32H21] IDF-11578, IDF-11580 +#define SOC_SYSTIMER_SUPPORTED 1 //TODO: [ESP32H21] IDF-11596, IDF-11598 +// #define SOC_SUPPORT_COEXISTENCE 1 //TODO: [ESP32H21] IDF-11658, IDF-11659, IDF-11660 +// #define SOC_MPI_SUPPORTED 1 +// #define SOC_SHA_SUPPORTED 1 //TODO: [ESP32H21] IDF-11501 +// #define SOC_HMAC_SUPPORTED 1 //TODO: [ESP32H21] IDF-11495 +// #define SOC_DIG_SIGN_SUPPORTED 1 //TODO: [ESP32H21] IDF-11497 +// #define SOC_ECC_SUPPORTED 1 //TODO: [ESP32H21] IDF-11502 +// #define SOC_ECC_EXTENDED_MODES_SUPPORTED 1 //TODO: [ESP32H21] IDF-11502 +// #define SOC_ECDSA_SUPPORTED 1 //TODO: [ESP32H21] IDF-11496 +#define SOC_FLASH_ENC_SUPPORTED 1 //TODO: [ESP32H21] IDF-11499 +// #define SOC_SECURE_BOOT_SUPPORTED 1 //TODO: [ESP32H21] IDF-11500 +// #define SOC_BOD_SUPPORTED 1 //TODO: [ESP32H21] IDF-11530 +// #define SOC_APM_SUPPORTED 1 //TODO: [ESP32H21] IDF-11494 +#define SOC_PMU_SUPPORTED 1 //TODO: [ESP32H21] IDf-11522 +// #define SOC_LP_TIMER_SUPPORTED 1 //TODO: [ESP32H21] IDF-11512 +// #define SOC_LP_AON_SUPPORTED 1 +// #define SOC_LP_PERIPHERALS_SUPPORTED 1 +// #define SOC_CLK_TREE_SUPPORTED 1 //TODO: [ESP32H21] IDF-11521 +// #define SOC_ASSIST_DEBUG_SUPPORTED 1 //TODO: [ESP32H21] IDF-11545 +// #define SOC_WDT_SUPPORTED 1 //TODO: [ESP32H21] IDF-11528 +#define SOC_SPI_FLASH_SUPPORTED 1 //TODO: [ESP32H21] IDF-11526 +// #define SOC_RNG_SUPPORTED 1 //TODO: [ESP32H21] IDF-11503 +// #define SOC_MODEM_CLOCK_SUPPORTED 1 +// #define SOC_REG_I2C_SUPPORTED 1 //TODO: [ESP32H21] IDF-11550 +// #define SOC_PHY_SUPPORTED 1 +// #define SOC_PCNT_SUPPORTED 1 //TODO: [ESP32H21] IDF-11566 +// #define SOC_MCPWM_SUPPORTED 1 //TODO: [ESP32H21] IDF-11601 +// #define SOC_TWAI_SUPPORTED 1 //TODO: [ESP32H21] IDF-11574 +// #define SOC_ETM_SUPPORTED 1 //TODO: [ESP32H21] IDF-11576 +// #define SOC_PARLIO_SUPPORTED 1 //TODO: [ESP32H21] IDF-11570, IDF-11572 +// #define SOC_RMT_SUPPORTED 1 //TODO: [ESP32H21] IDF-11622 +// #define SOC_AES_SUPPORTED 1 //TODO: [ESP32H21] IDF-11504 +// #define SOC_SDIO_SLAVE_SUPPORTED 1 +// #define SOC_PAU_SUPPORTED 1 +// #define SOC_LIGHT_SLEEP_SUPPORTED 1 //TODO: [ESP32H21] IDF-11517, IDF-11520 +// #define SOC_DEEP_SLEEP_SUPPORTED 1 //TODO: [ESP32H21] IDF-11514 +// #define SOC_MODEM_CLOCK_SUPPORTED 1 +// #define SOC_PM_SUPPORTED 1 + +/*-------------------------- XTAL CAPS ---------------------------------------*/ +#define SOC_XTAL_SUPPORT_32M 1 + +/*-------------------------- AES CAPS -----------------------------------------*/ +#define SOC_AES_SUPPORT_DMA (1) + +/* Has a centralized DMA, which is shared with all peripherals */ +#define SOC_AES_GDMA (1) + +#define SOC_AES_SUPPORT_AES_128 (1) +#define SOC_AES_SUPPORT_AES_256 (1) + +/*-------------------------- ADC CAPS -------------------------------*/ +/*!< SAR ADC Module*/ +// #define SOC_ADC_DIG_CTRL_SUPPORTED 1 +// #define SOC_ADC_DIG_IIR_FILTER_SUPPORTED 1 +// #define SOC_ADC_MONITOR_SUPPORTED 1 +// #define SOC_ADC_DIG_SUPPORTED_UNIT(UNIT) 1 //Digital controller supported ADC unit +// #define SOC_ADC_DMA_SUPPORTED 1 +#define SOC_ADC_PERIPH_NUM (1U) +#define SOC_ADC_CHANNEL_NUM(PERIPH_NUM) (5) +#define SOC_ADC_MAX_CHANNEL_NUM (5) +#define SOC_ADC_ATTEN_NUM (4) + +/*!< Digital */ +#define SOC_ADC_DIGI_CONTROLLER_NUM (1U) +#define SOC_ADC_PATT_LEN_MAX (8) /*!< One pattern table, each contains 8 items. Each item takes 1 byte */ +#define SOC_ADC_DIGI_MAX_BITWIDTH (12) +#define SOC_ADC_DIGI_MIN_BITWIDTH (12) +#define SOC_ADC_DIGI_IIR_FILTER_NUM (2) +#define SOC_ADC_DIGI_MONITOR_NUM (2) +#define SOC_ADC_DIGI_RESULT_BYTES (4) +#define SOC_ADC_DIGI_DATA_BYTES_PER_CONV (4) +/*!< F_sample = F_digi_con / 2 / interval. F_digi_con = 5M for now. 30 <= interval<= 4095 */ +#define SOC_ADC_SAMPLE_FREQ_THRES_HIGH 83333 +#define SOC_ADC_SAMPLE_FREQ_THRES_LOW 611 + +/*!< RTC */ +#define SOC_ADC_RTC_MIN_BITWIDTH (12) +#define SOC_ADC_RTC_MAX_BITWIDTH (12) + +/*!< Calibration */ +// #define SOC_ADC_CALIBRATION_V1_SUPPORTED (1) /*!< support HW offset calibration version 1*/ +// #define SOC_ADC_SELF_HW_CALI_SUPPORTED (1) /*!< support HW offset self calibration */ +// #define SOC_ADC_CALIB_CHAN_COMPENS_SUPPORTED (1) /*!< support channel compensation to the HW offset calibration */ + +/*!< Interrupt */ +// #define SOC_ADC_TEMPERATURE_SHARE_INTR (1) + +/*!< ADC power control is shared by PWDET */ +// #define SOC_ADC_SHARED_POWER 1 + +/*-------------------------- APB BACKUP DMA CAPS -------------------------------*/ +#define SOC_APB_BACKUP_DMA (0) + +/*-------------------------- BROWNOUT CAPS -----------------------------------*/ +#define SOC_BROWNOUT_RESET_SUPPORTED 1 + +/*-------------------------- CACHE CAPS --------------------------------------*/ +#define SOC_SHARED_IDCACHE_SUPPORTED 1 //Shared Cache for both instructions and data +#define SOC_CACHE_FREEZE_SUPPORTED 1 + +/*-------------------------- CPU CAPS ----------------------------------------*/ +#define SOC_CPU_CORES_NUM (1U) +#define SOC_CPU_INTR_NUM 32 +#define SOC_CPU_HAS_FLEXIBLE_INTC 1 +#define SOC_INT_PLIC_SUPPORTED 1 //riscv platform-level interrupt controller +#define SOC_CPU_HAS_CSR_PC 1 + +#define SOC_CPU_BREAKPOINTS_NUM 4 +#define SOC_CPU_WATCHPOINTS_NUM 4 +#define SOC_CPU_WATCHPOINT_MAX_REGION_SIZE 0x80000000 // bytes + +#define SOC_CPU_HAS_PMA 1 +#define SOC_CPU_IDRAM_SPLIT_USING_PMP 1 +#define SOC_CPU_PMP_REGION_GRANULARITY 4 + +/*-------------------------- MMU CAPS ----------------------------------------*/ +// #define SOC_MMU_PAGE_SIZE_CONFIGURABLE (1) +// #define SOC_MMU_PAGE_SIZE_8KB_SUPPORTED (1) +#define SOC_MMU_PERIPH_NUM (1U) +#define SOC_MMU_LINEAR_ADDRESS_REGION_NUM (1U) +#define SOC_MMU_DI_VADDR_SHARED (1) /*!< D/I vaddr are shared */ + +/*-------------------------- DIGITAL SIGNATURE CAPS ----------------------------------------*/ +/** The maximum length of a Digital Signature in bits. */ +#define SOC_DS_SIGNATURE_MAX_BIT_LEN (3072) + +/** Initialization vector (IV) length for the RSA key parameter message digest (MD) in bytes. */ +#define SOC_DS_KEY_PARAM_MD_IV_LENGTH (16) + +/** Maximum wait time for DS parameter decryption key. If overdue, then key error. + See TRM DS chapter for more details */ +#define SOC_DS_KEY_CHECK_MAX_WAIT_US (1100) + +/*-------------------------- GDMA CAPS -------------------------------------*/ +#define SOC_AHB_GDMA_VERSION 1U +#define SOC_GDMA_NUM_GROUPS_MAX 1U +#define SOC_GDMA_PAIRS_PER_GROUP_MAX 3 +// #define SOC_GDMA_SUPPORT_ETM 1 // Support ETM submodule +// #define SOC_GDMA_SUPPORT_SLEEP_RETENTION 1 + +/*-------------------------- ETM CAPS --------------------------------------*/ +#define SOC_ETM_GROUPS 1U // Number of ETM groups +#define SOC_ETM_CHANNELS_PER_GROUP 50 // Number of ETM channels in the group + +/*-------------------------- GPIO CAPS ---------------------------------------*/ +// ESP32-H21 has 1 GPIO peripheral +#define SOC_GPIO_PORT 1U +#define SOC_GPIO_PIN_COUNT 28 +// #define SOC_GPIO_SUPPORT_PIN_GLITCH_FILTER 1 +// #define SOC_GPIO_FLEX_GLITCH_FILTER_NUM 8 +// #define SOC_GPIO_SUPPORT_PIN_HYS_FILTER 1 +// #define SOC_GPIO_SUPPORT_PIN_HYS_CTRL_BY_EFUSE 1 // By default, hysteresis enable/disable is controlled by efuse + +// GPIO peripheral has the ETM extension +// #define SOC_GPIO_SUPPORT_ETM 1 + +// Target has no full LP IO subsystem, GPIO7~14 remain LP function (powered by VDD3V3_LP, and can be used as ext1 wakeup pins) +// Digital IOs have their own registers to control pullup/down/capability +// However, there is no way to control pullup/down/capability for IOs under LP function since there is no LP_IOMUX registers +#define SOC_GPIO_SUPPORT_RTC_INDEPENDENT (1) + +// LP IO peripherals have independent clock gating to manage +#define SOC_LP_IO_CLOCK_IS_INDEPENDENT (1) + +#define SOC_GPIO_VALID_GPIO_MASK ((1U << SOC_GPIO_PIN_COUNT) - 1) +#define SOC_GPIO_VALID_OUTPUT_GPIO_MASK SOC_GPIO_VALID_GPIO_MASK + +#define SOC_GPIO_IN_RANGE_MAX 27 +#define SOC_GPIO_OUT_RANGE_MAX 27 + +// digital I/O pad powered by VDD3P3_CPU or VDD_SPI(GPIO_NUM_0~6. GPIO_NUM_15~27) +#define SOC_GPIO_VALID_DIGITAL_IO_PAD_MASK 0x000000000FFF807FULL + +// Support to force hold all IOs +// #define SOC_GPIO_SUPPORT_FORCE_HOLD (1) +// Support to hold a single digital I/O when the digital domain is powered off +// #define SOC_GPIO_SUPPORT_HOLD_SINGLE_IO_IN_DSLP (1) + +// The Clock Out signal is route to the pin by GPIO matrix +#define SOC_GPIO_CLOCKOUT_BY_GPIO_MATRIX (1) +#define SOC_CLOCKOUT_HAS_SOURCE_GATE (1) +#define SOC_GPIO_CLOCKOUT_CHANNEL_NUM (3) + +/*-------------------------- RTCIO CAPS --------------------------------------*/ +/* No dedicated LP_IOMUX subsystem on ESP32-H2. LP functions are still supported + * for hold, wake & 32kHz crystal functions - via LP_AON registers */ +// #define SOC_RTCIO_PIN_COUNT (8U) +// #define SOC_RTCIO_HOLD_SUPPORTED (1) +// #define SOC_RTCIO_VALID_RTCIO_MASK (0x7F80) + +/*-------------------------- Dedicated GPIO CAPS -----------------------------*/ +#define SOC_DEDIC_GPIO_OUT_CHANNELS_NUM (8) /*!< 8 outward channels on each CPU core */ +#define SOC_DEDIC_GPIO_IN_CHANNELS_NUM (8) /*!< 8 inward channels on each CPU core */ +#define SOC_DEDIC_PERIPH_ALWAYS_ENABLE (1) /*!< The dedicated GPIO (a.k.a. fast GPIO) is featured by some customized CPU instructions, which is always enabled */ + +/*------------------------- Analog Comparator CAPS ---------------------------*/ +#define SOC_ANA_CMPR_NUM (1U) +#define SOC_ANA_CMPR_INTR_SHARE_WITH_GPIO (1) + +/*-------------------------- I2C CAPS ----------------------------------------*/ +// ESP32-H21 has 2 I2C +// #define SOC_I2C_NUM (2U) +// #define SOC_HP_I2C_NUM (2U) + +// #define SOC_I2C_FIFO_LEN (32) /*!< I2C hardware FIFO depth */ +// #define SOC_I2C_CMD_REG_NUM (8) /*!< Number of I2C command registers */ +// #define SOC_I2C_SUPPORT_SLAVE (1) + +// #define SOC_I2C_SUPPORT_HW_FSM_RST (1) +// #define SOC_I2C_SUPPORT_HW_CLR_BUS (1) + +// #define SOC_I2C_SUPPORT_XTAL (1) +// #define SOC_I2C_SUPPORT_RTC (1) +// #define SOC_I2C_SUPPORT_10BIT_ADDR (1) +// #define SOC_I2C_SLAVE_SUPPORT_BROADCAST (1) +// #define SOC_I2C_SLAVE_CAN_GET_STRETCH_CAUSE (1) +// #define SOC_I2C_SLAVE_SUPPORT_I2CRAM_ACCESS (1) +// #define SOC_I2C_SLAVE_SUPPORT_SLAVE_UNMATCH (1) +// #define SOC_I2C_SUPPORT_SLEEP_RETENTION (1) + +/*-------------------------- I2S CAPS ----------------------------------------*/ +// #define SOC_I2S_NUM (1U) +// #define SOC_I2S_HW_VERSION_2 (1) +// // #define SOC_I2S_SUPPORTS_ETM (1) +// #define SOC_I2S_SUPPORTS_XTAL (1) +// #define SOC_I2S_SUPPORTS_PLL_F96M (1) +// #define SOC_I2S_SUPPORTS_PLL_F64M (1) +// #define SOC_I2S_SUPPORTS_PCM (1) +// #define SOC_I2S_SUPPORTS_PDM (1) +// #define SOC_I2S_SUPPORTS_PDM_TX (1) +// #define SOC_I2S_PDM_MAX_TX_LINES (2) +// #define SOC_I2S_SUPPORTS_TDM (1) +// #define SOC_I2S_TDM_FULL_DATA_WIDTH (1) /*!< No limitation to data bit width when using multiple slots */ + +/*-------------------------- LEDC CAPS ---------------------------------------*/ +// #define SOC_LEDC_SUPPORT_PLL_DIV_CLOCK (1) +// #define SOC_LEDC_SUPPORT_XTAL_CLOCK (1) +// #define SOC_LEDC_CHANNEL_NUM (6) +// #define SOC_LEDC_TIMER_BIT_WIDTH (20) +// #define SOC_LEDC_SUPPORT_FADE_STOP (1) +// #define SOC_LEDC_GAMMA_CURVE_FADE_SUPPORTED (1) +// #define SOC_LEDC_GAMMA_CURVE_FADE_RANGE_MAX (16) +// #define SOC_LEDC_FADE_PARAMS_BIT_WIDTH (10) + +/*-------------------------- MPU CAPS ----------------------------------------*/ +// #define SOC_MPU_CONFIGURABLE_REGIONS_SUPPORTED 0 +// #define SOC_MPU_MIN_REGION_SIZE 0x20000000U +// #define SOC_MPU_REGIONS_MAX_NUM 8 +// #define SOC_MPU_REGION_RO_SUPPORTED 0 +// #define SOC_MPU_REGION_WO_SUPPORTED 0 + +/*-------------------------- PCNT CAPS ---------------------------------------*/ +// #define SOC_PCNT_GROUPS 1U +// #define SOC_PCNT_UNITS_PER_GROUP 4 +// #define SOC_PCNT_CHANNELS_PER_UNIT 2 +// #define SOC_PCNT_THRES_POINT_PER_UNIT 2 +// #define SOC_PCNT_SUPPORT_RUNTIME_THRES_UPDATE 1 + +/*--------------------------- RMT CAPS ---------------------------------------*/ +// #define SOC_RMT_GROUPS 1U /*!< One RMT group */ +// #define SOC_RMT_TX_CANDIDATES_PER_GROUP 2 /*!< Number of channels that capable of Transmit */ +// #define SOC_RMT_RX_CANDIDATES_PER_GROUP 2 /*!< Number of channels that capable of Receive */ +// #define SOC_RMT_CHANNELS_PER_GROUP 4 /*!< Total 4 channels */ +// #define SOC_RMT_MEM_WORDS_PER_CHANNEL 48 /*!< Each channel owns 48 words memory (1 word = 4 Bytes) */ +// #define SOC_RMT_SUPPORT_RX_PINGPONG 1 /*!< Support Ping-Pong mode on RX path */ +// #define SOC_RMT_SUPPORT_RX_DEMODULATION 1 /*!< Support signal demodulation on RX path (i.e. remove carrier) */ +// #define SOC_RMT_SUPPORT_TX_ASYNC_STOP 1 /*!< Support stop transmission asynchronously */ +// #define SOC_RMT_SUPPORT_TX_LOOP_COUNT 1 /*!< Support transmit specified number of cycles in loop mode */ +// #define SOC_RMT_SUPPORT_TX_LOOP_AUTO_STOP 1 /*!< Hardware support of auto-stop in loop mode */ +// #define SOC_RMT_SUPPORT_TX_SYNCHRO 1 /*!< Support coordinate a group of TX channels to start simultaneously */ +// #define SOC_RMT_SUPPORT_TX_CARRIER_DATA_ONLY 1 /*!< TX carrier can be modulated to data phase only */ +// #define SOC_RMT_SUPPORT_XTAL 1 /*!< Support set XTAL clock as the RMT clock source */ +// #define SOC_RMT_SUPPORT_RC_FAST 1 /*!< Support set RC_FAST as the RMT clock source */ +// #define SOC_RMT_SUPPORT_SLEEP_RETENTION 1 /*!< The sleep retention feature can help back up RMT registers before sleep */ + +/*-------------------------- MCPWM CAPS --------------------------------------*/ +// #define SOC_MCPWM_GROUPS (1U) ///< 1 MCPWM groups on the chip (i.e., the number of independent MCPWM peripherals) +// #define SOC_MCPWM_TIMERS_PER_GROUP (3) ///< The number of timers that each group has +// #define SOC_MCPWM_OPERATORS_PER_GROUP (3) ///< The number of operators that each group has +// #define SOC_MCPWM_COMPARATORS_PER_OPERATOR (2) ///< The number of comparators that each operator has +// #define SOC_MCPWM_GENERATORS_PER_OPERATOR (2) ///< The number of generators that each operator has +// #define SOC_MCPWM_TRIGGERS_PER_OPERATOR (2) ///< The number of triggers that each operator has +// #define SOC_MCPWM_GPIO_FAULTS_PER_GROUP (3) ///< The number of fault signal detectors that each group has +// #define SOC_MCPWM_CAPTURE_TIMERS_PER_GROUP (1) ///< The number of capture timers that each group has +// #define SOC_MCPWM_CAPTURE_CHANNELS_PER_TIMER (3) ///< The number of capture channels that each capture timer has +// #define SOC_MCPWM_GPIO_SYNCHROS_PER_GROUP (3) ///< The number of GPIO synchros that each group has +// #define SOC_MCPWM_SWSYNC_CAN_PROPAGATE (1) ///< Software sync event can be routed to its output +// #define SOC_MCPWM_SUPPORT_ETM (1) ///< Support ETM (Event Task Matrix) +// #define SOC_MCPWM_CAPTURE_CLK_FROM_GROUP (1) ///< Capture timer shares clock with other PWM timers + +/*------------------------ USB SERIAL JTAG CAPS ------------------------------*/ +// #define SOC_USB_SERIAL_JTAG_SUPPORT_LIGHT_SLEEP (1) /*!< Support to maintain minimum usb communication during light sleep */ // TODO: IDF-6395 + +/*-------------------------- PARLIO CAPS --------------------------------------*/ +// #define SOC_PARLIO_GROUPS 1U /*!< Number of parallel IO peripherals */ +// #define SOC_PARLIO_TX_UNITS_PER_GROUP 1U /*!< number of TX units in each group */ +// #define SOC_PARLIO_RX_UNITS_PER_GROUP 1U /*!< number of RX units in each group */ +// #define SOC_PARLIO_TX_UNIT_MAX_DATA_WIDTH 8 /*!< Number of data lines of the TX unit */ +// #define SOC_PARLIO_RX_UNIT_MAX_DATA_WIDTH 8 /*!< Number of data lines of the RX unit */ +// #define SOC_PARLIO_TX_CLK_SUPPORT_GATING 1 /*!< Support gating TX clock */ +// #define SOC_PARLIO_RX_CLK_SUPPORT_GATING 1 /*!< Support gating RX clock */ +// #define SOC_PARLIO_RX_CLK_SUPPORT_OUTPUT 1 /*!< Support output RX clock to a GPIO */ +// #define SOC_PARLIO_TRANS_BIT_ALIGN 1 /*!< Support bit alignment in transaction */ + +/*--------------------------- MPI CAPS ---------------------------------------*/ +#define SOC_MPI_MEM_BLOCKS_NUM (4) +#define SOC_MPI_OPERATIONS_NUM (3) + +/*--------------------------- RSA CAPS ---------------------------------------*/ +#define SOC_RSA_MAX_BIT_LEN (3072) + +/*--------------------------- SHA CAPS ---------------------------------------*/ + +/* Max amount of bytes in a single DMA operation is 4095, + for SHA this means that the biggest safe amount of bytes is + 31 blocks of 128 bytes = 3968 +*/ +#define SOC_SHA_DMA_MAX_BUFFER_SIZE (3968) +#define SOC_SHA_SUPPORT_DMA (1) + +/* The SHA engine is able to resume hashing from a user */ +#define SOC_SHA_SUPPORT_RESUME (1) + +/* Has a centralized DMA, which is shared with all peripherals */ +#define SOC_SHA_GDMA (1) + +/* Supported HW algorithms */ +#define SOC_SHA_SUPPORT_SHA1 (1) +#define SOC_SHA_SUPPORT_SHA224 (1) +#define SOC_SHA_SUPPORT_SHA256 (1) + +/*-------------------------- SPI CAPS ----------------------------------------*/ +#define SOC_SPI_PERIPH_NUM 2 +#define SOC_SPI_PERIPH_CS_NUM(i) 6 +#define SOC_SPI_MAX_CS_NUM 6 + +#define SOC_SPI_MAXIMUM_BUFFER_SIZE 64 + +#define SOC_SPI_SUPPORT_DDRCLK 1 +#define SOC_SPI_SLAVE_SUPPORT_SEG_TRANS 1 +#define SOC_SPI_SUPPORT_CD_SIG 1 +#define SOC_SPI_SUPPORT_CONTINUOUS_TRANS 1 +#define SOC_SPI_SUPPORT_SLAVE_HD_VER2 1 +#define SOC_SPI_SUPPORT_CLK_XTAL 1 +#define SOC_SPI_SUPPORT_CLK_PLL_F48M 1 +#define SOC_SPI_SUPPORT_CLK_RC_FAST 1 + +// Peripheral supports DIO, DOUT, QIO, or QOUT +// host_id = 0 -> SPI0/SPI1, host_id = 1 -> SPI2, +#define SOC_SPI_PERIPH_SUPPORT_MULTILINE_MODE(host_id) ({(void)host_id; 1;}) + +#define SOC_SPI_SCT_SUPPORTED 1 +#define SOC_SPI_SCT_SUPPORTED_PERIPH(PERIPH_NUM) ((PERIPH_NUM==1) ? 1 : 0) //Support Segmented-Configure-Transfer +#define SOC_SPI_SCT_REG_NUM 14 +#define SOC_SPI_SCT_BUFFER_NUM_MAX (1 + SOC_SPI_SCT_REG_NUM) //1-word-bitmap + 14-word-regs +#define SOC_SPI_SCT_CONF_BITLEN_MAX 0x3FFFA //18 bits wide reg + +#define SOC_MEMSPI_IS_INDEPENDENT 1 +#define SOC_SPI_MAX_PRE_DIVIDER 16 + +/*-------------------------- SPI MEM CAPS ---------------------------------------*/ +#define SOC_SPI_MEM_SUPPORT_AUTO_WAIT_IDLE (1) +#define SOC_SPI_MEM_SUPPORT_AUTO_SUSPEND (1) +#define SOC_SPI_MEM_SUPPORT_AUTO_RESUME (1) +#define SOC_SPI_MEM_SUPPORT_IDLE_INTR (1) +#define SOC_SPI_MEM_SUPPORT_SW_SUSPEND (1) +#define SOC_SPI_MEM_SUPPORT_CHECK_SUS (1) +#define SOC_SPI_MEM_SUPPORT_WRAP (1) + +#define SOC_MEMSPI_SRC_FREQ_64M_SUPPORTED 1 +#define SOC_MEMSPI_SRC_FREQ_32M_SUPPORTED 1 +#define SOC_MEMSPI_SRC_FREQ_16M_SUPPORTED 1 + +/*-------------------------- SYSTIMER CAPS ----------------------------------*/ +#define SOC_SYSTIMER_COUNTER_NUM 2 // Number of counter units +#define SOC_SYSTIMER_ALARM_NUM 3 // Number of alarm units +#define SOC_SYSTIMER_BIT_WIDTH_LO 32 // Bit width of systimer low part +#define SOC_SYSTIMER_BIT_WIDTH_HI 20 // Bit width of systimer high part +#define SOC_SYSTIMER_FIXED_DIVIDER 1 // Clock source divider is fixed to 2 when clock source is XTAL +#define SOC_SYSTIMER_SUPPORT_RC_FAST 1 // Systimer can use RC_FAST clock source +#define SOC_SYSTIMER_INT_LEVEL 1 // Systimer peripheral uses level interrupt +#define SOC_SYSTIMER_ALARM_MISS_COMPENSATE 1 // Systimer peripheral can generate interrupt immediately if t(target) > t(current) +// #define SOC_SYSTIMER_SUPPORT_ETM 1 // Systimer comparator can generate ETM event + +/*-------------------------- LP_TIMER CAPS ----------------------------------*/ +#define SOC_LP_TIMER_BIT_WIDTH_LO 32 // Bit width of lp_timer low part +#define SOC_LP_TIMER_BIT_WIDTH_HI 16 // Bit width of lp_timer high part + +/*--------------------------- TIMER GROUP CAPS ---------------------------------------*/ +#define SOC_TIMER_GROUPS (2) +#define SOC_TIMER_GROUP_TIMERS_PER_GROUP (1U) +#define SOC_TIMER_GROUP_COUNTER_BIT_WIDTH (54) +#define SOC_TIMER_GROUP_SUPPORT_XTAL (1) +#define SOC_TIMER_GROUP_SUPPORT_RC_FAST (1) +#define SOC_TIMER_GROUP_TOTAL_TIMERS (2) +// #define SOC_TIMER_SUPPORT_ETM (1) +// #define SOC_TIMER_SUPPORT_SLEEP_RETENTION (1) + +/*--------------------------- WATCHDOG CAPS ---------------------------------------*/ +#define SOC_MWDT_SUPPORT_XTAL (1) +// #define SOC_MWDT_SUPPORT_SLEEP_RETENTION (1) + +/*-------------------------- TWAI CAPS ---------------------------------------*/ +// #define SOC_TWAI_CONTROLLER_NUM 1UL +// #define SOC_TWAI_CLK_SUPPORT_XTAL 1 +// #define SOC_TWAI_BRP_MIN 2 +// #define SOC_TWAI_BRP_MAX 32768 +// #define SOC_TWAI_SUPPORTS_RX_STATUS 1 + +/*-------------------------- eFuse CAPS----------------------------*/ +#define SOC_EFUSE_DIS_PAD_JTAG 1 +#define SOC_EFUSE_DIS_USB_JTAG 1 +#define SOC_EFUSE_DIS_DIRECT_BOOT 1 +#define SOC_EFUSE_SOFT_DIS_JTAG 1 +#define SOC_EFUSE_DIS_ICACHE 1 +#define SOC_EFUSE_BLOCK9_KEY_PURPOSE_QUIRK 1 // XTS-AES and ECDSA key purposes not supported for this block +#define SOC_EFUSE_ECDSA_USE_HARDWARE_K 1 // Force use hardware TRNG supplied K for ECDSA +#define SOC_EFUSE_ECDSA_KEY 1 + +/*-------------------------- Secure Boot CAPS----------------------------*/ +#define SOC_SECURE_BOOT_V2_RSA 1 +#define SOC_SECURE_BOOT_V2_ECC 1 +#define SOC_EFUSE_SECURE_BOOT_KEY_DIGESTS 3 +#define SOC_EFUSE_REVOKE_BOOT_KEY_DIGESTS 1 +#define SOC_SUPPORT_SECURE_BOOT_REVOKE_KEY 1 + +/*-------------------------- Flash Encryption CAPS----------------------------*/ +#define SOC_FLASH_ENCRYPTED_XTS_AES_BLOCK_MAX (64) +#define SOC_FLASH_ENCRYPTION_XTS_AES 1 +#define SOC_FLASH_ENCRYPTION_XTS_AES_128 1 + +/*-------------------------- APM CAPS ----------------------------------------*/ +#define SOC_APM_CTRL_FILTER_SUPPORTED 1 /*!< Support for APM control filter */ + +/*------------------------ Anti DPA (Security) CAPS --------------------------*/ +#define SOC_CRYPTO_DPA_PROTECTION_SUPPORTED 1 + +/*------------------------- ECDSA CAPS -------------------------*/ +#define SOC_ECDSA_USES_MPI (1) + +/*-------------------------- UART CAPS ---------------------------------------*/ +// ESP32-H21 has 2 UARTs +#define SOC_UART_NUM (2) +#define SOC_UART_HP_NUM (2) +#define SOC_UART_FIFO_LEN (128) /*!< The UART hardware FIFO length */ +#define SOC_UART_BITRATE_MAX (5000000) /*!< Max bit rate supported by UART */ + +#define SOC_UART_SUPPORT_RTC_CLK (1) /*!< Support RTC clock as the clock source */ +#define SOC_UART_SUPPORT_XTAL_CLK (1) /*!< Support XTAL clock as the clock source */ +#define SOC_UART_SUPPORT_WAKEUP_INT (1) /*!< Support UART wakeup interrupt */ + +// UART has an extra TX_WAIT_SEND state when the FIFO is not empty and XOFF is enabled +#define SOC_UART_SUPPORT_FSM_TX_WAIT_SEND (1) + +// #define SOC_UART_SUPPORT_SLEEP_RETENTION (1) /*!< Support back up registers before sleep */ + +/*-------------------------- COEXISTENCE HARDWARE PTI CAPS -------------------------------*/ +#define SOC_COEX_HW_PTI (1) + +/*-------------------------- EXTERNAL COEXISTENCE CAPS -------------------------------------*/ +#define SOC_EXTERNAL_COEX_ADVANCE (1) /*!< HARDWARE ADVANCED EXTERNAL COEXISTENCE CAPS */ +#define SOC_EXTERNAL_COEX_LEADER_TX_LINE (0) /*!< EXTERNAL COEXISTENCE TX LINE CAPS */ + +/*--------------- PHY REGISTER AND MEMORY SIZE CAPS --------------------------*/ +#define SOC_PHY_DIG_REGS_MEM_SIZE (21*4) + +/*-------------------------- Power Management CAPS ----------------------------*/ +#define SOC_PM_SUPPORT_BT_WAKEUP (1) +#define SOC_PM_SUPPORT_EXT1_WAKEUP (1) +#define SOC_PM_SUPPORT_EXT1_WAKEUP_MODE_PER_PIN (1) /*! #include "soc/soc.h" +#include "soc/efuse_defs.h" #ifdef __cplusplus extern "C" { #endif /** EFUSE_PGM_DATA0_REG register - * Represents pgm_data0 + * Register 0 that stores data to be programmed. */ #define EFUSE_PGM_DATA0_REG (DR_REG_EFUSE_BASE + 0x0) /** EFUSE_PGM_DATA_0 : R/W; bitpos: [31:0]; default: 0; @@ -24,11 +25,11 @@ extern "C" { #define EFUSE_PGM_DATA_0_S 0 /** EFUSE_PGM_DATA1_REG register - * Represents pgm_data1 + * Register 1 that stores data to be programmed. */ #define EFUSE_PGM_DATA1_REG (DR_REG_EFUSE_BASE + 0x4) /** EFUSE_PGM_DATA_1 : R/W; bitpos: [31:0]; default: 0; - * Configures the 1th 32-bit data to be programmed. + * Configures the 1st 32-bit data to be programmed. */ #define EFUSE_PGM_DATA_1 0xFFFFFFFFU #define EFUSE_PGM_DATA_1_M (EFUSE_PGM_DATA_1_V << EFUSE_PGM_DATA_1_S) @@ -36,11 +37,11 @@ extern "C" { #define EFUSE_PGM_DATA_1_S 0 /** EFUSE_PGM_DATA2_REG register - * Represents pgm_data2 + * Register 2 that stores data to be programmed. */ #define EFUSE_PGM_DATA2_REG (DR_REG_EFUSE_BASE + 0x8) /** EFUSE_PGM_DATA_2 : R/W; bitpos: [31:0]; default: 0; - * Configures the 2th 32-bit data to be programmed. + * Configures the 2nd 32-bit data to be programmed. */ #define EFUSE_PGM_DATA_2 0xFFFFFFFFU #define EFUSE_PGM_DATA_2_M (EFUSE_PGM_DATA_2_V << EFUSE_PGM_DATA_2_S) @@ -48,11 +49,11 @@ extern "C" { #define EFUSE_PGM_DATA_2_S 0 /** EFUSE_PGM_DATA3_REG register - * Represents pgm_data3 + * Register 3 that stores data to be programmed. */ #define EFUSE_PGM_DATA3_REG (DR_REG_EFUSE_BASE + 0xc) /** EFUSE_PGM_DATA_3 : R/W; bitpos: [31:0]; default: 0; - * Configures the 3th 32-bit data to be programmed. + * Configures the 3rd 32-bit data to be programmed. */ #define EFUSE_PGM_DATA_3 0xFFFFFFFFU #define EFUSE_PGM_DATA_3_M (EFUSE_PGM_DATA_3_V << EFUSE_PGM_DATA_3_S) @@ -60,7 +61,7 @@ extern "C" { #define EFUSE_PGM_DATA_3_S 0 /** EFUSE_PGM_DATA4_REG register - * Represents pgm_data4 + * Register 4 that stores data to be programmed. */ #define EFUSE_PGM_DATA4_REG (DR_REG_EFUSE_BASE + 0x10) /** EFUSE_PGM_DATA_4 : R/W; bitpos: [31:0]; default: 0; @@ -72,7 +73,7 @@ extern "C" { #define EFUSE_PGM_DATA_4_S 0 /** EFUSE_PGM_DATA5_REG register - * Represents pgm_data5 + * Register 5 that stores data to be programmed. */ #define EFUSE_PGM_DATA5_REG (DR_REG_EFUSE_BASE + 0x14) /** EFUSE_PGM_DATA_5 : R/W; bitpos: [31:0]; default: 0; @@ -84,7 +85,7 @@ extern "C" { #define EFUSE_PGM_DATA_5_S 0 /** EFUSE_PGM_DATA6_REG register - * Represents pgm_data6 + * Register 6 that stores data to be programmed. */ #define EFUSE_PGM_DATA6_REG (DR_REG_EFUSE_BASE + 0x18) /** EFUSE_PGM_DATA_6 : R/W; bitpos: [31:0]; default: 0; @@ -96,7 +97,7 @@ extern "C" { #define EFUSE_PGM_DATA_6_S 0 /** EFUSE_PGM_DATA7_REG register - * Represents pgm_data7 + * Register 7 that stores data to be programmed. */ #define EFUSE_PGM_DATA7_REG (DR_REG_EFUSE_BASE + 0x1c) /** EFUSE_PGM_DATA_7 : R/W; bitpos: [31:0]; default: 0; @@ -108,11 +109,11 @@ extern "C" { #define EFUSE_PGM_DATA_7_S 0 /** EFUSE_PGM_CHECK_VALUE0_REG register - * Represents pgm_check_value0 + * Register 0 that stores the RS code to be programmed. */ #define EFUSE_PGM_CHECK_VALUE0_REG (DR_REG_EFUSE_BASE + 0x20) /** EFUSE_PGM_RS_DATA_0 : R/W; bitpos: [31:0]; default: 0; - * Configures the 0th RS code to be programmed. + * Configures the 0th 32-bit RS code to be programmed. */ #define EFUSE_PGM_RS_DATA_0 0xFFFFFFFFU #define EFUSE_PGM_RS_DATA_0_M (EFUSE_PGM_RS_DATA_0_V << EFUSE_PGM_RS_DATA_0_S) @@ -120,11 +121,11 @@ extern "C" { #define EFUSE_PGM_RS_DATA_0_S 0 /** EFUSE_PGM_CHECK_VALUE1_REG register - * Represents pgm_check_value1 + * Register 1 that stores the RS code to be programmed. */ #define EFUSE_PGM_CHECK_VALUE1_REG (DR_REG_EFUSE_BASE + 0x24) /** EFUSE_PGM_RS_DATA_1 : R/W; bitpos: [31:0]; default: 0; - * Configures the 1th RS code to be programmed. + * Configures the 1st 32-bit RS code to be programmed. */ #define EFUSE_PGM_RS_DATA_1 0xFFFFFFFFU #define EFUSE_PGM_RS_DATA_1_M (EFUSE_PGM_RS_DATA_1_V << EFUSE_PGM_RS_DATA_1_S) @@ -132,11 +133,11 @@ extern "C" { #define EFUSE_PGM_RS_DATA_1_S 0 /** EFUSE_PGM_CHECK_VALUE2_REG register - * Represents pgm_check_value2 + * Register 2 that stores the RS code to be programmed. */ #define EFUSE_PGM_CHECK_VALUE2_REG (DR_REG_EFUSE_BASE + 0x28) /** EFUSE_PGM_RS_DATA_2 : R/W; bitpos: [31:0]; default: 0; - * Configures the 2th RS code to be programmed. + * Configures the 2nd 32-bit RS code to be programmed. */ #define EFUSE_PGM_RS_DATA_2 0xFFFFFFFFU #define EFUSE_PGM_RS_DATA_2_M (EFUSE_PGM_RS_DATA_2_V << EFUSE_PGM_RS_DATA_2_S) @@ -144,14 +145,12 @@ extern "C" { #define EFUSE_PGM_RS_DATA_2_S 0 /** EFUSE_RD_WR_DIS_REG register - * Represents rd_wr_dis + * BLOCK0 data register 0. */ #define EFUSE_RD_WR_DIS_REG (DR_REG_EFUSE_BASE + 0x2c) /** EFUSE_WR_DIS : RO; bitpos: [31:0]; default: 0; * Represents whether programming of individual eFuse memory bit is disabled or - * enabled. - * 1: Disabled - * 0: Enabled + * enabled. 1: Disabled. 0 Enabled. */ #define EFUSE_WR_DIS 0xFFFFFFFFU #define EFUSE_WR_DIS_M (EFUSE_WR_DIS_V << EFUSE_WR_DIS_S) @@ -159,243 +158,219 @@ extern "C" { #define EFUSE_WR_DIS_S 0 /** EFUSE_RD_REPEAT_DATA0_REG register - * Represents rd_repeat_data + * BLOCK0 data register 1. */ #define EFUSE_RD_REPEAT_DATA0_REG (DR_REG_EFUSE_BASE + 0x30) /** EFUSE_RD_DIS : RO; bitpos: [6:0]; default: 0; * Represents whether reading of individual eFuse block(block4~block10) is disabled or - * enabled. - * 1: Disabled - * 0: Enabled + * enabled. 1: disabled. 0: enabled. */ #define EFUSE_RD_DIS 0x0000007FU #define EFUSE_RD_DIS_M (EFUSE_RD_DIS_V << EFUSE_RD_DIS_S) #define EFUSE_RD_DIS_V 0x0000007FU #define EFUSE_RD_DIS_S 0 -/** EFUSE_PVT_GLITCH_EN : RO; bitpos: [7]; default: 0; - * Represents whether to enable PVT power glitch monitor function. - * 1: Enable. - * 0: Disable - */ -#define EFUSE_PVT_GLITCH_EN (BIT(7)) -#define EFUSE_PVT_GLITCH_EN_M (EFUSE_PVT_GLITCH_EN_V << EFUSE_PVT_GLITCH_EN_S) -#define EFUSE_PVT_GLITCH_EN_V 0x00000001U -#define EFUSE_PVT_GLITCH_EN_S 7 +/** EFUSE_RPT4_RESERVED0_4 : RO; bitpos: [7]; default: 0; + * Reserved. + */ +#define EFUSE_RPT4_RESERVED0_4 (BIT(7)) +#define EFUSE_RPT4_RESERVED0_4_M (EFUSE_RPT4_RESERVED0_4_V << EFUSE_RPT4_RESERVED0_4_S) +#define EFUSE_RPT4_RESERVED0_4_V 0x00000001U +#define EFUSE_RPT4_RESERVED0_4_S 7 /** EFUSE_DIS_ICACHE : RO; bitpos: [8]; default: 0; - * Represents whether icache is disabled or enabled. - * 1: Disabled - * 0: Enabled + * Represents whether icache is disabled or enabled. 1: disabled. 0: enabled. */ #define EFUSE_DIS_ICACHE (BIT(8)) #define EFUSE_DIS_ICACHE_M (EFUSE_DIS_ICACHE_V << EFUSE_DIS_ICACHE_S) #define EFUSE_DIS_ICACHE_V 0x00000001U #define EFUSE_DIS_ICACHE_S 8 /** EFUSE_DIS_USB_JTAG : RO; bitpos: [9]; default: 0; - * Represents whether the USB-to-JTAG function in USB Serial/JTAG is disabled. - * 1: Disabled - * 0: Enabled + * Represents whether the function of usb switch to jtag is disabled or enabled. 1: + * disabled. 0: enabled. */ #define EFUSE_DIS_USB_JTAG (BIT(9)) #define EFUSE_DIS_USB_JTAG_M (EFUSE_DIS_USB_JTAG_V << EFUSE_DIS_USB_JTAG_S) #define EFUSE_DIS_USB_JTAG_V 0x00000001U #define EFUSE_DIS_USB_JTAG_S 9 /** EFUSE_POWERGLITCH_EN : RO; bitpos: [10]; default: 0; - * Represents whether to enable power glitch function. + * Represents whether power glitch function is enabled. 1: enabled. 0: disabled. */ #define EFUSE_POWERGLITCH_EN (BIT(10)) #define EFUSE_POWERGLITCH_EN_M (EFUSE_POWERGLITCH_EN_V << EFUSE_POWERGLITCH_EN_S) #define EFUSE_POWERGLITCH_EN_V 0x00000001U #define EFUSE_POWERGLITCH_EN_S 10 +/** EFUSE_DIS_USB_SERIAL_JTAG : RO; bitpos: [11]; default: 0; + * Represents whether USB-Serial-JTAG is disabled or enabled. 1: disabled. 0: enabled. + */ +#define EFUSE_DIS_USB_SERIAL_JTAG (BIT(11)) +#define EFUSE_DIS_USB_SERIAL_JTAG_M (EFUSE_DIS_USB_SERIAL_JTAG_V << EFUSE_DIS_USB_SERIAL_JTAG_S) +#define EFUSE_DIS_USB_SERIAL_JTAG_V 0x00000001U +#define EFUSE_DIS_USB_SERIAL_JTAG_S 11 /** EFUSE_DIS_FORCE_DOWNLOAD : RO; bitpos: [12]; default: 0; - * Represents whether the function that forces chip into Download mode is disabled. - * 1: Disabled - * 0: Enabled + * Represents whether the function that forces chip into download mode is disabled or + * enabled. 1: disabled. 0: enabled. */ #define EFUSE_DIS_FORCE_DOWNLOAD (BIT(12)) #define EFUSE_DIS_FORCE_DOWNLOAD_M (EFUSE_DIS_FORCE_DOWNLOAD_V << EFUSE_DIS_FORCE_DOWNLOAD_S) #define EFUSE_DIS_FORCE_DOWNLOAD_V 0x00000001U #define EFUSE_DIS_FORCE_DOWNLOAD_S 12 /** EFUSE_SPI_DOWNLOAD_MSPI_DIS : RO; bitpos: [13]; default: 0; - * Represents accessing MSPI flash/MSPI RAM by SYS AXI matrix is disabled during - * boot_mode_download. - * 1: Disabled - * 0: Enabled + * Represents whether SPI0 controller during boot_mode_download is disabled or + * enabled. 1: disabled. 0: enabled. */ #define EFUSE_SPI_DOWNLOAD_MSPI_DIS (BIT(13)) #define EFUSE_SPI_DOWNLOAD_MSPI_DIS_M (EFUSE_SPI_DOWNLOAD_MSPI_DIS_V << EFUSE_SPI_DOWNLOAD_MSPI_DIS_S) #define EFUSE_SPI_DOWNLOAD_MSPI_DIS_V 0x00000001U #define EFUSE_SPI_DOWNLOAD_MSPI_DIS_S 13 /** EFUSE_DIS_TWAI : RO; bitpos: [14]; default: 0; - * Represents whether TWAI function is disabled. - * 1: Disabled - * 0: Enabled + * Represents whether TWAI function is disabled or enabled. 1: disabled. 0: enabled. */ #define EFUSE_DIS_TWAI (BIT(14)) #define EFUSE_DIS_TWAI_M (EFUSE_DIS_TWAI_V << EFUSE_DIS_TWAI_S) #define EFUSE_DIS_TWAI_V 0x00000001U #define EFUSE_DIS_TWAI_S 14 /** EFUSE_JTAG_SEL_ENABLE : RO; bitpos: [15]; default: 0; - * Represents whether the selection of a JTAG signal source through the strapping pin - * value is enabled when both EFUSE_DIS_PAD_JTAG and EFUSE_DIS_USB_JTAG are configured - * to 0. For more information, please refer to Chapter Placeholder. - * 1: Enabled - * 0: Disabled + * Set this bit to enable selection between usb_to_jtag and pad_to_jtag through + * strapping gpio25 when both EFUSE_DIS_PAD_JTAG and EFUSE_DIS_USB_JTAG are equal to 0 */ #define EFUSE_JTAG_SEL_ENABLE (BIT(15)) #define EFUSE_JTAG_SEL_ENABLE_M (EFUSE_JTAG_SEL_ENABLE_V << EFUSE_JTAG_SEL_ENABLE_S) #define EFUSE_JTAG_SEL_ENABLE_V 0x00000001U #define EFUSE_JTAG_SEL_ENABLE_S 15 /** EFUSE_SOFT_DIS_JTAG : RO; bitpos: [18:16]; default: 0; - * Represents whether PAD JTAG is disabled in the soft way. It can be restarted via - * HMAC. - * Odd count of bits with a value of 1: Disabled - * Even count of bits with a value of 1: Enabled + * Represents whether JTAG is disabled in soft way. Odd number: disabled. Even number: + * enabled. */ #define EFUSE_SOFT_DIS_JTAG 0x00000007U #define EFUSE_SOFT_DIS_JTAG_M (EFUSE_SOFT_DIS_JTAG_V << EFUSE_SOFT_DIS_JTAG_S) #define EFUSE_SOFT_DIS_JTAG_V 0x00000007U #define EFUSE_SOFT_DIS_JTAG_S 16 /** EFUSE_DIS_PAD_JTAG : RO; bitpos: [19]; default: 0; - * Represents whether PAD JTAG is disabled in the hard way (permanently). - * 1: Disabled - * 0: Enabled + * Represents whether JTAG is disabled in the hard way(permanently). 1: disabled. 0: + * enabled. */ #define EFUSE_DIS_PAD_JTAG (BIT(19)) #define EFUSE_DIS_PAD_JTAG_M (EFUSE_DIS_PAD_JTAG_V << EFUSE_DIS_PAD_JTAG_S) #define EFUSE_DIS_PAD_JTAG_V 0x00000001U #define EFUSE_DIS_PAD_JTAG_S 19 /** EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT : RO; bitpos: [20]; default: 0; - * Represents whether flash encryption is disabled (except in SPI boot mode). - * 1: Disabled - * 0: Enabled + * Represents whether flash encrypt function is disabled or enabled(except in SPI boot + * mode). 1: disabled. 0: enabled. */ #define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT (BIT(20)) #define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_M (EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_V << EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_S) #define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_V 0x00000001U #define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_S 20 +/** EFUSE_USB_DREFH : RO; bitpos: [22:21]; default: 0; + * Represents the single-end input threshold vrefh, 1.76 V to 2 V with step of 80 mV. + */ +#define EFUSE_USB_DREFH 0x00000003U +#define EFUSE_USB_DREFH_M (EFUSE_USB_DREFH_V << EFUSE_USB_DREFH_S) +#define EFUSE_USB_DREFH_V 0x00000003U +#define EFUSE_USB_DREFH_S 21 +/** EFUSE_USB_DREFL : RO; bitpos: [24:23]; default: 0; + * Represents the single-end input threshold vrefl, 1.76 V to 2 V with step of 80 mV. + */ +#define EFUSE_USB_DREFL 0x00000003U +#define EFUSE_USB_DREFL_M (EFUSE_USB_DREFL_V << EFUSE_USB_DREFL_S) +#define EFUSE_USB_DREFL_V 0x00000003U +#define EFUSE_USB_DREFL_S 23 /** EFUSE_USB_EXCHG_PINS : RO; bitpos: [25]; default: 0; - * Represents whether the D+ and D- pins is exchanged. - * 1: Exchanged - * 0: Not exchanged + * Represents whether the D+ and D- pins is exchanged. 1: exchanged. 0: not exchanged. */ #define EFUSE_USB_EXCHG_PINS (BIT(25)) #define EFUSE_USB_EXCHG_PINS_M (EFUSE_USB_EXCHG_PINS_V << EFUSE_USB_EXCHG_PINS_S) #define EFUSE_USB_EXCHG_PINS_V 0x00000001U #define EFUSE_USB_EXCHG_PINS_S 25 /** EFUSE_VDD_SPI_AS_GPIO : RO; bitpos: [26]; default: 0; - * Represents whether vdd spi pin is functioned as gpio. - * 1: Functioned - * 0: Not functioned + * Represents whether vdd spi pin is functioned as gpio. 1: functioned. 0: not + * functioned. */ #define EFUSE_VDD_SPI_AS_GPIO (BIT(26)) #define EFUSE_VDD_SPI_AS_GPIO_M (EFUSE_VDD_SPI_AS_GPIO_V << EFUSE_VDD_SPI_AS_GPIO_S) #define EFUSE_VDD_SPI_AS_GPIO_V 0x00000001U #define EFUSE_VDD_SPI_AS_GPIO_S 26 -/** EFUSE_ECDSA_CURVE_MODE : RO; bitpos: [28:27]; default: 0; - * Represents the configuration of the curve of ECDSA calculation. - * 0: Only enable P256 - * 1: Only enable P192 - * 2: Both enable P256 and P192 - * 3: Only enable P256 - */ -#define EFUSE_ECDSA_CURVE_MODE 0x00000003U -#define EFUSE_ECDSA_CURVE_MODE_M (EFUSE_ECDSA_CURVE_MODE_V << EFUSE_ECDSA_CURVE_MODE_S) -#define EFUSE_ECDSA_CURVE_MODE_V 0x00000003U -#define EFUSE_ECDSA_CURVE_MODE_S 27 -/** EFUSE_ECC_FORCE_CONST_TIME : RO; bitpos: [29]; default: 0; - * Represents whether to permanently turn on ECC const-time mode. - * 0: Disabled - * 1: Enabled - */ -#define EFUSE_ECC_FORCE_CONST_TIME (BIT(29)) -#define EFUSE_ECC_FORCE_CONST_TIME_M (EFUSE_ECC_FORCE_CONST_TIME_V << EFUSE_ECC_FORCE_CONST_TIME_S) -#define EFUSE_ECC_FORCE_CONST_TIME_V 0x00000001U -#define EFUSE_ECC_FORCE_CONST_TIME_S 29 -/** EFUSE_XTS_DPA_PSEUDO_LEVEL : RO; bitpos: [31:30]; default: 0; - * Represents control method of xts pseudo-round anti-dpa attack function. - * 0: Controlled by register - * 1-3: The higher the value is, the more pseudo-rounds are inserted to the xts-aes - * calculation. - */ -#define EFUSE_XTS_DPA_PSEUDO_LEVEL 0x00000003U -#define EFUSE_XTS_DPA_PSEUDO_LEVEL_M (EFUSE_XTS_DPA_PSEUDO_LEVEL_V << EFUSE_XTS_DPA_PSEUDO_LEVEL_S) -#define EFUSE_XTS_DPA_PSEUDO_LEVEL_V 0x00000003U -#define EFUSE_XTS_DPA_PSEUDO_LEVEL_S 30 +/** EFUSE_RPT4_RESERVED0_2 : RO; bitpos: [28:27]; default: 0; + * Reserved. + */ +#define EFUSE_RPT4_RESERVED0_2 0x00000003U +#define EFUSE_RPT4_RESERVED0_2_M (EFUSE_RPT4_RESERVED0_2_V << EFUSE_RPT4_RESERVED0_2_S) +#define EFUSE_RPT4_RESERVED0_2_V 0x00000003U +#define EFUSE_RPT4_RESERVED0_2_S 27 +/** EFUSE_RPT4_RESERVED0_1 : RO; bitpos: [29]; default: 0; + * Reserved. + */ +#define EFUSE_RPT4_RESERVED0_1 (BIT(29)) +#define EFUSE_RPT4_RESERVED0_1_M (EFUSE_RPT4_RESERVED0_1_V << EFUSE_RPT4_RESERVED0_1_S) +#define EFUSE_RPT4_RESERVED0_1_V 0x00000001U +#define EFUSE_RPT4_RESERVED0_1_S 29 +/** EFUSE_RPT4_RESERVED0_0 : RO; bitpos: [31:30]; default: 0; + * Reserved. + */ +#define EFUSE_RPT4_RESERVED0_0 0x00000003U +#define EFUSE_RPT4_RESERVED0_0_M (EFUSE_RPT4_RESERVED0_0_V << EFUSE_RPT4_RESERVED0_0_S) +#define EFUSE_RPT4_RESERVED0_0_V 0x00000003U +#define EFUSE_RPT4_RESERVED0_0_S 30 /** EFUSE_RD_REPEAT_DATA1_REG register - * Represents rd_repeat_data + * BLOCK0 data register 2. */ #define EFUSE_RD_REPEAT_DATA1_REG (DR_REG_EFUSE_BASE + 0x34) -/** EFUSE_IO_LDO_ADJUST : RO; bitpos: [7:0]; default: 0; - * Represents configuration of IO LDO mode and voltage. - */ -#define EFUSE_IO_LDO_ADJUST 0x000000FFU -#define EFUSE_IO_LDO_ADJUST_M (EFUSE_IO_LDO_ADJUST_V << EFUSE_IO_LDO_ADJUST_S) -#define EFUSE_IO_LDO_ADJUST_V 0x000000FFU -#define EFUSE_IO_LDO_ADJUST_S 0 -/** EFUSE_VDD_SPI_LDO_ADJUST : RO; bitpos: [15:8]; default: 0; - * Represents configuration of FLASH LDO mode and voltage. - */ -#define EFUSE_VDD_SPI_LDO_ADJUST 0x000000FFU -#define EFUSE_VDD_SPI_LDO_ADJUST_M (EFUSE_VDD_SPI_LDO_ADJUST_V << EFUSE_VDD_SPI_LDO_ADJUST_S) -#define EFUSE_VDD_SPI_LDO_ADJUST_V 0x000000FFU -#define EFUSE_VDD_SPI_LDO_ADJUST_S 8 +/** EFUSE_RPT4_RESERVED1_1 : RO; bitpos: [15:0]; default: 0; + * Reserved. + */ +#define EFUSE_RPT4_RESERVED1_1 0x0000FFFFU +#define EFUSE_RPT4_RESERVED1_1_M (EFUSE_RPT4_RESERVED1_1_V << EFUSE_RPT4_RESERVED1_1_S) +#define EFUSE_RPT4_RESERVED1_1_V 0x0000FFFFU +#define EFUSE_RPT4_RESERVED1_1_S 0 /** EFUSE_WDT_DELAY_SEL : RO; bitpos: [17:16]; default: 0; - * Represents RTC watchdog timeout threshold. - * 0：The originally configured STG0 threshold × 2 - * 1：The originally configured STG0 threshold × 4 - * 2：The originally configured STG0 threshold × 8 - * 3：The originally configured STG0 threshold × 16 + * Represents whether RTC watchdog timeout threshold is selected at startup. 1: + * selected. 0: not selected. */ #define EFUSE_WDT_DELAY_SEL 0x00000003U #define EFUSE_WDT_DELAY_SEL_M (EFUSE_WDT_DELAY_SEL_V << EFUSE_WDT_DELAY_SEL_S) #define EFUSE_WDT_DELAY_SEL_V 0x00000003U #define EFUSE_WDT_DELAY_SEL_S 16 /** EFUSE_SPI_BOOT_CRYPT_CNT : RO; bitpos: [20:18]; default: 0; - * Represents whether SPI boot encryption/decryption is enabled. - * Odd count of bits with a value of 1: Enabled - * Even count of bits with a value of 1: Disabled + * Represents whether SPI boot encrypt/decrypt is disabled or enabled. Odd number of + * 1: enabled. Even number of 1: disabled. */ #define EFUSE_SPI_BOOT_CRYPT_CNT 0x00000007U #define EFUSE_SPI_BOOT_CRYPT_CNT_M (EFUSE_SPI_BOOT_CRYPT_CNT_V << EFUSE_SPI_BOOT_CRYPT_CNT_S) #define EFUSE_SPI_BOOT_CRYPT_CNT_V 0x00000007U #define EFUSE_SPI_BOOT_CRYPT_CNT_S 18 /** EFUSE_SECURE_BOOT_KEY_REVOKE0 : RO; bitpos: [21]; default: 0; - * Represents whether revoking Secure Boot key 0 is enabled. - * 1: Enabled - * 0: Disabled + * Represents whether revoking first secure boot key is enabled or disabled. 1: + * enabled. 0: disabled. */ #define EFUSE_SECURE_BOOT_KEY_REVOKE0 (BIT(21)) #define EFUSE_SECURE_BOOT_KEY_REVOKE0_M (EFUSE_SECURE_BOOT_KEY_REVOKE0_V << EFUSE_SECURE_BOOT_KEY_REVOKE0_S) #define EFUSE_SECURE_BOOT_KEY_REVOKE0_V 0x00000001U #define EFUSE_SECURE_BOOT_KEY_REVOKE0_S 21 /** EFUSE_SECURE_BOOT_KEY_REVOKE1 : RO; bitpos: [22]; default: 0; - * Represents whether revoking Secure Boot key 1 is enabled. - * 1: Enabled - * 0: Disabled + * Represents whether revoking second secure boot key is enabled or disabled. 1: + * enabled. 0: disabled. */ #define EFUSE_SECURE_BOOT_KEY_REVOKE1 (BIT(22)) #define EFUSE_SECURE_BOOT_KEY_REVOKE1_M (EFUSE_SECURE_BOOT_KEY_REVOKE1_V << EFUSE_SECURE_BOOT_KEY_REVOKE1_S) #define EFUSE_SECURE_BOOT_KEY_REVOKE1_V 0x00000001U #define EFUSE_SECURE_BOOT_KEY_REVOKE1_S 22 /** EFUSE_SECURE_BOOT_KEY_REVOKE2 : RO; bitpos: [23]; default: 0; - * Represents whether revoking Secure Boot key 2 is enabled. - * 1: Enabled - * 0: Disabled + * Represents whether revoking third secure boot key is enabled or disabled. 1: + * enabled. 0: disabled. */ #define EFUSE_SECURE_BOOT_KEY_REVOKE2 (BIT(23)) #define EFUSE_SECURE_BOOT_KEY_REVOKE2_M (EFUSE_SECURE_BOOT_KEY_REVOKE2_V << EFUSE_SECURE_BOOT_KEY_REVOKE2_S) #define EFUSE_SECURE_BOOT_KEY_REVOKE2_V 0x00000001U #define EFUSE_SECURE_BOOT_KEY_REVOKE2_S 23 /** EFUSE_KEY_PURPOSE_0 : RO; bitpos: [27:24]; default: 0; - * Represents the purpose of Key0. See Table tab:efuse-key-purpose. + * Represents the purpose of Key0. */ #define EFUSE_KEY_PURPOSE_0 0x0000000FU #define EFUSE_KEY_PURPOSE_0_M (EFUSE_KEY_PURPOSE_0_V << EFUSE_KEY_PURPOSE_0_S) #define EFUSE_KEY_PURPOSE_0_V 0x0000000FU #define EFUSE_KEY_PURPOSE_0_S 24 /** EFUSE_KEY_PURPOSE_1 : RO; bitpos: [31:28]; default: 0; - * Represents the purpose of Key1. See Table tab:efuse-key-purpose. + * Represents the purpose of Key1. */ #define EFUSE_KEY_PURPOSE_1 0x0000000FU #define EFUSE_KEY_PURPOSE_1_M (EFUSE_KEY_PURPOSE_1_V << EFUSE_KEY_PURPOSE_1_S) @@ -403,105 +378,85 @@ extern "C" { #define EFUSE_KEY_PURPOSE_1_S 28 /** EFUSE_RD_REPEAT_DATA2_REG register - * Represents rd_repeat_data + * BLOCK0 data register 3. */ #define EFUSE_RD_REPEAT_DATA2_REG (DR_REG_EFUSE_BASE + 0x38) /** EFUSE_KEY_PURPOSE_2 : RO; bitpos: [3:0]; default: 0; - * Represents the purpose of Key2. See Table tab:efuse-key-purpose. + * Represents the purpose of Key2. */ #define EFUSE_KEY_PURPOSE_2 0x0000000FU #define EFUSE_KEY_PURPOSE_2_M (EFUSE_KEY_PURPOSE_2_V << EFUSE_KEY_PURPOSE_2_S) #define EFUSE_KEY_PURPOSE_2_V 0x0000000FU #define EFUSE_KEY_PURPOSE_2_S 0 /** EFUSE_KEY_PURPOSE_3 : RO; bitpos: [7:4]; default: 0; - * Represents the purpose of Key3. See Table tab:efuse-key-purpose. + * Represents the purpose of Key3. */ #define EFUSE_KEY_PURPOSE_3 0x0000000FU #define EFUSE_KEY_PURPOSE_3_M (EFUSE_KEY_PURPOSE_3_V << EFUSE_KEY_PURPOSE_3_S) #define EFUSE_KEY_PURPOSE_3_V 0x0000000FU #define EFUSE_KEY_PURPOSE_3_S 4 /** EFUSE_KEY_PURPOSE_4 : RO; bitpos: [11:8]; default: 0; - * Represents the purpose of Key4. See Table tab:efuse-key-purpose. + * Represents the purpose of Key4. */ #define EFUSE_KEY_PURPOSE_4 0x0000000FU #define EFUSE_KEY_PURPOSE_4_M (EFUSE_KEY_PURPOSE_4_V << EFUSE_KEY_PURPOSE_4_S) #define EFUSE_KEY_PURPOSE_4_V 0x0000000FU #define EFUSE_KEY_PURPOSE_4_S 8 /** EFUSE_KEY_PURPOSE_5 : RO; bitpos: [15:12]; default: 0; - * Represents the purpose of Key5. See Table tab:efuse-key-purpose. + * Represents the purpose of Key5. */ #define EFUSE_KEY_PURPOSE_5 0x0000000FU #define EFUSE_KEY_PURPOSE_5_M (EFUSE_KEY_PURPOSE_5_V << EFUSE_KEY_PURPOSE_5_S) #define EFUSE_KEY_PURPOSE_5_V 0x0000000FU #define EFUSE_KEY_PURPOSE_5_S 12 /** EFUSE_SEC_DPA_LEVEL : RO; bitpos: [17:16]; default: 0; - * Represents the security level of anti-DPA attack. The level is adjusted by - * configuring the clock random frequency division mode. - * 0: Security level is SEC_DPA_OFF - * 1: Security level is SEC_DPA_LOW - * 2: Security level is SEC_DPA_MIDDLE - * 3: Security level is SEC_DPA_HIGH - * For more information, please refer to Chapter mod:sysreg > Section - * sec:sysreg-anti-dpa-attack-security-control. + * Represents the spa secure level by configuring the clock random divide mode. */ #define EFUSE_SEC_DPA_LEVEL 0x00000003U #define EFUSE_SEC_DPA_LEVEL_M (EFUSE_SEC_DPA_LEVEL_V << EFUSE_SEC_DPA_LEVEL_S) #define EFUSE_SEC_DPA_LEVEL_V 0x00000003U #define EFUSE_SEC_DPA_LEVEL_S 16 -/** EFUSE_IO_LDO_1P8 : RO; bitpos: [18]; default: 0; - * Represents select IO LDO voltage to 1.8V or 3.3V. - * 1: 1.8V - * 0: 3.3V - */ -#define EFUSE_IO_LDO_1P8 (BIT(18)) -#define EFUSE_IO_LDO_1P8_M (EFUSE_IO_LDO_1P8_V << EFUSE_IO_LDO_1P8_S) -#define EFUSE_IO_LDO_1P8_V 0x00000001U -#define EFUSE_IO_LDO_1P8_S 18 -/** EFUSE_CRYPT_DPA_ENABLE : RO; bitpos: [19]; default: 0; - * Represents whether defense against DPA attack is enabled. - * 1: Enabled - * 0: Disabled +/** EFUSE_ECDSA_FORCE_USE_HARDWARE_K : RO; bitpos: [18]; default: 1; + * Represents whether hardware random number k is forced used in ESDCA. 1: force used. + * 0: not force used. + */ +#define EFUSE_ECDSA_FORCE_USE_HARDWARE_K (BIT(18)) +#define EFUSE_ECDSA_FORCE_USE_HARDWARE_K_M (EFUSE_ECDSA_FORCE_USE_HARDWARE_K_V << EFUSE_ECDSA_FORCE_USE_HARDWARE_K_S) +#define EFUSE_ECDSA_FORCE_USE_HARDWARE_K_V 0x00000001U +#define EFUSE_ECDSA_FORCE_USE_HARDWARE_K_S 18 +/** EFUSE_CRYPT_DPA_ENABLE : RO; bitpos: [19]; default: 1; + * Represents whether anti-dpa attack is enabled. 1:enabled. 0: disabled. */ #define EFUSE_CRYPT_DPA_ENABLE (BIT(19)) #define EFUSE_CRYPT_DPA_ENABLE_M (EFUSE_CRYPT_DPA_ENABLE_V << EFUSE_CRYPT_DPA_ENABLE_S) #define EFUSE_CRYPT_DPA_ENABLE_V 0x00000001U #define EFUSE_CRYPT_DPA_ENABLE_S 19 /** EFUSE_SECURE_BOOT_EN : RO; bitpos: [20]; default: 0; - * Represents whether Secure Boot is enabled. - * 1: Enabled - * 0: Disabled + * Represents whether secure boot is enabled or disabled. 1: enabled. 0: disabled. */ #define EFUSE_SECURE_BOOT_EN (BIT(20)) #define EFUSE_SECURE_BOOT_EN_M (EFUSE_SECURE_BOOT_EN_V << EFUSE_SECURE_BOOT_EN_S) #define EFUSE_SECURE_BOOT_EN_V 0x00000001U #define EFUSE_SECURE_BOOT_EN_S 20 /** EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE : RO; bitpos: [21]; default: 0; - * Represents whether aggressive revocation of Secure Boot is enabled. - * 1: Enabled - * 0: Disabled + * Represents whether revoking aggressive secure boot is enabled or disabled. 1: + * enabled. 0: disabled. */ #define EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE (BIT(21)) #define EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_M (EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_V << EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_S) #define EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_V 0x00000001U #define EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_S 21 -/** EFUSE_POWERGLITCH_EN1 : RO; bitpos: [26:22]; default: 0; - * Represents whether to enable power glitch function when chip power on. - */ -#define EFUSE_POWERGLITCH_EN1 0x0000001FU -#define EFUSE_POWERGLITCH_EN1_M (EFUSE_POWERGLITCH_EN1_V << EFUSE_POWERGLITCH_EN1_S) -#define EFUSE_POWERGLITCH_EN1_V 0x0000001FU -#define EFUSE_POWERGLITCH_EN1_S 22 -/** EFUSE_DCDC_CCM_EN : RO; bitpos: [27]; default: 0; - * Represents whether change DCDC to CCM mode. - */ -#define EFUSE_DCDC_CCM_EN (BIT(27)) -#define EFUSE_DCDC_CCM_EN_M (EFUSE_DCDC_CCM_EN_V << EFUSE_DCDC_CCM_EN_S) -#define EFUSE_DCDC_CCM_EN_V 0x00000001U -#define EFUSE_DCDC_CCM_EN_S 27 +/** EFUSE_RPT4_RESERVED2_0 : RO; bitpos: [27:22]; default: 0; + * Reserved. + */ +#define EFUSE_RPT4_RESERVED2_0 0x0000003FU +#define EFUSE_RPT4_RESERVED2_0_M (EFUSE_RPT4_RESERVED2_0_V << EFUSE_RPT4_RESERVED2_0_S) +#define EFUSE_RPT4_RESERVED2_0_V 0x0000003FU +#define EFUSE_RPT4_RESERVED2_0_S 22 /** EFUSE_FLASH_TPUW : RO; bitpos: [31:28]; default: 0; - * Represents the flash waiting time after power-up. Measurement unit: ms. - * When the value is less than 15, the waiting time is the programmed value. - * Otherwise, the waiting time is a fixed value, i.e. 30 ms. + * Represents the flash waiting time after power-up, in unit of ms. When the value + * less than 15, the waiting time is the programmed value. Otherwise, the waiting time + * is 2 times the programmed value. */ #define EFUSE_FLASH_TPUW 0x0000000FU #define EFUSE_FLASH_TPUW_M (EFUSE_FLASH_TPUW_V << EFUSE_FLASH_TPUW_S) @@ -509,96 +464,87 @@ extern "C" { #define EFUSE_FLASH_TPUW_S 28 /** EFUSE_RD_REPEAT_DATA3_REG register - * Represents rd_repeat_data + * BLOCK0 data register 4. */ #define EFUSE_RD_REPEAT_DATA3_REG (DR_REG_EFUSE_BASE + 0x3c) /** EFUSE_DIS_DOWNLOAD_MODE : RO; bitpos: [0]; default: 0; - * Represents whether all download modes are disabled. - * 1: Disabled - * 0: Enabled + * Represents whether Download mode is disabled or enabled. 1: disabled. 0: enabled. */ #define EFUSE_DIS_DOWNLOAD_MODE (BIT(0)) #define EFUSE_DIS_DOWNLOAD_MODE_M (EFUSE_DIS_DOWNLOAD_MODE_V << EFUSE_DIS_DOWNLOAD_MODE_S) #define EFUSE_DIS_DOWNLOAD_MODE_V 0x00000001U #define EFUSE_DIS_DOWNLOAD_MODE_S 0 /** EFUSE_DIS_DIRECT_BOOT : RO; bitpos: [1]; default: 0; - * Represents whether direct boot mode is disabled. - * 1: Disabled - * 0: Enabled + * Represents whether direct boot mode is disabled or enabled. 1: disabled. 0: enabled. */ #define EFUSE_DIS_DIRECT_BOOT (BIT(1)) #define EFUSE_DIS_DIRECT_BOOT_M (EFUSE_DIS_DIRECT_BOOT_V << EFUSE_DIS_DIRECT_BOOT_S) #define EFUSE_DIS_DIRECT_BOOT_V 0x00000001U #define EFUSE_DIS_DIRECT_BOOT_S 1 /** EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT : RO; bitpos: [2]; default: 0; - * Represents whether print from USB-Serial-JTAG during ROM boot is disabled. - * 1: Disabled - * 0: Enabled + * Set this bit to disable USB-Serial-JTAG print during rom boot. */ #define EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT (BIT(2)) #define EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT_M (EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT_V << EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT_S) #define EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT_V 0x00000001U #define EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT_S 2 +/** EFUSE_RPT4_RESERVED3_5 : RO; bitpos: [3]; default: 0; + * Reserved. + */ +#define EFUSE_RPT4_RESERVED3_5 (BIT(3)) +#define EFUSE_RPT4_RESERVED3_5_M (EFUSE_RPT4_RESERVED3_5_V << EFUSE_RPT4_RESERVED3_5_S) +#define EFUSE_RPT4_RESERVED3_5_V 0x00000001U +#define EFUSE_RPT4_RESERVED3_5_S 3 /** EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE : RO; bitpos: [4]; default: 0; - * Represents whether the USB-Serial-JTAG download function is disabled. - * 1: Disabled - * 0: Enabled + * Represents whether the USB-Serial-JTAG download function is disabled or enabled. 1: + * disabled. 0: enabled. */ #define EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE (BIT(4)) #define EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE_M (EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE_V << EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE_S) #define EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE_V 0x00000001U #define EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE_S 4 /** EFUSE_ENABLE_SECURITY_DOWNLOAD : RO; bitpos: [5]; default: 0; - * Represents whether security download is enabled. Only UART is supported for - * download. Reading/writing RAM or registers is not supported (i.e. Stub download is - * not supported). - * 1: Enabled - * 0: Disabled + * Represents whether security download is enabled or disabled. 1: enabled. 0: + * disabled. */ #define EFUSE_ENABLE_SECURITY_DOWNLOAD (BIT(5)) #define EFUSE_ENABLE_SECURITY_DOWNLOAD_M (EFUSE_ENABLE_SECURITY_DOWNLOAD_V << EFUSE_ENABLE_SECURITY_DOWNLOAD_S) #define EFUSE_ENABLE_SECURITY_DOWNLOAD_V 0x00000001U #define EFUSE_ENABLE_SECURITY_DOWNLOAD_S 5 /** EFUSE_UART_PRINT_CONTROL : RO; bitpos: [7:6]; default: 0; - * Represents the type of UART printing. - * 0: Force enable printing. - * 1: Enable printing when GPIO8 is reset at low level. - * 2: Enable printing when GPIO8 is reset at high level. - * 3: Force disable printing. + * Represents the type of UART printing. 00: force enable printing. 01: enable + * printing when GPIO8 is reset at low level. 10: enable printing when GPIO8 is reset + * at high level. 11: force disable printing. */ #define EFUSE_UART_PRINT_CONTROL 0x00000003U #define EFUSE_UART_PRINT_CONTROL_M (EFUSE_UART_PRINT_CONTROL_V << EFUSE_UART_PRINT_CONTROL_S) #define EFUSE_UART_PRINT_CONTROL_V 0x00000003U #define EFUSE_UART_PRINT_CONTROL_S 6 /** EFUSE_FORCE_SEND_RESUME : RO; bitpos: [8]; default: 0; - * Represents whether ROM code is forced to send a resume command during SPI boot. - * 1: Forced - * 0: Not forced + * Represents whether ROM code is forced to send a resume command during SPI boot. 1: + * forced. 0:not forced. */ #define EFUSE_FORCE_SEND_RESUME (BIT(8)) #define EFUSE_FORCE_SEND_RESUME_M (EFUSE_FORCE_SEND_RESUME_V << EFUSE_FORCE_SEND_RESUME_S) #define EFUSE_FORCE_SEND_RESUME_V 0x00000001U #define EFUSE_FORCE_SEND_RESUME_S 8 /** EFUSE_SECURE_VERSION : RO; bitpos: [24:9]; default: 0; - * Represents the security version used by ESP-IDF anti-rollback feature. + * Represents the version used by ESP-IDF anti-rollback feature. */ #define EFUSE_SECURE_VERSION 0x0000FFFFU #define EFUSE_SECURE_VERSION_M (EFUSE_SECURE_VERSION_V << EFUSE_SECURE_VERSION_S) #define EFUSE_SECURE_VERSION_V 0x0000FFFFU #define EFUSE_SECURE_VERSION_S 9 /** EFUSE_SECURE_BOOT_DISABLE_FAST_WAKE : RO; bitpos: [25]; default: 0; - * Represents whether FAST VERIFY ON WAKE is disabled when Secure Boot is enabled. - * 1: Disabled - * 0: Enabled + * Represents whether FAST VERIFY ON WAKE is disabled or enabled when Secure Boot is + * enabled. 1: disabled. 0: enabled. */ #define EFUSE_SECURE_BOOT_DISABLE_FAST_WAKE (BIT(25)) #define EFUSE_SECURE_BOOT_DISABLE_FAST_WAKE_M (EFUSE_SECURE_BOOT_DISABLE_FAST_WAKE_V << EFUSE_SECURE_BOOT_DISABLE_FAST_WAKE_S) #define EFUSE_SECURE_BOOT_DISABLE_FAST_WAKE_V 0x00000001U #define EFUSE_SECURE_BOOT_DISABLE_FAST_WAKE_S 25 /** EFUSE_HYS_EN_PAD0 : RO; bitpos: [31:26]; default: 0; - * Represents whether to enable the hysteresis function of pad 0-5. - * 0: Disabled - * 1: Enabled + * Set bits to enable hysteresis function of PAD0~5 */ #define EFUSE_HYS_EN_PAD0 0x0000003FU #define EFUSE_HYS_EN_PAD0_M (EFUSE_HYS_EN_PAD0_V << EFUSE_HYS_EN_PAD0_S) @@ -606,267 +552,443 @@ extern "C" { #define EFUSE_HYS_EN_PAD0_S 26 /** EFUSE_RD_REPEAT_DATA4_REG register - * Represents rd_repeat_data + * BLOCK0 data register 5. */ #define EFUSE_RD_REPEAT_DATA4_REG (DR_REG_EFUSE_BASE + 0x40) /** EFUSE_HYS_EN_PAD1 : RO; bitpos: [21:0]; default: 0; - * Represents whether to enable the hysteresis function of pad 6-27. - * 0: Disabled - * 1: Enabled + * Set bits to enable hysteresis function of PAD6~27 */ #define EFUSE_HYS_EN_PAD1 0x003FFFFFU #define EFUSE_HYS_EN_PAD1_M (EFUSE_HYS_EN_PAD1_V << EFUSE_HYS_EN_PAD1_S) #define EFUSE_HYS_EN_PAD1_V 0x003FFFFFU #define EFUSE_HYS_EN_PAD1_S 0 -/** EFUSE_FLASH_LDO_POWER_SEL : RO; bitpos: [22]; default: 0; - * Represents which flash LDO is selected. - * 0: FLASH LDO 1P8. - * 1: FLASH LDO 1P2. +/** EFUSE_RPT4_RESERVED4_1 : RO; bitpos: [23:22]; default: 0; + * Reserved. */ -#define EFUSE_FLASH_LDO_POWER_SEL (BIT(22)) -#define EFUSE_FLASH_LDO_POWER_SEL_M (EFUSE_FLASH_LDO_POWER_SEL_V << EFUSE_FLASH_LDO_POWER_SEL_S) -#define EFUSE_FLASH_LDO_POWER_SEL_V 0x00000001U -#define EFUSE_FLASH_LDO_POWER_SEL_S 22 +#define EFUSE_RPT4_RESERVED4_1 0x00000003U +#define EFUSE_RPT4_RESERVED4_1_M (EFUSE_RPT4_RESERVED4_1_V << EFUSE_RPT4_RESERVED4_1_S) +#define EFUSE_RPT4_RESERVED4_1_V 0x00000003U +#define EFUSE_RPT4_RESERVED4_1_S 22 +/** EFUSE_RPT4_RESERVED4_0 : RO; bitpos: [31:24]; default: 0; + * Reserved. + */ +#define EFUSE_RPT4_RESERVED4_0 0x000000FFU +#define EFUSE_RPT4_RESERVED4_0_M (EFUSE_RPT4_RESERVED4_0_V << EFUSE_RPT4_RESERVED4_0_S) +#define EFUSE_RPT4_RESERVED4_0_V 0x000000FFU +#define EFUSE_RPT4_RESERVED4_0_S 24 -/** EFUSE_RD_MAC_SYS0_REG register - * Represents rd_mac_sys +/** EFUSE_RD_MAC_SYS_0_REG register + * BLOCK1 data register $n. */ -#define EFUSE_RD_MAC_SYS0_REG (DR_REG_EFUSE_BASE + 0x44) +#define EFUSE_RD_MAC_SYS_0_REG (DR_REG_EFUSE_BASE + 0x44) /** EFUSE_MAC_0 : RO; bitpos: [31:0]; default: 0; - * Represents MAC address. Low 32-bit. + * Stores the low 32 bits of MAC address. */ #define EFUSE_MAC_0 0xFFFFFFFFU #define EFUSE_MAC_0_M (EFUSE_MAC_0_V << EFUSE_MAC_0_S) #define EFUSE_MAC_0_V 0xFFFFFFFFU #define EFUSE_MAC_0_S 0 -/** EFUSE_RD_MAC_SYS1_REG register - * Represents rd_mac_sys +/** EFUSE_RD_MAC_SYS_1_REG register + * BLOCK1 data register $n. */ -#define EFUSE_RD_MAC_SYS1_REG (DR_REG_EFUSE_BASE + 0x48) +#define EFUSE_RD_MAC_SYS_1_REG (DR_REG_EFUSE_BASE + 0x48) /** EFUSE_MAC_1 : RO; bitpos: [15:0]; default: 0; - * Represents MAC address. High 16-bit. + * Stores the high 16 bits of MAC address. */ #define EFUSE_MAC_1 0x0000FFFFU #define EFUSE_MAC_1_M (EFUSE_MAC_1_V << EFUSE_MAC_1_S) #define EFUSE_MAC_1_V 0x0000FFFFU #define EFUSE_MAC_1_S 0 /** EFUSE_MAC_EXT : RO; bitpos: [31:16]; default: 0; - * Represents the extended bits of MAC address. + * Stores the extended bits of MAC address. */ #define EFUSE_MAC_EXT 0x0000FFFFU #define EFUSE_MAC_EXT_M (EFUSE_MAC_EXT_V << EFUSE_MAC_EXT_S) #define EFUSE_MAC_EXT_V 0x0000FFFFU #define EFUSE_MAC_EXT_S 16 -/** EFUSE_RD_MAC_SYS2_REG register - * Represents rd_mac_sys - */ -#define EFUSE_RD_MAC_SYS2_REG (DR_REG_EFUSE_BASE + 0x4c) -/** EFUSE_MAC_RESERVED_0 : RO; bitpos: [13:0]; default: 0; - * Reserved. - */ -#define EFUSE_MAC_RESERVED_0 0x00003FFFU -#define EFUSE_MAC_RESERVED_0_M (EFUSE_MAC_RESERVED_0_V << EFUSE_MAC_RESERVED_0_S) -#define EFUSE_MAC_RESERVED_0_V 0x00003FFFU -#define EFUSE_MAC_RESERVED_0_S 0 -/** EFUSE_MAC_RESERVED_1 : RO; bitpos: [31:14]; default: 0; - * Reserved. - */ -#define EFUSE_MAC_RESERVED_1 0x0003FFFFU -#define EFUSE_MAC_RESERVED_1_M (EFUSE_MAC_RESERVED_1_V << EFUSE_MAC_RESERVED_1_S) -#define EFUSE_MAC_RESERVED_1_V 0x0003FFFFU -#define EFUSE_MAC_RESERVED_1_S 14 - -/** EFUSE_RD_MAC_SYS3_REG register - * Represents rd_mac_sys - */ -#define EFUSE_RD_MAC_SYS3_REG (DR_REG_EFUSE_BASE + 0x50) -/** EFUSE_MAC_RESERVED_2 : RO; bitpos: [3:0]; default: 0; +/** EFUSE_RD_MAC_SYS_2_REG register + * BLOCK1 data register $n. + */ +#define EFUSE_RD_MAC_SYS_2_REG (DR_REG_EFUSE_BASE + 0x4c) +/** EFUSE_RXIQ_VERSION : RO; bitpos: [2:0]; default: 0; + * Stores RF Calibration data. RXIQ version. + */ +#define EFUSE_RXIQ_VERSION 0x00000007U +#define EFUSE_RXIQ_VERSION_M (EFUSE_RXIQ_VERSION_V << EFUSE_RXIQ_VERSION_S) +#define EFUSE_RXIQ_VERSION_V 0x00000007U +#define EFUSE_RXIQ_VERSION_S 0 +/** EFUSE_RXIQ_0 : RO; bitpos: [9:3]; default: 0; + * Stores RF Calibration data. RXIQ data 0. + */ +#define EFUSE_RXIQ_0 0x0000007FU +#define EFUSE_RXIQ_0_M (EFUSE_RXIQ_0_V << EFUSE_RXIQ_0_S) +#define EFUSE_RXIQ_0_V 0x0000007FU +#define EFUSE_RXIQ_0_S 3 +/** EFUSE_RXIQ_1 : RO; bitpos: [16:10]; default: 0; + * Stores RF Calibration data. RXIQ data 1. + */ +#define EFUSE_RXIQ_1 0x0000007FU +#define EFUSE_RXIQ_1_M (EFUSE_RXIQ_1_V << EFUSE_RXIQ_1_S) +#define EFUSE_RXIQ_1_V 0x0000007FU +#define EFUSE_RXIQ_1_S 10 +/** EFUSE_ACTIVE_HP_DBIAS : RO; bitpos: [21:17]; default: 0; + * Stores the PMU active hp dbias. + */ +#define EFUSE_ACTIVE_HP_DBIAS 0x0000001FU +#define EFUSE_ACTIVE_HP_DBIAS_M (EFUSE_ACTIVE_HP_DBIAS_V << EFUSE_ACTIVE_HP_DBIAS_S) +#define EFUSE_ACTIVE_HP_DBIAS_V 0x0000001FU +#define EFUSE_ACTIVE_HP_DBIAS_S 17 +/** EFUSE_ACTIVE_LP_DBIAS : RO; bitpos: [26:22]; default: 0; + * Stores the PMU active lp dbias. + */ +#define EFUSE_ACTIVE_LP_DBIAS 0x0000001FU +#define EFUSE_ACTIVE_LP_DBIAS_M (EFUSE_ACTIVE_LP_DBIAS_V << EFUSE_ACTIVE_LP_DBIAS_S) +#define EFUSE_ACTIVE_LP_DBIAS_V 0x0000001FU +#define EFUSE_ACTIVE_LP_DBIAS_S 22 +/** EFUSE_DSLP_DBIAS : RO; bitpos: [30:27]; default: 0; + * Stores the PMU sleep dbias. + */ +#define EFUSE_DSLP_DBIAS 0x0000000FU +#define EFUSE_DSLP_DBIAS_M (EFUSE_DSLP_DBIAS_V << EFUSE_DSLP_DBIAS_S) +#define EFUSE_DSLP_DBIAS_V 0x0000000FU +#define EFUSE_DSLP_DBIAS_S 27 +/** EFUSE_DBIAS_VOL_GAP_VALUE1 : RO; bitpos: [31]; default: 0; + * Stores the low 1 bit of dbias_vol_gap. + */ +#define EFUSE_DBIAS_VOL_GAP_VALUE1 (BIT(31)) +#define EFUSE_DBIAS_VOL_GAP_VALUE1_M (EFUSE_DBIAS_VOL_GAP_VALUE1_V << EFUSE_DBIAS_VOL_GAP_VALUE1_S) +#define EFUSE_DBIAS_VOL_GAP_VALUE1_V 0x00000001U +#define EFUSE_DBIAS_VOL_GAP_VALUE1_S 31 + +/** EFUSE_RD_MAC_SYS_3_REG register + * BLOCK1 data register $n. + */ +#define EFUSE_RD_MAC_SYS_3_REG (DR_REG_EFUSE_BASE + 0x50) +/** EFUSE_DBIAS_VOL_GAP_VALUE2 : RO; bitpos: [2:0]; default: 0; + * Stores the high 3 bits of dbias_vol_gap. + */ +#define EFUSE_DBIAS_VOL_GAP_VALUE2 0x00000007U +#define EFUSE_DBIAS_VOL_GAP_VALUE2_M (EFUSE_DBIAS_VOL_GAP_VALUE2_V << EFUSE_DBIAS_VOL_GAP_VALUE2_S) +#define EFUSE_DBIAS_VOL_GAP_VALUE2_V 0x00000007U +#define EFUSE_DBIAS_VOL_GAP_VALUE2_S 0 +/** EFUSE_DBIAS_VOL_GAP_SIGN : RO; bitpos: [3]; default: 0; + * Stores the sign bit of dbias_vol_gap. + */ +#define EFUSE_DBIAS_VOL_GAP_SIGN (BIT(3)) +#define EFUSE_DBIAS_VOL_GAP_SIGN_M (EFUSE_DBIAS_VOL_GAP_SIGN_V << EFUSE_DBIAS_VOL_GAP_SIGN_S) +#define EFUSE_DBIAS_VOL_GAP_SIGN_V 0x00000001U +#define EFUSE_DBIAS_VOL_GAP_SIGN_S 3 +/** EFUSE_MAC_RESERVED_2 : RO; bitpos: [17:4]; default: 0; * Reserved. */ -#define EFUSE_MAC_RESERVED_2 0x0000000FU +#define EFUSE_MAC_RESERVED_2 0x00003FFFU #define EFUSE_MAC_RESERVED_2_M (EFUSE_MAC_RESERVED_2_V << EFUSE_MAC_RESERVED_2_S) -#define EFUSE_MAC_RESERVED_2_V 0x0000000FU -#define EFUSE_MAC_RESERVED_2_S 0 -/** EFUSE_PVT_CELL_SELECT : RO; bitpos: [10:4]; default: 0; - * Represents the selection of Power glitch monitor PVT cell. - */ -#define EFUSE_PVT_CELL_SELECT 0x0000007FU -#define EFUSE_PVT_CELL_SELECT_M (EFUSE_PVT_CELL_SELECT_V << EFUSE_PVT_CELL_SELECT_S) -#define EFUSE_PVT_CELL_SELECT_V 0x0000007FU -#define EFUSE_PVT_CELL_SELECT_S 4 -/** EFUSE_MAC_RESERVED_3 : RO; bitpos: [17:11]; default: 0; - * Reserved. - */ -#define EFUSE_MAC_RESERVED_3 0x0000007FU -#define EFUSE_MAC_RESERVED_3_M (EFUSE_MAC_RESERVED_3_V << EFUSE_MAC_RESERVED_3_S) -#define EFUSE_MAC_RESERVED_3_V 0x0000007FU -#define EFUSE_MAC_RESERVED_3_S 11 -/** EFUSE_SYS_DATA_PART0_0 : RO; bitpos: [31:18]; default: 0; - * Represents the first 14-bit of zeroth part of system data. - */ -#define EFUSE_SYS_DATA_PART0_0 0x00003FFFU -#define EFUSE_SYS_DATA_PART0_0_M (EFUSE_SYS_DATA_PART0_0_V << EFUSE_SYS_DATA_PART0_0_S) -#define EFUSE_SYS_DATA_PART0_0_V 0x00003FFFU -#define EFUSE_SYS_DATA_PART0_0_S 18 - -/** EFUSE_RD_MAC_SYS4_REG register - * Represents rd_mac_sys - */ -#define EFUSE_RD_MAC_SYS4_REG (DR_REG_EFUSE_BASE + 0x54) -/** EFUSE_PVT_LIMIT : RO; bitpos: [20:5]; default: 0; - * Represents the threshold of power glitch monitor. - */ -#define EFUSE_PVT_LIMIT 0x0000FFFFU -#define EFUSE_PVT_LIMIT_M (EFUSE_PVT_LIMIT_V << EFUSE_PVT_LIMIT_S) -#define EFUSE_PVT_LIMIT_V 0x0000FFFFU -#define EFUSE_PVT_LIMIT_S 5 -/** EFUSE_PVT_GLITCH_CHARGE_RESET : RO; bitpos: [21]; default: 0; - * Represents whether to trigger reset or charge pump when PVT power glitch happened. - * 1:Trigger charge pump. - * 0:Trigger reset - */ -#define EFUSE_PVT_GLITCH_CHARGE_RESET (BIT(21)) -#define EFUSE_PVT_GLITCH_CHARGE_RESET_M (EFUSE_PVT_GLITCH_CHARGE_RESET_V << EFUSE_PVT_GLITCH_CHARGE_RESET_S) -#define EFUSE_PVT_GLITCH_CHARGE_RESET_V 0x00000001U -#define EFUSE_PVT_GLITCH_CHARGE_RESET_S 21 -/** EFUSE_PVT_GLITCH_MODE : RO; bitpos: [23:22]; default: 0; - * Represents the configuration of glitch mode. - */ -#define EFUSE_PVT_GLITCH_MODE 0x00000003U -#define EFUSE_PVT_GLITCH_MODE_M (EFUSE_PVT_GLITCH_MODE_V << EFUSE_PVT_GLITCH_MODE_S) -#define EFUSE_PVT_GLITCH_MODE_V 0x00000003U -#define EFUSE_PVT_GLITCH_MODE_S 22 -/** EFUSE_PVT_PUMP_LIMIT : RO; bitpos: [31:24]; default: 0; - * Represents the configuration voltage monitor limit for charge pump. - */ -#define EFUSE_PVT_PUMP_LIMIT 0x000000FFU -#define EFUSE_PVT_PUMP_LIMIT_M (EFUSE_PVT_PUMP_LIMIT_V << EFUSE_PVT_PUMP_LIMIT_S) -#define EFUSE_PVT_PUMP_LIMIT_V 0x000000FFU -#define EFUSE_PVT_PUMP_LIMIT_S 24 - -/** EFUSE_RD_MAC_SYS5_REG register - * Represents rd_mac_sys - */ -#define EFUSE_RD_MAC_SYS5_REG (DR_REG_EFUSE_BASE + 0x58) -/** EFUSE_PUMP_DRV : RO; bitpos: [3:0]; default: 0; - * Use to configure charge pump voltage gain. - */ -#define EFUSE_PUMP_DRV 0x0000000FU -#define EFUSE_PUMP_DRV_M (EFUSE_PUMP_DRV_V << EFUSE_PUMP_DRV_S) -#define EFUSE_PUMP_DRV_V 0x0000000FU -#define EFUSE_PUMP_DRV_S 0 -/** EFUSE_SYS_DATA_PART0_2 : RO; bitpos: [31:4]; default: 0; - * Represents the second 28-bit of zeroth part of system data. - */ -#define EFUSE_SYS_DATA_PART0_2 0x0FFFFFFFU +#define EFUSE_MAC_RESERVED_2_V 0x00003FFFU +#define EFUSE_MAC_RESERVED_2_S 4 +/** EFUSE_WAFER_VERSION_MINOR : RO; bitpos: [20:18]; default: 0; + * Stores the wafer version minor. + */ +#define EFUSE_WAFER_VERSION_MINOR 0x00000007U +#define EFUSE_WAFER_VERSION_MINOR_M (EFUSE_WAFER_VERSION_MINOR_V << EFUSE_WAFER_VERSION_MINOR_S) +#define EFUSE_WAFER_VERSION_MINOR_V 0x00000007U +#define EFUSE_WAFER_VERSION_MINOR_S 18 +/** EFUSE_WAFER_VERSION_MAJOR : RO; bitpos: [22:21]; default: 0; + * Stores the wafer version major. + */ +#define EFUSE_WAFER_VERSION_MAJOR 0x00000003U +#define EFUSE_WAFER_VERSION_MAJOR_M (EFUSE_WAFER_VERSION_MAJOR_V << EFUSE_WAFER_VERSION_MAJOR_S) +#define EFUSE_WAFER_VERSION_MAJOR_V 0x00000003U +#define EFUSE_WAFER_VERSION_MAJOR_S 21 +/** EFUSE_DISABLE_WAFER_VERSION_MAJOR : RO; bitpos: [23]; default: 0; + * Disables check of wafer version major. + */ +#define EFUSE_DISABLE_WAFER_VERSION_MAJOR (BIT(23)) +#define EFUSE_DISABLE_WAFER_VERSION_MAJOR_M (EFUSE_DISABLE_WAFER_VERSION_MAJOR_V << EFUSE_DISABLE_WAFER_VERSION_MAJOR_S) +#define EFUSE_DISABLE_WAFER_VERSION_MAJOR_V 0x00000001U +#define EFUSE_DISABLE_WAFER_VERSION_MAJOR_S 23 +/** EFUSE_FLASH_CAP : RO; bitpos: [26:24]; default: 0; + * Stores the flash cap. + */ +#define EFUSE_FLASH_CAP 0x00000007U +#define EFUSE_FLASH_CAP_M (EFUSE_FLASH_CAP_V << EFUSE_FLASH_CAP_S) +#define EFUSE_FLASH_CAP_V 0x00000007U +#define EFUSE_FLASH_CAP_S 24 +/** EFUSE_FLASH_TEMP : RO; bitpos: [28:27]; default: 0; + * Stores the flash temp. + */ +#define EFUSE_FLASH_TEMP 0x00000003U +#define EFUSE_FLASH_TEMP_M (EFUSE_FLASH_TEMP_V << EFUSE_FLASH_TEMP_S) +#define EFUSE_FLASH_TEMP_V 0x00000003U +#define EFUSE_FLASH_TEMP_S 27 +/** EFUSE_FLASH_VENDOR : RO; bitpos: [31:29]; default: 0; + * Stores the flash vendor. + */ +#define EFUSE_FLASH_VENDOR 0x00000007U +#define EFUSE_FLASH_VENDOR_M (EFUSE_FLASH_VENDOR_V << EFUSE_FLASH_VENDOR_S) +#define EFUSE_FLASH_VENDOR_V 0x00000007U +#define EFUSE_FLASH_VENDOR_S 29 + +/** EFUSE_RD_MAC_SYS_4_REG register + * BLOCK1 data register $n. + */ +#define EFUSE_RD_MAC_SYS_4_REG (DR_REG_EFUSE_BASE + 0x54) +/** EFUSE_PKG_VERSION : R; bitpos: [2:0]; default: 0; + * Package version + */ +#define EFUSE_PKG_VERSION 0x00000007U +#define EFUSE_PKG_VERSION_M (EFUSE_PKG_VERSION_V << EFUSE_PKG_VERSION_S) +#define EFUSE_PKG_VERSION_V 0x00000007U +#define EFUSE_PKG_VERSION_S 0 +/** EFUSE_RESERVED_1_131 : R; bitpos: [31:3]; default: 0; + * reserved + */ +#define EFUSE_RESERVED_1_131 0x1FFFFFFFU +#define EFUSE_RESERVED_1_131_M (EFUSE_RESERVED_1_131_V << EFUSE_RESERVED_1_131_S) +#define EFUSE_RESERVED_1_131_V 0x1FFFFFFFU +#define EFUSE_RESERVED_1_131_S 3 + +/** EFUSE_RD_MAC_SYS_5_REG register + * BLOCK1 data register $n. + */ +#define EFUSE_RD_MAC_SYS_5_REG (DR_REG_EFUSE_BASE + 0x58) +/** EFUSE_SYS_DATA_PART0_2 : RO; bitpos: [31:0]; default: 0; + * Stores the second 32 bits of the zeroth part of system data. + */ +#define EFUSE_SYS_DATA_PART0_2 0xFFFFFFFFU #define EFUSE_SYS_DATA_PART0_2_M (EFUSE_SYS_DATA_PART0_2_V << EFUSE_SYS_DATA_PART0_2_S) -#define EFUSE_SYS_DATA_PART0_2_V 0x0FFFFFFFU -#define EFUSE_SYS_DATA_PART0_2_S 4 +#define EFUSE_SYS_DATA_PART0_2_V 0xFFFFFFFFU +#define EFUSE_SYS_DATA_PART0_2_S 0 /** EFUSE_RD_SYS_PART1_DATA0_REG register - * Represents rd_sys_part1_data0 + * Register $n of BLOCK2 (system). */ #define EFUSE_RD_SYS_PART1_DATA0_REG (DR_REG_EFUSE_BASE + 0x5c) -/** EFUSE_SYS_DATA_PART1_0 : RO; bitpos: [31:0]; default: 0; - * Represents the zeroth 32-bit of first part of system data. +/** EFUSE_OPTIONAL_UNIQUE_ID : R; bitpos: [31:0]; default: 0; + * Optional unique 128-bit ID */ -#define EFUSE_SYS_DATA_PART1_0 0xFFFFFFFFU -#define EFUSE_SYS_DATA_PART1_0_M (EFUSE_SYS_DATA_PART1_0_V << EFUSE_SYS_DATA_PART1_0_S) -#define EFUSE_SYS_DATA_PART1_0_V 0xFFFFFFFFU -#define EFUSE_SYS_DATA_PART1_0_S 0 +#define EFUSE_OPTIONAL_UNIQUE_ID 0xFFFFFFFFU +#define EFUSE_OPTIONAL_UNIQUE_ID_M (EFUSE_OPTIONAL_UNIQUE_ID_V << EFUSE_OPTIONAL_UNIQUE_ID_S) +#define EFUSE_OPTIONAL_UNIQUE_ID_V 0xFFFFFFFFU +#define EFUSE_OPTIONAL_UNIQUE_ID_S 0 /** EFUSE_RD_SYS_PART1_DATA1_REG register - * Represents rd_sys_part1_data1 + * Register $n of BLOCK2 (system). */ #define EFUSE_RD_SYS_PART1_DATA1_REG (DR_REG_EFUSE_BASE + 0x60) -/** EFUSE_SYS_DATA_PART1_1 : RO; bitpos: [31:0]; default: 0; - * Represents the zeroth 32-bit of first part of system data. +/** EFUSE_OPTIONAL_UNIQUE_ID_1 : R; bitpos: [31:0]; default: 0; + * Optional unique 128-bit ID */ -#define EFUSE_SYS_DATA_PART1_1 0xFFFFFFFFU -#define EFUSE_SYS_DATA_PART1_1_M (EFUSE_SYS_DATA_PART1_1_V << EFUSE_SYS_DATA_PART1_1_S) -#define EFUSE_SYS_DATA_PART1_1_V 0xFFFFFFFFU -#define EFUSE_SYS_DATA_PART1_1_S 0 +#define EFUSE_OPTIONAL_UNIQUE_ID_1 0xFFFFFFFFU +#define EFUSE_OPTIONAL_UNIQUE_ID_1_M (EFUSE_OPTIONAL_UNIQUE_ID_1_V << EFUSE_OPTIONAL_UNIQUE_ID_1_S) +#define EFUSE_OPTIONAL_UNIQUE_ID_1_V 0xFFFFFFFFU +#define EFUSE_OPTIONAL_UNIQUE_ID_1_S 0 /** EFUSE_RD_SYS_PART1_DATA2_REG register - * Represents rd_sys_part1_data2 + * Register $n of BLOCK2 (system). */ #define EFUSE_RD_SYS_PART1_DATA2_REG (DR_REG_EFUSE_BASE + 0x64) -/** EFUSE_SYS_DATA_PART1_2 : RO; bitpos: [31:0]; default: 0; - * Represents the zeroth 32-bit of first part of system data. +/** EFUSE_OPTIONAL_UNIQUE_ID_2 : R; bitpos: [31:0]; default: 0; + * Optional unique 128-bit ID */ -#define EFUSE_SYS_DATA_PART1_2 0xFFFFFFFFU -#define EFUSE_SYS_DATA_PART1_2_M (EFUSE_SYS_DATA_PART1_2_V << EFUSE_SYS_DATA_PART1_2_S) -#define EFUSE_SYS_DATA_PART1_2_V 0xFFFFFFFFU -#define EFUSE_SYS_DATA_PART1_2_S 0 +#define EFUSE_OPTIONAL_UNIQUE_ID_2 0xFFFFFFFFU +#define EFUSE_OPTIONAL_UNIQUE_ID_2_M (EFUSE_OPTIONAL_UNIQUE_ID_2_V << EFUSE_OPTIONAL_UNIQUE_ID_2_S) +#define EFUSE_OPTIONAL_UNIQUE_ID_2_V 0xFFFFFFFFU +#define EFUSE_OPTIONAL_UNIQUE_ID_2_S 0 /** EFUSE_RD_SYS_PART1_DATA3_REG register - * Represents rd_sys_part1_data3 + * Register $n of BLOCK2 (system). */ #define EFUSE_RD_SYS_PART1_DATA3_REG (DR_REG_EFUSE_BASE + 0x68) -/** EFUSE_SYS_DATA_PART1_3 : RO; bitpos: [31:0]; default: 0; - * Represents the zeroth 32-bit of first part of system data. +/** EFUSE_OPTIONAL_UNIQUE_ID_3 : R; bitpos: [31:0]; default: 0; + * Optional unique 128-bit ID */ -#define EFUSE_SYS_DATA_PART1_3 0xFFFFFFFFU -#define EFUSE_SYS_DATA_PART1_3_M (EFUSE_SYS_DATA_PART1_3_V << EFUSE_SYS_DATA_PART1_3_S) -#define EFUSE_SYS_DATA_PART1_3_V 0xFFFFFFFFU -#define EFUSE_SYS_DATA_PART1_3_S 0 +#define EFUSE_OPTIONAL_UNIQUE_ID_3 0xFFFFFFFFU +#define EFUSE_OPTIONAL_UNIQUE_ID_3_M (EFUSE_OPTIONAL_UNIQUE_ID_3_V << EFUSE_OPTIONAL_UNIQUE_ID_3_S) +#define EFUSE_OPTIONAL_UNIQUE_ID_3_V 0xFFFFFFFFU +#define EFUSE_OPTIONAL_UNIQUE_ID_3_S 0 /** EFUSE_RD_SYS_PART1_DATA4_REG register - * Represents rd_sys_part1_data4 + * Register $n of BLOCK2 (system). */ #define EFUSE_RD_SYS_PART1_DATA4_REG (DR_REG_EFUSE_BASE + 0x6c) -/** EFUSE_SYS_DATA_PART1_4 : RO; bitpos: [31:0]; default: 0; - * Represents the zeroth 32-bit of first part of system data. - */ -#define EFUSE_SYS_DATA_PART1_4 0xFFFFFFFFU -#define EFUSE_SYS_DATA_PART1_4_M (EFUSE_SYS_DATA_PART1_4_V << EFUSE_SYS_DATA_PART1_4_S) -#define EFUSE_SYS_DATA_PART1_4_V 0xFFFFFFFFU -#define EFUSE_SYS_DATA_PART1_4_S 0 +/** EFUSE_RESERVED_2_128 : R; bitpos: [1:0]; default: 0; + * reserved + */ +#define EFUSE_RESERVED_2_128 0x00000003U +#define EFUSE_RESERVED_2_128_M (EFUSE_RESERVED_2_128_V << EFUSE_RESERVED_2_128_S) +#define EFUSE_RESERVED_2_128_V 0x00000003U +#define EFUSE_RESERVED_2_128_S 0 +/** EFUSE_BLK_VERSION_MINOR : R; bitpos: [4:2]; default: 0; + * BLK_VERSION_MINOR of BLOCK2. 1: RF Calibration data in BLOCK1 + */ +#define EFUSE_BLK_VERSION_MINOR 0x00000007U +#define EFUSE_BLK_VERSION_MINOR_M (EFUSE_BLK_VERSION_MINOR_V << EFUSE_BLK_VERSION_MINOR_S) +#define EFUSE_BLK_VERSION_MINOR_V 0x00000007U +#define EFUSE_BLK_VERSION_MINOR_S 2 +/** EFUSE_BLK_VERSION_MAJOR : R; bitpos: [6:5]; default: 0; + * BLK_VERSION_MAJOR of BLOCK2 + */ +#define EFUSE_BLK_VERSION_MAJOR 0x00000003U +#define EFUSE_BLK_VERSION_MAJOR_M (EFUSE_BLK_VERSION_MAJOR_V << EFUSE_BLK_VERSION_MAJOR_S) +#define EFUSE_BLK_VERSION_MAJOR_V 0x00000003U +#define EFUSE_BLK_VERSION_MAJOR_S 5 +/** EFUSE_DISABLE_BLK_VERSION_MAJOR : R; bitpos: [7]; default: 0; + * Disables check of blk version major + */ +#define EFUSE_DISABLE_BLK_VERSION_MAJOR (BIT(7)) +#define EFUSE_DISABLE_BLK_VERSION_MAJOR_M (EFUSE_DISABLE_BLK_VERSION_MAJOR_V << EFUSE_DISABLE_BLK_VERSION_MAJOR_S) +#define EFUSE_DISABLE_BLK_VERSION_MAJOR_V 0x00000001U +#define EFUSE_DISABLE_BLK_VERSION_MAJOR_S 7 +/** EFUSE_TEMP_CALIB : R; bitpos: [16:8]; default: 0; + * Temperature calibration data + */ +#define EFUSE_TEMP_CALIB 0x000001FFU +#define EFUSE_TEMP_CALIB_M (EFUSE_TEMP_CALIB_V << EFUSE_TEMP_CALIB_S) +#define EFUSE_TEMP_CALIB_V 0x000001FFU +#define EFUSE_TEMP_CALIB_S 8 +/** EFUSE_ADC1_AVE_INITCODE_ATTEN0 : R; bitpos: [26:17]; default: 0; + * ADC1 calibration data + */ +#define EFUSE_ADC1_AVE_INITCODE_ATTEN0 0x000003FFU +#define EFUSE_ADC1_AVE_INITCODE_ATTEN0_M (EFUSE_ADC1_AVE_INITCODE_ATTEN0_V << EFUSE_ADC1_AVE_INITCODE_ATTEN0_S) +#define EFUSE_ADC1_AVE_INITCODE_ATTEN0_V 0x000003FFU +#define EFUSE_ADC1_AVE_INITCODE_ATTEN0_S 17 +/** EFUSE_ADC1_AVE_INITCODE_ATTEN1 : R; bitpos: [31:27]; default: 0; + * ADC1 calibration data + */ +#define EFUSE_ADC1_AVE_INITCODE_ATTEN1 0x0000001FU +#define EFUSE_ADC1_AVE_INITCODE_ATTEN1_M (EFUSE_ADC1_AVE_INITCODE_ATTEN1_V << EFUSE_ADC1_AVE_INITCODE_ATTEN1_S) +#define EFUSE_ADC1_AVE_INITCODE_ATTEN1_V 0x0000001FU +#define EFUSE_ADC1_AVE_INITCODE_ATTEN1_S 27 /** EFUSE_RD_SYS_PART1_DATA5_REG register - * Represents rd_sys_part1_data5 + * Register $n of BLOCK2 (system). */ #define EFUSE_RD_SYS_PART1_DATA5_REG (DR_REG_EFUSE_BASE + 0x70) -/** EFUSE_SYS_DATA_PART1_5 : RO; bitpos: [31:0]; default: 0; - * Represents the zeroth 32-bit of first part of system data. - */ -#define EFUSE_SYS_DATA_PART1_5 0xFFFFFFFFU -#define EFUSE_SYS_DATA_PART1_5_M (EFUSE_SYS_DATA_PART1_5_V << EFUSE_SYS_DATA_PART1_5_S) -#define EFUSE_SYS_DATA_PART1_5_V 0xFFFFFFFFU -#define EFUSE_SYS_DATA_PART1_5_S 0 +/** EFUSE_ADC1_AVE_INITCODE_ATTEN1_1 : R; bitpos: [4:0]; default: 0; + * ADC1 calibration data + */ +#define EFUSE_ADC1_AVE_INITCODE_ATTEN1_1 0x0000001FU +#define EFUSE_ADC1_AVE_INITCODE_ATTEN1_1_M (EFUSE_ADC1_AVE_INITCODE_ATTEN1_1_V << EFUSE_ADC1_AVE_INITCODE_ATTEN1_1_S) +#define EFUSE_ADC1_AVE_INITCODE_ATTEN1_1_V 0x0000001FU +#define EFUSE_ADC1_AVE_INITCODE_ATTEN1_1_S 0 +/** EFUSE_ADC1_AVE_INITCODE_ATTEN2 : R; bitpos: [14:5]; default: 0; + * ADC1 calibration data + */ +#define EFUSE_ADC1_AVE_INITCODE_ATTEN2 0x000003FFU +#define EFUSE_ADC1_AVE_INITCODE_ATTEN2_M (EFUSE_ADC1_AVE_INITCODE_ATTEN2_V << EFUSE_ADC1_AVE_INITCODE_ATTEN2_S) +#define EFUSE_ADC1_AVE_INITCODE_ATTEN2_V 0x000003FFU +#define EFUSE_ADC1_AVE_INITCODE_ATTEN2_S 5 +/** EFUSE_ADC1_AVE_INITCODE_ATTEN3 : R; bitpos: [24:15]; default: 0; + * ADC1 calibration data + */ +#define EFUSE_ADC1_AVE_INITCODE_ATTEN3 0x000003FFU +#define EFUSE_ADC1_AVE_INITCODE_ATTEN3_M (EFUSE_ADC1_AVE_INITCODE_ATTEN3_V << EFUSE_ADC1_AVE_INITCODE_ATTEN3_S) +#define EFUSE_ADC1_AVE_INITCODE_ATTEN3_V 0x000003FFU +#define EFUSE_ADC1_AVE_INITCODE_ATTEN3_S 15 +/** EFUSE_ADC1_HI_DOUT_ATTEN0 : R; bitpos: [31:25]; default: 0; + * ADC1 calibration data + */ +#define EFUSE_ADC1_HI_DOUT_ATTEN0 0x0000007FU +#define EFUSE_ADC1_HI_DOUT_ATTEN0_M (EFUSE_ADC1_HI_DOUT_ATTEN0_V << EFUSE_ADC1_HI_DOUT_ATTEN0_S) +#define EFUSE_ADC1_HI_DOUT_ATTEN0_V 0x0000007FU +#define EFUSE_ADC1_HI_DOUT_ATTEN0_S 25 /** EFUSE_RD_SYS_PART1_DATA6_REG register - * Represents rd_sys_part1_data6 + * Register $n of BLOCK2 (system). */ #define EFUSE_RD_SYS_PART1_DATA6_REG (DR_REG_EFUSE_BASE + 0x74) -/** EFUSE_SYS_DATA_PART1_6 : RO; bitpos: [31:0]; default: 0; - * Represents the zeroth 32-bit of first part of system data. - */ -#define EFUSE_SYS_DATA_PART1_6 0xFFFFFFFFU -#define EFUSE_SYS_DATA_PART1_6_M (EFUSE_SYS_DATA_PART1_6_V << EFUSE_SYS_DATA_PART1_6_S) -#define EFUSE_SYS_DATA_PART1_6_V 0xFFFFFFFFU -#define EFUSE_SYS_DATA_PART1_6_S 0 +/** EFUSE_ADC1_HI_DOUT_ATTEN0_1 : R; bitpos: [2:0]; default: 0; + * ADC1 calibration data + */ +#define EFUSE_ADC1_HI_DOUT_ATTEN0_1 0x00000007U +#define EFUSE_ADC1_HI_DOUT_ATTEN0_1_M (EFUSE_ADC1_HI_DOUT_ATTEN0_1_V << EFUSE_ADC1_HI_DOUT_ATTEN0_1_S) +#define EFUSE_ADC1_HI_DOUT_ATTEN0_1_V 0x00000007U +#define EFUSE_ADC1_HI_DOUT_ATTEN0_1_S 0 +/** EFUSE_ADC1_HI_DOUT_ATTEN1 : R; bitpos: [12:3]; default: 0; + * ADC1 calibration data + */ +#define EFUSE_ADC1_HI_DOUT_ATTEN1 0x000003FFU +#define EFUSE_ADC1_HI_DOUT_ATTEN1_M (EFUSE_ADC1_HI_DOUT_ATTEN1_V << EFUSE_ADC1_HI_DOUT_ATTEN1_S) +#define EFUSE_ADC1_HI_DOUT_ATTEN1_V 0x000003FFU +#define EFUSE_ADC1_HI_DOUT_ATTEN1_S 3 +/** EFUSE_ADC1_HI_DOUT_ATTEN2 : R; bitpos: [22:13]; default: 0; + * ADC1 calibration data + */ +#define EFUSE_ADC1_HI_DOUT_ATTEN2 0x000003FFU +#define EFUSE_ADC1_HI_DOUT_ATTEN2_M (EFUSE_ADC1_HI_DOUT_ATTEN2_V << EFUSE_ADC1_HI_DOUT_ATTEN2_S) +#define EFUSE_ADC1_HI_DOUT_ATTEN2_V 0x000003FFU +#define EFUSE_ADC1_HI_DOUT_ATTEN2_S 13 +/** EFUSE_ADC1_HI_DOUT_ATTEN3 : R; bitpos: [31:23]; default: 0; + * ADC1 calibration data + */ +#define EFUSE_ADC1_HI_DOUT_ATTEN3 0x000001FFU +#define EFUSE_ADC1_HI_DOUT_ATTEN3_M (EFUSE_ADC1_HI_DOUT_ATTEN3_V << EFUSE_ADC1_HI_DOUT_ATTEN3_S) +#define EFUSE_ADC1_HI_DOUT_ATTEN3_V 0x000001FFU +#define EFUSE_ADC1_HI_DOUT_ATTEN3_S 23 /** EFUSE_RD_SYS_PART1_DATA7_REG register - * Represents rd_sys_part1_data7 + * Register $n of BLOCK2 (system). */ #define EFUSE_RD_SYS_PART1_DATA7_REG (DR_REG_EFUSE_BASE + 0x78) -/** EFUSE_SYS_DATA_PART1_7 : RO; bitpos: [31:0]; default: 0; - * Represents the zeroth 32-bit of first part of system data. - */ -#define EFUSE_SYS_DATA_PART1_7 0xFFFFFFFFU -#define EFUSE_SYS_DATA_PART1_7_M (EFUSE_SYS_DATA_PART1_7_V << EFUSE_SYS_DATA_PART1_7_S) -#define EFUSE_SYS_DATA_PART1_7_V 0xFFFFFFFFU -#define EFUSE_SYS_DATA_PART1_7_S 0 +/** EFUSE_ADC1_HI_DOUT_ATTEN3_1 : R; bitpos: [0]; default: 0; + * ADC1 calibration data + */ +#define EFUSE_ADC1_HI_DOUT_ATTEN3_1 (BIT(0)) +#define EFUSE_ADC1_HI_DOUT_ATTEN3_1_M (EFUSE_ADC1_HI_DOUT_ATTEN3_1_V << EFUSE_ADC1_HI_DOUT_ATTEN3_1_S) +#define EFUSE_ADC1_HI_DOUT_ATTEN3_1_V 0x00000001U +#define EFUSE_ADC1_HI_DOUT_ATTEN3_1_S 0 +/** EFUSE_ADC1_CH0_ATTEN0_INITCODE_DIFF : R; bitpos: [4:1]; default: 0; + * ADC1 calibration data + */ +#define EFUSE_ADC1_CH0_ATTEN0_INITCODE_DIFF 0x0000000FU +#define EFUSE_ADC1_CH0_ATTEN0_INITCODE_DIFF_M (EFUSE_ADC1_CH0_ATTEN0_INITCODE_DIFF_V << EFUSE_ADC1_CH0_ATTEN0_INITCODE_DIFF_S) +#define EFUSE_ADC1_CH0_ATTEN0_INITCODE_DIFF_V 0x0000000FU +#define EFUSE_ADC1_CH0_ATTEN0_INITCODE_DIFF_S 1 +/** EFUSE_ADC1_CH1_ATTEN0_INITCODE_DIFF : R; bitpos: [8:5]; default: 0; + * ADC1 calibration data + */ +#define EFUSE_ADC1_CH1_ATTEN0_INITCODE_DIFF 0x0000000FU +#define EFUSE_ADC1_CH1_ATTEN0_INITCODE_DIFF_M (EFUSE_ADC1_CH1_ATTEN0_INITCODE_DIFF_V << EFUSE_ADC1_CH1_ATTEN0_INITCODE_DIFF_S) +#define EFUSE_ADC1_CH1_ATTEN0_INITCODE_DIFF_V 0x0000000FU +#define EFUSE_ADC1_CH1_ATTEN0_INITCODE_DIFF_S 5 +/** EFUSE_ADC1_CH2_ATTEN0_INITCODE_DIFF : R; bitpos: [12:9]; default: 0; + * ADC1 calibration data + */ +#define EFUSE_ADC1_CH2_ATTEN0_INITCODE_DIFF 0x0000000FU +#define EFUSE_ADC1_CH2_ATTEN0_INITCODE_DIFF_M (EFUSE_ADC1_CH2_ATTEN0_INITCODE_DIFF_V << EFUSE_ADC1_CH2_ATTEN0_INITCODE_DIFF_S) +#define EFUSE_ADC1_CH2_ATTEN0_INITCODE_DIFF_V 0x0000000FU +#define EFUSE_ADC1_CH2_ATTEN0_INITCODE_DIFF_S 9 +/** EFUSE_ADC1_CH3_ATTEN0_INITCODE_DIFF : R; bitpos: [16:13]; default: 0; + * ADC1 calibration data + */ +#define EFUSE_ADC1_CH3_ATTEN0_INITCODE_DIFF 0x0000000FU +#define EFUSE_ADC1_CH3_ATTEN0_INITCODE_DIFF_M (EFUSE_ADC1_CH3_ATTEN0_INITCODE_DIFF_V << EFUSE_ADC1_CH3_ATTEN0_INITCODE_DIFF_S) +#define EFUSE_ADC1_CH3_ATTEN0_INITCODE_DIFF_V 0x0000000FU +#define EFUSE_ADC1_CH3_ATTEN0_INITCODE_DIFF_S 13 +/** EFUSE_ADC1_CH4_ATTEN0_INITCODE_DIFF : R; bitpos: [20:17]; default: 0; + * ADC1 calibration data + */ +#define EFUSE_ADC1_CH4_ATTEN0_INITCODE_DIFF 0x0000000FU +#define EFUSE_ADC1_CH4_ATTEN0_INITCODE_DIFF_M (EFUSE_ADC1_CH4_ATTEN0_INITCODE_DIFF_V << EFUSE_ADC1_CH4_ATTEN0_INITCODE_DIFF_S) +#define EFUSE_ADC1_CH4_ATTEN0_INITCODE_DIFF_V 0x0000000FU +#define EFUSE_ADC1_CH4_ATTEN0_INITCODE_DIFF_S 17 +/** EFUSE_RESERVED_2_245 : R; bitpos: [31:21]; default: 0; + * reserved + */ +#define EFUSE_RESERVED_2_245 0x000007FFU +#define EFUSE_RESERVED_2_245_M (EFUSE_RESERVED_2_245_V << EFUSE_RESERVED_2_245_S) +#define EFUSE_RESERVED_2_245_V 0x000007FFU +#define EFUSE_RESERVED_2_245_S 21 /** EFUSE_RD_USR_DATA0_REG register - * Represents rd_usr_data0 + * Register $n of BLOCK3 (user). */ #define EFUSE_RD_USR_DATA0_REG (DR_REG_EFUSE_BASE + 0x7c) /** EFUSE_USR_DATA0 : RO; bitpos: [31:0]; default: 0; - * Represents the zeroth 32-bit of block3 (user). + * Stores the zeroth 32 bits of BLOCK3 (user). */ #define EFUSE_USR_DATA0 0xFFFFFFFFU #define EFUSE_USR_DATA0_M (EFUSE_USR_DATA0_V << EFUSE_USR_DATA0_S) @@ -874,11 +996,11 @@ extern "C" { #define EFUSE_USR_DATA0_S 0 /** EFUSE_RD_USR_DATA1_REG register - * Represents rd_usr_data1 + * Register $n of BLOCK3 (user). */ #define EFUSE_RD_USR_DATA1_REG (DR_REG_EFUSE_BASE + 0x80) /** EFUSE_USR_DATA1 : RO; bitpos: [31:0]; default: 0; - * Represents the zeroth 32-bit of block3 (user). + * Stores the first 32 bits of BLOCK3 (user). */ #define EFUSE_USR_DATA1 0xFFFFFFFFU #define EFUSE_USR_DATA1_M (EFUSE_USR_DATA1_V << EFUSE_USR_DATA1_S) @@ -886,11 +1008,11 @@ extern "C" { #define EFUSE_USR_DATA1_S 0 /** EFUSE_RD_USR_DATA2_REG register - * Represents rd_usr_data2 + * Register $n of BLOCK3 (user). */ #define EFUSE_RD_USR_DATA2_REG (DR_REG_EFUSE_BASE + 0x84) /** EFUSE_USR_DATA2 : RO; bitpos: [31:0]; default: 0; - * Represents the zeroth 32-bit of block3 (user). + * Stores the second 32 bits of BLOCK3 (user). */ #define EFUSE_USR_DATA2 0xFFFFFFFFU #define EFUSE_USR_DATA2_M (EFUSE_USR_DATA2_V << EFUSE_USR_DATA2_S) @@ -898,11 +1020,11 @@ extern "C" { #define EFUSE_USR_DATA2_S 0 /** EFUSE_RD_USR_DATA3_REG register - * Represents rd_usr_data3 + * Register $n of BLOCK3 (user). */ #define EFUSE_RD_USR_DATA3_REG (DR_REG_EFUSE_BASE + 0x88) /** EFUSE_USR_DATA3 : RO; bitpos: [31:0]; default: 0; - * Represents the zeroth 32-bit of block3 (user). + * Stores the third 32 bits of BLOCK3 (user). */ #define EFUSE_USR_DATA3 0xFFFFFFFFU #define EFUSE_USR_DATA3_M (EFUSE_USR_DATA3_V << EFUSE_USR_DATA3_S) @@ -910,11 +1032,11 @@ extern "C" { #define EFUSE_USR_DATA3_S 0 /** EFUSE_RD_USR_DATA4_REG register - * Represents rd_usr_data4 + * Register $n of BLOCK3 (user). */ #define EFUSE_RD_USR_DATA4_REG (DR_REG_EFUSE_BASE + 0x8c) /** EFUSE_USR_DATA4 : RO; bitpos: [31:0]; default: 0; - * Represents the zeroth 32-bit of block3 (user). + * Stores the fourth 32 bits of BLOCK3 (user). */ #define EFUSE_USR_DATA4 0xFFFFFFFFU #define EFUSE_USR_DATA4_M (EFUSE_USR_DATA4_V << EFUSE_USR_DATA4_S) @@ -922,11 +1044,11 @@ extern "C" { #define EFUSE_USR_DATA4_S 0 /** EFUSE_RD_USR_DATA5_REG register - * Represents rd_usr_data5 + * Register $n of BLOCK3 (user). */ #define EFUSE_RD_USR_DATA5_REG (DR_REG_EFUSE_BASE + 0x90) /** EFUSE_USR_DATA5 : RO; bitpos: [31:0]; default: 0; - * Represents the zeroth 32-bit of block3 (user). + * Stores the fifth 32 bits of BLOCK3 (user). */ #define EFUSE_USR_DATA5 0xFFFFFFFFU #define EFUSE_USR_DATA5_M (EFUSE_USR_DATA5_V << EFUSE_USR_DATA5_S) @@ -934,35 +1056,49 @@ extern "C" { #define EFUSE_USR_DATA5_S 0 /** EFUSE_RD_USR_DATA6_REG register - * Represents rd_usr_data6 + * Register $n of BLOCK3 (user). */ #define EFUSE_RD_USR_DATA6_REG (DR_REG_EFUSE_BASE + 0x94) -/** EFUSE_USR_DATA6 : RO; bitpos: [31:0]; default: 0; - * Represents the zeroth 32-bit of block3 (user). +/** EFUSE_RESERVED_3_192 : R; bitpos: [7:0]; default: 0; + * reserved + */ +#define EFUSE_RESERVED_3_192 0x000000FFU +#define EFUSE_RESERVED_3_192_M (EFUSE_RESERVED_3_192_V << EFUSE_RESERVED_3_192_S) +#define EFUSE_RESERVED_3_192_V 0x000000FFU +#define EFUSE_RESERVED_3_192_S 0 +/** EFUSE_CUSTOM_MAC : R; bitpos: [31:8]; default: 0; + * Custom MAC */ -#define EFUSE_USR_DATA6 0xFFFFFFFFU -#define EFUSE_USR_DATA6_M (EFUSE_USR_DATA6_V << EFUSE_USR_DATA6_S) -#define EFUSE_USR_DATA6_V 0xFFFFFFFFU -#define EFUSE_USR_DATA6_S 0 +#define EFUSE_CUSTOM_MAC 0x00FFFFFFU +#define EFUSE_CUSTOM_MAC_M (EFUSE_CUSTOM_MAC_V << EFUSE_CUSTOM_MAC_S) +#define EFUSE_CUSTOM_MAC_V 0x00FFFFFFU +#define EFUSE_CUSTOM_MAC_S 8 /** EFUSE_RD_USR_DATA7_REG register - * Represents rd_usr_data7 + * Register $n of BLOCK3 (user). */ #define EFUSE_RD_USR_DATA7_REG (DR_REG_EFUSE_BASE + 0x98) -/** EFUSE_USR_DATA7 : RO; bitpos: [31:0]; default: 0; - * Represents the zeroth 32-bit of block3 (user). +/** EFUSE_CUSTOM_MAC_1 : R; bitpos: [23:0]; default: 0; + * Custom MAC */ -#define EFUSE_USR_DATA7 0xFFFFFFFFU -#define EFUSE_USR_DATA7_M (EFUSE_USR_DATA7_V << EFUSE_USR_DATA7_S) -#define EFUSE_USR_DATA7_V 0xFFFFFFFFU -#define EFUSE_USR_DATA7_S 0 +#define EFUSE_CUSTOM_MAC_1 0x00FFFFFFU +#define EFUSE_CUSTOM_MAC_1_M (EFUSE_CUSTOM_MAC_1_V << EFUSE_CUSTOM_MAC_1_S) +#define EFUSE_CUSTOM_MAC_1_V 0x00FFFFFFU +#define EFUSE_CUSTOM_MAC_1_S 0 +/** EFUSE_RESERVED_3_248 : R; bitpos: [31:24]; default: 0; + * reserved + */ +#define EFUSE_RESERVED_3_248 0x000000FFU +#define EFUSE_RESERVED_3_248_M (EFUSE_RESERVED_3_248_V << EFUSE_RESERVED_3_248_S) +#define EFUSE_RESERVED_3_248_V 0x000000FFU +#define EFUSE_RESERVED_3_248_S 24 /** EFUSE_RD_KEY0_DATA0_REG register - * Represents rd_key0_data0 + * Register $n of BLOCK4 (KEY0). */ #define EFUSE_RD_KEY0_DATA0_REG (DR_REG_EFUSE_BASE + 0x9c) /** EFUSE_KEY0_DATA0 : RO; bitpos: [31:0]; default: 0; - * Represents the zeroth 32-bit of key0. + * Stores the zeroth 32 bits of KEY0. */ #define EFUSE_KEY0_DATA0 0xFFFFFFFFU #define EFUSE_KEY0_DATA0_M (EFUSE_KEY0_DATA0_V << EFUSE_KEY0_DATA0_S) @@ -970,11 +1106,11 @@ extern "C" { #define EFUSE_KEY0_DATA0_S 0 /** EFUSE_RD_KEY0_DATA1_REG register - * Represents rd_key0_data1 + * Register $n of BLOCK4 (KEY0). */ #define EFUSE_RD_KEY0_DATA1_REG (DR_REG_EFUSE_BASE + 0xa0) /** EFUSE_KEY0_DATA1 : RO; bitpos: [31:0]; default: 0; - * Represents the zeroth 32-bit of key0. + * Stores the first 32 bits of KEY0. */ #define EFUSE_KEY0_DATA1 0xFFFFFFFFU #define EFUSE_KEY0_DATA1_M (EFUSE_KEY0_DATA1_V << EFUSE_KEY0_DATA1_S) @@ -982,11 +1118,11 @@ extern "C" { #define EFUSE_KEY0_DATA1_S 0 /** EFUSE_RD_KEY0_DATA2_REG register - * Represents rd_key0_data2 + * Register $n of BLOCK4 (KEY0). */ #define EFUSE_RD_KEY0_DATA2_REG (DR_REG_EFUSE_BASE + 0xa4) /** EFUSE_KEY0_DATA2 : RO; bitpos: [31:0]; default: 0; - * Represents the zeroth 32-bit of key0. + * Stores the second 32 bits of KEY0. */ #define EFUSE_KEY0_DATA2 0xFFFFFFFFU #define EFUSE_KEY0_DATA2_M (EFUSE_KEY0_DATA2_V << EFUSE_KEY0_DATA2_S) @@ -994,11 +1130,11 @@ extern "C" { #define EFUSE_KEY0_DATA2_S 0 /** EFUSE_RD_KEY0_DATA3_REG register - * Represents rd_key0_data3 + * Register $n of BLOCK4 (KEY0). */ #define EFUSE_RD_KEY0_DATA3_REG (DR_REG_EFUSE_BASE + 0xa8) /** EFUSE_KEY0_DATA3 : RO; bitpos: [31:0]; default: 0; - * Represents the zeroth 32-bit of key0. + * Stores the third 32 bits of KEY0. */ #define EFUSE_KEY0_DATA3 0xFFFFFFFFU #define EFUSE_KEY0_DATA3_M (EFUSE_KEY0_DATA3_V << EFUSE_KEY0_DATA3_S) @@ -1006,11 +1142,11 @@ extern "C" { #define EFUSE_KEY0_DATA3_S 0 /** EFUSE_RD_KEY0_DATA4_REG register - * Represents rd_key0_data4 + * Register $n of BLOCK4 (KEY0). */ #define EFUSE_RD_KEY0_DATA4_REG (DR_REG_EFUSE_BASE + 0xac) /** EFUSE_KEY0_DATA4 : RO; bitpos: [31:0]; default: 0; - * Represents the zeroth 32-bit of key0. + * Stores the fourth 32 bits of KEY0. */ #define EFUSE_KEY0_DATA4 0xFFFFFFFFU #define EFUSE_KEY0_DATA4_M (EFUSE_KEY0_DATA4_V << EFUSE_KEY0_DATA4_S) @@ -1018,11 +1154,11 @@ extern "C" { #define EFUSE_KEY0_DATA4_S 0 /** EFUSE_RD_KEY0_DATA5_REG register - * Represents rd_key0_data5 + * Register $n of BLOCK4 (KEY0). */ #define EFUSE_RD_KEY0_DATA5_REG (DR_REG_EFUSE_BASE + 0xb0) /** EFUSE_KEY0_DATA5 : RO; bitpos: [31:0]; default: 0; - * Represents the zeroth 32-bit of key0. + * Stores the fifth 32 bits of KEY0. */ #define EFUSE_KEY0_DATA5 0xFFFFFFFFU #define EFUSE_KEY0_DATA5_M (EFUSE_KEY0_DATA5_V << EFUSE_KEY0_DATA5_S) @@ -1030,11 +1166,11 @@ extern "C" { #define EFUSE_KEY0_DATA5_S 0 /** EFUSE_RD_KEY0_DATA6_REG register - * Represents rd_key0_data6 + * Register $n of BLOCK4 (KEY0). */ #define EFUSE_RD_KEY0_DATA6_REG (DR_REG_EFUSE_BASE + 0xb4) /** EFUSE_KEY0_DATA6 : RO; bitpos: [31:0]; default: 0; - * Represents the zeroth 32-bit of key0. + * Stores the sixth 32 bits of KEY0. */ #define EFUSE_KEY0_DATA6 0xFFFFFFFFU #define EFUSE_KEY0_DATA6_M (EFUSE_KEY0_DATA6_V << EFUSE_KEY0_DATA6_S) @@ -1042,11 +1178,11 @@ extern "C" { #define EFUSE_KEY0_DATA6_S 0 /** EFUSE_RD_KEY0_DATA7_REG register - * Represents rd_key0_data7 + * Register $n of BLOCK4 (KEY0). */ #define EFUSE_RD_KEY0_DATA7_REG (DR_REG_EFUSE_BASE + 0xb8) /** EFUSE_KEY0_DATA7 : RO; bitpos: [31:0]; default: 0; - * Represents the zeroth 32-bit of key0. + * Stores the seventh 32 bits of KEY0. */ #define EFUSE_KEY0_DATA7 0xFFFFFFFFU #define EFUSE_KEY0_DATA7_M (EFUSE_KEY0_DATA7_V << EFUSE_KEY0_DATA7_S) @@ -1054,11 +1190,11 @@ extern "C" { #define EFUSE_KEY0_DATA7_S 0 /** EFUSE_RD_KEY1_DATA0_REG register - * Represents rd_key1_data0 + * Register $n of BLOCK5 (KEY1). */ #define EFUSE_RD_KEY1_DATA0_REG (DR_REG_EFUSE_BASE + 0xbc) /** EFUSE_KEY1_DATA0 : RO; bitpos: [31:0]; default: 0; - * Represents the zeroth 32-bit of key1. + * Stores the zeroth 32 bits of KEY1. */ #define EFUSE_KEY1_DATA0 0xFFFFFFFFU #define EFUSE_KEY1_DATA0_M (EFUSE_KEY1_DATA0_V << EFUSE_KEY1_DATA0_S) @@ -1066,11 +1202,11 @@ extern "C" { #define EFUSE_KEY1_DATA0_S 0 /** EFUSE_RD_KEY1_DATA1_REG register - * Represents rd_key1_data1 + * Register $n of BLOCK5 (KEY1). */ #define EFUSE_RD_KEY1_DATA1_REG (DR_REG_EFUSE_BASE + 0xc0) /** EFUSE_KEY1_DATA1 : RO; bitpos: [31:0]; default: 0; - * Represents the zeroth 32-bit of key1. + * Stores the first 32 bits of KEY1. */ #define EFUSE_KEY1_DATA1 0xFFFFFFFFU #define EFUSE_KEY1_DATA1_M (EFUSE_KEY1_DATA1_V << EFUSE_KEY1_DATA1_S) @@ -1078,11 +1214,11 @@ extern "C" { #define EFUSE_KEY1_DATA1_S 0 /** EFUSE_RD_KEY1_DATA2_REG register - * Represents rd_key1_data2 + * Register $n of BLOCK5 (KEY1). */ #define EFUSE_RD_KEY1_DATA2_REG (DR_REG_EFUSE_BASE + 0xc4) /** EFUSE_KEY1_DATA2 : RO; bitpos: [31:0]; default: 0; - * Represents the zeroth 32-bit of key1. + * Stores the second 32 bits of KEY1. */ #define EFUSE_KEY1_DATA2 0xFFFFFFFFU #define EFUSE_KEY1_DATA2_M (EFUSE_KEY1_DATA2_V << EFUSE_KEY1_DATA2_S) @@ -1090,11 +1226,11 @@ extern "C" { #define EFUSE_KEY1_DATA2_S 0 /** EFUSE_RD_KEY1_DATA3_REG register - * Represents rd_key1_data3 + * Register $n of BLOCK5 (KEY1). */ #define EFUSE_RD_KEY1_DATA3_REG (DR_REG_EFUSE_BASE + 0xc8) /** EFUSE_KEY1_DATA3 : RO; bitpos: [31:0]; default: 0; - * Represents the zeroth 32-bit of key1. + * Stores the third 32 bits of KEY1. */ #define EFUSE_KEY1_DATA3 0xFFFFFFFFU #define EFUSE_KEY1_DATA3_M (EFUSE_KEY1_DATA3_V << EFUSE_KEY1_DATA3_S) @@ -1102,11 +1238,11 @@ extern "C" { #define EFUSE_KEY1_DATA3_S 0 /** EFUSE_RD_KEY1_DATA4_REG register - * Represents rd_key1_data4 + * Register $n of BLOCK5 (KEY1). */ #define EFUSE_RD_KEY1_DATA4_REG (DR_REG_EFUSE_BASE + 0xcc) /** EFUSE_KEY1_DATA4 : RO; bitpos: [31:0]; default: 0; - * Represents the zeroth 32-bit of key1. + * Stores the fourth 32 bits of KEY1. */ #define EFUSE_KEY1_DATA4 0xFFFFFFFFU #define EFUSE_KEY1_DATA4_M (EFUSE_KEY1_DATA4_V << EFUSE_KEY1_DATA4_S) @@ -1114,11 +1250,11 @@ extern "C" { #define EFUSE_KEY1_DATA4_S 0 /** EFUSE_RD_KEY1_DATA5_REG register - * Represents rd_key1_data5 + * Register $n of BLOCK5 (KEY1). */ #define EFUSE_RD_KEY1_DATA5_REG (DR_REG_EFUSE_BASE + 0xd0) /** EFUSE_KEY1_DATA5 : RO; bitpos: [31:0]; default: 0; - * Represents the zeroth 32-bit of key1. + * Stores the fifth 32 bits of KEY1. */ #define EFUSE_KEY1_DATA5 0xFFFFFFFFU #define EFUSE_KEY1_DATA5_M (EFUSE_KEY1_DATA5_V << EFUSE_KEY1_DATA5_S) @@ -1126,11 +1262,11 @@ extern "C" { #define EFUSE_KEY1_DATA5_S 0 /** EFUSE_RD_KEY1_DATA6_REG register - * Represents rd_key1_data6 + * Register $n of BLOCK5 (KEY1). */ #define EFUSE_RD_KEY1_DATA6_REG (DR_REG_EFUSE_BASE + 0xd4) /** EFUSE_KEY1_DATA6 : RO; bitpos: [31:0]; default: 0; - * Represents the zeroth 32-bit of key1. + * Stores the sixth 32 bits of KEY1. */ #define EFUSE_KEY1_DATA6 0xFFFFFFFFU #define EFUSE_KEY1_DATA6_M (EFUSE_KEY1_DATA6_V << EFUSE_KEY1_DATA6_S) @@ -1138,11 +1274,11 @@ extern "C" { #define EFUSE_KEY1_DATA6_S 0 /** EFUSE_RD_KEY1_DATA7_REG register - * Represents rd_key1_data7 + * Register $n of BLOCK5 (KEY1). */ #define EFUSE_RD_KEY1_DATA7_REG (DR_REG_EFUSE_BASE + 0xd8) /** EFUSE_KEY1_DATA7 : RO; bitpos: [31:0]; default: 0; - * Represents the zeroth 32-bit of key1. + * Stores the seventh 32 bits of KEY1. */ #define EFUSE_KEY1_DATA7 0xFFFFFFFFU #define EFUSE_KEY1_DATA7_M (EFUSE_KEY1_DATA7_V << EFUSE_KEY1_DATA7_S) @@ -1150,11 +1286,11 @@ extern "C" { #define EFUSE_KEY1_DATA7_S 0 /** EFUSE_RD_KEY2_DATA0_REG register - * Represents rd_key2_data0 + * Register $n of BLOCK6 (KEY2). */ #define EFUSE_RD_KEY2_DATA0_REG (DR_REG_EFUSE_BASE + 0xdc) /** EFUSE_KEY2_DATA0 : RO; bitpos: [31:0]; default: 0; - * Represents the zeroth 32-bit of key2. + * Stores the zeroth 32 bits of KEY2. */ #define EFUSE_KEY2_DATA0 0xFFFFFFFFU #define EFUSE_KEY2_DATA0_M (EFUSE_KEY2_DATA0_V << EFUSE_KEY2_DATA0_S) @@ -1162,11 +1298,11 @@ extern "C" { #define EFUSE_KEY2_DATA0_S 0 /** EFUSE_RD_KEY2_DATA1_REG register - * Represents rd_key2_data1 + * Register $n of BLOCK6 (KEY2). */ #define EFUSE_RD_KEY2_DATA1_REG (DR_REG_EFUSE_BASE + 0xe0) /** EFUSE_KEY2_DATA1 : RO; bitpos: [31:0]; default: 0; - * Represents the zeroth 32-bit of key2. + * Stores the first 32 bits of KEY2. */ #define EFUSE_KEY2_DATA1 0xFFFFFFFFU #define EFUSE_KEY2_DATA1_M (EFUSE_KEY2_DATA1_V << EFUSE_KEY2_DATA1_S) @@ -1174,11 +1310,11 @@ extern "C" { #define EFUSE_KEY2_DATA1_S 0 /** EFUSE_RD_KEY2_DATA2_REG register - * Represents rd_key2_data2 + * Register $n of BLOCK6 (KEY2). */ #define EFUSE_RD_KEY2_DATA2_REG (DR_REG_EFUSE_BASE + 0xe4) /** EFUSE_KEY2_DATA2 : RO; bitpos: [31:0]; default: 0; - * Represents the zeroth 32-bit of key2. + * Stores the second 32 bits of KEY2. */ #define EFUSE_KEY2_DATA2 0xFFFFFFFFU #define EFUSE_KEY2_DATA2_M (EFUSE_KEY2_DATA2_V << EFUSE_KEY2_DATA2_S) @@ -1186,11 +1322,11 @@ extern "C" { #define EFUSE_KEY2_DATA2_S 0 /** EFUSE_RD_KEY2_DATA3_REG register - * Represents rd_key2_data3 + * Register $n of BLOCK6 (KEY2). */ #define EFUSE_RD_KEY2_DATA3_REG (DR_REG_EFUSE_BASE + 0xe8) /** EFUSE_KEY2_DATA3 : RO; bitpos: [31:0]; default: 0; - * Represents the zeroth 32-bit of key2. + * Stores the third 32 bits of KEY2. */ #define EFUSE_KEY2_DATA3 0xFFFFFFFFU #define EFUSE_KEY2_DATA3_M (EFUSE_KEY2_DATA3_V << EFUSE_KEY2_DATA3_S) @@ -1198,11 +1334,11 @@ extern "C" { #define EFUSE_KEY2_DATA3_S 0 /** EFUSE_RD_KEY2_DATA4_REG register - * Represents rd_key2_data4 + * Register $n of BLOCK6 (KEY2). */ #define EFUSE_RD_KEY2_DATA4_REG (DR_REG_EFUSE_BASE + 0xec) /** EFUSE_KEY2_DATA4 : RO; bitpos: [31:0]; default: 0; - * Represents the zeroth 32-bit of key2. + * Stores the fourth 32 bits of KEY2. */ #define EFUSE_KEY2_DATA4 0xFFFFFFFFU #define EFUSE_KEY2_DATA4_M (EFUSE_KEY2_DATA4_V << EFUSE_KEY2_DATA4_S) @@ -1210,11 +1346,11 @@ extern "C" { #define EFUSE_KEY2_DATA4_S 0 /** EFUSE_RD_KEY2_DATA5_REG register - * Represents rd_key2_data5 + * Register $n of BLOCK6 (KEY2). */ #define EFUSE_RD_KEY2_DATA5_REG (DR_REG_EFUSE_BASE + 0xf0) /** EFUSE_KEY2_DATA5 : RO; bitpos: [31:0]; default: 0; - * Represents the zeroth 32-bit of key2. + * Stores the fifth 32 bits of KEY2. */ #define EFUSE_KEY2_DATA5 0xFFFFFFFFU #define EFUSE_KEY2_DATA5_M (EFUSE_KEY2_DATA5_V << EFUSE_KEY2_DATA5_S) @@ -1222,11 +1358,11 @@ extern "C" { #define EFUSE_KEY2_DATA5_S 0 /** EFUSE_RD_KEY2_DATA6_REG register - * Represents rd_key2_data6 + * Register $n of BLOCK6 (KEY2). */ #define EFUSE_RD_KEY2_DATA6_REG (DR_REG_EFUSE_BASE + 0xf4) /** EFUSE_KEY2_DATA6 : RO; bitpos: [31:0]; default: 0; - * Represents the zeroth 32-bit of key2. + * Stores the sixth 32 bits of KEY2. */ #define EFUSE_KEY2_DATA6 0xFFFFFFFFU #define EFUSE_KEY2_DATA6_M (EFUSE_KEY2_DATA6_V << EFUSE_KEY2_DATA6_S) @@ -1234,11 +1370,11 @@ extern "C" { #define EFUSE_KEY2_DATA6_S 0 /** EFUSE_RD_KEY2_DATA7_REG register - * Represents rd_key2_data7 + * Register $n of BLOCK6 (KEY2). */ #define EFUSE_RD_KEY2_DATA7_REG (DR_REG_EFUSE_BASE + 0xf8) /** EFUSE_KEY2_DATA7 : RO; bitpos: [31:0]; default: 0; - * Represents the zeroth 32-bit of key2. + * Stores the seventh 32 bits of KEY2. */ #define EFUSE_KEY2_DATA7 0xFFFFFFFFU #define EFUSE_KEY2_DATA7_M (EFUSE_KEY2_DATA7_V << EFUSE_KEY2_DATA7_S) @@ -1246,11 +1382,11 @@ extern "C" { #define EFUSE_KEY2_DATA7_S 0 /** EFUSE_RD_KEY3_DATA0_REG register - * Represents rd_key3_data0 + * Register $n of BLOCK7 (KEY3). */ #define EFUSE_RD_KEY3_DATA0_REG (DR_REG_EFUSE_BASE + 0xfc) /** EFUSE_KEY3_DATA0 : RO; bitpos: [31:0]; default: 0; - * Represents the zeroth 32-bit of key3. + * Stores the zeroth 32 bits of KEY3. */ #define EFUSE_KEY3_DATA0 0xFFFFFFFFU #define EFUSE_KEY3_DATA0_M (EFUSE_KEY3_DATA0_V << EFUSE_KEY3_DATA0_S) @@ -1258,11 +1394,11 @@ extern "C" { #define EFUSE_KEY3_DATA0_S 0 /** EFUSE_RD_KEY3_DATA1_REG register - * Represents rd_key3_data1 + * Register $n of BLOCK7 (KEY3). */ #define EFUSE_RD_KEY3_DATA1_REG (DR_REG_EFUSE_BASE + 0x100) /** EFUSE_KEY3_DATA1 : RO; bitpos: [31:0]; default: 0; - * Represents the zeroth 32-bit of key3. + * Stores the first 32 bits of KEY3. */ #define EFUSE_KEY3_DATA1 0xFFFFFFFFU #define EFUSE_KEY3_DATA1_M (EFUSE_KEY3_DATA1_V << EFUSE_KEY3_DATA1_S) @@ -1270,11 +1406,11 @@ extern "C" { #define EFUSE_KEY3_DATA1_S 0 /** EFUSE_RD_KEY3_DATA2_REG register - * Represents rd_key3_data2 + * Register $n of BLOCK7 (KEY3). */ #define EFUSE_RD_KEY3_DATA2_REG (DR_REG_EFUSE_BASE + 0x104) /** EFUSE_KEY3_DATA2 : RO; bitpos: [31:0]; default: 0; - * Represents the zeroth 32-bit of key3. + * Stores the second 32 bits of KEY3. */ #define EFUSE_KEY3_DATA2 0xFFFFFFFFU #define EFUSE_KEY3_DATA2_M (EFUSE_KEY3_DATA2_V << EFUSE_KEY3_DATA2_S) @@ -1282,11 +1418,11 @@ extern "C" { #define EFUSE_KEY3_DATA2_S 0 /** EFUSE_RD_KEY3_DATA3_REG register - * Represents rd_key3_data3 + * Register $n of BLOCK7 (KEY3). */ #define EFUSE_RD_KEY3_DATA3_REG (DR_REG_EFUSE_BASE + 0x108) /** EFUSE_KEY3_DATA3 : RO; bitpos: [31:0]; default: 0; - * Represents the zeroth 32-bit of key3. + * Stores the third 32 bits of KEY3. */ #define EFUSE_KEY3_DATA3 0xFFFFFFFFU #define EFUSE_KEY3_DATA3_M (EFUSE_KEY3_DATA3_V << EFUSE_KEY3_DATA3_S) @@ -1294,11 +1430,11 @@ extern "C" { #define EFUSE_KEY3_DATA3_S 0 /** EFUSE_RD_KEY3_DATA4_REG register - * Represents rd_key3_data4 + * Register $n of BLOCK7 (KEY3). */ #define EFUSE_RD_KEY3_DATA4_REG (DR_REG_EFUSE_BASE + 0x10c) /** EFUSE_KEY3_DATA4 : RO; bitpos: [31:0]; default: 0; - * Represents the zeroth 32-bit of key3. + * Stores the fourth 32 bits of KEY3. */ #define EFUSE_KEY3_DATA4 0xFFFFFFFFU #define EFUSE_KEY3_DATA4_M (EFUSE_KEY3_DATA4_V << EFUSE_KEY3_DATA4_S) @@ -1306,11 +1442,11 @@ extern "C" { #define EFUSE_KEY3_DATA4_S 0 /** EFUSE_RD_KEY3_DATA5_REG register - * Represents rd_key3_data5 + * Register $n of BLOCK7 (KEY3). */ #define EFUSE_RD_KEY3_DATA5_REG (DR_REG_EFUSE_BASE + 0x110) /** EFUSE_KEY3_DATA5 : RO; bitpos: [31:0]; default: 0; - * Represents the zeroth 32-bit of key3. + * Stores the fifth 32 bits of KEY3. */ #define EFUSE_KEY3_DATA5 0xFFFFFFFFU #define EFUSE_KEY3_DATA5_M (EFUSE_KEY3_DATA5_V << EFUSE_KEY3_DATA5_S) @@ -1318,11 +1454,11 @@ extern "C" { #define EFUSE_KEY3_DATA5_S 0 /** EFUSE_RD_KEY3_DATA6_REG register - * Represents rd_key3_data6 + * Register $n of BLOCK7 (KEY3). */ #define EFUSE_RD_KEY3_DATA6_REG (DR_REG_EFUSE_BASE + 0x114) /** EFUSE_KEY3_DATA6 : RO; bitpos: [31:0]; default: 0; - * Represents the zeroth 32-bit of key3. + * Stores the sixth 32 bits of KEY3. */ #define EFUSE_KEY3_DATA6 0xFFFFFFFFU #define EFUSE_KEY3_DATA6_M (EFUSE_KEY3_DATA6_V << EFUSE_KEY3_DATA6_S) @@ -1330,11 +1466,11 @@ extern "C" { #define EFUSE_KEY3_DATA6_S 0 /** EFUSE_RD_KEY3_DATA7_REG register - * Represents rd_key3_data7 + * Register $n of BLOCK7 (KEY3). */ #define EFUSE_RD_KEY3_DATA7_REG (DR_REG_EFUSE_BASE + 0x118) /** EFUSE_KEY3_DATA7 : RO; bitpos: [31:0]; default: 0; - * Represents the zeroth 32-bit of key3. + * Stores the seventh 32 bits of KEY3. */ #define EFUSE_KEY3_DATA7 0xFFFFFFFFU #define EFUSE_KEY3_DATA7_M (EFUSE_KEY3_DATA7_V << EFUSE_KEY3_DATA7_S) @@ -1342,11 +1478,11 @@ extern "C" { #define EFUSE_KEY3_DATA7_S 0 /** EFUSE_RD_KEY4_DATA0_REG register - * Represents rd_key4_data0 + * Register $n of BLOCK8 (KEY4). */ #define EFUSE_RD_KEY4_DATA0_REG (DR_REG_EFUSE_BASE + 0x11c) /** EFUSE_KEY4_DATA0 : RO; bitpos: [31:0]; default: 0; - * Represents the zeroth 32-bit of key4. + * Stores the zeroth 32 bits of KEY4. */ #define EFUSE_KEY4_DATA0 0xFFFFFFFFU #define EFUSE_KEY4_DATA0_M (EFUSE_KEY4_DATA0_V << EFUSE_KEY4_DATA0_S) @@ -1354,11 +1490,11 @@ extern "C" { #define EFUSE_KEY4_DATA0_S 0 /** EFUSE_RD_KEY4_DATA1_REG register - * Represents rd_key4_data1 + * Register $n of BLOCK8 (KEY4). */ #define EFUSE_RD_KEY4_DATA1_REG (DR_REG_EFUSE_BASE + 0x120) /** EFUSE_KEY4_DATA1 : RO; bitpos: [31:0]; default: 0; - * Represents the zeroth 32-bit of key4. + * Stores the first 32 bits of KEY4. */ #define EFUSE_KEY4_DATA1 0xFFFFFFFFU #define EFUSE_KEY4_DATA1_M (EFUSE_KEY4_DATA1_V << EFUSE_KEY4_DATA1_S) @@ -1366,11 +1502,11 @@ extern "C" { #define EFUSE_KEY4_DATA1_S 0 /** EFUSE_RD_KEY4_DATA2_REG register - * Represents rd_key4_data2 + * Register $n of BLOCK8 (KEY4). */ #define EFUSE_RD_KEY4_DATA2_REG (DR_REG_EFUSE_BASE + 0x124) /** EFUSE_KEY4_DATA2 : RO; bitpos: [31:0]; default: 0; - * Represents the zeroth 32-bit of key4. + * Stores the second 32 bits of KEY4. */ #define EFUSE_KEY4_DATA2 0xFFFFFFFFU #define EFUSE_KEY4_DATA2_M (EFUSE_KEY4_DATA2_V << EFUSE_KEY4_DATA2_S) @@ -1378,11 +1514,11 @@ extern "C" { #define EFUSE_KEY4_DATA2_S 0 /** EFUSE_RD_KEY4_DATA3_REG register - * Represents rd_key4_data3 + * Register $n of BLOCK8 (KEY4). */ #define EFUSE_RD_KEY4_DATA3_REG (DR_REG_EFUSE_BASE + 0x128) /** EFUSE_KEY4_DATA3 : RO; bitpos: [31:0]; default: 0; - * Represents the zeroth 32-bit of key4. + * Stores the third 32 bits of KEY4. */ #define EFUSE_KEY4_DATA3 0xFFFFFFFFU #define EFUSE_KEY4_DATA3_M (EFUSE_KEY4_DATA3_V << EFUSE_KEY4_DATA3_S) @@ -1390,11 +1526,11 @@ extern "C" { #define EFUSE_KEY4_DATA3_S 0 /** EFUSE_RD_KEY4_DATA4_REG register - * Represents rd_key4_data4 + * Register $n of BLOCK8 (KEY4). */ #define EFUSE_RD_KEY4_DATA4_REG (DR_REG_EFUSE_BASE + 0x12c) /** EFUSE_KEY4_DATA4 : RO; bitpos: [31:0]; default: 0; - * Represents the zeroth 32-bit of key4. + * Stores the fourth 32 bits of KEY4. */ #define EFUSE_KEY4_DATA4 0xFFFFFFFFU #define EFUSE_KEY4_DATA4_M (EFUSE_KEY4_DATA4_V << EFUSE_KEY4_DATA4_S) @@ -1402,11 +1538,11 @@ extern "C" { #define EFUSE_KEY4_DATA4_S 0 /** EFUSE_RD_KEY4_DATA5_REG register - * Represents rd_key4_data5 + * Register $n of BLOCK8 (KEY4). */ #define EFUSE_RD_KEY4_DATA5_REG (DR_REG_EFUSE_BASE + 0x130) /** EFUSE_KEY4_DATA5 : RO; bitpos: [31:0]; default: 0; - * Represents the zeroth 32-bit of key4. + * Stores the fifth 32 bits of KEY4. */ #define EFUSE_KEY4_DATA5 0xFFFFFFFFU #define EFUSE_KEY4_DATA5_M (EFUSE_KEY4_DATA5_V << EFUSE_KEY4_DATA5_S) @@ -1414,11 +1550,11 @@ extern "C" { #define EFUSE_KEY4_DATA5_S 0 /** EFUSE_RD_KEY4_DATA6_REG register - * Represents rd_key4_data6 + * Register $n of BLOCK8 (KEY4). */ #define EFUSE_RD_KEY4_DATA6_REG (DR_REG_EFUSE_BASE + 0x134) /** EFUSE_KEY4_DATA6 : RO; bitpos: [31:0]; default: 0; - * Represents the zeroth 32-bit of key4. + * Stores the sixth 32 bits of KEY4. */ #define EFUSE_KEY4_DATA6 0xFFFFFFFFU #define EFUSE_KEY4_DATA6_M (EFUSE_KEY4_DATA6_V << EFUSE_KEY4_DATA6_S) @@ -1426,11 +1562,11 @@ extern "C" { #define EFUSE_KEY4_DATA6_S 0 /** EFUSE_RD_KEY4_DATA7_REG register - * Represents rd_key4_data7 + * Register $n of BLOCK8 (KEY4). */ #define EFUSE_RD_KEY4_DATA7_REG (DR_REG_EFUSE_BASE + 0x138) /** EFUSE_KEY4_DATA7 : RO; bitpos: [31:0]; default: 0; - * Represents the zeroth 32-bit of key4. + * Stores the seventh 32 bits of KEY4. */ #define EFUSE_KEY4_DATA7 0xFFFFFFFFU #define EFUSE_KEY4_DATA7_M (EFUSE_KEY4_DATA7_V << EFUSE_KEY4_DATA7_S) @@ -1438,11 +1574,11 @@ extern "C" { #define EFUSE_KEY4_DATA7_S 0 /** EFUSE_RD_KEY5_DATA0_REG register - * Represents rd_key5_data0 + * Register $n of BLOCK9 (KEY5). */ #define EFUSE_RD_KEY5_DATA0_REG (DR_REG_EFUSE_BASE + 0x13c) /** EFUSE_KEY5_DATA0 : RO; bitpos: [31:0]; default: 0; - * Represents the zeroth 32-bit of key5. + * Stores the zeroth 32 bits of KEY5. */ #define EFUSE_KEY5_DATA0 0xFFFFFFFFU #define EFUSE_KEY5_DATA0_M (EFUSE_KEY5_DATA0_V << EFUSE_KEY5_DATA0_S) @@ -1450,11 +1586,11 @@ extern "C" { #define EFUSE_KEY5_DATA0_S 0 /** EFUSE_RD_KEY5_DATA1_REG register - * Represents rd_key5_data1 + * Register $n of BLOCK9 (KEY5). */ #define EFUSE_RD_KEY5_DATA1_REG (DR_REG_EFUSE_BASE + 0x140) /** EFUSE_KEY5_DATA1 : RO; bitpos: [31:0]; default: 0; - * Represents the zeroth 32-bit of key5. + * Stores the first 32 bits of KEY5. */ #define EFUSE_KEY5_DATA1 0xFFFFFFFFU #define EFUSE_KEY5_DATA1_M (EFUSE_KEY5_DATA1_V << EFUSE_KEY5_DATA1_S) @@ -1462,11 +1598,11 @@ extern "C" { #define EFUSE_KEY5_DATA1_S 0 /** EFUSE_RD_KEY5_DATA2_REG register - * Represents rd_key5_data2 + * Register $n of BLOCK9 (KEY5). */ #define EFUSE_RD_KEY5_DATA2_REG (DR_REG_EFUSE_BASE + 0x144) /** EFUSE_KEY5_DATA2 : RO; bitpos: [31:0]; default: 0; - * Represents the zeroth 32-bit of key5. + * Stores the second 32 bits of KEY5. */ #define EFUSE_KEY5_DATA2 0xFFFFFFFFU #define EFUSE_KEY5_DATA2_M (EFUSE_KEY5_DATA2_V << EFUSE_KEY5_DATA2_S) @@ -1474,11 +1610,11 @@ extern "C" { #define EFUSE_KEY5_DATA2_S 0 /** EFUSE_RD_KEY5_DATA3_REG register - * Represents rd_key5_data3 + * Register $n of BLOCK9 (KEY5). */ #define EFUSE_RD_KEY5_DATA3_REG (DR_REG_EFUSE_BASE + 0x148) /** EFUSE_KEY5_DATA3 : RO; bitpos: [31:0]; default: 0; - * Represents the zeroth 32-bit of key5. + * Stores the third 32 bits of KEY5. */ #define EFUSE_KEY5_DATA3 0xFFFFFFFFU #define EFUSE_KEY5_DATA3_M (EFUSE_KEY5_DATA3_V << EFUSE_KEY5_DATA3_S) @@ -1486,11 +1622,11 @@ extern "C" { #define EFUSE_KEY5_DATA3_S 0 /** EFUSE_RD_KEY5_DATA4_REG register - * Represents rd_key5_data4 + * Register $n of BLOCK9 (KEY5). */ #define EFUSE_RD_KEY5_DATA4_REG (DR_REG_EFUSE_BASE + 0x14c) /** EFUSE_KEY5_DATA4 : RO; bitpos: [31:0]; default: 0; - * Represents the zeroth 32-bit of key5. + * Stores the fourth 32 bits of KEY5. */ #define EFUSE_KEY5_DATA4 0xFFFFFFFFU #define EFUSE_KEY5_DATA4_M (EFUSE_KEY5_DATA4_V << EFUSE_KEY5_DATA4_S) @@ -1498,11 +1634,11 @@ extern "C" { #define EFUSE_KEY5_DATA4_S 0 /** EFUSE_RD_KEY5_DATA5_REG register - * Represents rd_key5_data5 + * Register $n of BLOCK9 (KEY5). */ #define EFUSE_RD_KEY5_DATA5_REG (DR_REG_EFUSE_BASE + 0x150) /** EFUSE_KEY5_DATA5 : RO; bitpos: [31:0]; default: 0; - * Represents the zeroth 32-bit of key5. + * Stores the fifth 32 bits of KEY5. */ #define EFUSE_KEY5_DATA5 0xFFFFFFFFU #define EFUSE_KEY5_DATA5_M (EFUSE_KEY5_DATA5_V << EFUSE_KEY5_DATA5_S) @@ -1510,11 +1646,11 @@ extern "C" { #define EFUSE_KEY5_DATA5_S 0 /** EFUSE_RD_KEY5_DATA6_REG register - * Represents rd_key5_data6 + * Register $n of BLOCK9 (KEY5). */ #define EFUSE_RD_KEY5_DATA6_REG (DR_REG_EFUSE_BASE + 0x154) /** EFUSE_KEY5_DATA6 : RO; bitpos: [31:0]; default: 0; - * Represents the zeroth 32-bit of key5. + * Stores the sixth 32 bits of KEY5. */ #define EFUSE_KEY5_DATA6 0xFFFFFFFFU #define EFUSE_KEY5_DATA6_M (EFUSE_KEY5_DATA6_V << EFUSE_KEY5_DATA6_S) @@ -1522,11 +1658,11 @@ extern "C" { #define EFUSE_KEY5_DATA6_S 0 /** EFUSE_RD_KEY5_DATA7_REG register - * Represents rd_key5_data7 + * Register $n of BLOCK9 (KEY5). */ #define EFUSE_RD_KEY5_DATA7_REG (DR_REG_EFUSE_BASE + 0x158) /** EFUSE_KEY5_DATA7 : RO; bitpos: [31:0]; default: 0; - * Represents the zeroth 32-bit of key5. + * Stores the seventh 32 bits of KEY5. */ #define EFUSE_KEY5_DATA7 0xFFFFFFFFU #define EFUSE_KEY5_DATA7_M (EFUSE_KEY5_DATA7_V << EFUSE_KEY5_DATA7_S) @@ -1534,11 +1670,11 @@ extern "C" { #define EFUSE_KEY5_DATA7_S 0 /** EFUSE_RD_SYS_PART2_DATA0_REG register - * Represents rd_sys_part2_data0 + * Register $n of BLOCK10 (system). */ #define EFUSE_RD_SYS_PART2_DATA0_REG (DR_REG_EFUSE_BASE + 0x15c) /** EFUSE_SYS_DATA_PART2_0 : RO; bitpos: [31:0]; default: 0; - * Represents the zeroth 32-bit of second part of system data. + * Stores the $nth 32 bits of the 2nd part of system data. */ #define EFUSE_SYS_DATA_PART2_0 0xFFFFFFFFU #define EFUSE_SYS_DATA_PART2_0_M (EFUSE_SYS_DATA_PART2_0_V << EFUSE_SYS_DATA_PART2_0_S) @@ -1546,11 +1682,11 @@ extern "C" { #define EFUSE_SYS_DATA_PART2_0_S 0 /** EFUSE_RD_SYS_PART2_DATA1_REG register - * Represents rd_sys_part2_data1 + * Register $n of BLOCK9 (KEY5). */ #define EFUSE_RD_SYS_PART2_DATA1_REG (DR_REG_EFUSE_BASE + 0x160) /** EFUSE_SYS_DATA_PART2_1 : RO; bitpos: [31:0]; default: 0; - * Represents the zeroth 32-bit of second part of system data. + * Stores the $nth 32 bits of the 2nd part of system data. */ #define EFUSE_SYS_DATA_PART2_1 0xFFFFFFFFU #define EFUSE_SYS_DATA_PART2_1_M (EFUSE_SYS_DATA_PART2_1_V << EFUSE_SYS_DATA_PART2_1_S) @@ -1558,11 +1694,11 @@ extern "C" { #define EFUSE_SYS_DATA_PART2_1_S 0 /** EFUSE_RD_SYS_PART2_DATA2_REG register - * Represents rd_sys_part2_data2 + * Register $n of BLOCK10 (system). */ #define EFUSE_RD_SYS_PART2_DATA2_REG (DR_REG_EFUSE_BASE + 0x164) /** EFUSE_SYS_DATA_PART2_2 : RO; bitpos: [31:0]; default: 0; - * Represents the zeroth 32-bit of second part of system data. + * Stores the $nth 32 bits of the 2nd part of system data. */ #define EFUSE_SYS_DATA_PART2_2 0xFFFFFFFFU #define EFUSE_SYS_DATA_PART2_2_M (EFUSE_SYS_DATA_PART2_2_V << EFUSE_SYS_DATA_PART2_2_S) @@ -1570,11 +1706,11 @@ extern "C" { #define EFUSE_SYS_DATA_PART2_2_S 0 /** EFUSE_RD_SYS_PART2_DATA3_REG register - * Represents rd_sys_part2_data3 + * Register $n of BLOCK10 (system). */ #define EFUSE_RD_SYS_PART2_DATA3_REG (DR_REG_EFUSE_BASE + 0x168) /** EFUSE_SYS_DATA_PART2_3 : RO; bitpos: [31:0]; default: 0; - * Represents the zeroth 32-bit of second part of system data. + * Stores the $nth 32 bits of the 2nd part of system data. */ #define EFUSE_SYS_DATA_PART2_3 0xFFFFFFFFU #define EFUSE_SYS_DATA_PART2_3_M (EFUSE_SYS_DATA_PART2_3_V << EFUSE_SYS_DATA_PART2_3_S) @@ -1582,11 +1718,11 @@ extern "C" { #define EFUSE_SYS_DATA_PART2_3_S 0 /** EFUSE_RD_SYS_PART2_DATA4_REG register - * Represents rd_sys_part2_data4 + * Register $n of BLOCK10 (system). */ #define EFUSE_RD_SYS_PART2_DATA4_REG (DR_REG_EFUSE_BASE + 0x16c) /** EFUSE_SYS_DATA_PART2_4 : RO; bitpos: [31:0]; default: 0; - * Represents the zeroth 32-bit of second part of system data. + * Stores the $nth 32 bits of the 2nd part of system data. */ #define EFUSE_SYS_DATA_PART2_4 0xFFFFFFFFU #define EFUSE_SYS_DATA_PART2_4_M (EFUSE_SYS_DATA_PART2_4_V << EFUSE_SYS_DATA_PART2_4_S) @@ -1594,11 +1730,11 @@ extern "C" { #define EFUSE_SYS_DATA_PART2_4_S 0 /** EFUSE_RD_SYS_PART2_DATA5_REG register - * Represents rd_sys_part2_data5 + * Register $n of BLOCK10 (system). */ #define EFUSE_RD_SYS_PART2_DATA5_REG (DR_REG_EFUSE_BASE + 0x170) /** EFUSE_SYS_DATA_PART2_5 : RO; bitpos: [31:0]; default: 0; - * Represents the zeroth 32-bit of second part of system data. + * Stores the $nth 32 bits of the 2nd part of system data. */ #define EFUSE_SYS_DATA_PART2_5 0xFFFFFFFFU #define EFUSE_SYS_DATA_PART2_5_M (EFUSE_SYS_DATA_PART2_5_V << EFUSE_SYS_DATA_PART2_5_S) @@ -1606,11 +1742,11 @@ extern "C" { #define EFUSE_SYS_DATA_PART2_5_S 0 /** EFUSE_RD_SYS_PART2_DATA6_REG register - * Represents rd_sys_part2_data6 + * Register $n of BLOCK10 (system). */ #define EFUSE_RD_SYS_PART2_DATA6_REG (DR_REG_EFUSE_BASE + 0x174) /** EFUSE_SYS_DATA_PART2_6 : RO; bitpos: [31:0]; default: 0; - * Represents the zeroth 32-bit of second part of system data. + * Stores the $nth 32 bits of the 2nd part of system data. */ #define EFUSE_SYS_DATA_PART2_6 0xFFFFFFFFU #define EFUSE_SYS_DATA_PART2_6_M (EFUSE_SYS_DATA_PART2_6_V << EFUSE_SYS_DATA_PART2_6_S) @@ -1618,629 +1754,600 @@ extern "C" { #define EFUSE_SYS_DATA_PART2_6_S 0 /** EFUSE_RD_SYS_PART2_DATA7_REG register - * Represents rd_sys_part2_data7 + * Register $n of BLOCK10 (system). */ #define EFUSE_RD_SYS_PART2_DATA7_REG (DR_REG_EFUSE_BASE + 0x178) /** EFUSE_SYS_DATA_PART2_7 : RO; bitpos: [31:0]; default: 0; - * Represents the zeroth 32-bit of second part of system data. + * Stores the $nth 32 bits of the 2nd part of system data. */ #define EFUSE_SYS_DATA_PART2_7 0xFFFFFFFFU #define EFUSE_SYS_DATA_PART2_7_M (EFUSE_SYS_DATA_PART2_7_V << EFUSE_SYS_DATA_PART2_7_S) #define EFUSE_SYS_DATA_PART2_7_V 0xFFFFFFFFU #define EFUSE_SYS_DATA_PART2_7_S 0 -/** EFUSE_RD_REPEAT_DATA_ERR0_REG register - * Represents rd_repeat_data_err +/** EFUSE_RD_REPEAT_ERR0_REG register + * Programming error record register 0 of BLOCK0. */ -#define EFUSE_RD_REPEAT_DATA_ERR0_REG (DR_REG_EFUSE_BASE + 0x17c) +#define EFUSE_RD_REPEAT_ERR0_REG (DR_REG_EFUSE_BASE + 0x17c) /** EFUSE_RD_DIS_ERR : RO; bitpos: [6:0]; default: 0; - * Represents the programming error of EFUSE_RD_DIS + * Indicates a programming error of RD_DIS. */ #define EFUSE_RD_DIS_ERR 0x0000007FU #define EFUSE_RD_DIS_ERR_M (EFUSE_RD_DIS_ERR_V << EFUSE_RD_DIS_ERR_S) #define EFUSE_RD_DIS_ERR_V 0x0000007FU #define EFUSE_RD_DIS_ERR_S 0 -/** EFUSE_PVT_GLITCH_EN_ERR : RO; bitpos: [7]; default: 0; - * Represents the programming error of EFUSE_PVT_GLITCH_EN +/** EFUSE_RPT4_RESERVED0_ERR_4 : RO; bitpos: [7]; default: 0; + * Reserved. */ -#define EFUSE_PVT_GLITCH_EN_ERR (BIT(7)) -#define EFUSE_PVT_GLITCH_EN_ERR_M (EFUSE_PVT_GLITCH_EN_ERR_V << EFUSE_PVT_GLITCH_EN_ERR_S) -#define EFUSE_PVT_GLITCH_EN_ERR_V 0x00000001U -#define EFUSE_PVT_GLITCH_EN_ERR_S 7 +#define EFUSE_RPT4_RESERVED0_ERR_4 (BIT(7)) +#define EFUSE_RPT4_RESERVED0_ERR_4_M (EFUSE_RPT4_RESERVED0_ERR_4_V << EFUSE_RPT4_RESERVED0_ERR_4_S) +#define EFUSE_RPT4_RESERVED0_ERR_4_V 0x00000001U +#define EFUSE_RPT4_RESERVED0_ERR_4_S 7 /** EFUSE_DIS_ICACHE_ERR : RO; bitpos: [8]; default: 0; - * Represents the programming error of EFUSE_DIS_ICACHE + * Indicates a programming error of DIS_ICACHE. */ #define EFUSE_DIS_ICACHE_ERR (BIT(8)) #define EFUSE_DIS_ICACHE_ERR_M (EFUSE_DIS_ICACHE_ERR_V << EFUSE_DIS_ICACHE_ERR_S) #define EFUSE_DIS_ICACHE_ERR_V 0x00000001U #define EFUSE_DIS_ICACHE_ERR_S 8 /** EFUSE_DIS_USB_JTAG_ERR : RO; bitpos: [9]; default: 0; - * Represents the programming error of EFUSE_DIS_USB_JTAG + * Indicates a programming error of DIS_USB_JTAG. */ #define EFUSE_DIS_USB_JTAG_ERR (BIT(9)) #define EFUSE_DIS_USB_JTAG_ERR_M (EFUSE_DIS_USB_JTAG_ERR_V << EFUSE_DIS_USB_JTAG_ERR_S) #define EFUSE_DIS_USB_JTAG_ERR_V 0x00000001U #define EFUSE_DIS_USB_JTAG_ERR_S 9 /** EFUSE_POWERGLITCH_EN_ERR : RO; bitpos: [10]; default: 0; - * Represents the programming error of EFUSE_POWERGLITCH_EN + * Indicates a programming error of POWERGLITCH_EN. */ #define EFUSE_POWERGLITCH_EN_ERR (BIT(10)) #define EFUSE_POWERGLITCH_EN_ERR_M (EFUSE_POWERGLITCH_EN_ERR_V << EFUSE_POWERGLITCH_EN_ERR_S) #define EFUSE_POWERGLITCH_EN_ERR_V 0x00000001U #define EFUSE_POWERGLITCH_EN_ERR_S 10 +/** EFUSE_DIS_USB_SERIAL_JTAG_ERR : RO; bitpos: [11]; default: 0; + * Indicates a programming error of DIS_USB_DEVICE. + */ +#define EFUSE_DIS_USB_SERIAL_JTAG_ERR (BIT(11)) +#define EFUSE_DIS_USB_SERIAL_JTAG_ERR_M (EFUSE_DIS_USB_SERIAL_JTAG_ERR_V << EFUSE_DIS_USB_SERIAL_JTAG_ERR_S) +#define EFUSE_DIS_USB_SERIAL_JTAG_ERR_V 0x00000001U +#define EFUSE_DIS_USB_SERIAL_JTAG_ERR_S 11 /** EFUSE_DIS_FORCE_DOWNLOAD_ERR : RO; bitpos: [12]; default: 0; - * Represents the programming error of EFUSE_DIS_FORCE_DOWNLOAD + * Indicates a programming error of DIS_FORCE_DOWNLOAD. */ #define EFUSE_DIS_FORCE_DOWNLOAD_ERR (BIT(12)) #define EFUSE_DIS_FORCE_DOWNLOAD_ERR_M (EFUSE_DIS_FORCE_DOWNLOAD_ERR_V << EFUSE_DIS_FORCE_DOWNLOAD_ERR_S) #define EFUSE_DIS_FORCE_DOWNLOAD_ERR_V 0x00000001U #define EFUSE_DIS_FORCE_DOWNLOAD_ERR_S 12 /** EFUSE_SPI_DOWNLOAD_MSPI_DIS_ERR : RO; bitpos: [13]; default: 0; - * Represents the programming error of EFUSE_SPI_DOWNLOAD_MSPI_DIS + * Indicates a programming error of SPI_DOWNLOAD_MSPI_DIS. */ #define EFUSE_SPI_DOWNLOAD_MSPI_DIS_ERR (BIT(13)) #define EFUSE_SPI_DOWNLOAD_MSPI_DIS_ERR_M (EFUSE_SPI_DOWNLOAD_MSPI_DIS_ERR_V << EFUSE_SPI_DOWNLOAD_MSPI_DIS_ERR_S) #define EFUSE_SPI_DOWNLOAD_MSPI_DIS_ERR_V 0x00000001U #define EFUSE_SPI_DOWNLOAD_MSPI_DIS_ERR_S 13 /** EFUSE_DIS_TWAI_ERR : RO; bitpos: [14]; default: 0; - * Represents the programming error of EFUSE_DIS_TWAI + * Indicates a programming error of DIS_CAN. */ #define EFUSE_DIS_TWAI_ERR (BIT(14)) #define EFUSE_DIS_TWAI_ERR_M (EFUSE_DIS_TWAI_ERR_V << EFUSE_DIS_TWAI_ERR_S) #define EFUSE_DIS_TWAI_ERR_V 0x00000001U #define EFUSE_DIS_TWAI_ERR_S 14 /** EFUSE_JTAG_SEL_ENABLE_ERR : RO; bitpos: [15]; default: 0; - * Represents the programming error of EFUSE_JTAG_SEL_ENABLE + * Indicates a programming error of JTAG_SEL_ENABLE. */ #define EFUSE_JTAG_SEL_ENABLE_ERR (BIT(15)) #define EFUSE_JTAG_SEL_ENABLE_ERR_M (EFUSE_JTAG_SEL_ENABLE_ERR_V << EFUSE_JTAG_SEL_ENABLE_ERR_S) #define EFUSE_JTAG_SEL_ENABLE_ERR_V 0x00000001U #define EFUSE_JTAG_SEL_ENABLE_ERR_S 15 /** EFUSE_SOFT_DIS_JTAG_ERR : RO; bitpos: [18:16]; default: 0; - * Represents the programming error of EFUSE_SOFT_DIS_JTAG + * Indicates a programming error of SOFT_DIS_JTAG. */ #define EFUSE_SOFT_DIS_JTAG_ERR 0x00000007U #define EFUSE_SOFT_DIS_JTAG_ERR_M (EFUSE_SOFT_DIS_JTAG_ERR_V << EFUSE_SOFT_DIS_JTAG_ERR_S) #define EFUSE_SOFT_DIS_JTAG_ERR_V 0x00000007U #define EFUSE_SOFT_DIS_JTAG_ERR_S 16 /** EFUSE_DIS_PAD_JTAG_ERR : RO; bitpos: [19]; default: 0; - * Represents the programming error of EFUSE_DIS_PAD_JTAG + * Indicates a programming error of DIS_PAD_JTAG. */ #define EFUSE_DIS_PAD_JTAG_ERR (BIT(19)) #define EFUSE_DIS_PAD_JTAG_ERR_M (EFUSE_DIS_PAD_JTAG_ERR_V << EFUSE_DIS_PAD_JTAG_ERR_S) #define EFUSE_DIS_PAD_JTAG_ERR_V 0x00000001U #define EFUSE_DIS_PAD_JTAG_ERR_S 19 /** EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_ERR : RO; bitpos: [20]; default: 0; - * Represents the programming error of EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT + * Indicates a programming error of DIS_DOWNLOAD_MANUAL_ENCRYPT. */ #define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_ERR (BIT(20)) #define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_ERR_M (EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_ERR_V << EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_ERR_S) #define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_ERR_V 0x00000001U #define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_ERR_S 20 +/** EFUSE_USB_DREFH_ERR : RO; bitpos: [22:21]; default: 0; + * Indicates a programming error of USB_DREFH. + */ +#define EFUSE_USB_DREFH_ERR 0x00000003U +#define EFUSE_USB_DREFH_ERR_M (EFUSE_USB_DREFH_ERR_V << EFUSE_USB_DREFH_ERR_S) +#define EFUSE_USB_DREFH_ERR_V 0x00000003U +#define EFUSE_USB_DREFH_ERR_S 21 +/** EFUSE_USB_DREFL_ERR : RO; bitpos: [24:23]; default: 0; + * Indicates a programming error of USB_DREFL. + */ +#define EFUSE_USB_DREFL_ERR 0x00000003U +#define EFUSE_USB_DREFL_ERR_M (EFUSE_USB_DREFL_ERR_V << EFUSE_USB_DREFL_ERR_S) +#define EFUSE_USB_DREFL_ERR_V 0x00000003U +#define EFUSE_USB_DREFL_ERR_S 23 /** EFUSE_USB_EXCHG_PINS_ERR : RO; bitpos: [25]; default: 0; - * Represents the programming error of EFUSE_USB_EXCHG_PINS + * Indicates a programming error of USB_EXCHG_PINS. */ #define EFUSE_USB_EXCHG_PINS_ERR (BIT(25)) #define EFUSE_USB_EXCHG_PINS_ERR_M (EFUSE_USB_EXCHG_PINS_ERR_V << EFUSE_USB_EXCHG_PINS_ERR_S) #define EFUSE_USB_EXCHG_PINS_ERR_V 0x00000001U #define EFUSE_USB_EXCHG_PINS_ERR_S 25 /** EFUSE_VDD_SPI_AS_GPIO_ERR : RO; bitpos: [26]; default: 0; - * Represents the programming error of EFUSE_VDD_SPI_AS_GPIO + * Indicates a programming error of VDD_SPI_AS_GPIO. */ #define EFUSE_VDD_SPI_AS_GPIO_ERR (BIT(26)) #define EFUSE_VDD_SPI_AS_GPIO_ERR_M (EFUSE_VDD_SPI_AS_GPIO_ERR_V << EFUSE_VDD_SPI_AS_GPIO_ERR_S) #define EFUSE_VDD_SPI_AS_GPIO_ERR_V 0x00000001U #define EFUSE_VDD_SPI_AS_GPIO_ERR_S 26 -/** EFUSE_ECDSA_CURVE_MODE_ERR : RO; bitpos: [28:27]; default: 0; - * Represents the programming error of EFUSE_ECDSA_CURVE_MODE - */ -#define EFUSE_ECDSA_CURVE_MODE_ERR 0x00000003U -#define EFUSE_ECDSA_CURVE_MODE_ERR_M (EFUSE_ECDSA_CURVE_MODE_ERR_V << EFUSE_ECDSA_CURVE_MODE_ERR_S) -#define EFUSE_ECDSA_CURVE_MODE_ERR_V 0x00000003U -#define EFUSE_ECDSA_CURVE_MODE_ERR_S 27 -/** EFUSE_ECC_FORCE_CONST_TIME_ERR : RO; bitpos: [29]; default: 0; - * Represents the programming error of EFUSE_ECC_FORCE_CONST_TIME - */ -#define EFUSE_ECC_FORCE_CONST_TIME_ERR (BIT(29)) -#define EFUSE_ECC_FORCE_CONST_TIME_ERR_M (EFUSE_ECC_FORCE_CONST_TIME_ERR_V << EFUSE_ECC_FORCE_CONST_TIME_ERR_S) -#define EFUSE_ECC_FORCE_CONST_TIME_ERR_V 0x00000001U -#define EFUSE_ECC_FORCE_CONST_TIME_ERR_S 29 -/** EFUSE_XTS_DPA_PSEUDO_LEVEL_ERR : RO; bitpos: [31:30]; default: 0; - * Represents the programming error of EFUSE_XTS_DPA_PSEUDO_LEVEL - */ -#define EFUSE_XTS_DPA_PSEUDO_LEVEL_ERR 0x00000003U -#define EFUSE_XTS_DPA_PSEUDO_LEVEL_ERR_M (EFUSE_XTS_DPA_PSEUDO_LEVEL_ERR_V << EFUSE_XTS_DPA_PSEUDO_LEVEL_ERR_S) -#define EFUSE_XTS_DPA_PSEUDO_LEVEL_ERR_V 0x00000003U -#define EFUSE_XTS_DPA_PSEUDO_LEVEL_ERR_S 30 - -/** EFUSE_RD_REPEAT_DATA_ERR1_REG register - * Represents rd_repeat_data_err - */ -#define EFUSE_RD_REPEAT_DATA_ERR1_REG (DR_REG_EFUSE_BASE + 0x180) -/** EFUSE_IO_LDO_ADJUST_ERR : RO; bitpos: [7:0]; default: 0; - * Represents the programming error of EFUSE_IO_LDO_ADJUST - */ -#define EFUSE_IO_LDO_ADJUST_ERR 0x000000FFU -#define EFUSE_IO_LDO_ADJUST_ERR_M (EFUSE_IO_LDO_ADJUST_ERR_V << EFUSE_IO_LDO_ADJUST_ERR_S) -#define EFUSE_IO_LDO_ADJUST_ERR_V 0x000000FFU -#define EFUSE_IO_LDO_ADJUST_ERR_S 0 -/** EFUSE_VDD_SPI_LDO_ADJUST_ERR : RO; bitpos: [15:8]; default: 0; - * Represents the programming error of EFUSE_VDD_SPI_LDO_ADJUST - */ -#define EFUSE_VDD_SPI_LDO_ADJUST_ERR 0x000000FFU -#define EFUSE_VDD_SPI_LDO_ADJUST_ERR_M (EFUSE_VDD_SPI_LDO_ADJUST_ERR_V << EFUSE_VDD_SPI_LDO_ADJUST_ERR_S) -#define EFUSE_VDD_SPI_LDO_ADJUST_ERR_V 0x000000FFU -#define EFUSE_VDD_SPI_LDO_ADJUST_ERR_S 8 +/** EFUSE_RPT4_RESERVED0_ERR_2 : RO; bitpos: [28:27]; default: 0; + * Reserved. + */ +#define EFUSE_RPT4_RESERVED0_ERR_2 0x00000003U +#define EFUSE_RPT4_RESERVED0_ERR_2_M (EFUSE_RPT4_RESERVED0_ERR_2_V << EFUSE_RPT4_RESERVED0_ERR_2_S) +#define EFUSE_RPT4_RESERVED0_ERR_2_V 0x00000003U +#define EFUSE_RPT4_RESERVED0_ERR_2_S 27 +/** EFUSE_RPT4_RESERVED0_ERR_1 : RO; bitpos: [29]; default: 0; + * Reserved. + */ +#define EFUSE_RPT4_RESERVED0_ERR_1 (BIT(29)) +#define EFUSE_RPT4_RESERVED0_ERR_1_M (EFUSE_RPT4_RESERVED0_ERR_1_V << EFUSE_RPT4_RESERVED0_ERR_1_S) +#define EFUSE_RPT4_RESERVED0_ERR_1_V 0x00000001U +#define EFUSE_RPT4_RESERVED0_ERR_1_S 29 +/** EFUSE_RPT4_RESERVED0_ERR_0 : RO; bitpos: [31:30]; default: 0; + * Reserved. + */ +#define EFUSE_RPT4_RESERVED0_ERR_0 0x00000003U +#define EFUSE_RPT4_RESERVED0_ERR_0_M (EFUSE_RPT4_RESERVED0_ERR_0_V << EFUSE_RPT4_RESERVED0_ERR_0_S) +#define EFUSE_RPT4_RESERVED0_ERR_0_V 0x00000003U +#define EFUSE_RPT4_RESERVED0_ERR_0_S 30 + +/** EFUSE_RD_REPEAT_ERR1_REG register + * Programming error record register 1 of BLOCK0. + */ +#define EFUSE_RD_REPEAT_ERR1_REG (DR_REG_EFUSE_BASE + 0x180) +/** EFUSE_RPT4_RESERVED1_ERR_0 : RO; bitpos: [15:0]; default: 0; + * Reserved. + */ +#define EFUSE_RPT4_RESERVED1_ERR_0 0x0000FFFFU +#define EFUSE_RPT4_RESERVED1_ERR_0_M (EFUSE_RPT4_RESERVED1_ERR_0_V << EFUSE_RPT4_RESERVED1_ERR_0_S) +#define EFUSE_RPT4_RESERVED1_ERR_0_V 0x0000FFFFU +#define EFUSE_RPT4_RESERVED1_ERR_0_S 0 /** EFUSE_WDT_DELAY_SEL_ERR : RO; bitpos: [17:16]; default: 0; - * Represents the programming error of EFUSE_WDT_DELAY_SEL + * Indicates a programming error of WDT_DELAY_SEL. */ #define EFUSE_WDT_DELAY_SEL_ERR 0x00000003U #define EFUSE_WDT_DELAY_SEL_ERR_M (EFUSE_WDT_DELAY_SEL_ERR_V << EFUSE_WDT_DELAY_SEL_ERR_S) #define EFUSE_WDT_DELAY_SEL_ERR_V 0x00000003U #define EFUSE_WDT_DELAY_SEL_ERR_S 16 /** EFUSE_SPI_BOOT_CRYPT_CNT_ERR : RO; bitpos: [20:18]; default: 0; - * Represents the programming error of EFUSE_SPI_BOOT_CRYPT_CNT + * Indicates a programming error of SPI_BOOT_CRYPT_CNT. */ #define EFUSE_SPI_BOOT_CRYPT_CNT_ERR 0x00000007U #define EFUSE_SPI_BOOT_CRYPT_CNT_ERR_M (EFUSE_SPI_BOOT_CRYPT_CNT_ERR_V << EFUSE_SPI_BOOT_CRYPT_CNT_ERR_S) #define EFUSE_SPI_BOOT_CRYPT_CNT_ERR_V 0x00000007U #define EFUSE_SPI_BOOT_CRYPT_CNT_ERR_S 18 /** EFUSE_SECURE_BOOT_KEY_REVOKE0_ERR : RO; bitpos: [21]; default: 0; - * Represents the programming error of EFUSE_SECURE_BOOT_KEY_REVOKE0 + * Indicates a programming error of SECURE_BOOT_KEY_REVOKE0. */ #define EFUSE_SECURE_BOOT_KEY_REVOKE0_ERR (BIT(21)) #define EFUSE_SECURE_BOOT_KEY_REVOKE0_ERR_M (EFUSE_SECURE_BOOT_KEY_REVOKE0_ERR_V << EFUSE_SECURE_BOOT_KEY_REVOKE0_ERR_S) #define EFUSE_SECURE_BOOT_KEY_REVOKE0_ERR_V 0x00000001U #define EFUSE_SECURE_BOOT_KEY_REVOKE0_ERR_S 21 /** EFUSE_SECURE_BOOT_KEY_REVOKE1_ERR : RO; bitpos: [22]; default: 0; - * Represents the programming error of EFUSE_SECURE_BOOT_KEY_REVOKE1 + * Indicates a programming error of SECURE_BOOT_KEY_REVOKE1. */ #define EFUSE_SECURE_BOOT_KEY_REVOKE1_ERR (BIT(22)) #define EFUSE_SECURE_BOOT_KEY_REVOKE1_ERR_M (EFUSE_SECURE_BOOT_KEY_REVOKE1_ERR_V << EFUSE_SECURE_BOOT_KEY_REVOKE1_ERR_S) #define EFUSE_SECURE_BOOT_KEY_REVOKE1_ERR_V 0x00000001U #define EFUSE_SECURE_BOOT_KEY_REVOKE1_ERR_S 22 /** EFUSE_SECURE_BOOT_KEY_REVOKE2_ERR : RO; bitpos: [23]; default: 0; - * Represents the programming error of EFUSE_SECURE_BOOT_KEY_REVOKE2 + * Indicates a programming error of SECURE_BOOT_KEY_REVOKE2. */ #define EFUSE_SECURE_BOOT_KEY_REVOKE2_ERR (BIT(23)) #define EFUSE_SECURE_BOOT_KEY_REVOKE2_ERR_M (EFUSE_SECURE_BOOT_KEY_REVOKE2_ERR_V << EFUSE_SECURE_BOOT_KEY_REVOKE2_ERR_S) #define EFUSE_SECURE_BOOT_KEY_REVOKE2_ERR_V 0x00000001U #define EFUSE_SECURE_BOOT_KEY_REVOKE2_ERR_S 23 /** EFUSE_KEY_PURPOSE_0_ERR : RO; bitpos: [27:24]; default: 0; - * Represents the programming error of EFUSE_KEY_PURPOSE_0 + * Indicates a programming error of KEY_PURPOSE_0. */ #define EFUSE_KEY_PURPOSE_0_ERR 0x0000000FU #define EFUSE_KEY_PURPOSE_0_ERR_M (EFUSE_KEY_PURPOSE_0_ERR_V << EFUSE_KEY_PURPOSE_0_ERR_S) #define EFUSE_KEY_PURPOSE_0_ERR_V 0x0000000FU #define EFUSE_KEY_PURPOSE_0_ERR_S 24 /** EFUSE_KEY_PURPOSE_1_ERR : RO; bitpos: [31:28]; default: 0; - * Represents the programming error of EFUSE_KEY_PURPOSE_1 + * Indicates a programming error of KEY_PURPOSE_1. */ #define EFUSE_KEY_PURPOSE_1_ERR 0x0000000FU #define EFUSE_KEY_PURPOSE_1_ERR_M (EFUSE_KEY_PURPOSE_1_ERR_V << EFUSE_KEY_PURPOSE_1_ERR_S) #define EFUSE_KEY_PURPOSE_1_ERR_V 0x0000000FU #define EFUSE_KEY_PURPOSE_1_ERR_S 28 -/** EFUSE_RD_REPEAT_DATA_ERR2_REG register - * Represents rd_repeat_data_err +/** EFUSE_RD_REPEAT_ERR2_REG register + * Programming error record register 2 of BLOCK0. */ -#define EFUSE_RD_REPEAT_DATA_ERR2_REG (DR_REG_EFUSE_BASE + 0x184) +#define EFUSE_RD_REPEAT_ERR2_REG (DR_REG_EFUSE_BASE + 0x184) /** EFUSE_KEY_PURPOSE_2_ERR : RO; bitpos: [3:0]; default: 0; - * Represents the programming error of EFUSE_KEY_PURPOSE_2 + * Indicates a programming error of KEY_PURPOSE_2. */ #define EFUSE_KEY_PURPOSE_2_ERR 0x0000000FU #define EFUSE_KEY_PURPOSE_2_ERR_M (EFUSE_KEY_PURPOSE_2_ERR_V << EFUSE_KEY_PURPOSE_2_ERR_S) #define EFUSE_KEY_PURPOSE_2_ERR_V 0x0000000FU #define EFUSE_KEY_PURPOSE_2_ERR_S 0 /** EFUSE_KEY_PURPOSE_3_ERR : RO; bitpos: [7:4]; default: 0; - * Represents the programming error of EFUSE_KEY_PURPOSE_3 + * Indicates a programming error of KEY_PURPOSE_3. */ #define EFUSE_KEY_PURPOSE_3_ERR 0x0000000FU #define EFUSE_KEY_PURPOSE_3_ERR_M (EFUSE_KEY_PURPOSE_3_ERR_V << EFUSE_KEY_PURPOSE_3_ERR_S) #define EFUSE_KEY_PURPOSE_3_ERR_V 0x0000000FU #define EFUSE_KEY_PURPOSE_3_ERR_S 4 /** EFUSE_KEY_PURPOSE_4_ERR : RO; bitpos: [11:8]; default: 0; - * Represents the programming error of EFUSE_KEY_PURPOSE_4 + * Indicates a programming error of KEY_PURPOSE_4. */ #define EFUSE_KEY_PURPOSE_4_ERR 0x0000000FU #define EFUSE_KEY_PURPOSE_4_ERR_M (EFUSE_KEY_PURPOSE_4_ERR_V << EFUSE_KEY_PURPOSE_4_ERR_S) #define EFUSE_KEY_PURPOSE_4_ERR_V 0x0000000FU #define EFUSE_KEY_PURPOSE_4_ERR_S 8 /** EFUSE_KEY_PURPOSE_5_ERR : RO; bitpos: [15:12]; default: 0; - * Represents the programming error of EFUSE_KEY_PURPOSE_5 + * Indicates a programming error of KEY_PURPOSE_5. */ #define EFUSE_KEY_PURPOSE_5_ERR 0x0000000FU #define EFUSE_KEY_PURPOSE_5_ERR_M (EFUSE_KEY_PURPOSE_5_ERR_V << EFUSE_KEY_PURPOSE_5_ERR_S) #define EFUSE_KEY_PURPOSE_5_ERR_V 0x0000000FU #define EFUSE_KEY_PURPOSE_5_ERR_S 12 /** EFUSE_SEC_DPA_LEVEL_ERR : RO; bitpos: [17:16]; default: 0; - * Represents the programming error of EFUSE_SEC_DPA_LEVEL + * Indicates a programming error of SEC_DPA_LEVEL. */ #define EFUSE_SEC_DPA_LEVEL_ERR 0x00000003U #define EFUSE_SEC_DPA_LEVEL_ERR_M (EFUSE_SEC_DPA_LEVEL_ERR_V << EFUSE_SEC_DPA_LEVEL_ERR_S) #define EFUSE_SEC_DPA_LEVEL_ERR_V 0x00000003U #define EFUSE_SEC_DPA_LEVEL_ERR_S 16 -/** EFUSE_IO_LDO_1P8_ERR : RO; bitpos: [18]; default: 0; - * Represents the programming error of EFUSE_IO_LDO_1P8 +/** EFUSE_RPT4_RESERVED2_ERR_1 : RO; bitpos: [18]; default: 0; + * Reserved. */ -#define EFUSE_IO_LDO_1P8_ERR (BIT(18)) -#define EFUSE_IO_LDO_1P8_ERR_M (EFUSE_IO_LDO_1P8_ERR_V << EFUSE_IO_LDO_1P8_ERR_S) -#define EFUSE_IO_LDO_1P8_ERR_V 0x00000001U -#define EFUSE_IO_LDO_1P8_ERR_S 18 +#define EFUSE_RPT4_RESERVED2_ERR_1 (BIT(18)) +#define EFUSE_RPT4_RESERVED2_ERR_1_M (EFUSE_RPT4_RESERVED2_ERR_1_V << EFUSE_RPT4_RESERVED2_ERR_1_S) +#define EFUSE_RPT4_RESERVED2_ERR_1_V 0x00000001U +#define EFUSE_RPT4_RESERVED2_ERR_1_S 18 /** EFUSE_CRYPT_DPA_ENABLE_ERR : RO; bitpos: [19]; default: 0; - * Represents the programming error of EFUSE_CRYPT_DPA_ENABLE + * Indicates a programming error of CRYPT_DPA_ENABLE. */ #define EFUSE_CRYPT_DPA_ENABLE_ERR (BIT(19)) #define EFUSE_CRYPT_DPA_ENABLE_ERR_M (EFUSE_CRYPT_DPA_ENABLE_ERR_V << EFUSE_CRYPT_DPA_ENABLE_ERR_S) #define EFUSE_CRYPT_DPA_ENABLE_ERR_V 0x00000001U #define EFUSE_CRYPT_DPA_ENABLE_ERR_S 19 /** EFUSE_SECURE_BOOT_EN_ERR : RO; bitpos: [20]; default: 0; - * Represents the programming error of EFUSE_SECURE_BOOT_EN + * Indicates a programming error of SECURE_BOOT_EN. */ #define EFUSE_SECURE_BOOT_EN_ERR (BIT(20)) #define EFUSE_SECURE_BOOT_EN_ERR_M (EFUSE_SECURE_BOOT_EN_ERR_V << EFUSE_SECURE_BOOT_EN_ERR_S) #define EFUSE_SECURE_BOOT_EN_ERR_V 0x00000001U #define EFUSE_SECURE_BOOT_EN_ERR_S 20 /** EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_ERR : RO; bitpos: [21]; default: 0; - * Represents the programming error of EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE + * Indicates a programming error of SECURE_BOOT_AGGRESSIVE_REVOKE. */ #define EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_ERR (BIT(21)) #define EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_ERR_M (EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_ERR_V << EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_ERR_S) #define EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_ERR_V 0x00000001U #define EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_ERR_S 21 -/** EFUSE_POWERGLITCH_EN1_ERR : RO; bitpos: [26:22]; default: 0; - * Represents the programming error of EFUSE_POWERGLITCH_EN1 - */ -#define EFUSE_POWERGLITCH_EN1_ERR 0x0000001FU -#define EFUSE_POWERGLITCH_EN1_ERR_M (EFUSE_POWERGLITCH_EN1_ERR_V << EFUSE_POWERGLITCH_EN1_ERR_S) -#define EFUSE_POWERGLITCH_EN1_ERR_V 0x0000001FU -#define EFUSE_POWERGLITCH_EN1_ERR_S 22 -/** EFUSE_DCDC_CCM_EN_ERR : RO; bitpos: [27]; default: 0; - * Represents the programming error of EFUSE_DCDC_CCM_EN - */ -#define EFUSE_DCDC_CCM_EN_ERR (BIT(27)) -#define EFUSE_DCDC_CCM_EN_ERR_M (EFUSE_DCDC_CCM_EN_ERR_V << EFUSE_DCDC_CCM_EN_ERR_S) -#define EFUSE_DCDC_CCM_EN_ERR_V 0x00000001U -#define EFUSE_DCDC_CCM_EN_ERR_S 27 +/** EFUSE_RPT4_RESERVED2_ERR_0 : RO; bitpos: [27:22]; default: 0; + * Reserved. + */ +#define EFUSE_RPT4_RESERVED2_ERR_0 0x0000003FU +#define EFUSE_RPT4_RESERVED2_ERR_0_M (EFUSE_RPT4_RESERVED2_ERR_0_V << EFUSE_RPT4_RESERVED2_ERR_0_S) +#define EFUSE_RPT4_RESERVED2_ERR_0_V 0x0000003FU +#define EFUSE_RPT4_RESERVED2_ERR_0_S 22 /** EFUSE_FLASH_TPUW_ERR : RO; bitpos: [31:28]; default: 0; - * Represents the programming error of EFUSE_FLASH_TPUW + * Indicates a programming error of FLASH_TPUW. */ #define EFUSE_FLASH_TPUW_ERR 0x0000000FU #define EFUSE_FLASH_TPUW_ERR_M (EFUSE_FLASH_TPUW_ERR_V << EFUSE_FLASH_TPUW_ERR_S) #define EFUSE_FLASH_TPUW_ERR_V 0x0000000FU #define EFUSE_FLASH_TPUW_ERR_S 28 -/** EFUSE_RD_REPEAT_DATA_ERR3_REG register - * Represents rd_repeat_data_err +/** EFUSE_RD_REPEAT_ERR3_REG register + * Programming error record register 3 of BLOCK0. */ -#define EFUSE_RD_REPEAT_DATA_ERR3_REG (DR_REG_EFUSE_BASE + 0x188) +#define EFUSE_RD_REPEAT_ERR3_REG (DR_REG_EFUSE_BASE + 0x188) /** EFUSE_DIS_DOWNLOAD_MODE_ERR : RO; bitpos: [0]; default: 0; - * Represents the programming error of EFUSE_DIS_DOWNLOAD_MODE + * Indicates a programming error of DIS_DOWNLOAD_MODE. */ #define EFUSE_DIS_DOWNLOAD_MODE_ERR (BIT(0)) #define EFUSE_DIS_DOWNLOAD_MODE_ERR_M (EFUSE_DIS_DOWNLOAD_MODE_ERR_V << EFUSE_DIS_DOWNLOAD_MODE_ERR_S) #define EFUSE_DIS_DOWNLOAD_MODE_ERR_V 0x00000001U #define EFUSE_DIS_DOWNLOAD_MODE_ERR_S 0 /** EFUSE_DIS_DIRECT_BOOT_ERR : RO; bitpos: [1]; default: 0; - * Represents the programming error of EFUSE_DIS_DIRECT_BOOT + * Indicates a programming error of DIS_DIRECT_BOOT. */ #define EFUSE_DIS_DIRECT_BOOT_ERR (BIT(1)) #define EFUSE_DIS_DIRECT_BOOT_ERR_M (EFUSE_DIS_DIRECT_BOOT_ERR_V << EFUSE_DIS_DIRECT_BOOT_ERR_S) #define EFUSE_DIS_DIRECT_BOOT_ERR_V 0x00000001U #define EFUSE_DIS_DIRECT_BOOT_ERR_S 1 -/** EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT_ERR : RO; bitpos: [2]; default: 0; - * Represents the programming error of EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT +/** EFUSE_USB_PRINT_ERR : RO; bitpos: [2]; default: 0; + * Indicates a programming error of UART_PRINT_CHANNEL. + */ +#define EFUSE_USB_PRINT_ERR (BIT(2)) +#define EFUSE_USB_PRINT_ERR_M (EFUSE_USB_PRINT_ERR_V << EFUSE_USB_PRINT_ERR_S) +#define EFUSE_USB_PRINT_ERR_V 0x00000001U +#define EFUSE_USB_PRINT_ERR_S 2 +/** EFUSE_RPT4_RESERVED3_ERR_5 : RO; bitpos: [3]; default: 0; + * Reserved. */ -#define EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT_ERR (BIT(2)) -#define EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT_ERR_M (EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT_ERR_V << EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT_ERR_S) -#define EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT_ERR_V 0x00000001U -#define EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT_ERR_S 2 +#define EFUSE_RPT4_RESERVED3_ERR_5 (BIT(3)) +#define EFUSE_RPT4_RESERVED3_ERR_5_M (EFUSE_RPT4_RESERVED3_ERR_5_V << EFUSE_RPT4_RESERVED3_ERR_5_S) +#define EFUSE_RPT4_RESERVED3_ERR_5_V 0x00000001U +#define EFUSE_RPT4_RESERVED3_ERR_5_S 3 /** EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE_ERR : RO; bitpos: [4]; default: 0; - * Represents the programming error of EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE + * Indicates a programming error of DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE. */ #define EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE_ERR (BIT(4)) #define EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE_ERR_M (EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE_ERR_V << EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE_ERR_S) #define EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE_ERR_V 0x00000001U #define EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE_ERR_S 4 /** EFUSE_ENABLE_SECURITY_DOWNLOAD_ERR : RO; bitpos: [5]; default: 0; - * Represents the programming error of EFUSE_ENABLE_SECURITY_DOWNLOAD + * Indicates a programming error of ENABLE_SECURITY_DOWNLOAD. */ #define EFUSE_ENABLE_SECURITY_DOWNLOAD_ERR (BIT(5)) #define EFUSE_ENABLE_SECURITY_DOWNLOAD_ERR_M (EFUSE_ENABLE_SECURITY_DOWNLOAD_ERR_V << EFUSE_ENABLE_SECURITY_DOWNLOAD_ERR_S) #define EFUSE_ENABLE_SECURITY_DOWNLOAD_ERR_V 0x00000001U #define EFUSE_ENABLE_SECURITY_DOWNLOAD_ERR_S 5 /** EFUSE_UART_PRINT_CONTROL_ERR : RO; bitpos: [7:6]; default: 0; - * Represents the programming error of EFUSE_UART_PRINT_CONTROL + * Indicates a programming error of UART_PRINT_CONTROL. */ #define EFUSE_UART_PRINT_CONTROL_ERR 0x00000003U #define EFUSE_UART_PRINT_CONTROL_ERR_M (EFUSE_UART_PRINT_CONTROL_ERR_V << EFUSE_UART_PRINT_CONTROL_ERR_S) #define EFUSE_UART_PRINT_CONTROL_ERR_V 0x00000003U #define EFUSE_UART_PRINT_CONTROL_ERR_S 6 /** EFUSE_FORCE_SEND_RESUME_ERR : RO; bitpos: [8]; default: 0; - * Represents the programming error of EFUSE_FORCE_SEND_RESUME + * Indicates a programming error of FORCE_SEND_RESUME. */ #define EFUSE_FORCE_SEND_RESUME_ERR (BIT(8)) #define EFUSE_FORCE_SEND_RESUME_ERR_M (EFUSE_FORCE_SEND_RESUME_ERR_V << EFUSE_FORCE_SEND_RESUME_ERR_S) #define EFUSE_FORCE_SEND_RESUME_ERR_V 0x00000001U #define EFUSE_FORCE_SEND_RESUME_ERR_S 8 /** EFUSE_SECURE_VERSION_ERR : RO; bitpos: [24:9]; default: 0; - * Represents the programming error of EFUSE_SECURE_VERSION + * Indicates a programming error of SECURE VERSION. */ #define EFUSE_SECURE_VERSION_ERR 0x0000FFFFU #define EFUSE_SECURE_VERSION_ERR_M (EFUSE_SECURE_VERSION_ERR_V << EFUSE_SECURE_VERSION_ERR_S) #define EFUSE_SECURE_VERSION_ERR_V 0x0000FFFFU #define EFUSE_SECURE_VERSION_ERR_S 9 /** EFUSE_SECURE_BOOT_DISABLE_FAST_WAKE_ERR : RO; bitpos: [25]; default: 0; - * Represents the programming error of EFUSE_SECURE_BOOT_DISABLE_FAST_WAKE + * Indicates a programming error of SECURE_BOOT_DISABLE_FAST_WAKE. */ #define EFUSE_SECURE_BOOT_DISABLE_FAST_WAKE_ERR (BIT(25)) #define EFUSE_SECURE_BOOT_DISABLE_FAST_WAKE_ERR_M (EFUSE_SECURE_BOOT_DISABLE_FAST_WAKE_ERR_V << EFUSE_SECURE_BOOT_DISABLE_FAST_WAKE_ERR_S) #define EFUSE_SECURE_BOOT_DISABLE_FAST_WAKE_ERR_V 0x00000001U #define EFUSE_SECURE_BOOT_DISABLE_FAST_WAKE_ERR_S 25 /** EFUSE_HYS_EN_PAD0_ERR : RO; bitpos: [31:26]; default: 0; - * Represents the programming error of EFUSE_HYS_EN_PAD0 + * Indicates a programming error of HYS_EN_PAD0. */ #define EFUSE_HYS_EN_PAD0_ERR 0x0000003FU #define EFUSE_HYS_EN_PAD0_ERR_M (EFUSE_HYS_EN_PAD0_ERR_V << EFUSE_HYS_EN_PAD0_ERR_S) #define EFUSE_HYS_EN_PAD0_ERR_V 0x0000003FU #define EFUSE_HYS_EN_PAD0_ERR_S 26 -/** EFUSE_RD_REPEAT_DATA_ERR4_REG register - * Represents rd_repeat_data_err +/** EFUSE_RD_REPEAT_ERR4_REG register + * Programming error record register 4 of BLOCK0. */ -#define EFUSE_RD_REPEAT_DATA_ERR4_REG (DR_REG_EFUSE_BASE + 0x18c) +#define EFUSE_RD_REPEAT_ERR4_REG (DR_REG_EFUSE_BASE + 0x18c) /** EFUSE_HYS_EN_PAD1_ERR : RO; bitpos: [21:0]; default: 0; - * Represents the programming error of EFUSE_HYS_EN_PAD1 + * Indicates a programming error of HYS_EN_PAD1. */ #define EFUSE_HYS_EN_PAD1_ERR 0x003FFFFFU #define EFUSE_HYS_EN_PAD1_ERR_M (EFUSE_HYS_EN_PAD1_ERR_V << EFUSE_HYS_EN_PAD1_ERR_S) #define EFUSE_HYS_EN_PAD1_ERR_V 0x003FFFFFU #define EFUSE_HYS_EN_PAD1_ERR_S 0 -/** EFUSE_FLASH_LDO_POWER_SEL_ERR : RO; bitpos: [22]; default: 0; - * Represents the programming error of EFUSE_FLASH_LDO_POWER_SEL - */ -#define EFUSE_FLASH_LDO_POWER_SEL_ERR (BIT(22)) -#define EFUSE_FLASH_LDO_POWER_SEL_ERR_M (EFUSE_FLASH_LDO_POWER_SEL_ERR_V << EFUSE_FLASH_LDO_POWER_SEL_ERR_S) -#define EFUSE_FLASH_LDO_POWER_SEL_ERR_V 0x00000001U -#define EFUSE_FLASH_LDO_POWER_SEL_ERR_S 22 - -/** EFUSE_RD_RS_DATA_ERR0_REG register - * Represents rd_rs_data_err - */ -#define EFUSE_RD_RS_DATA_ERR0_REG (DR_REG_EFUSE_BASE + 0x190) -/** EFUSE_RD_MAC_SYS_ERR_NUM : RO; bitpos: [2:0]; default: 0; - * Represents the error number of registers. - * The value of this signal means the number of error bytes in rd_mac_sys - */ -#define EFUSE_RD_MAC_SYS_ERR_NUM 0x00000007U -#define EFUSE_RD_MAC_SYS_ERR_NUM_M (EFUSE_RD_MAC_SYS_ERR_NUM_V << EFUSE_RD_MAC_SYS_ERR_NUM_S) -#define EFUSE_RD_MAC_SYS_ERR_NUM_V 0x00000007U -#define EFUSE_RD_MAC_SYS_ERR_NUM_S 0 -/** EFUSE_RD_MAC_SYS_FAIL : RO; bitpos: [3]; default: 0; - * Represents error status of register. - * 0: Means no failure and that the data of rd_mac_sys is reliable - * 1: Means that programming rd_mac_sys failed and the number of error bytes is over 6. - */ -#define EFUSE_RD_MAC_SYS_FAIL (BIT(3)) -#define EFUSE_RD_MAC_SYS_FAIL_M (EFUSE_RD_MAC_SYS_FAIL_V << EFUSE_RD_MAC_SYS_FAIL_S) -#define EFUSE_RD_MAC_SYS_FAIL_V 0x00000001U -#define EFUSE_RD_MAC_SYS_FAIL_S 3 -/** EFUSE_RD_SYS_PART1_DATA_ERR_NUM : RO; bitpos: [6:4]; default: 0; - * Represents the error number of registers. - * The value of this signal means the number of error bytes in rd_sys_part1_data - */ -#define EFUSE_RD_SYS_PART1_DATA_ERR_NUM 0x00000007U -#define EFUSE_RD_SYS_PART1_DATA_ERR_NUM_M (EFUSE_RD_SYS_PART1_DATA_ERR_NUM_V << EFUSE_RD_SYS_PART1_DATA_ERR_NUM_S) -#define EFUSE_RD_SYS_PART1_DATA_ERR_NUM_V 0x00000007U -#define EFUSE_RD_SYS_PART1_DATA_ERR_NUM_S 4 -/** EFUSE_RD_SYS_PART1_DATA_FAIL : RO; bitpos: [7]; default: 0; - * Represents error status of register. - * 0: Means no failure and that the data of rd_sys_part1_data is reliable - * 1: Means that programming rd_sys_part1_data failed and the number of error bytes is - * over 6. - */ -#define EFUSE_RD_SYS_PART1_DATA_FAIL (BIT(7)) -#define EFUSE_RD_SYS_PART1_DATA_FAIL_M (EFUSE_RD_SYS_PART1_DATA_FAIL_V << EFUSE_RD_SYS_PART1_DATA_FAIL_S) -#define EFUSE_RD_SYS_PART1_DATA_FAIL_V 0x00000001U -#define EFUSE_RD_SYS_PART1_DATA_FAIL_S 7 -/** EFUSE_RD_USR_DATA_ERR_NUM : RO; bitpos: [10:8]; default: 0; - * Represents the error number of registers. - * The value of this signal means the number of error bytes in rd_usr_data - */ -#define EFUSE_RD_USR_DATA_ERR_NUM 0x00000007U -#define EFUSE_RD_USR_DATA_ERR_NUM_M (EFUSE_RD_USR_DATA_ERR_NUM_V << EFUSE_RD_USR_DATA_ERR_NUM_S) -#define EFUSE_RD_USR_DATA_ERR_NUM_V 0x00000007U -#define EFUSE_RD_USR_DATA_ERR_NUM_S 8 -/** EFUSE_RD_USR_DATA_FAIL : RO; bitpos: [11]; default: 0; - * Represents error status of register. - * 0: Means no failure and that the data of rd_usr_data is reliable - * 1: Means that programming rd_usr_data failed and the number of error bytes is over - * 6. - */ -#define EFUSE_RD_USR_DATA_FAIL (BIT(11)) -#define EFUSE_RD_USR_DATA_FAIL_M (EFUSE_RD_USR_DATA_FAIL_V << EFUSE_RD_USR_DATA_FAIL_S) -#define EFUSE_RD_USR_DATA_FAIL_V 0x00000001U -#define EFUSE_RD_USR_DATA_FAIL_S 11 -/** EFUSE_RD_KEY0_DATA_ERR_NUM : RO; bitpos: [14:12]; default: 0; - * Represents the error number of registers. - * The value of this signal means the number of error bytes in rd_key0_data - */ -#define EFUSE_RD_KEY0_DATA_ERR_NUM 0x00000007U -#define EFUSE_RD_KEY0_DATA_ERR_NUM_M (EFUSE_RD_KEY0_DATA_ERR_NUM_V << EFUSE_RD_KEY0_DATA_ERR_NUM_S) -#define EFUSE_RD_KEY0_DATA_ERR_NUM_V 0x00000007U -#define EFUSE_RD_KEY0_DATA_ERR_NUM_S 12 -/** EFUSE_RD_KEY0_DATA_FAIL : RO; bitpos: [15]; default: 0; - * Represents error status of register. - * 0: Means no failure and that the data of rd_key0_data is reliable - * 1: Means that programming rd_key0_data failed and the number of error bytes is over - * 6. - */ -#define EFUSE_RD_KEY0_DATA_FAIL (BIT(15)) -#define EFUSE_RD_KEY0_DATA_FAIL_M (EFUSE_RD_KEY0_DATA_FAIL_V << EFUSE_RD_KEY0_DATA_FAIL_S) -#define EFUSE_RD_KEY0_DATA_FAIL_V 0x00000001U -#define EFUSE_RD_KEY0_DATA_FAIL_S 15 -/** EFUSE_RD_KEY1_DATA_ERR_NUM : RO; bitpos: [18:16]; default: 0; - * Represents the error number of registers. - * The value of this signal means the number of error bytes in rd_key1_data - */ -#define EFUSE_RD_KEY1_DATA_ERR_NUM 0x00000007U -#define EFUSE_RD_KEY1_DATA_ERR_NUM_M (EFUSE_RD_KEY1_DATA_ERR_NUM_V << EFUSE_RD_KEY1_DATA_ERR_NUM_S) -#define EFUSE_RD_KEY1_DATA_ERR_NUM_V 0x00000007U -#define EFUSE_RD_KEY1_DATA_ERR_NUM_S 16 -/** EFUSE_RD_KEY1_DATA_FAIL : RO; bitpos: [19]; default: 0; - * Represents error status of register. - * 0: Means no failure and that the data of rd_key1_data is reliable - * 1: Means that programming rd_key1_data failed and the number of error bytes is over - * 6. - */ -#define EFUSE_RD_KEY1_DATA_FAIL (BIT(19)) -#define EFUSE_RD_KEY1_DATA_FAIL_M (EFUSE_RD_KEY1_DATA_FAIL_V << EFUSE_RD_KEY1_DATA_FAIL_S) -#define EFUSE_RD_KEY1_DATA_FAIL_V 0x00000001U -#define EFUSE_RD_KEY1_DATA_FAIL_S 19 -/** EFUSE_RD_KEY2_DATA_ERR_NUM : RO; bitpos: [22:20]; default: 0; - * Represents the error number of registers. - * The value of this signal means the number of error bytes in rd_key2_data - */ -#define EFUSE_RD_KEY2_DATA_ERR_NUM 0x00000007U -#define EFUSE_RD_KEY2_DATA_ERR_NUM_M (EFUSE_RD_KEY2_DATA_ERR_NUM_V << EFUSE_RD_KEY2_DATA_ERR_NUM_S) -#define EFUSE_RD_KEY2_DATA_ERR_NUM_V 0x00000007U -#define EFUSE_RD_KEY2_DATA_ERR_NUM_S 20 -/** EFUSE_RD_KEY2_DATA_FAIL : RO; bitpos: [23]; default: 0; - * Represents error status of register. - * 0: Means no failure and that the data of rd_key2_data is reliable - * 1: Means that programming rd_key2_data failed and the number of error bytes is over - * 6. - */ -#define EFUSE_RD_KEY2_DATA_FAIL (BIT(23)) -#define EFUSE_RD_KEY2_DATA_FAIL_M (EFUSE_RD_KEY2_DATA_FAIL_V << EFUSE_RD_KEY2_DATA_FAIL_S) -#define EFUSE_RD_KEY2_DATA_FAIL_V 0x00000001U -#define EFUSE_RD_KEY2_DATA_FAIL_S 23 -/** EFUSE_RD_KEY3_DATA_ERR_NUM : RO; bitpos: [26:24]; default: 0; - * Represents the error number of registers. - * The value of this signal means the number of error bytes in rd_key3_data - */ -#define EFUSE_RD_KEY3_DATA_ERR_NUM 0x00000007U -#define EFUSE_RD_KEY3_DATA_ERR_NUM_M (EFUSE_RD_KEY3_DATA_ERR_NUM_V << EFUSE_RD_KEY3_DATA_ERR_NUM_S) -#define EFUSE_RD_KEY3_DATA_ERR_NUM_V 0x00000007U -#define EFUSE_RD_KEY3_DATA_ERR_NUM_S 24 -/** EFUSE_RD_KEY3_DATA_FAIL : RO; bitpos: [27]; default: 0; - * Represents error status of register. - * 0: Means no failure and that the data of rd_key3_data is reliable - * 1: Means that programming rd_key3_data failed and the number of error bytes is over - * 6. - */ -#define EFUSE_RD_KEY3_DATA_FAIL (BIT(27)) -#define EFUSE_RD_KEY3_DATA_FAIL_M (EFUSE_RD_KEY3_DATA_FAIL_V << EFUSE_RD_KEY3_DATA_FAIL_S) -#define EFUSE_RD_KEY3_DATA_FAIL_V 0x00000001U -#define EFUSE_RD_KEY3_DATA_FAIL_S 27 -/** EFUSE_RD_KEY4_DATA_ERR_NUM : RO; bitpos: [30:28]; default: 0; - * Represents the error number of registers. - * The value of this signal means the number of error bytes in rd_key4_data - */ -#define EFUSE_RD_KEY4_DATA_ERR_NUM 0x00000007U -#define EFUSE_RD_KEY4_DATA_ERR_NUM_M (EFUSE_RD_KEY4_DATA_ERR_NUM_V << EFUSE_RD_KEY4_DATA_ERR_NUM_S) -#define EFUSE_RD_KEY4_DATA_ERR_NUM_V 0x00000007U -#define EFUSE_RD_KEY4_DATA_ERR_NUM_S 28 -/** EFUSE_RD_KEY4_DATA_FAIL : RO; bitpos: [31]; default: 0; - * Represents error status of register. - * 0: Means no failure and that the data of rd_key4_data is reliable - * 1: Means that programming rd_key4_data failed and the number of error bytes is over - * 6. - */ -#define EFUSE_RD_KEY4_DATA_FAIL (BIT(31)) -#define EFUSE_RD_KEY4_DATA_FAIL_M (EFUSE_RD_KEY4_DATA_FAIL_V << EFUSE_RD_KEY4_DATA_FAIL_S) -#define EFUSE_RD_KEY4_DATA_FAIL_V 0x00000001U -#define EFUSE_RD_KEY4_DATA_FAIL_S 31 - -/** EFUSE_RD_RS_DATA_ERR1_REG register - * Represents rd_rs_data_err - */ -#define EFUSE_RD_RS_DATA_ERR1_REG (DR_REG_EFUSE_BASE + 0x194) -/** EFUSE_RD_KEY5_DATA_ERR_NUM : RO; bitpos: [2:0]; default: 0; - * Represents the error number of registers. - * The value of this signal means the number of error bytes in rd_key5_data - */ -#define EFUSE_RD_KEY5_DATA_ERR_NUM 0x00000007U -#define EFUSE_RD_KEY5_DATA_ERR_NUM_M (EFUSE_RD_KEY5_DATA_ERR_NUM_V << EFUSE_RD_KEY5_DATA_ERR_NUM_S) -#define EFUSE_RD_KEY5_DATA_ERR_NUM_V 0x00000007U -#define EFUSE_RD_KEY5_DATA_ERR_NUM_S 0 -/** EFUSE_RD_KEY5_DATA_FAIL : RO; bitpos: [3]; default: 0; - * Represents error status of register. - * 0: Means no failure and that the data of rd_key5_data is reliable - * 1: Means that programming rd_key5_data failed and the number of error bytes is over - * 6. - */ -#define EFUSE_RD_KEY5_DATA_FAIL (BIT(3)) -#define EFUSE_RD_KEY5_DATA_FAIL_M (EFUSE_RD_KEY5_DATA_FAIL_V << EFUSE_RD_KEY5_DATA_FAIL_S) -#define EFUSE_RD_KEY5_DATA_FAIL_V 0x00000001U -#define EFUSE_RD_KEY5_DATA_FAIL_S 3 -/** EFUSE_RD_SYS_PART2_DATA_ERR_NUM : RO; bitpos: [6:4]; default: 0; - * Represents the error number of registers. - * The value of this signal means the number of error bytes in rd_sys_part2_data - */ -#define EFUSE_RD_SYS_PART2_DATA_ERR_NUM 0x00000007U -#define EFUSE_RD_SYS_PART2_DATA_ERR_NUM_M (EFUSE_RD_SYS_PART2_DATA_ERR_NUM_V << EFUSE_RD_SYS_PART2_DATA_ERR_NUM_S) -#define EFUSE_RD_SYS_PART2_DATA_ERR_NUM_V 0x00000007U -#define EFUSE_RD_SYS_PART2_DATA_ERR_NUM_S 4 -/** EFUSE_RD_SYS_PART2_DATA_FAIL : RO; bitpos: [7]; default: 0; - * Represents error status of register. - * 0: Means no failure and that the data of rd_sys_part2_data is reliable - * 1: Means that programming rd_sys_part2_data failed and the number of error bytes is - * over 6. - */ -#define EFUSE_RD_SYS_PART2_DATA_FAIL (BIT(7)) -#define EFUSE_RD_SYS_PART2_DATA_FAIL_M (EFUSE_RD_SYS_PART2_DATA_FAIL_V << EFUSE_RD_SYS_PART2_DATA_FAIL_S) -#define EFUSE_RD_SYS_PART2_DATA_FAIL_V 0x00000001U -#define EFUSE_RD_SYS_PART2_DATA_FAIL_S 7 - -/** EFUSE_DATE_REG register - * eFuse version register. +/** EFUSE_RPT4_RESERVED4_ERR_1 : RO; bitpos: [23:22]; default: 0; + * Reserved. */ -#define EFUSE_DATE_REG (DR_REG_EFUSE_BASE + 0x198) -/** EFUSE_DATE : R/W; bitpos: [27:0]; default: 37814560; - * Represents eFuse version. Date:2024-10-12 12:09:57, - * ScriptRev:892332a1019d3a17987b08c6835edce28f46e261 +#define EFUSE_RPT4_RESERVED4_ERR_1 0x00000003U +#define EFUSE_RPT4_RESERVED4_ERR_1_M (EFUSE_RPT4_RESERVED4_ERR_1_V << EFUSE_RPT4_RESERVED4_ERR_1_S) +#define EFUSE_RPT4_RESERVED4_ERR_1_V 0x00000003U +#define EFUSE_RPT4_RESERVED4_ERR_1_S 22 +/** EFUSE_RPT4_RESERVED4_ERR_0 : RO; bitpos: [31:24]; default: 0; + * Reserved. */ -#define EFUSE_DATE 0x0FFFFFFFU -#define EFUSE_DATE_M (EFUSE_DATE_V << EFUSE_DATE_S) -#define EFUSE_DATE_V 0x0FFFFFFFU -#define EFUSE_DATE_S 0 +#define EFUSE_RPT4_RESERVED4_ERR_0 0x000000FFU +#define EFUSE_RPT4_RESERVED4_ERR_0_M (EFUSE_RPT4_RESERVED4_ERR_0_V << EFUSE_RPT4_RESERVED4_ERR_0_S) +#define EFUSE_RPT4_RESERVED4_ERR_0_V 0x000000FFU +#define EFUSE_RPT4_RESERVED4_ERR_0_S 24 + +/** EFUSE_RD_RS_ERR0_REG register + * Programming error record register 0 of BLOCK1-10. + */ +#define EFUSE_RD_RS_ERR0_REG (DR_REG_EFUSE_BASE + 0x1c0) +/** EFUSE_MAC_SPI_8M_ERR_NUM : RO; bitpos: [2:0]; default: 0; + * The value of this signal means the number of error bytes. + */ +#define EFUSE_MAC_SPI_8M_ERR_NUM 0x00000007U +#define EFUSE_MAC_SPI_8M_ERR_NUM_M (EFUSE_MAC_SPI_8M_ERR_NUM_V << EFUSE_MAC_SPI_8M_ERR_NUM_S) +#define EFUSE_MAC_SPI_8M_ERR_NUM_V 0x00000007U +#define EFUSE_MAC_SPI_8M_ERR_NUM_S 0 +/** EFUSE_MAC_SPI_8M_FAIL : RO; bitpos: [3]; default: 0; + * 0: Means no failure and that the data of MAC_SPI_8M is reliable 1: Means that + * programming user data failed and the number of error bytes is over 6. + */ +#define EFUSE_MAC_SPI_8M_FAIL (BIT(3)) +#define EFUSE_MAC_SPI_8M_FAIL_M (EFUSE_MAC_SPI_8M_FAIL_V << EFUSE_MAC_SPI_8M_FAIL_S) +#define EFUSE_MAC_SPI_8M_FAIL_V 0x00000001U +#define EFUSE_MAC_SPI_8M_FAIL_S 3 +/** EFUSE_SYS_PART1_NUM : RO; bitpos: [6:4]; default: 0; + * The value of this signal means the number of error bytes. + */ +#define EFUSE_SYS_PART1_NUM 0x00000007U +#define EFUSE_SYS_PART1_NUM_M (EFUSE_SYS_PART1_NUM_V << EFUSE_SYS_PART1_NUM_S) +#define EFUSE_SYS_PART1_NUM_V 0x00000007U +#define EFUSE_SYS_PART1_NUM_S 4 +/** EFUSE_SYS_PART1_FAIL : RO; bitpos: [7]; default: 0; + * 0: Means no failure and that the data of system part1 is reliable 1: Means that + * programming user data failed and the number of error bytes is over 6. + */ +#define EFUSE_SYS_PART1_FAIL (BIT(7)) +#define EFUSE_SYS_PART1_FAIL_M (EFUSE_SYS_PART1_FAIL_V << EFUSE_SYS_PART1_FAIL_S) +#define EFUSE_SYS_PART1_FAIL_V 0x00000001U +#define EFUSE_SYS_PART1_FAIL_S 7 +/** EFUSE_USR_DATA_ERR_NUM : RO; bitpos: [10:8]; default: 0; + * The value of this signal means the number of error bytes. + */ +#define EFUSE_USR_DATA_ERR_NUM 0x00000007U +#define EFUSE_USR_DATA_ERR_NUM_M (EFUSE_USR_DATA_ERR_NUM_V << EFUSE_USR_DATA_ERR_NUM_S) +#define EFUSE_USR_DATA_ERR_NUM_V 0x00000007U +#define EFUSE_USR_DATA_ERR_NUM_S 8 +/** EFUSE_USR_DATA_FAIL : RO; bitpos: [11]; default: 0; + * 0: Means no failure and that the user data is reliable 1: Means that programming + * user data failed and the number of error bytes is over 6. + */ +#define EFUSE_USR_DATA_FAIL (BIT(11)) +#define EFUSE_USR_DATA_FAIL_M (EFUSE_USR_DATA_FAIL_V << EFUSE_USR_DATA_FAIL_S) +#define EFUSE_USR_DATA_FAIL_V 0x00000001U +#define EFUSE_USR_DATA_FAIL_S 11 +/** EFUSE_KEY0_ERR_NUM : RO; bitpos: [14:12]; default: 0; + * The value of this signal means the number of error bytes. + */ +#define EFUSE_KEY0_ERR_NUM 0x00000007U +#define EFUSE_KEY0_ERR_NUM_M (EFUSE_KEY0_ERR_NUM_V << EFUSE_KEY0_ERR_NUM_S) +#define EFUSE_KEY0_ERR_NUM_V 0x00000007U +#define EFUSE_KEY0_ERR_NUM_S 12 +/** EFUSE_KEY0_FAIL : RO; bitpos: [15]; default: 0; + * 0: Means no failure and that the data of key0 is reliable 1: Means that programming + * key0 failed and the number of error bytes is over 6. + */ +#define EFUSE_KEY0_FAIL (BIT(15)) +#define EFUSE_KEY0_FAIL_M (EFUSE_KEY0_FAIL_V << EFUSE_KEY0_FAIL_S) +#define EFUSE_KEY0_FAIL_V 0x00000001U +#define EFUSE_KEY0_FAIL_S 15 +/** EFUSE_KEY1_ERR_NUM : RO; bitpos: [18:16]; default: 0; + * The value of this signal means the number of error bytes. + */ +#define EFUSE_KEY1_ERR_NUM 0x00000007U +#define EFUSE_KEY1_ERR_NUM_M (EFUSE_KEY1_ERR_NUM_V << EFUSE_KEY1_ERR_NUM_S) +#define EFUSE_KEY1_ERR_NUM_V 0x00000007U +#define EFUSE_KEY1_ERR_NUM_S 16 +/** EFUSE_KEY1_FAIL : RO; bitpos: [19]; default: 0; + * 0: Means no failure and that the data of key1 is reliable 1: Means that programming + * key1 failed and the number of error bytes is over 6. + */ +#define EFUSE_KEY1_FAIL (BIT(19)) +#define EFUSE_KEY1_FAIL_M (EFUSE_KEY1_FAIL_V << EFUSE_KEY1_FAIL_S) +#define EFUSE_KEY1_FAIL_V 0x00000001U +#define EFUSE_KEY1_FAIL_S 19 +/** EFUSE_KEY2_ERR_NUM : RO; bitpos: [22:20]; default: 0; + * The value of this signal means the number of error bytes. + */ +#define EFUSE_KEY2_ERR_NUM 0x00000007U +#define EFUSE_KEY2_ERR_NUM_M (EFUSE_KEY2_ERR_NUM_V << EFUSE_KEY2_ERR_NUM_S) +#define EFUSE_KEY2_ERR_NUM_V 0x00000007U +#define EFUSE_KEY2_ERR_NUM_S 20 +/** EFUSE_KEY2_FAIL : RO; bitpos: [23]; default: 0; + * 0: Means no failure and that the data of key2 is reliable 1: Means that programming + * key2 failed and the number of error bytes is over 6. + */ +#define EFUSE_KEY2_FAIL (BIT(23)) +#define EFUSE_KEY2_FAIL_M (EFUSE_KEY2_FAIL_V << EFUSE_KEY2_FAIL_S) +#define EFUSE_KEY2_FAIL_V 0x00000001U +#define EFUSE_KEY2_FAIL_S 23 +/** EFUSE_KEY3_ERR_NUM : RO; bitpos: [26:24]; default: 0; + * The value of this signal means the number of error bytes. + */ +#define EFUSE_KEY3_ERR_NUM 0x00000007U +#define EFUSE_KEY3_ERR_NUM_M (EFUSE_KEY3_ERR_NUM_V << EFUSE_KEY3_ERR_NUM_S) +#define EFUSE_KEY3_ERR_NUM_V 0x00000007U +#define EFUSE_KEY3_ERR_NUM_S 24 +/** EFUSE_KEY3_FAIL : RO; bitpos: [27]; default: 0; + * 0: Means no failure and that the data of key3 is reliable 1: Means that programming + * key3 failed and the number of error bytes is over 6. + */ +#define EFUSE_KEY3_FAIL (BIT(27)) +#define EFUSE_KEY3_FAIL_M (EFUSE_KEY3_FAIL_V << EFUSE_KEY3_FAIL_S) +#define EFUSE_KEY3_FAIL_V 0x00000001U +#define EFUSE_KEY3_FAIL_S 27 +/** EFUSE_KEY4_ERR_NUM : RO; bitpos: [30:28]; default: 0; + * The value of this signal means the number of error bytes. + */ +#define EFUSE_KEY4_ERR_NUM 0x00000007U +#define EFUSE_KEY4_ERR_NUM_M (EFUSE_KEY4_ERR_NUM_V << EFUSE_KEY4_ERR_NUM_S) +#define EFUSE_KEY4_ERR_NUM_V 0x00000007U +#define EFUSE_KEY4_ERR_NUM_S 28 +/** EFUSE_KEY4_FAIL : RO; bitpos: [31]; default: 0; + * 0: Means no failure and that the data of key4 is reliable 1: Means that programming + * key4 failed and the number of error bytes is over 6. + */ +#define EFUSE_KEY4_FAIL (BIT(31)) +#define EFUSE_KEY4_FAIL_M (EFUSE_KEY4_FAIL_V << EFUSE_KEY4_FAIL_S) +#define EFUSE_KEY4_FAIL_V 0x00000001U +#define EFUSE_KEY4_FAIL_S 31 + +/** EFUSE_RD_RS_ERR1_REG register + * Programming error record register 1 of BLOCK1-10. + */ +#define EFUSE_RD_RS_ERR1_REG (DR_REG_EFUSE_BASE + 0x1c4) +/** EFUSE_KEY5_ERR_NUM : RO; bitpos: [2:0]; default: 0; + * The value of this signal means the number of error bytes. + */ +#define EFUSE_KEY5_ERR_NUM 0x00000007U +#define EFUSE_KEY5_ERR_NUM_M (EFUSE_KEY5_ERR_NUM_V << EFUSE_KEY5_ERR_NUM_S) +#define EFUSE_KEY5_ERR_NUM_V 0x00000007U +#define EFUSE_KEY5_ERR_NUM_S 0 +/** EFUSE_KEY5_FAIL : RO; bitpos: [3]; default: 0; + * 0: Means no failure and that the data of key5 is reliable 1: Means that programming + * key5 failed and the number of error bytes is over 6. + */ +#define EFUSE_KEY5_FAIL (BIT(3)) +#define EFUSE_KEY5_FAIL_M (EFUSE_KEY5_FAIL_V << EFUSE_KEY5_FAIL_S) +#define EFUSE_KEY5_FAIL_V 0x00000001U +#define EFUSE_KEY5_FAIL_S 3 +/** EFUSE_SYS_PART2_ERR_NUM : RO; bitpos: [6:4]; default: 0; + * The value of this signal means the number of error bytes. + */ +#define EFUSE_SYS_PART2_ERR_NUM 0x00000007U +#define EFUSE_SYS_PART2_ERR_NUM_M (EFUSE_SYS_PART2_ERR_NUM_V << EFUSE_SYS_PART2_ERR_NUM_S) +#define EFUSE_SYS_PART2_ERR_NUM_V 0x00000007U +#define EFUSE_SYS_PART2_ERR_NUM_S 4 +/** EFUSE_SYS_PART2_FAIL : RO; bitpos: [7]; default: 0; + * 0: Means no failure and that the data of system part2 is reliable 1: Means that + * programming user data failed and the number of error bytes is over 6. + */ +#define EFUSE_SYS_PART2_FAIL (BIT(7)) +#define EFUSE_SYS_PART2_FAIL_M (EFUSE_SYS_PART2_FAIL_V << EFUSE_SYS_PART2_FAIL_S) +#define EFUSE_SYS_PART2_FAIL_V 0x00000001U +#define EFUSE_SYS_PART2_FAIL_S 7 /** EFUSE_CLK_REG register * eFuse clcok configuration register. */ #define EFUSE_CLK_REG (DR_REG_EFUSE_BASE + 0x1c8) /** EFUSE_MEM_FORCE_PD : R/W; bitpos: [0]; default: 0; - * Configures whether to force power down eFuse SRAM. - * 1: Force - * 0: No effect + * Set this bit to force eFuse SRAM into power-saving mode. */ #define EFUSE_MEM_FORCE_PD (BIT(0)) #define EFUSE_MEM_FORCE_PD_M (EFUSE_MEM_FORCE_PD_V << EFUSE_MEM_FORCE_PD_S) #define EFUSE_MEM_FORCE_PD_V 0x00000001U #define EFUSE_MEM_FORCE_PD_S 0 /** EFUSE_MEM_CLK_FORCE_ON : R/W; bitpos: [1]; default: 1; - * Configures whether to force activate clock signal of eFuse SRAM. - * 1: Force activate - * 0: No effect + * Set this bit and force to activate clock signal of eFuse SRAM. */ #define EFUSE_MEM_CLK_FORCE_ON (BIT(1)) #define EFUSE_MEM_CLK_FORCE_ON_M (EFUSE_MEM_CLK_FORCE_ON_V << EFUSE_MEM_CLK_FORCE_ON_S) #define EFUSE_MEM_CLK_FORCE_ON_V 0x00000001U #define EFUSE_MEM_CLK_FORCE_ON_S 1 /** EFUSE_MEM_FORCE_PU : R/W; bitpos: [2]; default: 0; - * Configures whether to force power up eFuse SRAM. - * 1: Force - * 0: No effect + * Set this bit to force eFuse SRAM into working mode. */ #define EFUSE_MEM_FORCE_PU (BIT(2)) #define EFUSE_MEM_FORCE_PU_M (EFUSE_MEM_FORCE_PU_V << EFUSE_MEM_FORCE_PU_S) #define EFUSE_MEM_FORCE_PU_V 0x00000001U #define EFUSE_MEM_FORCE_PU_S 2 /** EFUSE_CLK_EN : R/W; bitpos: [16]; default: 0; - * Configures whether to force enable eFuse register configuration clock signal. - * 1: Force - * 0: The clock is enabled only during the reading and writing of registers + * Set this bit to force enable eFuse register configuration clock signal. */ #define EFUSE_CLK_EN (BIT(16)) #define EFUSE_CLK_EN_M (EFUSE_CLK_EN_V << EFUSE_CLK_EN_S) @@ -2252,91 +2359,109 @@ extern "C" { */ #define EFUSE_CONF_REG (DR_REG_EFUSE_BASE + 0x1cc) /** EFUSE_OP_CODE : R/W; bitpos: [15:0]; default: 0; - * Configures operation command type. - * 0x5A5A: Program operation command - * 0x5AA5: Read operation command - * Other values: No effect + * 0x5A5A: programming operation command 0x5AA5: read operation command. */ #define EFUSE_OP_CODE 0x0000FFFFU #define EFUSE_OP_CODE_M (EFUSE_OP_CODE_V << EFUSE_OP_CODE_S) #define EFUSE_OP_CODE_V 0x0000FFFFU #define EFUSE_OP_CODE_S 0 -/** EFUSE_CFG_ECDSA_L_BLK : R/W; bitpos: [19:16]; default: 0; - * Configures which block to use for ECDSA key low part output. +/** EFUSE_CFG_ECDSA_BLK : R/W; bitpos: [19:16]; default: 0; + * Configures which block to use for ECDSA key output. */ -#define EFUSE_CFG_ECDSA_L_BLK 0x0000000FU -#define EFUSE_CFG_ECDSA_L_BLK_M (EFUSE_CFG_ECDSA_L_BLK_V << EFUSE_CFG_ECDSA_L_BLK_S) -#define EFUSE_CFG_ECDSA_L_BLK_V 0x0000000FU -#define EFUSE_CFG_ECDSA_L_BLK_S 16 -/** EFUSE_CFG_ECDSA_H_BLK : R/W; bitpos: [23:20]; default: 0; - * Configures which block to use for ECDSA key high part output. - */ -#define EFUSE_CFG_ECDSA_H_BLK 0x0000000FU -#define EFUSE_CFG_ECDSA_H_BLK_M (EFUSE_CFG_ECDSA_H_BLK_V << EFUSE_CFG_ECDSA_H_BLK_S) -#define EFUSE_CFG_ECDSA_H_BLK_V 0x0000000FU -#define EFUSE_CFG_ECDSA_H_BLK_S 20 +#define EFUSE_CFG_ECDSA_BLK 0x0000000FU +#define EFUSE_CFG_ECDSA_BLK_M (EFUSE_CFG_ECDSA_BLK_V << EFUSE_CFG_ECDSA_BLK_S) +#define EFUSE_CFG_ECDSA_BLK_V 0x0000000FU +#define EFUSE_CFG_ECDSA_BLK_S 16 /** EFUSE_STATUS_REG register * eFuse status register. */ #define EFUSE_STATUS_REG (DR_REG_EFUSE_BASE + 0x1d0) /** EFUSE_STATE : RO; bitpos: [3:0]; default: 0; - * Represents the state of the eFuse state machine. - * 0: Reset state, the initial state after power-up - * 1: Idle state - * Other values: Non-idle state + * Indicates the state of the eFuse state machine. */ #define EFUSE_STATE 0x0000000FU #define EFUSE_STATE_M (EFUSE_STATE_V << EFUSE_STATE_S) #define EFUSE_STATE_V 0x0000000FU #define EFUSE_STATE_S 0 +/** EFUSE_OTP_LOAD_SW : RO; bitpos: [4]; default: 0; + * The value of OTP_LOAD_SW. + */ +#define EFUSE_OTP_LOAD_SW (BIT(4)) +#define EFUSE_OTP_LOAD_SW_M (EFUSE_OTP_LOAD_SW_V << EFUSE_OTP_LOAD_SW_S) +#define EFUSE_OTP_LOAD_SW_V 0x00000001U +#define EFUSE_OTP_LOAD_SW_S 4 +/** EFUSE_OTP_VDDQ_C_SYNC2 : RO; bitpos: [5]; default: 0; + * The value of OTP_VDDQ_C_SYNC2. + */ +#define EFUSE_OTP_VDDQ_C_SYNC2 (BIT(5)) +#define EFUSE_OTP_VDDQ_C_SYNC2_M (EFUSE_OTP_VDDQ_C_SYNC2_V << EFUSE_OTP_VDDQ_C_SYNC2_S) +#define EFUSE_OTP_VDDQ_C_SYNC2_V 0x00000001U +#define EFUSE_OTP_VDDQ_C_SYNC2_S 5 +/** EFUSE_OTP_STROBE_SW : RO; bitpos: [6]; default: 0; + * The value of OTP_STROBE_SW. + */ +#define EFUSE_OTP_STROBE_SW (BIT(6)) +#define EFUSE_OTP_STROBE_SW_M (EFUSE_OTP_STROBE_SW_V << EFUSE_OTP_STROBE_SW_S) +#define EFUSE_OTP_STROBE_SW_V 0x00000001U +#define EFUSE_OTP_STROBE_SW_S 6 +/** EFUSE_OTP_CSB_SW : RO; bitpos: [7]; default: 0; + * The value of OTP_CSB_SW. + */ +#define EFUSE_OTP_CSB_SW (BIT(7)) +#define EFUSE_OTP_CSB_SW_M (EFUSE_OTP_CSB_SW_V << EFUSE_OTP_CSB_SW_S) +#define EFUSE_OTP_CSB_SW_V 0x00000001U +#define EFUSE_OTP_CSB_SW_S 7 +/** EFUSE_OTP_PGENB_SW : RO; bitpos: [8]; default: 0; + * The value of OTP_PGENB_SW. + */ +#define EFUSE_OTP_PGENB_SW (BIT(8)) +#define EFUSE_OTP_PGENB_SW_M (EFUSE_OTP_PGENB_SW_V << EFUSE_OTP_PGENB_SW_S) +#define EFUSE_OTP_PGENB_SW_V 0x00000001U +#define EFUSE_OTP_PGENB_SW_S 8 +/** EFUSE_OTP_VDDQ_IS_SW : RO; bitpos: [9]; default: 0; + * The value of OTP_VDDQ_IS_SW. + */ +#define EFUSE_OTP_VDDQ_IS_SW (BIT(9)) +#define EFUSE_OTP_VDDQ_IS_SW_M (EFUSE_OTP_VDDQ_IS_SW_V << EFUSE_OTP_VDDQ_IS_SW_S) +#define EFUSE_OTP_VDDQ_IS_SW_V 0x00000001U +#define EFUSE_OTP_VDDQ_IS_SW_S 9 /** EFUSE_BLK0_VALID_BIT_CNT : RO; bitpos: [19:10]; default: 0; - * Represents the number of block valid bit. + * Indicates the number of block valid bit. */ #define EFUSE_BLK0_VALID_BIT_CNT 0x000003FFU #define EFUSE_BLK0_VALID_BIT_CNT_M (EFUSE_BLK0_VALID_BIT_CNT_V << EFUSE_BLK0_VALID_BIT_CNT_S) #define EFUSE_BLK0_VALID_BIT_CNT_V 0x000003FFU #define EFUSE_BLK0_VALID_BIT_CNT_S 10 -/** EFUSE_CUR_ECDSA_L_BLK : RO; bitpos: [23:20]; default: 0; - * Represents which block is used for ECDSA key low part output. - */ -#define EFUSE_CUR_ECDSA_L_BLK 0x0000000FU -#define EFUSE_CUR_ECDSA_L_BLK_M (EFUSE_CUR_ECDSA_L_BLK_V << EFUSE_CUR_ECDSA_L_BLK_S) -#define EFUSE_CUR_ECDSA_L_BLK_V 0x0000000FU -#define EFUSE_CUR_ECDSA_L_BLK_S 20 -/** EFUSE_CUR_ECDSA_H_BLK : RO; bitpos: [27:24]; default: 0; - * Represents which block is used for ECDSA key high part output. +/** EFUSE_CUR_ECDSA_BLK : RO; bitpos: [23:20]; default: 0; + * Indicates which block is used for ECDSA key output. */ -#define EFUSE_CUR_ECDSA_H_BLK 0x0000000FU -#define EFUSE_CUR_ECDSA_H_BLK_M (EFUSE_CUR_ECDSA_H_BLK_V << EFUSE_CUR_ECDSA_H_BLK_S) -#define EFUSE_CUR_ECDSA_H_BLK_V 0x0000000FU -#define EFUSE_CUR_ECDSA_H_BLK_S 24 +#define EFUSE_CUR_ECDSA_BLK 0x0000000FU +#define EFUSE_CUR_ECDSA_BLK_M (EFUSE_CUR_ECDSA_BLK_V << EFUSE_CUR_ECDSA_BLK_S) +#define EFUSE_CUR_ECDSA_BLK_V 0x0000000FU +#define EFUSE_CUR_ECDSA_BLK_S 20 /** EFUSE_CMD_REG register * eFuse command register. */ #define EFUSE_CMD_REG (DR_REG_EFUSE_BASE + 0x1d4) /** EFUSE_READ_CMD : R/W/SC; bitpos: [0]; default: 0; - * Configures whether to send read commands. - * 1: Send - * 0: No effect + * Set this bit to send read command. */ #define EFUSE_READ_CMD (BIT(0)) #define EFUSE_READ_CMD_M (EFUSE_READ_CMD_V << EFUSE_READ_CMD_S) #define EFUSE_READ_CMD_V 0x00000001U #define EFUSE_READ_CMD_S 0 /** EFUSE_PGM_CMD : R/W/SC; bitpos: [1]; default: 0; - * Configures whether to send programming commands. - * 1: Send - * 0: No effect + * Set this bit to send programming command. */ #define EFUSE_PGM_CMD (BIT(1)) #define EFUSE_PGM_CMD_M (EFUSE_PGM_CMD_V << EFUSE_PGM_CMD_S) #define EFUSE_PGM_CMD_V 0x00000001U #define EFUSE_PGM_CMD_S 1 /** EFUSE_BLK_NUM : R/W; bitpos: [5:2]; default: 0; - * Configures the serial number of the block to be programmed. Value 0-10 corresponds - * to block number 0-10, respectively. + * The serial number of the block to be programmed. Value 0-10 corresponds to block + * number 0-10, respectively. */ #define EFUSE_BLK_NUM 0x0000000FU #define EFUSE_BLK_NUM_M (EFUSE_BLK_NUM_V << EFUSE_BLK_NUM_S) @@ -2348,14 +2473,14 @@ extern "C" { */ #define EFUSE_INT_RAW_REG (DR_REG_EFUSE_BASE + 0x1d8) /** EFUSE_READ_DONE_INT_RAW : R/SS/WTC; bitpos: [0]; default: 0; - * The raw interrupt status of EFUSE_READ_DONE_INT. + * The raw bit signal for read_done interrupt. */ #define EFUSE_READ_DONE_INT_RAW (BIT(0)) #define EFUSE_READ_DONE_INT_RAW_M (EFUSE_READ_DONE_INT_RAW_V << EFUSE_READ_DONE_INT_RAW_S) #define EFUSE_READ_DONE_INT_RAW_V 0x00000001U #define EFUSE_READ_DONE_INT_RAW_S 0 /** EFUSE_PGM_DONE_INT_RAW : R/SS/WTC; bitpos: [1]; default: 0; - * The raw interrupt status of EFUSE_PGM_DONE_INT. + * The raw bit signal for pgm_done interrupt. */ #define EFUSE_PGM_DONE_INT_RAW (BIT(1)) #define EFUSE_PGM_DONE_INT_RAW_M (EFUSE_PGM_DONE_INT_RAW_V << EFUSE_PGM_DONE_INT_RAW_S) @@ -2367,14 +2492,14 @@ extern "C" { */ #define EFUSE_INT_ST_REG (DR_REG_EFUSE_BASE + 0x1dc) /** EFUSE_READ_DONE_INT_ST : RO; bitpos: [0]; default: 0; - * The masked interrupt status of EFUSE_READ_DONE_INT. + * The status signal for read_done interrupt. */ #define EFUSE_READ_DONE_INT_ST (BIT(0)) #define EFUSE_READ_DONE_INT_ST_M (EFUSE_READ_DONE_INT_ST_V << EFUSE_READ_DONE_INT_ST_S) #define EFUSE_READ_DONE_INT_ST_V 0x00000001U #define EFUSE_READ_DONE_INT_ST_S 0 /** EFUSE_PGM_DONE_INT_ST : RO; bitpos: [1]; default: 0; - * The masked interrupt status of EFUSE_PGM_DONE_INT. + * The status signal for pgm_done interrupt. */ #define EFUSE_PGM_DONE_INT_ST (BIT(1)) #define EFUSE_PGM_DONE_INT_ST_M (EFUSE_PGM_DONE_INT_ST_V << EFUSE_PGM_DONE_INT_ST_S) @@ -2386,14 +2511,14 @@ extern "C" { */ #define EFUSE_INT_ENA_REG (DR_REG_EFUSE_BASE + 0x1e0) /** EFUSE_READ_DONE_INT_ENA : R/W; bitpos: [0]; default: 0; - * Write 1 to enable EFUSE_READ_DONE_INT. + * The enable signal for read_done interrupt. */ #define EFUSE_READ_DONE_INT_ENA (BIT(0)) #define EFUSE_READ_DONE_INT_ENA_M (EFUSE_READ_DONE_INT_ENA_V << EFUSE_READ_DONE_INT_ENA_S) #define EFUSE_READ_DONE_INT_ENA_V 0x00000001U #define EFUSE_READ_DONE_INT_ENA_S 0 /** EFUSE_PGM_DONE_INT_ENA : R/W; bitpos: [1]; default: 0; - * Write 1 to enable EFUSE_PGM_DONE_INT. + * The enable signal for pgm_done interrupt. */ #define EFUSE_PGM_DONE_INT_ENA (BIT(1)) #define EFUSE_PGM_DONE_INT_ENA_M (EFUSE_PGM_DONE_INT_ENA_V << EFUSE_PGM_DONE_INT_ENA_S) @@ -2405,14 +2530,14 @@ extern "C" { */ #define EFUSE_INT_CLR_REG (DR_REG_EFUSE_BASE + 0x1e4) /** EFUSE_READ_DONE_INT_CLR : WT; bitpos: [0]; default: 0; - * Write 1 to clear EFUSE_READ_DONE_INT. + * The clear signal for read_done interrupt. */ #define EFUSE_READ_DONE_INT_CLR (BIT(0)) #define EFUSE_READ_DONE_INT_CLR_M (EFUSE_READ_DONE_INT_CLR_V << EFUSE_READ_DONE_INT_CLR_S) #define EFUSE_READ_DONE_INT_CLR_V 0x00000001U #define EFUSE_READ_DONE_INT_CLR_S 0 /** EFUSE_PGM_DONE_INT_CLR : WT; bitpos: [1]; default: 0; - * Write 1 to clear EFUSE_PGM_DONE_INT. + * The clear signal for pgm_done interrupt. */ #define EFUSE_PGM_DONE_INT_CLR (BIT(1)) #define EFUSE_PGM_DONE_INT_CLR_M (EFUSE_PGM_DONE_INT_CLR_V << EFUSE_PGM_DONE_INT_CLR_S) @@ -2423,8 +2548,8 @@ extern "C" { * Controls the eFuse programming voltage. */ #define EFUSE_DAC_CONF_REG (DR_REG_EFUSE_BASE + 0x1e8) -/** EFUSE_DAC_CLK_DIV : R/W; bitpos: [7:0]; default: 19; - * Configures the division factor of the rising clock of the programming voltage. +/** EFUSE_DAC_CLK_DIV : R/W; bitpos: [7:0]; default: 23; + * Controls the division factor of the rising clock of the programming voltage. */ #define EFUSE_DAC_CLK_DIV 0x000000FFU #define EFUSE_DAC_CLK_DIV_M (EFUSE_DAC_CLK_DIV_V << EFUSE_DAC_CLK_DIV_S) @@ -2438,17 +2563,14 @@ extern "C" { #define EFUSE_DAC_CLK_PAD_SEL_V 0x00000001U #define EFUSE_DAC_CLK_PAD_SEL_S 8 /** EFUSE_DAC_NUM : R/W; bitpos: [16:9]; default: 255; - * Configures clock cycles for programming voltage to rise. Measurement unit: a clock - * cycle divided by EFUSE_DAC_CLK_DIV. + * Controls the rising period of the programming voltage. */ #define EFUSE_DAC_NUM 0x000000FFU #define EFUSE_DAC_NUM_M (EFUSE_DAC_NUM_V << EFUSE_DAC_NUM_S) #define EFUSE_DAC_NUM_V 0x000000FFU #define EFUSE_DAC_NUM_S 9 /** EFUSE_OE_CLR : R/W; bitpos: [17]; default: 0; - * Configures whether to reduce the power supply of programming voltage. - * 0: Not reduce - * 1: Reduce + * Reduces the power supply of the programming voltage. */ #define EFUSE_OE_CLR (BIT(17)) #define EFUSE_OE_CLR_M (EFUSE_OE_CLR_V << EFUSE_OE_CLR_S) @@ -2460,29 +2582,28 @@ extern "C" { */ #define EFUSE_RD_TIM_CONF_REG (DR_REG_EFUSE_BASE + 0x1ec) /** EFUSE_THR_A : R/W; bitpos: [7:0]; default: 1; - * Configures the read hold time. Measurement unit: One cycle of the eFuse core clock. + * Configures the read hold time. */ #define EFUSE_THR_A 0x000000FFU #define EFUSE_THR_A_M (EFUSE_THR_A_V << EFUSE_THR_A_S) #define EFUSE_THR_A_V 0x000000FFU #define EFUSE_THR_A_S 0 /** EFUSE_TRD : R/W; bitpos: [15:8]; default: 2; - * Configures the read time. Measurement unit: One cycle of the eFuse core clock. + * Configures the read time. */ #define EFUSE_TRD 0x000000FFU #define EFUSE_TRD_M (EFUSE_TRD_V << EFUSE_TRD_S) #define EFUSE_TRD_V 0x000000FFU #define EFUSE_TRD_S 8 /** EFUSE_TSUR_A : R/W; bitpos: [23:16]; default: 1; - * Configures the read setup time. Measurement unit: One cycle of the eFuse core clock. + * Configures the read setup time. */ #define EFUSE_TSUR_A 0x000000FFU #define EFUSE_TSUR_A_M (EFUSE_TSUR_A_V << EFUSE_TSUR_A_S) #define EFUSE_TSUR_A_V 0x000000FFU #define EFUSE_TSUR_A_S 16 -/** EFUSE_READ_INIT_NUM : R/W; bitpos: [31:24]; default: 18; - * Configures the waiting time of reading eFuse memory. Measurement unit: One cycle of - * the eFuse core clock. +/** EFUSE_READ_INIT_NUM : R/W; bitpos: [31:24]; default: 15; + * Configures the waiting time of reading eFuse memory. */ #define EFUSE_READ_INIT_NUM 0x000000FFU #define EFUSE_READ_INIT_NUM_M (EFUSE_READ_INIT_NUM_V << EFUSE_READ_INIT_NUM_S) @@ -2494,24 +2615,21 @@ extern "C" { */ #define EFUSE_WR_TIM_CONF1_REG (DR_REG_EFUSE_BASE + 0x1f0) /** EFUSE_TSUP_A : R/W; bitpos: [7:0]; default: 1; - * Configures the programming setup time. Measurement unit: One cycle of the eFuse - * core clock. + * Configures the programming setup time. */ #define EFUSE_TSUP_A 0x000000FFU #define EFUSE_TSUP_A_M (EFUSE_TSUP_A_V << EFUSE_TSUP_A_S) #define EFUSE_TSUP_A_V 0x000000FFU #define EFUSE_TSUP_A_S 0 /** EFUSE_PWR_ON_NUM : R/W; bitpos: [23:8]; default: 9831; - * Configures the power up time for VDDQ. Measurement unit: One cycle of the eFuse - * core clock. + * Configures the power up time for VDDQ. */ #define EFUSE_PWR_ON_NUM 0x0000FFFFU #define EFUSE_PWR_ON_NUM_M (EFUSE_PWR_ON_NUM_V << EFUSE_PWR_ON_NUM_S) #define EFUSE_PWR_ON_NUM_V 0x0000FFFFU #define EFUSE_PWR_ON_NUM_S 8 /** EFUSE_THP_A : R/W; bitpos: [31:24]; default: 1; - * Configures the programming hold time. Measurement unit: One cycle of the eFuse core - * clock. + * Configures the programming hold time. */ #define EFUSE_THP_A 0x000000FFU #define EFUSE_THP_A_M (EFUSE_THP_A_V << EFUSE_THP_A_S) @@ -2523,16 +2641,14 @@ extern "C" { */ #define EFUSE_WR_TIM_CONF2_REG (DR_REG_EFUSE_BASE + 0x1f4) /** EFUSE_PWR_OFF_NUM : R/W; bitpos: [15:0]; default: 320; - * Configures the power outage time for VDDQ. Measurement unit: One cycle of the eFuse - * core clock. + * Configures the power outage time for VDDQ. */ #define EFUSE_PWR_OFF_NUM 0x0000FFFFU #define EFUSE_PWR_OFF_NUM_M (EFUSE_PWR_OFF_NUM_V << EFUSE_PWR_OFF_NUM_S) #define EFUSE_PWR_OFF_NUM_V 0x0000FFFFU #define EFUSE_PWR_OFF_NUM_S 0 /** EFUSE_TPGM : R/W; bitpos: [31:16]; default: 160; - * Configures the active programming time. Measurement unit: One cycle of the eFuse - * core clock. + * Configures the active programming time. */ #define EFUSE_TPGM 0x0000FFFFU #define EFUSE_TPGM_M (EFUSE_TPGM_V << EFUSE_TPGM_S) @@ -2545,39 +2661,46 @@ extern "C" { */ #define EFUSE_WR_TIM_CONF0_RS_BYPASS_REG (DR_REG_EFUSE_BASE + 0x1f8) /** EFUSE_BYPASS_RS_CORRECTION : R/W; bitpos: [0]; default: 0; - * Configures whether to bypass the Reed-Solomon (RS) correction step. - * 0: Not bypass - * 1: Bypass + * Set this bit to bypass reed solomon correction step. */ #define EFUSE_BYPASS_RS_CORRECTION (BIT(0)) #define EFUSE_BYPASS_RS_CORRECTION_M (EFUSE_BYPASS_RS_CORRECTION_V << EFUSE_BYPASS_RS_CORRECTION_S) #define EFUSE_BYPASS_RS_CORRECTION_V 0x00000001U #define EFUSE_BYPASS_RS_CORRECTION_S 0 /** EFUSE_BYPASS_RS_BLK_NUM : R/W; bitpos: [11:1]; default: 0; - * Configures which block number to bypass the Reed-Solomon (RS) correction step. + * Configures block number of programming twice operation. */ #define EFUSE_BYPASS_RS_BLK_NUM 0x000007FFU #define EFUSE_BYPASS_RS_BLK_NUM_M (EFUSE_BYPASS_RS_BLK_NUM_V << EFUSE_BYPASS_RS_BLK_NUM_S) #define EFUSE_BYPASS_RS_BLK_NUM_V 0x000007FFU #define EFUSE_BYPASS_RS_BLK_NUM_S 1 /** EFUSE_UPDATE : WT; bitpos: [12]; default: 0; - * Configures whether to update multi-bit register signals. - * 1: Update - * 0: No effect + * Set this bit to update multi-bit register signals. */ #define EFUSE_UPDATE (BIT(12)) #define EFUSE_UPDATE_M (EFUSE_UPDATE_V << EFUSE_UPDATE_S) #define EFUSE_UPDATE_V 0x00000001U #define EFUSE_UPDATE_S 12 /** EFUSE_TPGM_INACTIVE : R/W; bitpos: [20:13]; default: 1; - * Configures the inactive programming time. Measurement unit: One cycle of the eFuse - * core clock. + * Configures the inactive programming time. */ #define EFUSE_TPGM_INACTIVE 0x000000FFU #define EFUSE_TPGM_INACTIVE_M (EFUSE_TPGM_INACTIVE_V << EFUSE_TPGM_INACTIVE_S) #define EFUSE_TPGM_INACTIVE_V 0x000000FFU #define EFUSE_TPGM_INACTIVE_S 13 +/** EFUSE_DATE_REG register + * eFuse version register. + */ +#define EFUSE_DATE_REG (DR_REG_EFUSE_BASE + 0x1fc) +/** EFUSE_DATE : R/W; bitpos: [27:0]; default: 35684640; + * Stores eFuse version. + */ +#define EFUSE_DATE 0x0FFFFFFFU +#define EFUSE_DATE_M (EFUSE_DATE_V << EFUSE_DATE_S) +#define EFUSE_DATE_V 0x0FFFFFFFU +#define EFUSE_DATE_S 0 + #ifdef __cplusplus } #endif diff --git a/components/soc/esp32h21/register/soc/efuse_struct.h b/components/soc/esp32h21/register/soc/efuse_struct.h index 477270f8213..ab4c17e4750 100644 --- a/components/soc/esp32h21/register/soc/efuse_struct.h +++ b/components/soc/esp32h21/register/soc/efuse_struct.h @@ -10,45 +10,160 @@ extern "C" { #endif -/** Group: program_data registers */ -/** Type of pgm_datan register - * Represents pgm_datan +/** Group: PGM Data Register */ +/** Type of pgm_data0 register + * Register 0 that stores data to be programmed. */ typedef union { struct { - /** pgm_data_n : R/W; bitpos: [31:0]; default: 0; - * Configures the nth 32-bit data to be programmed. + /** pgm_data_0 : R/W; bitpos: [31:0]; default: 0; + * Configures the 0th 32-bit data to be programmed. */ - uint32_t pgm_data_n:32; + uint32_t pgm_data_0:32; }; uint32_t val; -} efuse_pgm_datan_reg_t; +} efuse_pgm_data0_reg_t; -/** Type of pgm_check_valuen register - * Represents pgm_check_valuen +/** Type of pgm_data1 register + * Register 1 that stores data to be programmed. */ typedef union { struct { - /** pgm_rs_data_n : R/W; bitpos: [31:0]; default: 0; - * Configures the nth RS code to be programmed. + /** pgm_data_1 : R/W; bitpos: [31:0]; default: 0; + * Configures the 1st 32-bit data to be programmed. */ - uint32_t pgm_rs_data_n:32; + uint32_t pgm_data_1:32; }; uint32_t val; -} efuse_pgm_check_valuen_reg_t; +} efuse_pgm_data1_reg_t; +/** Type of pgm_data2 register + * Register 2 that stores data to be programmed. + */ +typedef union { + struct { + /** pgm_data_2 : R/W; bitpos: [31:0]; default: 0; + * Configures the 2nd 32-bit data to be programmed. + */ + uint32_t pgm_data_2:32; + }; + uint32_t val; +} efuse_pgm_data2_reg_t; + +/** Type of pgm_data3 register + * Register 3 that stores data to be programmed. + */ +typedef union { + struct { + /** pgm_data_3 : R/W; bitpos: [31:0]; default: 0; + * Configures the 3rd 32-bit data to be programmed. + */ + uint32_t pgm_data_3:32; + }; + uint32_t val; +} efuse_pgm_data3_reg_t; + +/** Type of pgm_data4 register + * Register 4 that stores data to be programmed. + */ +typedef union { + struct { + /** pgm_data_4 : R/W; bitpos: [31:0]; default: 0; + * Configures the 4th 32-bit data to be programmed. + */ + uint32_t pgm_data_4:32; + }; + uint32_t val; +} efuse_pgm_data4_reg_t; + +/** Type of pgm_data5 register + * Register 5 that stores data to be programmed. + */ +typedef union { + struct { + /** pgm_data_5 : R/W; bitpos: [31:0]; default: 0; + * Configures the 5th 32-bit data to be programmed. + */ + uint32_t pgm_data_5:32; + }; + uint32_t val; +} efuse_pgm_data5_reg_t; + +/** Type of pgm_data6 register + * Register 6 that stores data to be programmed. + */ +typedef union { + struct { + /** pgm_data_6 : R/W; bitpos: [31:0]; default: 0; + * Configures the 6th 32-bit data to be programmed. + */ + uint32_t pgm_data_6:32; + }; + uint32_t val; +} efuse_pgm_data6_reg_t; + +/** Type of pgm_data7 register + * Register 7 that stores data to be programmed. + */ +typedef union { + struct { + /** pgm_data_7 : R/W; bitpos: [31:0]; default: 0; + * Configures the 7th 32-bit data to be programmed. + */ + uint32_t pgm_data_7:32; + }; + uint32_t val; +} efuse_pgm_data7_reg_t; + +/** Type of pgm_check_value0 register + * Register 0 that stores the RS code to be programmed. + */ +typedef union { + struct { + /** pgm_rs_data_0 : R/W; bitpos: [31:0]; default: 0; + * Configures the 0th 32-bit RS code to be programmed. + */ + uint32_t pgm_rs_data_0:32; + }; + uint32_t val; +} efuse_pgm_check_value0_reg_t; -/** Group: block0 registers */ +/** Type of pgm_check_value1 register + * Register 1 that stores the RS code to be programmed. + */ +typedef union { + struct { + /** pgm_rs_data_1 : R/W; bitpos: [31:0]; default: 0; + * Configures the 1st 32-bit RS code to be programmed. + */ + uint32_t pgm_rs_data_1:32; + }; + uint32_t val; +} efuse_pgm_check_value1_reg_t; + +/** Type of pgm_check_value2 register + * Register 2 that stores the RS code to be programmed. + */ +typedef union { + struct { + /** pgm_rs_data_2 : R/W; bitpos: [31:0]; default: 0; + * Configures the 2nd 32-bit RS code to be programmed. + */ + uint32_t pgm_rs_data_2:32; + }; + uint32_t val; +} efuse_pgm_check_value2_reg_t; + + +/** Group: Read Data Register */ /** Type of rd_wr_dis register - * Represents rd_wr_dis + * BLOCK0 data register 0. */ typedef union { struct { /** wr_dis : RO; bitpos: [31:0]; default: 0; * Represents whether programming of individual eFuse memory bit is disabled or - * enabled. - * 1: Disabled - * 0: Enabled + * enabled. 1: Disabled. 0 Enabled. */ uint32_t wr_dis:32; }; @@ -56,1041 +171,1834 @@ typedef union { } efuse_rd_wr_dis_reg_t; /** Type of rd_repeat_data0 register - * Represents rd_repeat_data + * BLOCK0 data register 1. */ typedef union { struct { /** rd_dis : RO; bitpos: [6:0]; default: 0; * Represents whether reading of individual eFuse block(block4~block10) is disabled or - * enabled. - * 1: Disabled - * 0: Enabled + * enabled. 1: disabled. 0: enabled. */ uint32_t rd_dis:7; - /** pvt_glitch_en : RO; bitpos: [7]; default: 0; - * Represents whether to enable PVT power glitch monitor function. - * 1: Enable. - * 0: Disable + /** rpt4_reserved0_4 : RO; bitpos: [7]; default: 0; + * Reserved. */ - uint32_t pvt_glitch_en:1; + uint32_t rpt4_reserved0_4:1; /** dis_icache : RO; bitpos: [8]; default: 0; - * Represents whether icache is disabled or enabled. - * 1: Disabled - * 0: Enabled + * Represents whether icache is disabled or enabled. 1: disabled. 0: enabled. */ uint32_t dis_icache:1; /** dis_usb_jtag : RO; bitpos: [9]; default: 0; - * Represents whether the USB-to-JTAG function in USB Serial/JTAG is disabled. - * 1: Disabled - * 0: Enabled + * Represents whether the function of usb switch to jtag is disabled or enabled. 1: + * disabled. 0: enabled. */ uint32_t dis_usb_jtag:1; /** powerglitch_en : RO; bitpos: [10]; default: 0; - * Represents whether to enable power glitch function. + * Represents whether power glitch function is enabled. 1: enabled. 0: disabled. */ uint32_t powerglitch_en:1; - uint32_t reserved_11:1; + /** dis_usb_serial_jtag : RO; bitpos: [11]; default: 0; + * Represents whether USB-Serial-JTAG is disabled or enabled. 1: disabled. 0: enabled. + */ + uint32_t dis_usb_serial_jtag:1; /** dis_force_download : RO; bitpos: [12]; default: 0; - * Represents whether the function that forces chip into Download mode is disabled. - * 1: Disabled - * 0: Enabled + * Represents whether the function that forces chip into download mode is disabled or + * enabled. 1: disabled. 0: enabled. */ uint32_t dis_force_download:1; /** spi_download_mspi_dis : RO; bitpos: [13]; default: 0; - * Represents accessing MSPI flash/MSPI RAM by SYS AXI matrix is disabled during - * boot_mode_download. - * 1: Disabled - * 0: Enabled + * Represents whether SPI0 controller during boot_mode_download is disabled or + * enabled. 1: disabled. 0: enabled. */ uint32_t spi_download_mspi_dis:1; /** dis_twai : RO; bitpos: [14]; default: 0; - * Represents whether TWAI function is disabled. - * 1: Disabled - * 0: Enabled + * Represents whether TWAI function is disabled or enabled. 1: disabled. 0: enabled. */ uint32_t dis_twai:1; /** jtag_sel_enable : RO; bitpos: [15]; default: 0; - * Represents whether the selection of a JTAG signal source through the strapping pin - * value is enabled when both EFUSE_DIS_PAD_JTAG and EFUSE_DIS_USB_JTAG are configured - * to 0. For more information, please refer to Chapter Placeholder. - * 1: Enabled - * 0: Disabled + * Set this bit to enable selection between usb_to_jtag and pad_to_jtag through + * strapping gpio25 when both EFUSE_DIS_PAD_JTAG and EFUSE_DIS_USB_JTAG are equal to 0 */ uint32_t jtag_sel_enable:1; /** soft_dis_jtag : RO; bitpos: [18:16]; default: 0; - * Represents whether PAD JTAG is disabled in the soft way. It can be restarted via - * HMAC. - * Odd count of bits with a value of 1: Disabled - * Even count of bits with a value of 1: Enabled + * Represents whether JTAG is disabled in soft way. Odd number: disabled. Even number: + * enabled. */ uint32_t soft_dis_jtag:3; /** dis_pad_jtag : RO; bitpos: [19]; default: 0; - * Represents whether PAD JTAG is disabled in the hard way (permanently). - * 1: Disabled - * 0: Enabled + * Represents whether JTAG is disabled in the hard way(permanently). 1: disabled. 0: + * enabled. */ uint32_t dis_pad_jtag:1; /** dis_download_manual_encrypt : RO; bitpos: [20]; default: 0; - * Represents whether flash encryption is disabled (except in SPI boot mode). - * 1: Disabled - * 0: Enabled + * Represents whether flash encrypt function is disabled or enabled(except in SPI boot + * mode). 1: disabled. 0: enabled. */ uint32_t dis_download_manual_encrypt:1; - uint32_t reserved_21:4; + /** usb_drefh : RO; bitpos: [22:21]; default: 0; + * Represents the single-end input threshold vrefh, 1.76 V to 2 V with step of 80 mV. + */ + uint32_t usb_drefh:2; + /** usb_drefl : RO; bitpos: [24:23]; default: 0; + * Represents the single-end input threshold vrefl, 1.76 V to 2 V with step of 80 mV. + */ + uint32_t usb_drefl:2; /** usb_exchg_pins : RO; bitpos: [25]; default: 0; - * Represents whether the D+ and D- pins is exchanged. - * 1: Exchanged - * 0: Not exchanged + * Represents whether the D+ and D- pins is exchanged. 1: exchanged. 0: not exchanged. */ uint32_t usb_exchg_pins:1; /** vdd_spi_as_gpio : RO; bitpos: [26]; default: 0; - * Represents whether vdd spi pin is functioned as gpio. - * 1: Functioned - * 0: Not functioned + * Represents whether vdd spi pin is functioned as gpio. 1: functioned. 0: not + * functioned. */ uint32_t vdd_spi_as_gpio:1; - /** ecdsa_curve_mode : RO; bitpos: [28:27]; default: 0; - * Represents the configuration of the curve of ECDSA calculation. - * 0: Only enable P256 - * 1: Only enable P192 - * 2: Both enable P256 and P192 - * 3: Only enable P256 + /** rpt4_reserved0_2 : RO; bitpos: [28:27]; default: 0; + * Reserved. + */ + uint32_t rpt4_reserved0_2:2; + /** rpt4_reserved0_1 : RO; bitpos: [29]; default: 0; + * Reserved. + */ + uint32_t rpt4_reserved0_1:1; + /** rpt4_reserved0_0 : RO; bitpos: [31:30]; default: 0; + * Reserved. + */ + uint32_t rpt4_reserved0_0:2; + }; + uint32_t val; +} efuse_rd_repeat_data0_reg_t; + +/** Type of rd_repeat_data1 register + * BLOCK0 data register 2. + */ +typedef union { + struct { + /** rpt4_reserved1_1 : RO; bitpos: [15:0]; default: 0; + * Reserved. + */ + uint32_t rpt4_reserved1_1:16; + /** wdt_delay_sel : RO; bitpos: [17:16]; default: 0; + * Represents whether RTC watchdog timeout threshold is selected at startup. 1: + * selected. 0: not selected. + */ + uint32_t wdt_delay_sel:2; + /** spi_boot_crypt_cnt : RO; bitpos: [20:18]; default: 0; + * Represents whether SPI boot encrypt/decrypt is disabled or enabled. Odd number of + * 1: enabled. Even number of 1: disabled. + */ + uint32_t spi_boot_crypt_cnt:3; + /** secure_boot_key_revoke0 : RO; bitpos: [21]; default: 0; + * Represents whether revoking first secure boot key is enabled or disabled. 1: + * enabled. 0: disabled. + */ + uint32_t secure_boot_key_revoke0:1; + /** secure_boot_key_revoke1 : RO; bitpos: [22]; default: 0; + * Represents whether revoking second secure boot key is enabled or disabled. 1: + * enabled. 0: disabled. + */ + uint32_t secure_boot_key_revoke1:1; + /** secure_boot_key_revoke2 : RO; bitpos: [23]; default: 0; + * Represents whether revoking third secure boot key is enabled or disabled. 1: + * enabled. 0: disabled. + */ + uint32_t secure_boot_key_revoke2:1; + /** key_purpose_0 : RO; bitpos: [27:24]; default: 0; + * Represents the purpose of Key0. + */ + uint32_t key_purpose_0:4; + /** key_purpose_1 : RO; bitpos: [31:28]; default: 0; + * Represents the purpose of Key1. + */ + uint32_t key_purpose_1:4; + }; + uint32_t val; +} efuse_rd_repeat_data1_reg_t; + +/** Type of rd_repeat_data2 register + * BLOCK0 data register 3. + */ +typedef union { + struct { + /** key_purpose_2 : RO; bitpos: [3:0]; default: 0; + * Represents the purpose of Key2. + */ + uint32_t key_purpose_2:4; + /** key_purpose_3 : RO; bitpos: [7:4]; default: 0; + * Represents the purpose of Key3. + */ + uint32_t key_purpose_3:4; + /** key_purpose_4 : RO; bitpos: [11:8]; default: 0; + * Represents the purpose of Key4. + */ + uint32_t key_purpose_4:4; + /** key_purpose_5 : RO; bitpos: [15:12]; default: 0; + * Represents the purpose of Key5. + */ + uint32_t key_purpose_5:4; + /** sec_dpa_level : RO; bitpos: [17:16]; default: 0; + * Represents the spa secure level by configuring the clock random divide mode. + */ + uint32_t sec_dpa_level:2; + /** ecdsa_force_use_hardware_k : RO; bitpos: [18]; default: 1; + * Represents whether hardware random number k is forced used in ESDCA. 1: force used. + * 0: not force used. + */ + uint32_t ecdsa_force_use_hardware_k:1; + /** crypt_dpa_enable : RO; bitpos: [19]; default: 1; + * Represents whether anti-dpa attack is enabled. 1:enabled. 0: disabled. + */ + uint32_t crypt_dpa_enable:1; + /** secure_boot_en : RO; bitpos: [20]; default: 0; + * Represents whether secure boot is enabled or disabled. 1: enabled. 0: disabled. + */ + uint32_t secure_boot_en:1; + /** secure_boot_aggressive_revoke : RO; bitpos: [21]; default: 0; + * Represents whether revoking aggressive secure boot is enabled or disabled. 1: + * enabled. 0: disabled. + */ + uint32_t secure_boot_aggressive_revoke:1; + /** rpt4_reserved2_0 : RO; bitpos: [27:22]; default: 0; + * Reserved. + */ + uint32_t rpt4_reserved2_0:6; + /** flash_tpuw : RO; bitpos: [31:28]; default: 0; + * Represents the flash waiting time after power-up, in unit of ms. When the value + * less than 15, the waiting time is the programmed value. Otherwise, the waiting time + * is 2 times the programmed value. + */ + uint32_t flash_tpuw:4; + }; + uint32_t val; +} efuse_rd_repeat_data2_reg_t; + +/** Type of rd_repeat_data3 register + * BLOCK0 data register 4. + */ +typedef union { + struct { + /** dis_download_mode : RO; bitpos: [0]; default: 0; + * Represents whether Download mode is disabled or enabled. 1: disabled. 0: enabled. + */ + uint32_t dis_download_mode:1; + /** dis_direct_boot : RO; bitpos: [1]; default: 0; + * Represents whether direct boot mode is disabled or enabled. 1: disabled. 0: enabled. + */ + uint32_t dis_direct_boot:1; + /** dis_usb_serial_jtag_rom_print : RO; bitpos: [2]; default: 0; + * Set this bit to disable USB-Serial-JTAG print during rom boot. + */ + uint32_t dis_usb_serial_jtag_rom_print:1; + /** rpt4_reserved3_5 : RO; bitpos: [3]; default: 0; + * Reserved. + */ + uint32_t rpt4_reserved3_5:1; + /** dis_usb_serial_jtag_download_mode : RO; bitpos: [4]; default: 0; + * Represents whether the USB-Serial-JTAG download function is disabled or enabled. 1: + * disabled. 0: enabled. + */ + uint32_t dis_usb_serial_jtag_download_mode:1; + /** enable_security_download : RO; bitpos: [5]; default: 0; + * Represents whether security download is enabled or disabled. 1: enabled. 0: + * disabled. + */ + uint32_t enable_security_download:1; + /** uart_print_control : RO; bitpos: [7:6]; default: 0; + * Represents the type of UART printing. 00: force enable printing. 01: enable + * printing when GPIO8 is reset at low level. 10: enable printing when GPIO8 is reset + * at high level. 11: force disable printing. + */ + uint32_t uart_print_control:2; + /** force_send_resume : RO; bitpos: [8]; default: 0; + * Represents whether ROM code is forced to send a resume command during SPI boot. 1: + * forced. 0:not forced. + */ + uint32_t force_send_resume:1; + /** secure_version : RO; bitpos: [24:9]; default: 0; + * Represents the version used by ESP-IDF anti-rollback feature. + */ + uint32_t secure_version:16; + /** secure_boot_disable_fast_wake : RO; bitpos: [25]; default: 0; + * Represents whether FAST VERIFY ON WAKE is disabled or enabled when Secure Boot is + * enabled. 1: disabled. 0: enabled. + */ + uint32_t secure_boot_disable_fast_wake:1; + /** hys_en_pad0 : RO; bitpos: [31:26]; default: 0; + * Set bits to enable hysteresis function of PAD0~5 + */ + uint32_t hys_en_pad0:6; + }; + uint32_t val; +} efuse_rd_repeat_data3_reg_t; + +/** Type of rd_repeat_data4 register + * BLOCK0 data register 5. + */ +typedef union { + struct { + /** hys_en_pad1 : RO; bitpos: [21:0]; default: 0; + * Set bits to enable hysteresis function of PAD6~27 + */ + uint32_t hys_en_pad1:22; + /** rpt4_reserved4_1 : RO; bitpos: [23:22]; default: 0; + * Reserved. + */ + uint32_t rpt4_reserved4_1:2; + /** rpt4_reserved4_0 : RO; bitpos: [31:24]; default: 0; + * Reserved. + */ + uint32_t rpt4_reserved4_0:8; + }; + uint32_t val; +} efuse_rd_repeat_data4_reg_t; + +/** Type of rd_mac_sys_0 register + * BLOCK1 data register $n. + */ +typedef union { + struct { + /** mac_0 : RO; bitpos: [31:0]; default: 0; + * Stores the low 32 bits of MAC address. + */ + uint32_t mac_0:32; + }; + uint32_t val; +} efuse_rd_mac_sys_0_reg_t; + +/** Type of rd_mac_sys_1 register + * BLOCK1 data register $n. + */ +typedef union { + struct { + /** mac_1 : RO; bitpos: [15:0]; default: 0; + * Stores the high 16 bits of MAC address. + */ + uint32_t mac_1:16; + /** mac_ext : RO; bitpos: [31:16]; default: 0; + * Stores the extended bits of MAC address. + */ + uint32_t mac_ext:16; + }; + uint32_t val; +} efuse_rd_mac_sys_1_reg_t; + +/** Type of rd_mac_sys_2 register + * BLOCK1 data register $n. + */ +typedef union { + struct { + /** rxiq_version : RO; bitpos: [2:0]; default: 0; + * Stores RF Calibration data. RXIQ version. + */ + uint32_t rxiq_version:3; + /** rxiq_0 : RO; bitpos: [9:3]; default: 0; + * Stores RF Calibration data. RXIQ data 0. + */ + uint32_t rxiq_0:7; + /** rxiq_1 : RO; bitpos: [16:10]; default: 0; + * Stores RF Calibration data. RXIQ data 1. + */ + uint32_t rxiq_1:7; + /** active_hp_dbias : RO; bitpos: [21:17]; default: 0; + * Stores the PMU active hp dbias. + */ + uint32_t active_hp_dbias:5; + /** active_lp_dbias : RO; bitpos: [26:22]; default: 0; + * Stores the PMU active lp dbias. + */ + uint32_t active_lp_dbias:5; + /** dslp_dbias : RO; bitpos: [30:27]; default: 0; + * Stores the PMU sleep dbias. + */ + uint32_t dslp_dbias:4; + /** dbias_vol_gap_value1 : RO; bitpos: [31]; default: 0; + * Stores the low 1 bit of dbias_vol_gap. + */ + uint32_t dbias_vol_gap_value1:1; + }; + uint32_t val; +} efuse_rd_mac_sys_2_reg_t; + +/** Type of rd_mac_sys_3 register + * BLOCK1 data register $n. + */ +typedef union { + struct { + /** dbias_vol_gap_value2 : RO; bitpos: [2:0]; default: 0; + * Stores the high 3 bits of dbias_vol_gap. + */ + uint32_t dbias_vol_gap_value2:3; + /** dbias_vol_gap_sign : RO; bitpos: [3]; default: 0; + * Stores the sign bit of dbias_vol_gap. + */ + uint32_t dbias_vol_gap_sign:1; + /** mac_reserved_2 : RO; bitpos: [17:4]; default: 0; + * Reserved. + */ + uint32_t mac_reserved_2:14; + /** wafer_version_minor : RO; bitpos: [20:18]; default: 0; + * Stores the wafer version minor. + */ + uint32_t wafer_version_minor:3; + /** wafer_version_major : RO; bitpos: [22:21]; default: 0; + * Stores the wafer version major. + */ + uint32_t wafer_version_major:2; + /** disable_wafer_version_major : RO; bitpos: [23]; default: 0; + * Disables check of wafer version major. + */ + uint32_t disable_wafer_version_major:1; + /** flash_cap : RO; bitpos: [26:24]; default: 0; + * Stores the flash cap. */ - uint32_t ecdsa_curve_mode:2; - /** ecc_force_const_time : RO; bitpos: [29]; default: 0; - * Represents whether to permanently turn on ECC const-time mode. - * 0: Disabled - * 1: Enabled + uint32_t flash_cap:3; + /** flash_temp : RO; bitpos: [28:27]; default: 0; + * Stores the flash temp. + */ + uint32_t flash_temp:2; + /** flash_vendor : RO; bitpos: [31:29]; default: 0; + * Stores the flash vendor. + */ + uint32_t flash_vendor:3; + }; + uint32_t val; +} efuse_rd_mac_sys_3_reg_t; + +/** Type of rd_mac_sys_4 register + * BLOCK1 data register $n. + */ +typedef union { + struct { + /** pkg_version : R; bitpos: [2:0]; default: 0; + * Package version */ - uint32_t ecc_force_const_time:1; - /** xts_dpa_pseudo_level : RO; bitpos: [31:30]; default: 0; - * Represents control method of xts pseudo-round anti-dpa attack function. - * 0: Controlled by register - * 1-3: The higher the value is, the more pseudo-rounds are inserted to the xts-aes - * calculation. + uint32_t pkg_version:3; + /** reserved_1_131 : R; bitpos: [31:3]; default: 0; + * reserved + */ + uint32_t reserved_1_131:29; + }; + uint32_t val; +} efuse_rd_mac_sys_4_reg_t; + +/** Type of rd_mac_sys_5 register + * BLOCK1 data register $n. + */ +typedef union { + struct { + /** sys_data_part0_2 : RO; bitpos: [31:0]; default: 0; + * Stores the second 32 bits of the zeroth part of system data. + */ + uint32_t sys_data_part0_2:32; + }; + uint32_t val; +} efuse_rd_mac_sys_5_reg_t; + +/** Type of rd_sys_part1_data0 register + * Register $n of BLOCK2 (system). + */ +typedef union { + struct { + /** optional_unique_id : R; bitpos: [31:0]; default: 0; + * Optional unique 128-bit ID + */ + uint32_t optional_unique_id:32; + }; + uint32_t val; +} efuse_rd_sys_part1_data0_reg_t; + +/** Type of rd_sys_part1_data1 register + * Register $n of BLOCK2 (system). + */ +typedef union { + struct { + /** optional_unique_id_1 : R; bitpos: [31:0]; default: 0; + * Optional unique 128-bit ID + */ + uint32_t optional_unique_id_1:32; + }; + uint32_t val; +} efuse_rd_sys_part1_data1_reg_t; + +/** Type of rd_sys_part1_data2 register + * Register $n of BLOCK2 (system). + */ +typedef union { + struct { + /** optional_unique_id_2 : R; bitpos: [31:0]; default: 0; + * Optional unique 128-bit ID + */ + uint32_t optional_unique_id_2:32; + }; + uint32_t val; +} efuse_rd_sys_part1_data2_reg_t; + +/** Type of rd_sys_part1_data3 register + * Register $n of BLOCK2 (system). + */ +typedef union { + struct { + /** optional_unique_id_3 : R; bitpos: [31:0]; default: 0; + * Optional unique 128-bit ID + */ + uint32_t optional_unique_id_3:32; + }; + uint32_t val; +} efuse_rd_sys_part1_data3_reg_t; + +/** Type of rd_sys_part1_data4 register + * Register $n of BLOCK2 (system). + */ +typedef union { + struct { + /** reserved_2_128 : R; bitpos: [1:0]; default: 0; + * reserved + */ + uint32_t reserved_2_128:2; + /** blk_version_minor : R; bitpos: [4:2]; default: 0; + * BLK_VERSION_MINOR of BLOCK2. 1: RF Calibration data in BLOCK1 + */ + uint32_t blk_version_minor:3; + /** blk_version_major : R; bitpos: [6:5]; default: 0; + * BLK_VERSION_MAJOR of BLOCK2 + */ + uint32_t blk_version_major:2; + /** disable_blk_version_major : R; bitpos: [7]; default: 0; + * Disables check of blk version major + */ + uint32_t disable_blk_version_major:1; + /** temp_calib : R; bitpos: [16:8]; default: 0; + * Temperature calibration data + */ + uint32_t temp_calib:9; + /** adc1_ave_initcode_atten0 : R; bitpos: [26:17]; default: 0; + * ADC1 calibration data + */ + uint32_t adc1_ave_initcode_atten0:10; + /** adc1_ave_initcode_atten1 : R; bitpos: [31:27]; default: 0; + * ADC1 calibration data + */ + uint32_t adc1_ave_initcode_atten1:5; + }; + uint32_t val; +} efuse_rd_sys_part1_data4_reg_t; + +/** Type of rd_sys_part1_data5 register + * Register $n of BLOCK2 (system). + */ +typedef union { + struct { + /** adc1_ave_initcode_atten1_1 : R; bitpos: [4:0]; default: 0; + * ADC1 calibration data + */ + uint32_t adc1_ave_initcode_atten1_1:5; + /** adc1_ave_initcode_atten2 : R; bitpos: [14:5]; default: 0; + * ADC1 calibration data + */ + uint32_t adc1_ave_initcode_atten2:10; + /** adc1_ave_initcode_atten3 : R; bitpos: [24:15]; default: 0; + * ADC1 calibration data + */ + uint32_t adc1_ave_initcode_atten3:10; + /** adc1_hi_dout_atten0 : R; bitpos: [31:25]; default: 0; + * ADC1 calibration data + */ + uint32_t adc1_hi_dout_atten0:7; + }; + uint32_t val; +} efuse_rd_sys_part1_data5_reg_t; + +/** Type of rd_sys_part1_data6 register + * Register $n of BLOCK2 (system). + */ +typedef union { + struct { + /** adc1_hi_dout_atten0_1 : R; bitpos: [2:0]; default: 0; + * ADC1 calibration data + */ + uint32_t adc1_hi_dout_atten0_1:3; + /** adc1_hi_dout_atten1 : R; bitpos: [12:3]; default: 0; + * ADC1 calibration data + */ + uint32_t adc1_hi_dout_atten1:10; + /** adc1_hi_dout_atten2 : R; bitpos: [22:13]; default: 0; + * ADC1 calibration data + */ + uint32_t adc1_hi_dout_atten2:10; + /** adc1_hi_dout_atten3 : R; bitpos: [31:23]; default: 0; + * ADC1 calibration data + */ + uint32_t adc1_hi_dout_atten3:9; + }; + uint32_t val; +} efuse_rd_sys_part1_data6_reg_t; + +/** Type of rd_sys_part1_data7 register + * Register $n of BLOCK2 (system). + */ +typedef union { + struct { + /** adc1_hi_dout_atten3_1 : R; bitpos: [0]; default: 0; + * ADC1 calibration data + */ + uint32_t adc1_hi_dout_atten3_1:1; + /** adc1_ch0_atten0_initcode_diff : R; bitpos: [4:1]; default: 0; + * ADC1 calibration data + */ + uint32_t adc1_ch0_atten0_initcode_diff:4; + /** adc1_ch1_atten0_initcode_diff : R; bitpos: [8:5]; default: 0; + * ADC1 calibration data + */ + uint32_t adc1_ch1_atten0_initcode_diff:4; + /** adc1_ch2_atten0_initcode_diff : R; bitpos: [12:9]; default: 0; + * ADC1 calibration data + */ + uint32_t adc1_ch2_atten0_initcode_diff:4; + /** adc1_ch3_atten0_initcode_diff : R; bitpos: [16:13]; default: 0; + * ADC1 calibration data + */ + uint32_t adc1_ch3_atten0_initcode_diff:4; + /** adc1_ch4_atten0_initcode_diff : R; bitpos: [20:17]; default: 0; + * ADC1 calibration data + */ + uint32_t adc1_ch4_atten0_initcode_diff:4; + /** reserved_2_245 : R; bitpos: [31:21]; default: 0; + * reserved + */ + uint32_t reserved_2_245:11; + }; + uint32_t val; +} efuse_rd_sys_part1_data7_reg_t; + +/** Type of rd_usr_data0 register + * Register $n of BLOCK3 (user). + */ +typedef union { + struct { + /** usr_data0 : RO; bitpos: [31:0]; default: 0; + * Stores the zeroth 32 bits of BLOCK3 (user). + */ + uint32_t usr_data0:32; + }; + uint32_t val; +} efuse_rd_usr_data0_reg_t; + +/** Type of rd_usr_data1 register + * Register $n of BLOCK3 (user). + */ +typedef union { + struct { + /** usr_data1 : RO; bitpos: [31:0]; default: 0; + * Stores the first 32 bits of BLOCK3 (user). + */ + uint32_t usr_data1:32; + }; + uint32_t val; +} efuse_rd_usr_data1_reg_t; + +/** Type of rd_usr_data2 register + * Register $n of BLOCK3 (user). + */ +typedef union { + struct { + /** usr_data2 : RO; bitpos: [31:0]; default: 0; + * Stores the second 32 bits of BLOCK3 (user). + */ + uint32_t usr_data2:32; + }; + uint32_t val; +} efuse_rd_usr_data2_reg_t; + +/** Type of rd_usr_data3 register + * Register $n of BLOCK3 (user). + */ +typedef union { + struct { + /** usr_data3 : RO; bitpos: [31:0]; default: 0; + * Stores the third 32 bits of BLOCK3 (user). + */ + uint32_t usr_data3:32; + }; + uint32_t val; +} efuse_rd_usr_data3_reg_t; + +/** Type of rd_usr_data4 register + * Register $n of BLOCK3 (user). + */ +typedef union { + struct { + /** usr_data4 : RO; bitpos: [31:0]; default: 0; + * Stores the fourth 32 bits of BLOCK3 (user). + */ + uint32_t usr_data4:32; + }; + uint32_t val; +} efuse_rd_usr_data4_reg_t; + +/** Type of rd_usr_data5 register + * Register $n of BLOCK3 (user). + */ +typedef union { + struct { + /** usr_data5 : RO; bitpos: [31:0]; default: 0; + * Stores the fifth 32 bits of BLOCK3 (user). + */ + uint32_t usr_data5:32; + }; + uint32_t val; +} efuse_rd_usr_data5_reg_t; + +/** Type of rd_usr_data6 register + * Register $n of BLOCK3 (user). + */ +typedef union { + struct { + /** reserved_3_192 : R; bitpos: [7:0]; default: 0; + * reserved + */ + uint32_t reserved_3_192:8; + /** custom_mac : R; bitpos: [31:8]; default: 0; + * Custom MAC + */ + uint32_t custom_mac:24; + }; + uint32_t val; +} efuse_rd_usr_data6_reg_t; + +/** Type of rd_usr_data7 register + * Register $n of BLOCK3 (user). + */ +typedef union { + struct { + /** custom_mac_1 : R; bitpos: [23:0]; default: 0; + * Custom MAC + */ + uint32_t custom_mac_1:24; + /** reserved_3_248 : R; bitpos: [31:24]; default: 0; + * reserved + */ + uint32_t reserved_3_248:8; + }; + uint32_t val; +} efuse_rd_usr_data7_reg_t; + +/** Type of rd_key0_data0 register + * Register $n of BLOCK4 (KEY0). + */ +typedef union { + struct { + /** key0_data0 : RO; bitpos: [31:0]; default: 0; + * Stores the zeroth 32 bits of KEY0. + */ + uint32_t key0_data0:32; + }; + uint32_t val; +} efuse_rd_key0_data0_reg_t; + +/** Type of rd_key0_data1 register + * Register $n of BLOCK4 (KEY0). + */ +typedef union { + struct { + /** key0_data1 : RO; bitpos: [31:0]; default: 0; + * Stores the first 32 bits of KEY0. + */ + uint32_t key0_data1:32; + }; + uint32_t val; +} efuse_rd_key0_data1_reg_t; + +/** Type of rd_key0_data2 register + * Register $n of BLOCK4 (KEY0). + */ +typedef union { + struct { + /** key0_data2 : RO; bitpos: [31:0]; default: 0; + * Stores the second 32 bits of KEY0. + */ + uint32_t key0_data2:32; + }; + uint32_t val; +} efuse_rd_key0_data2_reg_t; + +/** Type of rd_key0_data3 register + * Register $n of BLOCK4 (KEY0). + */ +typedef union { + struct { + /** key0_data3 : RO; bitpos: [31:0]; default: 0; + * Stores the third 32 bits of KEY0. + */ + uint32_t key0_data3:32; + }; + uint32_t val; +} efuse_rd_key0_data3_reg_t; + +/** Type of rd_key0_data4 register + * Register $n of BLOCK4 (KEY0). + */ +typedef union { + struct { + /** key0_data4 : RO; bitpos: [31:0]; default: 0; + * Stores the fourth 32 bits of KEY0. + */ + uint32_t key0_data4:32; + }; + uint32_t val; +} efuse_rd_key0_data4_reg_t; + +/** Type of rd_key0_data5 register + * Register $n of BLOCK4 (KEY0). + */ +typedef union { + struct { + /** key0_data5 : RO; bitpos: [31:0]; default: 0; + * Stores the fifth 32 bits of KEY0. + */ + uint32_t key0_data5:32; + }; + uint32_t val; +} efuse_rd_key0_data5_reg_t; + +/** Type of rd_key0_data6 register + * Register $n of BLOCK4 (KEY0). + */ +typedef union { + struct { + /** key0_data6 : RO; bitpos: [31:0]; default: 0; + * Stores the sixth 32 bits of KEY0. + */ + uint32_t key0_data6:32; + }; + uint32_t val; +} efuse_rd_key0_data6_reg_t; + +/** Type of rd_key0_data7 register + * Register $n of BLOCK4 (KEY0). + */ +typedef union { + struct { + /** key0_data7 : RO; bitpos: [31:0]; default: 0; + * Stores the seventh 32 bits of KEY0. + */ + uint32_t key0_data7:32; + }; + uint32_t val; +} efuse_rd_key0_data7_reg_t; + +/** Type of rd_key1_data0 register + * Register $n of BLOCK5 (KEY1). + */ +typedef union { + struct { + /** key1_data0 : RO; bitpos: [31:0]; default: 0; + * Stores the zeroth 32 bits of KEY1. + */ + uint32_t key1_data0:32; + }; + uint32_t val; +} efuse_rd_key1_data0_reg_t; + +/** Type of rd_key1_data1 register + * Register $n of BLOCK5 (KEY1). + */ +typedef union { + struct { + /** key1_data1 : RO; bitpos: [31:0]; default: 0; + * Stores the first 32 bits of KEY1. + */ + uint32_t key1_data1:32; + }; + uint32_t val; +} efuse_rd_key1_data1_reg_t; + +/** Type of rd_key1_data2 register + * Register $n of BLOCK5 (KEY1). + */ +typedef union { + struct { + /** key1_data2 : RO; bitpos: [31:0]; default: 0; + * Stores the second 32 bits of KEY1. + */ + uint32_t key1_data2:32; + }; + uint32_t val; +} efuse_rd_key1_data2_reg_t; + +/** Type of rd_key1_data3 register + * Register $n of BLOCK5 (KEY1). + */ +typedef union { + struct { + /** key1_data3 : RO; bitpos: [31:0]; default: 0; + * Stores the third 32 bits of KEY1. + */ + uint32_t key1_data3:32; + }; + uint32_t val; +} efuse_rd_key1_data3_reg_t; + +/** Type of rd_key1_data4 register + * Register $n of BLOCK5 (KEY1). + */ +typedef union { + struct { + /** key1_data4 : RO; bitpos: [31:0]; default: 0; + * Stores the fourth 32 bits of KEY1. + */ + uint32_t key1_data4:32; + }; + uint32_t val; +} efuse_rd_key1_data4_reg_t; + +/** Type of rd_key1_data5 register + * Register $n of BLOCK5 (KEY1). + */ +typedef union { + struct { + /** key1_data5 : RO; bitpos: [31:0]; default: 0; + * Stores the fifth 32 bits of KEY1. + */ + uint32_t key1_data5:32; + }; + uint32_t val; +} efuse_rd_key1_data5_reg_t; + +/** Type of rd_key1_data6 register + * Register $n of BLOCK5 (KEY1). + */ +typedef union { + struct { + /** key1_data6 : RO; bitpos: [31:0]; default: 0; + * Stores the sixth 32 bits of KEY1. + */ + uint32_t key1_data6:32; + }; + uint32_t val; +} efuse_rd_key1_data6_reg_t; + +/** Type of rd_key1_data7 register + * Register $n of BLOCK5 (KEY1). + */ +typedef union { + struct { + /** key1_data7 : RO; bitpos: [31:0]; default: 0; + * Stores the seventh 32 bits of KEY1. + */ + uint32_t key1_data7:32; + }; + uint32_t val; +} efuse_rd_key1_data7_reg_t; + +/** Type of rd_key2_data0 register + * Register $n of BLOCK6 (KEY2). + */ +typedef union { + struct { + /** key2_data0 : RO; bitpos: [31:0]; default: 0; + * Stores the zeroth 32 bits of KEY2. + */ + uint32_t key2_data0:32; + }; + uint32_t val; +} efuse_rd_key2_data0_reg_t; + +/** Type of rd_key2_data1 register + * Register $n of BLOCK6 (KEY2). + */ +typedef union { + struct { + /** key2_data1 : RO; bitpos: [31:0]; default: 0; + * Stores the first 32 bits of KEY2. + */ + uint32_t key2_data1:32; + }; + uint32_t val; +} efuse_rd_key2_data1_reg_t; + +/** Type of rd_key2_data2 register + * Register $n of BLOCK6 (KEY2). + */ +typedef union { + struct { + /** key2_data2 : RO; bitpos: [31:0]; default: 0; + * Stores the second 32 bits of KEY2. + */ + uint32_t key2_data2:32; + }; + uint32_t val; +} efuse_rd_key2_data2_reg_t; + +/** Type of rd_key2_data3 register + * Register $n of BLOCK6 (KEY2). + */ +typedef union { + struct { + /** key2_data3 : RO; bitpos: [31:0]; default: 0; + * Stores the third 32 bits of KEY2. + */ + uint32_t key2_data3:32; + }; + uint32_t val; +} efuse_rd_key2_data3_reg_t; + +/** Type of rd_key2_data4 register + * Register $n of BLOCK6 (KEY2). + */ +typedef union { + struct { + /** key2_data4 : RO; bitpos: [31:0]; default: 0; + * Stores the fourth 32 bits of KEY2. + */ + uint32_t key2_data4:32; + }; + uint32_t val; +} efuse_rd_key2_data4_reg_t; + +/** Type of rd_key2_data5 register + * Register $n of BLOCK6 (KEY2). + */ +typedef union { + struct { + /** key2_data5 : RO; bitpos: [31:0]; default: 0; + * Stores the fifth 32 bits of KEY2. + */ + uint32_t key2_data5:32; + }; + uint32_t val; +} efuse_rd_key2_data5_reg_t; + +/** Type of rd_key2_data6 register + * Register $n of BLOCK6 (KEY2). + */ +typedef union { + struct { + /** key2_data6 : RO; bitpos: [31:0]; default: 0; + * Stores the sixth 32 bits of KEY2. + */ + uint32_t key2_data6:32; + }; + uint32_t val; +} efuse_rd_key2_data6_reg_t; + +/** Type of rd_key2_data7 register + * Register $n of BLOCK6 (KEY2). + */ +typedef union { + struct { + /** key2_data7 : RO; bitpos: [31:0]; default: 0; + * Stores the seventh 32 bits of KEY2. + */ + uint32_t key2_data7:32; + }; + uint32_t val; +} efuse_rd_key2_data7_reg_t; + +/** Type of rd_key3_data0 register + * Register $n of BLOCK7 (KEY3). + */ +typedef union { + struct { + /** key3_data0 : RO; bitpos: [31:0]; default: 0; + * Stores the zeroth 32 bits of KEY3. + */ + uint32_t key3_data0:32; + }; + uint32_t val; +} efuse_rd_key3_data0_reg_t; + +/** Type of rd_key3_data1 register + * Register $n of BLOCK7 (KEY3). + */ +typedef union { + struct { + /** key3_data1 : RO; bitpos: [31:0]; default: 0; + * Stores the first 32 bits of KEY3. + */ + uint32_t key3_data1:32; + }; + uint32_t val; +} efuse_rd_key3_data1_reg_t; + +/** Type of rd_key3_data2 register + * Register $n of BLOCK7 (KEY3). + */ +typedef union { + struct { + /** key3_data2 : RO; bitpos: [31:0]; default: 0; + * Stores the second 32 bits of KEY3. + */ + uint32_t key3_data2:32; + }; + uint32_t val; +} efuse_rd_key3_data2_reg_t; + +/** Type of rd_key3_data3 register + * Register $n of BLOCK7 (KEY3). + */ +typedef union { + struct { + /** key3_data3 : RO; bitpos: [31:0]; default: 0; + * Stores the third 32 bits of KEY3. + */ + uint32_t key3_data3:32; + }; + uint32_t val; +} efuse_rd_key3_data3_reg_t; + +/** Type of rd_key3_data4 register + * Register $n of BLOCK7 (KEY3). + */ +typedef union { + struct { + /** key3_data4 : RO; bitpos: [31:0]; default: 0; + * Stores the fourth 32 bits of KEY3. */ - uint32_t xts_dpa_pseudo_level:2; + uint32_t key3_data4:32; }; uint32_t val; -} efuse_rd_repeat_data0_reg_t; +} efuse_rd_key3_data4_reg_t; -/** Type of rd_repeat_data1 register - * Represents rd_repeat_data +/** Type of rd_key3_data5 register + * Register $n of BLOCK7 (KEY3). */ typedef union { struct { - /** io_ldo_adjust : RO; bitpos: [7:0]; default: 0; - * Represents configuration of IO LDO mode and voltage. - */ - uint32_t io_ldo_adjust:8; - /** vdd_spi_ldo_adjust : RO; bitpos: [15:8]; default: 0; - * Represents configuration of FLASH LDO mode and voltage. - */ - uint32_t vdd_spi_ldo_adjust:8; - /** wdt_delay_sel : RO; bitpos: [17:16]; default: 0; - * Represents RTC watchdog timeout threshold. - * 0：The originally configured STG0 threshold × 2 - * 1：The originally configured STG0 threshold × 4 - * 2：The originally configured STG0 threshold × 8 - * 3：The originally configured STG0 threshold × 16 - */ - uint32_t wdt_delay_sel:2; - /** spi_boot_crypt_cnt : RO; bitpos: [20:18]; default: 0; - * Represents whether SPI boot encryption/decryption is enabled. - * Odd count of bits with a value of 1: Enabled - * Even count of bits with a value of 1: Disabled - */ - uint32_t spi_boot_crypt_cnt:3; - /** secure_boot_key_revoke0 : RO; bitpos: [21]; default: 0; - * Represents whether revoking Secure Boot key 0 is enabled. - * 1: Enabled - * 0: Disabled - */ - uint32_t secure_boot_key_revoke0:1; - /** secure_boot_key_revoke1 : RO; bitpos: [22]; default: 0; - * Represents whether revoking Secure Boot key 1 is enabled. - * 1: Enabled - * 0: Disabled - */ - uint32_t secure_boot_key_revoke1:1; - /** secure_boot_key_revoke2 : RO; bitpos: [23]; default: 0; - * Represents whether revoking Secure Boot key 2 is enabled. - * 1: Enabled - * 0: Disabled - */ - uint32_t secure_boot_key_revoke2:1; - /** key_purpose_0 : RO; bitpos: [27:24]; default: 0; - * Represents the purpose of Key0. See Table tab:efuse-key-purpose. + /** key3_data5 : RO; bitpos: [31:0]; default: 0; + * Stores the fifth 32 bits of KEY3. */ - uint32_t key_purpose_0:4; - /** key_purpose_1 : RO; bitpos: [31:28]; default: 0; - * Represents the purpose of Key1. See Table tab:efuse-key-purpose. - */ - uint32_t key_purpose_1:4; + uint32_t key3_data5:32; }; uint32_t val; -} efuse_rd_repeat_data1_reg_t; +} efuse_rd_key3_data5_reg_t; -/** Type of rd_repeat_data2 register - * Represents rd_repeat_data +/** Type of rd_key3_data6 register + * Register $n of BLOCK7 (KEY3). */ typedef union { struct { - /** key_purpose_2 : RO; bitpos: [3:0]; default: 0; - * Represents the purpose of Key2. See Table tab:efuse-key-purpose. - */ - uint32_t key_purpose_2:4; - /** key_purpose_3 : RO; bitpos: [7:4]; default: 0; - * Represents the purpose of Key3. See Table tab:efuse-key-purpose. - */ - uint32_t key_purpose_3:4; - /** key_purpose_4 : RO; bitpos: [11:8]; default: 0; - * Represents the purpose of Key4. See Table tab:efuse-key-purpose. - */ - uint32_t key_purpose_4:4; - /** key_purpose_5 : RO; bitpos: [15:12]; default: 0; - * Represents the purpose of Key5. See Table tab:efuse-key-purpose. - */ - uint32_t key_purpose_5:4; - /** sec_dpa_level : RO; bitpos: [17:16]; default: 0; - * Represents the security level of anti-DPA attack. The level is adjusted by - * configuring the clock random frequency division mode. - * 0: Security level is SEC_DPA_OFF - * 1: Security level is SEC_DPA_LOW - * 2: Security level is SEC_DPA_MIDDLE - * 3: Security level is SEC_DPA_HIGH - * For more information, please refer to Chapter mod:sysreg > Section - * sec:sysreg-anti-dpa-attack-security-control. - */ - uint32_t sec_dpa_level:2; - /** io_ldo_1p8 : RO; bitpos: [18]; default: 0; - * Represents select IO LDO voltage to 1.8V or 3.3V. - * 1: 1.8V - * 0: 3.3V - */ - uint32_t io_ldo_1p8:1; - /** crypt_dpa_enable : RO; bitpos: [19]; default: 0; - * Represents whether defense against DPA attack is enabled. - * 1: Enabled - * 0: Disabled - */ - uint32_t crypt_dpa_enable:1; - /** secure_boot_en : RO; bitpos: [20]; default: 0; - * Represents whether Secure Boot is enabled. - * 1: Enabled - * 0: Disabled - */ - uint32_t secure_boot_en:1; - /** secure_boot_aggressive_revoke : RO; bitpos: [21]; default: 0; - * Represents whether aggressive revocation of Secure Boot is enabled. - * 1: Enabled - * 0: Disabled + /** key3_data6 : RO; bitpos: [31:0]; default: 0; + * Stores the sixth 32 bits of KEY3. */ - uint32_t secure_boot_aggressive_revoke:1; - /** powerglitch_en1 : RO; bitpos: [26:22]; default: 0; - * Represents whether to enable power glitch function when chip power on. - */ - uint32_t powerglitch_en1:5; - /** dcdc_ccm_en : RO; bitpos: [27]; default: 0; - * Represents whether change DCDC to CCM mode. - */ - uint32_t dcdc_ccm_en:1; - /** flash_tpuw : RO; bitpos: [31:28]; default: 0; - * Represents the flash waiting time after power-up. Measurement unit: ms. - * When the value is less than 15, the waiting time is the programmed value. - * Otherwise, the waiting time is a fixed value, i.e. 30 ms. - */ - uint32_t flash_tpuw:4; + uint32_t key3_data6:32; }; uint32_t val; -} efuse_rd_repeat_data2_reg_t; +} efuse_rd_key3_data6_reg_t; -/** Type of rd_repeat_data3 register - * Represents rd_repeat_data +/** Type of rd_key3_data7 register + * Register $n of BLOCK7 (KEY3). */ typedef union { struct { - /** dis_download_mode : RO; bitpos: [0]; default: 0; - * Represents whether all download modes are disabled. - * 1: Disabled - * 0: Enabled - */ - uint32_t dis_download_mode:1; - /** dis_direct_boot : RO; bitpos: [1]; default: 0; - * Represents whether direct boot mode is disabled. - * 1: Disabled - * 0: Enabled - */ - uint32_t dis_direct_boot:1; - /** dis_usb_serial_jtag_rom_print : RO; bitpos: [2]; default: 0; - * Represents whether print from USB-Serial-JTAG during ROM boot is disabled. - * 1: Disabled - * 0: Enabled - */ - uint32_t dis_usb_serial_jtag_rom_print:1; - uint32_t reserved_3:1; - /** dis_usb_serial_jtag_download_mode : RO; bitpos: [4]; default: 0; - * Represents whether the USB-Serial-JTAG download function is disabled. - * 1: Disabled - * 0: Enabled - */ - uint32_t dis_usb_serial_jtag_download_mode:1; - /** enable_security_download : RO; bitpos: [5]; default: 0; - * Represents whether security download is enabled. Only UART is supported for - * download. Reading/writing RAM or registers is not supported (i.e. Stub download is - * not supported). - * 1: Enabled - * 0: Disabled - */ - uint32_t enable_security_download:1; - /** uart_print_control : RO; bitpos: [7:6]; default: 0; - * Represents the type of UART printing. - * 0: Force enable printing. - * 1: Enable printing when GPIO8 is reset at low level. - * 2: Enable printing when GPIO8 is reset at high level. - * 3: Force disable printing. - */ - uint32_t uart_print_control:2; - /** force_send_resume : RO; bitpos: [8]; default: 0; - * Represents whether ROM code is forced to send a resume command during SPI boot. - * 1: Forced - * 0: Not forced - */ - uint32_t force_send_resume:1; - /** secure_version : RO; bitpos: [24:9]; default: 0; - * Represents the security version used by ESP-IDF anti-rollback feature. - */ - uint32_t secure_version:16; - /** secure_boot_disable_fast_wake : RO; bitpos: [25]; default: 0; - * Represents whether FAST VERIFY ON WAKE is disabled when Secure Boot is enabled. - * 1: Disabled - * 0: Enabled - */ - uint32_t secure_boot_disable_fast_wake:1; - /** hys_en_pad0 : RO; bitpos: [31:26]; default: 0; - * Represents whether to enable the hysteresis function of pad 0-5. - * 0: Disabled - * 1: Enabled + /** key3_data7 : RO; bitpos: [31:0]; default: 0; + * Stores the seventh 32 bits of KEY3. */ - uint32_t hys_en_pad0:6; + uint32_t key3_data7:32; }; uint32_t val; -} efuse_rd_repeat_data3_reg_t; +} efuse_rd_key3_data7_reg_t; -/** Type of rd_repeat_data4 register - * Represents rd_repeat_data +/** Type of rd_key4_data0 register + * Register $n of BLOCK8 (KEY4). */ typedef union { struct { - /** hys_en_pad1 : RO; bitpos: [21:0]; default: 0; - * Represents whether to enable the hysteresis function of pad 6-27. - * 0: Disabled - * 1: Enabled + /** key4_data0 : RO; bitpos: [31:0]; default: 0; + * Stores the zeroth 32 bits of KEY4. */ - uint32_t hys_en_pad1:22; - /** flash_ldo_power_sel : RO; bitpos: [22]; default: 0; - * Represents which flash LDO is selected. - * 0: FLASH LDO 1P8. - * 1: FLASH LDO 1P2. - */ - uint32_t flash_ldo_power_sel:1; - uint32_t reserved_23:9; + uint32_t key4_data0:32; }; uint32_t val; -} efuse_rd_repeat_data4_reg_t; - +} efuse_rd_key4_data0_reg_t; -/** Group: block1 registers */ -/** Type of rd_mac_sys0 register - * Represents rd_mac_sys +/** Type of rd_key4_data1 register + * Register $n of BLOCK8 (KEY4). */ typedef union { struct { - /** mac_0 : RO; bitpos: [31:0]; default: 0; - * Represents MAC address. Low 32-bit. + /** key4_data1 : RO; bitpos: [31:0]; default: 0; + * Stores the first 32 bits of KEY4. */ - uint32_t mac_0:32; + uint32_t key4_data1:32; }; uint32_t val; -} efuse_rd_mac_sys0_reg_t; +} efuse_rd_key4_data1_reg_t; -/** Type of rd_mac_sys1 register - * Represents rd_mac_sys +/** Type of rd_key4_data2 register + * Register $n of BLOCK8 (KEY4). */ typedef union { struct { - /** mac_1 : RO; bitpos: [15:0]; default: 0; - * Represents MAC address. High 16-bit. - */ - uint32_t mac_1:16; - /** mac_ext : RO; bitpos: [31:16]; default: 0; - * Represents the extended bits of MAC address. + /** key4_data2 : RO; bitpos: [31:0]; default: 0; + * Stores the second 32 bits of KEY4. */ - uint32_t mac_ext:16; + uint32_t key4_data2:32; }; uint32_t val; -} efuse_rd_mac_sys1_reg_t; +} efuse_rd_key4_data2_reg_t; -/** Type of rd_mac_sys2 register - * Represents rd_mac_sys +/** Type of rd_key4_data3 register + * Register $n of BLOCK8 (KEY4). */ typedef union { struct { - /** mac_reserved_0 : RO; bitpos: [13:0]; default: 0; - * Reserved. + /** key4_data3 : RO; bitpos: [31:0]; default: 0; + * Stores the third 32 bits of KEY4. */ - uint32_t mac_reserved_0:14; - /** mac_reserved_1 : RO; bitpos: [31:14]; default: 0; - * Reserved. - */ - uint32_t mac_reserved_1:18; + uint32_t key4_data3:32; }; uint32_t val; -} efuse_rd_mac_sys2_reg_t; +} efuse_rd_key4_data3_reg_t; -/** Type of rd_mac_sys3 register - * Represents rd_mac_sys +/** Type of rd_key4_data4 register + * Register $n of BLOCK8 (KEY4). */ typedef union { struct { - /** mac_reserved_2 : RO; bitpos: [3:0]; default: 0; - * Reserved. - */ - uint32_t mac_reserved_2:4; - /** pvt_cell_select : RO; bitpos: [10:4]; default: 0; - * Represents the selection of Power glitch monitor PVT cell. + /** key4_data4 : RO; bitpos: [31:0]; default: 0; + * Stores the fourth 32 bits of KEY4. */ - uint32_t pvt_cell_select:7; - /** mac_reserved_3 : RO; bitpos: [17:11]; default: 0; - * Reserved. - */ - uint32_t mac_reserved_3:7; - /** sys_data_part0_0 : RO; bitpos: [31:18]; default: 0; - * Represents the first 14-bit of zeroth part of system data. - */ - uint32_t sys_data_part0_0:14; + uint32_t key4_data4:32; }; uint32_t val; -} efuse_rd_mac_sys3_reg_t; +} efuse_rd_key4_data4_reg_t; -/** Type of rd_mac_sys4 register - * Represents rd_mac_sys +/** Type of rd_key4_data5 register + * Register $n of BLOCK8 (KEY4). */ typedef union { struct { - uint32_t reserved_0:5; - /** pvt_limit : RO; bitpos: [20:5]; default: 0; - * Represents the threshold of power glitch monitor. - */ - uint32_t pvt_limit:16; - /** pvt_glitch_charge_reset : RO; bitpos: [21]; default: 0; - * Represents whether to trigger reset or charge pump when PVT power glitch happened. - * 1:Trigger charge pump. - * 0:Trigger reset + /** key4_data5 : RO; bitpos: [31:0]; default: 0; + * Stores the fifth 32 bits of KEY4. */ - uint32_t pvt_glitch_charge_reset:1; - /** pvt_glitch_mode : RO; bitpos: [23:22]; default: 0; - * Represents the configuration of glitch mode. - */ - uint32_t pvt_glitch_mode:2; - /** pvt_pump_limit : RO; bitpos: [31:24]; default: 0; - * Represents the configuration voltage monitor limit for charge pump. - */ - uint32_t pvt_pump_limit:8; + uint32_t key4_data5:32; }; uint32_t val; -} efuse_rd_mac_sys4_reg_t; +} efuse_rd_key4_data5_reg_t; -/** Type of rd_mac_sys5 register - * Represents rd_mac_sys +/** Type of rd_key4_data6 register + * Register $n of BLOCK8 (KEY4). */ typedef union { struct { - /** pump_drv : RO; bitpos: [3:0]; default: 0; - * Use to configure charge pump voltage gain. + /** key4_data6 : RO; bitpos: [31:0]; default: 0; + * Stores the sixth 32 bits of KEY4. */ - uint32_t pump_drv:4; - /** sys_data_part0_2 : RO; bitpos: [31:4]; default: 0; - * Represents the second 28-bit of zeroth part of system data. - */ - uint32_t sys_data_part0_2:28; + uint32_t key4_data6:32; }; uint32_t val; -} efuse_rd_mac_sys5_reg_t; - +} efuse_rd_key4_data6_reg_t; -/** Group: block2 registers */ -/** Type of rd_sys_part1_datan register - * Represents rd_sys_part1_datan +/** Type of rd_key4_data7 register + * Register $n of BLOCK8 (KEY4). */ typedef union { struct { - /** sys_data_part1_n : RO; bitpos: [31:0]; default: 0; - * Represents the zeroth 32-bit of first part of system data. + /** key4_data7 : RO; bitpos: [31:0]; default: 0; + * Stores the seventh 32 bits of KEY4. */ - uint32_t sys_data_part1_n:32; + uint32_t key4_data7:32; }; uint32_t val; -} efuse_rd_sys_part1_datan_reg_t; +} efuse_rd_key4_data7_reg_t; +/** Type of rd_key5_data0 register + * Register $n of BLOCK9 (KEY5). + */ +typedef union { + struct { + /** key5_data0 : RO; bitpos: [31:0]; default: 0; + * Stores the zeroth 32 bits of KEY5. + */ + uint32_t key5_data0:32; + }; + uint32_t val; +} efuse_rd_key5_data0_reg_t; -/** Group: block3 registers */ -/** Type of rd_usr_datan register - * Represents rd_usr_datan +/** Type of rd_key5_data1 register + * Register $n of BLOCK9 (KEY5). */ typedef union { struct { - /** usr_datan : RO; bitpos: [31:0]; default: 0; - * Represents the zeroth 32-bit of block3 (user). + /** key5_data1 : RO; bitpos: [31:0]; default: 0; + * Stores the first 32 bits of KEY5. */ - uint32_t usr_datan:32; + uint32_t key5_data1:32; }; uint32_t val; -} efuse_rd_usr_datan_reg_t; +} efuse_rd_key5_data1_reg_t; +/** Type of rd_key5_data2 register + * Register $n of BLOCK9 (KEY5). + */ +typedef union { + struct { + /** key5_data2 : RO; bitpos: [31:0]; default: 0; + * Stores the second 32 bits of KEY5. + */ + uint32_t key5_data2:32; + }; + uint32_t val; +} efuse_rd_key5_data2_reg_t; -/** Group: block4 registers */ -/** Type of rd_key0_datan register - * Represents rd_key0_datan +/** Type of rd_key5_data3 register + * Register $n of BLOCK9 (KEY5). */ typedef union { struct { - /** key0_datan : RO; bitpos: [31:0]; default: 0; - * Represents the zeroth 32-bit of key0. + /** key5_data3 : RO; bitpos: [31:0]; default: 0; + * Stores the third 32 bits of KEY5. */ - uint32_t key0_datan:32; + uint32_t key5_data3:32; }; uint32_t val; -} efuse_rd_key0_datan_reg_t; +} efuse_rd_key5_data3_reg_t; +/** Type of rd_key5_data4 register + * Register $n of BLOCK9 (KEY5). + */ +typedef union { + struct { + /** key5_data4 : RO; bitpos: [31:0]; default: 0; + * Stores the fourth 32 bits of KEY5. + */ + uint32_t key5_data4:32; + }; + uint32_t val; +} efuse_rd_key5_data4_reg_t; -/** Group: block5 registers */ -/** Type of rd_key1_datan register - * Represents rd_key1_datan +/** Type of rd_key5_data5 register + * Register $n of BLOCK9 (KEY5). */ typedef union { struct { - /** key1_datan : RO; bitpos: [31:0]; default: 0; - * Represents the zeroth 32-bit of key1. + /** key5_data5 : RO; bitpos: [31:0]; default: 0; + * Stores the fifth 32 bits of KEY5. */ - uint32_t key1_datan:32; + uint32_t key5_data5:32; }; uint32_t val; -} efuse_rd_key1_datan_reg_t; +} efuse_rd_key5_data5_reg_t; +/** Type of rd_key5_data6 register + * Register $n of BLOCK9 (KEY5). + */ +typedef union { + struct { + /** key5_data6 : RO; bitpos: [31:0]; default: 0; + * Stores the sixth 32 bits of KEY5. + */ + uint32_t key5_data6:32; + }; + uint32_t val; +} efuse_rd_key5_data6_reg_t; -/** Group: block6 registers */ -/** Type of rd_key2_datan register - * Represents rd_key2_datan +/** Type of rd_key5_data7 register + * Register $n of BLOCK9 (KEY5). */ typedef union { struct { - /** key2_datan : RO; bitpos: [31:0]; default: 0; - * Represents the zeroth 32-bit of key2. + /** key5_data7 : RO; bitpos: [31:0]; default: 0; + * Stores the seventh 32 bits of KEY5. */ - uint32_t key2_datan:32; + uint32_t key5_data7:32; }; uint32_t val; -} efuse_rd_key2_datan_reg_t; +} efuse_rd_key5_data7_reg_t; +/** Type of rd_sys_part2_data0 register + * Register $n of BLOCK10 (system). + */ +typedef union { + struct { + /** sys_data_part2_0 : RO; bitpos: [31:0]; default: 0; + * Stores the $nth 32 bits of the 2nd part of system data. + */ + uint32_t sys_data_part2_0:32; + }; + uint32_t val; +} efuse_rd_sys_part2_data0_reg_t; -/** Group: block7 registers */ -/** Type of rd_key3_datan register - * Represents rd_key3_datan +/** Type of rd_sys_part2_data1 register + * Register $n of BLOCK9 (KEY5). */ typedef union { struct { - /** key3_datan : RO; bitpos: [31:0]; default: 0; - * Represents the zeroth 32-bit of key3. + /** sys_data_part2_1 : RO; bitpos: [31:0]; default: 0; + * Stores the $nth 32 bits of the 2nd part of system data. */ - uint32_t key3_datan:32; + uint32_t sys_data_part2_1:32; }; uint32_t val; -} efuse_rd_key3_datan_reg_t; +} efuse_rd_sys_part2_data1_reg_t; +/** Type of rd_sys_part2_data2 register + * Register $n of BLOCK10 (system). + */ +typedef union { + struct { + /** sys_data_part2_2 : RO; bitpos: [31:0]; default: 0; + * Stores the $nth 32 bits of the 2nd part of system data. + */ + uint32_t sys_data_part2_2:32; + }; + uint32_t val; +} efuse_rd_sys_part2_data2_reg_t; -/** Group: block8 registers */ -/** Type of rd_key4_datan register - * Represents rd_key4_datan +/** Type of rd_sys_part2_data3 register + * Register $n of BLOCK10 (system). */ typedef union { struct { - /** key4_datan : RO; bitpos: [31:0]; default: 0; - * Represents the zeroth 32-bit of key4. + /** sys_data_part2_3 : RO; bitpos: [31:0]; default: 0; + * Stores the $nth 32 bits of the 2nd part of system data. */ - uint32_t key4_datan:32; + uint32_t sys_data_part2_3:32; }; uint32_t val; -} efuse_rd_key4_datan_reg_t; +} efuse_rd_sys_part2_data3_reg_t; +/** Type of rd_sys_part2_data4 register + * Register $n of BLOCK10 (system). + */ +typedef union { + struct { + /** sys_data_part2_4 : RO; bitpos: [31:0]; default: 0; + * Stores the $nth 32 bits of the 2nd part of system data. + */ + uint32_t sys_data_part2_4:32; + }; + uint32_t val; +} efuse_rd_sys_part2_data4_reg_t; -/** Group: block9 registers */ -/** Type of rd_key5_datan register - * Represents rd_key5_datan +/** Type of rd_sys_part2_data5 register + * Register $n of BLOCK10 (system). */ typedef union { struct { - /** key5_datan : RO; bitpos: [31:0]; default: 0; - * Represents the zeroth 32-bit of key5. + /** sys_data_part2_5 : RO; bitpos: [31:0]; default: 0; + * Stores the $nth 32 bits of the 2nd part of system data. */ - uint32_t key5_datan:32; + uint32_t sys_data_part2_5:32; }; uint32_t val; -} efuse_rd_key5_datan_reg_t; +} efuse_rd_sys_part2_data5_reg_t; +/** Type of rd_sys_part2_data6 register + * Register $n of BLOCK10 (system). + */ +typedef union { + struct { + /** sys_data_part2_6 : RO; bitpos: [31:0]; default: 0; + * Stores the $nth 32 bits of the 2nd part of system data. + */ + uint32_t sys_data_part2_6:32; + }; + uint32_t val; +} efuse_rd_sys_part2_data6_reg_t; -/** Group: block10 registers */ -/** Type of rd_sys_part2_datan register - * Represents rd_sys_part2_datan +/** Type of rd_sys_part2_data7 register + * Register $n of BLOCK10 (system). */ typedef union { struct { - /** sys_data_part2_n : RO; bitpos: [31:0]; default: 0; - * Represents the zeroth 32-bit of second part of system data. + /** sys_data_part2_7 : RO; bitpos: [31:0]; default: 0; + * Stores the $nth 32 bits of the 2nd part of system data. */ - uint32_t sys_data_part2_n:32; + uint32_t sys_data_part2_7:32; }; uint32_t val; -} efuse_rd_sys_part2_datan_reg_t; +} efuse_rd_sys_part2_data7_reg_t; -/** Group: block0 error report registers */ -/** Type of rd_repeat_data_err0 register - * Represents rd_repeat_data_err +/** Group: Report Register */ +/** Type of rd_repeat_err0 register + * Programming error record register 0 of BLOCK0. */ typedef union { struct { /** rd_dis_err : RO; bitpos: [6:0]; default: 0; - * Represents the programming error of EFUSE_RD_DIS + * Indicates a programming error of RD_DIS. */ uint32_t rd_dis_err:7; - /** pvt_glitch_en_err : RO; bitpos: [7]; default: 0; - * Represents the programming error of EFUSE_PVT_GLITCH_EN + /** rpt4_reserved0_err_4 : RO; bitpos: [7]; default: 0; + * Reserved. */ - uint32_t pvt_glitch_en_err:1; + uint32_t rpt4_reserved0_err_4:1; /** dis_icache_err : RO; bitpos: [8]; default: 0; - * Represents the programming error of EFUSE_DIS_ICACHE + * Indicates a programming error of DIS_ICACHE. */ uint32_t dis_icache_err:1; /** dis_usb_jtag_err : RO; bitpos: [9]; default: 0; - * Represents the programming error of EFUSE_DIS_USB_JTAG + * Indicates a programming error of DIS_USB_JTAG. */ uint32_t dis_usb_jtag_err:1; /** powerglitch_en_err : RO; bitpos: [10]; default: 0; - * Represents the programming error of EFUSE_POWERGLITCH_EN + * Indicates a programming error of POWERGLITCH_EN. */ uint32_t powerglitch_en_err:1; - uint32_t reserved_11:1; + /** dis_usb_serial_jtag_err : RO; bitpos: [11]; default: 0; + * Indicates a programming error of DIS_USB_DEVICE. + */ + uint32_t dis_usb_serial_jtag_err:1; /** dis_force_download_err : RO; bitpos: [12]; default: 0; - * Represents the programming error of EFUSE_DIS_FORCE_DOWNLOAD + * Indicates a programming error of DIS_FORCE_DOWNLOAD. */ uint32_t dis_force_download_err:1; /** spi_download_mspi_dis_err : RO; bitpos: [13]; default: 0; - * Represents the programming error of EFUSE_SPI_DOWNLOAD_MSPI_DIS + * Indicates a programming error of SPI_DOWNLOAD_MSPI_DIS. */ uint32_t spi_download_mspi_dis_err:1; /** dis_twai_err : RO; bitpos: [14]; default: 0; - * Represents the programming error of EFUSE_DIS_TWAI + * Indicates a programming error of DIS_CAN. */ uint32_t dis_twai_err:1; /** jtag_sel_enable_err : RO; bitpos: [15]; default: 0; - * Represents the programming error of EFUSE_JTAG_SEL_ENABLE + * Indicates a programming error of JTAG_SEL_ENABLE. */ uint32_t jtag_sel_enable_err:1; /** soft_dis_jtag_err : RO; bitpos: [18:16]; default: 0; - * Represents the programming error of EFUSE_SOFT_DIS_JTAG + * Indicates a programming error of SOFT_DIS_JTAG. */ uint32_t soft_dis_jtag_err:3; /** dis_pad_jtag_err : RO; bitpos: [19]; default: 0; - * Represents the programming error of EFUSE_DIS_PAD_JTAG + * Indicates a programming error of DIS_PAD_JTAG. */ uint32_t dis_pad_jtag_err:1; /** dis_download_manual_encrypt_err : RO; bitpos: [20]; default: 0; - * Represents the programming error of EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT + * Indicates a programming error of DIS_DOWNLOAD_MANUAL_ENCRYPT. */ uint32_t dis_download_manual_encrypt_err:1; - uint32_t reserved_21:4; + /** usb_drefh_err : RO; bitpos: [22:21]; default: 0; + * Indicates a programming error of USB_DREFH. + */ + uint32_t usb_drefh_err:2; + /** usb_drefl_err : RO; bitpos: [24:23]; default: 0; + * Indicates a programming error of USB_DREFL. + */ + uint32_t usb_drefl_err:2; /** usb_exchg_pins_err : RO; bitpos: [25]; default: 0; - * Represents the programming error of EFUSE_USB_EXCHG_PINS + * Indicates a programming error of USB_EXCHG_PINS. */ uint32_t usb_exchg_pins_err:1; /** vdd_spi_as_gpio_err : RO; bitpos: [26]; default: 0; - * Represents the programming error of EFUSE_VDD_SPI_AS_GPIO + * Indicates a programming error of VDD_SPI_AS_GPIO. */ uint32_t vdd_spi_as_gpio_err:1; - /** ecdsa_curve_mode_err : RO; bitpos: [28:27]; default: 0; - * Represents the programming error of EFUSE_ECDSA_CURVE_MODE + /** rpt4_reserved0_err_2 : RO; bitpos: [28:27]; default: 0; + * Reserved. */ - uint32_t ecdsa_curve_mode_err:2; - /** ecc_force_const_time_err : RO; bitpos: [29]; default: 0; - * Represents the programming error of EFUSE_ECC_FORCE_CONST_TIME + uint32_t rpt4_reserved0_err_2:2; + /** rpt4_reserved0_err_1 : RO; bitpos: [29]; default: 0; + * Reserved. */ - uint32_t ecc_force_const_time_err:1; - /** xts_dpa_pseudo_level_err : RO; bitpos: [31:30]; default: 0; - * Represents the programming error of EFUSE_XTS_DPA_PSEUDO_LEVEL + uint32_t rpt4_reserved0_err_1:1; + /** rpt4_reserved0_err_0 : RO; bitpos: [31:30]; default: 0; + * Reserved. */ - uint32_t xts_dpa_pseudo_level_err:2; + uint32_t rpt4_reserved0_err_0:2; }; uint32_t val; -} efuse_rd_repeat_data_err0_reg_t; +} efuse_rd_repeat_err0_reg_t; -/** Type of rd_repeat_data_err1 register - * Represents rd_repeat_data_err +/** Type of rd_repeat_err1 register + * Programming error record register 1 of BLOCK0. */ typedef union { struct { - /** io_ldo_adjust_err : RO; bitpos: [7:0]; default: 0; - * Represents the programming error of EFUSE_IO_LDO_ADJUST - */ - uint32_t io_ldo_adjust_err:8; - /** vdd_spi_ldo_adjust_err : RO; bitpos: [15:8]; default: 0; - * Represents the programming error of EFUSE_VDD_SPI_LDO_ADJUST + /** rpt4_reserved1_err_0 : RO; bitpos: [15:0]; default: 0; + * Reserved. */ - uint32_t vdd_spi_ldo_adjust_err:8; + uint32_t rpt4_reserved1_err_0:16; /** wdt_delay_sel_err : RO; bitpos: [17:16]; default: 0; - * Represents the programming error of EFUSE_WDT_DELAY_SEL + * Indicates a programming error of WDT_DELAY_SEL. */ uint32_t wdt_delay_sel_err:2; /** spi_boot_crypt_cnt_err : RO; bitpos: [20:18]; default: 0; - * Represents the programming error of EFUSE_SPI_BOOT_CRYPT_CNT + * Indicates a programming error of SPI_BOOT_CRYPT_CNT. */ uint32_t spi_boot_crypt_cnt_err:3; /** secure_boot_key_revoke0_err : RO; bitpos: [21]; default: 0; - * Represents the programming error of EFUSE_SECURE_BOOT_KEY_REVOKE0 + * Indicates a programming error of SECURE_BOOT_KEY_REVOKE0. */ uint32_t secure_boot_key_revoke0_err:1; /** secure_boot_key_revoke1_err : RO; bitpos: [22]; default: 0; - * Represents the programming error of EFUSE_SECURE_BOOT_KEY_REVOKE1 + * Indicates a programming error of SECURE_BOOT_KEY_REVOKE1. */ uint32_t secure_boot_key_revoke1_err:1; /** secure_boot_key_revoke2_err : RO; bitpos: [23]; default: 0; - * Represents the programming error of EFUSE_SECURE_BOOT_KEY_REVOKE2 + * Indicates a programming error of SECURE_BOOT_KEY_REVOKE2. */ uint32_t secure_boot_key_revoke2_err:1; /** key_purpose_0_err : RO; bitpos: [27:24]; default: 0; - * Represents the programming error of EFUSE_KEY_PURPOSE_0 + * Indicates a programming error of KEY_PURPOSE_0. */ uint32_t key_purpose_0_err:4; /** key_purpose_1_err : RO; bitpos: [31:28]; default: 0; - * Represents the programming error of EFUSE_KEY_PURPOSE_1 + * Indicates a programming error of KEY_PURPOSE_1. */ uint32_t key_purpose_1_err:4; }; uint32_t val; -} efuse_rd_repeat_data_err1_reg_t; +} efuse_rd_repeat_err1_reg_t; -/** Type of rd_repeat_data_err2 register - * Represents rd_repeat_data_err +/** Type of rd_repeat_err2 register + * Programming error record register 2 of BLOCK0. */ typedef union { struct { /** key_purpose_2_err : RO; bitpos: [3:0]; default: 0; - * Represents the programming error of EFUSE_KEY_PURPOSE_2 + * Indicates a programming error of KEY_PURPOSE_2. */ uint32_t key_purpose_2_err:4; /** key_purpose_3_err : RO; bitpos: [7:4]; default: 0; - * Represents the programming error of EFUSE_KEY_PURPOSE_3 + * Indicates a programming error of KEY_PURPOSE_3. */ uint32_t key_purpose_3_err:4; /** key_purpose_4_err : RO; bitpos: [11:8]; default: 0; - * Represents the programming error of EFUSE_KEY_PURPOSE_4 + * Indicates a programming error of KEY_PURPOSE_4. */ uint32_t key_purpose_4_err:4; /** key_purpose_5_err : RO; bitpos: [15:12]; default: 0; - * Represents the programming error of EFUSE_KEY_PURPOSE_5 + * Indicates a programming error of KEY_PURPOSE_5. */ uint32_t key_purpose_5_err:4; /** sec_dpa_level_err : RO; bitpos: [17:16]; default: 0; - * Represents the programming error of EFUSE_SEC_DPA_LEVEL + * Indicates a programming error of SEC_DPA_LEVEL. */ uint32_t sec_dpa_level_err:2; - /** io_ldo_1p8_err : RO; bitpos: [18]; default: 0; - * Represents the programming error of EFUSE_IO_LDO_1P8 + /** rpt4_reserved2_err_1 : RO; bitpos: [18]; default: 0; + * Reserved. */ - uint32_t io_ldo_1p8_err:1; + uint32_t rpt4_reserved2_err_1:1; /** crypt_dpa_enable_err : RO; bitpos: [19]; default: 0; - * Represents the programming error of EFUSE_CRYPT_DPA_ENABLE + * Indicates a programming error of CRYPT_DPA_ENABLE. */ uint32_t crypt_dpa_enable_err:1; /** secure_boot_en_err : RO; bitpos: [20]; default: 0; - * Represents the programming error of EFUSE_SECURE_BOOT_EN + * Indicates a programming error of SECURE_BOOT_EN. */ uint32_t secure_boot_en_err:1; /** secure_boot_aggressive_revoke_err : RO; bitpos: [21]; default: 0; - * Represents the programming error of EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE + * Indicates a programming error of SECURE_BOOT_AGGRESSIVE_REVOKE. */ uint32_t secure_boot_aggressive_revoke_err:1; - /** powerglitch_en1_err : RO; bitpos: [26:22]; default: 0; - * Represents the programming error of EFUSE_POWERGLITCH_EN1 - */ - uint32_t powerglitch_en1_err:5; - /** dcdc_ccm_en_err : RO; bitpos: [27]; default: 0; - * Represents the programming error of EFUSE_DCDC_CCM_EN + /** rpt4_reserved2_err_0 : RO; bitpos: [27:22]; default: 0; + * Reserved. */ - uint32_t dcdc_ccm_en_err:1; + uint32_t rpt4_reserved2_err_0:6; /** flash_tpuw_err : RO; bitpos: [31:28]; default: 0; - * Represents the programming error of EFUSE_FLASH_TPUW + * Indicates a programming error of FLASH_TPUW. */ uint32_t flash_tpuw_err:4; }; uint32_t val; -} efuse_rd_repeat_data_err2_reg_t; +} efuse_rd_repeat_err2_reg_t; -/** Type of rd_repeat_data_err3 register - * Represents rd_repeat_data_err +/** Type of rd_repeat_err3 register + * Programming error record register 3 of BLOCK0. */ typedef union { struct { /** dis_download_mode_err : RO; bitpos: [0]; default: 0; - * Represents the programming error of EFUSE_DIS_DOWNLOAD_MODE + * Indicates a programming error of DIS_DOWNLOAD_MODE. */ uint32_t dis_download_mode_err:1; /** dis_direct_boot_err : RO; bitpos: [1]; default: 0; - * Represents the programming error of EFUSE_DIS_DIRECT_BOOT + * Indicates a programming error of DIS_DIRECT_BOOT. */ uint32_t dis_direct_boot_err:1; - /** dis_usb_serial_jtag_rom_print_err : RO; bitpos: [2]; default: 0; - * Represents the programming error of EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT + /** usb_print_err : RO; bitpos: [2]; default: 0; + * Indicates a programming error of UART_PRINT_CHANNEL. */ - uint32_t dis_usb_serial_jtag_rom_print_err:1; - uint32_t reserved_3:1; + uint32_t usb_print_err:1; + /** rpt4_reserved3_err_5 : RO; bitpos: [3]; default: 0; + * Reserved. + */ + uint32_t rpt4_reserved3_err_5:1; /** dis_usb_serial_jtag_download_mode_err : RO; bitpos: [4]; default: 0; - * Represents the programming error of EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE + * Indicates a programming error of DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE. */ uint32_t dis_usb_serial_jtag_download_mode_err:1; /** enable_security_download_err : RO; bitpos: [5]; default: 0; - * Represents the programming error of EFUSE_ENABLE_SECURITY_DOWNLOAD + * Indicates a programming error of ENABLE_SECURITY_DOWNLOAD. */ uint32_t enable_security_download_err:1; /** uart_print_control_err : RO; bitpos: [7:6]; default: 0; - * Represents the programming error of EFUSE_UART_PRINT_CONTROL + * Indicates a programming error of UART_PRINT_CONTROL. */ uint32_t uart_print_control_err:2; /** force_send_resume_err : RO; bitpos: [8]; default: 0; - * Represents the programming error of EFUSE_FORCE_SEND_RESUME + * Indicates a programming error of FORCE_SEND_RESUME. */ uint32_t force_send_resume_err:1; /** secure_version_err : RO; bitpos: [24:9]; default: 0; - * Represents the programming error of EFUSE_SECURE_VERSION + * Indicates a programming error of SECURE VERSION. */ uint32_t secure_version_err:16; /** secure_boot_disable_fast_wake_err : RO; bitpos: [25]; default: 0; - * Represents the programming error of EFUSE_SECURE_BOOT_DISABLE_FAST_WAKE + * Indicates a programming error of SECURE_BOOT_DISABLE_FAST_WAKE. */ uint32_t secure_boot_disable_fast_wake_err:1; /** hys_en_pad0_err : RO; bitpos: [31:26]; default: 0; - * Represents the programming error of EFUSE_HYS_EN_PAD0 + * Indicates a programming error of HYS_EN_PAD0. */ uint32_t hys_en_pad0_err:6; }; uint32_t val; -} efuse_rd_repeat_data_err3_reg_t; +} efuse_rd_repeat_err3_reg_t; -/** Type of rd_repeat_data_err4 register - * Represents rd_repeat_data_err +/** Type of rd_repeat_err4 register + * Programming error record register 4 of BLOCK0. */ typedef union { struct { /** hys_en_pad1_err : RO; bitpos: [21:0]; default: 0; - * Represents the programming error of EFUSE_HYS_EN_PAD1 + * Indicates a programming error of HYS_EN_PAD1. */ uint32_t hys_en_pad1_err:22; - /** flash_ldo_power_sel_err : RO; bitpos: [22]; default: 0; - * Represents the programming error of EFUSE_FLASH_LDO_POWER_SEL - */ - uint32_t flash_ldo_power_sel_err:1; - uint32_t reserved_23:9; - }; - uint32_t val; -} efuse_rd_repeat_data_err4_reg_t; - - -/** Group: RS block error report registers */ -/** Type of rd_rs_data_err0 register - * Represents rd_rs_data_err - */ -typedef union { - struct { - /** rd_mac_sys_err_num : RO; bitpos: [2:0]; default: 0; - * Represents the error number of registers. - * The value of this signal means the number of error bytes in rd_mac_sys - */ - uint32_t rd_mac_sys_err_num:3; - /** rd_mac_sys_fail : RO; bitpos: [3]; default: 0; - * Represents error status of register. - * 0: Means no failure and that the data of rd_mac_sys is reliable - * 1: Means that programming rd_mac_sys failed and the number of error bytes is over 6. + /** rpt4_reserved4_err_1 : RO; bitpos: [23:22]; default: 0; + * Reserved. */ - uint32_t rd_mac_sys_fail:1; - /** rd_sys_part1_data_err_num : RO; bitpos: [6:4]; default: 0; - * Represents the error number of registers. - * The value of this signal means the number of error bytes in rd_sys_part1_data + uint32_t rpt4_reserved4_err_1:2; + /** rpt4_reserved4_err_0 : RO; bitpos: [31:24]; default: 0; + * Reserved. */ - uint32_t rd_sys_part1_data_err_num:3; - /** rd_sys_part1_data_fail : RO; bitpos: [7]; default: 0; - * Represents error status of register. - * 0: Means no failure and that the data of rd_sys_part1_data is reliable - * 1: Means that programming rd_sys_part1_data failed and the number of error bytes is - * over 6. - */ - uint32_t rd_sys_part1_data_fail:1; - /** rd_usr_data_err_num : RO; bitpos: [10:8]; default: 0; - * Represents the error number of registers. - * The value of this signal means the number of error bytes in rd_usr_data - */ - uint32_t rd_usr_data_err_num:3; - /** rd_usr_data_fail : RO; bitpos: [11]; default: 0; - * Represents error status of register. - * 0: Means no failure and that the data of rd_usr_data is reliable - * 1: Means that programming rd_usr_data failed and the number of error bytes is over - * 6. - */ - uint32_t rd_usr_data_fail:1; - /** rd_key0_data_err_num : RO; bitpos: [14:12]; default: 0; - * Represents the error number of registers. - * The value of this signal means the number of error bytes in rd_key0_data - */ - uint32_t rd_key0_data_err_num:3; - /** rd_key0_data_fail : RO; bitpos: [15]; default: 0; - * Represents error status of register. - * 0: Means no failure and that the data of rd_key0_data is reliable - * 1: Means that programming rd_key0_data failed and the number of error bytes is over - * 6. - */ - uint32_t rd_key0_data_fail:1; - /** rd_key1_data_err_num : RO; bitpos: [18:16]; default: 0; - * Represents the error number of registers. - * The value of this signal means the number of error bytes in rd_key1_data - */ - uint32_t rd_key1_data_err_num:3; - /** rd_key1_data_fail : RO; bitpos: [19]; default: 0; - * Represents error status of register. - * 0: Means no failure and that the data of rd_key1_data is reliable - * 1: Means that programming rd_key1_data failed and the number of error bytes is over - * 6. - */ - uint32_t rd_key1_data_fail:1; - /** rd_key2_data_err_num : RO; bitpos: [22:20]; default: 0; - * Represents the error number of registers. - * The value of this signal means the number of error bytes in rd_key2_data - */ - uint32_t rd_key2_data_err_num:3; - /** rd_key2_data_fail : RO; bitpos: [23]; default: 0; - * Represents error status of register. - * 0: Means no failure and that the data of rd_key2_data is reliable - * 1: Means that programming rd_key2_data failed and the number of error bytes is over - * 6. - */ - uint32_t rd_key2_data_fail:1; - /** rd_key3_data_err_num : RO; bitpos: [26:24]; default: 0; - * Represents the error number of registers. - * The value of this signal means the number of error bytes in rd_key3_data - */ - uint32_t rd_key3_data_err_num:3; - /** rd_key3_data_fail : RO; bitpos: [27]; default: 0; - * Represents error status of register. - * 0: Means no failure and that the data of rd_key3_data is reliable - * 1: Means that programming rd_key3_data failed and the number of error bytes is over - * 6. - */ - uint32_t rd_key3_data_fail:1; - /** rd_key4_data_err_num : RO; bitpos: [30:28]; default: 0; - * Represents the error number of registers. - * The value of this signal means the number of error bytes in rd_key4_data - */ - uint32_t rd_key4_data_err_num:3; - /** rd_key4_data_fail : RO; bitpos: [31]; default: 0; - * Represents error status of register. - * 0: Means no failure and that the data of rd_key4_data is reliable - * 1: Means that programming rd_key4_data failed and the number of error bytes is over - * 6. - */ - uint32_t rd_key4_data_fail:1; - }; - uint32_t val; -} efuse_rd_rs_data_err0_reg_t; - -/** Type of rd_rs_data_err1 register - * Represents rd_rs_data_err - */ -typedef union { - struct { - /** rd_key5_data_err_num : RO; bitpos: [2:0]; default: 0; - * Represents the error number of registers. - * The value of this signal means the number of error bytes in rd_key5_data - */ - uint32_t rd_key5_data_err_num:3; - /** rd_key5_data_fail : RO; bitpos: [3]; default: 0; - * Represents error status of register. - * 0: Means no failure and that the data of rd_key5_data is reliable - * 1: Means that programming rd_key5_data failed and the number of error bytes is over - * 6. - */ - uint32_t rd_key5_data_fail:1; - /** rd_sys_part2_data_err_num : RO; bitpos: [6:4]; default: 0; - * Represents the error number of registers. - * The value of this signal means the number of error bytes in rd_sys_part2_data - */ - uint32_t rd_sys_part2_data_err_num:3; - /** rd_sys_part2_data_fail : RO; bitpos: [7]; default: 0; - * Represents error status of register. - * 0: Means no failure and that the data of rd_sys_part2_data is reliable - * 1: Means that programming rd_sys_part2_data failed and the number of error bytes is - * over 6. - */ - uint32_t rd_sys_part2_data_fail:1; - uint32_t reserved_8:24; + uint32_t rpt4_reserved4_err_0:8; }; uint32_t val; -} efuse_rd_rs_data_err1_reg_t; +} efuse_rd_repeat_err4_reg_t; +/** Type of rd_rs_err0 register + * Programming error record register 0 of BLOCK1-10. + */ +typedef union { + struct { + /** mac_spi_8m_err_num : RO; bitpos: [2:0]; default: 0; + * The value of this signal means the number of error bytes. + */ + uint32_t mac_spi_8m_err_num:3; + /** mac_spi_8m_fail : RO; bitpos: [3]; default: 0; + * 0: Means no failure and that the data of MAC_SPI_8M is reliable 1: Means that + * programming user data failed and the number of error bytes is over 6. + */ + uint32_t mac_spi_8m_fail:1; + /** sys_part1_num : RO; bitpos: [6:4]; default: 0; + * The value of this signal means the number of error bytes. + */ + uint32_t sys_part1_num:3; + /** sys_part1_fail : RO; bitpos: [7]; default: 0; + * 0: Means no failure and that the data of system part1 is reliable 1: Means that + * programming user data failed and the number of error bytes is over 6. + */ + uint32_t sys_part1_fail:1; + /** usr_data_err_num : RO; bitpos: [10:8]; default: 0; + * The value of this signal means the number of error bytes. + */ + uint32_t usr_data_err_num:3; + /** usr_data_fail : RO; bitpos: [11]; default: 0; + * 0: Means no failure and that the user data is reliable 1: Means that programming + * user data failed and the number of error bytes is over 6. + */ + uint32_t usr_data_fail:1; + /** key0_err_num : RO; bitpos: [14:12]; default: 0; + * The value of this signal means the number of error bytes. + */ + uint32_t key0_err_num:3; + /** key0_fail : RO; bitpos: [15]; default: 0; + * 0: Means no failure and that the data of key0 is reliable 1: Means that programming + * key0 failed and the number of error bytes is over 6. + */ + uint32_t key0_fail:1; + /** key1_err_num : RO; bitpos: [18:16]; default: 0; + * The value of this signal means the number of error bytes. + */ + uint32_t key1_err_num:3; + /** key1_fail : RO; bitpos: [19]; default: 0; + * 0: Means no failure and that the data of key1 is reliable 1: Means that programming + * key1 failed and the number of error bytes is over 6. + */ + uint32_t key1_fail:1; + /** key2_err_num : RO; bitpos: [22:20]; default: 0; + * The value of this signal means the number of error bytes. + */ + uint32_t key2_err_num:3; + /** key2_fail : RO; bitpos: [23]; default: 0; + * 0: Means no failure and that the data of key2 is reliable 1: Means that programming + * key2 failed and the number of error bytes is over 6. + */ + uint32_t key2_fail:1; + /** key3_err_num : RO; bitpos: [26:24]; default: 0; + * The value of this signal means the number of error bytes. + */ + uint32_t key3_err_num:3; + /** key3_fail : RO; bitpos: [27]; default: 0; + * 0: Means no failure and that the data of key3 is reliable 1: Means that programming + * key3 failed and the number of error bytes is over 6. + */ + uint32_t key3_fail:1; + /** key4_err_num : RO; bitpos: [30:28]; default: 0; + * The value of this signal means the number of error bytes. + */ + uint32_t key4_err_num:3; + /** key4_fail : RO; bitpos: [31]; default: 0; + * 0: Means no failure and that the data of key4 is reliable 1: Means that programming + * key4 failed and the number of error bytes is over 6. + */ + uint32_t key4_fail:1; + }; + uint32_t val; +} efuse_rd_rs_err0_reg_t; -/** Group: EFUSE Version Register */ -/** Type of date register - * eFuse version register. +/** Type of rd_rs_err1 register + * Programming error record register 1 of BLOCK1-10. */ typedef union { struct { - /** date : R/W; bitpos: [27:0]; default: 37814560; - * Represents eFuse version. Date:2024-10-12 12:09:57, - * ScriptRev:892332a1019d3a17987b08c6835edce28f46e261 + /** key5_err_num : RO; bitpos: [2:0]; default: 0; + * The value of this signal means the number of error bytes. */ - uint32_t date:28; - uint32_t reserved_28:4; + uint32_t key5_err_num:3; + /** key5_fail : RO; bitpos: [3]; default: 0; + * 0: Means no failure and that the data of key5 is reliable 1: Means that programming + * key5 failed and the number of error bytes is over 6. + */ + uint32_t key5_fail:1; + /** sys_part2_err_num : RO; bitpos: [6:4]; default: 0; + * The value of this signal means the number of error bytes. + */ + uint32_t sys_part2_err_num:3; + /** sys_part2_fail : RO; bitpos: [7]; default: 0; + * 0: Means no failure and that the data of system part2 is reliable 1: Means that + * programming user data failed and the number of error bytes is over 6. + */ + uint32_t sys_part2_fail:1; + uint32_t reserved_8:24; }; uint32_t val; -} efuse_date_reg_t; +} efuse_rd_rs_err1_reg_t; -/** Group: EFUSE Clock Registers */ +/** Group: Configuration Register */ /** Type of clk register * eFuse clcok configuration register. */ typedef union { struct { /** mem_force_pd : R/W; bitpos: [0]; default: 0; - * Configures whether to force power down eFuse SRAM. - * 1: Force - * 0: No effect + * Set this bit to force eFuse SRAM into power-saving mode. */ uint32_t mem_force_pd:1; /** mem_clk_force_on : R/W; bitpos: [1]; default: 1; - * Configures whether to force activate clock signal of eFuse SRAM. - * 1: Force activate - * 0: No effect + * Set this bit and force to activate clock signal of eFuse SRAM. */ uint32_t mem_clk_force_on:1; /** mem_force_pu : R/W; bitpos: [2]; default: 0; - * Configures whether to force power up eFuse SRAM. - * 1: Force - * 0: No effect + * Set this bit to force eFuse SRAM into working mode. */ uint32_t mem_force_pu:1; uint32_t reserved_3:13; /** clk_en : R/W; bitpos: [16]; default: 0; - * Configures whether to force enable eFuse register configuration clock signal. - * 1: Force - * 0: The clock is enabled only during the reading and writing of registers + * Set this bit to force enable eFuse register configuration clock signal. */ uint32_t clk_en:1; uint32_t reserved_17:15; @@ -1098,40 +2006,54 @@ typedef union { uint32_t val; } efuse_clk_reg_t; - -/** Group: EFUSE Configure Registers */ /** Type of conf register * eFuse operation mode configuration register */ typedef union { struct { /** op_code : R/W; bitpos: [15:0]; default: 0; - * Configures operation command type. - * 0x5A5A: Program operation command - * 0x5AA5: Read operation command - * Other values: No effect + * 0x5A5A: programming operation command 0x5AA5: read operation command. */ uint32_t op_code:16; - /** cfg_ecdsa_l_blk : R/W; bitpos: [19:16]; default: 0; - * Configures which block to use for ECDSA key low part output. - */ - uint32_t cfg_ecdsa_l_blk:4; - /** cfg_ecdsa_h_blk : R/W; bitpos: [23:20]; default: 0; - * Configures which block to use for ECDSA key high part output. + /** cfg_ecdsa_blk : R/W; bitpos: [19:16]; default: 0; + * Configures which block to use for ECDSA key output. */ - uint32_t cfg_ecdsa_h_blk:4; - uint32_t reserved_24:8; + uint32_t cfg_ecdsa_blk:4; + uint32_t reserved_20:12; }; uint32_t val; } efuse_conf_reg_t; +/** Type of cmd register + * eFuse command register. + */ +typedef union { + struct { + /** read_cmd : R/W/SC; bitpos: [0]; default: 0; + * Set this bit to send read command. + */ + uint32_t read_cmd:1; + /** pgm_cmd : R/W/SC; bitpos: [1]; default: 0; + * Set this bit to send programming command. + */ + uint32_t pgm_cmd:1; + /** blk_num : R/W; bitpos: [5:2]; default: 0; + * The serial number of the block to be programmed. Value 0-10 corresponds to block + * number 0-10, respectively. + */ + uint32_t blk_num:4; + uint32_t reserved_6:26; + }; + uint32_t val; +} efuse_cmd_reg_t; + /** Type of dac_conf register * Controls the eFuse programming voltage. */ typedef union { struct { - /** dac_clk_div : R/W; bitpos: [7:0]; default: 19; - * Configures the division factor of the rising clock of the programming voltage. + /** dac_clk_div : R/W; bitpos: [7:0]; default: 23; + * Controls the division factor of the rising clock of the programming voltage. */ uint32_t dac_clk_div:8; /** dac_clk_pad_sel : R/W; bitpos: [8]; default: 0; @@ -1139,14 +2061,11 @@ typedef union { */ uint32_t dac_clk_pad_sel:1; /** dac_num : R/W; bitpos: [16:9]; default: 255; - * Configures clock cycles for programming voltage to rise. Measurement unit: a clock - * cycle divided by EFUSE_DAC_CLK_DIV. + * Controls the rising period of the programming voltage. */ uint32_t dac_num:8; /** oe_clr : R/W; bitpos: [17]; default: 0; - * Configures whether to reduce the power supply of programming voltage. - * 0: Not reduce - * 1: Reduce + * Reduces the power supply of the programming voltage. */ uint32_t oe_clr:1; uint32_t reserved_18:14; @@ -1160,20 +2079,19 @@ typedef union { typedef union { struct { /** thr_a : R/W; bitpos: [7:0]; default: 1; - * Configures the read hold time. Measurement unit: One cycle of the eFuse core clock. + * Configures the read hold time. */ uint32_t thr_a:8; /** trd : R/W; bitpos: [15:8]; default: 2; - * Configures the read time. Measurement unit: One cycle of the eFuse core clock. + * Configures the read time. */ uint32_t trd:8; /** tsur_a : R/W; bitpos: [23:16]; default: 1; - * Configures the read setup time. Measurement unit: One cycle of the eFuse core clock. + * Configures the read setup time. */ uint32_t tsur_a:8; - /** read_init_num : R/W; bitpos: [31:24]; default: 18; - * Configures the waiting time of reading eFuse memory. Measurement unit: One cycle of - * the eFuse core clock. + /** read_init_num : R/W; bitpos: [31:24]; default: 15; + * Configures the waiting time of reading eFuse memory. */ uint32_t read_init_num:8; }; @@ -1186,18 +2104,15 @@ typedef union { typedef union { struct { /** tsup_a : R/W; bitpos: [7:0]; default: 1; - * Configures the programming setup time. Measurement unit: One cycle of the eFuse - * core clock. + * Configures the programming setup time. */ uint32_t tsup_a:8; /** pwr_on_num : R/W; bitpos: [23:8]; default: 9831; - * Configures the power up time for VDDQ. Measurement unit: One cycle of the eFuse - * core clock. + * Configures the power up time for VDDQ. */ uint32_t pwr_on_num:16; /** thp_a : R/W; bitpos: [31:24]; default: 1; - * Configures the programming hold time. Measurement unit: One cycle of the eFuse core - * clock. + * Configures the programming hold time. */ uint32_t thp_a:8; }; @@ -1210,13 +2125,11 @@ typedef union { typedef union { struct { /** pwr_off_num : R/W; bitpos: [15:0]; default: 320; - * Configures the power outage time for VDDQ. Measurement unit: One cycle of the eFuse - * core clock. + * Configures the power outage time for VDDQ. */ uint32_t pwr_off_num:16; /** tpgm : R/W; bitpos: [31:16]; default: 160; - * Configures the active programming time. Measurement unit: One cycle of the eFuse - * core clock. + * Configures the active programming time. */ uint32_t tpgm:16; }; @@ -1230,24 +2143,19 @@ typedef union { typedef union { struct { /** bypass_rs_correction : R/W; bitpos: [0]; default: 0; - * Configures whether to bypass the Reed-Solomon (RS) correction step. - * 0: Not bypass - * 1: Bypass + * Set this bit to bypass reed solomon correction step. */ uint32_t bypass_rs_correction:1; /** bypass_rs_blk_num : R/W; bitpos: [11:1]; default: 0; - * Configures which block number to bypass the Reed-Solomon (RS) correction step. + * Configures block number of programming twice operation. */ uint32_t bypass_rs_blk_num:11; /** update : WT; bitpos: [12]; default: 0; - * Configures whether to update multi-bit register signals. - * 1: Update - * 0: No effect + * Set this bit to update multi-bit register signals. */ uint32_t update:1; /** tpgm_inactive : R/W; bitpos: [20:13]; default: 1; - * Configures the inactive programming time. Measurement unit: One cycle of the eFuse - * core clock. + * Configures the inactive programming time. */ uint32_t tpgm_inactive:8; uint32_t reserved_21:11; @@ -1256,79 +2164,66 @@ typedef union { } efuse_wr_tim_conf0_rs_bypass_reg_t; -/** Group: EFUSE Status Registers */ +/** Group: Status Register */ /** Type of status register * eFuse status register. */ typedef union { struct { /** state : RO; bitpos: [3:0]; default: 0; - * Represents the state of the eFuse state machine. - * 0: Reset state, the initial state after power-up - * 1: Idle state - * Other values: Non-idle state + * Indicates the state of the eFuse state machine. */ uint32_t state:4; - uint32_t reserved_4:6; - /** blk0_valid_bit_cnt : RO; bitpos: [19:10]; default: 0; - * Represents the number of block valid bit. + /** otp_load_sw : RO; bitpos: [4]; default: 0; + * The value of OTP_LOAD_SW. */ - uint32_t blk0_valid_bit_cnt:10; - /** cur_ecdsa_l_blk : RO; bitpos: [23:20]; default: 0; - * Represents which block is used for ECDSA key low part output. + uint32_t otp_load_sw:1; + /** otp_vddq_c_sync2 : RO; bitpos: [5]; default: 0; + * The value of OTP_VDDQ_C_SYNC2. */ - uint32_t cur_ecdsa_l_blk:4; - /** cur_ecdsa_h_blk : RO; bitpos: [27:24]; default: 0; - * Represents which block is used for ECDSA key high part output. + uint32_t otp_vddq_c_sync2:1; + /** otp_strobe_sw : RO; bitpos: [6]; default: 0; + * The value of OTP_STROBE_SW. */ - uint32_t cur_ecdsa_h_blk:4; - uint32_t reserved_28:4; - }; - uint32_t val; -} efuse_status_reg_t; - - -/** Group: EFUSE Command Registers */ -/** Type of cmd register - * eFuse command register. - */ -typedef union { - struct { - /** read_cmd : R/W/SC; bitpos: [0]; default: 0; - * Configures whether to send read commands. - * 1: Send - * 0: No effect + uint32_t otp_strobe_sw:1; + /** otp_csb_sw : RO; bitpos: [7]; default: 0; + * The value of OTP_CSB_SW. */ - uint32_t read_cmd:1; - /** pgm_cmd : R/W/SC; bitpos: [1]; default: 0; - * Configures whether to send programming commands. - * 1: Send - * 0: No effect + uint32_t otp_csb_sw:1; + /** otp_pgenb_sw : RO; bitpos: [8]; default: 0; + * The value of OTP_PGENB_SW. */ - uint32_t pgm_cmd:1; - /** blk_num : R/W; bitpos: [5:2]; default: 0; - * Configures the serial number of the block to be programmed. Value 0-10 corresponds - * to block number 0-10, respectively. + uint32_t otp_pgenb_sw:1; + /** otp_vddq_is_sw : RO; bitpos: [9]; default: 0; + * The value of OTP_VDDQ_IS_SW. */ - uint32_t blk_num:4; - uint32_t reserved_6:26; + uint32_t otp_vddq_is_sw:1; + /** blk0_valid_bit_cnt : RO; bitpos: [19:10]; default: 0; + * Indicates the number of block valid bit. + */ + uint32_t blk0_valid_bit_cnt:10; + /** cur_ecdsa_blk : RO; bitpos: [23:20]; default: 0; + * Indicates which block is used for ECDSA key output. + */ + uint32_t cur_ecdsa_blk:4; + uint32_t reserved_24:8; }; uint32_t val; -} efuse_cmd_reg_t; +} efuse_status_reg_t; -/** Group: Interrupt Registers */ +/** Group: Interrupt Register */ /** Type of int_raw register * eFuse raw interrupt register. */ typedef union { struct { /** read_done_int_raw : R/SS/WTC; bitpos: [0]; default: 0; - * The raw interrupt status of EFUSE_READ_DONE_INT. + * The raw bit signal for read_done interrupt. */ uint32_t read_done_int_raw:1; /** pgm_done_int_raw : R/SS/WTC; bitpos: [1]; default: 0; - * The raw interrupt status of EFUSE_PGM_DONE_INT. + * The raw bit signal for pgm_done interrupt. */ uint32_t pgm_done_int_raw:1; uint32_t reserved_2:30; @@ -1342,11 +2237,11 @@ typedef union { typedef union { struct { /** read_done_int_st : RO; bitpos: [0]; default: 0; - * The masked interrupt status of EFUSE_READ_DONE_INT. + * The status signal for read_done interrupt. */ uint32_t read_done_int_st:1; /** pgm_done_int_st : RO; bitpos: [1]; default: 0; - * The masked interrupt status of EFUSE_PGM_DONE_INT. + * The status signal for pgm_done interrupt. */ uint32_t pgm_done_int_st:1; uint32_t reserved_2:30; @@ -1360,11 +2255,11 @@ typedef union { typedef union { struct { /** read_done_int_ena : R/W; bitpos: [0]; default: 0; - * Write 1 to enable EFUSE_READ_DONE_INT. + * The enable signal for read_done interrupt. */ uint32_t read_done_int_ena:1; /** pgm_done_int_ena : R/W; bitpos: [1]; default: 0; - * Write 1 to enable EFUSE_PGM_DONE_INT. + * The enable signal for pgm_done interrupt. */ uint32_t pgm_done_int_ena:1; uint32_t reserved_2:30; @@ -1378,11 +2273,11 @@ typedef union { typedef union { struct { /** read_done_int_clr : WT; bitpos: [0]; default: 0; - * Write 1 to clear EFUSE_READ_DONE_INT. + * The clear signal for read_done interrupt. */ uint32_t read_done_int_clr:1; /** pgm_done_int_clr : WT; bitpos: [1]; default: 0; - * Write 1 to clear EFUSE_PGM_DONE_INT. + * The clear signal for pgm_done interrupt. */ uint32_t pgm_done_int_clr:1; uint32_t reserved_2:30; @@ -1391,39 +2286,126 @@ typedef union { } efuse_int_clr_reg_t; +/** Group: Version Register */ +/** Type of date register + * eFuse version register. + */ +typedef union { + struct { + /** date : R/W; bitpos: [27:0]; default: 35684640; + * Stores eFuse version. + */ + uint32_t date:28; + uint32_t reserved_28:4; + }; + uint32_t val; +} efuse_date_reg_t; + + typedef struct { - volatile efuse_pgm_datan_reg_t pgm_datan[8]; - volatile efuse_pgm_check_valuen_reg_t pgm_check_valuen[3]; + volatile efuse_pgm_data0_reg_t pgm_data0; + volatile efuse_pgm_data1_reg_t pgm_data1; + volatile efuse_pgm_data2_reg_t pgm_data2; + volatile efuse_pgm_data3_reg_t pgm_data3; + volatile efuse_pgm_data4_reg_t pgm_data4; + volatile efuse_pgm_data5_reg_t pgm_data5; + volatile efuse_pgm_data6_reg_t pgm_data6; + volatile efuse_pgm_data7_reg_t pgm_data7; + volatile efuse_pgm_check_value0_reg_t pgm_check_value0; + volatile efuse_pgm_check_value1_reg_t pgm_check_value1; + volatile efuse_pgm_check_value2_reg_t pgm_check_value2; volatile efuse_rd_wr_dis_reg_t rd_wr_dis; volatile efuse_rd_repeat_data0_reg_t rd_repeat_data0; volatile efuse_rd_repeat_data1_reg_t rd_repeat_data1; volatile efuse_rd_repeat_data2_reg_t rd_repeat_data2; volatile efuse_rd_repeat_data3_reg_t rd_repeat_data3; volatile efuse_rd_repeat_data4_reg_t rd_repeat_data4; - volatile efuse_rd_mac_sys0_reg_t rd_mac_sys0; - volatile efuse_rd_mac_sys1_reg_t rd_mac_sys1; - volatile efuse_rd_mac_sys2_reg_t rd_mac_sys2; - volatile efuse_rd_mac_sys3_reg_t rd_mac_sys3; - volatile efuse_rd_mac_sys4_reg_t rd_mac_sys4; - volatile efuse_rd_mac_sys5_reg_t rd_mac_sys5; - volatile efuse_rd_sys_part1_datan_reg_t rd_sys_part1_datan[8]; - volatile efuse_rd_usr_datan_reg_t rd_usr_datan[8]; - volatile efuse_rd_key0_datan_reg_t rd_key0_datan[8]; - volatile efuse_rd_key1_datan_reg_t rd_key1_datan[8]; - volatile efuse_rd_key2_datan_reg_t rd_key2_datan[8]; - volatile efuse_rd_key3_datan_reg_t rd_key3_datan[8]; - volatile efuse_rd_key4_datan_reg_t rd_key4_datan[8]; - volatile efuse_rd_key5_datan_reg_t rd_key5_datan[8]; - volatile efuse_rd_sys_part2_datan_reg_t rd_sys_part2_datan[8]; - volatile efuse_rd_repeat_data_err0_reg_t rd_repeat_data_err0; - volatile efuse_rd_repeat_data_err1_reg_t rd_repeat_data_err1; - volatile efuse_rd_repeat_data_err2_reg_t rd_repeat_data_err2; - volatile efuse_rd_repeat_data_err3_reg_t rd_repeat_data_err3; - volatile efuse_rd_repeat_data_err4_reg_t rd_repeat_data_err4; - volatile efuse_rd_rs_data_err0_reg_t rd_rs_data_err0; - volatile efuse_rd_rs_data_err1_reg_t rd_rs_data_err1; - volatile efuse_date_reg_t date; - uint32_t reserved_19c[11]; + volatile efuse_rd_mac_sys_0_reg_t rd_mac_sys_0; + volatile efuse_rd_mac_sys_1_reg_t rd_mac_sys_1; + volatile efuse_rd_mac_sys_2_reg_t rd_mac_sys_2; + volatile efuse_rd_mac_sys_3_reg_t rd_mac_sys_3; + volatile efuse_rd_mac_sys_4_reg_t rd_mac_sys_4; + volatile efuse_rd_mac_sys_5_reg_t rd_mac_sys_5; + volatile efuse_rd_sys_part1_data0_reg_t rd_sys_part1_data0; + volatile efuse_rd_sys_part1_data1_reg_t rd_sys_part1_data1; + volatile efuse_rd_sys_part1_data2_reg_t rd_sys_part1_data2; + volatile efuse_rd_sys_part1_data3_reg_t rd_sys_part1_data3; + volatile efuse_rd_sys_part1_data4_reg_t rd_sys_part1_data4; + volatile efuse_rd_sys_part1_data5_reg_t rd_sys_part1_data5; + volatile efuse_rd_sys_part1_data6_reg_t rd_sys_part1_data6; + volatile efuse_rd_sys_part1_data7_reg_t rd_sys_part1_data7; + volatile efuse_rd_usr_data0_reg_t rd_usr_data0; + volatile efuse_rd_usr_data1_reg_t rd_usr_data1; + volatile efuse_rd_usr_data2_reg_t rd_usr_data2; + volatile efuse_rd_usr_data3_reg_t rd_usr_data3; + volatile efuse_rd_usr_data4_reg_t rd_usr_data4; + volatile efuse_rd_usr_data5_reg_t rd_usr_data5; + volatile efuse_rd_usr_data6_reg_t rd_usr_data6; + volatile efuse_rd_usr_data7_reg_t rd_usr_data7; + volatile efuse_rd_key0_data0_reg_t rd_key0_data0; + volatile efuse_rd_key0_data1_reg_t rd_key0_data1; + volatile efuse_rd_key0_data2_reg_t rd_key0_data2; + volatile efuse_rd_key0_data3_reg_t rd_key0_data3; + volatile efuse_rd_key0_data4_reg_t rd_key0_data4; + volatile efuse_rd_key0_data5_reg_t rd_key0_data5; + volatile efuse_rd_key0_data6_reg_t rd_key0_data6; + volatile efuse_rd_key0_data7_reg_t rd_key0_data7; + volatile efuse_rd_key1_data0_reg_t rd_key1_data0; + volatile efuse_rd_key1_data1_reg_t rd_key1_data1; + volatile efuse_rd_key1_data2_reg_t rd_key1_data2; + volatile efuse_rd_key1_data3_reg_t rd_key1_data3; + volatile efuse_rd_key1_data4_reg_t rd_key1_data4; + volatile efuse_rd_key1_data5_reg_t rd_key1_data5; + volatile efuse_rd_key1_data6_reg_t rd_key1_data6; + volatile efuse_rd_key1_data7_reg_t rd_key1_data7; + volatile efuse_rd_key2_data0_reg_t rd_key2_data0; + volatile efuse_rd_key2_data1_reg_t rd_key2_data1; + volatile efuse_rd_key2_data2_reg_t rd_key2_data2; + volatile efuse_rd_key2_data3_reg_t rd_key2_data3; + volatile efuse_rd_key2_data4_reg_t rd_key2_data4; + volatile efuse_rd_key2_data5_reg_t rd_key2_data5; + volatile efuse_rd_key2_data6_reg_t rd_key2_data6; + volatile efuse_rd_key2_data7_reg_t rd_key2_data7; + volatile efuse_rd_key3_data0_reg_t rd_key3_data0; + volatile efuse_rd_key3_data1_reg_t rd_key3_data1; + volatile efuse_rd_key3_data2_reg_t rd_key3_data2; + volatile efuse_rd_key3_data3_reg_t rd_key3_data3; + volatile efuse_rd_key3_data4_reg_t rd_key3_data4; + volatile efuse_rd_key3_data5_reg_t rd_key3_data5; + volatile efuse_rd_key3_data6_reg_t rd_key3_data6; + volatile efuse_rd_key3_data7_reg_t rd_key3_data7; + volatile efuse_rd_key4_data0_reg_t rd_key4_data0; + volatile efuse_rd_key4_data1_reg_t rd_key4_data1; + volatile efuse_rd_key4_data2_reg_t rd_key4_data2; + volatile efuse_rd_key4_data3_reg_t rd_key4_data3; + volatile efuse_rd_key4_data4_reg_t rd_key4_data4; + volatile efuse_rd_key4_data5_reg_t rd_key4_data5; + volatile efuse_rd_key4_data6_reg_t rd_key4_data6; + volatile efuse_rd_key4_data7_reg_t rd_key4_data7; + volatile efuse_rd_key5_data0_reg_t rd_key5_data0; + volatile efuse_rd_key5_data1_reg_t rd_key5_data1; + volatile efuse_rd_key5_data2_reg_t rd_key5_data2; + volatile efuse_rd_key5_data3_reg_t rd_key5_data3; + volatile efuse_rd_key5_data4_reg_t rd_key5_data4; + volatile efuse_rd_key5_data5_reg_t rd_key5_data5; + volatile efuse_rd_key5_data6_reg_t rd_key5_data6; + volatile efuse_rd_key5_data7_reg_t rd_key5_data7; + volatile efuse_rd_sys_part2_data0_reg_t rd_sys_part2_data0; + volatile efuse_rd_sys_part2_data1_reg_t rd_sys_part2_data1; + volatile efuse_rd_sys_part2_data2_reg_t rd_sys_part2_data2; + volatile efuse_rd_sys_part2_data3_reg_t rd_sys_part2_data3; + volatile efuse_rd_sys_part2_data4_reg_t rd_sys_part2_data4; + volatile efuse_rd_sys_part2_data5_reg_t rd_sys_part2_data5; + volatile efuse_rd_sys_part2_data6_reg_t rd_sys_part2_data6; + volatile efuse_rd_sys_part2_data7_reg_t rd_sys_part2_data7; + volatile efuse_rd_repeat_err0_reg_t rd_repeat_err0; + volatile efuse_rd_repeat_err1_reg_t rd_repeat_err1; + volatile efuse_rd_repeat_err2_reg_t rd_repeat_err2; + volatile efuse_rd_repeat_err3_reg_t rd_repeat_err3; + volatile efuse_rd_repeat_err4_reg_t rd_repeat_err4; + uint32_t reserved_190[12]; + volatile efuse_rd_rs_err0_reg_t rd_rs_err0; + volatile efuse_rd_rs_err1_reg_t rd_rs_err1; volatile efuse_clk_reg_t clk; volatile efuse_conf_reg_t conf; volatile efuse_status_reg_t status; @@ -1437,12 +2419,13 @@ typedef struct { volatile efuse_wr_tim_conf1_reg_t wr_tim_conf1; volatile efuse_wr_tim_conf2_reg_t wr_tim_conf2; volatile efuse_wr_tim_conf0_rs_bypass_reg_t wr_tim_conf0_rs_bypass; + volatile efuse_date_reg_t date; } efuse_dev_t; extern efuse_dev_t EFUSE; #ifndef __cplusplus -_Static_assert(sizeof(efuse_dev_t) == 0x1fc, "Invalid size of efuse_dev_t structure"); +_Static_assert(sizeof(efuse_dev_t) == 0x200, "Invalid size of efuse_dev_t structure"); #endif #ifdef __cplusplus diff --git a/components/soc/esp32h21/register/soc/gdma_reg.h b/components/soc/esp32h21/register/soc/gdma_reg.h new file mode 100644 index 00000000000..1142b45dc8b --- /dev/null +++ b/components/soc/esp32h21/register/soc/gdma_reg.h @@ -0,0 +1,3161 @@ +/** + * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#include "soc/soc.h" +#ifdef __cplusplus +extern "C" { +#endif + +/** GDMA_IN_INT_RAW_CH0_REG register + * Raw status interrupt of channel 0. + */ +#define GDMA_IN_INT_RAW_CH0_REG (DR_REG_GDMA_BASE + 0x0) +/** GDMA_IN_DONE_CH0_INT_RAW : R/WTC/SS; bitpos: [0]; default: 0; + * The raw interrupt bit turns to high level when the last data pointed by one inlink + * descriptor has been received for Rx channel 0. + */ +#define GDMA_IN_DONE_CH0_INT_RAW (BIT(0)) +#define GDMA_IN_DONE_CH0_INT_RAW_M (GDMA_IN_DONE_CH0_INT_RAW_V << GDMA_IN_DONE_CH0_INT_RAW_S) +#define GDMA_IN_DONE_CH0_INT_RAW_V 0x00000001U +#define GDMA_IN_DONE_CH0_INT_RAW_S 0 +/** GDMA_IN_SUC_EOF_CH0_INT_RAW : R/WTC/SS; bitpos: [1]; default: 0; + * The raw interrupt bit turns to high level when the last data pointed by one inlink + * descriptor has been received for Rx channel 0. For UHCI0 the raw interrupt bit + * turns to high level when the last data pointed by one inlink descriptor has been + * received and no data error is detected for Rx channel 0. + */ +#define GDMA_IN_SUC_EOF_CH0_INT_RAW (BIT(1)) +#define GDMA_IN_SUC_EOF_CH0_INT_RAW_M (GDMA_IN_SUC_EOF_CH0_INT_RAW_V << GDMA_IN_SUC_EOF_CH0_INT_RAW_S) +#define GDMA_IN_SUC_EOF_CH0_INT_RAW_V 0x00000001U +#define GDMA_IN_SUC_EOF_CH0_INT_RAW_S 1 +/** GDMA_IN_ERR_EOF_CH0_INT_RAW : R/WTC/SS; bitpos: [2]; default: 0; + * The raw interrupt bit turns to high level when data error is detected only in the + * case that the peripheral is UHCI0 for Rx channel 0. For other peripherals this raw + * interrupt is reserved. + */ +#define GDMA_IN_ERR_EOF_CH0_INT_RAW (BIT(2)) +#define GDMA_IN_ERR_EOF_CH0_INT_RAW_M (GDMA_IN_ERR_EOF_CH0_INT_RAW_V << GDMA_IN_ERR_EOF_CH0_INT_RAW_S) +#define GDMA_IN_ERR_EOF_CH0_INT_RAW_V 0x00000001U +#define GDMA_IN_ERR_EOF_CH0_INT_RAW_S 2 +/** GDMA_IN_DSCR_ERR_CH0_INT_RAW : R/WTC/SS; bitpos: [3]; default: 0; + * The raw interrupt bit turns to high level when detecting inlink descriptor error + * including owner error and the second and third word error of inlink descriptor for + * Rx channel 0. + */ +#define GDMA_IN_DSCR_ERR_CH0_INT_RAW (BIT(3)) +#define GDMA_IN_DSCR_ERR_CH0_INT_RAW_M (GDMA_IN_DSCR_ERR_CH0_INT_RAW_V << GDMA_IN_DSCR_ERR_CH0_INT_RAW_S) +#define GDMA_IN_DSCR_ERR_CH0_INT_RAW_V 0x00000001U +#define GDMA_IN_DSCR_ERR_CH0_INT_RAW_S 3 +/** GDMA_IN_DSCR_EMPTY_CH0_INT_RAW : R/WTC/SS; bitpos: [4]; default: 0; + * The raw interrupt bit turns to high level when Rx buffer pointed by inlink is full + * and receiving data is not completed but there is no more inlink for Rx channel 0. + */ +#define GDMA_IN_DSCR_EMPTY_CH0_INT_RAW (BIT(4)) +#define GDMA_IN_DSCR_EMPTY_CH0_INT_RAW_M (GDMA_IN_DSCR_EMPTY_CH0_INT_RAW_V << GDMA_IN_DSCR_EMPTY_CH0_INT_RAW_S) +#define GDMA_IN_DSCR_EMPTY_CH0_INT_RAW_V 0x00000001U +#define GDMA_IN_DSCR_EMPTY_CH0_INT_RAW_S 4 +/** GDMA_INFIFO_OVF_CH0_INT_RAW : R/WTC/SS; bitpos: [5]; default: 0; + * This raw interrupt bit turns to high level when level 1 fifo of Rx channel 0 is + * overflow. + */ +#define GDMA_INFIFO_OVF_CH0_INT_RAW (BIT(5)) +#define GDMA_INFIFO_OVF_CH0_INT_RAW_M (GDMA_INFIFO_OVF_CH0_INT_RAW_V << GDMA_INFIFO_OVF_CH0_INT_RAW_S) +#define GDMA_INFIFO_OVF_CH0_INT_RAW_V 0x00000001U +#define GDMA_INFIFO_OVF_CH0_INT_RAW_S 5 +/** GDMA_INFIFO_UDF_CH0_INT_RAW : R/WTC/SS; bitpos: [6]; default: 0; + * This raw interrupt bit turns to high level when level 1 fifo of Rx channel 0 is + * underflow. + */ +#define GDMA_INFIFO_UDF_CH0_INT_RAW (BIT(6)) +#define GDMA_INFIFO_UDF_CH0_INT_RAW_M (GDMA_INFIFO_UDF_CH0_INT_RAW_V << GDMA_INFIFO_UDF_CH0_INT_RAW_S) +#define GDMA_INFIFO_UDF_CH0_INT_RAW_V 0x00000001U +#define GDMA_INFIFO_UDF_CH0_INT_RAW_S 6 + +/** GDMA_IN_INT_ST_CH0_REG register + * Masked interrupt of channel 0. + */ +#define GDMA_IN_INT_ST_CH0_REG (DR_REG_GDMA_BASE + 0x4) +/** GDMA_IN_DONE_CH0_INT_ST : RO; bitpos: [0]; default: 0; + * The raw interrupt status bit for the IN_DONE_CH_INT interrupt. + */ +#define GDMA_IN_DONE_CH0_INT_ST (BIT(0)) +#define GDMA_IN_DONE_CH0_INT_ST_M (GDMA_IN_DONE_CH0_INT_ST_V << GDMA_IN_DONE_CH0_INT_ST_S) +#define GDMA_IN_DONE_CH0_INT_ST_V 0x00000001U +#define GDMA_IN_DONE_CH0_INT_ST_S 0 +/** GDMA_IN_SUC_EOF_CH0_INT_ST : RO; bitpos: [1]; default: 0; + * The raw interrupt status bit for the IN_SUC_EOF_CH_INT interrupt. + */ +#define GDMA_IN_SUC_EOF_CH0_INT_ST (BIT(1)) +#define GDMA_IN_SUC_EOF_CH0_INT_ST_M (GDMA_IN_SUC_EOF_CH0_INT_ST_V << GDMA_IN_SUC_EOF_CH0_INT_ST_S) +#define GDMA_IN_SUC_EOF_CH0_INT_ST_V 0x00000001U +#define GDMA_IN_SUC_EOF_CH0_INT_ST_S 1 +/** GDMA_IN_ERR_EOF_CH0_INT_ST : RO; bitpos: [2]; default: 0; + * The raw interrupt status bit for the IN_ERR_EOF_CH_INT interrupt. + */ +#define GDMA_IN_ERR_EOF_CH0_INT_ST (BIT(2)) +#define GDMA_IN_ERR_EOF_CH0_INT_ST_M (GDMA_IN_ERR_EOF_CH0_INT_ST_V << GDMA_IN_ERR_EOF_CH0_INT_ST_S) +#define GDMA_IN_ERR_EOF_CH0_INT_ST_V 0x00000001U +#define GDMA_IN_ERR_EOF_CH0_INT_ST_S 2 +/** GDMA_IN_DSCR_ERR_CH0_INT_ST : RO; bitpos: [3]; default: 0; + * The raw interrupt status bit for the IN_DSCR_ERR_CH_INT interrupt. + */ +#define GDMA_IN_DSCR_ERR_CH0_INT_ST (BIT(3)) +#define GDMA_IN_DSCR_ERR_CH0_INT_ST_M (GDMA_IN_DSCR_ERR_CH0_INT_ST_V << GDMA_IN_DSCR_ERR_CH0_INT_ST_S) +#define GDMA_IN_DSCR_ERR_CH0_INT_ST_V 0x00000001U +#define GDMA_IN_DSCR_ERR_CH0_INT_ST_S 3 +/** GDMA_IN_DSCR_EMPTY_CH0_INT_ST : RO; bitpos: [4]; default: 0; + * The raw interrupt status bit for the IN_DSCR_EMPTY_CH_INT interrupt. + */ +#define GDMA_IN_DSCR_EMPTY_CH0_INT_ST (BIT(4)) +#define GDMA_IN_DSCR_EMPTY_CH0_INT_ST_M (GDMA_IN_DSCR_EMPTY_CH0_INT_ST_V << GDMA_IN_DSCR_EMPTY_CH0_INT_ST_S) +#define GDMA_IN_DSCR_EMPTY_CH0_INT_ST_V 0x00000001U +#define GDMA_IN_DSCR_EMPTY_CH0_INT_ST_S 4 +/** GDMA_INFIFO_OVF_CH0_INT_ST : RO; bitpos: [5]; default: 0; + * The raw interrupt status bit for the INFIFO_OVF_L1_CH_INT interrupt. + */ +#define GDMA_INFIFO_OVF_CH0_INT_ST (BIT(5)) +#define GDMA_INFIFO_OVF_CH0_INT_ST_M (GDMA_INFIFO_OVF_CH0_INT_ST_V << GDMA_INFIFO_OVF_CH0_INT_ST_S) +#define GDMA_INFIFO_OVF_CH0_INT_ST_V 0x00000001U +#define GDMA_INFIFO_OVF_CH0_INT_ST_S 5 +/** GDMA_INFIFO_UDF_CH0_INT_ST : RO; bitpos: [6]; default: 0; + * The raw interrupt status bit for the INFIFO_UDF_L1_CH_INT interrupt. + */ +#define GDMA_INFIFO_UDF_CH0_INT_ST (BIT(6)) +#define GDMA_INFIFO_UDF_CH0_INT_ST_M (GDMA_INFIFO_UDF_CH0_INT_ST_V << GDMA_INFIFO_UDF_CH0_INT_ST_S) +#define GDMA_INFIFO_UDF_CH0_INT_ST_V 0x00000001U +#define GDMA_INFIFO_UDF_CH0_INT_ST_S 6 + +/** GDMA_IN_INT_ENA_CH0_REG register + * Interrupt enable bits of channel 0. + */ +#define GDMA_IN_INT_ENA_CH0_REG (DR_REG_GDMA_BASE + 0x8) +/** GDMA_IN_DONE_CH0_INT_ENA : R/W; bitpos: [0]; default: 0; + * The interrupt enable bit for the IN_DONE_CH_INT interrupt. + */ +#define GDMA_IN_DONE_CH0_INT_ENA (BIT(0)) +#define GDMA_IN_DONE_CH0_INT_ENA_M (GDMA_IN_DONE_CH0_INT_ENA_V << GDMA_IN_DONE_CH0_INT_ENA_S) +#define GDMA_IN_DONE_CH0_INT_ENA_V 0x00000001U +#define GDMA_IN_DONE_CH0_INT_ENA_S 0 +/** GDMA_IN_SUC_EOF_CH0_INT_ENA : R/W; bitpos: [1]; default: 0; + * The interrupt enable bit for the IN_SUC_EOF_CH_INT interrupt. + */ +#define GDMA_IN_SUC_EOF_CH0_INT_ENA (BIT(1)) +#define GDMA_IN_SUC_EOF_CH0_INT_ENA_M (GDMA_IN_SUC_EOF_CH0_INT_ENA_V << GDMA_IN_SUC_EOF_CH0_INT_ENA_S) +#define GDMA_IN_SUC_EOF_CH0_INT_ENA_V 0x00000001U +#define GDMA_IN_SUC_EOF_CH0_INT_ENA_S 1 +/** GDMA_IN_ERR_EOF_CH0_INT_ENA : R/W; bitpos: [2]; default: 0; + * The interrupt enable bit for the IN_ERR_EOF_CH_INT interrupt. + */ +#define GDMA_IN_ERR_EOF_CH0_INT_ENA (BIT(2)) +#define GDMA_IN_ERR_EOF_CH0_INT_ENA_M (GDMA_IN_ERR_EOF_CH0_INT_ENA_V << GDMA_IN_ERR_EOF_CH0_INT_ENA_S) +#define GDMA_IN_ERR_EOF_CH0_INT_ENA_V 0x00000001U +#define GDMA_IN_ERR_EOF_CH0_INT_ENA_S 2 +/** GDMA_IN_DSCR_ERR_CH0_INT_ENA : R/W; bitpos: [3]; default: 0; + * The interrupt enable bit for the IN_DSCR_ERR_CH_INT interrupt. + */ +#define GDMA_IN_DSCR_ERR_CH0_INT_ENA (BIT(3)) +#define GDMA_IN_DSCR_ERR_CH0_INT_ENA_M (GDMA_IN_DSCR_ERR_CH0_INT_ENA_V << GDMA_IN_DSCR_ERR_CH0_INT_ENA_S) +#define GDMA_IN_DSCR_ERR_CH0_INT_ENA_V 0x00000001U +#define GDMA_IN_DSCR_ERR_CH0_INT_ENA_S 3 +/** GDMA_IN_DSCR_EMPTY_CH0_INT_ENA : R/W; bitpos: [4]; default: 0; + * The interrupt enable bit for the IN_DSCR_EMPTY_CH_INT interrupt. + */ +#define GDMA_IN_DSCR_EMPTY_CH0_INT_ENA (BIT(4)) +#define GDMA_IN_DSCR_EMPTY_CH0_INT_ENA_M (GDMA_IN_DSCR_EMPTY_CH0_INT_ENA_V << GDMA_IN_DSCR_EMPTY_CH0_INT_ENA_S) +#define GDMA_IN_DSCR_EMPTY_CH0_INT_ENA_V 0x00000001U +#define GDMA_IN_DSCR_EMPTY_CH0_INT_ENA_S 4 +/** GDMA_INFIFO_OVF_CH0_INT_ENA : R/W; bitpos: [5]; default: 0; + * The interrupt enable bit for the INFIFO_OVF_L1_CH_INT interrupt. + */ +#define GDMA_INFIFO_OVF_CH0_INT_ENA (BIT(5)) +#define GDMA_INFIFO_OVF_CH0_INT_ENA_M (GDMA_INFIFO_OVF_CH0_INT_ENA_V << GDMA_INFIFO_OVF_CH0_INT_ENA_S) +#define GDMA_INFIFO_OVF_CH0_INT_ENA_V 0x00000001U +#define GDMA_INFIFO_OVF_CH0_INT_ENA_S 5 +/** GDMA_INFIFO_UDF_CH0_INT_ENA : R/W; bitpos: [6]; default: 0; + * The interrupt enable bit for the INFIFO_UDF_L1_CH_INT interrupt. + */ +#define GDMA_INFIFO_UDF_CH0_INT_ENA (BIT(6)) +#define GDMA_INFIFO_UDF_CH0_INT_ENA_M (GDMA_INFIFO_UDF_CH0_INT_ENA_V << GDMA_INFIFO_UDF_CH0_INT_ENA_S) +#define GDMA_INFIFO_UDF_CH0_INT_ENA_V 0x00000001U +#define GDMA_INFIFO_UDF_CH0_INT_ENA_S 6 + +/** GDMA_IN_INT_CLR_CH0_REG register + * Interrupt clear bits of channel 0. + */ +#define GDMA_IN_INT_CLR_CH0_REG (DR_REG_GDMA_BASE + 0xc) +/** GDMA_IN_DONE_CH0_INT_CLR : WT; bitpos: [0]; default: 0; + * Set this bit to clear the IN_DONE_CH_INT interrupt. + */ +#define GDMA_IN_DONE_CH0_INT_CLR (BIT(0)) +#define GDMA_IN_DONE_CH0_INT_CLR_M (GDMA_IN_DONE_CH0_INT_CLR_V << GDMA_IN_DONE_CH0_INT_CLR_S) +#define GDMA_IN_DONE_CH0_INT_CLR_V 0x00000001U +#define GDMA_IN_DONE_CH0_INT_CLR_S 0 +/** GDMA_IN_SUC_EOF_CH0_INT_CLR : WT; bitpos: [1]; default: 0; + * Set this bit to clear the IN_SUC_EOF_CH_INT interrupt. + */ +#define GDMA_IN_SUC_EOF_CH0_INT_CLR (BIT(1)) +#define GDMA_IN_SUC_EOF_CH0_INT_CLR_M (GDMA_IN_SUC_EOF_CH0_INT_CLR_V << GDMA_IN_SUC_EOF_CH0_INT_CLR_S) +#define GDMA_IN_SUC_EOF_CH0_INT_CLR_V 0x00000001U +#define GDMA_IN_SUC_EOF_CH0_INT_CLR_S 1 +/** GDMA_IN_ERR_EOF_CH0_INT_CLR : WT; bitpos: [2]; default: 0; + * Set this bit to clear the IN_ERR_EOF_CH_INT interrupt. + */ +#define GDMA_IN_ERR_EOF_CH0_INT_CLR (BIT(2)) +#define GDMA_IN_ERR_EOF_CH0_INT_CLR_M (GDMA_IN_ERR_EOF_CH0_INT_CLR_V << GDMA_IN_ERR_EOF_CH0_INT_CLR_S) +#define GDMA_IN_ERR_EOF_CH0_INT_CLR_V 0x00000001U +#define GDMA_IN_ERR_EOF_CH0_INT_CLR_S 2 +/** GDMA_IN_DSCR_ERR_CH0_INT_CLR : WT; bitpos: [3]; default: 0; + * Set this bit to clear the IN_DSCR_ERR_CH_INT interrupt. + */ +#define GDMA_IN_DSCR_ERR_CH0_INT_CLR (BIT(3)) +#define GDMA_IN_DSCR_ERR_CH0_INT_CLR_M (GDMA_IN_DSCR_ERR_CH0_INT_CLR_V << GDMA_IN_DSCR_ERR_CH0_INT_CLR_S) +#define GDMA_IN_DSCR_ERR_CH0_INT_CLR_V 0x00000001U +#define GDMA_IN_DSCR_ERR_CH0_INT_CLR_S 3 +/** GDMA_IN_DSCR_EMPTY_CH0_INT_CLR : WT; bitpos: [4]; default: 0; + * Set this bit to clear the IN_DSCR_EMPTY_CH_INT interrupt. + */ +#define GDMA_IN_DSCR_EMPTY_CH0_INT_CLR (BIT(4)) +#define GDMA_IN_DSCR_EMPTY_CH0_INT_CLR_M (GDMA_IN_DSCR_EMPTY_CH0_INT_CLR_V << GDMA_IN_DSCR_EMPTY_CH0_INT_CLR_S) +#define GDMA_IN_DSCR_EMPTY_CH0_INT_CLR_V 0x00000001U +#define GDMA_IN_DSCR_EMPTY_CH0_INT_CLR_S 4 +/** GDMA_INFIFO_OVF_CH0_INT_CLR : WT; bitpos: [5]; default: 0; + * Set this bit to clear the INFIFO_OVF_L1_CH_INT interrupt. + */ +#define GDMA_INFIFO_OVF_CH0_INT_CLR (BIT(5)) +#define GDMA_INFIFO_OVF_CH0_INT_CLR_M (GDMA_INFIFO_OVF_CH0_INT_CLR_V << GDMA_INFIFO_OVF_CH0_INT_CLR_S) +#define GDMA_INFIFO_OVF_CH0_INT_CLR_V 0x00000001U +#define GDMA_INFIFO_OVF_CH0_INT_CLR_S 5 +/** GDMA_INFIFO_UDF_CH0_INT_CLR : WT; bitpos: [6]; default: 0; + * Set this bit to clear the INFIFO_UDF_L1_CH_INT interrupt. + */ +#define GDMA_INFIFO_UDF_CH0_INT_CLR (BIT(6)) +#define GDMA_INFIFO_UDF_CH0_INT_CLR_M (GDMA_INFIFO_UDF_CH0_INT_CLR_V << GDMA_INFIFO_UDF_CH0_INT_CLR_S) +#define GDMA_INFIFO_UDF_CH0_INT_CLR_V 0x00000001U +#define GDMA_INFIFO_UDF_CH0_INT_CLR_S 6 + +/** GDMA_IN_INT_RAW_CH1_REG register + * Raw status interrupt of channel 1. + */ +#define GDMA_IN_INT_RAW_CH1_REG (DR_REG_GDMA_BASE + 0x10) +/** GDMA_IN_DONE_CH1_INT_RAW : R/WTC/SS; bitpos: [0]; default: 0; + * The raw interrupt bit turns to high level when the last data pointed by one inlink + * descriptor has been received for Rx channel 1. + */ +#define GDMA_IN_DONE_CH1_INT_RAW (BIT(0)) +#define GDMA_IN_DONE_CH1_INT_RAW_M (GDMA_IN_DONE_CH1_INT_RAW_V << GDMA_IN_DONE_CH1_INT_RAW_S) +#define GDMA_IN_DONE_CH1_INT_RAW_V 0x00000001U +#define GDMA_IN_DONE_CH1_INT_RAW_S 0 +/** GDMA_IN_SUC_EOF_CH1_INT_RAW : R/WTC/SS; bitpos: [1]; default: 0; + * The raw interrupt bit turns to high level when the last data pointed by one inlink + * descriptor has been received for Rx channel 1. For UHCI0 the raw interrupt bit + * turns to high level when the last data pointed by one inlink descriptor has been + * received and no data error is detected for Rx channel 1. + */ +#define GDMA_IN_SUC_EOF_CH1_INT_RAW (BIT(1)) +#define GDMA_IN_SUC_EOF_CH1_INT_RAW_M (GDMA_IN_SUC_EOF_CH1_INT_RAW_V << GDMA_IN_SUC_EOF_CH1_INT_RAW_S) +#define GDMA_IN_SUC_EOF_CH1_INT_RAW_V 0x00000001U +#define GDMA_IN_SUC_EOF_CH1_INT_RAW_S 1 +/** GDMA_IN_ERR_EOF_CH1_INT_RAW : R/WTC/SS; bitpos: [2]; default: 0; + * The raw interrupt bit turns to high level when data error is detected only in the + * case that the peripheral is UHCI0 for Rx channel 1. For other peripherals this raw + * interrupt is reserved. + */ +#define GDMA_IN_ERR_EOF_CH1_INT_RAW (BIT(2)) +#define GDMA_IN_ERR_EOF_CH1_INT_RAW_M (GDMA_IN_ERR_EOF_CH1_INT_RAW_V << GDMA_IN_ERR_EOF_CH1_INT_RAW_S) +#define GDMA_IN_ERR_EOF_CH1_INT_RAW_V 0x00000001U +#define GDMA_IN_ERR_EOF_CH1_INT_RAW_S 2 +/** GDMA_IN_DSCR_ERR_CH1_INT_RAW : R/WTC/SS; bitpos: [3]; default: 0; + * The raw interrupt bit turns to high level when detecting inlink descriptor error + * including owner error and the second and third word error of inlink descriptor for + * Rx channel 1. + */ +#define GDMA_IN_DSCR_ERR_CH1_INT_RAW (BIT(3)) +#define GDMA_IN_DSCR_ERR_CH1_INT_RAW_M (GDMA_IN_DSCR_ERR_CH1_INT_RAW_V << GDMA_IN_DSCR_ERR_CH1_INT_RAW_S) +#define GDMA_IN_DSCR_ERR_CH1_INT_RAW_V 0x00000001U +#define GDMA_IN_DSCR_ERR_CH1_INT_RAW_S 3 +/** GDMA_IN_DSCR_EMPTY_CH1_INT_RAW : R/WTC/SS; bitpos: [4]; default: 0; + * The raw interrupt bit turns to high level when Rx buffer pointed by inlink is full + * and receiving data is not completed but there is no more inlink for Rx channel 1. + */ +#define GDMA_IN_DSCR_EMPTY_CH1_INT_RAW (BIT(4)) +#define GDMA_IN_DSCR_EMPTY_CH1_INT_RAW_M (GDMA_IN_DSCR_EMPTY_CH1_INT_RAW_V << GDMA_IN_DSCR_EMPTY_CH1_INT_RAW_S) +#define GDMA_IN_DSCR_EMPTY_CH1_INT_RAW_V 0x00000001U +#define GDMA_IN_DSCR_EMPTY_CH1_INT_RAW_S 4 +/** GDMA_INFIFO_OVF_CH1_INT_RAW : R/WTC/SS; bitpos: [5]; default: 0; + * This raw interrupt bit turns to high level when level 1 fifo of Rx channel 1 is + * overflow. + */ +#define GDMA_INFIFO_OVF_CH1_INT_RAW (BIT(5)) +#define GDMA_INFIFO_OVF_CH1_INT_RAW_M (GDMA_INFIFO_OVF_CH1_INT_RAW_V << GDMA_INFIFO_OVF_CH1_INT_RAW_S) +#define GDMA_INFIFO_OVF_CH1_INT_RAW_V 0x00000001U +#define GDMA_INFIFO_OVF_CH1_INT_RAW_S 5 +/** GDMA_INFIFO_UDF_CH1_INT_RAW : R/WTC/SS; bitpos: [6]; default: 0; + * This raw interrupt bit turns to high level when level 1 fifo of Rx channel 1 is + * underflow. + */ +#define GDMA_INFIFO_UDF_CH1_INT_RAW (BIT(6)) +#define GDMA_INFIFO_UDF_CH1_INT_RAW_M (GDMA_INFIFO_UDF_CH1_INT_RAW_V << GDMA_INFIFO_UDF_CH1_INT_RAW_S) +#define GDMA_INFIFO_UDF_CH1_INT_RAW_V 0x00000001U +#define GDMA_INFIFO_UDF_CH1_INT_RAW_S 6 + +/** GDMA_IN_INT_ST_CH1_REG register + * Masked interrupt of channel 1. + */ +#define GDMA_IN_INT_ST_CH1_REG (DR_REG_GDMA_BASE + 0x14) +/** GDMA_IN_DONE_CH1_INT_ST : RO; bitpos: [0]; default: 0; + * The raw interrupt status bit for the IN_DONE_CH_INT interrupt. + */ +#define GDMA_IN_DONE_CH1_INT_ST (BIT(0)) +#define GDMA_IN_DONE_CH1_INT_ST_M (GDMA_IN_DONE_CH1_INT_ST_V << GDMA_IN_DONE_CH1_INT_ST_S) +#define GDMA_IN_DONE_CH1_INT_ST_V 0x00000001U +#define GDMA_IN_DONE_CH1_INT_ST_S 0 +/** GDMA_IN_SUC_EOF_CH1_INT_ST : RO; bitpos: [1]; default: 0; + * The raw interrupt status bit for the IN_SUC_EOF_CH_INT interrupt. + */ +#define GDMA_IN_SUC_EOF_CH1_INT_ST (BIT(1)) +#define GDMA_IN_SUC_EOF_CH1_INT_ST_M (GDMA_IN_SUC_EOF_CH1_INT_ST_V << GDMA_IN_SUC_EOF_CH1_INT_ST_S) +#define GDMA_IN_SUC_EOF_CH1_INT_ST_V 0x00000001U +#define GDMA_IN_SUC_EOF_CH1_INT_ST_S 1 +/** GDMA_IN_ERR_EOF_CH1_INT_ST : RO; bitpos: [2]; default: 0; + * The raw interrupt status bit for the IN_ERR_EOF_CH_INT interrupt. + */ +#define GDMA_IN_ERR_EOF_CH1_INT_ST (BIT(2)) +#define GDMA_IN_ERR_EOF_CH1_INT_ST_M (GDMA_IN_ERR_EOF_CH1_INT_ST_V << GDMA_IN_ERR_EOF_CH1_INT_ST_S) +#define GDMA_IN_ERR_EOF_CH1_INT_ST_V 0x00000001U +#define GDMA_IN_ERR_EOF_CH1_INT_ST_S 2 +/** GDMA_IN_DSCR_ERR_CH1_INT_ST : RO; bitpos: [3]; default: 0; + * The raw interrupt status bit for the IN_DSCR_ERR_CH_INT interrupt. + */ +#define GDMA_IN_DSCR_ERR_CH1_INT_ST (BIT(3)) +#define GDMA_IN_DSCR_ERR_CH1_INT_ST_M (GDMA_IN_DSCR_ERR_CH1_INT_ST_V << GDMA_IN_DSCR_ERR_CH1_INT_ST_S) +#define GDMA_IN_DSCR_ERR_CH1_INT_ST_V 0x00000001U +#define GDMA_IN_DSCR_ERR_CH1_INT_ST_S 3 +/** GDMA_IN_DSCR_EMPTY_CH1_INT_ST : RO; bitpos: [4]; default: 0; + * The raw interrupt status bit for the IN_DSCR_EMPTY_CH_INT interrupt. + */ +#define GDMA_IN_DSCR_EMPTY_CH1_INT_ST (BIT(4)) +#define GDMA_IN_DSCR_EMPTY_CH1_INT_ST_M (GDMA_IN_DSCR_EMPTY_CH1_INT_ST_V << GDMA_IN_DSCR_EMPTY_CH1_INT_ST_S) +#define GDMA_IN_DSCR_EMPTY_CH1_INT_ST_V 0x00000001U +#define GDMA_IN_DSCR_EMPTY_CH1_INT_ST_S 4 +/** GDMA_INFIFO_OVF_CH1_INT_ST : RO; bitpos: [5]; default: 0; + * The raw interrupt status bit for the INFIFO_OVF_L1_CH_INT interrupt. + */ +#define GDMA_INFIFO_OVF_CH1_INT_ST (BIT(5)) +#define GDMA_INFIFO_OVF_CH1_INT_ST_M (GDMA_INFIFO_OVF_CH1_INT_ST_V << GDMA_INFIFO_OVF_CH1_INT_ST_S) +#define GDMA_INFIFO_OVF_CH1_INT_ST_V 0x00000001U +#define GDMA_INFIFO_OVF_CH1_INT_ST_S 5 +/** GDMA_INFIFO_UDF_CH1_INT_ST : RO; bitpos: [6]; default: 0; + * The raw interrupt status bit for the INFIFO_UDF_L1_CH_INT interrupt. + */ +#define GDMA_INFIFO_UDF_CH1_INT_ST (BIT(6)) +#define GDMA_INFIFO_UDF_CH1_INT_ST_M (GDMA_INFIFO_UDF_CH1_INT_ST_V << GDMA_INFIFO_UDF_CH1_INT_ST_S) +#define GDMA_INFIFO_UDF_CH1_INT_ST_V 0x00000001U +#define GDMA_INFIFO_UDF_CH1_INT_ST_S 6 + +/** GDMA_IN_INT_ENA_CH1_REG register + * Interrupt enable bits of channel 1. + */ +#define GDMA_IN_INT_ENA_CH1_REG (DR_REG_GDMA_BASE + 0x18) +/** GDMA_IN_DONE_CH1_INT_ENA : R/W; bitpos: [0]; default: 0; + * The interrupt enable bit for the IN_DONE_CH_INT interrupt. + */ +#define GDMA_IN_DONE_CH1_INT_ENA (BIT(0)) +#define GDMA_IN_DONE_CH1_INT_ENA_M (GDMA_IN_DONE_CH1_INT_ENA_V << GDMA_IN_DONE_CH1_INT_ENA_S) +#define GDMA_IN_DONE_CH1_INT_ENA_V 0x00000001U +#define GDMA_IN_DONE_CH1_INT_ENA_S 0 +/** GDMA_IN_SUC_EOF_CH1_INT_ENA : R/W; bitpos: [1]; default: 0; + * The interrupt enable bit for the IN_SUC_EOF_CH_INT interrupt. + */ +#define GDMA_IN_SUC_EOF_CH1_INT_ENA (BIT(1)) +#define GDMA_IN_SUC_EOF_CH1_INT_ENA_M (GDMA_IN_SUC_EOF_CH1_INT_ENA_V << GDMA_IN_SUC_EOF_CH1_INT_ENA_S) +#define GDMA_IN_SUC_EOF_CH1_INT_ENA_V 0x00000001U +#define GDMA_IN_SUC_EOF_CH1_INT_ENA_S 1 +/** GDMA_IN_ERR_EOF_CH1_INT_ENA : R/W; bitpos: [2]; default: 0; + * The interrupt enable bit for the IN_ERR_EOF_CH_INT interrupt. + */ +#define GDMA_IN_ERR_EOF_CH1_INT_ENA (BIT(2)) +#define GDMA_IN_ERR_EOF_CH1_INT_ENA_M (GDMA_IN_ERR_EOF_CH1_INT_ENA_V << GDMA_IN_ERR_EOF_CH1_INT_ENA_S) +#define GDMA_IN_ERR_EOF_CH1_INT_ENA_V 0x00000001U +#define GDMA_IN_ERR_EOF_CH1_INT_ENA_S 2 +/** GDMA_IN_DSCR_ERR_CH1_INT_ENA : R/W; bitpos: [3]; default: 0; + * The interrupt enable bit for the IN_DSCR_ERR_CH_INT interrupt. + */ +#define GDMA_IN_DSCR_ERR_CH1_INT_ENA (BIT(3)) +#define GDMA_IN_DSCR_ERR_CH1_INT_ENA_M (GDMA_IN_DSCR_ERR_CH1_INT_ENA_V << GDMA_IN_DSCR_ERR_CH1_INT_ENA_S) +#define GDMA_IN_DSCR_ERR_CH1_INT_ENA_V 0x00000001U +#define GDMA_IN_DSCR_ERR_CH1_INT_ENA_S 3 +/** GDMA_IN_DSCR_EMPTY_CH1_INT_ENA : R/W; bitpos: [4]; default: 0; + * The interrupt enable bit for the IN_DSCR_EMPTY_CH_INT interrupt. + */ +#define GDMA_IN_DSCR_EMPTY_CH1_INT_ENA (BIT(4)) +#define GDMA_IN_DSCR_EMPTY_CH1_INT_ENA_M (GDMA_IN_DSCR_EMPTY_CH1_INT_ENA_V << GDMA_IN_DSCR_EMPTY_CH1_INT_ENA_S) +#define GDMA_IN_DSCR_EMPTY_CH1_INT_ENA_V 0x00000001U +#define GDMA_IN_DSCR_EMPTY_CH1_INT_ENA_S 4 +/** GDMA_INFIFO_OVF_CH1_INT_ENA : R/W; bitpos: [5]; default: 0; + * The interrupt enable bit for the INFIFO_OVF_L1_CH_INT interrupt. + */ +#define GDMA_INFIFO_OVF_CH1_INT_ENA (BIT(5)) +#define GDMA_INFIFO_OVF_CH1_INT_ENA_M (GDMA_INFIFO_OVF_CH1_INT_ENA_V << GDMA_INFIFO_OVF_CH1_INT_ENA_S) +#define GDMA_INFIFO_OVF_CH1_INT_ENA_V 0x00000001U +#define GDMA_INFIFO_OVF_CH1_INT_ENA_S 5 +/** GDMA_INFIFO_UDF_CH1_INT_ENA : R/W; bitpos: [6]; default: 0; + * The interrupt enable bit for the INFIFO_UDF_L1_CH_INT interrupt. + */ +#define GDMA_INFIFO_UDF_CH1_INT_ENA (BIT(6)) +#define GDMA_INFIFO_UDF_CH1_INT_ENA_M (GDMA_INFIFO_UDF_CH1_INT_ENA_V << GDMA_INFIFO_UDF_CH1_INT_ENA_S) +#define GDMA_INFIFO_UDF_CH1_INT_ENA_V 0x00000001U +#define GDMA_INFIFO_UDF_CH1_INT_ENA_S 6 + +/** GDMA_IN_INT_CLR_CH1_REG register + * Interrupt clear bits of channel 1. + */ +#define GDMA_IN_INT_CLR_CH1_REG (DR_REG_GDMA_BASE + 0x1c) +/** GDMA_IN_DONE_CH1_INT_CLR : WT; bitpos: [0]; default: 0; + * Set this bit to clear the IN_DONE_CH_INT interrupt. + */ +#define GDMA_IN_DONE_CH1_INT_CLR (BIT(0)) +#define GDMA_IN_DONE_CH1_INT_CLR_M (GDMA_IN_DONE_CH1_INT_CLR_V << GDMA_IN_DONE_CH1_INT_CLR_S) +#define GDMA_IN_DONE_CH1_INT_CLR_V 0x00000001U +#define GDMA_IN_DONE_CH1_INT_CLR_S 0 +/** GDMA_IN_SUC_EOF_CH1_INT_CLR : WT; bitpos: [1]; default: 0; + * Set this bit to clear the IN_SUC_EOF_CH_INT interrupt. + */ +#define GDMA_IN_SUC_EOF_CH1_INT_CLR (BIT(1)) +#define GDMA_IN_SUC_EOF_CH1_INT_CLR_M (GDMA_IN_SUC_EOF_CH1_INT_CLR_V << GDMA_IN_SUC_EOF_CH1_INT_CLR_S) +#define GDMA_IN_SUC_EOF_CH1_INT_CLR_V 0x00000001U +#define GDMA_IN_SUC_EOF_CH1_INT_CLR_S 1 +/** GDMA_IN_ERR_EOF_CH1_INT_CLR : WT; bitpos: [2]; default: 0; + * Set this bit to clear the IN_ERR_EOF_CH_INT interrupt. + */ +#define GDMA_IN_ERR_EOF_CH1_INT_CLR (BIT(2)) +#define GDMA_IN_ERR_EOF_CH1_INT_CLR_M (GDMA_IN_ERR_EOF_CH1_INT_CLR_V << GDMA_IN_ERR_EOF_CH1_INT_CLR_S) +#define GDMA_IN_ERR_EOF_CH1_INT_CLR_V 0x00000001U +#define GDMA_IN_ERR_EOF_CH1_INT_CLR_S 2 +/** GDMA_IN_DSCR_ERR_CH1_INT_CLR : WT; bitpos: [3]; default: 0; + * Set this bit to clear the IN_DSCR_ERR_CH_INT interrupt. + */ +#define GDMA_IN_DSCR_ERR_CH1_INT_CLR (BIT(3)) +#define GDMA_IN_DSCR_ERR_CH1_INT_CLR_M (GDMA_IN_DSCR_ERR_CH1_INT_CLR_V << GDMA_IN_DSCR_ERR_CH1_INT_CLR_S) +#define GDMA_IN_DSCR_ERR_CH1_INT_CLR_V 0x00000001U +#define GDMA_IN_DSCR_ERR_CH1_INT_CLR_S 3 +/** GDMA_IN_DSCR_EMPTY_CH1_INT_CLR : WT; bitpos: [4]; default: 0; + * Set this bit to clear the IN_DSCR_EMPTY_CH_INT interrupt. + */ +#define GDMA_IN_DSCR_EMPTY_CH1_INT_CLR (BIT(4)) +#define GDMA_IN_DSCR_EMPTY_CH1_INT_CLR_M (GDMA_IN_DSCR_EMPTY_CH1_INT_CLR_V << GDMA_IN_DSCR_EMPTY_CH1_INT_CLR_S) +#define GDMA_IN_DSCR_EMPTY_CH1_INT_CLR_V 0x00000001U +#define GDMA_IN_DSCR_EMPTY_CH1_INT_CLR_S 4 +/** GDMA_INFIFO_OVF_CH1_INT_CLR : WT; bitpos: [5]; default: 0; + * Set this bit to clear the INFIFO_OVF_L1_CH_INT interrupt. + */ +#define GDMA_INFIFO_OVF_CH1_INT_CLR (BIT(5)) +#define GDMA_INFIFO_OVF_CH1_INT_CLR_M (GDMA_INFIFO_OVF_CH1_INT_CLR_V << GDMA_INFIFO_OVF_CH1_INT_CLR_S) +#define GDMA_INFIFO_OVF_CH1_INT_CLR_V 0x00000001U +#define GDMA_INFIFO_OVF_CH1_INT_CLR_S 5 +/** GDMA_INFIFO_UDF_CH1_INT_CLR : WT; bitpos: [6]; default: 0; + * Set this bit to clear the INFIFO_UDF_L1_CH_INT interrupt. + */ +#define GDMA_INFIFO_UDF_CH1_INT_CLR (BIT(6)) +#define GDMA_INFIFO_UDF_CH1_INT_CLR_M (GDMA_INFIFO_UDF_CH1_INT_CLR_V << GDMA_INFIFO_UDF_CH1_INT_CLR_S) +#define GDMA_INFIFO_UDF_CH1_INT_CLR_V 0x00000001U +#define GDMA_INFIFO_UDF_CH1_INT_CLR_S 6 + +/** GDMA_IN_INT_RAW_CH2_REG register + * Raw status interrupt of channel 2. + */ +#define GDMA_IN_INT_RAW_CH2_REG (DR_REG_GDMA_BASE + 0x20) +/** GDMA_IN_DONE_CH2_INT_RAW : R/WTC/SS; bitpos: [0]; default: 0; + * The raw interrupt bit turns to high level when the last data pointed by one inlink + * descriptor has been received for Rx channel 2. + */ +#define GDMA_IN_DONE_CH2_INT_RAW (BIT(0)) +#define GDMA_IN_DONE_CH2_INT_RAW_M (GDMA_IN_DONE_CH2_INT_RAW_V << GDMA_IN_DONE_CH2_INT_RAW_S) +#define GDMA_IN_DONE_CH2_INT_RAW_V 0x00000001U +#define GDMA_IN_DONE_CH2_INT_RAW_S 0 +/** GDMA_IN_SUC_EOF_CH2_INT_RAW : R/WTC/SS; bitpos: [1]; default: 0; + * The raw interrupt bit turns to high level when the last data pointed by one inlink + * descriptor has been received for Rx channel 2. For UHCI0 the raw interrupt bit + * turns to high level when the last data pointed by one inlink descriptor has been + * received and no data error is detected for Rx channel 2. + */ +#define GDMA_IN_SUC_EOF_CH2_INT_RAW (BIT(1)) +#define GDMA_IN_SUC_EOF_CH2_INT_RAW_M (GDMA_IN_SUC_EOF_CH2_INT_RAW_V << GDMA_IN_SUC_EOF_CH2_INT_RAW_S) +#define GDMA_IN_SUC_EOF_CH2_INT_RAW_V 0x00000001U +#define GDMA_IN_SUC_EOF_CH2_INT_RAW_S 1 +/** GDMA_IN_ERR_EOF_CH2_INT_RAW : R/WTC/SS; bitpos: [2]; default: 0; + * The raw interrupt bit turns to high level when data error is detected only in the + * case that the peripheral is UHCI0 for Rx channel 2. For other peripherals this raw + * interrupt is reserved. + */ +#define GDMA_IN_ERR_EOF_CH2_INT_RAW (BIT(2)) +#define GDMA_IN_ERR_EOF_CH2_INT_RAW_M (GDMA_IN_ERR_EOF_CH2_INT_RAW_V << GDMA_IN_ERR_EOF_CH2_INT_RAW_S) +#define GDMA_IN_ERR_EOF_CH2_INT_RAW_V 0x00000001U +#define GDMA_IN_ERR_EOF_CH2_INT_RAW_S 2 +/** GDMA_IN_DSCR_ERR_CH2_INT_RAW : R/WTC/SS; bitpos: [3]; default: 0; + * The raw interrupt bit turns to high level when detecting inlink descriptor error + * including owner error and the second and third word error of inlink descriptor for + * Rx channel 2. + */ +#define GDMA_IN_DSCR_ERR_CH2_INT_RAW (BIT(3)) +#define GDMA_IN_DSCR_ERR_CH2_INT_RAW_M (GDMA_IN_DSCR_ERR_CH2_INT_RAW_V << GDMA_IN_DSCR_ERR_CH2_INT_RAW_S) +#define GDMA_IN_DSCR_ERR_CH2_INT_RAW_V 0x00000001U +#define GDMA_IN_DSCR_ERR_CH2_INT_RAW_S 3 +/** GDMA_IN_DSCR_EMPTY_CH2_INT_RAW : R/WTC/SS; bitpos: [4]; default: 0; + * The raw interrupt bit turns to high level when Rx buffer pointed by inlink is full + * and receiving data is not completed but there is no more inlink for Rx channel 2. + */ +#define GDMA_IN_DSCR_EMPTY_CH2_INT_RAW (BIT(4)) +#define GDMA_IN_DSCR_EMPTY_CH2_INT_RAW_M (GDMA_IN_DSCR_EMPTY_CH2_INT_RAW_V << GDMA_IN_DSCR_EMPTY_CH2_INT_RAW_S) +#define GDMA_IN_DSCR_EMPTY_CH2_INT_RAW_V 0x00000001U +#define GDMA_IN_DSCR_EMPTY_CH2_INT_RAW_S 4 +/** GDMA_INFIFO_OVF_CH2_INT_RAW : R/WTC/SS; bitpos: [5]; default: 0; + * This raw interrupt bit turns to high level when level 1 fifo of Rx channel 2 is + * overflow. + */ +#define GDMA_INFIFO_OVF_CH2_INT_RAW (BIT(5)) +#define GDMA_INFIFO_OVF_CH2_INT_RAW_M (GDMA_INFIFO_OVF_CH2_INT_RAW_V << GDMA_INFIFO_OVF_CH2_INT_RAW_S) +#define GDMA_INFIFO_OVF_CH2_INT_RAW_V 0x00000001U +#define GDMA_INFIFO_OVF_CH2_INT_RAW_S 5 +/** GDMA_INFIFO_UDF_CH2_INT_RAW : R/WTC/SS; bitpos: [6]; default: 0; + * This raw interrupt bit turns to high level when level 1 fifo of Rx channel 2 is + * underflow. + */ +#define GDMA_INFIFO_UDF_CH2_INT_RAW (BIT(6)) +#define GDMA_INFIFO_UDF_CH2_INT_RAW_M (GDMA_INFIFO_UDF_CH2_INT_RAW_V << GDMA_INFIFO_UDF_CH2_INT_RAW_S) +#define GDMA_INFIFO_UDF_CH2_INT_RAW_V 0x00000001U +#define GDMA_INFIFO_UDF_CH2_INT_RAW_S 6 + +/** GDMA_IN_INT_ST_CH2_REG register + * Masked interrupt of channel 2. + */ +#define GDMA_IN_INT_ST_CH2_REG (DR_REG_GDMA_BASE + 0x24) +/** GDMA_IN_DONE_CH2_INT_ST : RO; bitpos: [0]; default: 0; + * The raw interrupt status bit for the IN_DONE_CH_INT interrupt. + */ +#define GDMA_IN_DONE_CH2_INT_ST (BIT(0)) +#define GDMA_IN_DONE_CH2_INT_ST_M (GDMA_IN_DONE_CH2_INT_ST_V << GDMA_IN_DONE_CH2_INT_ST_S) +#define GDMA_IN_DONE_CH2_INT_ST_V 0x00000001U +#define GDMA_IN_DONE_CH2_INT_ST_S 0 +/** GDMA_IN_SUC_EOF_CH2_INT_ST : RO; bitpos: [1]; default: 0; + * The raw interrupt status bit for the IN_SUC_EOF_CH_INT interrupt. + */ +#define GDMA_IN_SUC_EOF_CH2_INT_ST (BIT(1)) +#define GDMA_IN_SUC_EOF_CH2_INT_ST_M (GDMA_IN_SUC_EOF_CH2_INT_ST_V << GDMA_IN_SUC_EOF_CH2_INT_ST_S) +#define GDMA_IN_SUC_EOF_CH2_INT_ST_V 0x00000001U +#define GDMA_IN_SUC_EOF_CH2_INT_ST_S 1 +/** GDMA_IN_ERR_EOF_CH2_INT_ST : RO; bitpos: [2]; default: 0; + * The raw interrupt status bit for the IN_ERR_EOF_CH_INT interrupt. + */ +#define GDMA_IN_ERR_EOF_CH2_INT_ST (BIT(2)) +#define GDMA_IN_ERR_EOF_CH2_INT_ST_M (GDMA_IN_ERR_EOF_CH2_INT_ST_V << GDMA_IN_ERR_EOF_CH2_INT_ST_S) +#define GDMA_IN_ERR_EOF_CH2_INT_ST_V 0x00000001U +#define GDMA_IN_ERR_EOF_CH2_INT_ST_S 2 +/** GDMA_IN_DSCR_ERR_CH2_INT_ST : RO; bitpos: [3]; default: 0; + * The raw interrupt status bit for the IN_DSCR_ERR_CH_INT interrupt. + */ +#define GDMA_IN_DSCR_ERR_CH2_INT_ST (BIT(3)) +#define GDMA_IN_DSCR_ERR_CH2_INT_ST_M (GDMA_IN_DSCR_ERR_CH2_INT_ST_V << GDMA_IN_DSCR_ERR_CH2_INT_ST_S) +#define GDMA_IN_DSCR_ERR_CH2_INT_ST_V 0x00000001U +#define GDMA_IN_DSCR_ERR_CH2_INT_ST_S 3 +/** GDMA_IN_DSCR_EMPTY_CH2_INT_ST : RO; bitpos: [4]; default: 0; + * The raw interrupt status bit for the IN_DSCR_EMPTY_CH_INT interrupt. + */ +#define GDMA_IN_DSCR_EMPTY_CH2_INT_ST (BIT(4)) +#define GDMA_IN_DSCR_EMPTY_CH2_INT_ST_M (GDMA_IN_DSCR_EMPTY_CH2_INT_ST_V << GDMA_IN_DSCR_EMPTY_CH2_INT_ST_S) +#define GDMA_IN_DSCR_EMPTY_CH2_INT_ST_V 0x00000001U +#define GDMA_IN_DSCR_EMPTY_CH2_INT_ST_S 4 +/** GDMA_INFIFO_OVF_CH2_INT_ST : RO; bitpos: [5]; default: 0; + * The raw interrupt status bit for the INFIFO_OVF_L1_CH_INT interrupt. + */ +#define GDMA_INFIFO_OVF_CH2_INT_ST (BIT(5)) +#define GDMA_INFIFO_OVF_CH2_INT_ST_M (GDMA_INFIFO_OVF_CH2_INT_ST_V << GDMA_INFIFO_OVF_CH2_INT_ST_S) +#define GDMA_INFIFO_OVF_CH2_INT_ST_V 0x00000001U +#define GDMA_INFIFO_OVF_CH2_INT_ST_S 5 +/** GDMA_INFIFO_UDF_CH2_INT_ST : RO; bitpos: [6]; default: 0; + * The raw interrupt status bit for the INFIFO_UDF_L1_CH_INT interrupt. + */ +#define GDMA_INFIFO_UDF_CH2_INT_ST (BIT(6)) +#define GDMA_INFIFO_UDF_CH2_INT_ST_M (GDMA_INFIFO_UDF_CH2_INT_ST_V << GDMA_INFIFO_UDF_CH2_INT_ST_S) +#define GDMA_INFIFO_UDF_CH2_INT_ST_V 0x00000001U +#define GDMA_INFIFO_UDF_CH2_INT_ST_S 6 + +/** GDMA_IN_INT_ENA_CH2_REG register + * Interrupt enable bits of channel 2. + */ +#define GDMA_IN_INT_ENA_CH2_REG (DR_REG_GDMA_BASE + 0x28) +/** GDMA_IN_DONE_CH2_INT_ENA : R/W; bitpos: [0]; default: 0; + * The interrupt enable bit for the IN_DONE_CH_INT interrupt. + */ +#define GDMA_IN_DONE_CH2_INT_ENA (BIT(0)) +#define GDMA_IN_DONE_CH2_INT_ENA_M (GDMA_IN_DONE_CH2_INT_ENA_V << GDMA_IN_DONE_CH2_INT_ENA_S) +#define GDMA_IN_DONE_CH2_INT_ENA_V 0x00000001U +#define GDMA_IN_DONE_CH2_INT_ENA_S 0 +/** GDMA_IN_SUC_EOF_CH2_INT_ENA : R/W; bitpos: [1]; default: 0; + * The interrupt enable bit for the IN_SUC_EOF_CH_INT interrupt. + */ +#define GDMA_IN_SUC_EOF_CH2_INT_ENA (BIT(1)) +#define GDMA_IN_SUC_EOF_CH2_INT_ENA_M (GDMA_IN_SUC_EOF_CH2_INT_ENA_V << GDMA_IN_SUC_EOF_CH2_INT_ENA_S) +#define GDMA_IN_SUC_EOF_CH2_INT_ENA_V 0x00000001U +#define GDMA_IN_SUC_EOF_CH2_INT_ENA_S 1 +/** GDMA_IN_ERR_EOF_CH2_INT_ENA : R/W; bitpos: [2]; default: 0; + * The interrupt enable bit for the IN_ERR_EOF_CH_INT interrupt. + */ +#define GDMA_IN_ERR_EOF_CH2_INT_ENA (BIT(2)) +#define GDMA_IN_ERR_EOF_CH2_INT_ENA_M (GDMA_IN_ERR_EOF_CH2_INT_ENA_V << GDMA_IN_ERR_EOF_CH2_INT_ENA_S) +#define GDMA_IN_ERR_EOF_CH2_INT_ENA_V 0x00000001U +#define GDMA_IN_ERR_EOF_CH2_INT_ENA_S 2 +/** GDMA_IN_DSCR_ERR_CH2_INT_ENA : R/W; bitpos: [3]; default: 0; + * The interrupt enable bit for the IN_DSCR_ERR_CH_INT interrupt. + */ +#define GDMA_IN_DSCR_ERR_CH2_INT_ENA (BIT(3)) +#define GDMA_IN_DSCR_ERR_CH2_INT_ENA_M (GDMA_IN_DSCR_ERR_CH2_INT_ENA_V << GDMA_IN_DSCR_ERR_CH2_INT_ENA_S) +#define GDMA_IN_DSCR_ERR_CH2_INT_ENA_V 0x00000001U +#define GDMA_IN_DSCR_ERR_CH2_INT_ENA_S 3 +/** GDMA_IN_DSCR_EMPTY_CH2_INT_ENA : R/W; bitpos: [4]; default: 0; + * The interrupt enable bit for the IN_DSCR_EMPTY_CH_INT interrupt. + */ +#define GDMA_IN_DSCR_EMPTY_CH2_INT_ENA (BIT(4)) +#define GDMA_IN_DSCR_EMPTY_CH2_INT_ENA_M (GDMA_IN_DSCR_EMPTY_CH2_INT_ENA_V << GDMA_IN_DSCR_EMPTY_CH2_INT_ENA_S) +#define GDMA_IN_DSCR_EMPTY_CH2_INT_ENA_V 0x00000001U +#define GDMA_IN_DSCR_EMPTY_CH2_INT_ENA_S 4 +/** GDMA_INFIFO_OVF_CH2_INT_ENA : R/W; bitpos: [5]; default: 0; + * The interrupt enable bit for the INFIFO_OVF_L1_CH_INT interrupt. + */ +#define GDMA_INFIFO_OVF_CH2_INT_ENA (BIT(5)) +#define GDMA_INFIFO_OVF_CH2_INT_ENA_M (GDMA_INFIFO_OVF_CH2_INT_ENA_V << GDMA_INFIFO_OVF_CH2_INT_ENA_S) +#define GDMA_INFIFO_OVF_CH2_INT_ENA_V 0x00000001U +#define GDMA_INFIFO_OVF_CH2_INT_ENA_S 5 +/** GDMA_INFIFO_UDF_CH2_INT_ENA : R/W; bitpos: [6]; default: 0; + * The interrupt enable bit for the INFIFO_UDF_L1_CH_INT interrupt. + */ +#define GDMA_INFIFO_UDF_CH2_INT_ENA (BIT(6)) +#define GDMA_INFIFO_UDF_CH2_INT_ENA_M (GDMA_INFIFO_UDF_CH2_INT_ENA_V << GDMA_INFIFO_UDF_CH2_INT_ENA_S) +#define GDMA_INFIFO_UDF_CH2_INT_ENA_V 0x00000001U +#define GDMA_INFIFO_UDF_CH2_INT_ENA_S 6 + +/** GDMA_IN_INT_CLR_CH2_REG register + * Interrupt clear bits of channel 2. + */ +#define GDMA_IN_INT_CLR_CH2_REG (DR_REG_GDMA_BASE + 0x2c) +/** GDMA_IN_DONE_CH2_INT_CLR : WT; bitpos: [0]; default: 0; + * Set this bit to clear the IN_DONE_CH_INT interrupt. + */ +#define GDMA_IN_DONE_CH2_INT_CLR (BIT(0)) +#define GDMA_IN_DONE_CH2_INT_CLR_M (GDMA_IN_DONE_CH2_INT_CLR_V << GDMA_IN_DONE_CH2_INT_CLR_S) +#define GDMA_IN_DONE_CH2_INT_CLR_V 0x00000001U +#define GDMA_IN_DONE_CH2_INT_CLR_S 0 +/** GDMA_IN_SUC_EOF_CH2_INT_CLR : WT; bitpos: [1]; default: 0; + * Set this bit to clear the IN_SUC_EOF_CH_INT interrupt. + */ +#define GDMA_IN_SUC_EOF_CH2_INT_CLR (BIT(1)) +#define GDMA_IN_SUC_EOF_CH2_INT_CLR_M (GDMA_IN_SUC_EOF_CH2_INT_CLR_V << GDMA_IN_SUC_EOF_CH2_INT_CLR_S) +#define GDMA_IN_SUC_EOF_CH2_INT_CLR_V 0x00000001U +#define GDMA_IN_SUC_EOF_CH2_INT_CLR_S 1 +/** GDMA_IN_ERR_EOF_CH2_INT_CLR : WT; bitpos: [2]; default: 0; + * Set this bit to clear the IN_ERR_EOF_CH_INT interrupt. + */ +#define GDMA_IN_ERR_EOF_CH2_INT_CLR (BIT(2)) +#define GDMA_IN_ERR_EOF_CH2_INT_CLR_M (GDMA_IN_ERR_EOF_CH2_INT_CLR_V << GDMA_IN_ERR_EOF_CH2_INT_CLR_S) +#define GDMA_IN_ERR_EOF_CH2_INT_CLR_V 0x00000001U +#define GDMA_IN_ERR_EOF_CH2_INT_CLR_S 2 +/** GDMA_IN_DSCR_ERR_CH2_INT_CLR : WT; bitpos: [3]; default: 0; + * Set this bit to clear the IN_DSCR_ERR_CH_INT interrupt. + */ +#define GDMA_IN_DSCR_ERR_CH2_INT_CLR (BIT(3)) +#define GDMA_IN_DSCR_ERR_CH2_INT_CLR_M (GDMA_IN_DSCR_ERR_CH2_INT_CLR_V << GDMA_IN_DSCR_ERR_CH2_INT_CLR_S) +#define GDMA_IN_DSCR_ERR_CH2_INT_CLR_V 0x00000001U +#define GDMA_IN_DSCR_ERR_CH2_INT_CLR_S 3 +/** GDMA_IN_DSCR_EMPTY_CH2_INT_CLR : WT; bitpos: [4]; default: 0; + * Set this bit to clear the IN_DSCR_EMPTY_CH_INT interrupt. + */ +#define GDMA_IN_DSCR_EMPTY_CH2_INT_CLR (BIT(4)) +#define GDMA_IN_DSCR_EMPTY_CH2_INT_CLR_M (GDMA_IN_DSCR_EMPTY_CH2_INT_CLR_V << GDMA_IN_DSCR_EMPTY_CH2_INT_CLR_S) +#define GDMA_IN_DSCR_EMPTY_CH2_INT_CLR_V 0x00000001U +#define GDMA_IN_DSCR_EMPTY_CH2_INT_CLR_S 4 +/** GDMA_INFIFO_OVF_CH2_INT_CLR : WT; bitpos: [5]; default: 0; + * Set this bit to clear the INFIFO_OVF_L1_CH_INT interrupt. + */ +#define GDMA_INFIFO_OVF_CH2_INT_CLR (BIT(5)) +#define GDMA_INFIFO_OVF_CH2_INT_CLR_M (GDMA_INFIFO_OVF_CH2_INT_CLR_V << GDMA_INFIFO_OVF_CH2_INT_CLR_S) +#define GDMA_INFIFO_OVF_CH2_INT_CLR_V 0x00000001U +#define GDMA_INFIFO_OVF_CH2_INT_CLR_S 5 +/** GDMA_INFIFO_UDF_CH2_INT_CLR : WT; bitpos: [6]; default: 0; + * Set this bit to clear the INFIFO_UDF_L1_CH_INT interrupt. + */ +#define GDMA_INFIFO_UDF_CH2_INT_CLR (BIT(6)) +#define GDMA_INFIFO_UDF_CH2_INT_CLR_M (GDMA_INFIFO_UDF_CH2_INT_CLR_V << GDMA_INFIFO_UDF_CH2_INT_CLR_S) +#define GDMA_INFIFO_UDF_CH2_INT_CLR_V 0x00000001U +#define GDMA_INFIFO_UDF_CH2_INT_CLR_S 6 + +/** GDMA_OUT_INT_RAW_CH0_REG register + * Raw status interrupt of channel 0. + */ +#define GDMA_OUT_INT_RAW_CH0_REG (DR_REG_GDMA_BASE + 0x30) +/** GDMA_OUT_DONE_CH0_INT_RAW : R/WTC/SS; bitpos: [0]; default: 0; + * The raw interrupt bit turns to high level when the last data pointed by one outlink + * descriptor has been transmitted to peripherals for Tx channel 0. + */ +#define GDMA_OUT_DONE_CH0_INT_RAW (BIT(0)) +#define GDMA_OUT_DONE_CH0_INT_RAW_M (GDMA_OUT_DONE_CH0_INT_RAW_V << GDMA_OUT_DONE_CH0_INT_RAW_S) +#define GDMA_OUT_DONE_CH0_INT_RAW_V 0x00000001U +#define GDMA_OUT_DONE_CH0_INT_RAW_S 0 +/** GDMA_OUT_EOF_CH0_INT_RAW : R/WTC/SS; bitpos: [1]; default: 0; + * The raw interrupt bit turns to high level when the last data pointed by one outlink + * descriptor has been read from memory for Tx channel 0. + */ +#define GDMA_OUT_EOF_CH0_INT_RAW (BIT(1)) +#define GDMA_OUT_EOF_CH0_INT_RAW_M (GDMA_OUT_EOF_CH0_INT_RAW_V << GDMA_OUT_EOF_CH0_INT_RAW_S) +#define GDMA_OUT_EOF_CH0_INT_RAW_V 0x00000001U +#define GDMA_OUT_EOF_CH0_INT_RAW_S 1 +/** GDMA_OUT_DSCR_ERR_CH0_INT_RAW : R/WTC/SS; bitpos: [2]; default: 0; + * The raw interrupt bit turns to high level when detecting outlink descriptor error + * including owner error and the second and third word error of outlink descriptor for + * Tx channel 0. + */ +#define GDMA_OUT_DSCR_ERR_CH0_INT_RAW (BIT(2)) +#define GDMA_OUT_DSCR_ERR_CH0_INT_RAW_M (GDMA_OUT_DSCR_ERR_CH0_INT_RAW_V << GDMA_OUT_DSCR_ERR_CH0_INT_RAW_S) +#define GDMA_OUT_DSCR_ERR_CH0_INT_RAW_V 0x00000001U +#define GDMA_OUT_DSCR_ERR_CH0_INT_RAW_S 2 +/** GDMA_OUT_TOTAL_EOF_CH0_INT_RAW : R/WTC/SS; bitpos: [3]; default: 0; + * The raw interrupt bit turns to high level when data corresponding a outlink + * (includes one link descriptor or few link descriptors) is transmitted out for Tx + * channel 0. + */ +#define GDMA_OUT_TOTAL_EOF_CH0_INT_RAW (BIT(3)) +#define GDMA_OUT_TOTAL_EOF_CH0_INT_RAW_M (GDMA_OUT_TOTAL_EOF_CH0_INT_RAW_V << GDMA_OUT_TOTAL_EOF_CH0_INT_RAW_S) +#define GDMA_OUT_TOTAL_EOF_CH0_INT_RAW_V 0x00000001U +#define GDMA_OUT_TOTAL_EOF_CH0_INT_RAW_S 3 +/** GDMA_OUTFIFO_OVF_CH0_INT_RAW : R/WTC/SS; bitpos: [4]; default: 0; + * This raw interrupt bit turns to high level when level 1 fifo of Tx channel 0 is + * overflow. + */ +#define GDMA_OUTFIFO_OVF_CH0_INT_RAW (BIT(4)) +#define GDMA_OUTFIFO_OVF_CH0_INT_RAW_M (GDMA_OUTFIFO_OVF_CH0_INT_RAW_V << GDMA_OUTFIFO_OVF_CH0_INT_RAW_S) +#define GDMA_OUTFIFO_OVF_CH0_INT_RAW_V 0x00000001U +#define GDMA_OUTFIFO_OVF_CH0_INT_RAW_S 4 +/** GDMA_OUTFIFO_UDF_CH0_INT_RAW : R/WTC/SS; bitpos: [5]; default: 0; + * This raw interrupt bit turns to high level when level 1 fifo of Tx channel 0 is + * underflow. + */ +#define GDMA_OUTFIFO_UDF_CH0_INT_RAW (BIT(5)) +#define GDMA_OUTFIFO_UDF_CH0_INT_RAW_M (GDMA_OUTFIFO_UDF_CH0_INT_RAW_V << GDMA_OUTFIFO_UDF_CH0_INT_RAW_S) +#define GDMA_OUTFIFO_UDF_CH0_INT_RAW_V 0x00000001U +#define GDMA_OUTFIFO_UDF_CH0_INT_RAW_S 5 + +/** GDMA_OUT_INT_ST_CH0_REG register + * Masked interrupt of channel 0. + */ +#define GDMA_OUT_INT_ST_CH0_REG (DR_REG_GDMA_BASE + 0x34) +/** GDMA_OUT_DONE_CH0_INT_ST : RO; bitpos: [0]; default: 0; + * The raw interrupt status bit for the OUT_DONE_CH_INT interrupt. + */ +#define GDMA_OUT_DONE_CH0_INT_ST (BIT(0)) +#define GDMA_OUT_DONE_CH0_INT_ST_M (GDMA_OUT_DONE_CH0_INT_ST_V << GDMA_OUT_DONE_CH0_INT_ST_S) +#define GDMA_OUT_DONE_CH0_INT_ST_V 0x00000001U +#define GDMA_OUT_DONE_CH0_INT_ST_S 0 +/** GDMA_OUT_EOF_CH0_INT_ST : RO; bitpos: [1]; default: 0; + * The raw interrupt status bit for the OUT_EOF_CH_INT interrupt. + */ +#define GDMA_OUT_EOF_CH0_INT_ST (BIT(1)) +#define GDMA_OUT_EOF_CH0_INT_ST_M (GDMA_OUT_EOF_CH0_INT_ST_V << GDMA_OUT_EOF_CH0_INT_ST_S) +#define GDMA_OUT_EOF_CH0_INT_ST_V 0x00000001U +#define GDMA_OUT_EOF_CH0_INT_ST_S 1 +/** GDMA_OUT_DSCR_ERR_CH0_INT_ST : RO; bitpos: [2]; default: 0; + * The raw interrupt status bit for the OUT_DSCR_ERR_CH_INT interrupt. + */ +#define GDMA_OUT_DSCR_ERR_CH0_INT_ST (BIT(2)) +#define GDMA_OUT_DSCR_ERR_CH0_INT_ST_M (GDMA_OUT_DSCR_ERR_CH0_INT_ST_V << GDMA_OUT_DSCR_ERR_CH0_INT_ST_S) +#define GDMA_OUT_DSCR_ERR_CH0_INT_ST_V 0x00000001U +#define GDMA_OUT_DSCR_ERR_CH0_INT_ST_S 2 +/** GDMA_OUT_TOTAL_EOF_CH0_INT_ST : RO; bitpos: [3]; default: 0; + * The raw interrupt status bit for the OUT_TOTAL_EOF_CH_INT interrupt. + */ +#define GDMA_OUT_TOTAL_EOF_CH0_INT_ST (BIT(3)) +#define GDMA_OUT_TOTAL_EOF_CH0_INT_ST_M (GDMA_OUT_TOTAL_EOF_CH0_INT_ST_V << GDMA_OUT_TOTAL_EOF_CH0_INT_ST_S) +#define GDMA_OUT_TOTAL_EOF_CH0_INT_ST_V 0x00000001U +#define GDMA_OUT_TOTAL_EOF_CH0_INT_ST_S 3 +/** GDMA_OUTFIFO_OVF_CH0_INT_ST : RO; bitpos: [4]; default: 0; + * The raw interrupt status bit for the OUTFIFO_OVF_L1_CH_INT interrupt. + */ +#define GDMA_OUTFIFO_OVF_CH0_INT_ST (BIT(4)) +#define GDMA_OUTFIFO_OVF_CH0_INT_ST_M (GDMA_OUTFIFO_OVF_CH0_INT_ST_V << GDMA_OUTFIFO_OVF_CH0_INT_ST_S) +#define GDMA_OUTFIFO_OVF_CH0_INT_ST_V 0x00000001U +#define GDMA_OUTFIFO_OVF_CH0_INT_ST_S 4 +/** GDMA_OUTFIFO_UDF_CH0_INT_ST : RO; bitpos: [5]; default: 0; + * The raw interrupt status bit for the OUTFIFO_UDF_L1_CH_INT interrupt. + */ +#define GDMA_OUTFIFO_UDF_CH0_INT_ST (BIT(5)) +#define GDMA_OUTFIFO_UDF_CH0_INT_ST_M (GDMA_OUTFIFO_UDF_CH0_INT_ST_V << GDMA_OUTFIFO_UDF_CH0_INT_ST_S) +#define GDMA_OUTFIFO_UDF_CH0_INT_ST_V 0x00000001U +#define GDMA_OUTFIFO_UDF_CH0_INT_ST_S 5 + +/** GDMA_OUT_INT_ENA_CH0_REG register + * Interrupt enable bits of channel 0. + */ +#define GDMA_OUT_INT_ENA_CH0_REG (DR_REG_GDMA_BASE + 0x38) +/** GDMA_OUT_DONE_CH0_INT_ENA : R/W; bitpos: [0]; default: 0; + * The interrupt enable bit for the OUT_DONE_CH_INT interrupt. + */ +#define GDMA_OUT_DONE_CH0_INT_ENA (BIT(0)) +#define GDMA_OUT_DONE_CH0_INT_ENA_M (GDMA_OUT_DONE_CH0_INT_ENA_V << GDMA_OUT_DONE_CH0_INT_ENA_S) +#define GDMA_OUT_DONE_CH0_INT_ENA_V 0x00000001U +#define GDMA_OUT_DONE_CH0_INT_ENA_S 0 +/** GDMA_OUT_EOF_CH0_INT_ENA : R/W; bitpos: [1]; default: 0; + * The interrupt enable bit for the OUT_EOF_CH_INT interrupt. + */ +#define GDMA_OUT_EOF_CH0_INT_ENA (BIT(1)) +#define GDMA_OUT_EOF_CH0_INT_ENA_M (GDMA_OUT_EOF_CH0_INT_ENA_V << GDMA_OUT_EOF_CH0_INT_ENA_S) +#define GDMA_OUT_EOF_CH0_INT_ENA_V 0x00000001U +#define GDMA_OUT_EOF_CH0_INT_ENA_S 1 +/** GDMA_OUT_DSCR_ERR_CH0_INT_ENA : R/W; bitpos: [2]; default: 0; + * The interrupt enable bit for the OUT_DSCR_ERR_CH_INT interrupt. + */ +#define GDMA_OUT_DSCR_ERR_CH0_INT_ENA (BIT(2)) +#define GDMA_OUT_DSCR_ERR_CH0_INT_ENA_M (GDMA_OUT_DSCR_ERR_CH0_INT_ENA_V << GDMA_OUT_DSCR_ERR_CH0_INT_ENA_S) +#define GDMA_OUT_DSCR_ERR_CH0_INT_ENA_V 0x00000001U +#define GDMA_OUT_DSCR_ERR_CH0_INT_ENA_S 2 +/** GDMA_OUT_TOTAL_EOF_CH0_INT_ENA : R/W; bitpos: [3]; default: 0; + * The interrupt enable bit for the OUT_TOTAL_EOF_CH_INT interrupt. + */ +#define GDMA_OUT_TOTAL_EOF_CH0_INT_ENA (BIT(3)) +#define GDMA_OUT_TOTAL_EOF_CH0_INT_ENA_M (GDMA_OUT_TOTAL_EOF_CH0_INT_ENA_V << GDMA_OUT_TOTAL_EOF_CH0_INT_ENA_S) +#define GDMA_OUT_TOTAL_EOF_CH0_INT_ENA_V 0x00000001U +#define GDMA_OUT_TOTAL_EOF_CH0_INT_ENA_S 3 +/** GDMA_OUTFIFO_OVF_CH0_INT_ENA : R/W; bitpos: [4]; default: 0; + * The interrupt enable bit for the OUTFIFO_OVF_L1_CH_INT interrupt. + */ +#define GDMA_OUTFIFO_OVF_CH0_INT_ENA (BIT(4)) +#define GDMA_OUTFIFO_OVF_CH0_INT_ENA_M (GDMA_OUTFIFO_OVF_CH0_INT_ENA_V << GDMA_OUTFIFO_OVF_CH0_INT_ENA_S) +#define GDMA_OUTFIFO_OVF_CH0_INT_ENA_V 0x00000001U +#define GDMA_OUTFIFO_OVF_CH0_INT_ENA_S 4 +/** GDMA_OUTFIFO_UDF_CH0_INT_ENA : R/W; bitpos: [5]; default: 0; + * The interrupt enable bit for the OUTFIFO_UDF_L1_CH_INT interrupt. + */ +#define GDMA_OUTFIFO_UDF_CH0_INT_ENA (BIT(5)) +#define GDMA_OUTFIFO_UDF_CH0_INT_ENA_M (GDMA_OUTFIFO_UDF_CH0_INT_ENA_V << GDMA_OUTFIFO_UDF_CH0_INT_ENA_S) +#define GDMA_OUTFIFO_UDF_CH0_INT_ENA_V 0x00000001U +#define GDMA_OUTFIFO_UDF_CH0_INT_ENA_S 5 + +/** GDMA_OUT_INT_CLR_CH0_REG register + * Interrupt clear bits of channel 0. + */ +#define GDMA_OUT_INT_CLR_CH0_REG (DR_REG_GDMA_BASE + 0x3c) +/** GDMA_OUT_DONE_CH0_INT_CLR : WT; bitpos: [0]; default: 0; + * Set this bit to clear the OUT_DONE_CH_INT interrupt. + */ +#define GDMA_OUT_DONE_CH0_INT_CLR (BIT(0)) +#define GDMA_OUT_DONE_CH0_INT_CLR_M (GDMA_OUT_DONE_CH0_INT_CLR_V << GDMA_OUT_DONE_CH0_INT_CLR_S) +#define GDMA_OUT_DONE_CH0_INT_CLR_V 0x00000001U +#define GDMA_OUT_DONE_CH0_INT_CLR_S 0 +/** GDMA_OUT_EOF_CH0_INT_CLR : WT; bitpos: [1]; default: 0; + * Set this bit to clear the OUT_EOF_CH_INT interrupt. + */ +#define GDMA_OUT_EOF_CH0_INT_CLR (BIT(1)) +#define GDMA_OUT_EOF_CH0_INT_CLR_M (GDMA_OUT_EOF_CH0_INT_CLR_V << GDMA_OUT_EOF_CH0_INT_CLR_S) +#define GDMA_OUT_EOF_CH0_INT_CLR_V 0x00000001U +#define GDMA_OUT_EOF_CH0_INT_CLR_S 1 +/** GDMA_OUT_DSCR_ERR_CH0_INT_CLR : WT; bitpos: [2]; default: 0; + * Set this bit to clear the OUT_DSCR_ERR_CH_INT interrupt. + */ +#define GDMA_OUT_DSCR_ERR_CH0_INT_CLR (BIT(2)) +#define GDMA_OUT_DSCR_ERR_CH0_INT_CLR_M (GDMA_OUT_DSCR_ERR_CH0_INT_CLR_V << GDMA_OUT_DSCR_ERR_CH0_INT_CLR_S) +#define GDMA_OUT_DSCR_ERR_CH0_INT_CLR_V 0x00000001U +#define GDMA_OUT_DSCR_ERR_CH0_INT_CLR_S 2 +/** GDMA_OUT_TOTAL_EOF_CH0_INT_CLR : WT; bitpos: [3]; default: 0; + * Set this bit to clear the OUT_TOTAL_EOF_CH_INT interrupt. + */ +#define GDMA_OUT_TOTAL_EOF_CH0_INT_CLR (BIT(3)) +#define GDMA_OUT_TOTAL_EOF_CH0_INT_CLR_M (GDMA_OUT_TOTAL_EOF_CH0_INT_CLR_V << GDMA_OUT_TOTAL_EOF_CH0_INT_CLR_S) +#define GDMA_OUT_TOTAL_EOF_CH0_INT_CLR_V 0x00000001U +#define GDMA_OUT_TOTAL_EOF_CH0_INT_CLR_S 3 +/** GDMA_OUTFIFO_OVF_CH0_INT_CLR : WT; bitpos: [4]; default: 0; + * Set this bit to clear the OUTFIFO_OVF_L1_CH_INT interrupt. + */ +#define GDMA_OUTFIFO_OVF_CH0_INT_CLR (BIT(4)) +#define GDMA_OUTFIFO_OVF_CH0_INT_CLR_M (GDMA_OUTFIFO_OVF_CH0_INT_CLR_V << GDMA_OUTFIFO_OVF_CH0_INT_CLR_S) +#define GDMA_OUTFIFO_OVF_CH0_INT_CLR_V 0x00000001U +#define GDMA_OUTFIFO_OVF_CH0_INT_CLR_S 4 +/** GDMA_OUTFIFO_UDF_CH0_INT_CLR : WT; bitpos: [5]; default: 0; + * Set this bit to clear the OUTFIFO_UDF_L1_CH_INT interrupt. + */ +#define GDMA_OUTFIFO_UDF_CH0_INT_CLR (BIT(5)) +#define GDMA_OUTFIFO_UDF_CH0_INT_CLR_M (GDMA_OUTFIFO_UDF_CH0_INT_CLR_V << GDMA_OUTFIFO_UDF_CH0_INT_CLR_S) +#define GDMA_OUTFIFO_UDF_CH0_INT_CLR_V 0x00000001U +#define GDMA_OUTFIFO_UDF_CH0_INT_CLR_S 5 + +/** GDMA_OUT_INT_RAW_CH1_REG register + * Raw status interrupt of channel 1. + */ +#define GDMA_OUT_INT_RAW_CH1_REG (DR_REG_GDMA_BASE + 0x40) +/** GDMA_OUT_DONE_CH1_INT_RAW : R/WTC/SS; bitpos: [0]; default: 0; + * The raw interrupt bit turns to high level when the last data pointed by one outlink + * descriptor has been transmitted to peripherals for Tx channel 1. + */ +#define GDMA_OUT_DONE_CH1_INT_RAW (BIT(0)) +#define GDMA_OUT_DONE_CH1_INT_RAW_M (GDMA_OUT_DONE_CH1_INT_RAW_V << GDMA_OUT_DONE_CH1_INT_RAW_S) +#define GDMA_OUT_DONE_CH1_INT_RAW_V 0x00000001U +#define GDMA_OUT_DONE_CH1_INT_RAW_S 0 +/** GDMA_OUT_EOF_CH1_INT_RAW : R/WTC/SS; bitpos: [1]; default: 0; + * The raw interrupt bit turns to high level when the last data pointed by one outlink + * descriptor has been read from memory for Tx channel 1. + */ +#define GDMA_OUT_EOF_CH1_INT_RAW (BIT(1)) +#define GDMA_OUT_EOF_CH1_INT_RAW_M (GDMA_OUT_EOF_CH1_INT_RAW_V << GDMA_OUT_EOF_CH1_INT_RAW_S) +#define GDMA_OUT_EOF_CH1_INT_RAW_V 0x00000001U +#define GDMA_OUT_EOF_CH1_INT_RAW_S 1 +/** GDMA_OUT_DSCR_ERR_CH1_INT_RAW : R/WTC/SS; bitpos: [2]; default: 0; + * The raw interrupt bit turns to high level when detecting outlink descriptor error + * including owner error and the second and third word error of outlink descriptor for + * Tx channel 1. + */ +#define GDMA_OUT_DSCR_ERR_CH1_INT_RAW (BIT(2)) +#define GDMA_OUT_DSCR_ERR_CH1_INT_RAW_M (GDMA_OUT_DSCR_ERR_CH1_INT_RAW_V << GDMA_OUT_DSCR_ERR_CH1_INT_RAW_S) +#define GDMA_OUT_DSCR_ERR_CH1_INT_RAW_V 0x00000001U +#define GDMA_OUT_DSCR_ERR_CH1_INT_RAW_S 2 +/** GDMA_OUT_TOTAL_EOF_CH1_INT_RAW : R/WTC/SS; bitpos: [3]; default: 0; + * The raw interrupt bit turns to high level when data corresponding a outlink + * (includes one link descriptor or few link descriptors) is transmitted out for Tx + * channel 1. + */ +#define GDMA_OUT_TOTAL_EOF_CH1_INT_RAW (BIT(3)) +#define GDMA_OUT_TOTAL_EOF_CH1_INT_RAW_M (GDMA_OUT_TOTAL_EOF_CH1_INT_RAW_V << GDMA_OUT_TOTAL_EOF_CH1_INT_RAW_S) +#define GDMA_OUT_TOTAL_EOF_CH1_INT_RAW_V 0x00000001U +#define GDMA_OUT_TOTAL_EOF_CH1_INT_RAW_S 3 +/** GDMA_OUTFIFO_OVF_CH1_INT_RAW : R/WTC/SS; bitpos: [4]; default: 0; + * This raw interrupt bit turns to high level when level 1 fifo of Tx channel 1 is + * overflow. + */ +#define GDMA_OUTFIFO_OVF_CH1_INT_RAW (BIT(4)) +#define GDMA_OUTFIFO_OVF_CH1_INT_RAW_M (GDMA_OUTFIFO_OVF_CH1_INT_RAW_V << GDMA_OUTFIFO_OVF_CH1_INT_RAW_S) +#define GDMA_OUTFIFO_OVF_CH1_INT_RAW_V 0x00000001U +#define GDMA_OUTFIFO_OVF_CH1_INT_RAW_S 4 +/** GDMA_OUTFIFO_UDF_CH1_INT_RAW : R/WTC/SS; bitpos: [5]; default: 0; + * This raw interrupt bit turns to high level when level 1 fifo of Tx channel 1 is + * underflow. + */ +#define GDMA_OUTFIFO_UDF_CH1_INT_RAW (BIT(5)) +#define GDMA_OUTFIFO_UDF_CH1_INT_RAW_M (GDMA_OUTFIFO_UDF_CH1_INT_RAW_V << GDMA_OUTFIFO_UDF_CH1_INT_RAW_S) +#define GDMA_OUTFIFO_UDF_CH1_INT_RAW_V 0x00000001U +#define GDMA_OUTFIFO_UDF_CH1_INT_RAW_S 5 + +/** GDMA_OUT_INT_ST_CH1_REG register + * Masked interrupt of channel 1. + */ +#define GDMA_OUT_INT_ST_CH1_REG (DR_REG_GDMA_BASE + 0x44) +/** GDMA_OUT_DONE_CH1_INT_ST : RO; bitpos: [0]; default: 0; + * The raw interrupt status bit for the OUT_DONE_CH_INT interrupt. + */ +#define GDMA_OUT_DONE_CH1_INT_ST (BIT(0)) +#define GDMA_OUT_DONE_CH1_INT_ST_M (GDMA_OUT_DONE_CH1_INT_ST_V << GDMA_OUT_DONE_CH1_INT_ST_S) +#define GDMA_OUT_DONE_CH1_INT_ST_V 0x00000001U +#define GDMA_OUT_DONE_CH1_INT_ST_S 0 +/** GDMA_OUT_EOF_CH1_INT_ST : RO; bitpos: [1]; default: 0; + * The raw interrupt status bit for the OUT_EOF_CH_INT interrupt. + */ +#define GDMA_OUT_EOF_CH1_INT_ST (BIT(1)) +#define GDMA_OUT_EOF_CH1_INT_ST_M (GDMA_OUT_EOF_CH1_INT_ST_V << GDMA_OUT_EOF_CH1_INT_ST_S) +#define GDMA_OUT_EOF_CH1_INT_ST_V 0x00000001U +#define GDMA_OUT_EOF_CH1_INT_ST_S 1 +/** GDMA_OUT_DSCR_ERR_CH1_INT_ST : RO; bitpos: [2]; default: 0; + * The raw interrupt status bit for the OUT_DSCR_ERR_CH_INT interrupt. + */ +#define GDMA_OUT_DSCR_ERR_CH1_INT_ST (BIT(2)) +#define GDMA_OUT_DSCR_ERR_CH1_INT_ST_M (GDMA_OUT_DSCR_ERR_CH1_INT_ST_V << GDMA_OUT_DSCR_ERR_CH1_INT_ST_S) +#define GDMA_OUT_DSCR_ERR_CH1_INT_ST_V 0x00000001U +#define GDMA_OUT_DSCR_ERR_CH1_INT_ST_S 2 +/** GDMA_OUT_TOTAL_EOF_CH1_INT_ST : RO; bitpos: [3]; default: 0; + * The raw interrupt status bit for the OUT_TOTAL_EOF_CH_INT interrupt. + */ +#define GDMA_OUT_TOTAL_EOF_CH1_INT_ST (BIT(3)) +#define GDMA_OUT_TOTAL_EOF_CH1_INT_ST_M (GDMA_OUT_TOTAL_EOF_CH1_INT_ST_V << GDMA_OUT_TOTAL_EOF_CH1_INT_ST_S) +#define GDMA_OUT_TOTAL_EOF_CH1_INT_ST_V 0x00000001U +#define GDMA_OUT_TOTAL_EOF_CH1_INT_ST_S 3 +/** GDMA_OUTFIFO_OVF_CH1_INT_ST : RO; bitpos: [4]; default: 0; + * The raw interrupt status bit for the OUTFIFO_OVF_L1_CH_INT interrupt. + */ +#define GDMA_OUTFIFO_OVF_CH1_INT_ST (BIT(4)) +#define GDMA_OUTFIFO_OVF_CH1_INT_ST_M (GDMA_OUTFIFO_OVF_CH1_INT_ST_V << GDMA_OUTFIFO_OVF_CH1_INT_ST_S) +#define GDMA_OUTFIFO_OVF_CH1_INT_ST_V 0x00000001U +#define GDMA_OUTFIFO_OVF_CH1_INT_ST_S 4 +/** GDMA_OUTFIFO_UDF_CH1_INT_ST : RO; bitpos: [5]; default: 0; + * The raw interrupt status bit for the OUTFIFO_UDF_L1_CH_INT interrupt. + */ +#define GDMA_OUTFIFO_UDF_CH1_INT_ST (BIT(5)) +#define GDMA_OUTFIFO_UDF_CH1_INT_ST_M (GDMA_OUTFIFO_UDF_CH1_INT_ST_V << GDMA_OUTFIFO_UDF_CH1_INT_ST_S) +#define GDMA_OUTFIFO_UDF_CH1_INT_ST_V 0x00000001U +#define GDMA_OUTFIFO_UDF_CH1_INT_ST_S 5 + +/** GDMA_OUT_INT_ENA_CH1_REG register + * Interrupt enable bits of channel 1. + */ +#define GDMA_OUT_INT_ENA_CH1_REG (DR_REG_GDMA_BASE + 0x48) +/** GDMA_OUT_DONE_CH1_INT_ENA : R/W; bitpos: [0]; default: 0; + * The interrupt enable bit for the OUT_DONE_CH_INT interrupt. + */ +#define GDMA_OUT_DONE_CH1_INT_ENA (BIT(0)) +#define GDMA_OUT_DONE_CH1_INT_ENA_M (GDMA_OUT_DONE_CH1_INT_ENA_V << GDMA_OUT_DONE_CH1_INT_ENA_S) +#define GDMA_OUT_DONE_CH1_INT_ENA_V 0x00000001U +#define GDMA_OUT_DONE_CH1_INT_ENA_S 0 +/** GDMA_OUT_EOF_CH1_INT_ENA : R/W; bitpos: [1]; default: 0; + * The interrupt enable bit for the OUT_EOF_CH_INT interrupt. + */ +#define GDMA_OUT_EOF_CH1_INT_ENA (BIT(1)) +#define GDMA_OUT_EOF_CH1_INT_ENA_M (GDMA_OUT_EOF_CH1_INT_ENA_V << GDMA_OUT_EOF_CH1_INT_ENA_S) +#define GDMA_OUT_EOF_CH1_INT_ENA_V 0x00000001U +#define GDMA_OUT_EOF_CH1_INT_ENA_S 1 +/** GDMA_OUT_DSCR_ERR_CH1_INT_ENA : R/W; bitpos: [2]; default: 0; + * The interrupt enable bit for the OUT_DSCR_ERR_CH_INT interrupt. + */ +#define GDMA_OUT_DSCR_ERR_CH1_INT_ENA (BIT(2)) +#define GDMA_OUT_DSCR_ERR_CH1_INT_ENA_M (GDMA_OUT_DSCR_ERR_CH1_INT_ENA_V << GDMA_OUT_DSCR_ERR_CH1_INT_ENA_S) +#define GDMA_OUT_DSCR_ERR_CH1_INT_ENA_V 0x00000001U +#define GDMA_OUT_DSCR_ERR_CH1_INT_ENA_S 2 +/** GDMA_OUT_TOTAL_EOF_CH1_INT_ENA : R/W; bitpos: [3]; default: 0; + * The interrupt enable bit for the OUT_TOTAL_EOF_CH_INT interrupt. + */ +#define GDMA_OUT_TOTAL_EOF_CH1_INT_ENA (BIT(3)) +#define GDMA_OUT_TOTAL_EOF_CH1_INT_ENA_M (GDMA_OUT_TOTAL_EOF_CH1_INT_ENA_V << GDMA_OUT_TOTAL_EOF_CH1_INT_ENA_S) +#define GDMA_OUT_TOTAL_EOF_CH1_INT_ENA_V 0x00000001U +#define GDMA_OUT_TOTAL_EOF_CH1_INT_ENA_S 3 +/** GDMA_OUTFIFO_OVF_CH1_INT_ENA : R/W; bitpos: [4]; default: 0; + * The interrupt enable bit for the OUTFIFO_OVF_L1_CH_INT interrupt. + */ +#define GDMA_OUTFIFO_OVF_CH1_INT_ENA (BIT(4)) +#define GDMA_OUTFIFO_OVF_CH1_INT_ENA_M (GDMA_OUTFIFO_OVF_CH1_INT_ENA_V << GDMA_OUTFIFO_OVF_CH1_INT_ENA_S) +#define GDMA_OUTFIFO_OVF_CH1_INT_ENA_V 0x00000001U +#define GDMA_OUTFIFO_OVF_CH1_INT_ENA_S 4 +/** GDMA_OUTFIFO_UDF_CH1_INT_ENA : R/W; bitpos: [5]; default: 0; + * The interrupt enable bit for the OUTFIFO_UDF_L1_CH_INT interrupt. + */ +#define GDMA_OUTFIFO_UDF_CH1_INT_ENA (BIT(5)) +#define GDMA_OUTFIFO_UDF_CH1_INT_ENA_M (GDMA_OUTFIFO_UDF_CH1_INT_ENA_V << GDMA_OUTFIFO_UDF_CH1_INT_ENA_S) +#define GDMA_OUTFIFO_UDF_CH1_INT_ENA_V 0x00000001U +#define GDMA_OUTFIFO_UDF_CH1_INT_ENA_S 5 + +/** GDMA_OUT_INT_CLR_CH1_REG register + * Interrupt clear bits of channel 1. + */ +#define GDMA_OUT_INT_CLR_CH1_REG (DR_REG_GDMA_BASE + 0x4c) +/** GDMA_OUT_DONE_CH1_INT_CLR : WT; bitpos: [0]; default: 0; + * Set this bit to clear the OUT_DONE_CH_INT interrupt. + */ +#define GDMA_OUT_DONE_CH1_INT_CLR (BIT(0)) +#define GDMA_OUT_DONE_CH1_INT_CLR_M (GDMA_OUT_DONE_CH1_INT_CLR_V << GDMA_OUT_DONE_CH1_INT_CLR_S) +#define GDMA_OUT_DONE_CH1_INT_CLR_V 0x00000001U +#define GDMA_OUT_DONE_CH1_INT_CLR_S 0 +/** GDMA_OUT_EOF_CH1_INT_CLR : WT; bitpos: [1]; default: 0; + * Set this bit to clear the OUT_EOF_CH_INT interrupt. + */ +#define GDMA_OUT_EOF_CH1_INT_CLR (BIT(1)) +#define GDMA_OUT_EOF_CH1_INT_CLR_M (GDMA_OUT_EOF_CH1_INT_CLR_V << GDMA_OUT_EOF_CH1_INT_CLR_S) +#define GDMA_OUT_EOF_CH1_INT_CLR_V 0x00000001U +#define GDMA_OUT_EOF_CH1_INT_CLR_S 1 +/** GDMA_OUT_DSCR_ERR_CH1_INT_CLR : WT; bitpos: [2]; default: 0; + * Set this bit to clear the OUT_DSCR_ERR_CH_INT interrupt. + */ +#define GDMA_OUT_DSCR_ERR_CH1_INT_CLR (BIT(2)) +#define GDMA_OUT_DSCR_ERR_CH1_INT_CLR_M (GDMA_OUT_DSCR_ERR_CH1_INT_CLR_V << GDMA_OUT_DSCR_ERR_CH1_INT_CLR_S) +#define GDMA_OUT_DSCR_ERR_CH1_INT_CLR_V 0x00000001U +#define GDMA_OUT_DSCR_ERR_CH1_INT_CLR_S 2 +/** GDMA_OUT_TOTAL_EOF_CH1_INT_CLR : WT; bitpos: [3]; default: 0; + * Set this bit to clear the OUT_TOTAL_EOF_CH_INT interrupt. + */ +#define GDMA_OUT_TOTAL_EOF_CH1_INT_CLR (BIT(3)) +#define GDMA_OUT_TOTAL_EOF_CH1_INT_CLR_M (GDMA_OUT_TOTAL_EOF_CH1_INT_CLR_V << GDMA_OUT_TOTAL_EOF_CH1_INT_CLR_S) +#define GDMA_OUT_TOTAL_EOF_CH1_INT_CLR_V 0x00000001U +#define GDMA_OUT_TOTAL_EOF_CH1_INT_CLR_S 3 +/** GDMA_OUTFIFO_OVF_CH1_INT_CLR : WT; bitpos: [4]; default: 0; + * Set this bit to clear the OUTFIFO_OVF_L1_CH_INT interrupt. + */ +#define GDMA_OUTFIFO_OVF_CH1_INT_CLR (BIT(4)) +#define GDMA_OUTFIFO_OVF_CH1_INT_CLR_M (GDMA_OUTFIFO_OVF_CH1_INT_CLR_V << GDMA_OUTFIFO_OVF_CH1_INT_CLR_S) +#define GDMA_OUTFIFO_OVF_CH1_INT_CLR_V 0x00000001U +#define GDMA_OUTFIFO_OVF_CH1_INT_CLR_S 4 +/** GDMA_OUTFIFO_UDF_CH1_INT_CLR : WT; bitpos: [5]; default: 0; + * Set this bit to clear the OUTFIFO_UDF_L1_CH_INT interrupt. + */ +#define GDMA_OUTFIFO_UDF_CH1_INT_CLR (BIT(5)) +#define GDMA_OUTFIFO_UDF_CH1_INT_CLR_M (GDMA_OUTFIFO_UDF_CH1_INT_CLR_V << GDMA_OUTFIFO_UDF_CH1_INT_CLR_S) +#define GDMA_OUTFIFO_UDF_CH1_INT_CLR_V 0x00000001U +#define GDMA_OUTFIFO_UDF_CH1_INT_CLR_S 5 + +/** GDMA_OUT_INT_RAW_CH2_REG register + * Raw status interrupt of channel 2. + */ +#define GDMA_OUT_INT_RAW_CH2_REG (DR_REG_GDMA_BASE + 0x50) +/** GDMA_OUT_DONE_CH2_INT_RAW : R/WTC/SS; bitpos: [0]; default: 0; + * The raw interrupt bit turns to high level when the last data pointed by one outlink + * descriptor has been transmitted to peripherals for Tx channel 2. + */ +#define GDMA_OUT_DONE_CH2_INT_RAW (BIT(0)) +#define GDMA_OUT_DONE_CH2_INT_RAW_M (GDMA_OUT_DONE_CH2_INT_RAW_V << GDMA_OUT_DONE_CH2_INT_RAW_S) +#define GDMA_OUT_DONE_CH2_INT_RAW_V 0x00000001U +#define GDMA_OUT_DONE_CH2_INT_RAW_S 0 +/** GDMA_OUT_EOF_CH2_INT_RAW : R/WTC/SS; bitpos: [1]; default: 0; + * The raw interrupt bit turns to high level when the last data pointed by one outlink + * descriptor has been read from memory for Tx channel 2. + */ +#define GDMA_OUT_EOF_CH2_INT_RAW (BIT(1)) +#define GDMA_OUT_EOF_CH2_INT_RAW_M (GDMA_OUT_EOF_CH2_INT_RAW_V << GDMA_OUT_EOF_CH2_INT_RAW_S) +#define GDMA_OUT_EOF_CH2_INT_RAW_V 0x00000001U +#define GDMA_OUT_EOF_CH2_INT_RAW_S 1 +/** GDMA_OUT_DSCR_ERR_CH2_INT_RAW : R/WTC/SS; bitpos: [2]; default: 0; + * The raw interrupt bit turns to high level when detecting outlink descriptor error + * including owner error and the second and third word error of outlink descriptor for + * Tx channel 2. + */ +#define GDMA_OUT_DSCR_ERR_CH2_INT_RAW (BIT(2)) +#define GDMA_OUT_DSCR_ERR_CH2_INT_RAW_M (GDMA_OUT_DSCR_ERR_CH2_INT_RAW_V << GDMA_OUT_DSCR_ERR_CH2_INT_RAW_S) +#define GDMA_OUT_DSCR_ERR_CH2_INT_RAW_V 0x00000001U +#define GDMA_OUT_DSCR_ERR_CH2_INT_RAW_S 2 +/** GDMA_OUT_TOTAL_EOF_CH2_INT_RAW : R/WTC/SS; bitpos: [3]; default: 0; + * The raw interrupt bit turns to high level when data corresponding a outlink + * (includes one link descriptor or few link descriptors) is transmitted out for Tx + * channel 2. + */ +#define GDMA_OUT_TOTAL_EOF_CH2_INT_RAW (BIT(3)) +#define GDMA_OUT_TOTAL_EOF_CH2_INT_RAW_M (GDMA_OUT_TOTAL_EOF_CH2_INT_RAW_V << GDMA_OUT_TOTAL_EOF_CH2_INT_RAW_S) +#define GDMA_OUT_TOTAL_EOF_CH2_INT_RAW_V 0x00000001U +#define GDMA_OUT_TOTAL_EOF_CH2_INT_RAW_S 3 +/** GDMA_OUTFIFO_OVF_CH2_INT_RAW : R/WTC/SS; bitpos: [4]; default: 0; + * This raw interrupt bit turns to high level when level 1 fifo of Tx channel 2 is + * overflow. + */ +#define GDMA_OUTFIFO_OVF_CH2_INT_RAW (BIT(4)) +#define GDMA_OUTFIFO_OVF_CH2_INT_RAW_M (GDMA_OUTFIFO_OVF_CH2_INT_RAW_V << GDMA_OUTFIFO_OVF_CH2_INT_RAW_S) +#define GDMA_OUTFIFO_OVF_CH2_INT_RAW_V 0x00000001U +#define GDMA_OUTFIFO_OVF_CH2_INT_RAW_S 4 +/** GDMA_OUTFIFO_UDF_CH2_INT_RAW : R/WTC/SS; bitpos: [5]; default: 0; + * This raw interrupt bit turns to high level when level 1 fifo of Tx channel 2 is + * underflow. + */ +#define GDMA_OUTFIFO_UDF_CH2_INT_RAW (BIT(5)) +#define GDMA_OUTFIFO_UDF_CH2_INT_RAW_M (GDMA_OUTFIFO_UDF_CH2_INT_RAW_V << GDMA_OUTFIFO_UDF_CH2_INT_RAW_S) +#define GDMA_OUTFIFO_UDF_CH2_INT_RAW_V 0x00000001U +#define GDMA_OUTFIFO_UDF_CH2_INT_RAW_S 5 + +/** GDMA_OUT_INT_ST_CH2_REG register + * Masked interrupt of channel 2. + */ +#define GDMA_OUT_INT_ST_CH2_REG (DR_REG_GDMA_BASE + 0x54) +/** GDMA_OUT_DONE_CH2_INT_ST : RO; bitpos: [0]; default: 0; + * The raw interrupt status bit for the OUT_DONE_CH_INT interrupt. + */ +#define GDMA_OUT_DONE_CH2_INT_ST (BIT(0)) +#define GDMA_OUT_DONE_CH2_INT_ST_M (GDMA_OUT_DONE_CH2_INT_ST_V << GDMA_OUT_DONE_CH2_INT_ST_S) +#define GDMA_OUT_DONE_CH2_INT_ST_V 0x00000001U +#define GDMA_OUT_DONE_CH2_INT_ST_S 0 +/** GDMA_OUT_EOF_CH2_INT_ST : RO; bitpos: [1]; default: 0; + * The raw interrupt status bit for the OUT_EOF_CH_INT interrupt. + */ +#define GDMA_OUT_EOF_CH2_INT_ST (BIT(1)) +#define GDMA_OUT_EOF_CH2_INT_ST_M (GDMA_OUT_EOF_CH2_INT_ST_V << GDMA_OUT_EOF_CH2_INT_ST_S) +#define GDMA_OUT_EOF_CH2_INT_ST_V 0x00000001U +#define GDMA_OUT_EOF_CH2_INT_ST_S 1 +/** GDMA_OUT_DSCR_ERR_CH2_INT_ST : RO; bitpos: [2]; default: 0; + * The raw interrupt status bit for the OUT_DSCR_ERR_CH_INT interrupt. + */ +#define GDMA_OUT_DSCR_ERR_CH2_INT_ST (BIT(2)) +#define GDMA_OUT_DSCR_ERR_CH2_INT_ST_M (GDMA_OUT_DSCR_ERR_CH2_INT_ST_V << GDMA_OUT_DSCR_ERR_CH2_INT_ST_S) +#define GDMA_OUT_DSCR_ERR_CH2_INT_ST_V 0x00000001U +#define GDMA_OUT_DSCR_ERR_CH2_INT_ST_S 2 +/** GDMA_OUT_TOTAL_EOF_CH2_INT_ST : RO; bitpos: [3]; default: 0; + * The raw interrupt status bit for the OUT_TOTAL_EOF_CH_INT interrupt. + */ +#define GDMA_OUT_TOTAL_EOF_CH2_INT_ST (BIT(3)) +#define GDMA_OUT_TOTAL_EOF_CH2_INT_ST_M (GDMA_OUT_TOTAL_EOF_CH2_INT_ST_V << GDMA_OUT_TOTAL_EOF_CH2_INT_ST_S) +#define GDMA_OUT_TOTAL_EOF_CH2_INT_ST_V 0x00000001U +#define GDMA_OUT_TOTAL_EOF_CH2_INT_ST_S 3 +/** GDMA_OUTFIFO_OVF_CH2_INT_ST : RO; bitpos: [4]; default: 0; + * The raw interrupt status bit for the OUTFIFO_OVF_L1_CH_INT interrupt. + */ +#define GDMA_OUTFIFO_OVF_CH2_INT_ST (BIT(4)) +#define GDMA_OUTFIFO_OVF_CH2_INT_ST_M (GDMA_OUTFIFO_OVF_CH2_INT_ST_V << GDMA_OUTFIFO_OVF_CH2_INT_ST_S) +#define GDMA_OUTFIFO_OVF_CH2_INT_ST_V 0x00000001U +#define GDMA_OUTFIFO_OVF_CH2_INT_ST_S 4 +/** GDMA_OUTFIFO_UDF_CH2_INT_ST : RO; bitpos: [5]; default: 0; + * The raw interrupt status bit for the OUTFIFO_UDF_L1_CH_INT interrupt. + */ +#define GDMA_OUTFIFO_UDF_CH2_INT_ST (BIT(5)) +#define GDMA_OUTFIFO_UDF_CH2_INT_ST_M (GDMA_OUTFIFO_UDF_CH2_INT_ST_V << GDMA_OUTFIFO_UDF_CH2_INT_ST_S) +#define GDMA_OUTFIFO_UDF_CH2_INT_ST_V 0x00000001U +#define GDMA_OUTFIFO_UDF_CH2_INT_ST_S 5 + +/** GDMA_OUT_INT_ENA_CH2_REG register + * Interrupt enable bits of channel 2. + */ +#define GDMA_OUT_INT_ENA_CH2_REG (DR_REG_GDMA_BASE + 0x58) +/** GDMA_OUT_DONE_CH2_INT_ENA : R/W; bitpos: [0]; default: 0; + * The interrupt enable bit for the OUT_DONE_CH_INT interrupt. + */ +#define GDMA_OUT_DONE_CH2_INT_ENA (BIT(0)) +#define GDMA_OUT_DONE_CH2_INT_ENA_M (GDMA_OUT_DONE_CH2_INT_ENA_V << GDMA_OUT_DONE_CH2_INT_ENA_S) +#define GDMA_OUT_DONE_CH2_INT_ENA_V 0x00000001U +#define GDMA_OUT_DONE_CH2_INT_ENA_S 0 +/** GDMA_OUT_EOF_CH2_INT_ENA : R/W; bitpos: [1]; default: 0; + * The interrupt enable bit for the OUT_EOF_CH_INT interrupt. + */ +#define GDMA_OUT_EOF_CH2_INT_ENA (BIT(1)) +#define GDMA_OUT_EOF_CH2_INT_ENA_M (GDMA_OUT_EOF_CH2_INT_ENA_V << GDMA_OUT_EOF_CH2_INT_ENA_S) +#define GDMA_OUT_EOF_CH2_INT_ENA_V 0x00000001U +#define GDMA_OUT_EOF_CH2_INT_ENA_S 1 +/** GDMA_OUT_DSCR_ERR_CH2_INT_ENA : R/W; bitpos: [2]; default: 0; + * The interrupt enable bit for the OUT_DSCR_ERR_CH_INT interrupt. + */ +#define GDMA_OUT_DSCR_ERR_CH2_INT_ENA (BIT(2)) +#define GDMA_OUT_DSCR_ERR_CH2_INT_ENA_M (GDMA_OUT_DSCR_ERR_CH2_INT_ENA_V << GDMA_OUT_DSCR_ERR_CH2_INT_ENA_S) +#define GDMA_OUT_DSCR_ERR_CH2_INT_ENA_V 0x00000001U +#define GDMA_OUT_DSCR_ERR_CH2_INT_ENA_S 2 +/** GDMA_OUT_TOTAL_EOF_CH2_INT_ENA : R/W; bitpos: [3]; default: 0; + * The interrupt enable bit for the OUT_TOTAL_EOF_CH_INT interrupt. + */ +#define GDMA_OUT_TOTAL_EOF_CH2_INT_ENA (BIT(3)) +#define GDMA_OUT_TOTAL_EOF_CH2_INT_ENA_M (GDMA_OUT_TOTAL_EOF_CH2_INT_ENA_V << GDMA_OUT_TOTAL_EOF_CH2_INT_ENA_S) +#define GDMA_OUT_TOTAL_EOF_CH2_INT_ENA_V 0x00000001U +#define GDMA_OUT_TOTAL_EOF_CH2_INT_ENA_S 3 +/** GDMA_OUTFIFO_OVF_CH2_INT_ENA : R/W; bitpos: [4]; default: 0; + * The interrupt enable bit for the OUTFIFO_OVF_L1_CH_INT interrupt. + */ +#define GDMA_OUTFIFO_OVF_CH2_INT_ENA (BIT(4)) +#define GDMA_OUTFIFO_OVF_CH2_INT_ENA_M (GDMA_OUTFIFO_OVF_CH2_INT_ENA_V << GDMA_OUTFIFO_OVF_CH2_INT_ENA_S) +#define GDMA_OUTFIFO_OVF_CH2_INT_ENA_V 0x00000001U +#define GDMA_OUTFIFO_OVF_CH2_INT_ENA_S 4 +/** GDMA_OUTFIFO_UDF_CH2_INT_ENA : R/W; bitpos: [5]; default: 0; + * The interrupt enable bit for the OUTFIFO_UDF_L1_CH_INT interrupt. + */ +#define GDMA_OUTFIFO_UDF_CH2_INT_ENA (BIT(5)) +#define GDMA_OUTFIFO_UDF_CH2_INT_ENA_M (GDMA_OUTFIFO_UDF_CH2_INT_ENA_V << GDMA_OUTFIFO_UDF_CH2_INT_ENA_S) +#define GDMA_OUTFIFO_UDF_CH2_INT_ENA_V 0x00000001U +#define GDMA_OUTFIFO_UDF_CH2_INT_ENA_S 5 + +/** GDMA_OUT_INT_CLR_CH2_REG register + * Interrupt clear bits of channel 2. + */ +#define GDMA_OUT_INT_CLR_CH2_REG (DR_REG_GDMA_BASE + 0x5c) +/** GDMA_OUT_DONE_CH2_INT_CLR : WT; bitpos: [0]; default: 0; + * Set this bit to clear the OUT_DONE_CH_INT interrupt. + */ +#define GDMA_OUT_DONE_CH2_INT_CLR (BIT(0)) +#define GDMA_OUT_DONE_CH2_INT_CLR_M (GDMA_OUT_DONE_CH2_INT_CLR_V << GDMA_OUT_DONE_CH2_INT_CLR_S) +#define GDMA_OUT_DONE_CH2_INT_CLR_V 0x00000001U +#define GDMA_OUT_DONE_CH2_INT_CLR_S 0 +/** GDMA_OUT_EOF_CH2_INT_CLR : WT; bitpos: [1]; default: 0; + * Set this bit to clear the OUT_EOF_CH_INT interrupt. + */ +#define GDMA_OUT_EOF_CH2_INT_CLR (BIT(1)) +#define GDMA_OUT_EOF_CH2_INT_CLR_M (GDMA_OUT_EOF_CH2_INT_CLR_V << GDMA_OUT_EOF_CH2_INT_CLR_S) +#define GDMA_OUT_EOF_CH2_INT_CLR_V 0x00000001U +#define GDMA_OUT_EOF_CH2_INT_CLR_S 1 +/** GDMA_OUT_DSCR_ERR_CH2_INT_CLR : WT; bitpos: [2]; default: 0; + * Set this bit to clear the OUT_DSCR_ERR_CH_INT interrupt. + */ +#define GDMA_OUT_DSCR_ERR_CH2_INT_CLR (BIT(2)) +#define GDMA_OUT_DSCR_ERR_CH2_INT_CLR_M (GDMA_OUT_DSCR_ERR_CH2_INT_CLR_V << GDMA_OUT_DSCR_ERR_CH2_INT_CLR_S) +#define GDMA_OUT_DSCR_ERR_CH2_INT_CLR_V 0x00000001U +#define GDMA_OUT_DSCR_ERR_CH2_INT_CLR_S 2 +/** GDMA_OUT_TOTAL_EOF_CH2_INT_CLR : WT; bitpos: [3]; default: 0; + * Set this bit to clear the OUT_TOTAL_EOF_CH_INT interrupt. + */ +#define GDMA_OUT_TOTAL_EOF_CH2_INT_CLR (BIT(3)) +#define GDMA_OUT_TOTAL_EOF_CH2_INT_CLR_M (GDMA_OUT_TOTAL_EOF_CH2_INT_CLR_V << GDMA_OUT_TOTAL_EOF_CH2_INT_CLR_S) +#define GDMA_OUT_TOTAL_EOF_CH2_INT_CLR_V 0x00000001U +#define GDMA_OUT_TOTAL_EOF_CH2_INT_CLR_S 3 +/** GDMA_OUTFIFO_OVF_CH2_INT_CLR : WT; bitpos: [4]; default: 0; + * Set this bit to clear the OUTFIFO_OVF_L1_CH_INT interrupt. + */ +#define GDMA_OUTFIFO_OVF_CH2_INT_CLR (BIT(4)) +#define GDMA_OUTFIFO_OVF_CH2_INT_CLR_M (GDMA_OUTFIFO_OVF_CH2_INT_CLR_V << GDMA_OUTFIFO_OVF_CH2_INT_CLR_S) +#define GDMA_OUTFIFO_OVF_CH2_INT_CLR_V 0x00000001U +#define GDMA_OUTFIFO_OVF_CH2_INT_CLR_S 4 +/** GDMA_OUTFIFO_UDF_CH2_INT_CLR : WT; bitpos: [5]; default: 0; + * Set this bit to clear the OUTFIFO_UDF_L1_CH_INT interrupt. + */ +#define GDMA_OUTFIFO_UDF_CH2_INT_CLR (BIT(5)) +#define GDMA_OUTFIFO_UDF_CH2_INT_CLR_M (GDMA_OUTFIFO_UDF_CH2_INT_CLR_V << GDMA_OUTFIFO_UDF_CH2_INT_CLR_S) +#define GDMA_OUTFIFO_UDF_CH2_INT_CLR_V 0x00000001U +#define GDMA_OUTFIFO_UDF_CH2_INT_CLR_S 5 + +/** GDMA_AHB_TEST_REG register + * reserved + */ +#define GDMA_AHB_TEST_REG (DR_REG_GDMA_BASE + 0x60) +/** GDMA_AHB_TESTMODE : R/W; bitpos: [2:0]; default: 0; + * reserved + */ +#define GDMA_AHB_TESTMODE 0x00000007U +#define GDMA_AHB_TESTMODE_M (GDMA_AHB_TESTMODE_V << GDMA_AHB_TESTMODE_S) +#define GDMA_AHB_TESTMODE_V 0x00000007U +#define GDMA_AHB_TESTMODE_S 0 +/** GDMA_AHB_TESTADDR : R/W; bitpos: [5:4]; default: 0; + * reserved + */ +#define GDMA_AHB_TESTADDR 0x00000003U +#define GDMA_AHB_TESTADDR_M (GDMA_AHB_TESTADDR_V << GDMA_AHB_TESTADDR_S) +#define GDMA_AHB_TESTADDR_V 0x00000003U +#define GDMA_AHB_TESTADDR_S 4 + +/** GDMA_MISC_CONF_REG register + * MISC register + */ +#define GDMA_MISC_CONF_REG (DR_REG_GDMA_BASE + 0x64) +/** GDMA_AHBM_RST_INTER : R/W; bitpos: [0]; default: 0; + * Set this bit then clear this bit to reset the internal ahb FSM. + */ +#define GDMA_AHBM_RST_INTER (BIT(0)) +#define GDMA_AHBM_RST_INTER_M (GDMA_AHBM_RST_INTER_V << GDMA_AHBM_RST_INTER_S) +#define GDMA_AHBM_RST_INTER_V 0x00000001U +#define GDMA_AHBM_RST_INTER_S 0 +/** GDMA_ARB_PRI_DIS : R/W; bitpos: [2]; default: 0; + * Set this bit to disable priority arbitration function. + */ +#define GDMA_ARB_PRI_DIS (BIT(2)) +#define GDMA_ARB_PRI_DIS_M (GDMA_ARB_PRI_DIS_V << GDMA_ARB_PRI_DIS_S) +#define GDMA_ARB_PRI_DIS_V 0x00000001U +#define GDMA_ARB_PRI_DIS_S 2 +/** GDMA_CLK_EN : R/W; bitpos: [3]; default: 0; + * 1'h1: Force clock on for register. 1'h0: Support clock only when application writes + * registers. + */ +#define GDMA_CLK_EN (BIT(3)) +#define GDMA_CLK_EN_M (GDMA_CLK_EN_V << GDMA_CLK_EN_S) +#define GDMA_CLK_EN_V 0x00000001U +#define GDMA_CLK_EN_S 3 + +/** GDMA_DATE_REG register + * Version control register + */ +#define GDMA_DATE_REG (DR_REG_GDMA_BASE + 0x68) +/** GDMA_DATE : R/W; bitpos: [31:0]; default: 35660368; + * register version. + */ +#define GDMA_DATE 0xFFFFFFFFU +#define GDMA_DATE_M (GDMA_DATE_V << GDMA_DATE_S) +#define GDMA_DATE_V 0xFFFFFFFFU +#define GDMA_DATE_S 0 + +/** GDMA_IN_CONF0_CH0_REG register + * Configure 0 register of Rx channel 0. + */ +#define GDMA_IN_CONF0_CH0_REG (DR_REG_GDMA_BASE + 0x70) +/** GDMA_IN_RST_CH0 : R/W; bitpos: [0]; default: 0; + * This bit is used to reset DMA channel 0 Rx FSM and Rx FIFO pointer. + */ +#define GDMA_IN_RST_CH0 (BIT(0)) +#define GDMA_IN_RST_CH0_M (GDMA_IN_RST_CH0_V << GDMA_IN_RST_CH0_S) +#define GDMA_IN_RST_CH0_V 0x00000001U +#define GDMA_IN_RST_CH0_S 0 +/** GDMA_IN_LOOP_TEST_CH0 : R/W; bitpos: [1]; default: 0; + * reserved + */ +#define GDMA_IN_LOOP_TEST_CH0 (BIT(1)) +#define GDMA_IN_LOOP_TEST_CH0_M (GDMA_IN_LOOP_TEST_CH0_V << GDMA_IN_LOOP_TEST_CH0_S) +#define GDMA_IN_LOOP_TEST_CH0_V 0x00000001U +#define GDMA_IN_LOOP_TEST_CH0_S 1 +/** GDMA_INDSCR_BURST_EN_CH0 : R/W; bitpos: [2]; default: 0; + * Set this bit to 1 to enable INCR burst transfer for Rx channel 0 reading link + * descriptor when accessing internal SRAM. + */ +#define GDMA_INDSCR_BURST_EN_CH0 (BIT(2)) +#define GDMA_INDSCR_BURST_EN_CH0_M (GDMA_INDSCR_BURST_EN_CH0_V << GDMA_INDSCR_BURST_EN_CH0_S) +#define GDMA_INDSCR_BURST_EN_CH0_V 0x00000001U +#define GDMA_INDSCR_BURST_EN_CH0_S 2 +/** GDMA_IN_DATA_BURST_EN_CH0 : R/W; bitpos: [3]; default: 0; + * Set this bit to 1 to enable INCR burst transfer for Rx channel 0 receiving data + * when accessing internal SRAM. + */ +#define GDMA_IN_DATA_BURST_EN_CH0 (BIT(3)) +#define GDMA_IN_DATA_BURST_EN_CH0_M (GDMA_IN_DATA_BURST_EN_CH0_V << GDMA_IN_DATA_BURST_EN_CH0_S) +#define GDMA_IN_DATA_BURST_EN_CH0_V 0x00000001U +#define GDMA_IN_DATA_BURST_EN_CH0_S 3 +/** GDMA_MEM_TRANS_EN_CH0 : R/W; bitpos: [4]; default: 0; + * Set this bit 1 to enable automatic transmitting data from memory to memory via DMA. + */ +#define GDMA_MEM_TRANS_EN_CH0 (BIT(4)) +#define GDMA_MEM_TRANS_EN_CH0_M (GDMA_MEM_TRANS_EN_CH0_V << GDMA_MEM_TRANS_EN_CH0_S) +#define GDMA_MEM_TRANS_EN_CH0_V 0x00000001U +#define GDMA_MEM_TRANS_EN_CH0_S 4 +/** GDMA_IN_ETM_EN_CH0 : R/W; bitpos: [5]; default: 0; + * Set this bit to 1 to enable etm control mode, GDMA Rx channel 0 is triggered by etm + * task. + */ +#define GDMA_IN_ETM_EN_CH0 (BIT(5)) +#define GDMA_IN_ETM_EN_CH0_M (GDMA_IN_ETM_EN_CH0_V << GDMA_IN_ETM_EN_CH0_S) +#define GDMA_IN_ETM_EN_CH0_V 0x00000001U +#define GDMA_IN_ETM_EN_CH0_S 5 + +/** GDMA_IN_CONF1_CH0_REG register + * Configure 1 register of Rx channel 0. + */ +#define GDMA_IN_CONF1_CH0_REG (DR_REG_GDMA_BASE + 0x74) +/** GDMA_IN_CHECK_OWNER_CH0 : R/W; bitpos: [12]; default: 0; + * Set this bit to enable checking the owner attribute of the link descriptor. + */ +#define GDMA_IN_CHECK_OWNER_CH0 (BIT(12)) +#define GDMA_IN_CHECK_OWNER_CH0_M (GDMA_IN_CHECK_OWNER_CH0_V << GDMA_IN_CHECK_OWNER_CH0_S) +#define GDMA_IN_CHECK_OWNER_CH0_V 0x00000001U +#define GDMA_IN_CHECK_OWNER_CH0_S 12 + +/** GDMA_INFIFO_STATUS_CH0_REG register + * Receive FIFO status of Rx channel 0. + */ +#define GDMA_INFIFO_STATUS_CH0_REG (DR_REG_GDMA_BASE + 0x78) +/** GDMA_INFIFO_FULL_CH0 : RO; bitpos: [0]; default: 1; + * L1 Rx FIFO full signal for Rx channel 0. + */ +#define GDMA_INFIFO_FULL_CH0 (BIT(0)) +#define GDMA_INFIFO_FULL_CH0_M (GDMA_INFIFO_FULL_CH0_V << GDMA_INFIFO_FULL_CH0_S) +#define GDMA_INFIFO_FULL_CH0_V 0x00000001U +#define GDMA_INFIFO_FULL_CH0_S 0 +/** GDMA_INFIFO_EMPTY_CH0 : RO; bitpos: [1]; default: 1; + * L1 Rx FIFO empty signal for Rx channel 0. + */ +#define GDMA_INFIFO_EMPTY_CH0 (BIT(1)) +#define GDMA_INFIFO_EMPTY_CH0_M (GDMA_INFIFO_EMPTY_CH0_V << GDMA_INFIFO_EMPTY_CH0_S) +#define GDMA_INFIFO_EMPTY_CH0_V 0x00000001U +#define GDMA_INFIFO_EMPTY_CH0_S 1 +/** GDMA_INFIFO_CNT_CH0 : RO; bitpos: [7:2]; default: 0; + * The register stores the byte number of the data in L1 Rx FIFO for Rx channel 0. + */ +#define GDMA_INFIFO_CNT_CH0 0x0000003FU +#define GDMA_INFIFO_CNT_CH0_M (GDMA_INFIFO_CNT_CH0_V << GDMA_INFIFO_CNT_CH0_S) +#define GDMA_INFIFO_CNT_CH0_V 0x0000003FU +#define GDMA_INFIFO_CNT_CH0_S 2 +/** GDMA_IN_REMAIN_UNDER_1B_CH0 : RO; bitpos: [23]; default: 1; + * reserved + */ +#define GDMA_IN_REMAIN_UNDER_1B_CH0 (BIT(23)) +#define GDMA_IN_REMAIN_UNDER_1B_CH0_M (GDMA_IN_REMAIN_UNDER_1B_CH0_V << GDMA_IN_REMAIN_UNDER_1B_CH0_S) +#define GDMA_IN_REMAIN_UNDER_1B_CH0_V 0x00000001U +#define GDMA_IN_REMAIN_UNDER_1B_CH0_S 23 +/** GDMA_IN_REMAIN_UNDER_2B_CH0 : RO; bitpos: [24]; default: 1; + * reserved + */ +#define GDMA_IN_REMAIN_UNDER_2B_CH0 (BIT(24)) +#define GDMA_IN_REMAIN_UNDER_2B_CH0_M (GDMA_IN_REMAIN_UNDER_2B_CH0_V << GDMA_IN_REMAIN_UNDER_2B_CH0_S) +#define GDMA_IN_REMAIN_UNDER_2B_CH0_V 0x00000001U +#define GDMA_IN_REMAIN_UNDER_2B_CH0_S 24 +/** GDMA_IN_REMAIN_UNDER_3B_CH0 : RO; bitpos: [25]; default: 1; + * reserved + */ +#define GDMA_IN_REMAIN_UNDER_3B_CH0 (BIT(25)) +#define GDMA_IN_REMAIN_UNDER_3B_CH0_M (GDMA_IN_REMAIN_UNDER_3B_CH0_V << GDMA_IN_REMAIN_UNDER_3B_CH0_S) +#define GDMA_IN_REMAIN_UNDER_3B_CH0_V 0x00000001U +#define GDMA_IN_REMAIN_UNDER_3B_CH0_S 25 +/** GDMA_IN_REMAIN_UNDER_4B_CH0 : RO; bitpos: [26]; default: 1; + * reserved + */ +#define GDMA_IN_REMAIN_UNDER_4B_CH0 (BIT(26)) +#define GDMA_IN_REMAIN_UNDER_4B_CH0_M (GDMA_IN_REMAIN_UNDER_4B_CH0_V << GDMA_IN_REMAIN_UNDER_4B_CH0_S) +#define GDMA_IN_REMAIN_UNDER_4B_CH0_V 0x00000001U +#define GDMA_IN_REMAIN_UNDER_4B_CH0_S 26 +/** GDMA_IN_BUF_HUNGRY_CH0 : RO; bitpos: [27]; default: 0; + * reserved + */ +#define GDMA_IN_BUF_HUNGRY_CH0 (BIT(27)) +#define GDMA_IN_BUF_HUNGRY_CH0_M (GDMA_IN_BUF_HUNGRY_CH0_V << GDMA_IN_BUF_HUNGRY_CH0_S) +#define GDMA_IN_BUF_HUNGRY_CH0_V 0x00000001U +#define GDMA_IN_BUF_HUNGRY_CH0_S 27 + +/** GDMA_IN_POP_CH0_REG register + * Pop control register of Rx channel 0. + */ +#define GDMA_IN_POP_CH0_REG (DR_REG_GDMA_BASE + 0x7c) +/** GDMA_INFIFO_RDATA_CH0 : RO; bitpos: [11:0]; default: 2048; + * This register stores the data popping from GDMA FIFO. + */ +#define GDMA_INFIFO_RDATA_CH0 0x00000FFFU +#define GDMA_INFIFO_RDATA_CH0_M (GDMA_INFIFO_RDATA_CH0_V << GDMA_INFIFO_RDATA_CH0_S) +#define GDMA_INFIFO_RDATA_CH0_V 0x00000FFFU +#define GDMA_INFIFO_RDATA_CH0_S 0 +/** GDMA_INFIFO_POP_CH0 : WT; bitpos: [12]; default: 0; + * Set this bit to pop data from GDMA FIFO. + */ +#define GDMA_INFIFO_POP_CH0 (BIT(12)) +#define GDMA_INFIFO_POP_CH0_M (GDMA_INFIFO_POP_CH0_V << GDMA_INFIFO_POP_CH0_S) +#define GDMA_INFIFO_POP_CH0_V 0x00000001U +#define GDMA_INFIFO_POP_CH0_S 12 + +/** GDMA_IN_LINK_CH0_REG register + * Link descriptor configure and control register of Rx channel 0. + */ +#define GDMA_IN_LINK_CH0_REG (DR_REG_GDMA_BASE + 0x80) +/** GDMA_INLINK_ADDR_CH0 : R/W; bitpos: [19:0]; default: 0; + * This register stores the 20 least significant bits of the first inlink descriptor's + * address. + */ +#define GDMA_INLINK_ADDR_CH0 0x000FFFFFU +#define GDMA_INLINK_ADDR_CH0_M (GDMA_INLINK_ADDR_CH0_V << GDMA_INLINK_ADDR_CH0_S) +#define GDMA_INLINK_ADDR_CH0_V 0x000FFFFFU +#define GDMA_INLINK_ADDR_CH0_S 0 +/** GDMA_INLINK_AUTO_RET_CH0 : R/W; bitpos: [20]; default: 1; + * Set this bit to return to current inlink descriptor's address when there are some + * errors in current receiving data. + */ +#define GDMA_INLINK_AUTO_RET_CH0 (BIT(20)) +#define GDMA_INLINK_AUTO_RET_CH0_M (GDMA_INLINK_AUTO_RET_CH0_V << GDMA_INLINK_AUTO_RET_CH0_S) +#define GDMA_INLINK_AUTO_RET_CH0_V 0x00000001U +#define GDMA_INLINK_AUTO_RET_CH0_S 20 +/** GDMA_INLINK_STOP_CH0 : WT; bitpos: [21]; default: 0; + * Set this bit to stop dealing with the inlink descriptors. + */ +#define GDMA_INLINK_STOP_CH0 (BIT(21)) +#define GDMA_INLINK_STOP_CH0_M (GDMA_INLINK_STOP_CH0_V << GDMA_INLINK_STOP_CH0_S) +#define GDMA_INLINK_STOP_CH0_V 0x00000001U +#define GDMA_INLINK_STOP_CH0_S 21 +/** GDMA_INLINK_START_CH0 : WT; bitpos: [22]; default: 0; + * Set this bit to start dealing with the inlink descriptors. + */ +#define GDMA_INLINK_START_CH0 (BIT(22)) +#define GDMA_INLINK_START_CH0_M (GDMA_INLINK_START_CH0_V << GDMA_INLINK_START_CH0_S) +#define GDMA_INLINK_START_CH0_V 0x00000001U +#define GDMA_INLINK_START_CH0_S 22 +/** GDMA_INLINK_RESTART_CH0 : WT; bitpos: [23]; default: 0; + * Set this bit to mount a new inlink descriptor. + */ +#define GDMA_INLINK_RESTART_CH0 (BIT(23)) +#define GDMA_INLINK_RESTART_CH0_M (GDMA_INLINK_RESTART_CH0_V << GDMA_INLINK_RESTART_CH0_S) +#define GDMA_INLINK_RESTART_CH0_V 0x00000001U +#define GDMA_INLINK_RESTART_CH0_S 23 +/** GDMA_INLINK_PARK_CH0 : RO; bitpos: [24]; default: 1; + * 1: the inlink descriptor's FSM is in idle state. 0: the inlink descriptor's FSM is + * working. + */ +#define GDMA_INLINK_PARK_CH0 (BIT(24)) +#define GDMA_INLINK_PARK_CH0_M (GDMA_INLINK_PARK_CH0_V << GDMA_INLINK_PARK_CH0_S) +#define GDMA_INLINK_PARK_CH0_V 0x00000001U +#define GDMA_INLINK_PARK_CH0_S 24 + +/** GDMA_IN_STATE_CH0_REG register + * Receive status of Rx channel 0. + */ +#define GDMA_IN_STATE_CH0_REG (DR_REG_GDMA_BASE + 0x84) +/** GDMA_INLINK_DSCR_ADDR_CH0 : RO; bitpos: [17:0]; default: 0; + * This register stores the current inlink descriptor's address. + */ +#define GDMA_INLINK_DSCR_ADDR_CH0 0x0003FFFFU +#define GDMA_INLINK_DSCR_ADDR_CH0_M (GDMA_INLINK_DSCR_ADDR_CH0_V << GDMA_INLINK_DSCR_ADDR_CH0_S) +#define GDMA_INLINK_DSCR_ADDR_CH0_V 0x0003FFFFU +#define GDMA_INLINK_DSCR_ADDR_CH0_S 0 +/** GDMA_IN_DSCR_STATE_CH0 : RO; bitpos: [19:18]; default: 0; + * reserved + */ +#define GDMA_IN_DSCR_STATE_CH0 0x00000003U +#define GDMA_IN_DSCR_STATE_CH0_M (GDMA_IN_DSCR_STATE_CH0_V << GDMA_IN_DSCR_STATE_CH0_S) +#define GDMA_IN_DSCR_STATE_CH0_V 0x00000003U +#define GDMA_IN_DSCR_STATE_CH0_S 18 +/** GDMA_IN_STATE_CH0 : RO; bitpos: [22:20]; default: 0; + * reserved + */ +#define GDMA_IN_STATE_CH0 0x00000007U +#define GDMA_IN_STATE_CH0_M (GDMA_IN_STATE_CH0_V << GDMA_IN_STATE_CH0_S) +#define GDMA_IN_STATE_CH0_V 0x00000007U +#define GDMA_IN_STATE_CH0_S 20 + +/** GDMA_IN_SUC_EOF_DES_ADDR_CH0_REG register + * Inlink descriptor address when EOF occurs of Rx channel 0. + */ +#define GDMA_IN_SUC_EOF_DES_ADDR_CH0_REG (DR_REG_GDMA_BASE + 0x88) +/** GDMA_IN_SUC_EOF_DES_ADDR_CH0 : RO; bitpos: [31:0]; default: 0; + * This register stores the address of the inlink descriptor when the EOF bit in this + * descriptor is 1. + */ +#define GDMA_IN_SUC_EOF_DES_ADDR_CH0 0xFFFFFFFFU +#define GDMA_IN_SUC_EOF_DES_ADDR_CH0_M (GDMA_IN_SUC_EOF_DES_ADDR_CH0_V << GDMA_IN_SUC_EOF_DES_ADDR_CH0_S) +#define GDMA_IN_SUC_EOF_DES_ADDR_CH0_V 0xFFFFFFFFU +#define GDMA_IN_SUC_EOF_DES_ADDR_CH0_S 0 + +/** GDMA_IN_ERR_EOF_DES_ADDR_CH0_REG register + * Inlink descriptor address when errors occur of Rx channel 0. + */ +#define GDMA_IN_ERR_EOF_DES_ADDR_CH0_REG (DR_REG_GDMA_BASE + 0x8c) +/** GDMA_IN_ERR_EOF_DES_ADDR_CH0 : RO; bitpos: [31:0]; default: 0; + * This register stores the address of the inlink descriptor when there are some + * errors in current receiving data. Only used when peripheral is UHCI0. + */ +#define GDMA_IN_ERR_EOF_DES_ADDR_CH0 0xFFFFFFFFU +#define GDMA_IN_ERR_EOF_DES_ADDR_CH0_M (GDMA_IN_ERR_EOF_DES_ADDR_CH0_V << GDMA_IN_ERR_EOF_DES_ADDR_CH0_S) +#define GDMA_IN_ERR_EOF_DES_ADDR_CH0_V 0xFFFFFFFFU +#define GDMA_IN_ERR_EOF_DES_ADDR_CH0_S 0 + +/** GDMA_IN_DSCR_CH0_REG register + * Current inlink descriptor address of Rx channel 0. + */ +#define GDMA_IN_DSCR_CH0_REG (DR_REG_GDMA_BASE + 0x90) +/** GDMA_INLINK_DSCR_CH0 : RO; bitpos: [31:0]; default: 0; + * The address of the current inlink descriptor x. + */ +#define GDMA_INLINK_DSCR_CH0 0xFFFFFFFFU +#define GDMA_INLINK_DSCR_CH0_M (GDMA_INLINK_DSCR_CH0_V << GDMA_INLINK_DSCR_CH0_S) +#define GDMA_INLINK_DSCR_CH0_V 0xFFFFFFFFU +#define GDMA_INLINK_DSCR_CH0_S 0 + +/** GDMA_IN_DSCR_BF0_CH0_REG register + * The last inlink descriptor address of Rx channel 0. + */ +#define GDMA_IN_DSCR_BF0_CH0_REG (DR_REG_GDMA_BASE + 0x94) +/** GDMA_INLINK_DSCR_BF0_CH0 : RO; bitpos: [31:0]; default: 0; + * The address of the last inlink descriptor x-1. + */ +#define GDMA_INLINK_DSCR_BF0_CH0 0xFFFFFFFFU +#define GDMA_INLINK_DSCR_BF0_CH0_M (GDMA_INLINK_DSCR_BF0_CH0_V << GDMA_INLINK_DSCR_BF0_CH0_S) +#define GDMA_INLINK_DSCR_BF0_CH0_V 0xFFFFFFFFU +#define GDMA_INLINK_DSCR_BF0_CH0_S 0 + +/** GDMA_IN_DSCR_BF1_CH0_REG register + * The second-to-last inlink descriptor address of Rx channel 0. + */ +#define GDMA_IN_DSCR_BF1_CH0_REG (DR_REG_GDMA_BASE + 0x98) +/** GDMA_INLINK_DSCR_BF1_CH0 : RO; bitpos: [31:0]; default: 0; + * The address of the second-to-last inlink descriptor x-2. + */ +#define GDMA_INLINK_DSCR_BF1_CH0 0xFFFFFFFFU +#define GDMA_INLINK_DSCR_BF1_CH0_M (GDMA_INLINK_DSCR_BF1_CH0_V << GDMA_INLINK_DSCR_BF1_CH0_S) +#define GDMA_INLINK_DSCR_BF1_CH0_V 0xFFFFFFFFU +#define GDMA_INLINK_DSCR_BF1_CH0_S 0 + +/** GDMA_IN_PRI_CH0_REG register + * Priority register of Rx channel 0. + */ +#define GDMA_IN_PRI_CH0_REG (DR_REG_GDMA_BASE + 0x9c) +/** GDMA_RX_PRI_CH0 : R/W; bitpos: [3:0]; default: 0; + * The priority of Rx channel 0. The larger of the value the higher of the priority. + */ +#define GDMA_RX_PRI_CH0 0x0000000FU +#define GDMA_RX_PRI_CH0_M (GDMA_RX_PRI_CH0_V << GDMA_RX_PRI_CH0_S) +#define GDMA_RX_PRI_CH0_V 0x0000000FU +#define GDMA_RX_PRI_CH0_S 0 + +/** GDMA_IN_PERI_SEL_CH0_REG register + * Peripheral selection of Rx channel 0. + */ +#define GDMA_IN_PERI_SEL_CH0_REG (DR_REG_GDMA_BASE + 0xa0) +/** GDMA_PERI_IN_SEL_CH0 : R/W; bitpos: [5:0]; default: 63; + * This register is used to select peripheral for Rx channel 0. 0:SPI2. 1: Dummy. 2: + * UHCI0. 3: I2S0. 4: Dummy. 5: Dummy. 6: AES. 7: SHA. 8: ADC_DAC. 9: Parallel_IO. + * 10~15: Dummy + */ +#define GDMA_PERI_IN_SEL_CH0 0x0000003FU +#define GDMA_PERI_IN_SEL_CH0_M (GDMA_PERI_IN_SEL_CH0_V << GDMA_PERI_IN_SEL_CH0_S) +#define GDMA_PERI_IN_SEL_CH0_V 0x0000003FU +#define GDMA_PERI_IN_SEL_CH0_S 0 + +/** GDMA_OUT_CONF0_CH0_REG register + * Configure 0 register of Tx channel $n. + */ +#define GDMA_OUT_CONF0_CH0_REG (DR_REG_GDMA_BASE + 0xd0) +/** GDMA_OUT_RST_CH0 : R/W; bitpos: [0]; default: 0; + * This bit is used to reset GDMA channel 0 Tx FSM and Tx FIFO pointer. + */ +#define GDMA_OUT_RST_CH0 (BIT(0)) +#define GDMA_OUT_RST_CH0_M (GDMA_OUT_RST_CH0_V << GDMA_OUT_RST_CH0_S) +#define GDMA_OUT_RST_CH0_V 0x00000001U +#define GDMA_OUT_RST_CH0_S 0 +/** GDMA_OUT_LOOP_TEST_CH0 : R/W; bitpos: [1]; default: 0; + * reserved + */ +#define GDMA_OUT_LOOP_TEST_CH0 (BIT(1)) +#define GDMA_OUT_LOOP_TEST_CH0_M (GDMA_OUT_LOOP_TEST_CH0_V << GDMA_OUT_LOOP_TEST_CH0_S) +#define GDMA_OUT_LOOP_TEST_CH0_V 0x00000001U +#define GDMA_OUT_LOOP_TEST_CH0_S 1 +/** GDMA_OUT_AUTO_WRBACK_CH0 : R/W; bitpos: [2]; default: 0; + * Set this bit to enable automatic outlink-writeback when all the data in tx buffer + * has been transmitted. + */ +#define GDMA_OUT_AUTO_WRBACK_CH0 (BIT(2)) +#define GDMA_OUT_AUTO_WRBACK_CH0_M (GDMA_OUT_AUTO_WRBACK_CH0_V << GDMA_OUT_AUTO_WRBACK_CH0_S) +#define GDMA_OUT_AUTO_WRBACK_CH0_V 0x00000001U +#define GDMA_OUT_AUTO_WRBACK_CH0_S 2 +/** GDMA_OUT_EOF_MODE_CH0 : R/W; bitpos: [3]; default: 1; + * EOF flag generation mode when transmitting data. 1: EOF flag for Tx channel 0 is + * generated when data need to transmit has been popped from FIFO in GDMA + */ +#define GDMA_OUT_EOF_MODE_CH0 (BIT(3)) +#define GDMA_OUT_EOF_MODE_CH0_M (GDMA_OUT_EOF_MODE_CH0_V << GDMA_OUT_EOF_MODE_CH0_S) +#define GDMA_OUT_EOF_MODE_CH0_V 0x00000001U +#define GDMA_OUT_EOF_MODE_CH0_S 3 +/** GDMA_OUTDSCR_BURST_EN_CH0 : R/W; bitpos: [4]; default: 0; + * Set this bit to 1 to enable INCR burst transfer for Tx channel 0 reading link + * descriptor when accessing internal SRAM. + */ +#define GDMA_OUTDSCR_BURST_EN_CH0 (BIT(4)) +#define GDMA_OUTDSCR_BURST_EN_CH0_M (GDMA_OUTDSCR_BURST_EN_CH0_V << GDMA_OUTDSCR_BURST_EN_CH0_S) +#define GDMA_OUTDSCR_BURST_EN_CH0_V 0x00000001U +#define GDMA_OUTDSCR_BURST_EN_CH0_S 4 +/** GDMA_OUT_DATA_BURST_EN_CH0 : R/W; bitpos: [5]; default: 0; + * Set this bit to 1 to enable INCR burst transfer for Tx channel 0 transmitting data + * when accessing internal SRAM. + */ +#define GDMA_OUT_DATA_BURST_EN_CH0 (BIT(5)) +#define GDMA_OUT_DATA_BURST_EN_CH0_M (GDMA_OUT_DATA_BURST_EN_CH0_V << GDMA_OUT_DATA_BURST_EN_CH0_S) +#define GDMA_OUT_DATA_BURST_EN_CH0_V 0x00000001U +#define GDMA_OUT_DATA_BURST_EN_CH0_S 5 +/** GDMA_OUT_ETM_EN_CH0 : R/W; bitpos: [6]; default: 0; + * Set this bit to 1 to enable etm control mode, GDMA Tx channel 0 is triggered by etm + * task. + */ +#define GDMA_OUT_ETM_EN_CH0 (BIT(6)) +#define GDMA_OUT_ETM_EN_CH0_M (GDMA_OUT_ETM_EN_CH0_V << GDMA_OUT_ETM_EN_CH0_S) +#define GDMA_OUT_ETM_EN_CH0_V 0x00000001U +#define GDMA_OUT_ETM_EN_CH0_S 6 + +/** GDMA_OUT_CONF1_CH0_REG register + * Configure 1 register of Tx channel 0. + */ +#define GDMA_OUT_CONF1_CH0_REG (DR_REG_GDMA_BASE + 0xd4) +/** GDMA_OUT_CHECK_OWNER_CH0 : R/W; bitpos: [12]; default: 0; + * Set this bit to enable checking the owner attribute of the link descriptor. + */ +#define GDMA_OUT_CHECK_OWNER_CH0 (BIT(12)) +#define GDMA_OUT_CHECK_OWNER_CH0_M (GDMA_OUT_CHECK_OWNER_CH0_V << GDMA_OUT_CHECK_OWNER_CH0_S) +#define GDMA_OUT_CHECK_OWNER_CH0_V 0x00000001U +#define GDMA_OUT_CHECK_OWNER_CH0_S 12 + +/** GDMA_OUTFIFO_STATUS_CH0_REG register + * Transmit FIFO status of Tx channel 0. + */ +#define GDMA_OUTFIFO_STATUS_CH0_REG (DR_REG_GDMA_BASE + 0xd8) +/** GDMA_OUTFIFO_FULL_CH0 : RO; bitpos: [0]; default: 0; + * L1 Tx FIFO full signal for Tx channel 0. + */ +#define GDMA_OUTFIFO_FULL_CH0 (BIT(0)) +#define GDMA_OUTFIFO_FULL_CH0_M (GDMA_OUTFIFO_FULL_CH0_V << GDMA_OUTFIFO_FULL_CH0_S) +#define GDMA_OUTFIFO_FULL_CH0_V 0x00000001U +#define GDMA_OUTFIFO_FULL_CH0_S 0 +/** GDMA_OUTFIFO_EMPTY_CH0 : RO; bitpos: [1]; default: 1; + * L1 Tx FIFO empty signal for Tx channel 0. + */ +#define GDMA_OUTFIFO_EMPTY_CH0 (BIT(1)) +#define GDMA_OUTFIFO_EMPTY_CH0_M (GDMA_OUTFIFO_EMPTY_CH0_V << GDMA_OUTFIFO_EMPTY_CH0_S) +#define GDMA_OUTFIFO_EMPTY_CH0_V 0x00000001U +#define GDMA_OUTFIFO_EMPTY_CH0_S 1 +/** GDMA_OUTFIFO_CNT_CH0 : RO; bitpos: [7:2]; default: 0; + * The register stores the byte number of the data in L1 Tx FIFO for Tx channel 0. + */ +#define GDMA_OUTFIFO_CNT_CH0 0x0000003FU +#define GDMA_OUTFIFO_CNT_CH0_M (GDMA_OUTFIFO_CNT_CH0_V << GDMA_OUTFIFO_CNT_CH0_S) +#define GDMA_OUTFIFO_CNT_CH0_V 0x0000003FU +#define GDMA_OUTFIFO_CNT_CH0_S 2 +/** GDMA_OUT_REMAIN_UNDER_1B_CH0 : RO; bitpos: [23]; default: 1; + * reserved + */ +#define GDMA_OUT_REMAIN_UNDER_1B_CH0 (BIT(23)) +#define GDMA_OUT_REMAIN_UNDER_1B_CH0_M (GDMA_OUT_REMAIN_UNDER_1B_CH0_V << GDMA_OUT_REMAIN_UNDER_1B_CH0_S) +#define GDMA_OUT_REMAIN_UNDER_1B_CH0_V 0x00000001U +#define GDMA_OUT_REMAIN_UNDER_1B_CH0_S 23 +/** GDMA_OUT_REMAIN_UNDER_2B_CH0 : RO; bitpos: [24]; default: 1; + * reserved + */ +#define GDMA_OUT_REMAIN_UNDER_2B_CH0 (BIT(24)) +#define GDMA_OUT_REMAIN_UNDER_2B_CH0_M (GDMA_OUT_REMAIN_UNDER_2B_CH0_V << GDMA_OUT_REMAIN_UNDER_2B_CH0_S) +#define GDMA_OUT_REMAIN_UNDER_2B_CH0_V 0x00000001U +#define GDMA_OUT_REMAIN_UNDER_2B_CH0_S 24 +/** GDMA_OUT_REMAIN_UNDER_3B_CH0 : RO; bitpos: [25]; default: 1; + * reserved + */ +#define GDMA_OUT_REMAIN_UNDER_3B_CH0 (BIT(25)) +#define GDMA_OUT_REMAIN_UNDER_3B_CH0_M (GDMA_OUT_REMAIN_UNDER_3B_CH0_V << GDMA_OUT_REMAIN_UNDER_3B_CH0_S) +#define GDMA_OUT_REMAIN_UNDER_3B_CH0_V 0x00000001U +#define GDMA_OUT_REMAIN_UNDER_3B_CH0_S 25 +/** GDMA_OUT_REMAIN_UNDER_4B_CH0 : RO; bitpos: [26]; default: 1; + * reserved + */ +#define GDMA_OUT_REMAIN_UNDER_4B_CH0 (BIT(26)) +#define GDMA_OUT_REMAIN_UNDER_4B_CH0_M (GDMA_OUT_REMAIN_UNDER_4B_CH0_V << GDMA_OUT_REMAIN_UNDER_4B_CH0_S) +#define GDMA_OUT_REMAIN_UNDER_4B_CH0_V 0x00000001U +#define GDMA_OUT_REMAIN_UNDER_4B_CH0_S 26 + +/** GDMA_OUT_PUSH_CH0_REG register + * Push control register of Rx channel 0. + */ +#define GDMA_OUT_PUSH_CH0_REG (DR_REG_GDMA_BASE + 0xdc) +/** GDMA_OUTFIFO_WDATA_CH0 : R/W; bitpos: [8:0]; default: 0; + * This register stores the data that need to be pushed into GDMA FIFO. + */ +#define GDMA_OUTFIFO_WDATA_CH0 0x000001FFU +#define GDMA_OUTFIFO_WDATA_CH0_M (GDMA_OUTFIFO_WDATA_CH0_V << GDMA_OUTFIFO_WDATA_CH0_S) +#define GDMA_OUTFIFO_WDATA_CH0_V 0x000001FFU +#define GDMA_OUTFIFO_WDATA_CH0_S 0 +/** GDMA_OUTFIFO_PUSH_CH0 : WT; bitpos: [9]; default: 0; + * Set this bit to push data into GDMA FIFO. + */ +#define GDMA_OUTFIFO_PUSH_CH0 (BIT(9)) +#define GDMA_OUTFIFO_PUSH_CH0_M (GDMA_OUTFIFO_PUSH_CH0_V << GDMA_OUTFIFO_PUSH_CH0_S) +#define GDMA_OUTFIFO_PUSH_CH0_V 0x00000001U +#define GDMA_OUTFIFO_PUSH_CH0_S 9 + +/** GDMA_OUT_LINK_CH0_REG register + * Link descriptor configure and control register of Tx channel 0. + */ +#define GDMA_OUT_LINK_CH0_REG (DR_REG_GDMA_BASE + 0xe0) +/** GDMA_OUTLINK_ADDR_CH0 : R/W; bitpos: [19:0]; default: 0; + * This register stores the 20 least significant bits of the first outlink + * descriptor's address. + */ +#define GDMA_OUTLINK_ADDR_CH0 0x000FFFFFU +#define GDMA_OUTLINK_ADDR_CH0_M (GDMA_OUTLINK_ADDR_CH0_V << GDMA_OUTLINK_ADDR_CH0_S) +#define GDMA_OUTLINK_ADDR_CH0_V 0x000FFFFFU +#define GDMA_OUTLINK_ADDR_CH0_S 0 +/** GDMA_OUTLINK_STOP_CH0 : WT; bitpos: [20]; default: 0; + * Set this bit to stop dealing with the outlink descriptors. + */ +#define GDMA_OUTLINK_STOP_CH0 (BIT(20)) +#define GDMA_OUTLINK_STOP_CH0_M (GDMA_OUTLINK_STOP_CH0_V << GDMA_OUTLINK_STOP_CH0_S) +#define GDMA_OUTLINK_STOP_CH0_V 0x00000001U +#define GDMA_OUTLINK_STOP_CH0_S 20 +/** GDMA_OUTLINK_START_CH0 : WT; bitpos: [21]; default: 0; + * Set this bit to start dealing with the outlink descriptors. + */ +#define GDMA_OUTLINK_START_CH0 (BIT(21)) +#define GDMA_OUTLINK_START_CH0_M (GDMA_OUTLINK_START_CH0_V << GDMA_OUTLINK_START_CH0_S) +#define GDMA_OUTLINK_START_CH0_V 0x00000001U +#define GDMA_OUTLINK_START_CH0_S 21 +/** GDMA_OUTLINK_RESTART_CH0 : WT; bitpos: [22]; default: 0; + * Set this bit to restart a new outlink from the last address. + */ +#define GDMA_OUTLINK_RESTART_CH0 (BIT(22)) +#define GDMA_OUTLINK_RESTART_CH0_M (GDMA_OUTLINK_RESTART_CH0_V << GDMA_OUTLINK_RESTART_CH0_S) +#define GDMA_OUTLINK_RESTART_CH0_V 0x00000001U +#define GDMA_OUTLINK_RESTART_CH0_S 22 +/** GDMA_OUTLINK_PARK_CH0 : RO; bitpos: [23]; default: 1; + * 1: the outlink descriptor's FSM is in idle state. 0: the outlink descriptor's FSM + * is working. + */ +#define GDMA_OUTLINK_PARK_CH0 (BIT(23)) +#define GDMA_OUTLINK_PARK_CH0_M (GDMA_OUTLINK_PARK_CH0_V << GDMA_OUTLINK_PARK_CH0_S) +#define GDMA_OUTLINK_PARK_CH0_V 0x00000001U +#define GDMA_OUTLINK_PARK_CH0_S 23 + +/** GDMA_OUT_STATE_CH0_REG register + * Transmit status of Tx channel 0. + */ +#define GDMA_OUT_STATE_CH0_REG (DR_REG_GDMA_BASE + 0xe4) +/** GDMA_OUTLINK_DSCR_ADDR_CH0 : RO; bitpos: [17:0]; default: 0; + * This register stores the current outlink descriptor's address. + */ +#define GDMA_OUTLINK_DSCR_ADDR_CH0 0x0003FFFFU +#define GDMA_OUTLINK_DSCR_ADDR_CH0_M (GDMA_OUTLINK_DSCR_ADDR_CH0_V << GDMA_OUTLINK_DSCR_ADDR_CH0_S) +#define GDMA_OUTLINK_DSCR_ADDR_CH0_V 0x0003FFFFU +#define GDMA_OUTLINK_DSCR_ADDR_CH0_S 0 +/** GDMA_OUT_DSCR_STATE_CH0 : RO; bitpos: [19:18]; default: 0; + * reserved + */ +#define GDMA_OUT_DSCR_STATE_CH0 0x00000003U +#define GDMA_OUT_DSCR_STATE_CH0_M (GDMA_OUT_DSCR_STATE_CH0_V << GDMA_OUT_DSCR_STATE_CH0_S) +#define GDMA_OUT_DSCR_STATE_CH0_V 0x00000003U +#define GDMA_OUT_DSCR_STATE_CH0_S 18 +/** GDMA_OUT_STATE_CH0 : RO; bitpos: [22:20]; default: 0; + * reserved + */ +#define GDMA_OUT_STATE_CH0 0x00000007U +#define GDMA_OUT_STATE_CH0_M (GDMA_OUT_STATE_CH0_V << GDMA_OUT_STATE_CH0_S) +#define GDMA_OUT_STATE_CH0_V 0x00000007U +#define GDMA_OUT_STATE_CH0_S 20 + +/** GDMA_OUT_EOF_DES_ADDR_CH0_REG register + * Outlink descriptor address when EOF occurs of Tx channel 0. + */ +#define GDMA_OUT_EOF_DES_ADDR_CH0_REG (DR_REG_GDMA_BASE + 0xe8) +/** GDMA_OUT_EOF_DES_ADDR_CH0 : RO; bitpos: [31:0]; default: 0; + * This register stores the address of the outlink descriptor when the EOF bit in this + * descriptor is 1. + */ +#define GDMA_OUT_EOF_DES_ADDR_CH0 0xFFFFFFFFU +#define GDMA_OUT_EOF_DES_ADDR_CH0_M (GDMA_OUT_EOF_DES_ADDR_CH0_V << GDMA_OUT_EOF_DES_ADDR_CH0_S) +#define GDMA_OUT_EOF_DES_ADDR_CH0_V 0xFFFFFFFFU +#define GDMA_OUT_EOF_DES_ADDR_CH0_S 0 + +/** GDMA_OUT_EOF_BFR_DES_ADDR_CH0_REG register + * The last outlink descriptor address when EOF occurs of Tx channel 0. + */ +#define GDMA_OUT_EOF_BFR_DES_ADDR_CH0_REG (DR_REG_GDMA_BASE + 0xec) +/** GDMA_OUT_EOF_BFR_DES_ADDR_CH0 : RO; bitpos: [31:0]; default: 0; + * This register stores the address of the outlink descriptor before the last outlink + * descriptor. + */ +#define GDMA_OUT_EOF_BFR_DES_ADDR_CH0 0xFFFFFFFFU +#define GDMA_OUT_EOF_BFR_DES_ADDR_CH0_M (GDMA_OUT_EOF_BFR_DES_ADDR_CH0_V << GDMA_OUT_EOF_BFR_DES_ADDR_CH0_S) +#define GDMA_OUT_EOF_BFR_DES_ADDR_CH0_V 0xFFFFFFFFU +#define GDMA_OUT_EOF_BFR_DES_ADDR_CH0_S 0 + +/** GDMA_OUT_DSCR_CH0_REG register + * Current inlink descriptor address of Tx channel 0. + */ +#define GDMA_OUT_DSCR_CH0_REG (DR_REG_GDMA_BASE + 0xf0) +/** GDMA_OUTLINK_DSCR_CH0 : RO; bitpos: [31:0]; default: 0; + * The address of the current outlink descriptor y. + */ +#define GDMA_OUTLINK_DSCR_CH0 0xFFFFFFFFU +#define GDMA_OUTLINK_DSCR_CH0_M (GDMA_OUTLINK_DSCR_CH0_V << GDMA_OUTLINK_DSCR_CH0_S) +#define GDMA_OUTLINK_DSCR_CH0_V 0xFFFFFFFFU +#define GDMA_OUTLINK_DSCR_CH0_S 0 + +/** GDMA_OUT_DSCR_BF0_CH0_REG register + * The last inlink descriptor address of Tx channel 0. + */ +#define GDMA_OUT_DSCR_BF0_CH0_REG (DR_REG_GDMA_BASE + 0xf4) +/** GDMA_OUTLINK_DSCR_BF0_CH0 : RO; bitpos: [31:0]; default: 0; + * The address of the last outlink descriptor y-1. + */ +#define GDMA_OUTLINK_DSCR_BF0_CH0 0xFFFFFFFFU +#define GDMA_OUTLINK_DSCR_BF0_CH0_M (GDMA_OUTLINK_DSCR_BF0_CH0_V << GDMA_OUTLINK_DSCR_BF0_CH0_S) +#define GDMA_OUTLINK_DSCR_BF0_CH0_V 0xFFFFFFFFU +#define GDMA_OUTLINK_DSCR_BF0_CH0_S 0 + +/** GDMA_OUT_DSCR_BF1_CH0_REG register + * The second-to-last inlink descriptor address of Tx channel 0. + */ +#define GDMA_OUT_DSCR_BF1_CH0_REG (DR_REG_GDMA_BASE + 0xf8) +/** GDMA_OUTLINK_DSCR_BF1_CH0 : RO; bitpos: [31:0]; default: 0; + * The address of the second-to-last inlink descriptor x-2. + */ +#define GDMA_OUTLINK_DSCR_BF1_CH0 0xFFFFFFFFU +#define GDMA_OUTLINK_DSCR_BF1_CH0_M (GDMA_OUTLINK_DSCR_BF1_CH0_V << GDMA_OUTLINK_DSCR_BF1_CH0_S) +#define GDMA_OUTLINK_DSCR_BF1_CH0_V 0xFFFFFFFFU +#define GDMA_OUTLINK_DSCR_BF1_CH0_S 0 + +/** GDMA_OUT_PRI_CH0_REG register + * Priority register of Tx channel 0. + */ +#define GDMA_OUT_PRI_CH0_REG (DR_REG_GDMA_BASE + 0xfc) +/** GDMA_TX_PRI_CH0 : R/W; bitpos: [3:0]; default: 0; + * The priority of Tx channel 0. The larger of the value the higher of the priority. + */ +#define GDMA_TX_PRI_CH0 0x0000000FU +#define GDMA_TX_PRI_CH0_M (GDMA_TX_PRI_CH0_V << GDMA_TX_PRI_CH0_S) +#define GDMA_TX_PRI_CH0_V 0x0000000FU +#define GDMA_TX_PRI_CH0_S 0 + +/** GDMA_OUT_PERI_SEL_CH0_REG register + * Peripheral selection of Tx channel 0. + */ +#define GDMA_OUT_PERI_SEL_CH0_REG (DR_REG_GDMA_BASE + 0x100) +/** GDMA_PERI_OUT_SEL_CH0 : R/W; bitpos: [5:0]; default: 63; + * This register is used to select peripheral for Tx channel 0. 0:SPI2. 1: Dummy. 2: + * UHCI0. 3: I2S0. 4: Dummy. 5: Dummy. 6: AES. 7: SHA. 8: ADC_DAC. 9: Parallel_IO. + * 10~15: Dummy + */ +#define GDMA_PERI_OUT_SEL_CH0 0x0000003FU +#define GDMA_PERI_OUT_SEL_CH0_M (GDMA_PERI_OUT_SEL_CH0_V << GDMA_PERI_OUT_SEL_CH0_S) +#define GDMA_PERI_OUT_SEL_CH0_V 0x0000003FU +#define GDMA_PERI_OUT_SEL_CH0_S 0 + +/** GDMA_IN_CONF0_CH1_REG register + * Configure 0 register of Rx channel 1. + */ +#define GDMA_IN_CONF0_CH1_REG (DR_REG_GDMA_BASE + 0x130) +/** GDMA_IN_RST_CH1 : R/W; bitpos: [0]; default: 0; + * This bit is used to reset DMA channel 1 Rx FSM and Rx FIFO pointer. + */ +#define GDMA_IN_RST_CH1 (BIT(0)) +#define GDMA_IN_RST_CH1_M (GDMA_IN_RST_CH1_V << GDMA_IN_RST_CH1_S) +#define GDMA_IN_RST_CH1_V 0x00000001U +#define GDMA_IN_RST_CH1_S 0 +/** GDMA_IN_LOOP_TEST_CH1 : R/W; bitpos: [1]; default: 0; + * reserved + */ +#define GDMA_IN_LOOP_TEST_CH1 (BIT(1)) +#define GDMA_IN_LOOP_TEST_CH1_M (GDMA_IN_LOOP_TEST_CH1_V << GDMA_IN_LOOP_TEST_CH1_S) +#define GDMA_IN_LOOP_TEST_CH1_V 0x00000001U +#define GDMA_IN_LOOP_TEST_CH1_S 1 +/** GDMA_INDSCR_BURST_EN_CH1 : R/W; bitpos: [2]; default: 0; + * Set this bit to 1 to enable INCR burst transfer for Rx channel 1 reading link + * descriptor when accessing internal SRAM. + */ +#define GDMA_INDSCR_BURST_EN_CH1 (BIT(2)) +#define GDMA_INDSCR_BURST_EN_CH1_M (GDMA_INDSCR_BURST_EN_CH1_V << GDMA_INDSCR_BURST_EN_CH1_S) +#define GDMA_INDSCR_BURST_EN_CH1_V 0x00000001U +#define GDMA_INDSCR_BURST_EN_CH1_S 2 +/** GDMA_IN_DATA_BURST_EN_CH1 : R/W; bitpos: [3]; default: 0; + * Set this bit to 1 to enable INCR burst transfer for Rx channel 1 receiving data + * when accessing internal SRAM. + */ +#define GDMA_IN_DATA_BURST_EN_CH1 (BIT(3)) +#define GDMA_IN_DATA_BURST_EN_CH1_M (GDMA_IN_DATA_BURST_EN_CH1_V << GDMA_IN_DATA_BURST_EN_CH1_S) +#define GDMA_IN_DATA_BURST_EN_CH1_V 0x00000001U +#define GDMA_IN_DATA_BURST_EN_CH1_S 3 +/** GDMA_MEM_TRANS_EN_CH1 : R/W; bitpos: [4]; default: 0; + * Set this bit 1 to enable automatic transmitting data from memory to memory via DMA. + */ +#define GDMA_MEM_TRANS_EN_CH1 (BIT(4)) +#define GDMA_MEM_TRANS_EN_CH1_M (GDMA_MEM_TRANS_EN_CH1_V << GDMA_MEM_TRANS_EN_CH1_S) +#define GDMA_MEM_TRANS_EN_CH1_V 0x00000001U +#define GDMA_MEM_TRANS_EN_CH1_S 4 +/** GDMA_IN_ETM_EN_CH1 : R/W; bitpos: [5]; default: 0; + * Set this bit to 1 to enable etm control mode, GDMA Rx channel 1 is triggered by etm + * task. + */ +#define GDMA_IN_ETM_EN_CH1 (BIT(5)) +#define GDMA_IN_ETM_EN_CH1_M (GDMA_IN_ETM_EN_CH1_V << GDMA_IN_ETM_EN_CH1_S) +#define GDMA_IN_ETM_EN_CH1_V 0x00000001U +#define GDMA_IN_ETM_EN_CH1_S 5 + +/** GDMA_IN_CONF1_CH1_REG register + * Configure 1 register of Rx channel 1. + */ +#define GDMA_IN_CONF1_CH1_REG (DR_REG_GDMA_BASE + 0x134) +/** GDMA_IN_CHECK_OWNER_CH1 : R/W; bitpos: [12]; default: 0; + * Set this bit to enable checking the owner attribute of the link descriptor. + */ +#define GDMA_IN_CHECK_OWNER_CH1 (BIT(12)) +#define GDMA_IN_CHECK_OWNER_CH1_M (GDMA_IN_CHECK_OWNER_CH1_V << GDMA_IN_CHECK_OWNER_CH1_S) +#define GDMA_IN_CHECK_OWNER_CH1_V 0x00000001U +#define GDMA_IN_CHECK_OWNER_CH1_S 12 + +/** GDMA_INFIFO_STATUS_CH1_REG register + * Receive FIFO status of Rx channel 1. + */ +#define GDMA_INFIFO_STATUS_CH1_REG (DR_REG_GDMA_BASE + 0x138) +/** GDMA_INFIFO_FULL_CH1 : RO; bitpos: [0]; default: 1; + * L1 Rx FIFO full signal for Rx channel 1. + */ +#define GDMA_INFIFO_FULL_CH1 (BIT(0)) +#define GDMA_INFIFO_FULL_CH1_M (GDMA_INFIFO_FULL_CH1_V << GDMA_INFIFO_FULL_CH1_S) +#define GDMA_INFIFO_FULL_CH1_V 0x00000001U +#define GDMA_INFIFO_FULL_CH1_S 0 +/** GDMA_INFIFO_EMPTY_CH1 : RO; bitpos: [1]; default: 1; + * L1 Rx FIFO empty signal for Rx channel 1. + */ +#define GDMA_INFIFO_EMPTY_CH1 (BIT(1)) +#define GDMA_INFIFO_EMPTY_CH1_M (GDMA_INFIFO_EMPTY_CH1_V << GDMA_INFIFO_EMPTY_CH1_S) +#define GDMA_INFIFO_EMPTY_CH1_V 0x00000001U +#define GDMA_INFIFO_EMPTY_CH1_S 1 +/** GDMA_INFIFO_CNT_CH1 : RO; bitpos: [7:2]; default: 0; + * The register stores the byte number of the data in L1 Rx FIFO for Rx channel 1. + */ +#define GDMA_INFIFO_CNT_CH1 0x0000003FU +#define GDMA_INFIFO_CNT_CH1_M (GDMA_INFIFO_CNT_CH1_V << GDMA_INFIFO_CNT_CH1_S) +#define GDMA_INFIFO_CNT_CH1_V 0x0000003FU +#define GDMA_INFIFO_CNT_CH1_S 2 +/** GDMA_IN_REMAIN_UNDER_1B_CH1 : RO; bitpos: [23]; default: 1; + * reserved + */ +#define GDMA_IN_REMAIN_UNDER_1B_CH1 (BIT(23)) +#define GDMA_IN_REMAIN_UNDER_1B_CH1_M (GDMA_IN_REMAIN_UNDER_1B_CH1_V << GDMA_IN_REMAIN_UNDER_1B_CH1_S) +#define GDMA_IN_REMAIN_UNDER_1B_CH1_V 0x00000001U +#define GDMA_IN_REMAIN_UNDER_1B_CH1_S 23 +/** GDMA_IN_REMAIN_UNDER_2B_CH1 : RO; bitpos: [24]; default: 1; + * reserved + */ +#define GDMA_IN_REMAIN_UNDER_2B_CH1 (BIT(24)) +#define GDMA_IN_REMAIN_UNDER_2B_CH1_M (GDMA_IN_REMAIN_UNDER_2B_CH1_V << GDMA_IN_REMAIN_UNDER_2B_CH1_S) +#define GDMA_IN_REMAIN_UNDER_2B_CH1_V 0x00000001U +#define GDMA_IN_REMAIN_UNDER_2B_CH1_S 24 +/** GDMA_IN_REMAIN_UNDER_3B_CH1 : RO; bitpos: [25]; default: 1; + * reserved + */ +#define GDMA_IN_REMAIN_UNDER_3B_CH1 (BIT(25)) +#define GDMA_IN_REMAIN_UNDER_3B_CH1_M (GDMA_IN_REMAIN_UNDER_3B_CH1_V << GDMA_IN_REMAIN_UNDER_3B_CH1_S) +#define GDMA_IN_REMAIN_UNDER_3B_CH1_V 0x00000001U +#define GDMA_IN_REMAIN_UNDER_3B_CH1_S 25 +/** GDMA_IN_REMAIN_UNDER_4B_CH1 : RO; bitpos: [26]; default: 1; + * reserved + */ +#define GDMA_IN_REMAIN_UNDER_4B_CH1 (BIT(26)) +#define GDMA_IN_REMAIN_UNDER_4B_CH1_M (GDMA_IN_REMAIN_UNDER_4B_CH1_V << GDMA_IN_REMAIN_UNDER_4B_CH1_S) +#define GDMA_IN_REMAIN_UNDER_4B_CH1_V 0x00000001U +#define GDMA_IN_REMAIN_UNDER_4B_CH1_S 26 +/** GDMA_IN_BUF_HUNGRY_CH1 : RO; bitpos: [27]; default: 0; + * reserved + */ +#define GDMA_IN_BUF_HUNGRY_CH1 (BIT(27)) +#define GDMA_IN_BUF_HUNGRY_CH1_M (GDMA_IN_BUF_HUNGRY_CH1_V << GDMA_IN_BUF_HUNGRY_CH1_S) +#define GDMA_IN_BUF_HUNGRY_CH1_V 0x00000001U +#define GDMA_IN_BUF_HUNGRY_CH1_S 27 + +/** GDMA_IN_POP_CH1_REG register + * Pop control register of Rx channel 1. + */ +#define GDMA_IN_POP_CH1_REG (DR_REG_GDMA_BASE + 0x13c) +/** GDMA_INFIFO_RDATA_CH1 : RO; bitpos: [11:0]; default: 2048; + * This register stores the data popping from GDMA FIFO. + */ +#define GDMA_INFIFO_RDATA_CH1 0x00000FFFU +#define GDMA_INFIFO_RDATA_CH1_M (GDMA_INFIFO_RDATA_CH1_V << GDMA_INFIFO_RDATA_CH1_S) +#define GDMA_INFIFO_RDATA_CH1_V 0x00000FFFU +#define GDMA_INFIFO_RDATA_CH1_S 0 +/** GDMA_INFIFO_POP_CH1 : WT; bitpos: [12]; default: 0; + * Set this bit to pop data from GDMA FIFO. + */ +#define GDMA_INFIFO_POP_CH1 (BIT(12)) +#define GDMA_INFIFO_POP_CH1_M (GDMA_INFIFO_POP_CH1_V << GDMA_INFIFO_POP_CH1_S) +#define GDMA_INFIFO_POP_CH1_V 0x00000001U +#define GDMA_INFIFO_POP_CH1_S 12 + +/** GDMA_IN_LINK_CH1_REG register + * Link descriptor configure and control register of Rx channel 1. + */ +#define GDMA_IN_LINK_CH1_REG (DR_REG_GDMA_BASE + 0x140) +/** GDMA_INLINK_ADDR_CH1 : R/W; bitpos: [19:0]; default: 0; + * This register stores the 20 least significant bits of the first inlink descriptor's + * address. + */ +#define GDMA_INLINK_ADDR_CH1 0x000FFFFFU +#define GDMA_INLINK_ADDR_CH1_M (GDMA_INLINK_ADDR_CH1_V << GDMA_INLINK_ADDR_CH1_S) +#define GDMA_INLINK_ADDR_CH1_V 0x000FFFFFU +#define GDMA_INLINK_ADDR_CH1_S 0 +/** GDMA_INLINK_AUTO_RET_CH1 : R/W; bitpos: [20]; default: 1; + * Set this bit to return to current inlink descriptor's address when there are some + * errors in current receiving data. + */ +#define GDMA_INLINK_AUTO_RET_CH1 (BIT(20)) +#define GDMA_INLINK_AUTO_RET_CH1_M (GDMA_INLINK_AUTO_RET_CH1_V << GDMA_INLINK_AUTO_RET_CH1_S) +#define GDMA_INLINK_AUTO_RET_CH1_V 0x00000001U +#define GDMA_INLINK_AUTO_RET_CH1_S 20 +/** GDMA_INLINK_STOP_CH1 : WT; bitpos: [21]; default: 0; + * Set this bit to stop dealing with the inlink descriptors. + */ +#define GDMA_INLINK_STOP_CH1 (BIT(21)) +#define GDMA_INLINK_STOP_CH1_M (GDMA_INLINK_STOP_CH1_V << GDMA_INLINK_STOP_CH1_S) +#define GDMA_INLINK_STOP_CH1_V 0x00000001U +#define GDMA_INLINK_STOP_CH1_S 21 +/** GDMA_INLINK_START_CH1 : WT; bitpos: [22]; default: 0; + * Set this bit to start dealing with the inlink descriptors. + */ +#define GDMA_INLINK_START_CH1 (BIT(22)) +#define GDMA_INLINK_START_CH1_M (GDMA_INLINK_START_CH1_V << GDMA_INLINK_START_CH1_S) +#define GDMA_INLINK_START_CH1_V 0x00000001U +#define GDMA_INLINK_START_CH1_S 22 +/** GDMA_INLINK_RESTART_CH1 : WT; bitpos: [23]; default: 0; + * Set this bit to mount a new inlink descriptor. + */ +#define GDMA_INLINK_RESTART_CH1 (BIT(23)) +#define GDMA_INLINK_RESTART_CH1_M (GDMA_INLINK_RESTART_CH1_V << GDMA_INLINK_RESTART_CH1_S) +#define GDMA_INLINK_RESTART_CH1_V 0x00000001U +#define GDMA_INLINK_RESTART_CH1_S 23 +/** GDMA_INLINK_PARK_CH1 : RO; bitpos: [24]; default: 1; + * 1: the inlink descriptor's FSM is in idle state. 0: the inlink descriptor's FSM is + * working. + */ +#define GDMA_INLINK_PARK_CH1 (BIT(24)) +#define GDMA_INLINK_PARK_CH1_M (GDMA_INLINK_PARK_CH1_V << GDMA_INLINK_PARK_CH1_S) +#define GDMA_INLINK_PARK_CH1_V 0x00000001U +#define GDMA_INLINK_PARK_CH1_S 24 + +/** GDMA_IN_STATE_CH1_REG register + * Receive status of Rx channel 1. + */ +#define GDMA_IN_STATE_CH1_REG (DR_REG_GDMA_BASE + 0x144) +/** GDMA_INLINK_DSCR_ADDR_CH1 : RO; bitpos: [17:0]; default: 0; + * This register stores the current inlink descriptor's address. + */ +#define GDMA_INLINK_DSCR_ADDR_CH1 0x0003FFFFU +#define GDMA_INLINK_DSCR_ADDR_CH1_M (GDMA_INLINK_DSCR_ADDR_CH1_V << GDMA_INLINK_DSCR_ADDR_CH1_S) +#define GDMA_INLINK_DSCR_ADDR_CH1_V 0x0003FFFFU +#define GDMA_INLINK_DSCR_ADDR_CH1_S 0 +/** GDMA_IN_DSCR_STATE_CH1 : RO; bitpos: [19:18]; default: 0; + * reserved + */ +#define GDMA_IN_DSCR_STATE_CH1 0x00000003U +#define GDMA_IN_DSCR_STATE_CH1_M (GDMA_IN_DSCR_STATE_CH1_V << GDMA_IN_DSCR_STATE_CH1_S) +#define GDMA_IN_DSCR_STATE_CH1_V 0x00000003U +#define GDMA_IN_DSCR_STATE_CH1_S 18 +/** GDMA_IN_STATE_CH1 : RO; bitpos: [22:20]; default: 0; + * reserved + */ +#define GDMA_IN_STATE_CH1 0x00000007U +#define GDMA_IN_STATE_CH1_M (GDMA_IN_STATE_CH1_V << GDMA_IN_STATE_CH1_S) +#define GDMA_IN_STATE_CH1_V 0x00000007U +#define GDMA_IN_STATE_CH1_S 20 + +/** GDMA_IN_SUC_EOF_DES_ADDR_CH1_REG register + * Inlink descriptor address when EOF occurs of Rx channel 1. + */ +#define GDMA_IN_SUC_EOF_DES_ADDR_CH1_REG (DR_REG_GDMA_BASE + 0x148) +/** GDMA_IN_SUC_EOF_DES_ADDR_CH1 : RO; bitpos: [31:0]; default: 0; + * This register stores the address of the inlink descriptor when the EOF bit in this + * descriptor is 1. + */ +#define GDMA_IN_SUC_EOF_DES_ADDR_CH1 0xFFFFFFFFU +#define GDMA_IN_SUC_EOF_DES_ADDR_CH1_M (GDMA_IN_SUC_EOF_DES_ADDR_CH1_V << GDMA_IN_SUC_EOF_DES_ADDR_CH1_S) +#define GDMA_IN_SUC_EOF_DES_ADDR_CH1_V 0xFFFFFFFFU +#define GDMA_IN_SUC_EOF_DES_ADDR_CH1_S 0 + +/** GDMA_IN_ERR_EOF_DES_ADDR_CH1_REG register + * Inlink descriptor address when errors occur of Rx channel 1. + */ +#define GDMA_IN_ERR_EOF_DES_ADDR_CH1_REG (DR_REG_GDMA_BASE + 0x14c) +/** GDMA_IN_ERR_EOF_DES_ADDR_CH1 : RO; bitpos: [31:0]; default: 0; + * This register stores the address of the inlink descriptor when there are some + * errors in current receiving data. Only used when peripheral is UHCI0. + */ +#define GDMA_IN_ERR_EOF_DES_ADDR_CH1 0xFFFFFFFFU +#define GDMA_IN_ERR_EOF_DES_ADDR_CH1_M (GDMA_IN_ERR_EOF_DES_ADDR_CH1_V << GDMA_IN_ERR_EOF_DES_ADDR_CH1_S) +#define GDMA_IN_ERR_EOF_DES_ADDR_CH1_V 0xFFFFFFFFU +#define GDMA_IN_ERR_EOF_DES_ADDR_CH1_S 0 + +/** GDMA_IN_DSCR_CH1_REG register + * Current inlink descriptor address of Rx channel 1. + */ +#define GDMA_IN_DSCR_CH1_REG (DR_REG_GDMA_BASE + 0x150) +/** GDMA_INLINK_DSCR_CH1 : RO; bitpos: [31:0]; default: 0; + * The address of the current inlink descriptor x. + */ +#define GDMA_INLINK_DSCR_CH1 0xFFFFFFFFU +#define GDMA_INLINK_DSCR_CH1_M (GDMA_INLINK_DSCR_CH1_V << GDMA_INLINK_DSCR_CH1_S) +#define GDMA_INLINK_DSCR_CH1_V 0xFFFFFFFFU +#define GDMA_INLINK_DSCR_CH1_S 0 + +/** GDMA_IN_DSCR_BF0_CH1_REG register + * The last inlink descriptor address of Rx channel 1. + */ +#define GDMA_IN_DSCR_BF0_CH1_REG (DR_REG_GDMA_BASE + 0x154) +/** GDMA_INLINK_DSCR_BF0_CH1 : RO; bitpos: [31:0]; default: 0; + * The address of the last inlink descriptor x-1. + */ +#define GDMA_INLINK_DSCR_BF0_CH1 0xFFFFFFFFU +#define GDMA_INLINK_DSCR_BF0_CH1_M (GDMA_INLINK_DSCR_BF0_CH1_V << GDMA_INLINK_DSCR_BF0_CH1_S) +#define GDMA_INLINK_DSCR_BF0_CH1_V 0xFFFFFFFFU +#define GDMA_INLINK_DSCR_BF0_CH1_S 0 + +/** GDMA_IN_DSCR_BF1_CH1_REG register + * The second-to-last inlink descriptor address of Rx channel 1. + */ +#define GDMA_IN_DSCR_BF1_CH1_REG (DR_REG_GDMA_BASE + 0x158) +/** GDMA_INLINK_DSCR_BF1_CH1 : RO; bitpos: [31:0]; default: 0; + * The address of the second-to-last inlink descriptor x-2. + */ +#define GDMA_INLINK_DSCR_BF1_CH1 0xFFFFFFFFU +#define GDMA_INLINK_DSCR_BF1_CH1_M (GDMA_INLINK_DSCR_BF1_CH1_V << GDMA_INLINK_DSCR_BF1_CH1_S) +#define GDMA_INLINK_DSCR_BF1_CH1_V 0xFFFFFFFFU +#define GDMA_INLINK_DSCR_BF1_CH1_S 0 + +/** GDMA_IN_PRI_CH1_REG register + * Priority register of Rx channel 1. + */ +#define GDMA_IN_PRI_CH1_REG (DR_REG_GDMA_BASE + 0x15c) +/** GDMA_RX_PRI_CH1 : R/W; bitpos: [3:0]; default: 0; + * The priority of Rx channel 1. The larger of the value the higher of the priority. + */ +#define GDMA_RX_PRI_CH1 0x0000000FU +#define GDMA_RX_PRI_CH1_M (GDMA_RX_PRI_CH1_V << GDMA_RX_PRI_CH1_S) +#define GDMA_RX_PRI_CH1_V 0x0000000FU +#define GDMA_RX_PRI_CH1_S 0 + +/** GDMA_IN_PERI_SEL_CH1_REG register + * Peripheral selection of Rx channel 1. + */ +#define GDMA_IN_PERI_SEL_CH1_REG (DR_REG_GDMA_BASE + 0x160) +/** GDMA_PERI_IN_SEL_CH1 : R/W; bitpos: [5:0]; default: 63; + * This register is used to select peripheral for Rx channel 1. 0:SPI2. 1: Dummy. 2: + * UHCI0. 3: I2S0. 4: Dummy. 5: Dummy. 6: AES. 7: SHA. 8: ADC_DAC. 9: Parallel_IO. + * 10~15: Dummy + */ +#define GDMA_PERI_IN_SEL_CH1 0x0000003FU +#define GDMA_PERI_IN_SEL_CH1_M (GDMA_PERI_IN_SEL_CH1_V << GDMA_PERI_IN_SEL_CH1_S) +#define GDMA_PERI_IN_SEL_CH1_V 0x0000003FU +#define GDMA_PERI_IN_SEL_CH1_S 0 + +/** GDMA_OUT_CONF0_CH1_REG register + * Configure 0 register of Tx channel 1. + */ +#define GDMA_OUT_CONF0_CH1_REG (DR_REG_GDMA_BASE + 0x190) +/** GDMA_OUT_RST_CH1 : R/W; bitpos: [0]; default: 0; + * This bit is used to reset DMA channel 1 Tx FSM and Tx FIFO pointer. + */ +#define GDMA_OUT_RST_CH1 (BIT(0)) +#define GDMA_OUT_RST_CH1_M (GDMA_OUT_RST_CH1_V << GDMA_OUT_RST_CH1_S) +#define GDMA_OUT_RST_CH1_V 0x00000001U +#define GDMA_OUT_RST_CH1_S 0 +/** GDMA_OUT_LOOP_TEST_CH1 : R/W; bitpos: [1]; default: 0; + * reserved + */ +#define GDMA_OUT_LOOP_TEST_CH1 (BIT(1)) +#define GDMA_OUT_LOOP_TEST_CH1_M (GDMA_OUT_LOOP_TEST_CH1_V << GDMA_OUT_LOOP_TEST_CH1_S) +#define GDMA_OUT_LOOP_TEST_CH1_V 0x00000001U +#define GDMA_OUT_LOOP_TEST_CH1_S 1 +/** GDMA_OUT_AUTO_WRBACK_CH1 : R/W; bitpos: [2]; default: 0; + * Set this bit to enable automatic outlink-writeback when all the data in tx buffer + * has been transmitted. + */ +#define GDMA_OUT_AUTO_WRBACK_CH1 (BIT(2)) +#define GDMA_OUT_AUTO_WRBACK_CH1_M (GDMA_OUT_AUTO_WRBACK_CH1_V << GDMA_OUT_AUTO_WRBACK_CH1_S) +#define GDMA_OUT_AUTO_WRBACK_CH1_V 0x00000001U +#define GDMA_OUT_AUTO_WRBACK_CH1_S 2 +/** GDMA_OUT_EOF_MODE_CH1 : R/W; bitpos: [3]; default: 1; + * EOF flag generation mode when transmitting data. 1: EOF flag for Tx channel 1 is + * generated when data need to transmit has been popped from FIFO in DMA + */ +#define GDMA_OUT_EOF_MODE_CH1 (BIT(3)) +#define GDMA_OUT_EOF_MODE_CH1_M (GDMA_OUT_EOF_MODE_CH1_V << GDMA_OUT_EOF_MODE_CH1_S) +#define GDMA_OUT_EOF_MODE_CH1_V 0x00000001U +#define GDMA_OUT_EOF_MODE_CH1_S 3 +/** GDMA_OUTDSCR_BURST_EN_CH1 : R/W; bitpos: [4]; default: 0; + * Set this bit to 1 to enable INCR burst transfer for Tx channel 1 reading link + * descriptor when accessing internal SRAM. + */ +#define GDMA_OUTDSCR_BURST_EN_CH1 (BIT(4)) +#define GDMA_OUTDSCR_BURST_EN_CH1_M (GDMA_OUTDSCR_BURST_EN_CH1_V << GDMA_OUTDSCR_BURST_EN_CH1_S) +#define GDMA_OUTDSCR_BURST_EN_CH1_V 0x00000001U +#define GDMA_OUTDSCR_BURST_EN_CH1_S 4 +/** GDMA_OUT_DATA_BURST_EN_CH1 : R/W; bitpos: [5]; default: 0; + * Set this bit to 1 to enable INCR burst transfer for Tx channel 1 transmitting data + * when accessing internal SRAM. + */ +#define GDMA_OUT_DATA_BURST_EN_CH1 (BIT(5)) +#define GDMA_OUT_DATA_BURST_EN_CH1_M (GDMA_OUT_DATA_BURST_EN_CH1_V << GDMA_OUT_DATA_BURST_EN_CH1_S) +#define GDMA_OUT_DATA_BURST_EN_CH1_V 0x00000001U +#define GDMA_OUT_DATA_BURST_EN_CH1_S 5 +/** GDMA_OUT_ETM_EN_CH1 : R/W; bitpos: [6]; default: 0; + * Set this bit to 1 to enable etm control mode, GDMA Tx channel 1 is triggered by etm + * task. + */ +#define GDMA_OUT_ETM_EN_CH1 (BIT(6)) +#define GDMA_OUT_ETM_EN_CH1_M (GDMA_OUT_ETM_EN_CH1_V << GDMA_OUT_ETM_EN_CH1_S) +#define GDMA_OUT_ETM_EN_CH1_V 0x00000001U +#define GDMA_OUT_ETM_EN_CH1_S 6 + +/** GDMA_OUT_CONF1_CH1_REG register + * Configure 1 register of Tx channel 1. + */ +#define GDMA_OUT_CONF1_CH1_REG (DR_REG_GDMA_BASE + 0x194) +/** GDMA_OUT_CHECK_OWNER_CH1 : R/W; bitpos: [12]; default: 0; + * Set this bit to enable checking the owner attribute of the link descriptor. + */ +#define GDMA_OUT_CHECK_OWNER_CH1 (BIT(12)) +#define GDMA_OUT_CHECK_OWNER_CH1_M (GDMA_OUT_CHECK_OWNER_CH1_V << GDMA_OUT_CHECK_OWNER_CH1_S) +#define GDMA_OUT_CHECK_OWNER_CH1_V 0x00000001U +#define GDMA_OUT_CHECK_OWNER_CH1_S 12 + +/** GDMA_OUTFIFO_STATUS_CH1_REG register + * Transmit FIFO status of Tx channel 1. + */ +#define GDMA_OUTFIFO_STATUS_CH1_REG (DR_REG_GDMA_BASE + 0x198) +/** GDMA_OUTFIFO_FULL_CH1 : RO; bitpos: [0]; default: 0; + * L1 Tx FIFO full signal for Tx channel 1. + */ +#define GDMA_OUTFIFO_FULL_CH1 (BIT(0)) +#define GDMA_OUTFIFO_FULL_CH1_M (GDMA_OUTFIFO_FULL_CH1_V << GDMA_OUTFIFO_FULL_CH1_S) +#define GDMA_OUTFIFO_FULL_CH1_V 0x00000001U +#define GDMA_OUTFIFO_FULL_CH1_S 0 +/** GDMA_OUTFIFO_EMPTY_CH1 : RO; bitpos: [1]; default: 1; + * L1 Tx FIFO empty signal for Tx channel 1. + */ +#define GDMA_OUTFIFO_EMPTY_CH1 (BIT(1)) +#define GDMA_OUTFIFO_EMPTY_CH1_M (GDMA_OUTFIFO_EMPTY_CH1_V << GDMA_OUTFIFO_EMPTY_CH1_S) +#define GDMA_OUTFIFO_EMPTY_CH1_V 0x00000001U +#define GDMA_OUTFIFO_EMPTY_CH1_S 1 +/** GDMA_OUTFIFO_CNT_CH1 : RO; bitpos: [7:2]; default: 0; + * The register stores the byte number of the data in L1 Tx FIFO for Tx channel 1. + */ +#define GDMA_OUTFIFO_CNT_CH1 0x0000003FU +#define GDMA_OUTFIFO_CNT_CH1_M (GDMA_OUTFIFO_CNT_CH1_V << GDMA_OUTFIFO_CNT_CH1_S) +#define GDMA_OUTFIFO_CNT_CH1_V 0x0000003FU +#define GDMA_OUTFIFO_CNT_CH1_S 2 +/** GDMA_OUT_REMAIN_UNDER_1B_CH1 : RO; bitpos: [23]; default: 1; + * reserved + */ +#define GDMA_OUT_REMAIN_UNDER_1B_CH1 (BIT(23)) +#define GDMA_OUT_REMAIN_UNDER_1B_CH1_M (GDMA_OUT_REMAIN_UNDER_1B_CH1_V << GDMA_OUT_REMAIN_UNDER_1B_CH1_S) +#define GDMA_OUT_REMAIN_UNDER_1B_CH1_V 0x00000001U +#define GDMA_OUT_REMAIN_UNDER_1B_CH1_S 23 +/** GDMA_OUT_REMAIN_UNDER_2B_CH1 : RO; bitpos: [24]; default: 1; + * reserved + */ +#define GDMA_OUT_REMAIN_UNDER_2B_CH1 (BIT(24)) +#define GDMA_OUT_REMAIN_UNDER_2B_CH1_M (GDMA_OUT_REMAIN_UNDER_2B_CH1_V << GDMA_OUT_REMAIN_UNDER_2B_CH1_S) +#define GDMA_OUT_REMAIN_UNDER_2B_CH1_V 0x00000001U +#define GDMA_OUT_REMAIN_UNDER_2B_CH1_S 24 +/** GDMA_OUT_REMAIN_UNDER_3B_CH1 : RO; bitpos: [25]; default: 1; + * reserved + */ +#define GDMA_OUT_REMAIN_UNDER_3B_CH1 (BIT(25)) +#define GDMA_OUT_REMAIN_UNDER_3B_CH1_M (GDMA_OUT_REMAIN_UNDER_3B_CH1_V << GDMA_OUT_REMAIN_UNDER_3B_CH1_S) +#define GDMA_OUT_REMAIN_UNDER_3B_CH1_V 0x00000001U +#define GDMA_OUT_REMAIN_UNDER_3B_CH1_S 25 +/** GDMA_OUT_REMAIN_UNDER_4B_CH1 : RO; bitpos: [26]; default: 1; + * reserved + */ +#define GDMA_OUT_REMAIN_UNDER_4B_CH1 (BIT(26)) +#define GDMA_OUT_REMAIN_UNDER_4B_CH1_M (GDMA_OUT_REMAIN_UNDER_4B_CH1_V << GDMA_OUT_REMAIN_UNDER_4B_CH1_S) +#define GDMA_OUT_REMAIN_UNDER_4B_CH1_V 0x00000001U +#define GDMA_OUT_REMAIN_UNDER_4B_CH1_S 26 + +/** GDMA_OUT_PUSH_CH1_REG register + * Push control register of Rx channel 1. + */ +#define GDMA_OUT_PUSH_CH1_REG (DR_REG_GDMA_BASE + 0x19c) +/** GDMA_OUTFIFO_WDATA_CH1 : R/W; bitpos: [8:0]; default: 0; + * This register stores the data that need to be pushed into GDMA FIFO. + */ +#define GDMA_OUTFIFO_WDATA_CH1 0x000001FFU +#define GDMA_OUTFIFO_WDATA_CH1_M (GDMA_OUTFIFO_WDATA_CH1_V << GDMA_OUTFIFO_WDATA_CH1_S) +#define GDMA_OUTFIFO_WDATA_CH1_V 0x000001FFU +#define GDMA_OUTFIFO_WDATA_CH1_S 0 +/** GDMA_OUTFIFO_PUSH_CH1 : WT; bitpos: [9]; default: 0; + * Set this bit to push data into GDMA FIFO. + */ +#define GDMA_OUTFIFO_PUSH_CH1 (BIT(9)) +#define GDMA_OUTFIFO_PUSH_CH1_M (GDMA_OUTFIFO_PUSH_CH1_V << GDMA_OUTFIFO_PUSH_CH1_S) +#define GDMA_OUTFIFO_PUSH_CH1_V 0x00000001U +#define GDMA_OUTFIFO_PUSH_CH1_S 9 + +/** GDMA_OUT_LINK_CH1_REG register + * Link descriptor configure and control register of Tx channel 1. + */ +#define GDMA_OUT_LINK_CH1_REG (DR_REG_GDMA_BASE + 0x1a0) +/** GDMA_OUTLINK_ADDR_CH1 : R/W; bitpos: [19:0]; default: 0; + * This register stores the 20 least significant bits of the first outlink + * descriptor's address. + */ +#define GDMA_OUTLINK_ADDR_CH1 0x000FFFFFU +#define GDMA_OUTLINK_ADDR_CH1_M (GDMA_OUTLINK_ADDR_CH1_V << GDMA_OUTLINK_ADDR_CH1_S) +#define GDMA_OUTLINK_ADDR_CH1_V 0x000FFFFFU +#define GDMA_OUTLINK_ADDR_CH1_S 0 +/** GDMA_OUTLINK_STOP_CH1 : WT; bitpos: [20]; default: 0; + * Set this bit to stop dealing with the outlink descriptors. + */ +#define GDMA_OUTLINK_STOP_CH1 (BIT(20)) +#define GDMA_OUTLINK_STOP_CH1_M (GDMA_OUTLINK_STOP_CH1_V << GDMA_OUTLINK_STOP_CH1_S) +#define GDMA_OUTLINK_STOP_CH1_V 0x00000001U +#define GDMA_OUTLINK_STOP_CH1_S 20 +/** GDMA_OUTLINK_START_CH1 : WT; bitpos: [21]; default: 0; + * Set this bit to start dealing with the outlink descriptors. + */ +#define GDMA_OUTLINK_START_CH1 (BIT(21)) +#define GDMA_OUTLINK_START_CH1_M (GDMA_OUTLINK_START_CH1_V << GDMA_OUTLINK_START_CH1_S) +#define GDMA_OUTLINK_START_CH1_V 0x00000001U +#define GDMA_OUTLINK_START_CH1_S 21 +/** GDMA_OUTLINK_RESTART_CH1 : WT; bitpos: [22]; default: 0; + * Set this bit to restart a new outlink from the last address. + */ +#define GDMA_OUTLINK_RESTART_CH1 (BIT(22)) +#define GDMA_OUTLINK_RESTART_CH1_M (GDMA_OUTLINK_RESTART_CH1_V << GDMA_OUTLINK_RESTART_CH1_S) +#define GDMA_OUTLINK_RESTART_CH1_V 0x00000001U +#define GDMA_OUTLINK_RESTART_CH1_S 22 +/** GDMA_OUTLINK_PARK_CH1 : RO; bitpos: [23]; default: 1; + * 1: the outlink descriptor's FSM is in idle state. 0: the outlink descriptor's FSM + * is working. + */ +#define GDMA_OUTLINK_PARK_CH1 (BIT(23)) +#define GDMA_OUTLINK_PARK_CH1_M (GDMA_OUTLINK_PARK_CH1_V << GDMA_OUTLINK_PARK_CH1_S) +#define GDMA_OUTLINK_PARK_CH1_V 0x00000001U +#define GDMA_OUTLINK_PARK_CH1_S 23 + +/** GDMA_OUT_STATE_CH1_REG register + * Transmit status of Tx channel 1. + */ +#define GDMA_OUT_STATE_CH1_REG (DR_REG_GDMA_BASE + 0x1a4) +/** GDMA_OUTLINK_DSCR_ADDR_CH1 : RO; bitpos: [17:0]; default: 0; + * This register stores the current outlink descriptor's address. + */ +#define GDMA_OUTLINK_DSCR_ADDR_CH1 0x0003FFFFU +#define GDMA_OUTLINK_DSCR_ADDR_CH1_M (GDMA_OUTLINK_DSCR_ADDR_CH1_V << GDMA_OUTLINK_DSCR_ADDR_CH1_S) +#define GDMA_OUTLINK_DSCR_ADDR_CH1_V 0x0003FFFFU +#define GDMA_OUTLINK_DSCR_ADDR_CH1_S 0 +/** GDMA_OUT_DSCR_STATE_CH1 : RO; bitpos: [19:18]; default: 0; + * reserved + */ +#define GDMA_OUT_DSCR_STATE_CH1 0x00000003U +#define GDMA_OUT_DSCR_STATE_CH1_M (GDMA_OUT_DSCR_STATE_CH1_V << GDMA_OUT_DSCR_STATE_CH1_S) +#define GDMA_OUT_DSCR_STATE_CH1_V 0x00000003U +#define GDMA_OUT_DSCR_STATE_CH1_S 18 +/** GDMA_OUT_STATE_CH1 : RO; bitpos: [22:20]; default: 0; + * reserved + */ +#define GDMA_OUT_STATE_CH1 0x00000007U +#define GDMA_OUT_STATE_CH1_M (GDMA_OUT_STATE_CH1_V << GDMA_OUT_STATE_CH1_S) +#define GDMA_OUT_STATE_CH1_V 0x00000007U +#define GDMA_OUT_STATE_CH1_S 20 + +/** GDMA_OUT_EOF_DES_ADDR_CH1_REG register + * Outlink descriptor address when EOF occurs of Tx channel 1. + */ +#define GDMA_OUT_EOF_DES_ADDR_CH1_REG (DR_REG_GDMA_BASE + 0x1a8) +/** GDMA_OUT_EOF_DES_ADDR_CH1 : RO; bitpos: [31:0]; default: 0; + * This register stores the address of the outlink descriptor when the EOF bit in this + * descriptor is 1. + */ +#define GDMA_OUT_EOF_DES_ADDR_CH1 0xFFFFFFFFU +#define GDMA_OUT_EOF_DES_ADDR_CH1_M (GDMA_OUT_EOF_DES_ADDR_CH1_V << GDMA_OUT_EOF_DES_ADDR_CH1_S) +#define GDMA_OUT_EOF_DES_ADDR_CH1_V 0xFFFFFFFFU +#define GDMA_OUT_EOF_DES_ADDR_CH1_S 0 + +/** GDMA_OUT_EOF_BFR_DES_ADDR_CH1_REG register + * The last outlink descriptor address when EOF occurs of Tx channel 1. + */ +#define GDMA_OUT_EOF_BFR_DES_ADDR_CH1_REG (DR_REG_GDMA_BASE + 0x1ac) +/** GDMA_OUT_EOF_BFR_DES_ADDR_CH1 : RO; bitpos: [31:0]; default: 0; + * This register stores the address of the outlink descriptor before the last outlink + * descriptor. + */ +#define GDMA_OUT_EOF_BFR_DES_ADDR_CH1 0xFFFFFFFFU +#define GDMA_OUT_EOF_BFR_DES_ADDR_CH1_M (GDMA_OUT_EOF_BFR_DES_ADDR_CH1_V << GDMA_OUT_EOF_BFR_DES_ADDR_CH1_S) +#define GDMA_OUT_EOF_BFR_DES_ADDR_CH1_V 0xFFFFFFFFU +#define GDMA_OUT_EOF_BFR_DES_ADDR_CH1_S 0 + +/** GDMA_OUT_DSCR_CH1_REG register + * Current inlink descriptor address of Tx channel 1. + */ +#define GDMA_OUT_DSCR_CH1_REG (DR_REG_GDMA_BASE + 0x1b0) +/** GDMA_OUTLINK_DSCR_CH1 : RO; bitpos: [31:0]; default: 0; + * The address of the current outlink descriptor y. + */ +#define GDMA_OUTLINK_DSCR_CH1 0xFFFFFFFFU +#define GDMA_OUTLINK_DSCR_CH1_M (GDMA_OUTLINK_DSCR_CH1_V << GDMA_OUTLINK_DSCR_CH1_S) +#define GDMA_OUTLINK_DSCR_CH1_V 0xFFFFFFFFU +#define GDMA_OUTLINK_DSCR_CH1_S 0 + +/** GDMA_OUT_DSCR_BF0_CH1_REG register + * The last inlink descriptor address of Tx channel 1. + */ +#define GDMA_OUT_DSCR_BF0_CH1_REG (DR_REG_GDMA_BASE + 0x1b4) +/** GDMA_OUTLINK_DSCR_BF0_CH1 : RO; bitpos: [31:0]; default: 0; + * The address of the last outlink descriptor y-1. + */ +#define GDMA_OUTLINK_DSCR_BF0_CH1 0xFFFFFFFFU +#define GDMA_OUTLINK_DSCR_BF0_CH1_M (GDMA_OUTLINK_DSCR_BF0_CH1_V << GDMA_OUTLINK_DSCR_BF0_CH1_S) +#define GDMA_OUTLINK_DSCR_BF0_CH1_V 0xFFFFFFFFU +#define GDMA_OUTLINK_DSCR_BF0_CH1_S 0 + +/** GDMA_OUT_DSCR_BF1_CH1_REG register + * The second-to-last inlink descriptor address of Tx channel 1. + */ +#define GDMA_OUT_DSCR_BF1_CH1_REG (DR_REG_GDMA_BASE + 0x1b8) +/** GDMA_OUTLINK_DSCR_BF1_CH1 : RO; bitpos: [31:0]; default: 0; + * The address of the second-to-last inlink descriptor x-2. + */ +#define GDMA_OUTLINK_DSCR_BF1_CH1 0xFFFFFFFFU +#define GDMA_OUTLINK_DSCR_BF1_CH1_M (GDMA_OUTLINK_DSCR_BF1_CH1_V << GDMA_OUTLINK_DSCR_BF1_CH1_S) +#define GDMA_OUTLINK_DSCR_BF1_CH1_V 0xFFFFFFFFU +#define GDMA_OUTLINK_DSCR_BF1_CH1_S 0 + +/** GDMA_OUT_PRI_CH1_REG register + * Priority register of Tx channel 1. + */ +#define GDMA_OUT_PRI_CH1_REG (DR_REG_GDMA_BASE + 0x1bc) +/** GDMA_TX_PRI_CH1 : R/W; bitpos: [3:0]; default: 0; + * The priority of Tx channel 1. The larger of the value the higher of the priority. + */ +#define GDMA_TX_PRI_CH1 0x0000000FU +#define GDMA_TX_PRI_CH1_M (GDMA_TX_PRI_CH1_V << GDMA_TX_PRI_CH1_S) +#define GDMA_TX_PRI_CH1_V 0x0000000FU +#define GDMA_TX_PRI_CH1_S 0 + +/** GDMA_OUT_PERI_SEL_CH1_REG register + * Peripheral selection of Tx channel 1. + */ +#define GDMA_OUT_PERI_SEL_CH1_REG (DR_REG_GDMA_BASE + 0x1c0) +/** GDMA_PERI_OUT_SEL_CH1 : R/W; bitpos: [5:0]; default: 63; + * This register is used to select peripheral for Tx channel 1. 0:SPI2. 1: Dummy. 2: + * UHCI0. 3: I2S0. 4: Dummy. 5: Dummy. 6: AES. 7: SHA. 8: ADC_DAC. 9: Parallel_IO. + * 10~15: Dummy + */ +#define GDMA_PERI_OUT_SEL_CH1 0x0000003FU +#define GDMA_PERI_OUT_SEL_CH1_M (GDMA_PERI_OUT_SEL_CH1_V << GDMA_PERI_OUT_SEL_CH1_S) +#define GDMA_PERI_OUT_SEL_CH1_V 0x0000003FU +#define GDMA_PERI_OUT_SEL_CH1_S 0 + +/** GDMA_IN_CONF0_CH2_REG register + * Configure 0 register of Rx channel 2. + */ +#define GDMA_IN_CONF0_CH2_REG (DR_REG_GDMA_BASE + 0x1f0) +/** GDMA_IN_RST_CH2 : R/W; bitpos: [0]; default: 0; + * This bit is used to reset DMA channel 2 Rx FSM and Rx FIFO pointer. + */ +#define GDMA_IN_RST_CH2 (BIT(0)) +#define GDMA_IN_RST_CH2_M (GDMA_IN_RST_CH2_V << GDMA_IN_RST_CH2_S) +#define GDMA_IN_RST_CH2_V 0x00000001U +#define GDMA_IN_RST_CH2_S 0 +/** GDMA_IN_LOOP_TEST_CH2 : R/W; bitpos: [1]; default: 0; + * reserved + */ +#define GDMA_IN_LOOP_TEST_CH2 (BIT(1)) +#define GDMA_IN_LOOP_TEST_CH2_M (GDMA_IN_LOOP_TEST_CH2_V << GDMA_IN_LOOP_TEST_CH2_S) +#define GDMA_IN_LOOP_TEST_CH2_V 0x00000001U +#define GDMA_IN_LOOP_TEST_CH2_S 1 +/** GDMA_INDSCR_BURST_EN_CH2 : R/W; bitpos: [2]; default: 0; + * Set this bit to 1 to enable INCR burst transfer for Rx channel 2 reading link + * descriptor when accessing internal SRAM. + */ +#define GDMA_INDSCR_BURST_EN_CH2 (BIT(2)) +#define GDMA_INDSCR_BURST_EN_CH2_M (GDMA_INDSCR_BURST_EN_CH2_V << GDMA_INDSCR_BURST_EN_CH2_S) +#define GDMA_INDSCR_BURST_EN_CH2_V 0x00000001U +#define GDMA_INDSCR_BURST_EN_CH2_S 2 +/** GDMA_IN_DATA_BURST_EN_CH2 : R/W; bitpos: [3]; default: 0; + * Set this bit to 1 to enable INCR burst transfer for Rx channel 2 receiving data + * when accessing internal SRAM. + */ +#define GDMA_IN_DATA_BURST_EN_CH2 (BIT(3)) +#define GDMA_IN_DATA_BURST_EN_CH2_M (GDMA_IN_DATA_BURST_EN_CH2_V << GDMA_IN_DATA_BURST_EN_CH2_S) +#define GDMA_IN_DATA_BURST_EN_CH2_V 0x00000001U +#define GDMA_IN_DATA_BURST_EN_CH2_S 3 +/** GDMA_MEM_TRANS_EN_CH2 : R/W; bitpos: [4]; default: 0; + * Set this bit 1 to enable automatic transmitting data from memory to memory via GDMA. + */ +#define GDMA_MEM_TRANS_EN_CH2 (BIT(4)) +#define GDMA_MEM_TRANS_EN_CH2_M (GDMA_MEM_TRANS_EN_CH2_V << GDMA_MEM_TRANS_EN_CH2_S) +#define GDMA_MEM_TRANS_EN_CH2_V 0x00000001U +#define GDMA_MEM_TRANS_EN_CH2_S 4 +/** GDMA_IN_ETM_EN_CH2 : R/W; bitpos: [5]; default: 0; + * Set this bit to 1 to enable etm control mode, GDMA Rx channel 2 is triggered by etm + * task. + */ +#define GDMA_IN_ETM_EN_CH2 (BIT(5)) +#define GDMA_IN_ETM_EN_CH2_M (GDMA_IN_ETM_EN_CH2_V << GDMA_IN_ETM_EN_CH2_S) +#define GDMA_IN_ETM_EN_CH2_V 0x00000001U +#define GDMA_IN_ETM_EN_CH2_S 5 + +/** GDMA_IN_CONF1_CH2_REG register + * Configure 1 register of Rx channel 2. + */ +#define GDMA_IN_CONF1_CH2_REG (DR_REG_GDMA_BASE + 0x1f4) +/** GDMA_IN_CHECK_OWNER_CH2 : R/W; bitpos: [12]; default: 0; + * Set this bit to enable checking the owner attribute of the link descriptor. + */ +#define GDMA_IN_CHECK_OWNER_CH2 (BIT(12)) +#define GDMA_IN_CHECK_OWNER_CH2_M (GDMA_IN_CHECK_OWNER_CH2_V << GDMA_IN_CHECK_OWNER_CH2_S) +#define GDMA_IN_CHECK_OWNER_CH2_V 0x00000001U +#define GDMA_IN_CHECK_OWNER_CH2_S 12 + +/** GDMA_INFIFO_STATUS_CH2_REG register + * Receive FIFO status of Rx channel 2. + */ +#define GDMA_INFIFO_STATUS_CH2_REG (DR_REG_GDMA_BASE + 0x1f8) +/** GDMA_INFIFO_FULL_CH2 : RO; bitpos: [0]; default: 1; + * L1 Rx FIFO full signal for Rx channel 2. + */ +#define GDMA_INFIFO_FULL_CH2 (BIT(0)) +#define GDMA_INFIFO_FULL_CH2_M (GDMA_INFIFO_FULL_CH2_V << GDMA_INFIFO_FULL_CH2_S) +#define GDMA_INFIFO_FULL_CH2_V 0x00000001U +#define GDMA_INFIFO_FULL_CH2_S 0 +/** GDMA_INFIFO_EMPTY_CH2 : RO; bitpos: [1]; default: 1; + * L1 Rx FIFO empty signal for Rx channel 2. + */ +#define GDMA_INFIFO_EMPTY_CH2 (BIT(1)) +#define GDMA_INFIFO_EMPTY_CH2_M (GDMA_INFIFO_EMPTY_CH2_V << GDMA_INFIFO_EMPTY_CH2_S) +#define GDMA_INFIFO_EMPTY_CH2_V 0x00000001U +#define GDMA_INFIFO_EMPTY_CH2_S 1 +/** GDMA_INFIFO_CNT_CH2 : RO; bitpos: [7:2]; default: 0; + * The register stores the byte number of the data in L1 Rx FIFO for Rx channel 2. + */ +#define GDMA_INFIFO_CNT_CH2 0x0000003FU +#define GDMA_INFIFO_CNT_CH2_M (GDMA_INFIFO_CNT_CH2_V << GDMA_INFIFO_CNT_CH2_S) +#define GDMA_INFIFO_CNT_CH2_V 0x0000003FU +#define GDMA_INFIFO_CNT_CH2_S 2 +/** GDMA_IN_REMAIN_UNDER_1B_CH2 : RO; bitpos: [23]; default: 1; + * reserved + */ +#define GDMA_IN_REMAIN_UNDER_1B_CH2 (BIT(23)) +#define GDMA_IN_REMAIN_UNDER_1B_CH2_M (GDMA_IN_REMAIN_UNDER_1B_CH2_V << GDMA_IN_REMAIN_UNDER_1B_CH2_S) +#define GDMA_IN_REMAIN_UNDER_1B_CH2_V 0x00000001U +#define GDMA_IN_REMAIN_UNDER_1B_CH2_S 23 +/** GDMA_IN_REMAIN_UNDER_2B_CH2 : RO; bitpos: [24]; default: 1; + * reserved + */ +#define GDMA_IN_REMAIN_UNDER_2B_CH2 (BIT(24)) +#define GDMA_IN_REMAIN_UNDER_2B_CH2_M (GDMA_IN_REMAIN_UNDER_2B_CH2_V << GDMA_IN_REMAIN_UNDER_2B_CH2_S) +#define GDMA_IN_REMAIN_UNDER_2B_CH2_V 0x00000001U +#define GDMA_IN_REMAIN_UNDER_2B_CH2_S 24 +/** GDMA_IN_REMAIN_UNDER_3B_CH2 : RO; bitpos: [25]; default: 1; + * reserved + */ +#define GDMA_IN_REMAIN_UNDER_3B_CH2 (BIT(25)) +#define GDMA_IN_REMAIN_UNDER_3B_CH2_M (GDMA_IN_REMAIN_UNDER_3B_CH2_V << GDMA_IN_REMAIN_UNDER_3B_CH2_S) +#define GDMA_IN_REMAIN_UNDER_3B_CH2_V 0x00000001U +#define GDMA_IN_REMAIN_UNDER_3B_CH2_S 25 +/** GDMA_IN_REMAIN_UNDER_4B_CH2 : RO; bitpos: [26]; default: 1; + * reserved + */ +#define GDMA_IN_REMAIN_UNDER_4B_CH2 (BIT(26)) +#define GDMA_IN_REMAIN_UNDER_4B_CH2_M (GDMA_IN_REMAIN_UNDER_4B_CH2_V << GDMA_IN_REMAIN_UNDER_4B_CH2_S) +#define GDMA_IN_REMAIN_UNDER_4B_CH2_V 0x00000001U +#define GDMA_IN_REMAIN_UNDER_4B_CH2_S 26 +/** GDMA_IN_BUF_HUNGRY_CH2 : RO; bitpos: [27]; default: 0; + * reserved + */ +#define GDMA_IN_BUF_HUNGRY_CH2 (BIT(27)) +#define GDMA_IN_BUF_HUNGRY_CH2_M (GDMA_IN_BUF_HUNGRY_CH2_V << GDMA_IN_BUF_HUNGRY_CH2_S) +#define GDMA_IN_BUF_HUNGRY_CH2_V 0x00000001U +#define GDMA_IN_BUF_HUNGRY_CH2_S 27 + +/** GDMA_IN_POP_CH2_REG register + * Pop control register of Rx channel 2. + */ +#define GDMA_IN_POP_CH2_REG (DR_REG_GDMA_BASE + 0x1fc) +/** GDMA_INFIFO_RDATA_CH2 : RO; bitpos: [11:0]; default: 2048; + * This register stores the data popping from GDMA FIFO. + */ +#define GDMA_INFIFO_RDATA_CH2 0x00000FFFU +#define GDMA_INFIFO_RDATA_CH2_M (GDMA_INFIFO_RDATA_CH2_V << GDMA_INFIFO_RDATA_CH2_S) +#define GDMA_INFIFO_RDATA_CH2_V 0x00000FFFU +#define GDMA_INFIFO_RDATA_CH2_S 0 +/** GDMA_INFIFO_POP_CH2 : WT; bitpos: [12]; default: 0; + * Set this bit to pop data from GDMA FIFO. + */ +#define GDMA_INFIFO_POP_CH2 (BIT(12)) +#define GDMA_INFIFO_POP_CH2_M (GDMA_INFIFO_POP_CH2_V << GDMA_INFIFO_POP_CH2_S) +#define GDMA_INFIFO_POP_CH2_V 0x00000001U +#define GDMA_INFIFO_POP_CH2_S 12 + +/** GDMA_IN_LINK_CH2_REG register + * Link descriptor configure and control register of Rx channel 2. + */ +#define GDMA_IN_LINK_CH2_REG (DR_REG_GDMA_BASE + 0x200) +/** GDMA_INLINK_ADDR_CH2 : R/W; bitpos: [19:0]; default: 0; + * This register stores the 20 least significant bits of the first inlink descriptor's + * address. + */ +#define GDMA_INLINK_ADDR_CH2 0x000FFFFFU +#define GDMA_INLINK_ADDR_CH2_M (GDMA_INLINK_ADDR_CH2_V << GDMA_INLINK_ADDR_CH2_S) +#define GDMA_INLINK_ADDR_CH2_V 0x000FFFFFU +#define GDMA_INLINK_ADDR_CH2_S 0 +/** GDMA_INLINK_AUTO_RET_CH2 : R/W; bitpos: [20]; default: 1; + * Set this bit to return to current inlink descriptor's address when there are some + * errors in current receiving data. + */ +#define GDMA_INLINK_AUTO_RET_CH2 (BIT(20)) +#define GDMA_INLINK_AUTO_RET_CH2_M (GDMA_INLINK_AUTO_RET_CH2_V << GDMA_INLINK_AUTO_RET_CH2_S) +#define GDMA_INLINK_AUTO_RET_CH2_V 0x00000001U +#define GDMA_INLINK_AUTO_RET_CH2_S 20 +/** GDMA_INLINK_STOP_CH2 : WT; bitpos: [21]; default: 0; + * Set this bit to stop dealing with the inlink descriptors. + */ +#define GDMA_INLINK_STOP_CH2 (BIT(21)) +#define GDMA_INLINK_STOP_CH2_M (GDMA_INLINK_STOP_CH2_V << GDMA_INLINK_STOP_CH2_S) +#define GDMA_INLINK_STOP_CH2_V 0x00000001U +#define GDMA_INLINK_STOP_CH2_S 21 +/** GDMA_INLINK_START_CH2 : WT; bitpos: [22]; default: 0; + * Set this bit to start dealing with the inlink descriptors. + */ +#define GDMA_INLINK_START_CH2 (BIT(22)) +#define GDMA_INLINK_START_CH2_M (GDMA_INLINK_START_CH2_V << GDMA_INLINK_START_CH2_S) +#define GDMA_INLINK_START_CH2_V 0x00000001U +#define GDMA_INLINK_START_CH2_S 22 +/** GDMA_INLINK_RESTART_CH2 : WT; bitpos: [23]; default: 0; + * Set this bit to mount a new inlink descriptor. + */ +#define GDMA_INLINK_RESTART_CH2 (BIT(23)) +#define GDMA_INLINK_RESTART_CH2_M (GDMA_INLINK_RESTART_CH2_V << GDMA_INLINK_RESTART_CH2_S) +#define GDMA_INLINK_RESTART_CH2_V 0x00000001U +#define GDMA_INLINK_RESTART_CH2_S 23 +/** GDMA_INLINK_PARK_CH2 : RO; bitpos: [24]; default: 1; + * 1: the inlink descriptor's FSM is in idle state. 0: the inlink descriptor's FSM is + * working. + */ +#define GDMA_INLINK_PARK_CH2 (BIT(24)) +#define GDMA_INLINK_PARK_CH2_M (GDMA_INLINK_PARK_CH2_V << GDMA_INLINK_PARK_CH2_S) +#define GDMA_INLINK_PARK_CH2_V 0x00000001U +#define GDMA_INLINK_PARK_CH2_S 24 + +/** GDMA_IN_STATE_CH2_REG register + * Receive status of Rx channel 2. + */ +#define GDMA_IN_STATE_CH2_REG (DR_REG_GDMA_BASE + 0x204) +/** GDMA_INLINK_DSCR_ADDR_CH2 : RO; bitpos: [17:0]; default: 0; + * This register stores the current inlink descriptor's address. + */ +#define GDMA_INLINK_DSCR_ADDR_CH2 0x0003FFFFU +#define GDMA_INLINK_DSCR_ADDR_CH2_M (GDMA_INLINK_DSCR_ADDR_CH2_V << GDMA_INLINK_DSCR_ADDR_CH2_S) +#define GDMA_INLINK_DSCR_ADDR_CH2_V 0x0003FFFFU +#define GDMA_INLINK_DSCR_ADDR_CH2_S 0 +/** GDMA_IN_DSCR_STATE_CH2 : RO; bitpos: [19:18]; default: 0; + * reserved + */ +#define GDMA_IN_DSCR_STATE_CH2 0x00000003U +#define GDMA_IN_DSCR_STATE_CH2_M (GDMA_IN_DSCR_STATE_CH2_V << GDMA_IN_DSCR_STATE_CH2_S) +#define GDMA_IN_DSCR_STATE_CH2_V 0x00000003U +#define GDMA_IN_DSCR_STATE_CH2_S 18 +/** GDMA_IN_STATE_CH2 : RO; bitpos: [22:20]; default: 0; + * reserved + */ +#define GDMA_IN_STATE_CH2 0x00000007U +#define GDMA_IN_STATE_CH2_M (GDMA_IN_STATE_CH2_V << GDMA_IN_STATE_CH2_S) +#define GDMA_IN_STATE_CH2_V 0x00000007U +#define GDMA_IN_STATE_CH2_S 20 + +/** GDMA_IN_SUC_EOF_DES_ADDR_CH2_REG register + * Inlink descriptor address when EOF occurs of Rx channel 2. + */ +#define GDMA_IN_SUC_EOF_DES_ADDR_CH2_REG (DR_REG_GDMA_BASE + 0x208) +/** GDMA_IN_SUC_EOF_DES_ADDR_CH2 : RO; bitpos: [31:0]; default: 0; + * This register stores the address of the inlink descriptor when the EOF bit in this + * descriptor is 1. + */ +#define GDMA_IN_SUC_EOF_DES_ADDR_CH2 0xFFFFFFFFU +#define GDMA_IN_SUC_EOF_DES_ADDR_CH2_M (GDMA_IN_SUC_EOF_DES_ADDR_CH2_V << GDMA_IN_SUC_EOF_DES_ADDR_CH2_S) +#define GDMA_IN_SUC_EOF_DES_ADDR_CH2_V 0xFFFFFFFFU +#define GDMA_IN_SUC_EOF_DES_ADDR_CH2_S 0 + +/** GDMA_IN_ERR_EOF_DES_ADDR_CH2_REG register + * Inlink descriptor address when errors occur of Rx channel 2. + */ +#define GDMA_IN_ERR_EOF_DES_ADDR_CH2_REG (DR_REG_GDMA_BASE + 0x20c) +/** GDMA_IN_ERR_EOF_DES_ADDR_CH2 : RO; bitpos: [31:0]; default: 0; + * This register stores the address of the inlink descriptor when there are some + * errors in current receiving data. Only used when peripheral is UHCI0. + */ +#define GDMA_IN_ERR_EOF_DES_ADDR_CH2 0xFFFFFFFFU +#define GDMA_IN_ERR_EOF_DES_ADDR_CH2_M (GDMA_IN_ERR_EOF_DES_ADDR_CH2_V << GDMA_IN_ERR_EOF_DES_ADDR_CH2_S) +#define GDMA_IN_ERR_EOF_DES_ADDR_CH2_V 0xFFFFFFFFU +#define GDMA_IN_ERR_EOF_DES_ADDR_CH2_S 0 + +/** GDMA_IN_DSCR_CH2_REG register + * Current inlink descriptor address of Rx channel 2. + */ +#define GDMA_IN_DSCR_CH2_REG (DR_REG_GDMA_BASE + 0x210) +/** GDMA_INLINK_DSCR_CH2 : RO; bitpos: [31:0]; default: 0; + * The address of the current inlink descriptor x. + */ +#define GDMA_INLINK_DSCR_CH2 0xFFFFFFFFU +#define GDMA_INLINK_DSCR_CH2_M (GDMA_INLINK_DSCR_CH2_V << GDMA_INLINK_DSCR_CH2_S) +#define GDMA_INLINK_DSCR_CH2_V 0xFFFFFFFFU +#define GDMA_INLINK_DSCR_CH2_S 0 + +/** GDMA_IN_DSCR_BF0_CH2_REG register + * The last inlink descriptor address of Rx channel 2. + */ +#define GDMA_IN_DSCR_BF0_CH2_REG (DR_REG_GDMA_BASE + 0x214) +/** GDMA_INLINK_DSCR_BF0_CH2 : RO; bitpos: [31:0]; default: 0; + * The address of the last inlink descriptor x-1. + */ +#define GDMA_INLINK_DSCR_BF0_CH2 0xFFFFFFFFU +#define GDMA_INLINK_DSCR_BF0_CH2_M (GDMA_INLINK_DSCR_BF0_CH2_V << GDMA_INLINK_DSCR_BF0_CH2_S) +#define GDMA_INLINK_DSCR_BF0_CH2_V 0xFFFFFFFFU +#define GDMA_INLINK_DSCR_BF0_CH2_S 0 + +/** GDMA_IN_DSCR_BF1_CH2_REG register + * The second-to-last inlink descriptor address of Rx channel 2. + */ +#define GDMA_IN_DSCR_BF1_CH2_REG (DR_REG_GDMA_BASE + 0x218) +/** GDMA_INLINK_DSCR_BF1_CH2 : RO; bitpos: [31:0]; default: 0; + * The address of the second-to-last inlink descriptor x-2. + */ +#define GDMA_INLINK_DSCR_BF1_CH2 0xFFFFFFFFU +#define GDMA_INLINK_DSCR_BF1_CH2_M (GDMA_INLINK_DSCR_BF1_CH2_V << GDMA_INLINK_DSCR_BF1_CH2_S) +#define GDMA_INLINK_DSCR_BF1_CH2_V 0xFFFFFFFFU +#define GDMA_INLINK_DSCR_BF1_CH2_S 0 + +/** GDMA_IN_PRI_CH2_REG register + * Priority register of Rx channel 2. + */ +#define GDMA_IN_PRI_CH2_REG (DR_REG_GDMA_BASE + 0x21c) +/** GDMA_RX_PRI_CH2 : R/W; bitpos: [3:0]; default: 0; + * The priority of Rx channel 2. The larger of the value the higher of the priority. + */ +#define GDMA_RX_PRI_CH2 0x0000000FU +#define GDMA_RX_PRI_CH2_M (GDMA_RX_PRI_CH2_V << GDMA_RX_PRI_CH2_S) +#define GDMA_RX_PRI_CH2_V 0x0000000FU +#define GDMA_RX_PRI_CH2_S 0 + +/** GDMA_IN_PERI_SEL_CH2_REG register + * Peripheral selection of Rx channel 2. + */ +#define GDMA_IN_PERI_SEL_CH2_REG (DR_REG_GDMA_BASE + 0x220) +/** GDMA_PERI_IN_SEL_CH2 : R/W; bitpos: [5:0]; default: 63; + * This register is used to select peripheral for Rx channel 2. 0:SPI2. 1: Dummy. 2: + * UHCI0. 3: I2S0. 4: Dummy. 5: Dummy. 6: AES. 7: SHA. 8: ADC_DAC. 9: Parallel_IO. + * 10~15: Dummy + */ +#define GDMA_PERI_IN_SEL_CH2 0x0000003FU +#define GDMA_PERI_IN_SEL_CH2_M (GDMA_PERI_IN_SEL_CH2_V << GDMA_PERI_IN_SEL_CH2_S) +#define GDMA_PERI_IN_SEL_CH2_V 0x0000003FU +#define GDMA_PERI_IN_SEL_CH2_S 0 + +/** GDMA_OUT_CONF0_CH2_REG register + * Configure 0 register of Tx channel 2. + */ +#define GDMA_OUT_CONF0_CH2_REG (DR_REG_GDMA_BASE + 0x250) +/** GDMA_OUT_RST_CH2 : R/W; bitpos: [0]; default: 0; + * This bit is used to reset DMA channel 2 Tx FSM and Tx FIFO pointer. + */ +#define GDMA_OUT_RST_CH2 (BIT(0)) +#define GDMA_OUT_RST_CH2_M (GDMA_OUT_RST_CH2_V << GDMA_OUT_RST_CH2_S) +#define GDMA_OUT_RST_CH2_V 0x00000001U +#define GDMA_OUT_RST_CH2_S 0 +/** GDMA_OUT_LOOP_TEST_CH2 : R/W; bitpos: [1]; default: 0; + * reserved + */ +#define GDMA_OUT_LOOP_TEST_CH2 (BIT(1)) +#define GDMA_OUT_LOOP_TEST_CH2_M (GDMA_OUT_LOOP_TEST_CH2_V << GDMA_OUT_LOOP_TEST_CH2_S) +#define GDMA_OUT_LOOP_TEST_CH2_V 0x00000001U +#define GDMA_OUT_LOOP_TEST_CH2_S 1 +/** GDMA_OUT_AUTO_WRBACK_CH2 : R/W; bitpos: [2]; default: 0; + * Set this bit to enable automatic outlink-writeback when all the data in tx buffer + * has been transmitted. + */ +#define GDMA_OUT_AUTO_WRBACK_CH2 (BIT(2)) +#define GDMA_OUT_AUTO_WRBACK_CH2_M (GDMA_OUT_AUTO_WRBACK_CH2_V << GDMA_OUT_AUTO_WRBACK_CH2_S) +#define GDMA_OUT_AUTO_WRBACK_CH2_V 0x00000001U +#define GDMA_OUT_AUTO_WRBACK_CH2_S 2 +/** GDMA_OUT_EOF_MODE_CH2 : R/W; bitpos: [3]; default: 1; + * EOF flag generation mode when transmitting data. 1: EOF flag for Tx channel 2 is + * generated when data need to transmit has been popped from FIFO in DMA + */ +#define GDMA_OUT_EOF_MODE_CH2 (BIT(3)) +#define GDMA_OUT_EOF_MODE_CH2_M (GDMA_OUT_EOF_MODE_CH2_V << GDMA_OUT_EOF_MODE_CH2_S) +#define GDMA_OUT_EOF_MODE_CH2_V 0x00000001U +#define GDMA_OUT_EOF_MODE_CH2_S 3 +/** GDMA_OUTDSCR_BURST_EN_CH2 : R/W; bitpos: [4]; default: 0; + * Set this bit to 1 to enable INCR burst transfer for Tx channel 2 reading link + * descriptor when accessing internal SRAM. + */ +#define GDMA_OUTDSCR_BURST_EN_CH2 (BIT(4)) +#define GDMA_OUTDSCR_BURST_EN_CH2_M (GDMA_OUTDSCR_BURST_EN_CH2_V << GDMA_OUTDSCR_BURST_EN_CH2_S) +#define GDMA_OUTDSCR_BURST_EN_CH2_V 0x00000001U +#define GDMA_OUTDSCR_BURST_EN_CH2_S 4 +/** GDMA_OUT_DATA_BURST_EN_CH2 : R/W; bitpos: [5]; default: 0; + * Set this bit to 1 to enable INCR burst transfer for Tx channel 2 transmitting data + * when accessing internal SRAM. + */ +#define GDMA_OUT_DATA_BURST_EN_CH2 (BIT(5)) +#define GDMA_OUT_DATA_BURST_EN_CH2_M (GDMA_OUT_DATA_BURST_EN_CH2_V << GDMA_OUT_DATA_BURST_EN_CH2_S) +#define GDMA_OUT_DATA_BURST_EN_CH2_V 0x00000001U +#define GDMA_OUT_DATA_BURST_EN_CH2_S 5 +/** GDMA_OUT_ETM_EN_CH2 : R/W; bitpos: [6]; default: 0; + * Set this bit to 1 to enable etm control mode, GDMA Tx channel 2 is triggered by etm + * task. + */ +#define GDMA_OUT_ETM_EN_CH2 (BIT(6)) +#define GDMA_OUT_ETM_EN_CH2_M (GDMA_OUT_ETM_EN_CH2_V << GDMA_OUT_ETM_EN_CH2_S) +#define GDMA_OUT_ETM_EN_CH2_V 0x00000001U +#define GDMA_OUT_ETM_EN_CH2_S 6 + +/** GDMA_OUT_CONF1_CH2_REG register + * Configure 1 register of Tx channel 2. + */ +#define GDMA_OUT_CONF1_CH2_REG (DR_REG_GDMA_BASE + 0x254) +/** GDMA_OUT_CHECK_OWNER_CH2 : R/W; bitpos: [12]; default: 0; + * Set this bit to enable checking the owner attribute of the link descriptor. + */ +#define GDMA_OUT_CHECK_OWNER_CH2 (BIT(12)) +#define GDMA_OUT_CHECK_OWNER_CH2_M (GDMA_OUT_CHECK_OWNER_CH2_V << GDMA_OUT_CHECK_OWNER_CH2_S) +#define GDMA_OUT_CHECK_OWNER_CH2_V 0x00000001U +#define GDMA_OUT_CHECK_OWNER_CH2_S 12 + +/** GDMA_OUTFIFO_STATUS_CH2_REG register + * Transmit FIFO status of Tx channel 2. + */ +#define GDMA_OUTFIFO_STATUS_CH2_REG (DR_REG_GDMA_BASE + 0x258) +/** GDMA_OUTFIFO_FULL_CH2 : RO; bitpos: [0]; default: 0; + * L1 Tx FIFO full signal for Tx channel 2. + */ +#define GDMA_OUTFIFO_FULL_CH2 (BIT(0)) +#define GDMA_OUTFIFO_FULL_CH2_M (GDMA_OUTFIFO_FULL_CH2_V << GDMA_OUTFIFO_FULL_CH2_S) +#define GDMA_OUTFIFO_FULL_CH2_V 0x00000001U +#define GDMA_OUTFIFO_FULL_CH2_S 0 +/** GDMA_OUTFIFO_EMPTY_CH2 : RO; bitpos: [1]; default: 1; + * L1 Tx FIFO empty signal for Tx channel 2. + */ +#define GDMA_OUTFIFO_EMPTY_CH2 (BIT(1)) +#define GDMA_OUTFIFO_EMPTY_CH2_M (GDMA_OUTFIFO_EMPTY_CH2_V << GDMA_OUTFIFO_EMPTY_CH2_S) +#define GDMA_OUTFIFO_EMPTY_CH2_V 0x00000001U +#define GDMA_OUTFIFO_EMPTY_CH2_S 1 +/** GDMA_OUTFIFO_CNT_CH2 : RO; bitpos: [7:2]; default: 0; + * The register stores the byte number of the data in L1 Tx FIFO for Tx channel 2. + */ +#define GDMA_OUTFIFO_CNT_CH2 0x0000003FU +#define GDMA_OUTFIFO_CNT_CH2_M (GDMA_OUTFIFO_CNT_CH2_V << GDMA_OUTFIFO_CNT_CH2_S) +#define GDMA_OUTFIFO_CNT_CH2_V 0x0000003FU +#define GDMA_OUTFIFO_CNT_CH2_S 2 +/** GDMA_OUT_REMAIN_UNDER_1B_CH2 : RO; bitpos: [23]; default: 1; + * reserved + */ +#define GDMA_OUT_REMAIN_UNDER_1B_CH2 (BIT(23)) +#define GDMA_OUT_REMAIN_UNDER_1B_CH2_M (GDMA_OUT_REMAIN_UNDER_1B_CH2_V << GDMA_OUT_REMAIN_UNDER_1B_CH2_S) +#define GDMA_OUT_REMAIN_UNDER_1B_CH2_V 0x00000001U +#define GDMA_OUT_REMAIN_UNDER_1B_CH2_S 23 +/** GDMA_OUT_REMAIN_UNDER_2B_CH2 : RO; bitpos: [24]; default: 1; + * reserved + */ +#define GDMA_OUT_REMAIN_UNDER_2B_CH2 (BIT(24)) +#define GDMA_OUT_REMAIN_UNDER_2B_CH2_M (GDMA_OUT_REMAIN_UNDER_2B_CH2_V << GDMA_OUT_REMAIN_UNDER_2B_CH2_S) +#define GDMA_OUT_REMAIN_UNDER_2B_CH2_V 0x00000001U +#define GDMA_OUT_REMAIN_UNDER_2B_CH2_S 24 +/** GDMA_OUT_REMAIN_UNDER_3B_CH2 : RO; bitpos: [25]; default: 1; + * reserved + */ +#define GDMA_OUT_REMAIN_UNDER_3B_CH2 (BIT(25)) +#define GDMA_OUT_REMAIN_UNDER_3B_CH2_M (GDMA_OUT_REMAIN_UNDER_3B_CH2_V << GDMA_OUT_REMAIN_UNDER_3B_CH2_S) +#define GDMA_OUT_REMAIN_UNDER_3B_CH2_V 0x00000001U +#define GDMA_OUT_REMAIN_UNDER_3B_CH2_S 25 +/** GDMA_OUT_REMAIN_UNDER_4B_CH2 : RO; bitpos: [26]; default: 1; + * reserved + */ +#define GDMA_OUT_REMAIN_UNDER_4B_CH2 (BIT(26)) +#define GDMA_OUT_REMAIN_UNDER_4B_CH2_M (GDMA_OUT_REMAIN_UNDER_4B_CH2_V << GDMA_OUT_REMAIN_UNDER_4B_CH2_S) +#define GDMA_OUT_REMAIN_UNDER_4B_CH2_V 0x00000001U +#define GDMA_OUT_REMAIN_UNDER_4B_CH2_S 26 + +/** GDMA_OUT_PUSH_CH2_REG register + * Push control register of Rx channel 2. + */ +#define GDMA_OUT_PUSH_CH2_REG (DR_REG_GDMA_BASE + 0x25c) +/** GDMA_OUTFIFO_WDATA_CH2 : R/W; bitpos: [8:0]; default: 0; + * This register stores the data that need to be pushed into GDMA FIFO. + */ +#define GDMA_OUTFIFO_WDATA_CH2 0x000001FFU +#define GDMA_OUTFIFO_WDATA_CH2_M (GDMA_OUTFIFO_WDATA_CH2_V << GDMA_OUTFIFO_WDATA_CH2_S) +#define GDMA_OUTFIFO_WDATA_CH2_V 0x000001FFU +#define GDMA_OUTFIFO_WDATA_CH2_S 0 +/** GDMA_OUTFIFO_PUSH_CH2 : WT; bitpos: [9]; default: 0; + * Set this bit to push data into GDMA FIFO. + */ +#define GDMA_OUTFIFO_PUSH_CH2 (BIT(9)) +#define GDMA_OUTFIFO_PUSH_CH2_M (GDMA_OUTFIFO_PUSH_CH2_V << GDMA_OUTFIFO_PUSH_CH2_S) +#define GDMA_OUTFIFO_PUSH_CH2_V 0x00000001U +#define GDMA_OUTFIFO_PUSH_CH2_S 9 + +/** GDMA_OUT_LINK_CH2_REG register + * Link descriptor configure and control register of Tx channel 2. + */ +#define GDMA_OUT_LINK_CH2_REG (DR_REG_GDMA_BASE + 0x260) +/** GDMA_OUTLINK_ADDR_CH2 : R/W; bitpos: [19:0]; default: 0; + * This register stores the 20 least significant bits of the first outlink + * descriptor's address. + */ +#define GDMA_OUTLINK_ADDR_CH2 0x000FFFFFU +#define GDMA_OUTLINK_ADDR_CH2_M (GDMA_OUTLINK_ADDR_CH2_V << GDMA_OUTLINK_ADDR_CH2_S) +#define GDMA_OUTLINK_ADDR_CH2_V 0x000FFFFFU +#define GDMA_OUTLINK_ADDR_CH2_S 0 +/** GDMA_OUTLINK_STOP_CH2 : WT; bitpos: [20]; default: 0; + * Set this bit to stop dealing with the outlink descriptors. + */ +#define GDMA_OUTLINK_STOP_CH2 (BIT(20)) +#define GDMA_OUTLINK_STOP_CH2_M (GDMA_OUTLINK_STOP_CH2_V << GDMA_OUTLINK_STOP_CH2_S) +#define GDMA_OUTLINK_STOP_CH2_V 0x00000001U +#define GDMA_OUTLINK_STOP_CH2_S 20 +/** GDMA_OUTLINK_START_CH2 : WT; bitpos: [21]; default: 0; + * Set this bit to start dealing with the outlink descriptors. + */ +#define GDMA_OUTLINK_START_CH2 (BIT(21)) +#define GDMA_OUTLINK_START_CH2_M (GDMA_OUTLINK_START_CH2_V << GDMA_OUTLINK_START_CH2_S) +#define GDMA_OUTLINK_START_CH2_V 0x00000001U +#define GDMA_OUTLINK_START_CH2_S 21 +/** GDMA_OUTLINK_RESTART_CH2 : WT; bitpos: [22]; default: 0; + * Set this bit to restart a new outlink from the last address. + */ +#define GDMA_OUTLINK_RESTART_CH2 (BIT(22)) +#define GDMA_OUTLINK_RESTART_CH2_M (GDMA_OUTLINK_RESTART_CH2_V << GDMA_OUTLINK_RESTART_CH2_S) +#define GDMA_OUTLINK_RESTART_CH2_V 0x00000001U +#define GDMA_OUTLINK_RESTART_CH2_S 22 +/** GDMA_OUTLINK_PARK_CH2 : RO; bitpos: [23]; default: 1; + * 1: the outlink descriptor's FSM is in idle state. 0: the outlink descriptor's FSM + * is working. + */ +#define GDMA_OUTLINK_PARK_CH2 (BIT(23)) +#define GDMA_OUTLINK_PARK_CH2_M (GDMA_OUTLINK_PARK_CH2_V << GDMA_OUTLINK_PARK_CH2_S) +#define GDMA_OUTLINK_PARK_CH2_V 0x00000001U +#define GDMA_OUTLINK_PARK_CH2_S 23 + +/** GDMA_OUT_STATE_CH2_REG register + * Transmit status of Tx channel 2. + */ +#define GDMA_OUT_STATE_CH2_REG (DR_REG_GDMA_BASE + 0x264) +/** GDMA_OUTLINK_DSCR_ADDR_CH2 : RO; bitpos: [17:0]; default: 0; + * This register stores the current outlink descriptor's address. + */ +#define GDMA_OUTLINK_DSCR_ADDR_CH2 0x0003FFFFU +#define GDMA_OUTLINK_DSCR_ADDR_CH2_M (GDMA_OUTLINK_DSCR_ADDR_CH2_V << GDMA_OUTLINK_DSCR_ADDR_CH2_S) +#define GDMA_OUTLINK_DSCR_ADDR_CH2_V 0x0003FFFFU +#define GDMA_OUTLINK_DSCR_ADDR_CH2_S 0 +/** GDMA_OUT_DSCR_STATE_CH2 : RO; bitpos: [19:18]; default: 0; + * reserved + */ +#define GDMA_OUT_DSCR_STATE_CH2 0x00000003U +#define GDMA_OUT_DSCR_STATE_CH2_M (GDMA_OUT_DSCR_STATE_CH2_V << GDMA_OUT_DSCR_STATE_CH2_S) +#define GDMA_OUT_DSCR_STATE_CH2_V 0x00000003U +#define GDMA_OUT_DSCR_STATE_CH2_S 18 +/** GDMA_OUT_STATE_CH2 : RO; bitpos: [22:20]; default: 0; + * reserved + */ +#define GDMA_OUT_STATE_CH2 0x00000007U +#define GDMA_OUT_STATE_CH2_M (GDMA_OUT_STATE_CH2_V << GDMA_OUT_STATE_CH2_S) +#define GDMA_OUT_STATE_CH2_V 0x00000007U +#define GDMA_OUT_STATE_CH2_S 20 + +/** GDMA_OUT_EOF_DES_ADDR_CH2_REG register + * Outlink descriptor address when EOF occurs of Tx channel 2. + */ +#define GDMA_OUT_EOF_DES_ADDR_CH2_REG (DR_REG_GDMA_BASE + 0x268) +/** GDMA_OUT_EOF_DES_ADDR_CH2 : RO; bitpos: [31:0]; default: 0; + * This register stores the address of the outlink descriptor when the EOF bit in this + * descriptor is 1. + */ +#define GDMA_OUT_EOF_DES_ADDR_CH2 0xFFFFFFFFU +#define GDMA_OUT_EOF_DES_ADDR_CH2_M (GDMA_OUT_EOF_DES_ADDR_CH2_V << GDMA_OUT_EOF_DES_ADDR_CH2_S) +#define GDMA_OUT_EOF_DES_ADDR_CH2_V 0xFFFFFFFFU +#define GDMA_OUT_EOF_DES_ADDR_CH2_S 0 + +/** GDMA_OUT_EOF_BFR_DES_ADDR_CH2_REG register + * The last outlink descriptor address when EOF occurs of Tx channel 2. + */ +#define GDMA_OUT_EOF_BFR_DES_ADDR_CH2_REG (DR_REG_GDMA_BASE + 0x26c) +/** GDMA_OUT_EOF_BFR_DES_ADDR_CH2 : RO; bitpos: [31:0]; default: 0; + * This register stores the address of the outlink descriptor before the last outlink + * descriptor. + */ +#define GDMA_OUT_EOF_BFR_DES_ADDR_CH2 0xFFFFFFFFU +#define GDMA_OUT_EOF_BFR_DES_ADDR_CH2_M (GDMA_OUT_EOF_BFR_DES_ADDR_CH2_V << GDMA_OUT_EOF_BFR_DES_ADDR_CH2_S) +#define GDMA_OUT_EOF_BFR_DES_ADDR_CH2_V 0xFFFFFFFFU +#define GDMA_OUT_EOF_BFR_DES_ADDR_CH2_S 0 + +/** GDMA_OUT_DSCR_CH2_REG register + * Current inlink descriptor address of Tx channel 2. + */ +#define GDMA_OUT_DSCR_CH2_REG (DR_REG_GDMA_BASE + 0x270) +/** GDMA_OUTLINK_DSCR_CH2 : RO; bitpos: [31:0]; default: 0; + * The address of the current outlink descriptor y. + */ +#define GDMA_OUTLINK_DSCR_CH2 0xFFFFFFFFU +#define GDMA_OUTLINK_DSCR_CH2_M (GDMA_OUTLINK_DSCR_CH2_V << GDMA_OUTLINK_DSCR_CH2_S) +#define GDMA_OUTLINK_DSCR_CH2_V 0xFFFFFFFFU +#define GDMA_OUTLINK_DSCR_CH2_S 0 + +/** GDMA_OUT_DSCR_BF0_CH2_REG register + * The last inlink descriptor address of Tx channel 2. + */ +#define GDMA_OUT_DSCR_BF0_CH2_REG (DR_REG_GDMA_BASE + 0x274) +/** GDMA_OUTLINK_DSCR_BF0_CH2 : RO; bitpos: [31:0]; default: 0; + * The address of the last outlink descriptor y-1. + */ +#define GDMA_OUTLINK_DSCR_BF0_CH2 0xFFFFFFFFU +#define GDMA_OUTLINK_DSCR_BF0_CH2_M (GDMA_OUTLINK_DSCR_BF0_CH2_V << GDMA_OUTLINK_DSCR_BF0_CH2_S) +#define GDMA_OUTLINK_DSCR_BF0_CH2_V 0xFFFFFFFFU +#define GDMA_OUTLINK_DSCR_BF0_CH2_S 0 + +/** GDMA_OUT_DSCR_BF1_CH2_REG register + * The second-to-last inlink descriptor address of Tx channel 2. + */ +#define GDMA_OUT_DSCR_BF1_CH2_REG (DR_REG_GDMA_BASE + 0x278) +/** GDMA_OUTLINK_DSCR_BF1_CH2 : RO; bitpos: [31:0]; default: 0; + * The address of the second-to-last inlink descriptor x-2. + */ +#define GDMA_OUTLINK_DSCR_BF1_CH2 0xFFFFFFFFU +#define GDMA_OUTLINK_DSCR_BF1_CH2_M (GDMA_OUTLINK_DSCR_BF1_CH2_V << GDMA_OUTLINK_DSCR_BF1_CH2_S) +#define GDMA_OUTLINK_DSCR_BF1_CH2_V 0xFFFFFFFFU +#define GDMA_OUTLINK_DSCR_BF1_CH2_S 0 + +/** GDMA_OUT_PRI_CH2_REG register + * Priority register of Tx channel 2. + */ +#define GDMA_OUT_PRI_CH2_REG (DR_REG_GDMA_BASE + 0x27c) +/** GDMA_TX_PRI_CH2 : R/W; bitpos: [3:0]; default: 0; + * The priority of Tx channel 2. The larger of the value the higher of the priority. + */ +#define GDMA_TX_PRI_CH2 0x0000000FU +#define GDMA_TX_PRI_CH2_M (GDMA_TX_PRI_CH2_V << GDMA_TX_PRI_CH2_S) +#define GDMA_TX_PRI_CH2_V 0x0000000FU +#define GDMA_TX_PRI_CH2_S 0 + +/** GDMA_OUT_PERI_SEL_CH2_REG register + * Peripheral selection of Tx channel 2. + */ +#define GDMA_OUT_PERI_SEL_CH2_REG (DR_REG_GDMA_BASE + 0x280) +/** GDMA_PERI_OUT_SEL_CH2 : R/W; bitpos: [5:0]; default: 63; + * This register is used to select peripheral for Tx channel 2. 0:SPI2. 1: Dummy. 2: + * UHCI0. 3: I2S0. 4: Dummy. 5: Dummy. 6: AES. 7: SHA. 8: ADC_DAC. 9: Parallel_IO. + * 10~15: Dummy + */ +#define GDMA_PERI_OUT_SEL_CH2 0x0000003FU +#define GDMA_PERI_OUT_SEL_CH2_M (GDMA_PERI_OUT_SEL_CH2_V << GDMA_PERI_OUT_SEL_CH2_S) +#define GDMA_PERI_OUT_SEL_CH2_V 0x0000003FU +#define GDMA_PERI_OUT_SEL_CH2_S 0 + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32h21/register/soc/gdma_struct.h b/components/soc/esp32h21/register/soc/gdma_struct.h new file mode 100644 index 00000000000..abb3738f67e --- /dev/null +++ b/components/soc/esp32h21/register/soc/gdma_struct.h @@ -0,0 +1,1090 @@ +/** + * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#ifdef __cplusplus +extern "C" { +#endif + +/** Group: Interrupt Registers */ +/** Type of in_int_raw_chn register + * Raw status interrupt of channel n. + */ +typedef union { + struct { + /** in_done_chn_int_raw : R/WTC/SS; bitpos: [0]; default: 0; + * The raw interrupt bit turns to high level when the last data pointed by one inlink + * descriptor has been received for Rx channel n. + */ + uint32_t in_done_chn_int_raw:1; + /** in_suc_eof_chn_int_raw : R/WTC/SS; bitpos: [1]; default: 0; + * The raw interrupt bit turns to high level when the last data pointed by one inlink + * descriptor has been received for Rx channel n. For UHCI0 the raw interrupt bit + * turns to high level when the last data pointed by one inlink descriptor has been + * received and no data error is detected for Rx channel n. + */ + uint32_t in_suc_eof_chn_int_raw:1; + /** in_err_eof_chn_int_raw : R/WTC/SS; bitpos: [2]; default: 0; + * The raw interrupt bit turns to high level when data error is detected only in the + * case that the peripheral is UHCI0 for Rx channel n. For other peripherals this raw + * interrupt is reserved. + */ + uint32_t in_err_eof_chn_int_raw:1; + /** in_dscr_err_chn_int_raw : R/WTC/SS; bitpos: [3]; default: 0; + * The raw interrupt bit turns to high level when detecting inlink descriptor error + * including owner error and the second and third word error of inlink descriptor for + * Rx channel n. + */ + uint32_t in_dscr_err_chn_int_raw:1; + /** in_dscr_empty_chn_int_raw : R/WTC/SS; bitpos: [4]; default: 0; + * The raw interrupt bit turns to high level when Rx buffer pointed by inlink is full + * and receiving data is not completed but there is no more inlink for Rx channel n. + */ + uint32_t in_dscr_empty_chn_int_raw:1; + /** infifo_ovf_chn_int_raw : R/WTC/SS; bitpos: [5]; default: 0; + * This raw interrupt bit turns to high level when level 1 fifo of Rx channel n is + * overflow. + */ + uint32_t infifo_ovf_chn_int_raw:1; + /** infifo_udf_chn_int_raw : R/WTC/SS; bitpos: [6]; default: 0; + * This raw interrupt bit turns to high level when level 1 fifo of Rx channel n is + * underflow. + */ + uint32_t infifo_udf_chn_int_raw:1; + uint32_t reserved_7:25; + }; + uint32_t val; +} gdma_in_int_raw_chn_reg_t; + +/** Type of in_int_st_chn register + * Masked interrupt of channel n. + */ +typedef union { + struct { + /** in_done_chn_int_st : RO; bitpos: [0]; default: 0; + * The raw interrupt status bit for the IN_DONE_CH_INT interrupt. + */ + uint32_t in_done_chn_int_st:1; + /** in_suc_eof_chn_int_st : RO; bitpos: [1]; default: 0; + * The raw interrupt status bit for the IN_SUC_EOF_CH_INT interrupt. + */ + uint32_t in_suc_eof_chn_int_st:1; + /** in_err_eof_chn_int_st : RO; bitpos: [2]; default: 0; + * The raw interrupt status bit for the IN_ERR_EOF_CH_INT interrupt. + */ + uint32_t in_err_eof_chn_int_st:1; + /** in_dscr_err_chn_int_st : RO; bitpos: [3]; default: 0; + * The raw interrupt status bit for the IN_DSCR_ERR_CH_INT interrupt. + */ + uint32_t in_dscr_err_chn_int_st:1; + /** in_dscr_empty_chn_int_st : RO; bitpos: [4]; default: 0; + * The raw interrupt status bit for the IN_DSCR_EMPTY_CH_INT interrupt. + */ + uint32_t in_dscr_empty_chn_int_st:1; + /** infifo_ovf_chn_int_st : RO; bitpos: [5]; default: 0; + * The raw interrupt status bit for the INFIFO_OVF_L1_CH_INT interrupt. + */ + uint32_t infifo_ovf_chn_int_st:1; + /** infifo_udf_chn_int_st : RO; bitpos: [6]; default: 0; + * The raw interrupt status bit for the INFIFO_UDF_L1_CH_INT interrupt. + */ + uint32_t infifo_udf_chn_int_st:1; + uint32_t reserved_7:25; + }; + uint32_t val; +} gdma_in_int_st_chn_reg_t; + +/** Type of in_int_ena_chn register + * Interrupt enable bits of channel n. + */ +typedef union { + struct { + /** in_done_chn_int_ena : R/W; bitpos: [0]; default: 0; + * The interrupt enable bit for the IN_DONE_CH_INT interrupt. + */ + uint32_t in_done_chn_int_ena:1; + /** in_suc_eof_chn_int_ena : R/W; bitpos: [1]; default: 0; + * The interrupt enable bit for the IN_SUC_EOF_CH_INT interrupt. + */ + uint32_t in_suc_eof_chn_int_ena:1; + /** in_err_eof_chn_int_ena : R/W; bitpos: [2]; default: 0; + * The interrupt enable bit for the IN_ERR_EOF_CH_INT interrupt. + */ + uint32_t in_err_eof_chn_int_ena:1; + /** in_dscr_err_chn_int_ena : R/W; bitpos: [3]; default: 0; + * The interrupt enable bit for the IN_DSCR_ERR_CH_INT interrupt. + */ + uint32_t in_dscr_err_chn_int_ena:1; + /** in_dscr_empty_chn_int_ena : R/W; bitpos: [4]; default: 0; + * The interrupt enable bit for the IN_DSCR_EMPTY_CH_INT interrupt. + */ + uint32_t in_dscr_empty_chn_int_ena:1; + /** infifo_ovf_chn_int_ena : R/W; bitpos: [5]; default: 0; + * The interrupt enable bit for the INFIFO_OVF_L1_CH_INT interrupt. + */ + uint32_t infifo_ovf_chn_int_ena:1; + /** infifo_udf_chn_int_ena : R/W; bitpos: [6]; default: 0; + * The interrupt enable bit for the INFIFO_UDF_L1_CH_INT interrupt. + */ + uint32_t infifo_udf_chn_int_ena:1; + uint32_t reserved_7:25; + }; + uint32_t val; +} gdma_in_int_ena_chn_reg_t; + +/** Type of in_int_clr_chn register + * Interrupt clear bits of channel n. + */ +typedef union { + struct { + /** in_done_chn_int_clr : WT; bitpos: [0]; default: 0; + * Set this bit to clear the IN_DONE_CH_INT interrupt. + */ + uint32_t in_done_chn_int_clr:1; + /** in_suc_eof_chn_int_clr : WT; bitpos: [1]; default: 0; + * Set this bit to clear the IN_SUC_EOF_CH_INT interrupt. + */ + uint32_t in_suc_eof_chn_int_clr:1; + /** in_err_eof_chn_int_clr : WT; bitpos: [2]; default: 0; + * Set this bit to clear the IN_ERR_EOF_CH_INT interrupt. + */ + uint32_t in_err_eof_chn_int_clr:1; + /** in_dscr_err_chn_int_clr : WT; bitpos: [3]; default: 0; + * Set this bit to clear the IN_DSCR_ERR_CH_INT interrupt. + */ + uint32_t in_dscr_err_chn_int_clr:1; + /** in_dscr_empty_chn_int_clr : WT; bitpos: [4]; default: 0; + * Set this bit to clear the IN_DSCR_EMPTY_CH_INT interrupt. + */ + uint32_t in_dscr_empty_chn_int_clr:1; + /** infifo_ovf_chn_int_clr : WT; bitpos: [5]; default: 0; + * Set this bit to clear the INFIFO_OVF_L1_CH_INT interrupt. + */ + uint32_t infifo_ovf_chn_int_clr:1; + /** infifo_udf_chn_int_clr : WT; bitpos: [6]; default: 0; + * Set this bit to clear the INFIFO_UDF_L1_CH_INT interrupt. + */ + uint32_t infifo_udf_chn_int_clr:1; + uint32_t reserved_7:25; + }; + uint32_t val; +} gdma_in_int_clr_chn_reg_t; + +/** Type of out_int_raw_chn register + * Raw status interrupt of channel n. + */ +typedef union { + struct { + /** out_done_chn_int_raw : R/WTC/SS; bitpos: [0]; default: 0; + * The raw interrupt bit turns to high level when the last data pointed by one outlink + * descriptor has been transmitted to peripherals for Tx channel n. + */ + uint32_t out_done_chn_int_raw:1; + /** out_eof_chn_int_raw : R/WTC/SS; bitpos: [1]; default: 0; + * The raw interrupt bit turns to high level when the last data pointed by one outlink + * descriptor has been read from memory for Tx channel n. + */ + uint32_t out_eof_chn_int_raw:1; + /** out_dscr_err_chn_int_raw : R/WTC/SS; bitpos: [2]; default: 0; + * The raw interrupt bit turns to high level when detecting outlink descriptor error + * including owner error and the second and third word error of outlink descriptor for + * Tx channel n. + */ + uint32_t out_dscr_err_chn_int_raw:1; + /** out_total_eof_chn_int_raw : R/WTC/SS; bitpos: [3]; default: 0; + * The raw interrupt bit turns to high level when data corresponding a outlink + * (includes one link descriptor or few link descriptors) is transmitted out for Tx + * channel n. + */ + uint32_t out_total_eof_chn_int_raw:1; + /** outfifo_ovf_chn_int_raw : R/WTC/SS; bitpos: [4]; default: 0; + * This raw interrupt bit turns to high level when level 1 fifo of Tx channel n is + * overflow. + */ + uint32_t outfifo_ovf_chn_int_raw:1; + /** outfifo_udf_chn_int_raw : R/WTC/SS; bitpos: [5]; default: 0; + * This raw interrupt bit turns to high level when level 1 fifo of Tx channel n is + * underflow. + */ + uint32_t outfifo_udf_chn_int_raw:1; + uint32_t reserved_6:26; + }; + uint32_t val; +} gdma_out_int_raw_chn_reg_t; + +/** Type of out_int_st_chn register + * Masked interrupt of channel n. + */ +typedef union { + struct { + /** out_done_chn_int_st : RO; bitpos: [0]; default: 0; + * The raw interrupt status bit for the OUT_DONE_CH_INT interrupt. + */ + uint32_t out_done_chn_int_st:1; + /** out_eof_chn_int_st : RO; bitpos: [1]; default: 0; + * The raw interrupt status bit for the OUT_EOF_CH_INT interrupt. + */ + uint32_t out_eof_chn_int_st:1; + /** out_dscr_err_chn_int_st : RO; bitpos: [2]; default: 0; + * The raw interrupt status bit for the OUT_DSCR_ERR_CH_INT interrupt. + */ + uint32_t out_dscr_err_chn_int_st:1; + /** out_total_eof_chn_int_st : RO; bitpos: [3]; default: 0; + * The raw interrupt status bit for the OUT_TOTAL_EOF_CH_INT interrupt. + */ + uint32_t out_total_eof_chn_int_st:1; + /** outfifo_ovf_chn_int_st : RO; bitpos: [4]; default: 0; + * The raw interrupt status bit for the OUTFIFO_OVF_L1_CH_INT interrupt. + */ + uint32_t outfifo_ovf_chn_int_st:1; + /** outfifo_udf_chn_int_st : RO; bitpos: [5]; default: 0; + * The raw interrupt status bit for the OUTFIFO_UDF_L1_CH_INT interrupt. + */ + uint32_t outfifo_udf_chn_int_st:1; + uint32_t reserved_6:26; + }; + uint32_t val; +} gdma_out_int_st_chn_reg_t; + +/** Type of out_int_ena_chn register + * Interrupt enable bits of channel n. + */ +typedef union { + struct { + /** out_done_chn_int_ena : R/W; bitpos: [0]; default: 0; + * The interrupt enable bit for the OUT_DONE_CH_INT interrupt. + */ + uint32_t out_done_chn_int_ena:1; + /** out_eof_chn_int_ena : R/W; bitpos: [1]; default: 0; + * The interrupt enable bit for the OUT_EOF_CH_INT interrupt. + */ + uint32_t out_eof_chn_int_ena:1; + /** out_dscr_err_chn_int_ena : R/W; bitpos: [2]; default: 0; + * The interrupt enable bit for the OUT_DSCR_ERR_CH_INT interrupt. + */ + uint32_t out_dscr_err_chn_int_ena:1; + /** out_total_eof_chn_int_ena : R/W; bitpos: [3]; default: 0; + * The interrupt enable bit for the OUT_TOTAL_EOF_CH_INT interrupt. + */ + uint32_t out_total_eof_chn_int_ena:1; + /** outfifo_ovf_chn_int_ena : R/W; bitpos: [4]; default: 0; + * The interrupt enable bit for the OUTFIFO_OVF_L1_CH_INT interrupt. + */ + uint32_t outfifo_ovf_chn_int_ena:1; + /** outfifo_udf_chn_int_ena : R/W; bitpos: [5]; default: 0; + * The interrupt enable bit for the OUTFIFO_UDF_L1_CH_INT interrupt. + */ + uint32_t outfifo_udf_chn_int_ena:1; + uint32_t reserved_6:26; + }; + uint32_t val; +} gdma_out_int_ena_chn_reg_t; + +/** Type of out_int_clr_chn register + * Interrupt clear bits of channel n. + */ +typedef union { + struct { + /** out_done_chn_int_clr : WT; bitpos: [0]; default: 0; + * Set this bit to clear the OUT_DONE_CH_INT interrupt. + */ + uint32_t out_done_chn_int_clr:1; + /** out_eof_chn_int_clr : WT; bitpos: [1]; default: 0; + * Set this bit to clear the OUT_EOF_CH_INT interrupt. + */ + uint32_t out_eof_chn_int_clr:1; + /** out_dscr_err_chn_int_clr : WT; bitpos: [2]; default: 0; + * Set this bit to clear the OUT_DSCR_ERR_CH_INT interrupt. + */ + uint32_t out_dscr_err_chn_int_clr:1; + /** out_total_eof_chn_int_clr : WT; bitpos: [3]; default: 0; + * Set this bit to clear the OUT_TOTAL_EOF_CH_INT interrupt. + */ + uint32_t out_total_eof_chn_int_clr:1; + /** outfifo_ovf_chn_int_clr : WT; bitpos: [4]; default: 0; + * Set this bit to clear the OUTFIFO_OVF_L1_CH_INT interrupt. + */ + uint32_t outfifo_ovf_chn_int_clr:1; + /** outfifo_udf_chn_int_clr : WT; bitpos: [5]; default: 0; + * Set this bit to clear the OUTFIFO_UDF_L1_CH_INT interrupt. + */ + uint32_t outfifo_udf_chn_int_clr:1; + uint32_t reserved_6:26; + }; + uint32_t val; +} gdma_out_int_clr_chn_reg_t; + + +/** Group: Debug Registers */ +/** Type of ahb_test register + * reserved + */ +typedef union { + struct { + /** ahb_testmode : R/W; bitpos: [2:0]; default: 0; + * reserved + */ + uint32_t ahb_testmode:3; + uint32_t reserved_3:1; + /** ahb_testaddr : R/W; bitpos: [5:4]; default: 0; + * reserved + */ + uint32_t ahb_testaddr:2; + uint32_t reserved_6:26; + }; + uint32_t val; +} gdma_ahb_test_reg_t; + + +/** Group: Configuration Registers */ +/** Type of misc_conf register + * MISC register + */ +typedef union { + struct { + /** ahbm_rst_inter : R/W; bitpos: [0]; default: 0; + * Set this bit then clear this bit to reset the internal ahb FSM. + */ + uint32_t ahbm_rst_inter:1; + uint32_t reserved_1:1; + /** arb_pri_dis : R/W; bitpos: [2]; default: 0; + * Set this bit to disable priority arbitration function. + */ + uint32_t arb_pri_dis:1; + /** clk_en : R/W; bitpos: [3]; default: 0; + * 1'h1: Force clock on for register. 1'h0: Support clock only when application writes + * registers. + */ + uint32_t clk_en:1; + uint32_t reserved_4:28; + }; + uint32_t val; +} gdma_misc_conf_reg_t; + +/** Type of in_conf0_chn register + * Configure 0 register of Rx channel n. + */ +typedef union { + struct { + /** in_rst_chn : R/W; bitpos: [0]; default: 0; + * This bit is used to reset DMA channel n Rx FSM and Rx FIFO pointer. + */ + uint32_t in_rst_chn:1; + /** in_loop_test_chn : R/W; bitpos: [1]; default: 0; + * reserved + */ + uint32_t in_loop_test_chn:1; + /** indscr_burst_en_chn : R/W; bitpos: [2]; default: 0; + * Set this bit to 1 to enable INCR burst transfer for Rx channel n reading link + * descriptor when accessing internal SRAM. + */ + uint32_t indscr_burst_en_chn:1; + /** in_data_burst_en_chn : R/W; bitpos: [3]; default: 0; + * Set this bit to 1 to enable INCR burst transfer for Rx channel n receiving data + * when accessing internal SRAM. + */ + uint32_t in_data_burst_en_chn:1; + /** mem_trans_en_chn : R/W; bitpos: [4]; default: 0; + * Set this bit 1 to enable automatic transmitting data from memory to memory via DMA. + */ + uint32_t mem_trans_en_chn:1; + /** in_etm_en_chn : R/W; bitpos: [5]; default: 0; + * Set this bit to 1 to enable etm control mode, dma Rx channel n is triggered by etm + * task. + */ + uint32_t in_etm_en_chn:1; + uint32_t reserved_6:26; + }; + uint32_t val; +} gdma_in_conf0_chn_reg_t; + +/** Type of in_conf1_chn register + * Configure 1 register of Rx channel n. + */ +typedef union { + struct { + uint32_t reserved_0:12; + /** in_check_owner_chn : R/W; bitpos: [12]; default: 0; + * Set this bit to enable checking the owner attribute of the link descriptor. + */ + uint32_t in_check_owner_chn:1; + uint32_t reserved_13:19; + }; + uint32_t val; +} gdma_in_conf1_chn_reg_t; + +/** Type of in_pop_chn register + * Pop control register of Rx channel n. + */ +typedef union { + struct { + /** infifo_rdata_chn : RO; bitpos: [11:0]; default: 2048; + * This register stores the data popping from DMA FIFO. + */ + uint32_t infifo_rdata_chn:12; + /** infifo_pop_chn : WT; bitpos: [12]; default: 0; + * Set this bit to pop data from DMA FIFO. + */ + uint32_t infifo_pop_chn:1; + uint32_t reserved_13:19; + }; + uint32_t val; +} gdma_in_pop_chn_reg_t; + +/** Type of in_link_chn register + * Link descriptor configure and control register of Rx channel n. + */ +typedef union { + struct { + /** inlink_addr_chn : R/W; bitpos: [19:0]; default: 0; + * This register stores the 20 least significant bits of the first inlink descriptor's + * address. + */ + uint32_t inlink_addr_chn:20; + /** inlink_auto_ret_chn : R/W; bitpos: [20]; default: 1; + * Set this bit to return to current inlink descriptor's address when there are some + * errors in current receiving data. + */ + uint32_t inlink_auto_ret_chn:1; + /** inlink_stop_chn : WT; bitpos: [21]; default: 0; + * Set this bit to stop dealing with the inlink descriptors. + */ + uint32_t inlink_stop_chn:1; + /** inlink_start_chn : WT; bitpos: [22]; default: 0; + * Set this bit to start dealing with the inlink descriptors. + */ + uint32_t inlink_start_chn:1; + /** inlink_restart_chn : WT; bitpos: [23]; default: 0; + * Set this bit to mount a new inlink descriptor. + */ + uint32_t inlink_restart_chn:1; + /** inlink_park_chn : RO; bitpos: [24]; default: 1; + * 1: the inlink descriptor's FSM is in idle state. 0: the inlink descriptor's FSM is + * working. + */ + uint32_t inlink_park_chn:1; + uint32_t reserved_25:7; + }; + uint32_t val; +} gdma_in_link_chn_reg_t; + +/** Type of out_conf0_ch0 register + * Configure 0 register of Tx channel 0. + */ +typedef union { + struct { + /** out_rst_ch0 : R/W; bitpos: [0]; default: 0; + * This bit is used to reset DMA channel 0 Tx FSM and Tx FIFO pointer. + */ + uint32_t out_rst_ch0:1; + /** out_loop_test_ch0 : R/W; bitpos: [1]; default: 0; + * reserved + */ + uint32_t out_loop_test_ch0:1; + /** out_auto_wrback_ch0 : R/W; bitpos: [2]; default: 0; + * Set this bit to enable automatic outlink-writeback when all the data in tx buffer + * has been transmitted. + */ + uint32_t out_auto_wrback_ch0:1; + /** out_eof_mode_ch0 : R/W; bitpos: [3]; default: 1; + * EOF flag generation mode when transmitting data. 1: EOF flag for Tx channel 0 is + * generated when data need to transmit has been popped from FIFO in DMA + */ + uint32_t out_eof_mode_ch0:1; + /** outdscr_burst_en_ch0 : R/W; bitpos: [4]; default: 0; + * Set this bit to 1 to enable INCR burst transfer for Tx channel 0 reading link + * descriptor when accessing internal SRAM. + */ + uint32_t outdscr_burst_en_ch0:1; + /** out_data_burst_en_ch0 : R/W; bitpos: [5]; default: 0; + * Set this bit to 1 to enable INCR burst transfer for Tx channel 0 transmitting data + * when accessing internal SRAM. + */ + uint32_t out_data_burst_en_ch0:1; + /** out_etm_en_ch0 : R/W; bitpos: [6]; default: 0; + * Set this bit to 1 to enable etm control mode, dma Tx channel 0 is triggered by etm + * task. + */ + uint32_t out_etm_en_ch0:1; + uint32_t reserved_7:25; + }; + uint32_t val; +} gdma_out_conf0_ch0_reg_t; + +/** Type of out_conf1_chn register + * Configure 1 register of Tx channel n. + */ +typedef union { + struct { + uint32_t reserved_0:12; + /** out_check_owner_chn : R/W; bitpos: [12]; default: 0; + * Set this bit to enable checking the owner attribute of the link descriptor. + */ + uint32_t out_check_owner_chn:1; + uint32_t reserved_13:19; + }; + uint32_t val; +} gdma_out_conf1_chn_reg_t; + +/** Type of out_push_chn register + * Push control register of Rx channel n. + */ +typedef union { + struct { + /** outfifo_wdata_chn : R/W; bitpos: [8:0]; default: 0; + * This register stores the data that need to be pushed into DMA FIFO. + */ + uint32_t outfifo_wdata_chn:9; + /** outfifo_push_chn : WT; bitpos: [9]; default: 0; + * Set this bit to push data into DMA FIFO. + */ + uint32_t outfifo_push_chn:1; + uint32_t reserved_10:22; + }; + uint32_t val; +} gdma_out_push_chn_reg_t; + +/** Type of out_link_chn register + * Link descriptor configure and control register of Tx channel n. + */ +typedef union { + struct { + /** outlink_addr_chn : R/W; bitpos: [19:0]; default: 0; + * This register stores the 20 least significant bits of the first outlink + * descriptor's address. + */ + uint32_t outlink_addr_chn:20; + /** outlink_stop_chn : WT; bitpos: [20]; default: 0; + * Set this bit to stop dealing with the outlink descriptors. + */ + uint32_t outlink_stop_chn:1; + /** outlink_start_chn : WT; bitpos: [21]; default: 0; + * Set this bit to start dealing with the outlink descriptors. + */ + uint32_t outlink_start_chn:1; + /** outlink_restart_chn : WT; bitpos: [22]; default: 0; + * Set this bit to restart a new outlink from the last address. + */ + uint32_t outlink_restart_chn:1; + /** outlink_park_chn : RO; bitpos: [23]; default: 1; + * 1: the outlink descriptor's FSM is in idle state. 0: the outlink descriptor's FSM + * is working. + */ + uint32_t outlink_park_chn:1; + uint32_t reserved_24:8; + }; + uint32_t val; +} gdma_out_link_chn_reg_t; + +/** Type of out_conf0_chn register + * Configure 0 register of Tx channel n. + */ +typedef union { + struct { + /** out_rst_chn : R/W; bitpos: [0]; default: 0; + * This bit is used to reset DMA channel n Tx FSM and Tx FIFO pointer. + */ + uint32_t out_rst_chn:1; + /** out_loop_test_chn : R/W; bitpos: [1]; default: 0; + * reserved + */ + uint32_t out_loop_test_chn:1; + /** out_auto_wrback_chn : R/W; bitpos: [2]; default: 0; + * Set this bit to enable automatic outlink-writeback when all the data in tx buffer + * has been transmitted. + */ + uint32_t out_auto_wrback_chn:1; + /** out_eof_mode_chn : R/W; bitpos: [3]; default: 1; + * EOF flag generation mode when transmitting data. 1: EOF flag for Tx channel n is + * generated when data need to transmit has been popped from FIFO in DMA + */ + uint32_t out_eof_mode_chn:1; + /** outdscr_burst_en_chn : R/W; bitpos: [4]; default: 0; + * Set this bit to 1 to enable INCR burst transfer for Tx channel n reading link + * descriptor when accessing internal SRAM. + */ + uint32_t outdscr_burst_en_chn:1; + /** out_data_burst_en_chn : R/W; bitpos: [5]; default: 0; + * Set this bit to 1 to enable INCR burst transfer for Tx channel n transmitting data + * when accessing internal SRAM. + */ + uint32_t out_data_burst_en_chn:1; + /** out_etm_en_chn : R/W; bitpos: [6]; default: 0; + * Set this bit to 1 to enable etm control mode, dma Tx channel n is triggered by etm + * task. + */ + uint32_t out_etm_en_chn:1; + uint32_t reserved_7:25; + }; + uint32_t val; +} gdma_out_conf0_chn_reg_t; + + +/** Group: Version Registers */ +/** Type of date register + * Version control register + */ +typedef union { + struct { + /** date : R/W; bitpos: [31:0]; default: 35660368; + * register version. + */ + uint32_t date:32; + }; + uint32_t val; +} gdma_date_reg_t; + + +/** Group: Status Registers */ +/** Type of infifo_status_chn register + * Receive FIFO status of Rx channel n. + */ +typedef union { + struct { + /** infifo_full_chn : RO; bitpos: [0]; default: 1; + * L1 Rx FIFO full signal for Rx channel n. + */ + uint32_t infifo_full_chn:1; + /** infifo_empty_chn : RO; bitpos: [1]; default: 1; + * L1 Rx FIFO empty signal for Rx channel n. + */ + uint32_t infifo_empty_chn:1; + /** infifo_cnt_chn : RO; bitpos: [7:2]; default: 0; + * The register stores the byte number of the data in L1 Rx FIFO for Rx channel n. + */ + uint32_t infifo_cnt_chn:6; + uint32_t reserved_8:15; + /** in_remain_under_1b_chn : RO; bitpos: [23]; default: 1; + * reserved + */ + uint32_t in_remain_under_1b_chn:1; + /** in_remain_under_2b_chn : RO; bitpos: [24]; default: 1; + * reserved + */ + uint32_t in_remain_under_2b_chn:1; + /** in_remain_under_3b_chn : RO; bitpos: [25]; default: 1; + * reserved + */ + uint32_t in_remain_under_3b_chn:1; + /** in_remain_under_4b_chn : RO; bitpos: [26]; default: 1; + * reserved + */ + uint32_t in_remain_under_4b_chn:1; + /** in_buf_hungry_chn : RO; bitpos: [27]; default: 0; + * reserved + */ + uint32_t in_buf_hungry_chn:1; + uint32_t reserved_28:4; + }; + uint32_t val; +} gdma_infifo_status_chn_reg_t; + +/** Type of in_state_chn register + * Receive status of Rx channel n. + */ +typedef union { + struct { + /** inlink_dscr_addr_chn : RO; bitpos: [17:0]; default: 0; + * This register stores the current inlink descriptor's address. + */ + uint32_t inlink_dscr_addr_chn:18; + /** in_dscr_state_chn : RO; bitpos: [19:18]; default: 0; + * reserved + */ + uint32_t in_dscr_state_chn:2; + /** in_state_chn : RO; bitpos: [22:20]; default: 0; + * reserved + */ + uint32_t in_state_chn:3; + uint32_t reserved_23:9; + }; + uint32_t val; +} gdma_in_state_chn_reg_t; + +/** Type of in_suc_eof_des_addr_chn register + * Inlink descriptor address when EOF occurs of Rx channel n. + */ +typedef union { + struct { + /** in_suc_eof_des_addr_chn : RO; bitpos: [31:0]; default: 0; + * This register stores the address of the inlink descriptor when the EOF bit in this + * descriptor is 1. + */ + uint32_t in_suc_eof_des_addr_chn:32; + }; + uint32_t val; +} gdma_in_suc_eof_des_addr_chn_reg_t; + +/** Type of in_err_eof_des_addr_chn register + * Inlink descriptor address when errors occur of Rx channel n. + */ +typedef union { + struct { + /** in_err_eof_des_addr_chn : RO; bitpos: [31:0]; default: 0; + * This register stores the address of the inlink descriptor when there are some + * errors in current receiving data. Only used when peripheral is UHCI0. + */ + uint32_t in_err_eof_des_addr_chn:32; + }; + uint32_t val; +} gdma_in_err_eof_des_addr_chn_reg_t; + +/** Type of in_dscr_chn register + * Current inlink descriptor address of Rx channel n. + */ +typedef union { + struct { + /** inlink_dscr_chn : RO; bitpos: [31:0]; default: 0; + * The address of the current inlink descriptor x. + */ + uint32_t inlink_dscr_chn:32; + }; + uint32_t val; +} gdma_in_dscr_chn_reg_t; + +/** Type of in_dscr_bf0_chn register + * The last inlink descriptor address of Rx channel n. + */ +typedef union { + struct { + /** inlink_dscr_bf0_chn : RO; bitpos: [31:0]; default: 0; + * The address of the last inlink descriptor x-1. + */ + uint32_t inlink_dscr_bf0_chn:32; + }; + uint32_t val; +} gdma_in_dscr_bf0_chn_reg_t; + +/** Type of in_dscr_bf1_chn register + * The second-to-last inlink descriptor address of Rx channel n. + */ +typedef union { + struct { + /** inlink_dscr_bf1_chn : RO; bitpos: [31:0]; default: 0; + * The address of the second-to-last inlink descriptor x-2. + */ + uint32_t inlink_dscr_bf1_chn:32; + }; + uint32_t val; +} gdma_in_dscr_bf1_chn_reg_t; + +/** Type of outfifo_status_chn register + * Transmit FIFO status of Tx channel n. + */ +typedef union { + struct { + /** outfifo_full_chn : RO; bitpos: [0]; default: 0; + * L1 Tx FIFO full signal for Tx channel n. + */ + uint32_t outfifo_full_chn:1; + /** outfifo_empty_chn : RO; bitpos: [1]; default: 1; + * L1 Tx FIFO empty signal for Tx channel n. + */ + uint32_t outfifo_empty_chn:1; + /** outfifo_cnt_chn : RO; bitpos: [7:2]; default: 0; + * The register stores the byte number of the data in L1 Tx FIFO for Tx channel n. + */ + uint32_t outfifo_cnt_chn:6; + uint32_t reserved_8:15; + /** out_remain_under_1b_chn : RO; bitpos: [23]; default: 1; + * reserved + */ + uint32_t out_remain_under_1b_chn:1; + /** out_remain_under_2b_chn : RO; bitpos: [24]; default: 1; + * reserved + */ + uint32_t out_remain_under_2b_chn:1; + /** out_remain_under_3b_chn : RO; bitpos: [25]; default: 1; + * reserved + */ + uint32_t out_remain_under_3b_chn:1; + /** out_remain_under_4b_chn : RO; bitpos: [26]; default: 1; + * reserved + */ + uint32_t out_remain_under_4b_chn:1; + uint32_t reserved_27:5; + }; + uint32_t val; +} gdma_outfifo_status_chn_reg_t; + +/** Type of out_state_chn register + * Transmit status of Tx channel n. + */ +typedef union { + struct { + /** outlink_dscr_addr_chn : RO; bitpos: [17:0]; default: 0; + * This register stores the current outlink descriptor's address. + */ + uint32_t outlink_dscr_addr_chn:18; + /** out_dscr_state_chn : RO; bitpos: [19:18]; default: 0; + * reserved + */ + uint32_t out_dscr_state_chn:2; + /** out_state_chn : RO; bitpos: [22:20]; default: 0; + * reserved + */ + uint32_t out_state_chn:3; + uint32_t reserved_23:9; + }; + uint32_t val; +} gdma_out_state_chn_reg_t; + +/** Type of out_eof_des_addr_chn register + * Outlink descriptor address when EOF occurs of Tx channel n. + */ +typedef union { + struct { + /** out_eof_des_addr_chn : RO; bitpos: [31:0]; default: 0; + * This register stores the address of the outlink descriptor when the EOF bit in this + * descriptor is 1. + */ + uint32_t out_eof_des_addr_chn:32; + }; + uint32_t val; +} gdma_out_eof_des_addr_chn_reg_t; + +/** Type of out_eof_bfr_des_addr_chn register + * The last outlink descriptor address when EOF occurs of Tx channel n. + */ +typedef union { + struct { + /** out_eof_bfr_des_addr_chn : RO; bitpos: [31:0]; default: 0; + * This register stores the address of the outlink descriptor before the last outlink + * descriptor. + */ + uint32_t out_eof_bfr_des_addr_chn:32; + }; + uint32_t val; +} gdma_out_eof_bfr_des_addr_chn_reg_t; + +/** Type of out_dscr_chn register + * Current inlink descriptor address of Tx channel n. + */ +typedef union { + struct { + /** outlink_dscr_chn : RO; bitpos: [31:0]; default: 0; + * The address of the current outlink descriptor y. + */ + uint32_t outlink_dscr_chn:32; + }; + uint32_t val; +} gdma_out_dscr_chn_reg_t; + +/** Type of out_dscr_bf0_chn register + * The last inlink descriptor address of Tx channel n. + */ +typedef union { + struct { + /** outlink_dscr_bf0_chn : RO; bitpos: [31:0]; default: 0; + * The address of the last outlink descriptor y-1. + */ + uint32_t outlink_dscr_bf0_chn:32; + }; + uint32_t val; +} gdma_out_dscr_bf0_chn_reg_t; + +/** Type of out_dscr_bf1_chn register + * The second-to-last inlink descriptor address of Tx channel n. + */ +typedef union { + struct { + /** outlink_dscr_bf1_chn : RO; bitpos: [31:0]; default: 0; + * The address of the second-to-last inlink descriptor x-2. + */ + uint32_t outlink_dscr_bf1_chn:32; + }; + uint32_t val; +} gdma_out_dscr_bf1_chn_reg_t; + + +/** Group: Priority Registers */ +/** Type of in_pri_chn register + * Priority register of Rx channel n. + */ +typedef union { + struct { + /** rx_pri_chn : R/W; bitpos: [3:0]; default: 0; + * The priority of Rx channel n. The larger of the value the higher of the priority. + */ + uint32_t rx_pri_chn:4; + uint32_t reserved_4:28; + }; + uint32_t val; +} gdma_in_pri_chn_reg_t; + +/** Type of out_pri_chn register + * Priority register of Tx channel n. + */ +typedef union { + struct { + /** tx_pri_chn : R/W; bitpos: [3:0]; default: 0; + * The priority of Tx channel n. The larger of the value the higher of the priority. + */ + uint32_t tx_pri_chn:4; + uint32_t reserved_4:28; + }; + uint32_t val; +} gdma_out_pri_chn_reg_t; + + +/** Group: Peripheral Select Registers */ +/** Type of in_peri_sel_chn register + * Peripheral selection of Rx channel n. + */ +typedef union { + struct { + /** peri_in_sel_chn : R/W; bitpos: [5:0]; default: 63; + * This register is used to select peripheral for Rx channel n. 0:SPI2. 1: Dummy. 2: + * UHCI0. 3: I2S0. 4: Dummy. 5: Dummy. 6: AES. 7: SHA. 8: ADC_DAC. 9: Parallel_IO. + * 10~15: Dummy + */ + uint32_t peri_in_sel_chn:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} gdma_in_peri_sel_chn_reg_t; + +/** Type of out_peri_sel_chn register + * Peripheral selection of Tx channel n. + */ +typedef union { + struct { + /** peri_out_sel_chn : R/W; bitpos: [5:0]; default: 63; + * This register is used to select peripheral for Tx channel n. 0:SPI2. 1: Dummy. 2: + * UHCI0. 3: I2S0. 4: Dummy. 5: Dummy. 6: AES. 7: SHA. 8: ADC_DAC. 9: Parallel_IO. + * 10~15: Dummy + */ + uint32_t peri_out_sel_chn:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} gdma_out_peri_sel_chn_reg_t; + + +typedef struct { + volatile gdma_in_int_raw_chn_reg_t in_int_raw_ch0; + volatile gdma_in_int_st_chn_reg_t in_int_st_ch0; + volatile gdma_in_int_ena_chn_reg_t in_int_ena_ch0; + volatile gdma_in_int_clr_chn_reg_t in_int_clr_ch0; + volatile gdma_in_int_raw_chn_reg_t in_int_raw_ch1; + volatile gdma_in_int_st_chn_reg_t in_int_st_ch1; + volatile gdma_in_int_ena_chn_reg_t in_int_ena_ch1; + volatile gdma_in_int_clr_chn_reg_t in_int_clr_ch1; + volatile gdma_in_int_raw_chn_reg_t in_int_raw_ch2; + volatile gdma_in_int_st_chn_reg_t in_int_st_ch2; + volatile gdma_in_int_ena_chn_reg_t in_int_ena_ch2; + volatile gdma_in_int_clr_chn_reg_t in_int_clr_ch2; + volatile gdma_out_int_raw_chn_reg_t out_int_raw_ch0; + volatile gdma_out_int_st_chn_reg_t out_int_st_ch0; + volatile gdma_out_int_ena_chn_reg_t out_int_ena_ch0; + volatile gdma_out_int_clr_chn_reg_t out_int_clr_ch0; + volatile gdma_out_int_raw_chn_reg_t out_int_raw_ch1; + volatile gdma_out_int_st_chn_reg_t out_int_st_ch1; + volatile gdma_out_int_ena_chn_reg_t out_int_ena_ch1; + volatile gdma_out_int_clr_chn_reg_t out_int_clr_ch1; + volatile gdma_out_int_raw_chn_reg_t out_int_raw_ch2; + volatile gdma_out_int_st_chn_reg_t out_int_st_ch2; + volatile gdma_out_int_ena_chn_reg_t out_int_ena_ch2; + volatile gdma_out_int_clr_chn_reg_t out_int_clr_ch2; + volatile gdma_ahb_test_reg_t ahb_test; + volatile gdma_misc_conf_reg_t misc_conf; + volatile gdma_date_reg_t date; + uint32_t reserved_06c; + volatile gdma_in_conf0_chn_reg_t in_conf0_ch0; + volatile gdma_in_conf1_chn_reg_t in_conf1_ch0; + volatile gdma_infifo_status_chn_reg_t infifo_status_ch0; + volatile gdma_in_pop_chn_reg_t in_pop_ch0; + volatile gdma_in_link_chn_reg_t in_link_ch0; + volatile gdma_in_state_chn_reg_t in_state_ch0; + volatile gdma_in_suc_eof_des_addr_chn_reg_t in_suc_eof_des_addr_ch0; + volatile gdma_in_err_eof_des_addr_chn_reg_t in_err_eof_des_addr_ch0; + volatile gdma_in_dscr_chn_reg_t in_dscr_ch0; + volatile gdma_in_dscr_bf0_chn_reg_t in_dscr_bf0_ch0; + volatile gdma_in_dscr_bf1_chn_reg_t in_dscr_bf1_ch0; + volatile gdma_in_pri_chn_reg_t in_pri_ch0; + volatile gdma_in_peri_sel_chn_reg_t in_peri_sel_ch0; + uint32_t reserved_0a4[11]; + volatile gdma_out_conf0_ch0_reg_t out_conf0_ch0; + volatile gdma_out_conf1_chn_reg_t out_conf1_ch0; + volatile gdma_outfifo_status_chn_reg_t outfifo_status_ch0; + volatile gdma_out_push_chn_reg_t out_push_ch0; + volatile gdma_out_link_chn_reg_t out_link_ch0; + volatile gdma_out_state_chn_reg_t out_state_ch0; + volatile gdma_out_eof_des_addr_chn_reg_t out_eof_des_addr_ch0; + volatile gdma_out_eof_bfr_des_addr_chn_reg_t out_eof_bfr_des_addr_ch0; + volatile gdma_out_dscr_chn_reg_t out_dscr_ch0; + volatile gdma_out_dscr_bf0_chn_reg_t out_dscr_bf0_ch0; + volatile gdma_out_dscr_bf1_chn_reg_t out_dscr_bf1_ch0; + volatile gdma_out_pri_chn_reg_t out_pri_ch0; + volatile gdma_out_peri_sel_chn_reg_t out_peri_sel_ch0; + uint32_t reserved_104[11]; + volatile gdma_in_conf0_chn_reg_t in_conf0_ch1; + volatile gdma_in_conf1_chn_reg_t in_conf1_ch1; + volatile gdma_infifo_status_chn_reg_t infifo_status_ch1; + volatile gdma_in_pop_chn_reg_t in_pop_ch1; + volatile gdma_in_link_chn_reg_t in_link_ch1; + volatile gdma_in_state_chn_reg_t in_state_ch1; + volatile gdma_in_suc_eof_des_addr_chn_reg_t in_suc_eof_des_addr_ch1; + volatile gdma_in_err_eof_des_addr_chn_reg_t in_err_eof_des_addr_ch1; + volatile gdma_in_dscr_chn_reg_t in_dscr_ch1; + volatile gdma_in_dscr_bf0_chn_reg_t in_dscr_bf0_ch1; + volatile gdma_in_dscr_bf1_chn_reg_t in_dscr_bf1_ch1; + volatile gdma_in_pri_chn_reg_t in_pri_ch1; + volatile gdma_in_peri_sel_chn_reg_t in_peri_sel_ch1; + uint32_t reserved_164[11]; + volatile gdma_out_conf0_chn_reg_t out_conf0_ch1; + volatile gdma_out_conf1_chn_reg_t out_conf1_ch1; + volatile gdma_outfifo_status_chn_reg_t outfifo_status_ch1; + volatile gdma_out_push_chn_reg_t out_push_ch1; + volatile gdma_out_link_chn_reg_t out_link_ch1; + volatile gdma_out_state_chn_reg_t out_state_ch1; + volatile gdma_out_eof_des_addr_chn_reg_t out_eof_des_addr_ch1; + volatile gdma_out_eof_bfr_des_addr_chn_reg_t out_eof_bfr_des_addr_ch1; + volatile gdma_out_dscr_chn_reg_t out_dscr_ch1; + volatile gdma_out_dscr_bf0_chn_reg_t out_dscr_bf0_ch1; + volatile gdma_out_dscr_bf1_chn_reg_t out_dscr_bf1_ch1; + volatile gdma_out_pri_chn_reg_t out_pri_ch1; + volatile gdma_out_peri_sel_chn_reg_t out_peri_sel_ch1; + uint32_t reserved_1c4[11]; + volatile gdma_in_conf0_chn_reg_t in_conf0_ch2; + volatile gdma_in_conf1_chn_reg_t in_conf1_ch2; + volatile gdma_infifo_status_chn_reg_t infifo_status_ch2; + volatile gdma_in_pop_chn_reg_t in_pop_ch2; + volatile gdma_in_link_chn_reg_t in_link_ch2; + volatile gdma_in_state_chn_reg_t in_state_ch2; + volatile gdma_in_suc_eof_des_addr_chn_reg_t in_suc_eof_des_addr_ch2; + volatile gdma_in_err_eof_des_addr_chn_reg_t in_err_eof_des_addr_ch2; + volatile gdma_in_dscr_chn_reg_t in_dscr_ch2; + volatile gdma_in_dscr_bf0_chn_reg_t in_dscr_bf0_ch2; + volatile gdma_in_dscr_bf1_chn_reg_t in_dscr_bf1_ch2; + volatile gdma_in_pri_chn_reg_t in_pri_ch2; + volatile gdma_in_peri_sel_chn_reg_t in_peri_sel_ch2; + uint32_t reserved_224[11]; + volatile gdma_out_conf0_chn_reg_t out_conf0_ch2; + volatile gdma_out_conf1_chn_reg_t out_conf1_ch2; + volatile gdma_outfifo_status_chn_reg_t outfifo_status_ch2; + volatile gdma_out_push_chn_reg_t out_push_ch2; + volatile gdma_out_link_chn_reg_t out_link_ch2; + volatile gdma_out_state_chn_reg_t out_state_ch2; + volatile gdma_out_eof_des_addr_chn_reg_t out_eof_des_addr_ch2; + volatile gdma_out_eof_bfr_des_addr_chn_reg_t out_eof_bfr_des_addr_ch2; + volatile gdma_out_dscr_chn_reg_t out_dscr_ch2; + volatile gdma_out_dscr_bf0_chn_reg_t out_dscr_bf0_ch2; + volatile gdma_out_dscr_bf1_chn_reg_t out_dscr_bf1_ch2; + volatile gdma_out_pri_chn_reg_t out_pri_ch2; + volatile gdma_out_peri_sel_chn_reg_t out_peri_sel_ch2; +} gdma_dev_t; + +extern gdma_dev_t GDMA; + +#ifndef __cplusplus +_Static_assert(sizeof(gdma_dev_t) == 0x284, "Invalid size of gdma_dev_t structure"); +#endif + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32h21/register/soc/i2c_ana_mst_reg.h b/components/soc/esp32h21/register/soc/i2c_ana_mst_reg.h new file mode 100644 index 00000000000..01c003761a2 --- /dev/null +++ b/components/soc/esp32h21/register/soc/i2c_ana_mst_reg.h @@ -0,0 +1,220 @@ +/** + * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#include "soc/soc.h" +#ifdef __cplusplus +extern "C" { +#endif + +//TODO: [ESP32H21] IDF-11858 + +#define I2C_MST_I2C0_CTRL_REG (DR_REG_I2C_ANA_MST_BASE + 0x0) +/* I2C_MST_I2C0_CTRL : R/W; bitpos: [24:0]; default: 0;*/ +/* description: .*/ +#define I2C_MST_I2C0_CTRL 0x01FFFFFFU +#define I2C_MST_I2C0_CTRL_M (I2C_MST_I2C0_CTRL_V << I2C_MST_I2C0_CTRL_S) +#define I2C_MST_I2C0_CTRL_V 0x01FFFFFFU +#define I2C_MST_I2C0_CTRL_S 0 +/* I2C_MST_I2C0_BUSY : RO; bitpos: [25]; default: 0;*/ +/* description: .*/ +#define I2C_MST_I2C0_BUSY (BIT(25)) +#define I2C_MST_I2C0_BUSY_M (I2C_MST_I2C0_BUSY_V << I2C_MST_I2C0_BUSY_S) +#define I2C_MST_I2C0_BUSY_V 0x00000001U +#define I2C_MST_I2C0_BUSY_S 25 + +#define I2C_MST_I2C1_CTRL_REG (DR_REG_I2C_ANA_MST_BASE + 0x4) +/* I2C_MST_I2C1_CTRL : R/W; bitpos: [24:0]; default: 0;*/ +/* description: .*/ +#define I2C_MST_I2C1_CTRL 0x01FFFFFFU +#define I2C_MST_I2C1_CTRL_M (I2C_MST_I2C1_CTRL_V << I2C_MST_I2C1_CTRL_S) +#define I2C_MST_I2C1_CTRL_V 0x01FFFFFFU +#define I2C_MST_I2C1_CTRL_S 0 +/* I2C_MST_I2C1_BUSY : RO; bitpos: [25]; default: 0;*/ +/* description: .*/ +#define I2C_MST_I2C1_BUSY (BIT(25)) +#define I2C_MST_I2C1_BUSY_M (I2C_MST_I2C1_BUSY_V << I2C_MST_I2C1_BUSY_S) +#define I2C_MST_I2C1_BUSY_V 0x00000001U +#define I2C_MST_I2C1_BUSY_S 25 + +#define I2C_MST_I2C0_CONF_REG (DR_REG_I2C_ANA_MST_BASE + 0x8) +/* I2C_MST_I2C0_CONF : R/W; bitpos: [23:0]; default: 0;*/ +/* description: .*/ +#define I2C_MST_I2C0_CONF 0x00FFFFFFU +#define I2C_MST_I2C0_CONF_M (I2C_MST_I2C0_CONF_V << I2C_MST_I2C0_CONF_S) +#define I2C_MST_I2C0_CONF_V 0x00FFFFFFU +#define I2C_MST_I2C0_CONF_S 0 +/* I2C_MST_I2C0_STATUS : RO; bitpos: [31:24]; default: 0;*/ +/* description: .*/ +#define I2C_MST_I2C0_STATUS 0x000000FFU +#define I2C_MST_I2C0_STATUS_M (I2C_MST_I2C0_STATUS_V << I2C_MST_I2C0_STATUS_S) +#define I2C_MST_I2C0_STATUS_V 0x000000FFU +#define I2C_MST_I2C0_STATUS_S 24 + +#define I2C_MST_I2C1_CONF_REG (DR_REG_I2C_ANA_MST_BASE + 0xc) +/* I2C_MST_I2C1_CONF : R/W; bitpos: [23:0]; default: 0;*/ +/* description: .*/ +#define I2C_MST_I2C1_CONF 0x00FFFFFFU +#define I2C_MST_I2C1_CONF_M (I2C_MST_I2C1_CONF_V << I2C_MST_I2C1_CONF_S) +#define I2C_MST_I2C1_CONF_V 0x00FFFFFFU +#define I2C_MST_I2C1_CONF_S 0 +/* I2C_MST_I2C1_STATUS : RO; bitpos: [31:24]; default: 0;*/ +/* description: .*/ +#define I2C_MST_I2C1_STATUS 0x000000FFU +#define I2C_MST_I2C1_STATUS_M (I2C_MST_I2C1_STATUS_V << I2C_MST_I2C1_STATUS_S) +#define I2C_MST_I2C1_STATUS_V 0x000000FFU +#define I2C_MST_I2C1_STATUS_S 24 + +#define I2C_MST_I2C_BURST_CONF_REG (DR_REG_I2C_ANA_MST_BASE + 0x10) +/* I2C_MST_BURST_CTRL : R/W; bitpos: [31:0]; default: 0;*/ +/* description: .*/ +#define I2C_MST_BURST_CTRL 0xFFFFFFFFU +#define I2C_MST_BURST_CTRL_M (I2C_MST_BURST_CTRL_V << I2C_MST_BURST_CTRL_S) +#define I2C_MST_BURST_CTRL_V 0xFFFFFFFFU +#define I2C_MST_BURST_CTRL_S 0 + +#define I2C_MST_I2C_BURST_STATUS_REG (DR_REG_I2C_ANA_MST_BASE + 0x14) +/* I2C_MST_I2C_MST_BURST_DONE : RO; bitpos: [0]; default: 0;*/ +/* description: .*/ +#define I2C_MST_I2C_MST_BURST_DONE (BIT(0)) +#define I2C_MST_I2C_MST_BURST_DONE_M (I2C_MST_I2C_MST_BURST_DONE_V << I2C_MST_I2C_MST_BURST_DONE_S) +#define I2C_MST_I2C_MST_BURST_DONE_V 0x00000001U +#define I2C_MST_I2C_MST_BURST_DONE_S 0 +/* I2C_MST_I2C_MST0_BURST_ERR_FLAG : RO; bitpos: [1]; default: 0;*/ +/* description: .*/ +#define I2C_MST_I2C_MST0_BURST_ERR_FLAG (BIT(1)) +#define I2C_MST_I2C_MST0_BURST_ERR_FLAG_M (I2C_MST_I2C_MST0_BURST_ERR_FLAG_V << I2C_MST_I2C_MST0_BURST_ERR_FLAG_S) +#define I2C_MST_I2C_MST0_BURST_ERR_FLAG_V 0x00000001U +#define I2C_MST_I2C_MST0_BURST_ERR_FLAG_S 1 +/* I2C_MST_I2C_MST1_BURST_ERR_FLAG : RO; bitpos: [2]; default: 0;*/ +/* description: .*/ +#define I2C_MST_I2C_MST1_BURST_ERR_FLAG (BIT(2)) +#define I2C_MST_I2C_MST1_BURST_ERR_FLAG_M (I2C_MST_I2C_MST1_BURST_ERR_FLAG_V << I2C_MST_I2C_MST1_BURST_ERR_FLAG_S) +#define I2C_MST_I2C_MST1_BURST_ERR_FLAG_V 0x00000001U +#define I2C_MST_I2C_MST1_BURST_ERR_FLAG_S 2 +/* I2C_MST_BURST_TIMEOUT_CNT : RO; bitpos: [19:3]; default: 0;*/ +/* description: .*/ +#define I2C_MST_BURST_TIMEOUT_CNT 0x0001FFFFU +#define I2C_MST_BURST_TIMEOUT_CNT_M (I2C_MST_BURST_TIMEOUT_CNT_V << I2C_MST_BURST_TIMEOUT_CNT_S) +#define I2C_MST_BURST_TIMEOUT_CNT_V 0x0001FFFFU +#define I2C_MST_BURST_TIMEOUT_CNT_S 3 + +#define I2C_MST_ANA_CONF0_REG (DR_REG_I2C_ANA_MST_BASE + 0x18) +/* I2C_MST_ANA_CONF0 : R/W; bitpos: [23:0]; default: 0;*/ +/* description: .*/ +#define I2C_MST_ANA_CONF0 0x00FFFFFFU +#define I2C_MST_ANA_CONF0_M (I2C_MST_ANA_CONF0_V << I2C_MST_ANA_CONF0_S) +#define I2C_MST_ANA_CONF0_V 0x00FFFFFFU +#define I2C_MST_ANA_CONF0_S 0 +/* I2C_MST_ANA_STATUS0 : RO; bitpos: [31:24]; default: 0;*/ +/* description: .*/ +#define I2C_MST_ANA_STATUS0 0x000000FFU +#define I2C_MST_ANA_STATUS0_M (I2C_MST_ANA_STATUS0_V << I2C_MST_ANA_STATUS0_S) +#define I2C_MST_ANA_STATUS0_V 0x000000FFU +#define I2C_MST_ANA_STATUS0_S 24 + +#define I2C_MST_ANA_CONF1_REG (DR_REG_I2C_ANA_MST_BASE + 0x1c) +/* I2C_MST_ANA_CONF1 : R/W; bitpos: [23:0]; default: 0;*/ +/* description: .*/ +#define I2C_MST_ANA_CONF1 0x00FFFFFFU +#define I2C_MST_ANA_CONF1_M (I2C_MST_ANA_CONF1_V << I2C_MST_ANA_CONF1_S) +#define I2C_MST_ANA_CONF1_V 0x00FFFFFFU +#define I2C_MST_ANA_CONF1_S 0 +/* I2C_MST_ANA_STATUS1 : RO; bitpos: [31:24]; default: 0;*/ +/* description: .*/ +#define I2C_MST_ANA_STATUS1 0x000000FFU +#define I2C_MST_ANA_STATUS1_M (I2C_MST_ANA_STATUS1_V << I2C_MST_ANA_STATUS1_S) +#define I2C_MST_ANA_STATUS1_V 0x000000FFU +#define I2C_MST_ANA_STATUS1_S 24 + +#define I2C_MST_ANA_CONF2_REG (DR_REG_I2C_ANA_MST_BASE + 0x20) +/* I2C_MST_ANA_CONF2 : R/W; bitpos: [23:0]; default: 0;*/ +/* description: .*/ +#define I2C_MST_ANA_CONF2 0x00FFFFFFU +#define I2C_MST_ANA_CONF2_M (I2C_MST_ANA_CONF2_V << I2C_MST_ANA_CONF2_S) +#define I2C_MST_ANA_CONF2_V 0x00FFFFFFU +#define I2C_MST_ANA_CONF2_S 0 +/* I2C_MST_ANA_STATUS2 : RO; bitpos: [31:24]; default: 0;*/ +/* description: .*/ +#define I2C_MST_ANA_STATUS2 0x000000FFU +#define I2C_MST_ANA_STATUS2_M (I2C_MST_ANA_STATUS2_V << I2C_MST_ANA_STATUS2_S) +#define I2C_MST_ANA_STATUS2_V 0x000000FFU +#define I2C_MST_ANA_STATUS2_S 24 + +#define I2C_MST_I2C0_CTRL1_REG (DR_REG_I2C_ANA_MST_BASE + 0x24) +/* I2C_MST_I2C0_SCL_PULSE_DUR : R/W; bitpos: [5:0]; default: 2;*/ +/* description: .*/ +#define I2C_MST_I2C0_SCL_PULSE_DUR 0x0000003FU +#define I2C_MST_I2C0_SCL_PULSE_DUR_M (I2C_MST_I2C0_SCL_PULSE_DUR_V << I2C_MST_I2C0_SCL_PULSE_DUR_S) +#define I2C_MST_I2C0_SCL_PULSE_DUR_V 0x0000003FU +#define I2C_MST_I2C0_SCL_PULSE_DUR_S 0 +/* I2C_MST_I2C0_SDA_SIDE_GUARD : R/W; bitpos: [10:6]; default: 1;*/ +/* description: .*/ +#define I2C_MST_I2C0_SDA_SIDE_GUARD 0x0000001FU +#define I2C_MST_I2C0_SDA_SIDE_GUARD_M (I2C_MST_I2C0_SDA_SIDE_GUARD_V << I2C_MST_I2C0_SDA_SIDE_GUARD_S) +#define I2C_MST_I2C0_SDA_SIDE_GUARD_V 0x0000001FU +#define I2C_MST_I2C0_SDA_SIDE_GUARD_S 6 + +#define I2C_MST_I2C1_CTRL1_REG (DR_REG_I2C_ANA_MST_BASE + 0x28) +/* I2C_MST_I2C1_SCL_PULSE_DUR : R/W; bitpos: [5:0]; default: 2;*/ +/* description: .*/ +#define I2C_MST_I2C1_SCL_PULSE_DUR 0x0000003FU +#define I2C_MST_I2C1_SCL_PULSE_DUR_M (I2C_MST_I2C1_SCL_PULSE_DUR_V << I2C_MST_I2C1_SCL_PULSE_DUR_S) +#define I2C_MST_I2C1_SCL_PULSE_DUR_V 0x0000003FU +#define I2C_MST_I2C1_SCL_PULSE_DUR_S 0 +/* I2C_MST_I2C1_SDA_SIDE_GUARD : R/W; bitpos: [10:6]; default: 1;*/ +/* description: .*/ +#define I2C_MST_I2C1_SDA_SIDE_GUARD 0x0000001FU +#define I2C_MST_I2C1_SDA_SIDE_GUARD_M (I2C_MST_I2C1_SDA_SIDE_GUARD_V << I2C_MST_I2C1_SDA_SIDE_GUARD_S) +#define I2C_MST_I2C1_SDA_SIDE_GUARD_V 0x0000001FU +#define I2C_MST_I2C1_SDA_SIDE_GUARD_S 6 + +#define I2C_MST_HW_I2C_CTRL_REG (DR_REG_I2C_ANA_MST_BASE + 0x2c) +/* I2C_MST_HW_I2C_SCL_PULSE_DUR : R/W; bitpos: [5:0]; default: 2;*/ +/* description: .*/ +#define I2C_MST_HW_I2C_SCL_PULSE_DUR 0x0000003FU +#define I2C_MST_HW_I2C_SCL_PULSE_DUR_M (I2C_MST_HW_I2C_SCL_PULSE_DUR_V << I2C_MST_HW_I2C_SCL_PULSE_DUR_S) +#define I2C_MST_HW_I2C_SCL_PULSE_DUR_V 0x0000003FU +#define I2C_MST_HW_I2C_SCL_PULSE_DUR_S 0 +/* I2C_MST_HW_I2C_SDA_SIDE_GUARD : R/W; bitpos: [10:6]; default: 1;*/ +/* description: .*/ +#define I2C_MST_HW_I2C_SDA_SIDE_GUARD 0x0000001FU +#define I2C_MST_HW_I2C_SDA_SIDE_GUARD_M (I2C_MST_HW_I2C_SDA_SIDE_GUARD_V << I2C_MST_HW_I2C_SDA_SIDE_GUARD_S) +#define I2C_MST_HW_I2C_SDA_SIDE_GUARD_V 0x0000001FU +#define I2C_MST_HW_I2C_SDA_SIDE_GUARD_S 6 +/* I2C_MST_ARBITER_DIS : R/W; bitpos: [11]; default: 0;*/ +/* description: .*/ +#define I2C_MST_ARBITER_DIS (BIT(11)) +#define I2C_MST_ARBITER_DIS_M (I2C_MST_ARBITER_DIS_V << I2C_MST_ARBITER_DIS_S) +#define I2C_MST_ARBITER_DIS_V 0x00000001U +#define I2C_MST_ARBITER_DIS_S 11 + +#define I2C_MST_NOUSE_REG (DR_REG_I2C_ANA_MST_BASE + 0x30) +/* I2C_MST_NOUSE : R/W; bitpos: [31:0]; default: 0;*/ +/* description: .*/ +#define I2C_MST_NOUSE 0xFFFFFFFFU +#define I2C_MST_NOUSE_M (I2C_MST_NOUSE_V << I2C_MST_NOUSE_S) +#define I2C_MST_NOUSE_V 0xFFFFFFFFU +#define I2C_MST_NOUSE_S 0 + +#define I2C_MST_DATE_REG (DR_REG_I2C_ANA_MST_BASE + 0x34) +/* I2C_MST_DATE : R/W; bitpos: [27:0]; default: 35656448;*/ +/* description: .*/ +#define I2C_MST_DATE 0x0FFFFFFFU +#define I2C_MST_DATE_M (I2C_MST_DATE_V << I2C_MST_DATE_S) +#define I2C_MST_DATE_V 0x0FFFFFFFU +#define I2C_MST_DATE_S 0 +/* I2C_MST_CLK_EN : R/W; bitpos: [28]; default: 0;*/ +/* description: .*/ +#define I2C_MST_CLK_EN (BIT(28)) +#define I2C_MST_CLK_EN_M (I2C_MST_CLK_EN_V << I2C_MST_CLK_EN_S) +#define I2C_MST_CLK_EN_V 0x00000001U +#define I2C_MST_CLK_EN_S 28 + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32h21/register/soc/interrupt_matrix_reg.h b/components/soc/esp32h21/register/soc/interrupt_matrix_reg.h index ce4890cf34a..020976f85fc 100644 --- a/components/soc/esp32h21/register/soc/interrupt_matrix_reg.h +++ b/components/soc/esp32h21/register/soc/interrupt_matrix_reg.h @@ -5,7 +5,6 @@ */ #pragma once -#include #include "soc/soc.h" #ifdef __cplusplus extern "C" { diff --git a/components/soc/esp32h21/register/soc/interrupt_reg.h b/components/soc/esp32h21/register/soc/interrupt_reg.h new file mode 100644 index 00000000000..9d685cddd68 --- /dev/null +++ b/components/soc/esp32h21/register/soc/interrupt_reg.h @@ -0,0 +1,24 @@ +/* + * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include "interrupt_matrix_reg.h" +#include "plic_reg.h" +#include "soc/soc_caps.h" + +#define INTERRUPT_PRIO_REG(n) (PLIC_MXINT0_PRI_REG + (n)*4) +#define INTERRUPT_CURRENT_CORE_INT_THRESH_REG PLIC_MXINT_THRESH_REG + +/** + * ESP32H21 should use the PLIC controller as the interrupt controller instead of INTC (SOC_INT_PLIC_SUPPORTED = y) + * Keep the following macros for backward compatibility reasons + */ +#define INTERRUPT_CORE0_CPU_INT_ENABLE_REG PLIC_MXINT_ENABLE_REG +#define INTERRUPT_CORE0_CPU_INT_THRESH_REG PLIC_MXINT_THRESH_REG +#define INTERRUPT_CORE0_CPU_INT_CLEAR_REG PLIC_MXINT_CLEAR_REG +#define INTERRUPT_CORE0_CPU_INT_TYPE_REG PLIC_MXINT_TYPE_REG +#define INTC_INT_PRIO_REG(n) (PLIC_MXINT0_PRI_REG + (n)*4) +#define DR_REG_INTERRUPT_BASE DR_REG_INTERRUPT_MATRIX_BASE diff --git a/components/soc/esp32h21/register/soc/io_mux_reg.h b/components/soc/esp32h21/register/soc/io_mux_reg.h new file mode 100644 index 00000000000..076b9c3c4e1 --- /dev/null +++ b/components/soc/esp32h21/register/soc/io_mux_reg.h @@ -0,0 +1,365 @@ +/* + * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#pragma once +#include "soc/soc.h" + +/* The following are the bit fields for PERIPHS_IO_MUX_x_U registers */ +/* Output enable in sleep mode */ +#define SLP_OE (BIT(0)) +#define SLP_OE_M (BIT(0)) +#define SLP_OE_V 1 +#define SLP_OE_S 0 +/* Pin used for wakeup from sleep */ +#define SLP_SEL (BIT(1)) +#define SLP_SEL_M (BIT(1)) +#define SLP_SEL_V 1 +#define SLP_SEL_S 1 +/* Pulldown enable in sleep mode */ +#define SLP_PD (BIT(2)) +#define SLP_PD_M (BIT(2)) +#define SLP_PD_V 1 +#define SLP_PD_S 2 +/* Pullup enable in sleep mode */ +#define SLP_PU (BIT(3)) +#define SLP_PU_M (BIT(3)) +#define SLP_PU_V 1 +#define SLP_PU_S 3 +/* Input enable in sleep mode */ +#define SLP_IE (BIT(4)) +#define SLP_IE_M (BIT(4)) +#define SLP_IE_V 1 +#define SLP_IE_S 4 +/* Drive strength in sleep mode */ +#define SLP_DRV 0x3 +#define SLP_DRV_M (SLP_DRV_V << SLP_DRV_S) +#define SLP_DRV_V 0x3 +#define SLP_DRV_S 5 +/* Pulldown enable */ +#define FUN_PD (BIT(7)) +#define FUN_PD_M (BIT(7)) +#define FUN_PD_V 1 +#define FUN_PD_S 7 +/* Pullup enable */ +#define FUN_PU (BIT(8)) +#define FUN_PU_M (BIT(8)) +#define FUN_PU_V 1 +#define FUN_PU_S 8 +/* Input enable */ +#define FUN_IE (BIT(9)) +#define FUN_IE_M (FUN_IE_V << FUN_IE_S) +#define FUN_IE_V 1 +#define FUN_IE_S 9 +/* Drive strength */ +#define FUN_DRV 0x3 +#define FUN_DRV_M (FUN_DRV_V << FUN_DRV_S) +#define FUN_DRV_V 0x3 +#define FUN_DRV_S 10 +/* Function select (possible values are defined for each pin as FUNC_pinname_function below) */ +#define MCU_SEL 0x7 +#define MCU_SEL_M (MCU_SEL_V << MCU_SEL_S) +#define MCU_SEL_V 0x7 +#define MCU_SEL_S 12 +/* Pin filter (Pulse width shorter than 2 clock cycles will be filtered out) */ +#define FILTER_EN (BIT(15)) +#define FILTER_EN_M (FILTER_EN_V << FILTER_EN_S) +#define FILTER_EN_V 1 +#define FILTER_EN_S 15 + +/* HYS_EN : R/W; bitpos: [16]; default: 0; + * Software enables hysteresis function for the pad. + * 1: Hysteresis enabled. 0: Hysteresis disabled. + */ +#define HYS_EN (BIT(16)) +#define HYS_EN_M (HYS_EN_V << HYS_EN_S) +#define HYS_EN_V 0x00000001 +#define HYS_EN_S 16 +/* HYS_SEL : R/W; bitpos: [17]; default: 0; + * Select enabling signals of the pad from software and efuse hardware. + * 1: Select enabling signal from software. + * 0: Select enabling signal from efuse hardware. + */ +#define HYS_SEL (BIT(17)) +#define HYS_SEL_M (HYS_SEL_V << HYS_SEL_S) +#define HYS_SEL_V 0x00000001 +#define HYS_SEL_S 17 + +#define PIN_SLP_INPUT_ENABLE(PIN_NAME) SET_PERI_REG_MASK(PIN_NAME,SLP_IE) +#define PIN_SLP_INPUT_DISABLE(PIN_NAME) CLEAR_PERI_REG_MASK(PIN_NAME,SLP_IE) +#define PIN_SLP_OUTPUT_ENABLE(PIN_NAME) SET_PERI_REG_MASK(PIN_NAME,SLP_OE) +#define PIN_SLP_OUTPUT_DISABLE(PIN_NAME) CLEAR_PERI_REG_MASK(PIN_NAME,SLP_OE) +#define PIN_SLP_PULLUP_ENABLE(PIN_NAME) SET_PERI_REG_MASK(PIN_NAME,SLP_PU) +#define PIN_SLP_PULLUP_DISABLE(PIN_NAME) CLEAR_PERI_REG_MASK(PIN_NAME,SLP_PU) +#define PIN_SLP_PULLDOWN_ENABLE(PIN_NAME) SET_PERI_REG_MASK(PIN_NAME,SLP_PD) +#define PIN_SLP_PULLDOWN_DISABLE(PIN_NAME) CLEAR_PERI_REG_MASK(PIN_NAME,SLP_PD) +#define PIN_SLP_SEL_ENABLE(PIN_NAME) SET_PERI_REG_MASK(PIN_NAME,SLP_SEL) +#define PIN_SLP_SEL_DISABLE(PIN_NAME) CLEAR_PERI_REG_MASK(PIN_NAME,SLP_SEL) + +#define PIN_INPUT_ENABLE(PIN_NAME) SET_PERI_REG_MASK(PIN_NAME,FUN_IE) +#define PIN_INPUT_DISABLE(PIN_NAME) CLEAR_PERI_REG_MASK(PIN_NAME,FUN_IE) +#define PIN_SET_DRV(PIN_NAME, drv) REG_SET_FIELD(PIN_NAME, FUN_DRV, (drv)); +#define PIN_PULLUP_DIS(PIN_NAME) REG_CLR_BIT(PIN_NAME, FUN_PU) +#define PIN_PULLUP_EN(PIN_NAME) REG_SET_BIT(PIN_NAME, FUN_PU) +#define PIN_PULLDWN_DIS(PIN_NAME) REG_CLR_BIT(PIN_NAME, FUN_PD) +#define PIN_PULLDWN_EN(PIN_NAME) REG_SET_BIT(PIN_NAME, FUN_PD) +#define PIN_FUNC_SELECT(PIN_NAME, FUNC) REG_SET_FIELD(PIN_NAME, MCU_SEL, FUNC) +#define PIN_FILTER_EN(PIN_NAME) REG_SET_BIT(PIN_NAME, FILTER_EN) +#define PIN_FILTER_DIS(PIN_NAME) REG_CLR_BIT(PIN_NAME, FILTER_EN) +#define PIN_HYS_EN_SEL_EFUSE(PIN_NAME) REG_CLR_BIT(PIN_NAME, HYS_SEL) +#define PIN_HYS_EN_SEL_SOFT(PIN_NAME) REG_SET_BIT(PIN_NAME, HYS_SEL) +#define PIN_HYS_SOFT_ENABLE(PIN_NAME) REG_SET_BIT(PIN_NAME, HYS_EN) +#define PIN_HYS_SOFT_DISABLE(PIN_NAME) REG_CLR_BIT(PIN_NAME, HYS_EN) + +#define IO_MUX_GPIO0_REG PERIPHS_IO_MUX_U_PAD_MTMS +#define IO_MUX_GPIO1_REG PERIPHS_IO_MUX_U_PAD_MTDO +#define IO_MUX_GPIO2_REG PERIPHS_IO_MUX_U_PAD_MTCK +#define IO_MUX_GPIO3_REG PERIPHS_IO_MUX_U_PAD_MTDI +#define IO_MUX_GPIO4_REG PERIPHS_IO_MUX_U_PAD_GPIO4 +#define IO_MUX_GPIO5_REG PERIPHS_IO_MUX_U_PAD_GPIO5 +#define IO_MUX_GPIO6_REG PERIPHS_IO_MUX_U_PAD_GPIO6 +#define IO_MUX_GPIO7_REG PERIPHS_IO_MUX_U_PAD_GPIO7 +#define IO_MUX_GPIO8_REG PERIPHS_IO_MUX_U_PAD_GPIO8 +#define IO_MUX_GPIO9_REG PERIPHS_IO_MUX_U_PAD_GPIO9 +#define IO_MUX_GPIO10_REG PERIPHS_IO_MUX_U_PAD_XTAL_32K_N +#define IO_MUX_GPIO11_REG PERIPHS_IO_MUX_U_PAD_XTAL_32K_P +#define IO_MUX_GPIO12_REG PERIPHS_IO_MUX_U_PAD_GPIO12 +#define IO_MUX_GPIO13_REG PERIPHS_IO_MUX_U_PAD_GPIO13 +#define IO_MUX_GPIO14_REG PERIPHS_IO_MUX_U_PAD_GPIO14 +#define IO_MUX_GPIO15_REG PERIPHS_IO_MUX_U_PAD_U0RXD +#define IO_MUX_GPIO16_REG PERIPHS_IO_MUX_U_PAD_U0TXD +#define IO_MUX_GPIO17_REG PERIPHS_IO_MUX_U_PAD_GPIO17 +#define IO_MUX_GPIO18_REG PERIPHS_IO_MUX_U_PAD_GPIO18 +#define IO_MUX_GPIO19_REG PERIPHS_IO_MUX_U_PAD_VDD_SPI +#define IO_MUX_GPIO20_REG PERIPHS_IO_MUX_U_PAD_SPICS0 +#define IO_MUX_GPIO21_REG PERIPHS_IO_MUX_U_PAD_SPIQ +#define IO_MUX_GPIO22_REG PERIPHS_IO_MUX_U_PAD_SPIWP +#define IO_MUX_GPIO23_REG PERIPHS_IO_MUX_U_PAD_SPIHD +#define IO_MUX_GPIO24_REG PERIPHS_IO_MUX_U_PAD_SPICLK +#define IO_MUX_GPIO25_REG PERIPHS_IO_MUX_U_PAD_SPID + +#define FUNC_GPIO_GPIO 1 +#define PIN_FUNC_GPIO 1 + +#define GPIO_PAD_PULLUP(num) do{PIN_PULLDWN_DIS(IOMUX_REG_GPIO##num);PIN_PULLUP_EN(IOMUX_REG_GPIO##num);}while(0) +#define GPIO_PAD_PULLDOWN(num) do{PIN_PULLUP_DIS(IOMUX_REG_GPIO##num);PIN_PULLDWN_EN(IOMUX_REG_GPIO##num);}while(0) +#define GPIO_PAD_SET_DRV(num, drv) PIN_SET_DRV(IOMUX_REG_GPIO##num, drv) + +#define U0RXD_GPIO_NUM 15 +#define U0TXD_GPIO_NUM 16 + +#define SPI_HD_GPIO_NUM 23 +#define SPI_WP_GPIO_NUM 22 +#define SPI_CS0_GPIO_NUM 20 +#define SPI_CLK_GPIO_NUM 24 +#define SPI_D_GPIO_NUM 25 +#define SPI_Q_GPIO_NUM 21 + +#define USB_INT_PHY0_DM_GPIO_NUM 26 +#define USB_INT_PHY0_DP_GPIO_NUM 27 + +#define EXT_OSC_SLOW_GPIO_NUM 13 + + +#define MAX_RTC_GPIO_NUM 11 // GPIO5~11 are the pads with LP function +#define MAX_PAD_GPIO_NUM 25 +#define MAX_GPIO_NUM 29 +#define HIGH_IO_HOLD_BIT_SHIFT 32 + +#define GPIO_NUM_IN_INVALID 0x28 + +#define REG_IO_MUX_BASE DR_REG_IO_MUX_BASE +#define PIN_CTRL (REG_IO_MUX_BASE +0x00) +#define PAD_POWER_SEL BIT(15) +#define PAD_POWER_SEL_V 0x1 +#define PAD_POWER_SEL_M BIT(15) +#define PAD_POWER_SEL_S 15 + +#define PAD_POWER_SWITCH_DELAY 0x7 +#define PAD_POWER_SWITCH_DELAY_V 0x7 +#define PAD_POWER_SWITCH_DELAY_M (PAD_POWER_SWITCH_DELAY_V << PAD_POWER_SWITCH_DELAY_S) +#define PAD_POWER_SWITCH_DELAY_S 12 + +#define CLK_OUT3 IO_MUX_CLK_OUT3 +#define CLK_OUT3_V IO_MUX_CLK_OUT3_V +#define CLK_OUT3_S IO_MUX_CLK_OUT3_S +#define CLK_OUT3_M IO_MUX_CLK_OUT3_M +#define CLK_OUT2 IO_MUX_CLK_OUT2 +#define CLK_OUT2_V IO_MUX_CLK_OUT2_V +#define CLK_OUT2_S IO_MUX_CLK_OUT2_S +#define CLK_OUT2_M IO_MUX_CLK_OUT2_M +#define CLK_OUT1 IO_MUX_CLK_OUT1 +#define CLK_OUT1_V IO_MUX_CLK_OUT1_V +#define CLK_OUT1_S IO_MUX_CLK_OUT1_S +#define CLK_OUT1_M IO_MUX_CLK_OUT1_M +// definitions above are inherited from previous version of code, should double check + +// definitions below are generated from pin_txt.csv +#define PERIPHS_IO_MUX_U_PAD_MTMS (REG_IO_MUX_BASE + 0x0) +#define FUNC_MTMS_FSPIWP 2 +#define FUNC_MTMS_GPIO0 1 +#define FUNC_MTMS_MTMS 0 + +#define PERIPHS_IO_MUX_U_PAD_MTDO (REG_IO_MUX_BASE + 0x4) +#define FUNC_MTDO_FSPIHD 2 +#define FUNC_MTDO_GPIO1 1 +#define FUNC_MTDO_MTDO 0 + +#define PERIPHS_IO_MUX_U_PAD_MTCK (REG_IO_MUX_BASE + 0x8) +#define FUNC_MTCK_FSPICLK 2 +#define FUNC_MTCK_GPIO2 1 +#define FUNC_MTCK_MTCK 0 + +#define PERIPHS_IO_MUX_U_PAD_MTDI (REG_IO_MUX_BASE + 0xC) +#define FUNC_MTDI_FSPID 2 +#define FUNC_MTDI_GPIO3 1 +#define FUNC_MTDI_MTDI 0 + +#define PERIPHS_IO_MUX_U_PAD_GPIO4 (REG_IO_MUX_BASE + 0x10) +#define FUNC_GPIO4_FSPIQ 2 +#define FUNC_GPIO4_GPIO4 1 +#define FUNC_GPIO4_GPIO4_0 0 + +#define PERIPHS_IO_MUX_U_PAD_GPIO5 (REG_IO_MUX_BASE + 0x14) +#define FUNC_GPIO5_GPIO5 1 +#define FUNC_GPIO5_GPIO5_0 0 + +#define PERIPHS_IO_MUX_U_PAD_GPIO6 (REG_IO_MUX_BASE + 0x18) +#define FUNC_GPIO6_GPIO6 1 +#define FUNC_GPIO6_GPIO6_0 0 + +#define PERIPHS_IO_MUX_U_PAD_GPIO7 (REG_IO_MUX_BASE + 0x1C) +#define FUNC_GPIO7_GPIO7 1 +#define FUNC_GPIO7_GPIO7_0 0 + +#define PERIPHS_IO_MUX_U_PAD_GPIO8 (REG_IO_MUX_BASE + 0x20) +#define FUNC_GPIO8_GPIO8 1 +#define FUNC_GPIO8_GPIO8_0 0 + +#define PERIPHS_IO_MUX_U_PAD_GPIO9 (REG_IO_MUX_BASE + 0x24) +#define FUNC_GPIO9_GPIO9 1 +#define FUNC_GPIO9_GPIO9_0 0 + +#define PERIPHS_IO_MUX_U_PAD_XTAL_32K_N (REG_IO_MUX_BASE + 0x28) +#define FUNC_XTAL_32K_N_GPIO10 1 +#define FUNC_XTAL_32K_N_GPIO10_0 0 + +#define PERIPHS_IO_MUX_U_PAD_XTAL_32K_P (REG_IO_MUX_BASE + 0x2C) +#define FUNC_XTAL_32K_P_GPIO11 1 +#define FUNC_XTAL_32K_P_GPIO11_0 0 + +#define PERIPHS_IO_MUX_U_PAD_GPIO12 (REG_IO_MUX_BASE + 0x30) +#define FUNC_GPIO12_FSPICS0 2 +#define FUNC_GPIO12_GPIO12 1 +#define FUNC_GPIO12_GPIO12_0 0 + +#define PERIPHS_IO_MUX_U_PAD_GPIO13 (REG_IO_MUX_BASE + 0x34) +#define FUNC_GPIO13_GPIO13 1 +#define FUNC_GPIO13_GPIO13_0 0 + +#define PERIPHS_IO_MUX_U_PAD_GPIO14 (REG_IO_MUX_BASE + 0x38) +#define FUNC_GPIO14_GPIO14 1 +#define FUNC_GPIO14_GPIO14_0 0 + +#define PERIPHS_IO_MUX_U_PAD_U0RXD (REG_IO_MUX_BASE + 0x3C) +#define FUNC_U0RXD_GPIO15 1 +#define FUNC_U0RXD_U0RXD 0 + +#define PERIPHS_IO_MUX_U_PAD_U0TXD (REG_IO_MUX_BASE + 0x40) +#define FUNC_U0TXD_GPIO16 1 +#define FUNC_U0TXD_U0TXD 0 + +#define PERIPHS_IO_MUX_U_PAD_GPIO17 (REG_IO_MUX_BASE + 0x44) +#define FUNC_GPIO17_GPIO17 1 +#define FUNC_GPIO17_GPIO17_0 0 + +#define PERIPHS_IO_MUX_U_PAD_GPIO18 (REG_IO_MUX_BASE + 0x48) +#define FUNC_GPIO18_GPIO18 1 +#define FUNC_GPIO18_GPIO18_0 0 + +#define PERIPHS_IO_MUX_U_PAD_VDD_SPI (REG_IO_MUX_BASE + 0x4C) +#define FUNC_VDD_SPI_GPIO19 1 +#define FUNC_VDD_SPI_GPIO19_0 0 + +#define PERIPHS_IO_MUX_U_PAD_SPICS0 (REG_IO_MUX_BASE + 0x50) +#define FUNC_SPICS0_GPIO20 1 +#define FUNC_SPICS0_SPICS0 0 + +#define PERIPHS_IO_MUX_U_PAD_SPIQ (REG_IO_MUX_BASE + 0x54) +#define FUNC_SPIQ_GPIO21 1 +#define FUNC_SPIQ_SPIQ 0 + +#define PERIPHS_IO_MUX_U_PAD_SPIWP (REG_IO_MUX_BASE + 0x58) +#define FUNC_SPIWP_GPIO22 1 +#define FUNC_SPIWP_SPIWP 0 + +#define PERIPHS_IO_MUX_U_PAD_SPIHD (REG_IO_MUX_BASE + 0x5C) +#define FUNC_SPIHD_GPIO23 1 +#define FUNC_SPIHD_SPIHD 0 + +#define PERIPHS_IO_MUX_U_PAD_SPICLK (REG_IO_MUX_BASE + 0x60) +#define FUNC_SPICLK_GPIO24 1 +#define FUNC_SPICLK_SPICLK 0 + +#define PERIPHS_IO_MUX_U_PAD_SPID (REG_IO_MUX_BASE + 0x64) +#define FUNC_SPID_GPIO25 1 +#define FUNC_SPID_SPID 0 + +/** IO_MUX_PIN_CTRL_REG register + * Clock Output Configuration + * Register + */ +#define IO_MUX_PIN_CTRL_REG (REG_IO_MUX_BASE + 0x0) +/* IO_MUX_CLK_OUT1 : R/W; bitpos: [5:0]; default: 15; + * If you want to output clock for I2S to CLK_OUT_out1, set this register + * to 0x0. CLK_OUT_out1 can be found in peripheral output + * signals. + */ +#define IO_MUX_CLK_OUT1 0x0000001F +#define IO_MUX_CLK_OUT1_M (IO_MUX_CLK_OUT1_V << IO_MUX_CLK_OUT1_S) +#define IO_MUX_CLK_OUT1_V 0x0000001F +#define IO_MUX_CLK_OUT1_S 0 +/* IO_MUX_CLK_OUT2 : R/W; bitpos: [10:5]; default: 15; + * If you want to output clock for I2S to CLK_OUT_out2, set this register + * to 0x0. CLK_OUT_out2 can be found in peripheral output + * signals. + */ +#define IO_MUX_CLK_OUT2 0x0000001F +#define IO_MUX_CLK_OUT2_M (IO_MUX_CLK_OUT2_V << IO_MUX_CLK_OUT2_S) +#define IO_MUX_CLK_OUT2_V 0x0000001F +#define IO_MUX_CLK_OUT2_S 5 +/* IO_MUX_CLK_OUT3 : R/W; bitpos: [15:10]; default: 7; + * If you want to output clock for I2S to CLK_OUT_out3, set this register + * to 0x0. CLK_OUT_out3 can be found in peripheral output + * signals. + */ +#define IO_MUX_CLK_OUT3 0x0000001F +#define IO_MUX_CLK_OUT3_M (IO_MUX_CLK_OUT3_V << IO_MUX_CLK_OUT3_S) +#define IO_MUX_CLK_OUT3_V 0x0000001F +#define IO_MUX_CLK_OUT3_S 10 + +/** IO_MUX_MODEM_DIAG_EN_REG register + * GPIO MATRIX Configure Register for modem + * diag + */ +#define IO_MUX_MODEM_DIAG_EN_REG (REG_IO_MUX_BASE + 0xbc) +/* IO_MUX_MODEM_DIAG_EN : R/W; bitpos: [32:0]; default: 0; + * bit i to enable modem_diag[i] into gpio matrix. 1:enable modem_diag[i] + * into gpio matrix. 0:enable other signals into gpio + * matrix + */ +#define IO_MUX_MODEM_DIAG_EN 0xFFFFFFFF +#define IO_MUX_MODEM_DIAG_EN_M (IO_MUX_MODEM_DIAG_EN_V << IO_MUX_MODEM_DIAG_EN_S) +#define IO_MUX_MODEM_DIAG_EN_V 0xFFFFFFFF +#define IO_MUX_MODEM_DIAG_EN_S 0 + + +#define IO_MUX_DATE_REG (REG_IO_MUX_BASE + 0x1FC) +/* IO_MUX_REG_DATE : R/W ;bitpos:[27:0] ;default: 28'h2409110 ; */ +/*description: Version control register.*/ +#define IO_MUX_REG_DATE 0x0FFFFFFF +#define IO_MUX_REG_DATE_M ((IO_MUX_REG_DATE_V)<<(IO_MUX_REG_DATE_S)) +#define IO_MUX_REG_DATE_V 0xFFFFFFF +#define IO_MUX_REG_DATE_S 0 diff --git a/components/soc/esp32h21/register/soc/lp_timer_reg.h b/components/soc/esp32h21/register/soc/lp_timer_reg.h new file mode 100644 index 00000000000..4b3d82ef15f --- /dev/null +++ b/components/soc/esp32h21/register/soc/lp_timer_reg.h @@ -0,0 +1,242 @@ +/** + * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#include "soc/soc.h" +#ifdef __cplusplus +extern "C" { +#endif + +/** LP_TIMER_TAR0_LOW_REG register + * need_des + */ +#define LP_TIMER_TAR0_LOW_REG (DR_REG_LP_TIMER_BASE + 0x0) +/** LP_TIMER_MAIN_TIMER_TAR_LOW0 : R/W; bitpos: [31:0]; default: 0; + * need_des + */ +#define LP_TIMER_MAIN_TIMER_TAR_LOW0 0xFFFFFFFFU +#define LP_TIMER_MAIN_TIMER_TAR_LOW0_M (LP_TIMER_MAIN_TIMER_TAR_LOW0_V << LP_TIMER_MAIN_TIMER_TAR_LOW0_S) +#define LP_TIMER_MAIN_TIMER_TAR_LOW0_V 0xFFFFFFFFU +#define LP_TIMER_MAIN_TIMER_TAR_LOW0_S 0 + +/** LP_TIMER_TAR0_HIGH_REG register + * need_des + */ +#define LP_TIMER_TAR0_HIGH_REG (DR_REG_LP_TIMER_BASE + 0x4) +/** LP_TIMER_MAIN_TIMER_TAR_HIGH0 : R/W; bitpos: [15:0]; default: 0; + * need_des + */ +#define LP_TIMER_MAIN_TIMER_TAR_HIGH0 0x0000FFFFU +#define LP_TIMER_MAIN_TIMER_TAR_HIGH0_M (LP_TIMER_MAIN_TIMER_TAR_HIGH0_V << LP_TIMER_MAIN_TIMER_TAR_HIGH0_S) +#define LP_TIMER_MAIN_TIMER_TAR_HIGH0_V 0x0000FFFFU +#define LP_TIMER_MAIN_TIMER_TAR_HIGH0_S 0 +/** LP_TIMER_MAIN_TIMER_TAR_EN0 : WT; bitpos: [31]; default: 0; + * need_des + */ +#define LP_TIMER_MAIN_TIMER_TAR_EN0 (BIT(31)) +#define LP_TIMER_MAIN_TIMER_TAR_EN0_M (LP_TIMER_MAIN_TIMER_TAR_EN0_V << LP_TIMER_MAIN_TIMER_TAR_EN0_S) +#define LP_TIMER_MAIN_TIMER_TAR_EN0_V 0x00000001U +#define LP_TIMER_MAIN_TIMER_TAR_EN0_S 31 + +/** LP_TIMER_UPDATE_REG register + * need_des + */ +#define LP_TIMER_UPDATE_REG (DR_REG_LP_TIMER_BASE + 0x10) +/** LP_TIMER_MAIN_TIMER_UPDATE : WT; bitpos: [27]; default: 0; + * need_des + */ +#define LP_TIMER_MAIN_TIMER_UPDATE (BIT(27)) +#define LP_TIMER_MAIN_TIMER_UPDATE_M (LP_TIMER_MAIN_TIMER_UPDATE_V << LP_TIMER_MAIN_TIMER_UPDATE_S) +#define LP_TIMER_MAIN_TIMER_UPDATE_V 0x00000001U +#define LP_TIMER_MAIN_TIMER_UPDATE_S 27 +/** LP_TIMER_MAIN_TIMER_REGDMA_WORK : R/W; bitpos: [28]; default: 0; + * Selects the triggering condition for the RTC timer,triggered when regdma working + */ +#define LP_TIMER_MAIN_TIMER_REGDMA_WORK (BIT(28)) +#define LP_TIMER_MAIN_TIMER_REGDMA_WORK_M (LP_TIMER_MAIN_TIMER_REGDMA_WORK_V << LP_TIMER_MAIN_TIMER_REGDMA_WORK_S) +#define LP_TIMER_MAIN_TIMER_REGDMA_WORK_V 0x00000001U +#define LP_TIMER_MAIN_TIMER_REGDMA_WORK_S 28 +/** LP_TIMER_MAIN_TIMER_XTAL_OFF : R/W; bitpos: [29]; default: 0; + * need_des + */ +#define LP_TIMER_MAIN_TIMER_XTAL_OFF (BIT(29)) +#define LP_TIMER_MAIN_TIMER_XTAL_OFF_M (LP_TIMER_MAIN_TIMER_XTAL_OFF_V << LP_TIMER_MAIN_TIMER_XTAL_OFF_S) +#define LP_TIMER_MAIN_TIMER_XTAL_OFF_V 0x00000001U +#define LP_TIMER_MAIN_TIMER_XTAL_OFF_S 29 +/** LP_TIMER_MAIN_TIMER_SYS_STALL : R/W; bitpos: [30]; default: 0; + * need_des + */ +#define LP_TIMER_MAIN_TIMER_SYS_STALL (BIT(30)) +#define LP_TIMER_MAIN_TIMER_SYS_STALL_M (LP_TIMER_MAIN_TIMER_SYS_STALL_V << LP_TIMER_MAIN_TIMER_SYS_STALL_S) +#define LP_TIMER_MAIN_TIMER_SYS_STALL_V 0x00000001U +#define LP_TIMER_MAIN_TIMER_SYS_STALL_S 30 +/** LP_TIMER_MAIN_TIMER_SYS_RST : R/W; bitpos: [31]; default: 0; + * need_des + */ +#define LP_TIMER_MAIN_TIMER_SYS_RST (BIT(31)) +#define LP_TIMER_MAIN_TIMER_SYS_RST_M (LP_TIMER_MAIN_TIMER_SYS_RST_V << LP_TIMER_MAIN_TIMER_SYS_RST_S) +#define LP_TIMER_MAIN_TIMER_SYS_RST_V 0x00000001U +#define LP_TIMER_MAIN_TIMER_SYS_RST_S 31 + +/** LP_TIMER_MAIN_BUF0_LOW_REG register + * need_des + */ +#define LP_TIMER_MAIN_BUF0_LOW_REG (DR_REG_LP_TIMER_BASE + 0x14) +/** LP_TIMER_MAIN_TIMER_BUF0_LOW : RO; bitpos: [31:0]; default: 0; + * need_des + */ +#define LP_TIMER_MAIN_TIMER_BUF0_LOW 0xFFFFFFFFU +#define LP_TIMER_MAIN_TIMER_BUF0_LOW_M (LP_TIMER_MAIN_TIMER_BUF0_LOW_V << LP_TIMER_MAIN_TIMER_BUF0_LOW_S) +#define LP_TIMER_MAIN_TIMER_BUF0_LOW_V 0xFFFFFFFFU +#define LP_TIMER_MAIN_TIMER_BUF0_LOW_S 0 + +/** LP_TIMER_MAIN_BUF0_HIGH_REG register + * need_des + */ +#define LP_TIMER_MAIN_BUF0_HIGH_REG (DR_REG_LP_TIMER_BASE + 0x18) +/** LP_TIMER_MAIN_TIMER_BUF0_HIGH : RO; bitpos: [15:0]; default: 0; + * need_des + */ +#define LP_TIMER_MAIN_TIMER_BUF0_HIGH 0x0000FFFFU +#define LP_TIMER_MAIN_TIMER_BUF0_HIGH_M (LP_TIMER_MAIN_TIMER_BUF0_HIGH_V << LP_TIMER_MAIN_TIMER_BUF0_HIGH_S) +#define LP_TIMER_MAIN_TIMER_BUF0_HIGH_V 0x0000FFFFU +#define LP_TIMER_MAIN_TIMER_BUF0_HIGH_S 0 + +/** LP_TIMER_MAIN_BUF1_LOW_REG register + * need_des + */ +#define LP_TIMER_MAIN_BUF1_LOW_REG (DR_REG_LP_TIMER_BASE + 0x1c) +/** LP_TIMER_MAIN_TIMER_BUF1_LOW : RO; bitpos: [31:0]; default: 0; + * need_des + */ +#define LP_TIMER_MAIN_TIMER_BUF1_LOW 0xFFFFFFFFU +#define LP_TIMER_MAIN_TIMER_BUF1_LOW_M (LP_TIMER_MAIN_TIMER_BUF1_LOW_V << LP_TIMER_MAIN_TIMER_BUF1_LOW_S) +#define LP_TIMER_MAIN_TIMER_BUF1_LOW_V 0xFFFFFFFFU +#define LP_TIMER_MAIN_TIMER_BUF1_LOW_S 0 + +/** LP_TIMER_MAIN_BUF1_HIGH_REG register + * need_des + */ +#define LP_TIMER_MAIN_BUF1_HIGH_REG (DR_REG_LP_TIMER_BASE + 0x20) +/** LP_TIMER_MAIN_TIMER_BUF1_HIGH : RO; bitpos: [15:0]; default: 0; + * need_des + */ +#define LP_TIMER_MAIN_TIMER_BUF1_HIGH 0x0000FFFFU +#define LP_TIMER_MAIN_TIMER_BUF1_HIGH_M (LP_TIMER_MAIN_TIMER_BUF1_HIGH_V << LP_TIMER_MAIN_TIMER_BUF1_HIGH_S) +#define LP_TIMER_MAIN_TIMER_BUF1_HIGH_V 0x0000FFFFU +#define LP_TIMER_MAIN_TIMER_BUF1_HIGH_S 0 + +/** LP_TIMER_MAIN_OVERFLOW_REG register + * need_des + */ +#define LP_TIMER_MAIN_OVERFLOW_REG (DR_REG_LP_TIMER_BASE + 0x24) +/** LP_TIMER_MAIN_TIMER_ALARM_LOAD : WT; bitpos: [31]; default: 0; + * need_des + */ +#define LP_TIMER_MAIN_TIMER_ALARM_LOAD (BIT(31)) +#define LP_TIMER_MAIN_TIMER_ALARM_LOAD_M (LP_TIMER_MAIN_TIMER_ALARM_LOAD_V << LP_TIMER_MAIN_TIMER_ALARM_LOAD_S) +#define LP_TIMER_MAIN_TIMER_ALARM_LOAD_V 0x00000001U +#define LP_TIMER_MAIN_TIMER_ALARM_LOAD_S 31 + +/** LP_TIMER_INT_RAW_REG register + * need_des + */ +#define LP_TIMER_INT_RAW_REG (DR_REG_LP_TIMER_BASE + 0x28) +/** LP_TIMER_OVERFLOW_RAW : R/WTC/SS; bitpos: [30]; default: 0; + * need_des + */ +#define LP_TIMER_OVERFLOW_RAW (BIT(30)) +#define LP_TIMER_OVERFLOW_RAW_M (LP_TIMER_OVERFLOW_RAW_V << LP_TIMER_OVERFLOW_RAW_S) +#define LP_TIMER_OVERFLOW_RAW_V 0x00000001U +#define LP_TIMER_OVERFLOW_RAW_S 30 +/** LP_TIMER_SOC_WAKEUP_INT_RAW : R/WTC/SS; bitpos: [31]; default: 0; + * need_des + */ +#define LP_TIMER_SOC_WAKEUP_INT_RAW (BIT(31)) +#define LP_TIMER_SOC_WAKEUP_INT_RAW_M (LP_TIMER_SOC_WAKEUP_INT_RAW_V << LP_TIMER_SOC_WAKEUP_INT_RAW_S) +#define LP_TIMER_SOC_WAKEUP_INT_RAW_V 0x00000001U +#define LP_TIMER_SOC_WAKEUP_INT_RAW_S 31 + +/** LP_TIMER_INT_ST_REG register + * need_des + */ +#define LP_TIMER_INT_ST_REG (DR_REG_LP_TIMER_BASE + 0x2c) +/** LP_TIMER_OVERFLOW_ST : RO; bitpos: [30]; default: 0; + * need_des + */ +#define LP_TIMER_OVERFLOW_ST (BIT(30)) +#define LP_TIMER_OVERFLOW_ST_M (LP_TIMER_OVERFLOW_ST_V << LP_TIMER_OVERFLOW_ST_S) +#define LP_TIMER_OVERFLOW_ST_V 0x00000001U +#define LP_TIMER_OVERFLOW_ST_S 30 +/** LP_TIMER_SOC_WAKEUP_INT_ST : RO; bitpos: [31]; default: 0; + * need_des + */ +#define LP_TIMER_SOC_WAKEUP_INT_ST (BIT(31)) +#define LP_TIMER_SOC_WAKEUP_INT_ST_M (LP_TIMER_SOC_WAKEUP_INT_ST_V << LP_TIMER_SOC_WAKEUP_INT_ST_S) +#define LP_TIMER_SOC_WAKEUP_INT_ST_V 0x00000001U +#define LP_TIMER_SOC_WAKEUP_INT_ST_S 31 + +/** LP_TIMER_INT_ENA_REG register + * need_des + */ +#define LP_TIMER_INT_ENA_REG (DR_REG_LP_TIMER_BASE + 0x30) +/** LP_TIMER_OVERFLOW_ENA : R/W; bitpos: [30]; default: 0; + * need_des + */ +#define LP_TIMER_OVERFLOW_ENA (BIT(30)) +#define LP_TIMER_OVERFLOW_ENA_M (LP_TIMER_OVERFLOW_ENA_V << LP_TIMER_OVERFLOW_ENA_S) +#define LP_TIMER_OVERFLOW_ENA_V 0x00000001U +#define LP_TIMER_OVERFLOW_ENA_S 30 +/** LP_TIMER_SOC_WAKEUP_INT_ENA : R/W; bitpos: [31]; default: 0; + * need_des + */ +#define LP_TIMER_SOC_WAKEUP_INT_ENA (BIT(31)) +#define LP_TIMER_SOC_WAKEUP_INT_ENA_M (LP_TIMER_SOC_WAKEUP_INT_ENA_V << LP_TIMER_SOC_WAKEUP_INT_ENA_S) +#define LP_TIMER_SOC_WAKEUP_INT_ENA_V 0x00000001U +#define LP_TIMER_SOC_WAKEUP_INT_ENA_S 31 + +/** LP_TIMER_INT_CLR_REG register + * need_des + */ +#define LP_TIMER_INT_CLR_REG (DR_REG_LP_TIMER_BASE + 0x34) +/** LP_TIMER_OVERFLOW_CLR : WT; bitpos: [30]; default: 0; + * need_des + */ +#define LP_TIMER_OVERFLOW_CLR (BIT(30)) +#define LP_TIMER_OVERFLOW_CLR_M (LP_TIMER_OVERFLOW_CLR_V << LP_TIMER_OVERFLOW_CLR_S) +#define LP_TIMER_OVERFLOW_CLR_V 0x00000001U +#define LP_TIMER_OVERFLOW_CLR_S 30 +/** LP_TIMER_SOC_WAKEUP_INT_CLR : WT; bitpos: [31]; default: 0; + * need_des + */ +#define LP_TIMER_SOC_WAKEUP_INT_CLR (BIT(31)) +#define LP_TIMER_SOC_WAKEUP_INT_CLR_M (LP_TIMER_SOC_WAKEUP_INT_CLR_V << LP_TIMER_SOC_WAKEUP_INT_CLR_S) +#define LP_TIMER_SOC_WAKEUP_INT_CLR_V 0x00000001U +#define LP_TIMER_SOC_WAKEUP_INT_CLR_S 31 + +/** LP_TIMER_DATE_REG register + * need_des + */ +#define LP_TIMER_DATE_REG (DR_REG_LP_TIMER_BASE + 0x3fc) +/** LP_TIMER_DATE : R/W; bitpos: [30:0]; default: 37785904; + * need_des + */ +#define LP_TIMER_DATE 0x7FFFFFFFU +#define LP_TIMER_DATE_M (LP_TIMER_DATE_V << LP_TIMER_DATE_S) +#define LP_TIMER_DATE_V 0x7FFFFFFFU +#define LP_TIMER_DATE_S 0 +/** LP_TIMER_CLK_EN : R/W; bitpos: [31]; default: 0; + * need_des + */ +#define LP_TIMER_CLK_EN (BIT(31)) +#define LP_TIMER_CLK_EN_M (LP_TIMER_CLK_EN_V << LP_TIMER_CLK_EN_S) +#define LP_TIMER_CLK_EN_V 0x00000001U +#define LP_TIMER_CLK_EN_S 31 + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32h21/register/soc/lp_timer_struct.h b/components/soc/esp32h21/register/soc/lp_timer_struct.h new file mode 100644 index 00000000000..942322114f5 --- /dev/null +++ b/components/soc/esp32h21/register/soc/lp_timer_struct.h @@ -0,0 +1,258 @@ +/** + * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#ifdef __cplusplus +extern "C" { +#endif + +/** Group: configure_register */ +/** Type of timer_tar0_low register + * need_des + */ +typedef union { + struct { + /** timer_main_timer_tar_low0 : R/W; bitpos: [31:0]; default: 0; + * need_des + */ + uint32_t timer_main_timer_tar_low0:32; + }; + uint32_t val; +} lp_timer_tar0_low_reg_t; + +/** Type of timer_tar0_high register + * need_des + */ +typedef union { + struct { + /** timer_main_timer_tar_high0 : R/W; bitpos: [15:0]; default: 0; + * need_des + */ + uint32_t timer_main_timer_tar_high0:16; + uint32_t reserved_16:15; + /** timer_main_timer_tar_en0 : WT; bitpos: [31]; default: 0; + * need_des + */ + uint32_t timer_main_timer_tar_en0:1; + }; + uint32_t val; +} lp_timer_tar0_high_reg_t; + +/** Type of timer_update register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:27; + /** timer_main_timer_update : WT; bitpos: [27]; default: 0; + * need_des + */ + uint32_t timer_main_timer_update:1; + /** timer_main_timer_regdma_work : R/W; bitpos: [28]; default: 0; + * Selects the triggering condition for the RTC timer,triggered when regdma working + */ + uint32_t timer_main_timer_regdma_work:1; + /** timer_main_timer_xtal_off : R/W; bitpos: [29]; default: 0; + * need_des + */ + uint32_t timer_main_timer_xtal_off:1; + /** timer_main_timer_sys_stall : R/W; bitpos: [30]; default: 0; + * need_des + */ + uint32_t timer_main_timer_sys_stall:1; + /** timer_main_timer_sys_rst : R/W; bitpos: [31]; default: 0; + * need_des + */ + uint32_t timer_main_timer_sys_rst:1; + }; + uint32_t val; +} lp_timer_update_reg_t; + +/** Type of timer_main_buf0_low register + * need_des + */ +typedef union { + struct { + /** timer_main_timer_buf0_low : RO; bitpos: [31:0]; default: 0; + * need_des + */ + uint32_t timer_main_timer_buf0_low:32; + }; + uint32_t val; +} lp_timer_main_buf0_low_reg_t; + +/** Type of timer_main_buf0_high register + * need_des + */ +typedef union { + struct { + /** timer_main_timer_buf0_high : RO; bitpos: [15:0]; default: 0; + * need_des + */ + uint32_t timer_main_timer_buf0_high:16; + uint32_t reserved_16:16; + }; + uint32_t val; +} lp_timer_main_buf0_high_reg_t; + +/** Type of timer_main_buf1_low register + * need_des + */ +typedef union { + struct { + /** timer_main_timer_buf1_low : RO; bitpos: [31:0]; default: 0; + * need_des + */ + uint32_t timer_main_timer_buf1_low:32; + }; + uint32_t val; +} lp_timer_main_buf1_low_reg_t; + +/** Type of timer_main_buf1_high register + * need_des + */ +typedef union { + struct { + /** timer_main_timer_buf1_high : RO; bitpos: [15:0]; default: 0; + * need_des + */ + uint32_t timer_main_timer_buf1_high:16; + uint32_t reserved_16:16; + }; + uint32_t val; +} lp_timer_main_buf1_high_reg_t; + +/** Type of timer_main_overflow register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:31; + /** timer_main_timer_alarm_load : WT; bitpos: [31]; default: 0; + * need_des + */ + uint32_t timer_main_timer_alarm_load:1; + }; + uint32_t val; +} lp_timer_main_overflow_reg_t; + +/** Type of timer_int_raw register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:30; + /** timer_overflow_raw : R/WTC/SS; bitpos: [30]; default: 0; + * need_des + */ + uint32_t timer_overflow_raw:1; + /** timer_soc_wakeup_int_raw : R/WTC/SS; bitpos: [31]; default: 0; + * need_des + */ + uint32_t timer_soc_wakeup_int_raw:1; + }; + uint32_t val; +} lp_timer_int_raw_reg_t; + +/** Type of timer_int_st register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:30; + /** timer_overflow_st : RO; bitpos: [30]; default: 0; + * need_des + */ + uint32_t timer_overflow_st:1; + /** timer_soc_wakeup_int_st : RO; bitpos: [31]; default: 0; + * need_des + */ + uint32_t timer_soc_wakeup_int_st:1; + }; + uint32_t val; +} lp_timer_int_st_reg_t; + +/** Type of timer_int_ena register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:30; + /** timer_overflow_ena : R/W; bitpos: [30]; default: 0; + * need_des + */ + uint32_t timer_overflow_ena:1; + /** timer_soc_wakeup_int_ena : R/W; bitpos: [31]; default: 0; + * need_des + */ + uint32_t timer_soc_wakeup_int_ena:1; + }; + uint32_t val; +} lp_timer_int_ena_reg_t; + +/** Type of timer_int_clr register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:30; + /** timer_overflow_clr : WT; bitpos: [30]; default: 0; + * need_des + */ + uint32_t timer_overflow_clr:1; + /** timer_soc_wakeup_int_clr : WT; bitpos: [31]; default: 0; + * need_des + */ + uint32_t timer_soc_wakeup_int_clr:1; + }; + uint32_t val; +} lp_timer_int_clr_reg_t; + +/** Type of timer_date register + * need_des + */ +typedef union { + struct { + /** timer_date : R/W; bitpos: [30:0]; default: 37785904; + * need_des + */ + uint32_t timer_date:31; + /** timer_clk_en : R/W; bitpos: [31]; default: 0; + * need_des + */ + uint32_t timer_clk_en:1; + }; + uint32_t val; +} lp_timer_date_reg_t; + + +typedef struct { + volatile lp_timer_tar0_low_reg_t timer_tar0_low; + volatile lp_timer_tar0_high_reg_t timer_tar0_high; + uint32_t reserved_008[2]; + volatile lp_timer_update_reg_t timer_update; + volatile lp_timer_main_buf0_low_reg_t timer_main_buf0_low; + volatile lp_timer_main_buf0_high_reg_t timer_main_buf0_high; + volatile lp_timer_main_buf1_low_reg_t timer_main_buf1_low; + volatile lp_timer_main_buf1_high_reg_t timer_main_buf1_high; + volatile lp_timer_main_overflow_reg_t timer_main_overflow; + volatile lp_timer_int_raw_reg_t timer_int_raw; + volatile lp_timer_int_st_reg_t timer_int_st; + volatile lp_timer_int_ena_reg_t timer_int_ena; + volatile lp_timer_int_clr_reg_t timer_int_clr; + uint32_t reserved_038[241]; + volatile lp_timer_date_reg_t timer_date; +} lp_dev_t; + + +#ifndef __cplusplus +_Static_assert(sizeof(lp_dev_t) == 0x400, "Invalid size of lp_dev_t structure"); +#endif + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32h21/register/soc/lpperi_reg.h b/components/soc/esp32h21/register/soc/lpperi_reg.h new file mode 100644 index 00000000000..593e87e2e10 --- /dev/null +++ b/components/soc/esp32h21/register/soc/lpperi_reg.h @@ -0,0 +1,388 @@ +/** + * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#include "soc/soc.h" +#ifdef __cplusplus +extern "C" { +#endif + +/** LPPERI_CLK_EN_REG register + * need_des + */ +#define LPPERI_CLK_EN_REG (DR_REG_LPPERI_BASE + 0x0) +/** LPPERI_RNG_CK_EN : R/W; bitpos: [24]; default: 1; + * need_des + */ +#define LPPERI_RNG_CK_EN (BIT(24)) +#define LPPERI_RNG_CK_EN_M (LPPERI_RNG_CK_EN_V << LPPERI_RNG_CK_EN_S) +#define LPPERI_RNG_CK_EN_V 0x00000001U +#define LPPERI_RNG_CK_EN_S 24 +/** LPPERI_OTP_DBG_CK_EN : R/W; bitpos: [25]; default: 1; + * need_des + */ +#define LPPERI_OTP_DBG_CK_EN (BIT(25)) +#define LPPERI_OTP_DBG_CK_EN_M (LPPERI_OTP_DBG_CK_EN_V << LPPERI_OTP_DBG_CK_EN_S) +#define LPPERI_OTP_DBG_CK_EN_V 0x00000001U +#define LPPERI_OTP_DBG_CK_EN_S 25 +/** LPPERI_LP_UART_CK_EN : R/W; bitpos: [26]; default: 1; + * need_des + */ +#define LPPERI_LP_UART_CK_EN (BIT(26)) +#define LPPERI_LP_UART_CK_EN_M (LPPERI_LP_UART_CK_EN_V << LPPERI_LP_UART_CK_EN_S) +#define LPPERI_LP_UART_CK_EN_V 0x00000001U +#define LPPERI_LP_UART_CK_EN_S 26 +/** LPPERI_LP_IO_CK_EN : R/W; bitpos: [27]; default: 1; + * need_des + */ +#define LPPERI_LP_IO_CK_EN (BIT(27)) +#define LPPERI_LP_IO_CK_EN_M (LPPERI_LP_IO_CK_EN_V << LPPERI_LP_IO_CK_EN_S) +#define LPPERI_LP_IO_CK_EN_V 0x00000001U +#define LPPERI_LP_IO_CK_EN_S 27 +/** LPPERI_LP_EXT_I2C_CK_EN : R/W; bitpos: [28]; default: 1; + * need_des + */ +#define LPPERI_LP_EXT_I2C_CK_EN (BIT(28)) +#define LPPERI_LP_EXT_I2C_CK_EN_M (LPPERI_LP_EXT_I2C_CK_EN_V << LPPERI_LP_EXT_I2C_CK_EN_S) +#define LPPERI_LP_EXT_I2C_CK_EN_V 0x00000001U +#define LPPERI_LP_EXT_I2C_CK_EN_S 28 +/** LPPERI_LP_ANA_I2C_CK_EN : R/W; bitpos: [29]; default: 1; + * need_des + */ +#define LPPERI_LP_ANA_I2C_CK_EN (BIT(29)) +#define LPPERI_LP_ANA_I2C_CK_EN_M (LPPERI_LP_ANA_I2C_CK_EN_V << LPPERI_LP_ANA_I2C_CK_EN_S) +#define LPPERI_LP_ANA_I2C_CK_EN_V 0x00000001U +#define LPPERI_LP_ANA_I2C_CK_EN_S 29 +/** LPPERI_EFUSE_CK_EN : R/W; bitpos: [30]; default: 1; + * need_des + */ +#define LPPERI_EFUSE_CK_EN (BIT(30)) +#define LPPERI_EFUSE_CK_EN_M (LPPERI_EFUSE_CK_EN_V << LPPERI_EFUSE_CK_EN_S) +#define LPPERI_EFUSE_CK_EN_V 0x00000001U +#define LPPERI_EFUSE_CK_EN_S 30 +/** LPPERI_LP_CPU_CK_EN : R/W; bitpos: [31]; default: 0; + * need_des + */ +#define LPPERI_LP_CPU_CK_EN (BIT(31)) +#define LPPERI_LP_CPU_CK_EN_M (LPPERI_LP_CPU_CK_EN_V << LPPERI_LP_CPU_CK_EN_S) +#define LPPERI_LP_CPU_CK_EN_V 0x00000001U +#define LPPERI_LP_CPU_CK_EN_S 31 + +/** LPPERI_RESET_EN_REG register + * need_des + */ +#define LPPERI_RESET_EN_REG (DR_REG_LPPERI_BASE + 0x4) +/** LPPERI_BUS_RESET_EN : WT; bitpos: [23]; default: 0; + * need_des + */ +#define LPPERI_BUS_RESET_EN (BIT(23)) +#define LPPERI_BUS_RESET_EN_M (LPPERI_BUS_RESET_EN_V << LPPERI_BUS_RESET_EN_S) +#define LPPERI_BUS_RESET_EN_V 0x00000001U +#define LPPERI_BUS_RESET_EN_S 23 +/** LPPERI_LP_BLE_TIMER_RESET_EN : R/W; bitpos: [24]; default: 0; + * need_des + */ +#define LPPERI_LP_BLE_TIMER_RESET_EN (BIT(24)) +#define LPPERI_LP_BLE_TIMER_RESET_EN_M (LPPERI_LP_BLE_TIMER_RESET_EN_V << LPPERI_LP_BLE_TIMER_RESET_EN_S) +#define LPPERI_LP_BLE_TIMER_RESET_EN_V 0x00000001U +#define LPPERI_LP_BLE_TIMER_RESET_EN_S 24 +/** LPPERI_OTP_DBG_RESET_EN : R/W; bitpos: [25]; default: 0; + * need_des + */ +#define LPPERI_OTP_DBG_RESET_EN (BIT(25)) +#define LPPERI_OTP_DBG_RESET_EN_M (LPPERI_OTP_DBG_RESET_EN_V << LPPERI_OTP_DBG_RESET_EN_S) +#define LPPERI_OTP_DBG_RESET_EN_V 0x00000001U +#define LPPERI_OTP_DBG_RESET_EN_S 25 +/** LPPERI_LP_UART_RESET_EN : R/W; bitpos: [26]; default: 0; + * need_des + */ +#define LPPERI_LP_UART_RESET_EN (BIT(26)) +#define LPPERI_LP_UART_RESET_EN_M (LPPERI_LP_UART_RESET_EN_V << LPPERI_LP_UART_RESET_EN_S) +#define LPPERI_LP_UART_RESET_EN_V 0x00000001U +#define LPPERI_LP_UART_RESET_EN_S 26 +/** LPPERI_LP_IO_RESET_EN : R/W; bitpos: [27]; default: 0; + * need_des + */ +#define LPPERI_LP_IO_RESET_EN (BIT(27)) +#define LPPERI_LP_IO_RESET_EN_M (LPPERI_LP_IO_RESET_EN_V << LPPERI_LP_IO_RESET_EN_S) +#define LPPERI_LP_IO_RESET_EN_V 0x00000001U +#define LPPERI_LP_IO_RESET_EN_S 27 +/** LPPERI_LP_EXT_I2C_RESET_EN : R/W; bitpos: [28]; default: 0; + * need_des + */ +#define LPPERI_LP_EXT_I2C_RESET_EN (BIT(28)) +#define LPPERI_LP_EXT_I2C_RESET_EN_M (LPPERI_LP_EXT_I2C_RESET_EN_V << LPPERI_LP_EXT_I2C_RESET_EN_S) +#define LPPERI_LP_EXT_I2C_RESET_EN_V 0x00000001U +#define LPPERI_LP_EXT_I2C_RESET_EN_S 28 +/** LPPERI_LP_ANA_I2C_RESET_EN : R/W; bitpos: [29]; default: 0; + * need_des + */ +#define LPPERI_LP_ANA_I2C_RESET_EN (BIT(29)) +#define LPPERI_LP_ANA_I2C_RESET_EN_M (LPPERI_LP_ANA_I2C_RESET_EN_V << LPPERI_LP_ANA_I2C_RESET_EN_S) +#define LPPERI_LP_ANA_I2C_RESET_EN_V 0x00000001U +#define LPPERI_LP_ANA_I2C_RESET_EN_S 29 +/** LPPERI_EFUSE_RESET_EN : R/W; bitpos: [30]; default: 0; + * need_des + */ +#define LPPERI_EFUSE_RESET_EN (BIT(30)) +#define LPPERI_EFUSE_RESET_EN_M (LPPERI_EFUSE_RESET_EN_V << LPPERI_EFUSE_RESET_EN_S) +#define LPPERI_EFUSE_RESET_EN_V 0x00000001U +#define LPPERI_EFUSE_RESET_EN_S 30 +/** LPPERI_LP_CPU_RESET_EN : WT; bitpos: [31]; default: 0; + * need_des + */ +#define LPPERI_LP_CPU_RESET_EN (BIT(31)) +#define LPPERI_LP_CPU_RESET_EN_M (LPPERI_LP_CPU_RESET_EN_V << LPPERI_LP_CPU_RESET_EN_S) +#define LPPERI_LP_CPU_RESET_EN_V 0x00000001U +#define LPPERI_LP_CPU_RESET_EN_S 31 + +/** LPPERI_RNG_CFG_REG register + * need_des + */ +#define LPPERI_RNG_CFG_REG (DR_REG_LPPERI_BASE + 0x8) +/** LPPERI_RNG_SAMPLE_ENABLE : R/W; bitpos: [0]; default: 0; + * need des + */ +#define LPPERI_RNG_SAMPLE_ENABLE (BIT(0)) +#define LPPERI_RNG_SAMPLE_ENABLE_M (LPPERI_RNG_SAMPLE_ENABLE_V << LPPERI_RNG_SAMPLE_ENABLE_S) +#define LPPERI_RNG_SAMPLE_ENABLE_V 0x00000001U +#define LPPERI_RNG_SAMPLE_ENABLE_S 0 +/** LPPERI_RNG_TIMER_PSCALE : R/W; bitpos: [8:1]; default: 255; + * need des + */ +#define LPPERI_RNG_TIMER_PSCALE 0x000000FFU +#define LPPERI_RNG_TIMER_PSCALE_M (LPPERI_RNG_TIMER_PSCALE_V << LPPERI_RNG_TIMER_PSCALE_S) +#define LPPERI_RNG_TIMER_PSCALE_V 0x000000FFU +#define LPPERI_RNG_TIMER_PSCALE_S 1 +/** LPPERI_RNG_TIMER_EN : R/W; bitpos: [9]; default: 1; + * need des + */ +#define LPPERI_RNG_TIMER_EN (BIT(9)) +#define LPPERI_RNG_TIMER_EN_M (LPPERI_RNG_TIMER_EN_V << LPPERI_RNG_TIMER_EN_S) +#define LPPERI_RNG_TIMER_EN_V 0x00000001U +#define LPPERI_RNG_TIMER_EN_S 9 +/** LPPERI_RTC_TIMER_EN : R/W; bitpos: [11:10]; default: 3; + * need des + */ +#define LPPERI_RTC_TIMER_EN 0x00000003U +#define LPPERI_RTC_TIMER_EN_M (LPPERI_RTC_TIMER_EN_V << LPPERI_RTC_TIMER_EN_S) +#define LPPERI_RTC_TIMER_EN_V 0x00000003U +#define LPPERI_RTC_TIMER_EN_S 10 +/** LPPERI_RNG_SAMPLE_CNT : RO; bitpos: [31:24]; default: 0; + * need des + */ +#define LPPERI_RNG_SAMPLE_CNT 0x000000FFU +#define LPPERI_RNG_SAMPLE_CNT_M (LPPERI_RNG_SAMPLE_CNT_V << LPPERI_RNG_SAMPLE_CNT_S) +#define LPPERI_RNG_SAMPLE_CNT_V 0x000000FFU +#define LPPERI_RNG_SAMPLE_CNT_S 24 + +/** LPPERI_RNG_DATA_REG register + * need_des + */ +#define LPPERI_RNG_DATA_REG (DR_REG_LPPERI_BASE + 0xc) +/** LPPERI_RND_DATA : RO; bitpos: [31:0]; default: 0; + * need_des + */ +#define LPPERI_RND_DATA 0xFFFFFFFFU +#define LPPERI_RND_DATA_M (LPPERI_RND_DATA_V << LPPERI_RND_DATA_S) +#define LPPERI_RND_DATA_V 0xFFFFFFFFU +#define LPPERI_RND_DATA_S 0 + +/** LPPERI_CPU_REG register + * need_des + */ +#define LPPERI_CPU_REG (DR_REG_LPPERI_BASE + 0x10) +/** LPPERI_LPCORE_DBGM_UNAVALIABLE : R/W; bitpos: [31]; default: 1; + * need_des + */ +#define LPPERI_LPCORE_DBGM_UNAVALIABLE (BIT(31)) +#define LPPERI_LPCORE_DBGM_UNAVALIABLE_M (LPPERI_LPCORE_DBGM_UNAVALIABLE_V << LPPERI_LPCORE_DBGM_UNAVALIABLE_S) +#define LPPERI_LPCORE_DBGM_UNAVALIABLE_V 0x00000001U +#define LPPERI_LPCORE_DBGM_UNAVALIABLE_S 31 + +/** LPPERI_BUS_TIMEOUT_REG register + * need_des + */ +#define LPPERI_BUS_TIMEOUT_REG (DR_REG_LPPERI_BASE + 0x14) +/** LPPERI_LP_PERI_TIMEOUT_THRES : R/W; bitpos: [29:14]; default: 65535; + * need_des + */ +#define LPPERI_LP_PERI_TIMEOUT_THRES 0x0000FFFFU +#define LPPERI_LP_PERI_TIMEOUT_THRES_M (LPPERI_LP_PERI_TIMEOUT_THRES_V << LPPERI_LP_PERI_TIMEOUT_THRES_S) +#define LPPERI_LP_PERI_TIMEOUT_THRES_V 0x0000FFFFU +#define LPPERI_LP_PERI_TIMEOUT_THRES_S 14 +/** LPPERI_LP_PERI_TIMEOUT_INT_CLEAR : WT; bitpos: [30]; default: 0; + * need_des + */ +#define LPPERI_LP_PERI_TIMEOUT_INT_CLEAR (BIT(30)) +#define LPPERI_LP_PERI_TIMEOUT_INT_CLEAR_M (LPPERI_LP_PERI_TIMEOUT_INT_CLEAR_V << LPPERI_LP_PERI_TIMEOUT_INT_CLEAR_S) +#define LPPERI_LP_PERI_TIMEOUT_INT_CLEAR_V 0x00000001U +#define LPPERI_LP_PERI_TIMEOUT_INT_CLEAR_S 30 +/** LPPERI_LP_PERI_TIMEOUT_PROTECT_EN : R/W; bitpos: [31]; default: 1; + * need_des + */ +#define LPPERI_LP_PERI_TIMEOUT_PROTECT_EN (BIT(31)) +#define LPPERI_LP_PERI_TIMEOUT_PROTECT_EN_M (LPPERI_LP_PERI_TIMEOUT_PROTECT_EN_V << LPPERI_LP_PERI_TIMEOUT_PROTECT_EN_S) +#define LPPERI_LP_PERI_TIMEOUT_PROTECT_EN_V 0x00000001U +#define LPPERI_LP_PERI_TIMEOUT_PROTECT_EN_S 31 + +/** LPPERI_BUS_TIMEOUT_ADDR_REG register + * need_des + */ +#define LPPERI_BUS_TIMEOUT_ADDR_REG (DR_REG_LPPERI_BASE + 0x18) +/** LPPERI_LP_PERI_TIMEOUT_ADDR : RO; bitpos: [31:0]; default: 0; + * need_des + */ +#define LPPERI_LP_PERI_TIMEOUT_ADDR 0xFFFFFFFFU +#define LPPERI_LP_PERI_TIMEOUT_ADDR_M (LPPERI_LP_PERI_TIMEOUT_ADDR_V << LPPERI_LP_PERI_TIMEOUT_ADDR_S) +#define LPPERI_LP_PERI_TIMEOUT_ADDR_V 0xFFFFFFFFU +#define LPPERI_LP_PERI_TIMEOUT_ADDR_S 0 + +/** LPPERI_BUS_TIMEOUT_UID_REG register + * need_des + */ +#define LPPERI_BUS_TIMEOUT_UID_REG (DR_REG_LPPERI_BASE + 0x1c) +/** LPPERI_LP_PERI_TIMEOUT_UID : RO; bitpos: [6:0]; default: 0; + * need_des + */ +#define LPPERI_LP_PERI_TIMEOUT_UID 0x0000007FU +#define LPPERI_LP_PERI_TIMEOUT_UID_M (LPPERI_LP_PERI_TIMEOUT_UID_V << LPPERI_LP_PERI_TIMEOUT_UID_S) +#define LPPERI_LP_PERI_TIMEOUT_UID_V 0x0000007FU +#define LPPERI_LP_PERI_TIMEOUT_UID_S 0 + +/** LPPERI_MEM_CTRL_REG register + * need_des + */ +#define LPPERI_MEM_CTRL_REG (DR_REG_LPPERI_BASE + 0x20) +/** LPPERI_UART_WAKEUP_FLAG_CLR : WT; bitpos: [0]; default: 0; + * need_des + */ +#define LPPERI_UART_WAKEUP_FLAG_CLR (BIT(0)) +#define LPPERI_UART_WAKEUP_FLAG_CLR_M (LPPERI_UART_WAKEUP_FLAG_CLR_V << LPPERI_UART_WAKEUP_FLAG_CLR_S) +#define LPPERI_UART_WAKEUP_FLAG_CLR_V 0x00000001U +#define LPPERI_UART_WAKEUP_FLAG_CLR_S 0 +/** LPPERI_UART_WAKEUP_FLAG : R/WTC/SS; bitpos: [1]; default: 0; + * need_des + */ +#define LPPERI_UART_WAKEUP_FLAG (BIT(1)) +#define LPPERI_UART_WAKEUP_FLAG_M (LPPERI_UART_WAKEUP_FLAG_V << LPPERI_UART_WAKEUP_FLAG_S) +#define LPPERI_UART_WAKEUP_FLAG_V 0x00000001U +#define LPPERI_UART_WAKEUP_FLAG_S 1 +/** LPPERI_UART_WAKEUP_EN : R/W; bitpos: [29]; default: 0; + * need_des + */ +#define LPPERI_UART_WAKEUP_EN (BIT(29)) +#define LPPERI_UART_WAKEUP_EN_M (LPPERI_UART_WAKEUP_EN_V << LPPERI_UART_WAKEUP_EN_S) +#define LPPERI_UART_WAKEUP_EN_V 0x00000001U +#define LPPERI_UART_WAKEUP_EN_S 29 +/** LPPERI_UART_MEM_FORCE_PD : R/W; bitpos: [30]; default: 0; + * need_des + */ +#define LPPERI_UART_MEM_FORCE_PD (BIT(30)) +#define LPPERI_UART_MEM_FORCE_PD_M (LPPERI_UART_MEM_FORCE_PD_V << LPPERI_UART_MEM_FORCE_PD_S) +#define LPPERI_UART_MEM_FORCE_PD_V 0x00000001U +#define LPPERI_UART_MEM_FORCE_PD_S 30 +/** LPPERI_UART_MEM_FORCE_PU : R/W; bitpos: [31]; default: 1; + * need_des + */ +#define LPPERI_UART_MEM_FORCE_PU (BIT(31)) +#define LPPERI_UART_MEM_FORCE_PU_M (LPPERI_UART_MEM_FORCE_PU_V << LPPERI_UART_MEM_FORCE_PU_S) +#define LPPERI_UART_MEM_FORCE_PU_V 0x00000001U +#define LPPERI_UART_MEM_FORCE_PU_S 31 + +/** LPPERI_INTERRUPT_SOURCE_REG register + * need_des + */ +#define LPPERI_INTERRUPT_SOURCE_REG (DR_REG_LPPERI_BASE + 0x24) +/** LPPERI_LP_INTERRUPT_SOURCE : RO; bitpos: [5:0]; default: 0; + * BIT5~BIT0: pmu_lp_int, modem_lp_int, lp_timer_lp_int, lp_uart_int, lp_i2c_int, + * lp_io_int + */ +#define LPPERI_LP_INTERRUPT_SOURCE 0x0000003FU +#define LPPERI_LP_INTERRUPT_SOURCE_M (LPPERI_LP_INTERRUPT_SOURCE_V << LPPERI_LP_INTERRUPT_SOURCE_S) +#define LPPERI_LP_INTERRUPT_SOURCE_V 0x0000003FU +#define LPPERI_LP_INTERRUPT_SOURCE_S 0 + +/** LPPERI_DEBUG_SEL0_REG register + * need des + */ +#define LPPERI_DEBUG_SEL0_REG (DR_REG_LPPERI_BASE + 0x28) +/** LPPERI_DEBUG_SEL0 : R/W; bitpos: [6:0]; default: 0; + * need des + */ +#define LPPERI_DEBUG_SEL0 0x0000007FU +#define LPPERI_DEBUG_SEL0_M (LPPERI_DEBUG_SEL0_V << LPPERI_DEBUG_SEL0_S) +#define LPPERI_DEBUG_SEL0_V 0x0000007FU +#define LPPERI_DEBUG_SEL0_S 0 +/** LPPERI_DEBUG_SEL1 : R/W; bitpos: [13:7]; default: 0; + * need des + */ +#define LPPERI_DEBUG_SEL1 0x0000007FU +#define LPPERI_DEBUG_SEL1_M (LPPERI_DEBUG_SEL1_V << LPPERI_DEBUG_SEL1_S) +#define LPPERI_DEBUG_SEL1_V 0x0000007FU +#define LPPERI_DEBUG_SEL1_S 7 +/** LPPERI_DEBUG_SEL2 : R/W; bitpos: [20:14]; default: 0; + * need des + */ +#define LPPERI_DEBUG_SEL2 0x0000007FU +#define LPPERI_DEBUG_SEL2_M (LPPERI_DEBUG_SEL2_V << LPPERI_DEBUG_SEL2_S) +#define LPPERI_DEBUG_SEL2_V 0x0000007FU +#define LPPERI_DEBUG_SEL2_S 14 +/** LPPERI_DEBUG_SEL3 : R/W; bitpos: [27:21]; default: 0; + * need des + */ +#define LPPERI_DEBUG_SEL3 0x0000007FU +#define LPPERI_DEBUG_SEL3_M (LPPERI_DEBUG_SEL3_V << LPPERI_DEBUG_SEL3_S) +#define LPPERI_DEBUG_SEL3_V 0x0000007FU +#define LPPERI_DEBUG_SEL3_S 21 + +/** LPPERI_DEBUG_SEL1_REG register + * need des + */ +#define LPPERI_DEBUG_SEL1_REG (DR_REG_LPPERI_BASE + 0x2c) +/** LPPERI_DEBUG_SEL4 : R/W; bitpos: [6:0]; default: 0; + * need des + */ +#define LPPERI_DEBUG_SEL4 0x0000007FU +#define LPPERI_DEBUG_SEL4_M (LPPERI_DEBUG_SEL4_V << LPPERI_DEBUG_SEL4_S) +#define LPPERI_DEBUG_SEL4_V 0x0000007FU +#define LPPERI_DEBUG_SEL4_S 0 + +/** LPPERI_RNG_DATA_SYNC_REG register + * rng result sync register + */ +#define LPPERI_RNG_DATA_SYNC_REG (DR_REG_LPPERI_BASE + 0x30) +/** LPPERI_RND_SYNC_DATA : RO; bitpos: [31:0]; default: 0; + * get rng sync result + */ +#define LPPERI_RND_SYNC_DATA 0xFFFFFFFFU +#define LPPERI_RND_SYNC_DATA_M (LPPERI_RND_SYNC_DATA_V << LPPERI_RND_SYNC_DATA_S) +#define LPPERI_RND_SYNC_DATA_V 0xFFFFFFFFU +#define LPPERI_RND_SYNC_DATA_S 0 + +/** LPPERI_DATE_REG register + * need_des + */ +#define LPPERI_DATE_REG (DR_REG_LPPERI_BASE + 0x3fc) +/** LPPERI_LPPERI_DATE : R/W; bitpos: [30:0]; default: 37781793; + * need_des + */ +#define LPPERI_LPPERI_DATE 0x7FFFFFFFU +#define LPPERI_LPPERI_DATE_M (LPPERI_LPPERI_DATE_V << LPPERI_LPPERI_DATE_S) +#define LPPERI_LPPERI_DATE_V 0x7FFFFFFFU +#define LPPERI_LPPERI_DATE_S 0 +/** LPPERI_CLK_EN : R/W; bitpos: [31]; default: 0; + * need_des + */ +#define LPPERI_CLK_EN (BIT(31)) +#define LPPERI_CLK_EN_M (LPPERI_CLK_EN_V << LPPERI_CLK_EN_S) +#define LPPERI_CLK_EN_V 0x00000001U +#define LPPERI_CLK_EN_S 31 + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32h21/register/soc/lpperi_struct.h b/components/soc/esp32h21/register/soc/lpperi_struct.h new file mode 100644 index 00000000000..4ccec691b91 --- /dev/null +++ b/components/soc/esp32h21/register/soc/lpperi_struct.h @@ -0,0 +1,352 @@ +/** + * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#ifdef __cplusplus +extern "C" { +#endif + +/** Group: configure_register */ +/** Type of clk_en register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:24; + /** rng_ck_en : R/W; bitpos: [24]; default: 1; + * need_des + */ + uint32_t rng_ck_en:1; + /** otp_dbg_ck_en : R/W; bitpos: [25]; default: 1; + * need_des + */ + uint32_t otp_dbg_ck_en:1; + /** lp_uart_ck_en : R/W; bitpos: [26]; default: 1; + * need_des + */ + uint32_t lp_uart_ck_en:1; + /** lp_io_ck_en : R/W; bitpos: [27]; default: 1; + * need_des + */ + uint32_t lp_io_ck_en:1; + /** lp_ext_i2c_ck_en : R/W; bitpos: [28]; default: 1; + * need_des + */ + uint32_t lp_ext_i2c_ck_en:1; + /** lp_ana_i2c_ck_en : R/W; bitpos: [29]; default: 1; + * need_des + */ + uint32_t lp_ana_i2c_ck_en:1; + /** efuse_ck_en : R/W; bitpos: [30]; default: 1; + * need_des + */ + uint32_t efuse_ck_en:1; + /** lp_cpu_ck_en : R/W; bitpos: [31]; default: 0; + * need_des + */ + uint32_t lp_cpu_ck_en:1; + }; + uint32_t val; +} lpperi_clk_en_reg_t; + +/** Type of reset_en register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:23; + /** bus_reset_en : WT; bitpos: [23]; default: 0; + * need_des + */ + uint32_t bus_reset_en:1; + /** lp_ble_timer_reset_en : R/W; bitpos: [24]; default: 0; + * need_des + */ + uint32_t lp_ble_timer_reset_en:1; + /** otp_dbg_reset_en : R/W; bitpos: [25]; default: 0; + * need_des + */ + uint32_t otp_dbg_reset_en:1; + /** lp_uart_reset_en : R/W; bitpos: [26]; default: 0; + * need_des + */ + uint32_t lp_uart_reset_en:1; + /** lp_io_reset_en : R/W; bitpos: [27]; default: 0; + * need_des + */ + uint32_t lp_io_reset_en:1; + /** lp_ext_i2c_reset_en : R/W; bitpos: [28]; default: 0; + * need_des + */ + uint32_t lp_ext_i2c_reset_en:1; + /** lp_ana_i2c_reset_en : R/W; bitpos: [29]; default: 0; + * need_des + */ + uint32_t lp_ana_i2c_reset_en:1; + /** efuse_reset_en : R/W; bitpos: [30]; default: 0; + * need_des + */ + uint32_t efuse_reset_en:1; + /** lp_cpu_reset_en : WT; bitpos: [31]; default: 0; + * need_des + */ + uint32_t lp_cpu_reset_en:1; + }; + uint32_t val; +} lpperi_reset_en_reg_t; + +/** Type of rng_cfg register + * need_des + */ +typedef union { + struct { + /** rng_sample_enable : R/W; bitpos: [0]; default: 0; + * need des + */ + uint32_t rng_sample_enable:1; + /** rng_timer_pscale : R/W; bitpos: [8:1]; default: 255; + * need des + */ + uint32_t rng_timer_pscale:8; + /** rng_timer_en : R/W; bitpos: [9]; default: 1; + * need des + */ + uint32_t rng_timer_en:1; + /** rtc_timer_en : R/W; bitpos: [11:10]; default: 3; + * need des + */ + uint32_t rtc_timer_en:2; + uint32_t reserved_12:12; + /** rng_sample_cnt : RO; bitpos: [31:24]; default: 0; + * need des + */ + uint32_t rng_sample_cnt:8; + }; + uint32_t val; +} lpperi_rng_cfg_reg_t; + +/** Type of rng_data register + * need_des + */ +typedef union { + struct { + /** rnd_data : RO; bitpos: [31:0]; default: 0; + * need_des + */ + uint32_t rnd_data:32; + }; + uint32_t val; +} lpperi_rng_data_reg_t; + +/** Type of cpu register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:31; + /** lpcore_dbgm_unavaliable : R/W; bitpos: [31]; default: 1; + * need_des + */ + uint32_t lpcore_dbgm_unavaliable:1; + }; + uint32_t val; +} lpperi_cpu_reg_t; + +/** Type of bus_timeout register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:14; + /** lp_peri_timeout_thres : R/W; bitpos: [29:14]; default: 65535; + * need_des + */ + uint32_t lp_peri_timeout_thres:16; + /** lp_peri_timeout_int_clear : WT; bitpos: [30]; default: 0; + * need_des + */ + uint32_t lp_peri_timeout_int_clear:1; + /** lp_peri_timeout_protect_en : R/W; bitpos: [31]; default: 1; + * need_des + */ + uint32_t lp_peri_timeout_protect_en:1; + }; + uint32_t val; +} lpperi_bus_timeout_reg_t; + +/** Type of bus_timeout_addr register + * need_des + */ +typedef union { + struct { + /** lp_peri_timeout_addr : RO; bitpos: [31:0]; default: 0; + * need_des + */ + uint32_t lp_peri_timeout_addr:32; + }; + uint32_t val; +} lpperi_bus_timeout_addr_reg_t; + +/** Type of bus_timeout_uid register + * need_des + */ +typedef union { + struct { + /** lp_peri_timeout_uid : RO; bitpos: [6:0]; default: 0; + * need_des + */ + uint32_t lp_peri_timeout_uid:7; + uint32_t reserved_7:25; + }; + uint32_t val; +} lpperi_bus_timeout_uid_reg_t; + +/** Type of mem_ctrl register + * need_des + */ +typedef union { + struct { + /** uart_wakeup_flag_clr : WT; bitpos: [0]; default: 0; + * need_des + */ + uint32_t uart_wakeup_flag_clr:1; + /** uart_wakeup_flag : R/WTC/SS; bitpos: [1]; default: 0; + * need_des + */ + uint32_t uart_wakeup_flag:1; + uint32_t reserved_2:27; + /** uart_wakeup_en : R/W; bitpos: [29]; default: 0; + * need_des + */ + uint32_t uart_wakeup_en:1; + /** uart_mem_force_pd : R/W; bitpos: [30]; default: 0; + * need_des + */ + uint32_t uart_mem_force_pd:1; + /** uart_mem_force_pu : R/W; bitpos: [31]; default: 1; + * need_des + */ + uint32_t uart_mem_force_pu:1; + }; + uint32_t val; +} lpperi_mem_ctrl_reg_t; + +/** Type of interrupt_source register + * need_des + */ +typedef union { + struct { + /** lp_interrupt_source : RO; bitpos: [5:0]; default: 0; + * BIT5~BIT0: pmu_lp_int, modem_lp_int, lp_timer_lp_int, lp_uart_int, lp_i2c_int, + * lp_io_int + */ + uint32_t lp_interrupt_source:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} lpperi_interrupt_source_reg_t; + +/** Type of debug_sel0 register + * need des + */ +typedef union { + struct { + /** debug_sel0 : R/W; bitpos: [6:0]; default: 0; + * need des + */ + uint32_t debug_sel0:7; + /** debug_sel1 : R/W; bitpos: [13:7]; default: 0; + * need des + */ + uint32_t debug_sel1:7; + /** debug_sel2 : R/W; bitpos: [20:14]; default: 0; + * need des + */ + uint32_t debug_sel2:7; + /** debug_sel3 : R/W; bitpos: [27:21]; default: 0; + * need des + */ + uint32_t debug_sel3:7; + uint32_t reserved_28:4; + }; + uint32_t val; +} lpperi_debug_sel0_reg_t; + +/** Type of debug_sel1 register + * need des + */ +typedef union { + struct { + /** debug_sel4 : R/W; bitpos: [6:0]; default: 0; + * need des + */ + uint32_t debug_sel4:7; + uint32_t reserved_7:25; + }; + uint32_t val; +} lpperi_debug_sel1_reg_t; + +/** Type of rng_data_sync register + * rng result sync register + */ +typedef union { + struct { + /** rnd_sync_data : RO; bitpos: [31:0]; default: 0; + * get rng sync result + */ + uint32_t rnd_sync_data:32; + }; + uint32_t val; +} lpperi_rng_data_sync_reg_t; + + +/** Group: Version register */ +/** Type of date register + * need_des + */ +typedef union { + struct { + /** lpperi_date : R/W; bitpos: [30:0]; default: 37781793; + * need_des + */ + uint32_t lpperi_date:31; + /** clk_en : R/W; bitpos: [31]; default: 0; + * need_des + */ + uint32_t clk_en:1; + }; + uint32_t val; +} lpperi_date_reg_t; + + +typedef struct { + volatile lpperi_clk_en_reg_t clk_en; + volatile lpperi_reset_en_reg_t reset_en; + volatile lpperi_rng_cfg_reg_t rng_cfg; + volatile lpperi_rng_data_reg_t rng_data; + volatile lpperi_cpu_reg_t cpu; + volatile lpperi_bus_timeout_reg_t bus_timeout; + volatile lpperi_bus_timeout_addr_reg_t bus_timeout_addr; + volatile lpperi_bus_timeout_uid_reg_t bus_timeout_uid; + volatile lpperi_mem_ctrl_reg_t mem_ctrl; + volatile lpperi_interrupt_source_reg_t interrupt_source; + volatile lpperi_debug_sel0_reg_t debug_sel0; + volatile lpperi_debug_sel1_reg_t debug_sel1; + volatile lpperi_rng_data_sync_reg_t rng_data_sync; + uint32_t reserved_034[242]; + volatile lpperi_date_reg_t date; +} lpperi_dev_t; + +extern lpperi_dev_t LPPERI; + +#ifndef __cplusplus +_Static_assert(sizeof(lpperi_dev_t) == 0x400, "Invalid size of lpperi_dev_t structure"); +#endif + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32h21/register/soc/pcr_struct.h b/components/soc/esp32h21/register/soc/pcr_struct.h index e658e903b26..7e3c68bc9c1 100644 --- a/components/soc/esp32h21/register/soc/pcr_struct.h +++ b/components/soc/esp32h21/register/soc/pcr_struct.h @@ -1784,12 +1784,12 @@ typedef union { * This field indicates which one 32KHz clock will be used by timergroup. 1: XTAL32K * (default), 2/3: 32KHz from pad GPIO0. */ - uint32_t 32k_sel:2; + uint32_t clk_32k_sel:2; /** 32k_modem_sel : R/W; bitpos: [3:2]; default: 1; * This field indicates which one 32KHz clock will be used by MODEM_SYSTEM. 1: * XTAL32K(default), 2/3: 32KHz from pad GPIO0. */ - uint32_t 32k_modem_sel:2; + uint32_t clk_32k_modem_sel:2; uint32_t reserved_4:28; }; uint32_t val; diff --git a/components/soc/esp32h21/register/soc/plic_reg.h b/components/soc/esp32h21/register/soc/plic_reg.h new file mode 100644 index 00000000000..c9baf66064b --- /dev/null +++ b/components/soc/esp32h21/register/soc/plic_reg.h @@ -0,0 +1,635 @@ +/* + * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#pragma once + +#ifdef __cplusplus +extern "C" { +#endif + +//TODO: [ESP32H21] IDF-11859 + +#define DR_REG_PLIC_MX_BASE ( 0x20001000 ) +#define DR_REG_PLIC_UX_BASE ( 0x20001400 ) +#define PLIC_MXINT_CONF_REG ( 0x200013FC ) +#define PLIC_UXINT_CONF_REG ( 0x200017FC ) + +#define PLIC_MXINT_PRI_REG(n) (PLIC_MXINT0_PRI_REG + (n)*4) +#define PLIC_UXINT_PRI_REG(n) (PLIC_UXINT0_PRI_REG + (n)*4) + +/*PLIC MX*/ +#define PLIC_MXINT_ENABLE_REG (DR_REG_PLIC_MX_BASE + 0x0) +/* PLIC_CPU_MXINT_ENABLE : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: .*/ +#define PLIC_CPU_MXINT_ENABLE 0xFFFFFFFF +#define PLIC_CPU_MXINT_ENABLE_M ((PLIC_CPU_MXINT_ENABLE_V)<<(PLIC_CPU_MXINT_ENABLE_S)) +#define PLIC_CPU_MXINT_ENABLE_V 0xFFFFFFFF +#define PLIC_CPU_MXINT_ENABLE_S 0 + +#define PLIC_MXINT_TYPE_REG (DR_REG_PLIC_MX_BASE + 0x4) +/* PLIC_CPU_MXINT_TYPE : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: .*/ +#define PLIC_CPU_MXINT_TYPE 0xFFFFFFFF +#define PLIC_CPU_MXINT_TYPE_M ((PLIC_CPU_MXINT_TYPE_V)<<(PLIC_CPU_MXINT_TYPE_S)) +#define PLIC_CPU_MXINT_TYPE_V 0xFFFFFFFF +#define PLIC_CPU_MXINT_TYPE_S 0 + +#define PLIC_MXINT_CLEAR_REG (DR_REG_PLIC_MX_BASE + 0x8) +/* PLIC_CPU_MXINT_CLEAR : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: .*/ +#define PLIC_CPU_MXINT_CLEAR 0xFFFFFFFF +#define PLIC_CPU_MXINT_CLEAR_M ((PLIC_CPU_MXINT_CLEAR_V)<<(PLIC_CPU_MXINT_CLEAR_S)) +#define PLIC_CPU_MXINT_CLEAR_V 0xFFFFFFFF +#define PLIC_CPU_MXINT_CLEAR_S 0 + +#define PLIC_EMIP_STATUS_REG (DR_REG_PLIC_MX_BASE + 0xC) +/* PLIC_CPU_EIP_STATUS : RO ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: .*/ +#define PLIC_CPU_EIP_STATUS 0xFFFFFFFF +#define PLIC_CPU_EIP_STATUS_M ((PLIC_CPU_EIP_STATUS_V)<<(PLIC_CPU_EIP_STATUS_S)) +#define PLIC_CPU_EIP_STATUS_V 0xFFFFFFFF +#define PLIC_CPU_EIP_STATUS_S 0 + +#define PLIC_MXINT0_PRI_REG (DR_REG_PLIC_MX_BASE + 0x10) +/* PLIC_CPU_MXINT0_PRI : R/W ;bitpos:[3:0] ;default: 4'd0 ; */ +/*description: .*/ +#define PLIC_CPU_MXINT0_PRI 0x0000000F +#define PLIC_CPU_MXINT0_PRI_M ((PLIC_CPU_MXINT0_PRI_V)<<(PLIC_CPU_MXINT0_PRI_S)) +#define PLIC_CPU_MXINT0_PRI_V 0xF +#define PLIC_CPU_MXINT0_PRI_S 0 + +#define PLIC_MXINT1_PRI_REG (DR_REG_PLIC_MX_BASE + 0x14) +/* PLIC_CPU_MXINT1_PRI : R/W ;bitpos:[3:0] ;default: 4'd0 ; */ +/*description: .*/ +#define PLIC_CPU_MXINT1_PRI 0x0000000F +#define PLIC_CPU_MXINT1_PRI_M ((PLIC_CPU_MXINT1_PRI_V)<<(PLIC_CPU_MXINT1_PRI_S)) +#define PLIC_CPU_MXINT1_PRI_V 0xF +#define PLIC_CPU_MXINT1_PRI_S 0 + +#define PLIC_MXINT2_PRI_REG (DR_REG_PLIC_MX_BASE + 0x18) +/* PLIC_CPU_MXINT2_PRI : R/W ;bitpos:[3:0] ;default: 4'd0 ; */ +/*description: .*/ +#define PLIC_CPU_MXINT2_PRI 0x0000000F +#define PLIC_CPU_MXINT2_PRI_M ((PLIC_CPU_MXINT2_PRI_V)<<(PLIC_CPU_MXINT2_PRI_S)) +#define PLIC_CPU_MXINT2_PRI_V 0xF +#define PLIC_CPU_MXINT2_PRI_S 0 + +#define PLIC_MXINT3_PRI_REG (DR_REG_PLIC_MX_BASE + 0x1C) +/* PLIC_CPU_MXINT3_PRI : R/W ;bitpos:[3:0] ;default: 4'd0 ; */ +/*description: .*/ +#define PLIC_CPU_MXINT3_PRI 0x0000000F +#define PLIC_CPU_MXINT3_PRI_M ((PLIC_CPU_MXINT3_PRI_V)<<(PLIC_CPU_MXINT3_PRI_S)) +#define PLIC_CPU_MXINT3_PRI_V 0xF +#define PLIC_CPU_MXINT3_PRI_S 0 + +#define PLIC_MXINT4_PRI_REG (DR_REG_PLIC_MX_BASE + 0x20) +/* PLIC_CPU_MXINT4_PRI : R/W ;bitpos:[3:0] ;default: 4'd0 ; */ +/*description: .*/ +#define PLIC_CPU_MXINT4_PRI 0x0000000F +#define PLIC_CPU_MXINT4_PRI_M ((PLIC_CPU_MXINT4_PRI_V)<<(PLIC_CPU_MXINT4_PRI_S)) +#define PLIC_CPU_MXINT4_PRI_V 0xF +#define PLIC_CPU_MXINT4_PRI_S 0 + +#define PLIC_MXINT5_PRI_REG (DR_REG_PLIC_MX_BASE + 0x24) +/* PLIC_CPU_MXINT5_PRI : R/W ;bitpos:[3:0] ;default: 4'd0 ; */ +/*description: .*/ +#define PLIC_CPU_MXINT5_PRI 0x0000000F +#define PLIC_CPU_MXINT5_PRI_M ((PLIC_CPU_MXINT5_PRI_V)<<(PLIC_CPU_MXINT5_PRI_S)) +#define PLIC_CPU_MXINT5_PRI_V 0xF +#define PLIC_CPU_MXINT5_PRI_S 0 + +#define PLIC_MXINT6_PRI_REG (DR_REG_PLIC_MX_BASE + 0x28) +/* PLIC_CPU_MXINT6_PRI : R/W ;bitpos:[3:0] ;default: 4'd0 ; */ +/*description: .*/ +#define PLIC_CPU_MXINT6_PRI 0x0000000F +#define PLIC_CPU_MXINT6_PRI_M ((PLIC_CPU_MXINT6_PRI_V)<<(PLIC_CPU_MXINT6_PRI_S)) +#define PLIC_CPU_MXINT6_PRI_V 0xF +#define PLIC_CPU_MXINT6_PRI_S 0 + +#define PLIC_MXINT7_PRI_REG (DR_REG_PLIC_MX_BASE + 0x2C) +/* PLIC_CPU_MXINT7_PRI : R/W ;bitpos:[3:0] ;default: 4'd0 ; */ +/*description: .*/ +#define PLIC_CPU_MXINT7_PRI 0x0000000F +#define PLIC_CPU_MXINT7_PRI_M ((PLIC_CPU_MXINT7_PRI_V)<<(PLIC_CPU_MXINT7_PRI_S)) +#define PLIC_CPU_MXINT7_PRI_V 0xF +#define PLIC_CPU_MXINT7_PRI_S 0 + +#define PLIC_MXINT8_PRI_REG (DR_REG_PLIC_MX_BASE + 0x30) +/* PLIC_CPU_MXINT8_PRI : R/W ;bitpos:[3:0] ;default: 4'd0 ; */ +/*description: .*/ +#define PLIC_CPU_MXINT8_PRI 0x0000000F +#define PLIC_CPU_MXINT8_PRI_M ((PLIC_CPU_MXINT8_PRI_V)<<(PLIC_CPU_MXINT8_PRI_S)) +#define PLIC_CPU_MXINT8_PRI_V 0xF +#define PLIC_CPU_MXINT8_PRI_S 0 + +#define PLIC_MXINT9_PRI_REG (DR_REG_PLIC_MX_BASE + 0x34) +/* PLIC_CPU_MXINT9_PRI : R/W ;bitpos:[3:0] ;default: 4'd0 ; */ +/*description: .*/ +#define PLIC_CPU_MXINT9_PRI 0x0000000F +#define PLIC_CPU_MXINT9_PRI_M ((PLIC_CPU_MXINT9_PRI_V)<<(PLIC_CPU_MXINT9_PRI_S)) +#define PLIC_CPU_MXINT9_PRI_V 0xF +#define PLIC_CPU_MXINT9_PRI_S 0 + +#define PLIC_MXINT10_PRI_REG (DR_REG_PLIC_MX_BASE + 0x38) +/* PLIC_CPU_MXINT10_PRI : R/W ;bitpos:[3:0] ;default: 4'd0 ; */ +/*description: .*/ +#define PLIC_CPU_MXINT10_PRI 0x0000000F +#define PLIC_CPU_MXINT10_PRI_M ((PLIC_CPU_MXINT10_PRI_V)<<(PLIC_CPU_MXINT10_PRI_S)) +#define PLIC_CPU_MXINT10_PRI_V 0xF +#define PLIC_CPU_MXINT10_PRI_S 0 + +#define PLIC_MXINT11_PRI_REG (DR_REG_PLIC_MX_BASE + 0x3C) +/* PLIC_CPU_MXINT11_PRI : R/W ;bitpos:[3:0] ;default: 4'd0 ; */ +/*description: .*/ +#define PLIC_CPU_MXINT11_PRI 0x0000000F +#define PLIC_CPU_MXINT11_PRI_M ((PLIC_CPU_MXINT11_PRI_V)<<(PLIC_CPU_MXINT11_PRI_S)) +#define PLIC_CPU_MXINT11_PRI_V 0xF +#define PLIC_CPU_MXINT11_PRI_S 0 + +#define PLIC_MXINT12_PRI_REG (DR_REG_PLIC_MX_BASE + 0x40) +/* PLIC_CPU_MXINT12_PRI : R/W ;bitpos:[3:0] ;default: 4'd0 ; */ +/*description: .*/ +#define PLIC_CPU_MXINT12_PRI 0x0000000F +#define PLIC_CPU_MXINT12_PRI_M ((PLIC_CPU_MXINT12_PRI_V)<<(PLIC_CPU_MXINT12_PRI_S)) +#define PLIC_CPU_MXINT12_PRI_V 0xF +#define PLIC_CPU_MXINT12_PRI_S 0 + +#define PLIC_MXINT13_PRI_REG (DR_REG_PLIC_MX_BASE + 0x44) +/* PLIC_CPU_MXINT13_PRI : R/W ;bitpos:[3:0] ;default: 4'd0 ; */ +/*description: .*/ +#define PLIC_CPU_MXINT13_PRI 0x0000000F +#define PLIC_CPU_MXINT13_PRI_M ((PLIC_CPU_MXINT13_PRI_V)<<(PLIC_CPU_MXINT13_PRI_S)) +#define PLIC_CPU_MXINT13_PRI_V 0xF +#define PLIC_CPU_MXINT13_PRI_S 0 + +#define PLIC_MXINT14_PRI_REG (DR_REG_PLIC_MX_BASE + 0x48) +/* PLIC_CPU_MXINT14_PRI : R/W ;bitpos:[3:0] ;default: 4'd0 ; */ +/*description: .*/ +#define PLIC_CPU_MXINT14_PRI 0x0000000F +#define PLIC_CPU_MXINT14_PRI_M ((PLIC_CPU_MXINT14_PRI_V)<<(PLIC_CPU_MXINT14_PRI_S)) +#define PLIC_CPU_MXINT14_PRI_V 0xF +#define PLIC_CPU_MXINT14_PRI_S 0 + +#define PLIC_MXINT15_PRI_REG (DR_REG_PLIC_MX_BASE + 0x4C) +/* PLIC_CPU_MXINT15_PRI : R/W ;bitpos:[3:0] ;default: 4'd0 ; */ +/*description: .*/ +#define PLIC_CPU_MXINT15_PRI 0x0000000F +#define PLIC_CPU_MXINT15_PRI_M ((PLIC_CPU_MXINT15_PRI_V)<<(PLIC_CPU_MXINT15_PRI_S)) +#define PLIC_CPU_MXINT15_PRI_V 0xF +#define PLIC_CPU_MXINT15_PRI_S 0 + +#define PLIC_MXINT16_PRI_REG (DR_REG_PLIC_MX_BASE + 0x50) +/* PLIC_CPU_MXINT16_PRI : R/W ;bitpos:[3:0] ;default: 4'd0 ; */ +/*description: .*/ +#define PLIC_CPU_MXINT16_PRI 0x0000000F +#define PLIC_CPU_MXINT16_PRI_M ((PLIC_CPU_MXINT16_PRI_V)<<(PLIC_CPU_MXINT16_PRI_S)) +#define PLIC_CPU_MXINT16_PRI_V 0xF +#define PLIC_CPU_MXINT16_PRI_S 0 + +#define PLIC_MXINT17_PRI_REG (DR_REG_PLIC_MX_BASE + 0x54) +/* PLIC_CPU_MXINT17_PRI : R/W ;bitpos:[3:0] ;default: 4'd0 ; */ +/*description: .*/ +#define PLIC_CPU_MXINT17_PRI 0x0000000F +#define PLIC_CPU_MXINT17_PRI_M ((PLIC_CPU_MXINT17_PRI_V)<<(PLIC_CPU_MXINT17_PRI_S)) +#define PLIC_CPU_MXINT17_PRI_V 0xF +#define PLIC_CPU_MXINT17_PRI_S 0 + +#define PLIC_MXINT18_PRI_REG (DR_REG_PLIC_MX_BASE + 0x58) +/* PLIC_CPU_MXINT18_PRI : R/W ;bitpos:[3:0] ;default: 4'd0 ; */ +/*description: .*/ +#define PLIC_CPU_MXINT18_PRI 0x0000000F +#define PLIC_CPU_MXINT18_PRI_M ((PLIC_CPU_MXINT18_PRI_V)<<(PLIC_CPU_MXINT18_PRI_S)) +#define PLIC_CPU_MXINT18_PRI_V 0xF +#define PLIC_CPU_MXINT18_PRI_S 0 + +#define PLIC_MXINT19_PRI_REG (DR_REG_PLIC_MX_BASE + 0x5C) +/* PLIC_CPU_MXINT19_PRI : R/W ;bitpos:[3:0] ;default: 4'd0 ; */ +/*description: .*/ +#define PLIC_CPU_MXINT19_PRI 0x0000000F +#define PLIC_CPU_MXINT19_PRI_M ((PLIC_CPU_MXINT19_PRI_V)<<(PLIC_CPU_MXINT19_PRI_S)) +#define PLIC_CPU_MXINT19_PRI_V 0xF +#define PLIC_CPU_MXINT19_PRI_S 0 + +#define PLIC_MXINT20_PRI_REG (DR_REG_PLIC_MX_BASE + 0x60) +/* PLIC_CPU_MXINT20_PRI : R/W ;bitpos:[3:0] ;default: 4'd0 ; */ +/*description: .*/ +#define PLIC_CPU_MXINT20_PRI 0x0000000F +#define PLIC_CPU_MXINT20_PRI_M ((PLIC_CPU_MXINT20_PRI_V)<<(PLIC_CPU_MXINT20_PRI_S)) +#define PLIC_CPU_MXINT20_PRI_V 0xF +#define PLIC_CPU_MXINT20_PRI_S 0 + +#define PLIC_MXINT21_PRI_REG (DR_REG_PLIC_MX_BASE + 0x64) +/* PLIC_CPU_MXINT21_PRI : R/W ;bitpos:[3:0] ;default: 4'd0 ; */ +/*description: .*/ +#define PLIC_CPU_MXINT21_PRI 0x0000000F +#define PLIC_CPU_MXINT21_PRI_M ((PLIC_CPU_MXINT21_PRI_V)<<(PLIC_CPU_MXINT21_PRI_S)) +#define PLIC_CPU_MXINT21_PRI_V 0xF +#define PLIC_CPU_MXINT21_PRI_S 0 + +#define PLIC_MXINT22_PRI_REG (DR_REG_PLIC_MX_BASE + 0x68) +/* PLIC_CPU_MXINT22_PRI : R/W ;bitpos:[3:0] ;default: 4'd0 ; */ +/*description: .*/ +#define PLIC_CPU_MXINT22_PRI 0x0000000F +#define PLIC_CPU_MXINT22_PRI_M ((PLIC_CPU_MXINT22_PRI_V)<<(PLIC_CPU_MXINT22_PRI_S)) +#define PLIC_CPU_MXINT22_PRI_V 0xF +#define PLIC_CPU_MXINT22_PRI_S 0 + +#define PLIC_MXINT23_PRI_REG (DR_REG_PLIC_MX_BASE + 0x6C) +/* PLIC_CPU_MXINT23_PRI : R/W ;bitpos:[3:0] ;default: 4'd0 ; */ +/*description: .*/ +#define PLIC_CPU_MXINT23_PRI 0x0000000F +#define PLIC_CPU_MXINT23_PRI_M ((PLIC_CPU_MXINT23_PRI_V)<<(PLIC_CPU_MXINT23_PRI_S)) +#define PLIC_CPU_MXINT23_PRI_V 0xF +#define PLIC_CPU_MXINT23_PRI_S 0 + +#define PLIC_MXINT24_PRI_REG (DR_REG_PLIC_MX_BASE + 0x70) +/* PLIC_CPU_MXINT24_PRI : R/W ;bitpos:[3:0] ;default: 4'd0 ; */ +/*description: .*/ +#define PLIC_CPU_MXINT24_PRI 0x0000000F +#define PLIC_CPU_MXINT24_PRI_M ((PLIC_CPU_MXINT24_PRI_V)<<(PLIC_CPU_MXINT24_PRI_S)) +#define PLIC_CPU_MXINT24_PRI_V 0xF +#define PLIC_CPU_MXINT24_PRI_S 0 + +#define PLIC_MXINT25_PRI_REG (DR_REG_PLIC_MX_BASE + 0x74) +/* PLIC_CPU_MXINT25_PRI : R/W ;bitpos:[3:0] ;default: 4'd0 ; */ +/*description: .*/ +#define PLIC_CPU_MXINT25_PRI 0x0000000F +#define PLIC_CPU_MXINT25_PRI_M ((PLIC_CPU_MXINT25_PRI_V)<<(PLIC_CPU_MXINT25_PRI_S)) +#define PLIC_CPU_MXINT25_PRI_V 0xF +#define PLIC_CPU_MXINT25_PRI_S 0 + +#define PLIC_MXINT26_PRI_REG (DR_REG_PLIC_MX_BASE + 0x78) +/* PLIC_CPU_MXINT26_PRI : R/W ;bitpos:[3:0] ;default: 4'd0 ; */ +/*description: .*/ +#define PLIC_CPU_MXINT26_PRI 0x0000000F +#define PLIC_CPU_MXINT26_PRI_M ((PLIC_CPU_MXINT26_PRI_V)<<(PLIC_CPU_MXINT26_PRI_S)) +#define PLIC_CPU_MXINT26_PRI_V 0xF +#define PLIC_CPU_MXINT26_PRI_S 0 + +#define PLIC_MXINT27_PRI_REG (DR_REG_PLIC_MX_BASE + 0x7C) +/* PLIC_CPU_MXINT27_PRI : R/W ;bitpos:[3:0] ;default: 4'd0 ; */ +/*description: .*/ +#define PLIC_CPU_MXINT27_PRI 0x0000000F +#define PLIC_CPU_MXINT27_PRI_M ((PLIC_CPU_MXINT27_PRI_V)<<(PLIC_CPU_MXINT27_PRI_S)) +#define PLIC_CPU_MXINT27_PRI_V 0xF +#define PLIC_CPU_MXINT27_PRI_S 0 + +#define PLIC_MXINT28_PRI_REG (DR_REG_PLIC_MX_BASE + 0x80) +/* PLIC_CPU_MXINT28_PRI : R/W ;bitpos:[3:0] ;default: 4'd0 ; */ +/*description: .*/ +#define PLIC_CPU_MXINT28_PRI 0x0000000F +#define PLIC_CPU_MXINT28_PRI_M ((PLIC_CPU_MXINT28_PRI_V)<<(PLIC_CPU_MXINT28_PRI_S)) +#define PLIC_CPU_MXINT28_PRI_V 0xF +#define PLIC_CPU_MXINT28_PRI_S 0 + +#define PLIC_MXINT29_PRI_REG (DR_REG_PLIC_MX_BASE + 0x84) +/* PLIC_CPU_MXINT29_PRI : R/W ;bitpos:[3:0] ;default: 4'd0 ; */ +/*description: .*/ +#define PLIC_CPU_MXINT29_PRI 0x0000000F +#define PLIC_CPU_MXINT29_PRI_M ((PLIC_CPU_MXINT29_PRI_V)<<(PLIC_CPU_MXINT29_PRI_S)) +#define PLIC_CPU_MXINT29_PRI_V 0xF +#define PLIC_CPU_MXINT29_PRI_S 0 + +#define PLIC_MXINT30_PRI_REG (DR_REG_PLIC_MX_BASE + 0x88) +/* PLIC_CPU_MXINT30_PRI : R/W ;bitpos:[3:0] ;default: 4'd0 ; */ +/*description: .*/ +#define PLIC_CPU_MXINT30_PRI 0x0000000F +#define PLIC_CPU_MXINT30_PRI_M ((PLIC_CPU_MXINT30_PRI_V)<<(PLIC_CPU_MXINT30_PRI_S)) +#define PLIC_CPU_MXINT30_PRI_V 0xF +#define PLIC_CPU_MXINT30_PRI_S 0 + +#define PLIC_MXINT31_PRI_REG (DR_REG_PLIC_MX_BASE + 0x8C) +/* PLIC_CPU_MXINT31_PRI : R/W ;bitpos:[3:0] ;default: 4'd0 ; */ +/*description: .*/ +#define PLIC_CPU_MXINT31_PRI 0x0000000F +#define PLIC_CPU_MXINT31_PRI_M ((PLIC_CPU_MXINT31_PRI_V)<<(PLIC_CPU_MXINT31_PRI_S)) +#define PLIC_CPU_MXINT31_PRI_V 0xF +#define PLIC_CPU_MXINT31_PRI_S 0 + +#define PLIC_MXINT_THRESH_REG (DR_REG_PLIC_MX_BASE + 0x90) +/* PLIC_CPU_MXINT_THRESH : R/W ;bitpos:[7:0] ;default: 8'd0 ; */ +/*description: .*/ +#define PLIC_CPU_MXINT_THRESH 0x000000FF +#define PLIC_CPU_MXINT_THRESH_M ((PLIC_CPU_MXINT_THRESH_V)<<(PLIC_CPU_MXINT_THRESH_S)) +#define PLIC_CPU_MXINT_THRESH_V 0xFF +#define PLIC_CPU_MXINT_THRESH_S 0 + +#define PLIC_MXINT_CLAIM_REG (DR_REG_PLIC_MX_BASE + 0x94) +/* PLIC_LP_INTR_FLAG : R/W ;bitpos:[31:0] ;default: 32'b0 ; */ +/*description: hp_mb_int is generated after writing 32'h20200721 to core0_lp_intr_flag.*/ +#define PLIC_CPU_MXINT_CLAIM 0xFFFFFFFF +#define PLIC_CPU_MXINT_CLAIM_M ((PLIC_CPU_MXINT_CLAIM_V)<<(PLIC_CPU_MXINT_CLAIM_S)) +#define PLIC_CPU_MXINT_CLAIM_V 0xFFFFFFFF +#define PLIC_CPU_MXINT_CLAIM_S 0 + +/*PLIC UX*/ +#define PLIC_UXINT_ENABLE_REG (DR_REG_PLIC_UX_BASE + 0x0) +/* PLIC_CPU_UXINT_ENABLE : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: .*/ +#define PLIC_CPU_UXINT_ENABLE 0xFFFFFFFF +#define PLIC_CPU_UXINT_ENABLE_M ((PLIC_CPU_UXINT_ENABLE_V)<<(PLIC_CPU_UXINT_ENABLE_S)) +#define PLIC_CPU_UXINT_ENABLE_V 0xFFFFFFFF +#define PLIC_CPU_UXINT_ENABLE_S 0 + +#define PLIC_UXINT_TYPE_REG (DR_REG_PLIC_UX_BASE + 0x4) +/* PLIC_CPU_UXINT_TYPE : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: .*/ +#define PLIC_CPU_UXINT_TYPE 0xFFFFFFFF +#define PLIC_CPU_UXINT_TYPE_M ((PLIC_CPU_UXINT_TYPE_V)<<(PLIC_CPU_UXINT_TYPE_S)) +#define PLIC_CPU_UXINT_TYPE_V 0xFFFFFFFF +#define PLIC_CPU_UXINT_TYPE_S 0 + +#define PLIC_UXINT_CLEAR_REG (DR_REG_PLIC_UX_BASE + 0x8) +/* PLIC_CPU_UXINT_CLEAR : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: .*/ +#define PLIC_CPU_UXINT_CLEAR 0xFFFFFFFF +#define PLIC_CPU_UXINT_CLEAR_M ((PLIC_CPU_UXINT_CLEAR_V)<<(PLIC_CPU_UXINT_CLEAR_S)) +#define PLIC_CPU_UXINT_CLEAR_V 0xFFFFFFFF +#define PLIC_CPU_UXINT_CLEAR_S 0 + +#define PLIC_EUIP_STATUS_REG (DR_REG_PLIC_UX_BASE + 0xC) +/* PLIC_CPU_EIP_STATUS : RO ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: .*/ +#define PLIC_CPU_EIP_STATUS 0xFFFFFFFF +#define PLIC_CPU_EIP_STATUS_M ((PLIC_CPU_EIP_STATUS_V)<<(PLIC_CPU_EIP_STATUS_S)) +#define PLIC_CPU_EIP_STATUS_V 0xFFFFFFFF +#define PLIC_CPU_EIP_STATUS_S 0 + +#define PLIC_UXINT0_PRI_REG (DR_REG_PLIC_UX_BASE + 0x10) +/* PLIC_CPU_UXINT0_PRI : R/W ;bitpos:[3:0] ;default: 4'd0 ; */ +/*description: .*/ +#define PLIC_CPU_UXINT0_PRI 0x0000000F +#define PLIC_CPU_UXINT0_PRI_M ((PLIC_CPU_UXINT0_PRI_V)<<(PLIC_CPU_UXINT0_PRI_S)) +#define PLIC_CPU_UXINT0_PRI_V 0xF +#define PLIC_CPU_UXINT0_PRI_S 0 + +#define PLIC_UXINT1_PRI_REG (DR_REG_PLIC_UX_BASE + 0x14) +/* PLIC_CPU_UXINT1_PRI : R/W ;bitpos:[3:0] ;default: 4'd0 ; */ +/*description: .*/ +#define PLIC_CPU_UXINT1_PRI 0x0000000F +#define PLIC_CPU_UXINT1_PRI_M ((PLIC_CPU_UXINT1_PRI_V)<<(PLIC_CPU_UXINT1_PRI_S)) +#define PLIC_CPU_UXINT1_PRI_V 0xF +#define PLIC_CPU_UXINT1_PRI_S 0 + +#define PLIC_UXINT2_PRI_REG (DR_REG_PLIC_UX_BASE + 0x18) +/* PLIC_CPU_UXINT2_PRI : R/W ;bitpos:[3:0] ;default: 4'd0 ; */ +/*description: .*/ +#define PLIC_CPU_UXINT2_PRI 0x0000000F +#define PLIC_CPU_UXINT2_PRI_M ((PLIC_CPU_UXINT2_PRI_V)<<(PLIC_CPU_UXINT2_PRI_S)) +#define PLIC_CPU_UXINT2_PRI_V 0xF +#define PLIC_CPU_UXINT2_PRI_S 0 + +#define PLIC_UXINT3_PRI_REG (DR_REG_PLIC_UX_BASE + 0x1C) +/* PLIC_CPU_UXINT3_PRI : R/W ;bitpos:[3:0] ;default: 4'd0 ; */ +/*description: .*/ +#define PLIC_CPU_UXINT3_PRI 0x0000000F +#define PLIC_CPU_UXINT3_PRI_M ((PLIC_CPU_UXINT3_PRI_V)<<(PLIC_CPU_UXINT3_PRI_S)) +#define PLIC_CPU_UXINT3_PRI_V 0xF +#define PLIC_CPU_UXINT3_PRI_S 0 + +#define PLIC_UXINT4_PRI_REG (DR_REG_PLIC_UX_BASE + 0x20) +/* PLIC_CPU_UXINT4_PRI : R/W ;bitpos:[3:0] ;default: 4'd0 ; */ +/*description: .*/ +#define PLIC_CPU_UXINT4_PRI 0x0000000F +#define PLIC_CPU_UXINT4_PRI_M ((PLIC_CPU_UXINT4_PRI_V)<<(PLIC_CPU_UXINT4_PRI_S)) +#define PLIC_CPU_UXINT4_PRI_V 0xF +#define PLIC_CPU_UXINT4_PRI_S 0 + +#define PLIC_UXINT5_PRI_REG (DR_REG_PLIC_UX_BASE + 0x24) +/* PLIC_CPU_UXINT5_PRI : R/W ;bitpos:[3:0] ;default: 4'd0 ; */ +/*description: .*/ +#define PLIC_CPU_UXINT5_PRI 0x0000000F +#define PLIC_CPU_UXINT5_PRI_M ((PLIC_CPU_UXINT5_PRI_V)<<(PLIC_CPU_UXINT5_PRI_S)) +#define PLIC_CPU_UXINT5_PRI_V 0xF +#define PLIC_CPU_UXINT5_PRI_S 0 + +#define PLIC_UXINT6_PRI_REG (DR_REG_PLIC_UX_BASE + 0x28) +/* PLIC_CPU_UXINT6_PRI : R/W ;bitpos:[3:0] ;default: 4'd0 ; */ +/*description: .*/ +#define PLIC_CPU_UXINT6_PRI 0x0000000F +#define PLIC_CPU_UXINT6_PRI_M ((PLIC_CPU_UXINT6_PRI_V)<<(PLIC_CPU_UXINT6_PRI_S)) +#define PLIC_CPU_UXINT6_PRI_V 0xF +#define PLIC_CPU_UXINT6_PRI_S 0 + +#define PLIC_UXINT7_PRI_REG (DR_REG_PLIC_UX_BASE + 0x2C) +/* PLIC_CPU_UXINT7_PRI : R/W ;bitpos:[3:0] ;default: 4'd0 ; */ +/*description: .*/ +#define PLIC_CPU_UXINT7_PRI 0x0000000F +#define PLIC_CPU_UXINT7_PRI_M ((PLIC_CPU_UXINT7_PRI_V)<<(PLIC_CPU_UXINT7_PRI_S)) +#define PLIC_CPU_UXINT7_PRI_V 0xF +#define PLIC_CPU_UXINT7_PRI_S 0 + +#define PLIC_UXINT8_PRI_REG (DR_REG_PLIC_UX_BASE + 0x30) +/* PLIC_CPU_UXINT8_PRI : R/W ;bitpos:[3:0] ;default: 4'd0 ; */ +/*description: .*/ +#define PLIC_CPU_UXINT8_PRI 0x0000000F +#define PLIC_CPU_UXINT8_PRI_M ((PLIC_CPU_UXINT8_PRI_V)<<(PLIC_CPU_UXINT8_PRI_S)) +#define PLIC_CPU_UXINT8_PRI_V 0xF +#define PLIC_CPU_UXINT8_PRI_S 0 + +#define PLIC_UXINT9_PRI_REG (DR_REG_PLIC_UX_BASE + 0x34) +/* PLIC_CPU_UXINT9_PRI : R/W ;bitpos:[3:0] ;default: 4'd0 ; */ +/*description: .*/ +#define PLIC_CPU_UXINT9_PRI 0x0000000F +#define PLIC_CPU_UXINT9_PRI_M ((PLIC_CPU_UXINT9_PRI_V)<<(PLIC_CPU_UXINT9_PRI_S)) +#define PLIC_CPU_UXINT9_PRI_V 0xF +#define PLIC_CPU_UXINT9_PRI_S 0 + +#define PLIC_UXINT10_PRI_REG (DR_REG_PLIC_UX_BASE + 0x38) +/* PLIC_CPU_UXINT10_PRI : R/W ;bitpos:[3:0] ;default: 4'd0 ; */ +/*description: .*/ +#define PLIC_CPU_UXINT10_PRI 0x0000000F +#define PLIC_CPU_UXINT10_PRI_M ((PLIC_CPU_UXINT10_PRI_V)<<(PLIC_CPU_UXINT10_PRI_S)) +#define PLIC_CPU_UXINT10_PRI_V 0xF +#define PLIC_CPU_UXINT10_PRI_S 0 + +#define PLIC_UXINT11_PRI_REG (DR_REG_PLIC_UX_BASE + 0x3C) +/* PLIC_CPU_UXINT11_PRI : R/W ;bitpos:[3:0] ;default: 4'd0 ; */ +/*description: .*/ +#define PLIC_CPU_UXINT11_PRI 0x0000000F +#define PLIC_CPU_UXINT11_PRI_M ((PLIC_CPU_UXINT11_PRI_V)<<(PLIC_CPU_UXINT11_PRI_S)) +#define PLIC_CPU_UXINT11_PRI_V 0xF +#define PLIC_CPU_UXINT11_PRI_S 0 + +#define PLIC_UXINT12_PRI_REG (DR_REG_PLIC_UX_BASE + 0x40) +/* PLIC_CPU_UXINT12_PRI : R/W ;bitpos:[3:0] ;default: 4'd0 ; */ +/*description: .*/ +#define PLIC_CPU_UXINT12_PRI 0x0000000F +#define PLIC_CPU_UXINT12_PRI_M ((PLIC_CPU_UXINT12_PRI_V)<<(PLIC_CPU_UXINT12_PRI_S)) +#define PLIC_CPU_UXINT12_PRI_V 0xF +#define PLIC_CPU_UXINT12_PRI_S 0 + +#define PLIC_UXINT13_PRI_REG (DR_REG_PLIC_UX_BASE + 0x44) +/* PLIC_CPU_UXINT13_PRI : R/W ;bitpos:[3:0] ;default: 4'd0 ; */ +/*description: .*/ +#define PLIC_CPU_UXINT13_PRI 0x0000000F +#define PLIC_CPU_UXINT13_PRI_M ((PLIC_CPU_UXINT13_PRI_V)<<(PLIC_CPU_UXINT13_PRI_S)) +#define PLIC_CPU_UXINT13_PRI_V 0xF +#define PLIC_CPU_UXINT13_PRI_S 0 + +#define PLIC_UXINT14_PRI_REG (DR_REG_PLIC_UX_BASE + 0x48) +/* PLIC_CPU_UXINT14_PRI : R/W ;bitpos:[3:0] ;default: 4'd0 ; */ +/*description: .*/ +#define PLIC_CPU_UXINT14_PRI 0x0000000F +#define PLIC_CPU_UXINT14_PRI_M ((PLIC_CPU_UXINT14_PRI_V)<<(PLIC_CPU_UXINT14_PRI_S)) +#define PLIC_CPU_UXINT14_PRI_V 0xF +#define PLIC_CPU_UXINT14_PRI_S 0 + +#define PLIC_UXINT15_PRI_REG (DR_REG_PLIC_UX_BASE + 0x4C) +/* PLIC_CPU_UXINT15_PRI : R/W ;bitpos:[3:0] ;default: 4'd0 ; */ +/*description: .*/ +#define PLIC_CPU_UXINT15_PRI 0x0000000F +#define PLIC_CPU_UXINT15_PRI_M ((PLIC_CPU_UXINT15_PRI_V)<<(PLIC_CPU_UXINT15_PRI_S)) +#define PLIC_CPU_UXINT15_PRI_V 0xF +#define PLIC_CPU_UXINT15_PRI_S 0 + +#define PLIC_UXINT16_PRI_REG (DR_REG_PLIC_UX_BASE + 0x50) +/* PLIC_CPU_UXINT16_PRI : R/W ;bitpos:[3:0] ;default: 4'd0 ; */ +/*description: .*/ +#define PLIC_CPU_UXINT16_PRI 0x0000000F +#define PLIC_CPU_UXINT16_PRI_M ((PLIC_CPU_UXINT16_PRI_V)<<(PLIC_CPU_UXINT16_PRI_S)) +#define PLIC_CPU_UXINT16_PRI_V 0xF +#define PLIC_CPU_UXINT16_PRI_S 0 + +#define PLIC_UXINT17_PRI_REG (DR_REG_PLIC_UX_BASE + 0x54) +/* PLIC_CPU_UXINT17_PRI : R/W ;bitpos:[3:0] ;default: 4'd0 ; */ +/*description: .*/ +#define PLIC_CPU_UXINT17_PRI 0x0000000F +#define PLIC_CPU_UXINT17_PRI_M ((PLIC_CPU_UXINT17_PRI_V)<<(PLIC_CPU_UXINT17_PRI_S)) +#define PLIC_CPU_UXINT17_PRI_V 0xF +#define PLIC_CPU_UXINT17_PRI_S 0 + +#define PLIC_UXINT18_PRI_REG (DR_REG_PLIC_UX_BASE + 0x58) +/* PLIC_CPU_UXINT18_PRI : R/W ;bitpos:[3:0] ;default: 4'd0 ; */ +/*description: .*/ +#define PLIC_CPU_UXINT18_PRI 0x0000000F +#define PLIC_CPU_UXINT18_PRI_M ((PLIC_CPU_UXINT18_PRI_V)<<(PLIC_CPU_UXINT18_PRI_S)) +#define PLIC_CPU_UXINT18_PRI_V 0xF +#define PLIC_CPU_UXINT18_PRI_S 0 + +#define PLIC_UXINT19_PRI_REG (DR_REG_PLIC_UX_BASE + 0x5C) +/* PLIC_CPU_UXINT19_PRI : R/W ;bitpos:[3:0] ;default: 4'd0 ; */ +/*description: .*/ +#define PLIC_CPU_UXINT19_PRI 0x0000000F +#define PLIC_CPU_UXINT19_PRI_M ((PLIC_CPU_UXINT19_PRI_V)<<(PLIC_CPU_UXINT19_PRI_S)) +#define PLIC_CPU_UXINT19_PRI_V 0xF +#define PLIC_CPU_UXINT19_PRI_S 0 + +#define PLIC_UXINT20_PRI_REG (DR_REG_PLIC_UX_BASE + 0x60) +/* PLIC_CPU_UXINT20_PRI : R/W ;bitpos:[3:0] ;default: 4'd0 ; */ +/*description: .*/ +#define PLIC_CPU_UXINT20_PRI 0x0000000F +#define PLIC_CPU_UXINT20_PRI_M ((PLIC_CPU_UXINT20_PRI_V)<<(PLIC_CPU_UXINT20_PRI_S)) +#define PLIC_CPU_UXINT20_PRI_V 0xF +#define PLIC_CPU_UXINT20_PRI_S 0 + +#define PLIC_UXINT21_PRI_REG (DR_REG_PLIC_UX_BASE + 0x64) +/* PLIC_CPU_UXINT21_PRI : R/W ;bitpos:[3:0] ;default: 4'd0 ; */ +/*description: .*/ +#define PLIC_CPU_UXINT21_PRI 0x0000000F +#define PLIC_CPU_UXINT21_PRI_M ((PLIC_CPU_UXINT21_PRI_V)<<(PLIC_CPU_UXINT21_PRI_S)) +#define PLIC_CPU_UXINT21_PRI_V 0xF +#define PLIC_CPU_UXINT21_PRI_S 0 + +#define PLIC_UXINT22_PRI_REG (DR_REG_PLIC_UX_BASE + 0x68) +/* PLIC_CPU_UXINT22_PRI : R/W ;bitpos:[3:0] ;default: 4'd0 ; */ +/*description: .*/ +#define PLIC_CPU_UXINT22_PRI 0x0000000F +#define PLIC_CPU_UXINT22_PRI_M ((PLIC_CPU_UXINT22_PRI_V)<<(PLIC_CPU_UXINT22_PRI_S)) +#define PLIC_CPU_UXINT22_PRI_V 0xF +#define PLIC_CPU_UXINT22_PRI_S 0 + +#define PLIC_UXINT23_PRI_REG (DR_REG_PLIC_UX_BASE + 0x6C) +/* PLIC_CPU_UXINT23_PRI : R/W ;bitpos:[3:0] ;default: 4'd0 ; */ +/*description: .*/ +#define PLIC_CPU_UXINT23_PRI 0x0000000F +#define PLIC_CPU_UXINT23_PRI_M ((PLIC_CPU_UXINT23_PRI_V)<<(PLIC_CPU_UXINT23_PRI_S)) +#define PLIC_CPU_UXINT23_PRI_V 0xF +#define PLIC_CPU_UXINT23_PRI_S 0 + +#define PLIC_UXINT24_PRI_REG (DR_REG_PLIC_UX_BASE + 0x70) +/* PLIC_CPU_UXINT24_PRI : R/W ;bitpos:[3:0] ;default: 4'd0 ; */ +/*description: .*/ +#define PLIC_CPU_UXINT24_PRI 0x0000000F +#define PLIC_CPU_UXINT24_PRI_M ((PLIC_CPU_UXINT24_PRI_V)<<(PLIC_CPU_UXINT24_PRI_S)) +#define PLIC_CPU_UXINT24_PRI_V 0xF +#define PLIC_CPU_UXINT24_PRI_S 0 + +#define PLIC_UXINT25_PRI_REG (DR_REG_PLIC_UX_BASE + 0x74) +/* PLIC_CPU_UXINT25_PRI : R/W ;bitpos:[3:0] ;default: 4'd0 ; */ +/*description: .*/ +#define PLIC_CPU_UXINT25_PRI 0x0000000F +#define PLIC_CPU_UXINT25_PRI_M ((PLIC_CPU_UXINT25_PRI_V)<<(PLIC_CPU_UXINT25_PRI_S)) +#define PLIC_CPU_UXINT25_PRI_V 0xF +#define PLIC_CPU_UXINT25_PRI_S 0 + +#define PLIC_UXINT26_PRI_REG (DR_REG_PLIC_UX_BASE + 0x78) +/* PLIC_CPU_UXINT26_PRI : R/W ;bitpos:[3:0] ;default: 4'd0 ; */ +/*description: .*/ +#define PLIC_CPU_UXINT26_PRI 0x0000000F +#define PLIC_CPU_UXINT26_PRI_M ((PLIC_CPU_UXINT26_PRI_V)<<(PLIC_CPU_UXINT26_PRI_S)) +#define PLIC_CPU_UXINT26_PRI_V 0xF +#define PLIC_CPU_UXINT26_PRI_S 0 + +#define PLIC_UXINT27_PRI_REG (DR_REG_PLIC_UX_BASE + 0x7C) +/* PLIC_CPU_UXINT27_PRI : R/W ;bitpos:[3:0] ;default: 4'd0 ; */ +/*description: .*/ +#define PLIC_CPU_UXINT27_PRI 0x0000000F +#define PLIC_CPU_UXINT27_PRI_M ((PLIC_CPU_UXINT27_PRI_V)<<(PLIC_CPU_UXINT27_PRI_S)) +#define PLIC_CPU_UXINT27_PRI_V 0xF +#define PLIC_CPU_UXINT27_PRI_S 0 + +#define PLIC_UXINT28_PRI_REG (DR_REG_PLIC_UX_BASE + 0x80) +/* PLIC_CPU_UXINT28_PRI : R/W ;bitpos:[3:0] ;default: 4'd0 ; */ +/*description: .*/ +#define PLIC_CPU_UXINT28_PRI 0x0000000F +#define PLIC_CPU_UXINT28_PRI_M ((PLIC_CPU_UXINT28_PRI_V)<<(PLIC_CPU_UXINT28_PRI_S)) +#define PLIC_CPU_UXINT28_PRI_V 0xF +#define PLIC_CPU_UXINT28_PRI_S 0 + +#define PLIC_UXINT29_PRI_REG (DR_REG_PLIC_UX_BASE + 0x84) +/* PLIC_CPU_UXINT29_PRI : R/W ;bitpos:[3:0] ;default: 4'd0 ; */ +/*description: .*/ +#define PLIC_CPU_UXINT29_PRI 0x0000000F +#define PLIC_CPU_UXINT29_PRI_M ((PLIC_CPU_UXINT29_PRI_V)<<(PLIC_CPU_UXINT29_PRI_S)) +#define PLIC_CPU_UXINT29_PRI_V 0xF +#define PLIC_CPU_UXINT29_PRI_S 0 + +#define PLIC_UXINT30_PRI_REG (DR_REG_PLIC_UX_BASE + 0x88) +/* PLIC_CPU_UXINT30_PRI : R/W ;bitpos:[3:0] ;default: 4'd0 ; */ +/*description: .*/ +#define PLIC_CPU_UXINT30_PRI 0x0000000F +#define PLIC_CPU_UXINT30_PRI_M ((PLIC_CPU_UXINT30_PRI_V)<<(PLIC_CPU_UXINT30_PRI_S)) +#define PLIC_CPU_UXINT30_PRI_V 0xF +#define PLIC_CPU_UXINT30_PRI_S 0 + +#define PLIC_UXINT31_PRI_REG (DR_REG_PLIC_UX_BASE + 0x8C) +/* PLIC_CPU_UXINT31_PRI : R/W ;bitpos:[3:0] ;default: 4'd0 ; */ +/*description: .*/ +#define PLIC_CPU_UXINT31_PRI 0x0000000F +#define PLIC_CPU_UXINT31_PRI_M ((PLIC_CPU_UXINT31_PRI_V)<<(PLIC_CPU_UXINT31_PRI_S)) +#define PLIC_CPU_UXINT31_PRI_V 0xF +#define PLIC_CPU_UXINT31_PRI_S 0 + +#define PLIC_UXINT_THRESH_REG (DR_REG_PLIC_UX_BASE + 0x90) +/* PLIC_CPU_UXINT_THRESH : R/W ;bitpos:[7:0] ;default: 8'd0 ; */ +/*description: .*/ +#define PLIC_CPU_UXINT_THRESH 0x000000FF +#define PLIC_CPU_UXINT_THRESH_M ((PLIC_CPU_UXINT_THRESH_V)<<(PLIC_CPU_UXINT_THRESH_S)) +#define PLIC_CPU_UXINT_THRESH_V 0xFF +#define PLIC_CPU_UXINT_THRESH_S 0 + +#define PLIC_UXINT_CLAIM_REG (DR_REG_PLIC_UX_BASE + 0x94) +/* PLIC_CPU_UXINT_CLAIM : R/W ;bitpos:[31:0] ;default: 32'b0 ; */ +/*description: .*/ +#define PLIC_CPU_UXINT_CLAIM 0xFFFFFFFF +#define PLIC_CPU_UXINT_CLAIM_M ((PLIC_CPU_UXINT_CLAIM_V)<<(PLIC_CPU_UXINT_CLAIM_S)) +#define PLIC_CPU_UXINT_CLAIM_V 0xFFFFFFFF +#define PLIC_CPU_UXINT_CLAIM_S 0 + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32h21/register/soc/pmu_reg.h b/components/soc/esp32h21/register/soc/pmu_reg.h index abb9c041744..4394e9e1249 100644 --- a/components/soc/esp32h21/register/soc/pmu_reg.h +++ b/components/soc/esp32h21/register/soc/pmu_reg.h @@ -15,13 +15,13 @@ extern "C" { * need_des */ #define PMU_HP_ACTIVE_DIG_POWER_REG (DR_REG_PMU_BASE + 0x0) -/** PMU_HP_ACTIVE_VDD_FLASH_MODE : R/W; bitpos: [21:18]; default: 0; +/** PMU_HP_ACTIVE_VDD_SPI_PD_EN : R/W; bitpos: [21]; default: 0; * need_des */ -#define PMU_HP_ACTIVE_VDD_FLASH_MODE 0x0000000FU -#define PMU_HP_ACTIVE_VDD_FLASH_MODE_M (PMU_HP_ACTIVE_VDD_FLASH_MODE_V << PMU_HP_ACTIVE_VDD_FLASH_MODE_S) -#define PMU_HP_ACTIVE_VDD_FLASH_MODE_V 0x0000000FU -#define PMU_HP_ACTIVE_VDD_FLASH_MODE_S 18 +#define PMU_HP_ACTIVE_VDD_SPI_PD_EN (BIT(21)) +#define PMU_HP_ACTIVE_VDD_SPI_PD_EN_M (PMU_HP_ACTIVE_VDD_SPI_PD_EN_V << PMU_HP_ACTIVE_VDD_SPI_PD_EN_S) +#define PMU_HP_ACTIVE_VDD_SPI_PD_EN_V 0x00000001U +#define PMU_HP_ACTIVE_VDD_SPI_PD_EN_S 21 /** PMU_HP_ACTIVE_HP_MEM_DSLP : R/W; bitpos: [22]; default: 0; * need_des */ @@ -43,13 +43,6 @@ extern "C" { #define PMU_HP_ACTIVE_PD_HP_WIFI_PD_EN_M (PMU_HP_ACTIVE_PD_HP_WIFI_PD_EN_V << PMU_HP_ACTIVE_PD_HP_WIFI_PD_EN_S) #define PMU_HP_ACTIVE_PD_HP_WIFI_PD_EN_V 0x00000001U #define PMU_HP_ACTIVE_PD_HP_WIFI_PD_EN_S 27 -/** PMU_HP_ACTIVE_PD_HP_PERI_PD_EN : R/W; bitpos: [28]; default: 0; - * need_des - */ -#define PMU_HP_ACTIVE_PD_HP_PERI_PD_EN (BIT(28)) -#define PMU_HP_ACTIVE_PD_HP_PERI_PD_EN_M (PMU_HP_ACTIVE_PD_HP_PERI_PD_EN_V << PMU_HP_ACTIVE_PD_HP_PERI_PD_EN_S) -#define PMU_HP_ACTIVE_PD_HP_PERI_PD_EN_V 0x00000001U -#define PMU_HP_ACTIVE_PD_HP_PERI_PD_EN_S 28 /** PMU_HP_ACTIVE_PD_HP_CPU_PD_EN : R/W; bitpos: [29]; default: 0; * need_des */ @@ -199,48 +192,6 @@ extern "C" { * need_des */ #define PMU_HP_ACTIVE_BIAS_REG (DR_REG_PMU_BASE + 0x18) -/** PMU_HP_ACTIVE_DCDC_CCM_ENB : R/W; bitpos: [9]; default: 1; - * need_des - */ -#define PMU_HP_ACTIVE_DCDC_CCM_ENB (BIT(9)) -#define PMU_HP_ACTIVE_DCDC_CCM_ENB_M (PMU_HP_ACTIVE_DCDC_CCM_ENB_V << PMU_HP_ACTIVE_DCDC_CCM_ENB_S) -#define PMU_HP_ACTIVE_DCDC_CCM_ENB_V 0x00000001U -#define PMU_HP_ACTIVE_DCDC_CCM_ENB_S 9 -/** PMU_HP_ACTIVE_DCDC_CLEAR_RDY : R/W; bitpos: [10]; default: 0; - * need_des - */ -#define PMU_HP_ACTIVE_DCDC_CLEAR_RDY (BIT(10)) -#define PMU_HP_ACTIVE_DCDC_CLEAR_RDY_M (PMU_HP_ACTIVE_DCDC_CLEAR_RDY_V << PMU_HP_ACTIVE_DCDC_CLEAR_RDY_S) -#define PMU_HP_ACTIVE_DCDC_CLEAR_RDY_V 0x00000001U -#define PMU_HP_ACTIVE_DCDC_CLEAR_RDY_S 10 -/** PMU_HP_ACTIVE_DIG_PMU_DPCUR_BIAS : R/W; bitpos: [12:11]; default: 3; - * need_des - */ -#define PMU_HP_ACTIVE_DIG_PMU_DPCUR_BIAS 0x00000003U -#define PMU_HP_ACTIVE_DIG_PMU_DPCUR_BIAS_M (PMU_HP_ACTIVE_DIG_PMU_DPCUR_BIAS_V << PMU_HP_ACTIVE_DIG_PMU_DPCUR_BIAS_S) -#define PMU_HP_ACTIVE_DIG_PMU_DPCUR_BIAS_V 0x00000003U -#define PMU_HP_ACTIVE_DIG_PMU_DPCUR_BIAS_S 11 -/** PMU_HP_ACTIVE_DIG_PMU_DSFMOS : R/W; bitpos: [16:13]; default: 6; - * need_des - */ -#define PMU_HP_ACTIVE_DIG_PMU_DSFMOS 0x0000000FU -#define PMU_HP_ACTIVE_DIG_PMU_DSFMOS_M (PMU_HP_ACTIVE_DIG_PMU_DSFMOS_V << PMU_HP_ACTIVE_DIG_PMU_DSFMOS_S) -#define PMU_HP_ACTIVE_DIG_PMU_DSFMOS_V 0x0000000FU -#define PMU_HP_ACTIVE_DIG_PMU_DSFMOS_S 13 -/** PMU_HP_ACTIVE_DCM_VSET : R/W; bitpos: [21:17]; default: 23; - * need_des - */ -#define PMU_HP_ACTIVE_DCM_VSET 0x0000001FU -#define PMU_HP_ACTIVE_DCM_VSET_M (PMU_HP_ACTIVE_DCM_VSET_V << PMU_HP_ACTIVE_DCM_VSET_S) -#define PMU_HP_ACTIVE_DCM_VSET_V 0x0000001FU -#define PMU_HP_ACTIVE_DCM_VSET_S 17 -/** PMU_HP_ACTIVE_DCM_MODE : R/W; bitpos: [23:22]; default: 0; - * need_des - */ -#define PMU_HP_ACTIVE_DCM_MODE 0x00000003U -#define PMU_HP_ACTIVE_DCM_MODE_M (PMU_HP_ACTIVE_DCM_MODE_V << PMU_HP_ACTIVE_DCM_MODE_S) -#define PMU_HP_ACTIVE_DCM_MODE_V 0x00000003U -#define PMU_HP_ACTIVE_DCM_MODE_S 22 /** PMU_HP_ACTIVE_XPD_TRX : R/W; bitpos: [24]; default: 1; * need_des */ @@ -255,13 +206,6 @@ extern "C" { #define PMU_HP_ACTIVE_XPD_BIAS_M (PMU_HP_ACTIVE_XPD_BIAS_V << PMU_HP_ACTIVE_XPD_BIAS_S) #define PMU_HP_ACTIVE_XPD_BIAS_V 0x00000001U #define PMU_HP_ACTIVE_XPD_BIAS_S 25 -/** PMU_HP_ACTIVE_DISCNNT_DIG_RTC : R/W; bitpos: [29]; default: 0; - * need_des - */ -#define PMU_HP_ACTIVE_DISCNNT_DIG_RTC (BIT(29)) -#define PMU_HP_ACTIVE_DISCNNT_DIG_RTC_M (PMU_HP_ACTIVE_DISCNNT_DIG_RTC_V << PMU_HP_ACTIVE_DISCNNT_DIG_RTC_S) -#define PMU_HP_ACTIVE_DISCNNT_DIG_RTC_V 0x00000001U -#define PMU_HP_ACTIVE_DISCNNT_DIG_RTC_S 29 /** PMU_HP_ACTIVE_PD_CUR : R/W; bitpos: [30]; default: 0; * need_des */ @@ -295,6 +239,27 @@ extern "C" { #define PMU_HP_MODEM2ACTIVE_BACKUP_MODEM_CLK_CODE_M (PMU_HP_MODEM2ACTIVE_BACKUP_MODEM_CLK_CODE_V << PMU_HP_MODEM2ACTIVE_BACKUP_MODEM_CLK_CODE_S) #define PMU_HP_MODEM2ACTIVE_BACKUP_MODEM_CLK_CODE_V 0x00000003U #define PMU_HP_MODEM2ACTIVE_BACKUP_MODEM_CLK_CODE_S 6 +/** PMU_HP_ACTIVE_RETENTION_MODE : R/W; bitpos: [10]; default: 0; + * need_des + */ +#define PMU_HP_ACTIVE_RETENTION_MODE (BIT(10)) +#define PMU_HP_ACTIVE_RETENTION_MODE_M (PMU_HP_ACTIVE_RETENTION_MODE_V << PMU_HP_ACTIVE_RETENTION_MODE_S) +#define PMU_HP_ACTIVE_RETENTION_MODE_V 0x00000001U +#define PMU_HP_ACTIVE_RETENTION_MODE_S 10 +/** PMU_HP_SLEEP2ACTIVE_RETENTION_EN : R/W; bitpos: [11]; default: 0; + * need_des + */ +#define PMU_HP_SLEEP2ACTIVE_RETENTION_EN (BIT(11)) +#define PMU_HP_SLEEP2ACTIVE_RETENTION_EN_M (PMU_HP_SLEEP2ACTIVE_RETENTION_EN_V << PMU_HP_SLEEP2ACTIVE_RETENTION_EN_S) +#define PMU_HP_SLEEP2ACTIVE_RETENTION_EN_V 0x00000001U +#define PMU_HP_SLEEP2ACTIVE_RETENTION_EN_S 11 +/** PMU_HP_MODEM2ACTIVE_RETENTION_EN : R/W; bitpos: [12]; default: 0; + * need_des + */ +#define PMU_HP_MODEM2ACTIVE_RETENTION_EN (BIT(12)) +#define PMU_HP_MODEM2ACTIVE_RETENTION_EN_M (PMU_HP_MODEM2ACTIVE_RETENTION_EN_V << PMU_HP_MODEM2ACTIVE_RETENTION_EN_S) +#define PMU_HP_MODEM2ACTIVE_RETENTION_EN_V 0x00000001U +#define PMU_HP_MODEM2ACTIVE_RETENTION_EN_S 12 /** PMU_HP_SLEEP2ACTIVE_BACKUP_CLK_SEL : R/W; bitpos: [15:14]; default: 0; * need_des */ @@ -309,19 +274,19 @@ extern "C" { #define PMU_HP_MODEM2ACTIVE_BACKUP_CLK_SEL_M (PMU_HP_MODEM2ACTIVE_BACKUP_CLK_SEL_V << PMU_HP_MODEM2ACTIVE_BACKUP_CLK_SEL_S) #define PMU_HP_MODEM2ACTIVE_BACKUP_CLK_SEL_V 0x00000003U #define PMU_HP_MODEM2ACTIVE_BACKUP_CLK_SEL_S 16 -/** PMU_HP_SLEEP2ACTIVE_BACKUP_MODE : R/W; bitpos: [22:18]; default: 0; +/** PMU_HP_SLEEP2ACTIVE_BACKUP_MODE : R/W; bitpos: [22:20]; default: 0; * need_des */ -#define PMU_HP_SLEEP2ACTIVE_BACKUP_MODE 0x0000001FU +#define PMU_HP_SLEEP2ACTIVE_BACKUP_MODE 0x00000007U #define PMU_HP_SLEEP2ACTIVE_BACKUP_MODE_M (PMU_HP_SLEEP2ACTIVE_BACKUP_MODE_V << PMU_HP_SLEEP2ACTIVE_BACKUP_MODE_S) -#define PMU_HP_SLEEP2ACTIVE_BACKUP_MODE_V 0x0000001FU -#define PMU_HP_SLEEP2ACTIVE_BACKUP_MODE_S 18 -/** PMU_HP_MODEM2ACTIVE_BACKUP_MODE : R/W; bitpos: [27:23]; default: 0; +#define PMU_HP_SLEEP2ACTIVE_BACKUP_MODE_V 0x00000007U +#define PMU_HP_SLEEP2ACTIVE_BACKUP_MODE_S 20 +/** PMU_HP_MODEM2ACTIVE_BACKUP_MODE : R/W; bitpos: [25:23]; default: 0; * need_des */ -#define PMU_HP_MODEM2ACTIVE_BACKUP_MODE 0x0000001FU +#define PMU_HP_MODEM2ACTIVE_BACKUP_MODE 0x00000007U #define PMU_HP_MODEM2ACTIVE_BACKUP_MODE_M (PMU_HP_MODEM2ACTIVE_BACKUP_MODE_V << PMU_HP_MODEM2ACTIVE_BACKUP_MODE_S) -#define PMU_HP_MODEM2ACTIVE_BACKUP_MODE_V 0x0000001FU +#define PMU_HP_MODEM2ACTIVE_BACKUP_MODE_V 0x00000007U #define PMU_HP_MODEM2ACTIVE_BACKUP_MODE_S 23 /** PMU_HP_SLEEP2ACTIVE_BACKUP_EN : R/W; bitpos: [29]; default: 0; * need_des @@ -401,14 +366,14 @@ extern "C" { #define PMU_HP_ACTIVE_HP_POWER_DET_BYPASS_M (PMU_HP_ACTIVE_HP_POWER_DET_BYPASS_V << PMU_HP_ACTIVE_HP_POWER_DET_BYPASS_S) #define PMU_HP_ACTIVE_HP_POWER_DET_BYPASS_V 0x00000001U #define PMU_HP_ACTIVE_HP_POWER_DET_BYPASS_S 0 -/** PMU_LP_DBIAS_VOL : RO; bitpos: [8:4]; default: 24; +/** PMU_LP_DBIAS_VOL : RO; bitpos: [8:4]; default: 17; * need_des */ #define PMU_LP_DBIAS_VOL 0x0000001FU #define PMU_LP_DBIAS_VOL_M (PMU_LP_DBIAS_VOL_V << PMU_LP_DBIAS_VOL_S) #define PMU_LP_DBIAS_VOL_V 0x0000001FU #define PMU_LP_DBIAS_VOL_S 4 -/** PMU_HP_DBIAS_VOL : RO; bitpos: [13:9]; default: 24; +/** PMU_HP_DBIAS_VOL : RO; bitpos: [13:9]; default: 16; * need_des */ #define PMU_HP_DBIAS_VOL 0x0000001FU @@ -488,13 +453,6 @@ extern "C" { * need_des */ #define PMU_HP_ACTIVE_XTAL_REG (DR_REG_PMU_BASE + 0x30) -/** PMU_HP_ACTIVE_XPD_XTALX2 : R/W; bitpos: [30]; default: 1; - * need_des - */ -#define PMU_HP_ACTIVE_XPD_XTALX2 (BIT(30)) -#define PMU_HP_ACTIVE_XPD_XTALX2_M (PMU_HP_ACTIVE_XPD_XTALX2_V << PMU_HP_ACTIVE_XPD_XTALX2_S) -#define PMU_HP_ACTIVE_XPD_XTALX2_V 0x00000001U -#define PMU_HP_ACTIVE_XPD_XTALX2_S 30 /** PMU_HP_ACTIVE_XPD_XTAL : R/W; bitpos: [31]; default: 1; * need_des */ @@ -503,17 +461,404 @@ extern "C" { #define PMU_HP_ACTIVE_XPD_XTAL_V 0x00000001U #define PMU_HP_ACTIVE_XPD_XTAL_S 31 +/** PMU_HP_MODEM_DIG_POWER_REG register + * need_des + */ +#define PMU_HP_MODEM_DIG_POWER_REG (DR_REG_PMU_BASE + 0x34) +/** PMU_HP_MODEM_VDD_SPI_PD_EN : R/W; bitpos: [21]; default: 0; + * need_des + */ +#define PMU_HP_MODEM_VDD_SPI_PD_EN (BIT(21)) +#define PMU_HP_MODEM_VDD_SPI_PD_EN_M (PMU_HP_MODEM_VDD_SPI_PD_EN_V << PMU_HP_MODEM_VDD_SPI_PD_EN_S) +#define PMU_HP_MODEM_VDD_SPI_PD_EN_V 0x00000001U +#define PMU_HP_MODEM_VDD_SPI_PD_EN_S 21 +/** PMU_HP_MODEM_HP_MEM_DSLP : R/W; bitpos: [22]; default: 0; + * need_des + */ +#define PMU_HP_MODEM_HP_MEM_DSLP (BIT(22)) +#define PMU_HP_MODEM_HP_MEM_DSLP_M (PMU_HP_MODEM_HP_MEM_DSLP_V << PMU_HP_MODEM_HP_MEM_DSLP_S) +#define PMU_HP_MODEM_HP_MEM_DSLP_V 0x00000001U +#define PMU_HP_MODEM_HP_MEM_DSLP_S 22 +/** PMU_HP_MODEM_PD_HP_MEM_PD_EN : R/W; bitpos: [26:23]; default: 0; + * need_des + */ +#define PMU_HP_MODEM_PD_HP_MEM_PD_EN 0x0000000FU +#define PMU_HP_MODEM_PD_HP_MEM_PD_EN_M (PMU_HP_MODEM_PD_HP_MEM_PD_EN_V << PMU_HP_MODEM_PD_HP_MEM_PD_EN_S) +#define PMU_HP_MODEM_PD_HP_MEM_PD_EN_V 0x0000000FU +#define PMU_HP_MODEM_PD_HP_MEM_PD_EN_S 23 +/** PMU_HP_MODEM_PD_HP_WIFI_PD_EN : R/W; bitpos: [27]; default: 0; + * need_des + */ +#define PMU_HP_MODEM_PD_HP_WIFI_PD_EN (BIT(27)) +#define PMU_HP_MODEM_PD_HP_WIFI_PD_EN_M (PMU_HP_MODEM_PD_HP_WIFI_PD_EN_V << PMU_HP_MODEM_PD_HP_WIFI_PD_EN_S) +#define PMU_HP_MODEM_PD_HP_WIFI_PD_EN_V 0x00000001U +#define PMU_HP_MODEM_PD_HP_WIFI_PD_EN_S 27 +/** PMU_HP_MODEM_PD_HP_CPU_PD_EN : R/W; bitpos: [29]; default: 0; + * need_des + */ +#define PMU_HP_MODEM_PD_HP_CPU_PD_EN (BIT(29)) +#define PMU_HP_MODEM_PD_HP_CPU_PD_EN_M (PMU_HP_MODEM_PD_HP_CPU_PD_EN_V << PMU_HP_MODEM_PD_HP_CPU_PD_EN_S) +#define PMU_HP_MODEM_PD_HP_CPU_PD_EN_V 0x00000001U +#define PMU_HP_MODEM_PD_HP_CPU_PD_EN_S 29 +/** PMU_HP_MODEM_PD_HP_AON_PD_EN : R/W; bitpos: [30]; default: 0; + * need_des + */ +#define PMU_HP_MODEM_PD_HP_AON_PD_EN (BIT(30)) +#define PMU_HP_MODEM_PD_HP_AON_PD_EN_M (PMU_HP_MODEM_PD_HP_AON_PD_EN_V << PMU_HP_MODEM_PD_HP_AON_PD_EN_S) +#define PMU_HP_MODEM_PD_HP_AON_PD_EN_V 0x00000001U +#define PMU_HP_MODEM_PD_HP_AON_PD_EN_S 30 +/** PMU_HP_MODEM_PD_TOP_PD_EN : R/W; bitpos: [31]; default: 0; + * need_des + */ +#define PMU_HP_MODEM_PD_TOP_PD_EN (BIT(31)) +#define PMU_HP_MODEM_PD_TOP_PD_EN_M (PMU_HP_MODEM_PD_TOP_PD_EN_V << PMU_HP_MODEM_PD_TOP_PD_EN_S) +#define PMU_HP_MODEM_PD_TOP_PD_EN_V 0x00000001U +#define PMU_HP_MODEM_PD_TOP_PD_EN_S 31 + +/** PMU_HP_MODEM_ICG_HP_FUNC_REG register + * need_des + */ +#define PMU_HP_MODEM_ICG_HP_FUNC_REG (DR_REG_PMU_BASE + 0x38) +/** PMU_HP_MODEM_DIG_ICG_FUNC_EN : R/W; bitpos: [31:0]; default: 4294967295; + * need_des + */ +#define PMU_HP_MODEM_DIG_ICG_FUNC_EN 0xFFFFFFFFU +#define PMU_HP_MODEM_DIG_ICG_FUNC_EN_M (PMU_HP_MODEM_DIG_ICG_FUNC_EN_V << PMU_HP_MODEM_DIG_ICG_FUNC_EN_S) +#define PMU_HP_MODEM_DIG_ICG_FUNC_EN_V 0xFFFFFFFFU +#define PMU_HP_MODEM_DIG_ICG_FUNC_EN_S 0 + +/** PMU_HP_MODEM_ICG_HP_APB_REG register + * need_des + */ +#define PMU_HP_MODEM_ICG_HP_APB_REG (DR_REG_PMU_BASE + 0x3c) +/** PMU_HP_MODEM_DIG_ICG_APB_EN : R/W; bitpos: [31:0]; default: 4294967295; + * need_des + */ +#define PMU_HP_MODEM_DIG_ICG_APB_EN 0xFFFFFFFFU +#define PMU_HP_MODEM_DIG_ICG_APB_EN_M (PMU_HP_MODEM_DIG_ICG_APB_EN_V << PMU_HP_MODEM_DIG_ICG_APB_EN_S) +#define PMU_HP_MODEM_DIG_ICG_APB_EN_V 0xFFFFFFFFU +#define PMU_HP_MODEM_DIG_ICG_APB_EN_S 0 + +/** PMU_HP_MODEM_ICG_MODEM_REG register + * need_des + */ +#define PMU_HP_MODEM_ICG_MODEM_REG (DR_REG_PMU_BASE + 0x40) +/** PMU_HP_MODEM_DIG_ICG_MODEM_CODE : R/W; bitpos: [31:30]; default: 0; + * need_des + */ +#define PMU_HP_MODEM_DIG_ICG_MODEM_CODE 0x00000003U +#define PMU_HP_MODEM_DIG_ICG_MODEM_CODE_M (PMU_HP_MODEM_DIG_ICG_MODEM_CODE_V << PMU_HP_MODEM_DIG_ICG_MODEM_CODE_S) +#define PMU_HP_MODEM_DIG_ICG_MODEM_CODE_V 0x00000003U +#define PMU_HP_MODEM_DIG_ICG_MODEM_CODE_S 30 + +/** PMU_HP_MODEM_HP_SYS_CNTL_REG register + * need_des + */ +#define PMU_HP_MODEM_HP_SYS_CNTL_REG (DR_REG_PMU_BASE + 0x44) +/** PMU_HP_MODEM_UART_WAKEUP_EN : R/W; bitpos: [24]; default: 0; + * need_des + */ +#define PMU_HP_MODEM_UART_WAKEUP_EN (BIT(24)) +#define PMU_HP_MODEM_UART_WAKEUP_EN_M (PMU_HP_MODEM_UART_WAKEUP_EN_V << PMU_HP_MODEM_UART_WAKEUP_EN_S) +#define PMU_HP_MODEM_UART_WAKEUP_EN_V 0x00000001U +#define PMU_HP_MODEM_UART_WAKEUP_EN_S 24 +/** PMU_HP_MODEM_LP_PAD_HOLD_ALL : R/W; bitpos: [25]; default: 0; + * need_des + */ +#define PMU_HP_MODEM_LP_PAD_HOLD_ALL (BIT(25)) +#define PMU_HP_MODEM_LP_PAD_HOLD_ALL_M (PMU_HP_MODEM_LP_PAD_HOLD_ALL_V << PMU_HP_MODEM_LP_PAD_HOLD_ALL_S) +#define PMU_HP_MODEM_LP_PAD_HOLD_ALL_V 0x00000001U +#define PMU_HP_MODEM_LP_PAD_HOLD_ALL_S 25 +/** PMU_HP_MODEM_HP_PAD_HOLD_ALL : R/W; bitpos: [26]; default: 0; + * need_des + */ +#define PMU_HP_MODEM_HP_PAD_HOLD_ALL (BIT(26)) +#define PMU_HP_MODEM_HP_PAD_HOLD_ALL_M (PMU_HP_MODEM_HP_PAD_HOLD_ALL_V << PMU_HP_MODEM_HP_PAD_HOLD_ALL_S) +#define PMU_HP_MODEM_HP_PAD_HOLD_ALL_V 0x00000001U +#define PMU_HP_MODEM_HP_PAD_HOLD_ALL_S 26 +/** PMU_HP_MODEM_DIG_PAD_SLP_SEL : R/W; bitpos: [27]; default: 0; + * need_des + */ +#define PMU_HP_MODEM_DIG_PAD_SLP_SEL (BIT(27)) +#define PMU_HP_MODEM_DIG_PAD_SLP_SEL_M (PMU_HP_MODEM_DIG_PAD_SLP_SEL_V << PMU_HP_MODEM_DIG_PAD_SLP_SEL_S) +#define PMU_HP_MODEM_DIG_PAD_SLP_SEL_V 0x00000001U +#define PMU_HP_MODEM_DIG_PAD_SLP_SEL_S 27 +/** PMU_HP_MODEM_DIG_PAUSE_WDT : R/W; bitpos: [28]; default: 0; + * need_des + */ +#define PMU_HP_MODEM_DIG_PAUSE_WDT (BIT(28)) +#define PMU_HP_MODEM_DIG_PAUSE_WDT_M (PMU_HP_MODEM_DIG_PAUSE_WDT_V << PMU_HP_MODEM_DIG_PAUSE_WDT_S) +#define PMU_HP_MODEM_DIG_PAUSE_WDT_V 0x00000001U +#define PMU_HP_MODEM_DIG_PAUSE_WDT_S 28 +/** PMU_HP_MODEM_DIG_CPU_STALL : R/W; bitpos: [29]; default: 0; + * need_des + */ +#define PMU_HP_MODEM_DIG_CPU_STALL (BIT(29)) +#define PMU_HP_MODEM_DIG_CPU_STALL_M (PMU_HP_MODEM_DIG_CPU_STALL_V << PMU_HP_MODEM_DIG_CPU_STALL_S) +#define PMU_HP_MODEM_DIG_CPU_STALL_V 0x00000001U +#define PMU_HP_MODEM_DIG_CPU_STALL_S 29 + +/** PMU_HP_MODEM_HP_CK_POWER_REG register + * need_des + */ +#define PMU_HP_MODEM_HP_CK_POWER_REG (DR_REG_PMU_BASE + 0x48) +/** PMU_HP_MODEM_I2C_ISO_EN : R/W; bitpos: [26]; default: 0; + * need_des + */ +#define PMU_HP_MODEM_I2C_ISO_EN (BIT(26)) +#define PMU_HP_MODEM_I2C_ISO_EN_M (PMU_HP_MODEM_I2C_ISO_EN_V << PMU_HP_MODEM_I2C_ISO_EN_S) +#define PMU_HP_MODEM_I2C_ISO_EN_V 0x00000001U +#define PMU_HP_MODEM_I2C_ISO_EN_S 26 +/** PMU_HP_MODEM_I2C_RETENTION : R/W; bitpos: [27]; default: 0; + * need_des + */ +#define PMU_HP_MODEM_I2C_RETENTION (BIT(27)) +#define PMU_HP_MODEM_I2C_RETENTION_M (PMU_HP_MODEM_I2C_RETENTION_V << PMU_HP_MODEM_I2C_RETENTION_S) +#define PMU_HP_MODEM_I2C_RETENTION_V 0x00000001U +#define PMU_HP_MODEM_I2C_RETENTION_S 27 +/** PMU_HP_MODEM_XPD_BB_I2C : R/W; bitpos: [28]; default: 0; + * need_des + */ +#define PMU_HP_MODEM_XPD_BB_I2C (BIT(28)) +#define PMU_HP_MODEM_XPD_BB_I2C_M (PMU_HP_MODEM_XPD_BB_I2C_V << PMU_HP_MODEM_XPD_BB_I2C_S) +#define PMU_HP_MODEM_XPD_BB_I2C_V 0x00000001U +#define PMU_HP_MODEM_XPD_BB_I2C_S 28 +/** PMU_HP_MODEM_XPD_BBPLL_I2C : R/W; bitpos: [29]; default: 0; + * need_des + */ +#define PMU_HP_MODEM_XPD_BBPLL_I2C (BIT(29)) +#define PMU_HP_MODEM_XPD_BBPLL_I2C_M (PMU_HP_MODEM_XPD_BBPLL_I2C_V << PMU_HP_MODEM_XPD_BBPLL_I2C_S) +#define PMU_HP_MODEM_XPD_BBPLL_I2C_V 0x00000001U +#define PMU_HP_MODEM_XPD_BBPLL_I2C_S 29 +/** PMU_HP_MODEM_XPD_BBPLL : R/W; bitpos: [30]; default: 0; + * need_des + */ +#define PMU_HP_MODEM_XPD_BBPLL (BIT(30)) +#define PMU_HP_MODEM_XPD_BBPLL_M (PMU_HP_MODEM_XPD_BBPLL_V << PMU_HP_MODEM_XPD_BBPLL_S) +#define PMU_HP_MODEM_XPD_BBPLL_V 0x00000001U +#define PMU_HP_MODEM_XPD_BBPLL_S 30 + +/** PMU_HP_MODEM_BIAS_REG register + * need_des + */ +#define PMU_HP_MODEM_BIAS_REG (DR_REG_PMU_BASE + 0x4c) +/** PMU_HP_MODEM_XPD_TRX : R/W; bitpos: [24]; default: 1; + * need_des + */ +#define PMU_HP_MODEM_XPD_TRX (BIT(24)) +#define PMU_HP_MODEM_XPD_TRX_M (PMU_HP_MODEM_XPD_TRX_V << PMU_HP_MODEM_XPD_TRX_S) +#define PMU_HP_MODEM_XPD_TRX_V 0x00000001U +#define PMU_HP_MODEM_XPD_TRX_S 24 +/** PMU_HP_MODEM_XPD_BIAS : R/W; bitpos: [25]; default: 0; + * need_des + */ +#define PMU_HP_MODEM_XPD_BIAS (BIT(25)) +#define PMU_HP_MODEM_XPD_BIAS_M (PMU_HP_MODEM_XPD_BIAS_V << PMU_HP_MODEM_XPD_BIAS_S) +#define PMU_HP_MODEM_XPD_BIAS_V 0x00000001U +#define PMU_HP_MODEM_XPD_BIAS_S 25 +/** PMU_HP_MODEM_PD_CUR : R/W; bitpos: [30]; default: 0; + * need_des + */ +#define PMU_HP_MODEM_PD_CUR (BIT(30)) +#define PMU_HP_MODEM_PD_CUR_M (PMU_HP_MODEM_PD_CUR_V << PMU_HP_MODEM_PD_CUR_S) +#define PMU_HP_MODEM_PD_CUR_V 0x00000001U +#define PMU_HP_MODEM_PD_CUR_S 30 +/** PMU_HP_MODEM_BIAS_SLEEP : R/W; bitpos: [31]; default: 0; + * need_des + */ +#define PMU_HP_MODEM_BIAS_SLEEP (BIT(31)) +#define PMU_HP_MODEM_BIAS_SLEEP_M (PMU_HP_MODEM_BIAS_SLEEP_V << PMU_HP_MODEM_BIAS_SLEEP_S) +#define PMU_HP_MODEM_BIAS_SLEEP_V 0x00000001U +#define PMU_HP_MODEM_BIAS_SLEEP_S 31 + +/** PMU_HP_MODEM_BACKUP_REG register + * need_des + */ +#define PMU_HP_MODEM_BACKUP_REG (DR_REG_PMU_BASE + 0x50) +/** PMU_HP_SLEEP2MODEM_BACKUP_MODEM_CLK_CODE : R/W; bitpos: [5:4]; default: 0; + * need_des + */ +#define PMU_HP_SLEEP2MODEM_BACKUP_MODEM_CLK_CODE 0x00000003U +#define PMU_HP_SLEEP2MODEM_BACKUP_MODEM_CLK_CODE_M (PMU_HP_SLEEP2MODEM_BACKUP_MODEM_CLK_CODE_V << PMU_HP_SLEEP2MODEM_BACKUP_MODEM_CLK_CODE_S) +#define PMU_HP_SLEEP2MODEM_BACKUP_MODEM_CLK_CODE_V 0x00000003U +#define PMU_HP_SLEEP2MODEM_BACKUP_MODEM_CLK_CODE_S 4 +/** PMU_HP_MODEM_RETENTION_MODE : R/W; bitpos: [10]; default: 0; + * need_des + */ +#define PMU_HP_MODEM_RETENTION_MODE (BIT(10)) +#define PMU_HP_MODEM_RETENTION_MODE_M (PMU_HP_MODEM_RETENTION_MODE_V << PMU_HP_MODEM_RETENTION_MODE_S) +#define PMU_HP_MODEM_RETENTION_MODE_V 0x00000001U +#define PMU_HP_MODEM_RETENTION_MODE_S 10 +/** PMU_HP_SLEEP2MODEM_RETENTION_EN : R/W; bitpos: [11]; default: 0; + * need_des + */ +#define PMU_HP_SLEEP2MODEM_RETENTION_EN (BIT(11)) +#define PMU_HP_SLEEP2MODEM_RETENTION_EN_M (PMU_HP_SLEEP2MODEM_RETENTION_EN_V << PMU_HP_SLEEP2MODEM_RETENTION_EN_S) +#define PMU_HP_SLEEP2MODEM_RETENTION_EN_V 0x00000001U +#define PMU_HP_SLEEP2MODEM_RETENTION_EN_S 11 +/** PMU_HP_SLEEP2MODEM_BACKUP_CLK_SEL : R/W; bitpos: [15:14]; default: 0; + * need_des + */ +#define PMU_HP_SLEEP2MODEM_BACKUP_CLK_SEL 0x00000003U +#define PMU_HP_SLEEP2MODEM_BACKUP_CLK_SEL_M (PMU_HP_SLEEP2MODEM_BACKUP_CLK_SEL_V << PMU_HP_SLEEP2MODEM_BACKUP_CLK_SEL_S) +#define PMU_HP_SLEEP2MODEM_BACKUP_CLK_SEL_V 0x00000003U +#define PMU_HP_SLEEP2MODEM_BACKUP_CLK_SEL_S 14 +/** PMU_HP_SLEEP2MODEM_BACKUP_MODE : R/W; bitpos: [22:20]; default: 0; + * need_des + */ +#define PMU_HP_SLEEP2MODEM_BACKUP_MODE 0x00000007U +#define PMU_HP_SLEEP2MODEM_BACKUP_MODE_M (PMU_HP_SLEEP2MODEM_BACKUP_MODE_V << PMU_HP_SLEEP2MODEM_BACKUP_MODE_S) +#define PMU_HP_SLEEP2MODEM_BACKUP_MODE_V 0x00000007U +#define PMU_HP_SLEEP2MODEM_BACKUP_MODE_S 20 +/** PMU_HP_SLEEP2MODEM_BACKUP_EN : R/W; bitpos: [29]; default: 0; + * need_des + */ +#define PMU_HP_SLEEP2MODEM_BACKUP_EN (BIT(29)) +#define PMU_HP_SLEEP2MODEM_BACKUP_EN_M (PMU_HP_SLEEP2MODEM_BACKUP_EN_V << PMU_HP_SLEEP2MODEM_BACKUP_EN_S) +#define PMU_HP_SLEEP2MODEM_BACKUP_EN_V 0x00000001U +#define PMU_HP_SLEEP2MODEM_BACKUP_EN_S 29 + +/** PMU_HP_MODEM_BACKUP_CLK_REG register + * need_des + */ +#define PMU_HP_MODEM_BACKUP_CLK_REG (DR_REG_PMU_BASE + 0x54) +/** PMU_HP_MODEM_BACKUP_ICG_FUNC_EN : R/W; bitpos: [31:0]; default: 0; + * need_des + */ +#define PMU_HP_MODEM_BACKUP_ICG_FUNC_EN 0xFFFFFFFFU +#define PMU_HP_MODEM_BACKUP_ICG_FUNC_EN_M (PMU_HP_MODEM_BACKUP_ICG_FUNC_EN_V << PMU_HP_MODEM_BACKUP_ICG_FUNC_EN_S) +#define PMU_HP_MODEM_BACKUP_ICG_FUNC_EN_V 0xFFFFFFFFU +#define PMU_HP_MODEM_BACKUP_ICG_FUNC_EN_S 0 + +/** PMU_HP_MODEM_SYSCLK_REG register + * need_des + */ +#define PMU_HP_MODEM_SYSCLK_REG (DR_REG_PMU_BASE + 0x58) +/** PMU_HP_MODEM_DIG_SYS_CLK_NO_DIV : R/W; bitpos: [26]; default: 0; + * need_des + */ +#define PMU_HP_MODEM_DIG_SYS_CLK_NO_DIV (BIT(26)) +#define PMU_HP_MODEM_DIG_SYS_CLK_NO_DIV_M (PMU_HP_MODEM_DIG_SYS_CLK_NO_DIV_V << PMU_HP_MODEM_DIG_SYS_CLK_NO_DIV_S) +#define PMU_HP_MODEM_DIG_SYS_CLK_NO_DIV_V 0x00000001U +#define PMU_HP_MODEM_DIG_SYS_CLK_NO_DIV_S 26 +/** PMU_HP_MODEM_ICG_SYS_CLOCK_EN : R/W; bitpos: [27]; default: 0; + * need_des + */ +#define PMU_HP_MODEM_ICG_SYS_CLOCK_EN (BIT(27)) +#define PMU_HP_MODEM_ICG_SYS_CLOCK_EN_M (PMU_HP_MODEM_ICG_SYS_CLOCK_EN_V << PMU_HP_MODEM_ICG_SYS_CLOCK_EN_S) +#define PMU_HP_MODEM_ICG_SYS_CLOCK_EN_V 0x00000001U +#define PMU_HP_MODEM_ICG_SYS_CLOCK_EN_S 27 +/** PMU_HP_MODEM_SYS_CLK_SLP_SEL : R/W; bitpos: [28]; default: 0; + * need_des + */ +#define PMU_HP_MODEM_SYS_CLK_SLP_SEL (BIT(28)) +#define PMU_HP_MODEM_SYS_CLK_SLP_SEL_M (PMU_HP_MODEM_SYS_CLK_SLP_SEL_V << PMU_HP_MODEM_SYS_CLK_SLP_SEL_S) +#define PMU_HP_MODEM_SYS_CLK_SLP_SEL_V 0x00000001U +#define PMU_HP_MODEM_SYS_CLK_SLP_SEL_S 28 +/** PMU_HP_MODEM_ICG_SLP_SEL : R/W; bitpos: [29]; default: 0; + * need_des + */ +#define PMU_HP_MODEM_ICG_SLP_SEL (BIT(29)) +#define PMU_HP_MODEM_ICG_SLP_SEL_M (PMU_HP_MODEM_ICG_SLP_SEL_V << PMU_HP_MODEM_ICG_SLP_SEL_S) +#define PMU_HP_MODEM_ICG_SLP_SEL_V 0x00000001U +#define PMU_HP_MODEM_ICG_SLP_SEL_S 29 +/** PMU_HP_MODEM_DIG_SYS_CLK_SEL : R/W; bitpos: [31:30]; default: 0; + * need_des + */ +#define PMU_HP_MODEM_DIG_SYS_CLK_SEL 0x00000003U +#define PMU_HP_MODEM_DIG_SYS_CLK_SEL_M (PMU_HP_MODEM_DIG_SYS_CLK_SEL_V << PMU_HP_MODEM_DIG_SYS_CLK_SEL_S) +#define PMU_HP_MODEM_DIG_SYS_CLK_SEL_V 0x00000003U +#define PMU_HP_MODEM_DIG_SYS_CLK_SEL_S 30 + +/** PMU_HP_MODEM_HP_REGULATOR0_REG register + * need_des + */ +#define PMU_HP_MODEM_HP_REGULATOR0_REG (DR_REG_PMU_BASE + 0x5c) +/** PMU_HP_MODEM_HP_POWER_DET_BYPASS : R/W; bitpos: [0]; default: 0; + * need_des + */ +#define PMU_HP_MODEM_HP_POWER_DET_BYPASS (BIT(0)) +#define PMU_HP_MODEM_HP_POWER_DET_BYPASS_M (PMU_HP_MODEM_HP_POWER_DET_BYPASS_V << PMU_HP_MODEM_HP_POWER_DET_BYPASS_S) +#define PMU_HP_MODEM_HP_POWER_DET_BYPASS_V 0x00000001U +#define PMU_HP_MODEM_HP_POWER_DET_BYPASS_S 0 +/** PMU_HP_MODEM_HP_REGULATOR_SLP_MEM_XPD : R/W; bitpos: [16]; default: 1; + * need_des + */ +#define PMU_HP_MODEM_HP_REGULATOR_SLP_MEM_XPD (BIT(16)) +#define PMU_HP_MODEM_HP_REGULATOR_SLP_MEM_XPD_M (PMU_HP_MODEM_HP_REGULATOR_SLP_MEM_XPD_V << PMU_HP_MODEM_HP_REGULATOR_SLP_MEM_XPD_S) +#define PMU_HP_MODEM_HP_REGULATOR_SLP_MEM_XPD_V 0x00000001U +#define PMU_HP_MODEM_HP_REGULATOR_SLP_MEM_XPD_S 16 +/** PMU_HP_MODEM_HP_REGULATOR_SLP_LOGIC_XPD : R/W; bitpos: [17]; default: 1; + * need_des + */ +#define PMU_HP_MODEM_HP_REGULATOR_SLP_LOGIC_XPD (BIT(17)) +#define PMU_HP_MODEM_HP_REGULATOR_SLP_LOGIC_XPD_M (PMU_HP_MODEM_HP_REGULATOR_SLP_LOGIC_XPD_V << PMU_HP_MODEM_HP_REGULATOR_SLP_LOGIC_XPD_S) +#define PMU_HP_MODEM_HP_REGULATOR_SLP_LOGIC_XPD_V 0x00000001U +#define PMU_HP_MODEM_HP_REGULATOR_SLP_LOGIC_XPD_S 17 +/** PMU_HP_MODEM_HP_REGULATOR_XPD : R/W; bitpos: [18]; default: 1; + * need_des + */ +#define PMU_HP_MODEM_HP_REGULATOR_XPD (BIT(18)) +#define PMU_HP_MODEM_HP_REGULATOR_XPD_M (PMU_HP_MODEM_HP_REGULATOR_XPD_V << PMU_HP_MODEM_HP_REGULATOR_XPD_S) +#define PMU_HP_MODEM_HP_REGULATOR_XPD_V 0x00000001U +#define PMU_HP_MODEM_HP_REGULATOR_XPD_S 18 +/** PMU_HP_MODEM_HP_REGULATOR_SLP_MEM_DBIAS : R/W; bitpos: [22:19]; default: 8; + * need_des + */ +#define PMU_HP_MODEM_HP_REGULATOR_SLP_MEM_DBIAS 0x0000000FU +#define PMU_HP_MODEM_HP_REGULATOR_SLP_MEM_DBIAS_M (PMU_HP_MODEM_HP_REGULATOR_SLP_MEM_DBIAS_V << PMU_HP_MODEM_HP_REGULATOR_SLP_MEM_DBIAS_S) +#define PMU_HP_MODEM_HP_REGULATOR_SLP_MEM_DBIAS_V 0x0000000FU +#define PMU_HP_MODEM_HP_REGULATOR_SLP_MEM_DBIAS_S 19 +/** PMU_HP_MODEM_HP_REGULATOR_SLP_LOGIC_DBIAS : R/W; bitpos: [26:23]; default: 8; + * need_des + */ +#define PMU_HP_MODEM_HP_REGULATOR_SLP_LOGIC_DBIAS 0x0000000FU +#define PMU_HP_MODEM_HP_REGULATOR_SLP_LOGIC_DBIAS_M (PMU_HP_MODEM_HP_REGULATOR_SLP_LOGIC_DBIAS_V << PMU_HP_MODEM_HP_REGULATOR_SLP_LOGIC_DBIAS_S) +#define PMU_HP_MODEM_HP_REGULATOR_SLP_LOGIC_DBIAS_V 0x0000000FU +#define PMU_HP_MODEM_HP_REGULATOR_SLP_LOGIC_DBIAS_S 23 +/** PMU_HP_MODEM_HP_REGULATOR_DBIAS : R/W; bitpos: [31:27]; default: 16; + * need_des + */ +#define PMU_HP_MODEM_HP_REGULATOR_DBIAS 0x0000001FU +#define PMU_HP_MODEM_HP_REGULATOR_DBIAS_M (PMU_HP_MODEM_HP_REGULATOR_DBIAS_V << PMU_HP_MODEM_HP_REGULATOR_DBIAS_S) +#define PMU_HP_MODEM_HP_REGULATOR_DBIAS_V 0x0000001FU +#define PMU_HP_MODEM_HP_REGULATOR_DBIAS_S 27 + +/** PMU_HP_MODEM_HP_REGULATOR1_REG register + * need_des + */ +#define PMU_HP_MODEM_HP_REGULATOR1_REG (DR_REG_PMU_BASE + 0x60) +/** PMU_HP_MODEM_HP_REGULATOR_DRV_B : R/W; bitpos: [31:8]; default: 0; + * need_des + */ +#define PMU_HP_MODEM_HP_REGULATOR_DRV_B 0x00FFFFFFU +#define PMU_HP_MODEM_HP_REGULATOR_DRV_B_M (PMU_HP_MODEM_HP_REGULATOR_DRV_B_V << PMU_HP_MODEM_HP_REGULATOR_DRV_B_S) +#define PMU_HP_MODEM_HP_REGULATOR_DRV_B_V 0x00FFFFFFU +#define PMU_HP_MODEM_HP_REGULATOR_DRV_B_S 8 + +/** PMU_HP_MODEM_XTAL_REG register + * need_des + */ +#define PMU_HP_MODEM_XTAL_REG (DR_REG_PMU_BASE + 0x64) +/** PMU_HP_MODEM_XPD_XTAL : R/W; bitpos: [31]; default: 1; + * need_des + */ +#define PMU_HP_MODEM_XPD_XTAL (BIT(31)) +#define PMU_HP_MODEM_XPD_XTAL_M (PMU_HP_MODEM_XPD_XTAL_V << PMU_HP_MODEM_XPD_XTAL_S) +#define PMU_HP_MODEM_XPD_XTAL_V 0x00000001U +#define PMU_HP_MODEM_XPD_XTAL_S 31 + /** PMU_HP_SLEEP_DIG_POWER_REG register * need_des */ #define PMU_HP_SLEEP_DIG_POWER_REG (DR_REG_PMU_BASE + 0x68) -/** PMU_HP_SLEEP_VDD_FLASH_MODE : R/W; bitpos: [21:18]; default: 0; +/** PMU_HP_SLEEP_VDD_SPI_PD_EN : R/W; bitpos: [21]; default: 0; * need_des */ -#define PMU_HP_SLEEP_VDD_FLASH_MODE 0x0000000FU -#define PMU_HP_SLEEP_VDD_FLASH_MODE_M (PMU_HP_SLEEP_VDD_FLASH_MODE_V << PMU_HP_SLEEP_VDD_FLASH_MODE_S) -#define PMU_HP_SLEEP_VDD_FLASH_MODE_V 0x0000000FU -#define PMU_HP_SLEEP_VDD_FLASH_MODE_S 18 +#define PMU_HP_SLEEP_VDD_SPI_PD_EN (BIT(21)) +#define PMU_HP_SLEEP_VDD_SPI_PD_EN_M (PMU_HP_SLEEP_VDD_SPI_PD_EN_V << PMU_HP_SLEEP_VDD_SPI_PD_EN_S) +#define PMU_HP_SLEEP_VDD_SPI_PD_EN_V 0x00000001U +#define PMU_HP_SLEEP_VDD_SPI_PD_EN_S 21 /** PMU_HP_SLEEP_HP_MEM_DSLP : R/W; bitpos: [22]; default: 0; * need_des */ @@ -535,13 +880,6 @@ extern "C" { #define PMU_HP_SLEEP_PD_HP_WIFI_PD_EN_M (PMU_HP_SLEEP_PD_HP_WIFI_PD_EN_V << PMU_HP_SLEEP_PD_HP_WIFI_PD_EN_S) #define PMU_HP_SLEEP_PD_HP_WIFI_PD_EN_V 0x00000001U #define PMU_HP_SLEEP_PD_HP_WIFI_PD_EN_S 27 -/** PMU_HP_SLEEP_PD_HP_PERI_PD_EN : R/W; bitpos: [28]; default: 0; - * need_des - */ -#define PMU_HP_SLEEP_PD_HP_PERI_PD_EN (BIT(28)) -#define PMU_HP_SLEEP_PD_HP_PERI_PD_EN_M (PMU_HP_SLEEP_PD_HP_PERI_PD_EN_V << PMU_HP_SLEEP_PD_HP_PERI_PD_EN_S) -#define PMU_HP_SLEEP_PD_HP_PERI_PD_EN_V 0x00000001U -#define PMU_HP_SLEEP_PD_HP_PERI_PD_EN_S 28 /** PMU_HP_SLEEP_PD_HP_CPU_PD_EN : R/W; bitpos: [29]; default: 0; * need_des */ @@ -691,48 +1029,6 @@ extern "C" { * need_des */ #define PMU_HP_SLEEP_BIAS_REG (DR_REG_PMU_BASE + 0x80) -/** PMU_HP_SLEEP_DCDC_CCM_ENB : R/W; bitpos: [9]; default: 1; - * need_des - */ -#define PMU_HP_SLEEP_DCDC_CCM_ENB (BIT(9)) -#define PMU_HP_SLEEP_DCDC_CCM_ENB_M (PMU_HP_SLEEP_DCDC_CCM_ENB_V << PMU_HP_SLEEP_DCDC_CCM_ENB_S) -#define PMU_HP_SLEEP_DCDC_CCM_ENB_V 0x00000001U -#define PMU_HP_SLEEP_DCDC_CCM_ENB_S 9 -/** PMU_HP_SLEEP_DCDC_CLEAR_RDY : R/W; bitpos: [10]; default: 0; - * need_des - */ -#define PMU_HP_SLEEP_DCDC_CLEAR_RDY (BIT(10)) -#define PMU_HP_SLEEP_DCDC_CLEAR_RDY_M (PMU_HP_SLEEP_DCDC_CLEAR_RDY_V << PMU_HP_SLEEP_DCDC_CLEAR_RDY_S) -#define PMU_HP_SLEEP_DCDC_CLEAR_RDY_V 0x00000001U -#define PMU_HP_SLEEP_DCDC_CLEAR_RDY_S 10 -/** PMU_HP_SLEEP_DIG_PMU_DPCUR_BIAS : R/W; bitpos: [12:11]; default: 1; - * need_des - */ -#define PMU_HP_SLEEP_DIG_PMU_DPCUR_BIAS 0x00000003U -#define PMU_HP_SLEEP_DIG_PMU_DPCUR_BIAS_M (PMU_HP_SLEEP_DIG_PMU_DPCUR_BIAS_V << PMU_HP_SLEEP_DIG_PMU_DPCUR_BIAS_S) -#define PMU_HP_SLEEP_DIG_PMU_DPCUR_BIAS_V 0x00000003U -#define PMU_HP_SLEEP_DIG_PMU_DPCUR_BIAS_S 11 -/** PMU_HP_SLEEP_DIG_PMU_DSFMOS : R/W; bitpos: [16:13]; default: 4; - * need_des - */ -#define PMU_HP_SLEEP_DIG_PMU_DSFMOS 0x0000000FU -#define PMU_HP_SLEEP_DIG_PMU_DSFMOS_M (PMU_HP_SLEEP_DIG_PMU_DSFMOS_V << PMU_HP_SLEEP_DIG_PMU_DSFMOS_S) -#define PMU_HP_SLEEP_DIG_PMU_DSFMOS_V 0x0000000FU -#define PMU_HP_SLEEP_DIG_PMU_DSFMOS_S 13 -/** PMU_HP_SLEEP_DCM_VSET : R/W; bitpos: [21:17]; default: 23; - * need_des - */ -#define PMU_HP_SLEEP_DCM_VSET 0x0000001FU -#define PMU_HP_SLEEP_DCM_VSET_M (PMU_HP_SLEEP_DCM_VSET_V << PMU_HP_SLEEP_DCM_VSET_S) -#define PMU_HP_SLEEP_DCM_VSET_V 0x0000001FU -#define PMU_HP_SLEEP_DCM_VSET_S 17 -/** PMU_HP_SLEEP_DCM_MODE : R/W; bitpos: [23:22]; default: 0; - * need_des - */ -#define PMU_HP_SLEEP_DCM_MODE 0x00000003U -#define PMU_HP_SLEEP_DCM_MODE_M (PMU_HP_SLEEP_DCM_MODE_V << PMU_HP_SLEEP_DCM_MODE_S) -#define PMU_HP_SLEEP_DCM_MODE_V 0x00000003U -#define PMU_HP_SLEEP_DCM_MODE_S 22 /** PMU_HP_SLEEP_XPD_TRX : R/W; bitpos: [24]; default: 1; * need_des */ @@ -747,13 +1043,6 @@ extern "C" { #define PMU_HP_SLEEP_XPD_BIAS_M (PMU_HP_SLEEP_XPD_BIAS_V << PMU_HP_SLEEP_XPD_BIAS_S) #define PMU_HP_SLEEP_XPD_BIAS_V 0x00000001U #define PMU_HP_SLEEP_XPD_BIAS_S 25 -/** PMU_HP_SLEEP_DISCNNT_DIG_RTC : R/W; bitpos: [29]; default: 0; - * need_des - */ -#define PMU_HP_SLEEP_DISCNNT_DIG_RTC (BIT(29)) -#define PMU_HP_SLEEP_DISCNNT_DIG_RTC_M (PMU_HP_SLEEP_DISCNNT_DIG_RTC_V << PMU_HP_SLEEP_DISCNNT_DIG_RTC_S) -#define PMU_HP_SLEEP_DISCNNT_DIG_RTC_V 0x00000001U -#define PMU_HP_SLEEP_DISCNNT_DIG_RTC_S 29 /** PMU_HP_SLEEP_PD_CUR : R/W; bitpos: [30]; default: 0; * need_des */ @@ -787,6 +1076,27 @@ extern "C" { #define PMU_HP_ACTIVE2SLEEP_BACKUP_MODEM_CLK_CODE_M (PMU_HP_ACTIVE2SLEEP_BACKUP_MODEM_CLK_CODE_V << PMU_HP_ACTIVE2SLEEP_BACKUP_MODEM_CLK_CODE_S) #define PMU_HP_ACTIVE2SLEEP_BACKUP_MODEM_CLK_CODE_V 0x00000003U #define PMU_HP_ACTIVE2SLEEP_BACKUP_MODEM_CLK_CODE_S 8 +/** PMU_HP_SLEEP_RETENTION_MODE : R/W; bitpos: [10]; default: 0; + * need_des + */ +#define PMU_HP_SLEEP_RETENTION_MODE (BIT(10)) +#define PMU_HP_SLEEP_RETENTION_MODE_M (PMU_HP_SLEEP_RETENTION_MODE_V << PMU_HP_SLEEP_RETENTION_MODE_S) +#define PMU_HP_SLEEP_RETENTION_MODE_V 0x00000001U +#define PMU_HP_SLEEP_RETENTION_MODE_S 10 +/** PMU_HP_MODEM2SLEEP_RETENTION_EN : R/W; bitpos: [12]; default: 0; + * need_des + */ +#define PMU_HP_MODEM2SLEEP_RETENTION_EN (BIT(12)) +#define PMU_HP_MODEM2SLEEP_RETENTION_EN_M (PMU_HP_MODEM2SLEEP_RETENTION_EN_V << PMU_HP_MODEM2SLEEP_RETENTION_EN_S) +#define PMU_HP_MODEM2SLEEP_RETENTION_EN_V 0x00000001U +#define PMU_HP_MODEM2SLEEP_RETENTION_EN_S 12 +/** PMU_HP_ACTIVE2SLEEP_RETENTION_EN : R/W; bitpos: [13]; default: 0; + * need_des + */ +#define PMU_HP_ACTIVE2SLEEP_RETENTION_EN (BIT(13)) +#define PMU_HP_ACTIVE2SLEEP_RETENTION_EN_M (PMU_HP_ACTIVE2SLEEP_RETENTION_EN_V << PMU_HP_ACTIVE2SLEEP_RETENTION_EN_S) +#define PMU_HP_ACTIVE2SLEEP_RETENTION_EN_V 0x00000001U +#define PMU_HP_ACTIVE2SLEEP_RETENTION_EN_S 13 /** PMU_HP_MODEM2SLEEP_BACKUP_CLK_SEL : R/W; bitpos: [17:16]; default: 0; * need_des */ @@ -801,20 +1111,20 @@ extern "C" { #define PMU_HP_ACTIVE2SLEEP_BACKUP_CLK_SEL_M (PMU_HP_ACTIVE2SLEEP_BACKUP_CLK_SEL_V << PMU_HP_ACTIVE2SLEEP_BACKUP_CLK_SEL_S) #define PMU_HP_ACTIVE2SLEEP_BACKUP_CLK_SEL_V 0x00000003U #define PMU_HP_ACTIVE2SLEEP_BACKUP_CLK_SEL_S 18 -/** PMU_HP_MODEM2SLEEP_BACKUP_MODE : R/W; bitpos: [24:20]; default: 0; +/** PMU_HP_MODEM2SLEEP_BACKUP_MODE : R/W; bitpos: [25:23]; default: 0; * need_des */ -#define PMU_HP_MODEM2SLEEP_BACKUP_MODE 0x0000001FU +#define PMU_HP_MODEM2SLEEP_BACKUP_MODE 0x00000007U #define PMU_HP_MODEM2SLEEP_BACKUP_MODE_M (PMU_HP_MODEM2SLEEP_BACKUP_MODE_V << PMU_HP_MODEM2SLEEP_BACKUP_MODE_S) -#define PMU_HP_MODEM2SLEEP_BACKUP_MODE_V 0x0000001FU -#define PMU_HP_MODEM2SLEEP_BACKUP_MODE_S 20 -/** PMU_HP_ACTIVE2SLEEP_BACKUP_MODE : R/W; bitpos: [29:25]; default: 0; +#define PMU_HP_MODEM2SLEEP_BACKUP_MODE_V 0x00000007U +#define PMU_HP_MODEM2SLEEP_BACKUP_MODE_S 23 +/** PMU_HP_ACTIVE2SLEEP_BACKUP_MODE : R/W; bitpos: [28:26]; default: 0; * need_des */ -#define PMU_HP_ACTIVE2SLEEP_BACKUP_MODE 0x0000001FU +#define PMU_HP_ACTIVE2SLEEP_BACKUP_MODE 0x00000007U #define PMU_HP_ACTIVE2SLEEP_BACKUP_MODE_M (PMU_HP_ACTIVE2SLEEP_BACKUP_MODE_V << PMU_HP_ACTIVE2SLEEP_BACKUP_MODE_S) -#define PMU_HP_ACTIVE2SLEEP_BACKUP_MODE_V 0x0000001FU -#define PMU_HP_ACTIVE2SLEEP_BACKUP_MODE_S 25 +#define PMU_HP_ACTIVE2SLEEP_BACKUP_MODE_V 0x00000007U +#define PMU_HP_ACTIVE2SLEEP_BACKUP_MODE_S 26 /** PMU_HP_MODEM2SLEEP_BACKUP_EN : R/W; bitpos: [30]; default: 0; * need_des */ @@ -952,13 +1262,6 @@ extern "C" { * need_des */ #define PMU_HP_SLEEP_XTAL_REG (DR_REG_PMU_BASE + 0x98) -/** PMU_HP_SLEEP_XPD_XTALX2 : R/W; bitpos: [30]; default: 1; - * need_des - */ -#define PMU_HP_SLEEP_XPD_XTALX2 (BIT(30)) -#define PMU_HP_SLEEP_XPD_XTALX2_M (PMU_HP_SLEEP_XPD_XTALX2_V << PMU_HP_SLEEP_XPD_XTALX2_S) -#define PMU_HP_SLEEP_XPD_XTALX2_V 0x00000001U -#define PMU_HP_SLEEP_XPD_XTALX2_S 30 /** PMU_HP_SLEEP_XPD_XTAL : R/W; bitpos: [31]; default: 1; * need_des */ @@ -992,7 +1295,7 @@ extern "C" { #define PMU_HP_SLEEP_LP_REGULATOR_SLP_DBIAS_M (PMU_HP_SLEEP_LP_REGULATOR_SLP_DBIAS_V << PMU_HP_SLEEP_LP_REGULATOR_SLP_DBIAS_S) #define PMU_HP_SLEEP_LP_REGULATOR_SLP_DBIAS_V 0x0000000FU #define PMU_HP_SLEEP_LP_REGULATOR_SLP_DBIAS_S 23 -/** PMU_HP_SLEEP_LP_REGULATOR_DBIAS : R/W; bitpos: [31:27]; default: 0; +/** PMU_HP_SLEEP_LP_REGULATOR_DBIAS : R/W; bitpos: [31:27]; default: 17; * need_des */ #define PMU_HP_SLEEP_LP_REGULATOR_DBIAS 0x0000001FU @@ -1012,17 +1315,22 @@ extern "C" { #define PMU_HP_SLEEP_LP_REGULATOR_DRV_B_V 0x0000000FU #define PMU_HP_SLEEP_LP_REGULATOR_DRV_B_S 28 -/** PMU_HP_SLEEP_LP_DIG_POWER_REG register +/** PMU_HP_SLEEP_LP_DCDC_RESERVE_REG register * need_des */ -#define PMU_HP_SLEEP_LP_DIG_POWER_REG (DR_REG_PMU_BASE + 0xa8) -/** PMU_HP_SLEEP_VDD_IO_MODE : R/W; bitpos: [26:23]; default: 0; +#define PMU_HP_SLEEP_LP_DCDC_RESERVE_REG (DR_REG_PMU_BASE + 0xa4) +/** PMU_HP_SLEEP_LP_DCDC_RESERVE : WT; bitpos: [31:0]; default: 0; * need_des */ -#define PMU_HP_SLEEP_VDD_IO_MODE 0x0000000FU -#define PMU_HP_SLEEP_VDD_IO_MODE_M (PMU_HP_SLEEP_VDD_IO_MODE_V << PMU_HP_SLEEP_VDD_IO_MODE_S) -#define PMU_HP_SLEEP_VDD_IO_MODE_V 0x0000000FU -#define PMU_HP_SLEEP_VDD_IO_MODE_S 23 +#define PMU_HP_SLEEP_LP_DCDC_RESERVE 0xFFFFFFFFU +#define PMU_HP_SLEEP_LP_DCDC_RESERVE_M (PMU_HP_SLEEP_LP_DCDC_RESERVE_V << PMU_HP_SLEEP_LP_DCDC_RESERVE_S) +#define PMU_HP_SLEEP_LP_DCDC_RESERVE_V 0xFFFFFFFFU +#define PMU_HP_SLEEP_LP_DCDC_RESERVE_S 0 + +/** PMU_HP_SLEEP_LP_DIG_POWER_REG register + * need_des + */ +#define PMU_HP_SLEEP_LP_DIG_POWER_REG (DR_REG_PMU_BASE + 0xa8) /** PMU_HP_SLEEP_BOD_SOURCE_SEL : R/W; bitpos: [27]; default: 0; * need_des */ @@ -1092,6 +1400,18 @@ extern "C" { #define PMU_HP_SLEEP_PD_OSC_CLK_V 0x00000001U #define PMU_HP_SLEEP_PD_OSC_CLK_S 31 +/** PMU_LP_SLEEP_LP_BIAS_RESERVE_REG register + * need_des + */ +#define PMU_LP_SLEEP_LP_BIAS_RESERVE_REG (DR_REG_PMU_BASE + 0xb0) +/** PMU_LP_SLEEP_LP_BIAS_RESERVE : WT; bitpos: [31:0]; default: 0; + * need_des + */ +#define PMU_LP_SLEEP_LP_BIAS_RESERVE 0xFFFFFFFFU +#define PMU_LP_SLEEP_LP_BIAS_RESERVE_M (PMU_LP_SLEEP_LP_BIAS_RESERVE_V << PMU_LP_SLEEP_LP_BIAS_RESERVE_S) +#define PMU_LP_SLEEP_LP_BIAS_RESERVE_V 0xFFFFFFFFU +#define PMU_LP_SLEEP_LP_BIAS_RESERVE_S 0 + /** PMU_LP_SLEEP_LP_REGULATOR0_REG register * need_des */ @@ -1117,7 +1437,7 @@ extern "C" { #define PMU_LP_SLEEP_LP_REGULATOR_SLP_DBIAS_M (PMU_LP_SLEEP_LP_REGULATOR_SLP_DBIAS_V << PMU_LP_SLEEP_LP_REGULATOR_SLP_DBIAS_S) #define PMU_LP_SLEEP_LP_REGULATOR_SLP_DBIAS_V 0x0000000FU #define PMU_LP_SLEEP_LP_REGULATOR_SLP_DBIAS_S 23 -/** PMU_LP_SLEEP_LP_REGULATOR_DBIAS : R/W; bitpos: [31:27]; default: 0; +/** PMU_LP_SLEEP_LP_REGULATOR_DBIAS : R/W; bitpos: [31:27]; default: 17; * need_des */ #define PMU_LP_SLEEP_LP_REGULATOR_DBIAS 0x0000001FU @@ -1141,13 +1461,6 @@ extern "C" { * need_des */ #define PMU_LP_SLEEP_XTAL_REG (DR_REG_PMU_BASE + 0xbc) -/** PMU_LP_SLEEP_XPD_XTALX2 : R/W; bitpos: [30]; default: 1; - * need_des - */ -#define PMU_LP_SLEEP_XPD_XTALX2 (BIT(30)) -#define PMU_LP_SLEEP_XPD_XTALX2_M (PMU_LP_SLEEP_XPD_XTALX2_V << PMU_LP_SLEEP_XPD_XTALX2_S) -#define PMU_LP_SLEEP_XPD_XTALX2_V 0x00000001U -#define PMU_LP_SLEEP_XPD_XTALX2_S 30 /** PMU_LP_SLEEP_XPD_XTAL : R/W; bitpos: [31]; default: 1; * need_des */ @@ -1160,13 +1473,6 @@ extern "C" { * need_des */ #define PMU_LP_SLEEP_LP_DIG_POWER_REG (DR_REG_PMU_BASE + 0xc0) -/** PMU_LP_SLEEP_VDD_IO_MODE : R/W; bitpos: [26:23]; default: 0; - * need_des - */ -#define PMU_LP_SLEEP_VDD_IO_MODE 0x0000000FU -#define PMU_LP_SLEEP_VDD_IO_MODE_M (PMU_LP_SLEEP_VDD_IO_MODE_V << PMU_LP_SLEEP_VDD_IO_MODE_S) -#define PMU_LP_SLEEP_VDD_IO_MODE_V 0x0000000FU -#define PMU_LP_SLEEP_VDD_IO_MODE_S 23 /** PMU_LP_SLEEP_BOD_SOURCE_SEL : R/W; bitpos: [27]; default: 0; * need_des */ @@ -1240,48 +1546,6 @@ extern "C" { * need_des */ #define PMU_LP_SLEEP_BIAS_REG (DR_REG_PMU_BASE + 0xc8) -/** PMU_LP_SLEEP_DCDC_CCM_ENB : R/W; bitpos: [9]; default: 1; - * need_des - */ -#define PMU_LP_SLEEP_DCDC_CCM_ENB (BIT(9)) -#define PMU_LP_SLEEP_DCDC_CCM_ENB_M (PMU_LP_SLEEP_DCDC_CCM_ENB_V << PMU_LP_SLEEP_DCDC_CCM_ENB_S) -#define PMU_LP_SLEEP_DCDC_CCM_ENB_V 0x00000001U -#define PMU_LP_SLEEP_DCDC_CCM_ENB_S 9 -/** PMU_LP_SLEEP_DCDC_CLEAR_RDY : R/W; bitpos: [10]; default: 0; - * need_des - */ -#define PMU_LP_SLEEP_DCDC_CLEAR_RDY (BIT(10)) -#define PMU_LP_SLEEP_DCDC_CLEAR_RDY_M (PMU_LP_SLEEP_DCDC_CLEAR_RDY_V << PMU_LP_SLEEP_DCDC_CLEAR_RDY_S) -#define PMU_LP_SLEEP_DCDC_CLEAR_RDY_V 0x00000001U -#define PMU_LP_SLEEP_DCDC_CLEAR_RDY_S 10 -/** PMU_LP_SLEEP_DIG_PMU_DPCUR_BIAS : R/W; bitpos: [12:11]; default: 1; - * need_des - */ -#define PMU_LP_SLEEP_DIG_PMU_DPCUR_BIAS 0x00000003U -#define PMU_LP_SLEEP_DIG_PMU_DPCUR_BIAS_M (PMU_LP_SLEEP_DIG_PMU_DPCUR_BIAS_V << PMU_LP_SLEEP_DIG_PMU_DPCUR_BIAS_S) -#define PMU_LP_SLEEP_DIG_PMU_DPCUR_BIAS_V 0x00000003U -#define PMU_LP_SLEEP_DIG_PMU_DPCUR_BIAS_S 11 -/** PMU_LP_SLEEP_DIG_PMU_DSFMOS : R/W; bitpos: [16:13]; default: 4; - * need_des - */ -#define PMU_LP_SLEEP_DIG_PMU_DSFMOS 0x0000000FU -#define PMU_LP_SLEEP_DIG_PMU_DSFMOS_M (PMU_LP_SLEEP_DIG_PMU_DSFMOS_V << PMU_LP_SLEEP_DIG_PMU_DSFMOS_S) -#define PMU_LP_SLEEP_DIG_PMU_DSFMOS_V 0x0000000FU -#define PMU_LP_SLEEP_DIG_PMU_DSFMOS_S 13 -/** PMU_LP_SLEEP_DCM_VSET : R/W; bitpos: [21:17]; default: 23; - * need_des - */ -#define PMU_LP_SLEEP_DCM_VSET 0x0000001FU -#define PMU_LP_SLEEP_DCM_VSET_M (PMU_LP_SLEEP_DCM_VSET_V << PMU_LP_SLEEP_DCM_VSET_S) -#define PMU_LP_SLEEP_DCM_VSET_V 0x0000001FU -#define PMU_LP_SLEEP_DCM_VSET_S 17 -/** PMU_LP_SLEEP_DCM_MODE : R/W; bitpos: [23:22]; default: 0; - * need_des - */ -#define PMU_LP_SLEEP_DCM_MODE 0x00000003U -#define PMU_LP_SLEEP_DCM_MODE_M (PMU_LP_SLEEP_DCM_MODE_V << PMU_LP_SLEEP_DCM_MODE_S) -#define PMU_LP_SLEEP_DCM_MODE_V 0x00000003U -#define PMU_LP_SLEEP_DCM_MODE_S 22 /** PMU_LP_SLEEP_XPD_BIAS : R/W; bitpos: [25]; default: 0; * need_des */ @@ -1289,13 +1553,6 @@ extern "C" { #define PMU_LP_SLEEP_XPD_BIAS_M (PMU_LP_SLEEP_XPD_BIAS_V << PMU_LP_SLEEP_XPD_BIAS_S) #define PMU_LP_SLEEP_XPD_BIAS_V 0x00000001U #define PMU_LP_SLEEP_XPD_BIAS_S 25 -/** PMU_LP_SLEEP_DISCNNT_DIG_RTC : R/W; bitpos: [29]; default: 0; - * need_des - */ -#define PMU_LP_SLEEP_DISCNNT_DIG_RTC (BIT(29)) -#define PMU_LP_SLEEP_DISCNNT_DIG_RTC_M (PMU_LP_SLEEP_DISCNNT_DIG_RTC_V << PMU_LP_SLEEP_DISCNNT_DIG_RTC_S) -#define PMU_LP_SLEEP_DISCNNT_DIG_RTC_V 0x00000001U -#define PMU_LP_SLEEP_DISCNNT_DIG_RTC_S 29 /** PMU_LP_SLEEP_PD_CUR : R/W; bitpos: [30]; default: 0; * need_des */ @@ -1364,34 +1621,6 @@ extern "C" { #define PMU_TIE_LOW_XPD_XTAL_M (PMU_TIE_LOW_XPD_XTAL_V << PMU_TIE_LOW_XPD_XTAL_S) #define PMU_TIE_LOW_XPD_XTAL_V 0x00000001U #define PMU_TIE_LOW_XPD_XTAL_S 6 -/** PMU_TIE_LOW_GLOBAL_XTALX2_ICG : WT; bitpos: [7]; default: 0; - * need_des - */ -#define PMU_TIE_LOW_GLOBAL_XTALX2_ICG (BIT(7)) -#define PMU_TIE_LOW_GLOBAL_XTALX2_ICG_M (PMU_TIE_LOW_GLOBAL_XTALX2_ICG_V << PMU_TIE_LOW_GLOBAL_XTALX2_ICG_S) -#define PMU_TIE_LOW_GLOBAL_XTALX2_ICG_V 0x00000001U -#define PMU_TIE_LOW_GLOBAL_XTALX2_ICG_S 7 -/** PMU_TIE_LOW_XPD_XTALX2 : WT; bitpos: [8]; default: 0; - * need_des - */ -#define PMU_TIE_LOW_XPD_XTALX2 (BIT(8)) -#define PMU_TIE_LOW_XPD_XTALX2_M (PMU_TIE_LOW_XPD_XTALX2_V << PMU_TIE_LOW_XPD_XTALX2_S) -#define PMU_TIE_LOW_XPD_XTALX2_V 0x00000001U -#define PMU_TIE_LOW_XPD_XTALX2_S 8 -/** PMU_TIE_HIGH_XTALX2 : WT; bitpos: [23]; default: 0; - * need_des - */ -#define PMU_TIE_HIGH_XTALX2 (BIT(23)) -#define PMU_TIE_HIGH_XTALX2_M (PMU_TIE_HIGH_XTALX2_V << PMU_TIE_HIGH_XTALX2_S) -#define PMU_TIE_HIGH_XTALX2_V 0x00000001U -#define PMU_TIE_HIGH_XTALX2_S 23 -/** PMU_TIE_HIGH_GLOBAL_XTALX2_ICG : WT; bitpos: [24]; default: 0; - * need_des - */ -#define PMU_TIE_HIGH_GLOBAL_XTALX2_ICG (BIT(24)) -#define PMU_TIE_HIGH_GLOBAL_XTALX2_ICG_M (PMU_TIE_HIGH_GLOBAL_XTALX2_ICG_V << PMU_TIE_HIGH_GLOBAL_XTALX2_ICG_S) -#define PMU_TIE_HIGH_GLOBAL_XTALX2_ICG_V 0x00000001U -#define PMU_TIE_HIGH_GLOBAL_XTALX2_ICG_S 24 /** PMU_TIE_HIGH_GLOBAL_BBPLL_ICG : WT; bitpos: [25]; default: 0; * need_des */ @@ -1534,20 +1763,6 @@ extern "C" { * need_des */ #define PMU_IMM_PAD_HOLD_ALL_REG (DR_REG_PMU_BASE + 0xe4) -/** PMU_TIE_HIGH_DIG_PAD_SLP_SEL : WT; bitpos: [26]; default: 0; - * need_des - */ -#define PMU_TIE_HIGH_DIG_PAD_SLP_SEL (BIT(26)) -#define PMU_TIE_HIGH_DIG_PAD_SLP_SEL_M (PMU_TIE_HIGH_DIG_PAD_SLP_SEL_V << PMU_TIE_HIGH_DIG_PAD_SLP_SEL_S) -#define PMU_TIE_HIGH_DIG_PAD_SLP_SEL_V 0x00000001U -#define PMU_TIE_HIGH_DIG_PAD_SLP_SEL_S 26 -/** PMU_TIE_LOW_DIG_PAD_SLP_SEL : WT; bitpos: [27]; default: 0; - * need_des - */ -#define PMU_TIE_LOW_DIG_PAD_SLP_SEL (BIT(27)) -#define PMU_TIE_LOW_DIG_PAD_SLP_SEL_M (PMU_TIE_LOW_DIG_PAD_SLP_SEL_V << PMU_TIE_LOW_DIG_PAD_SLP_SEL_S) -#define PMU_TIE_LOW_DIG_PAD_SLP_SEL_V 0x00000001U -#define PMU_TIE_LOW_DIG_PAD_SLP_SEL_S 27 /** PMU_TIE_HIGH_LP_PAD_HOLD_ALL : WT; bitpos: [28]; default: 0; * need_des */ @@ -1614,77 +1829,44 @@ extern "C" { #define PMU_DG_HP_POWERUP_TIMER_M (PMU_DG_HP_POWERUP_TIMER_V << PMU_DG_HP_POWERUP_TIMER_S) #define PMU_DG_HP_POWERUP_TIMER_V 0x000001FFU #define PMU_DG_HP_POWERUP_TIMER_S 14 -/** PMU_DG_HP_PD_WAIT_TIMER : R/W; bitpos: [31:23]; default: 255; +/** PMU_DG_HP_WAIT_TIMER : R/W; bitpos: [31:23]; default: 255; * need_des */ -#define PMU_DG_HP_PD_WAIT_TIMER 0x000001FFU -#define PMU_DG_HP_PD_WAIT_TIMER_M (PMU_DG_HP_PD_WAIT_TIMER_V << PMU_DG_HP_PD_WAIT_TIMER_S) -#define PMU_DG_HP_PD_WAIT_TIMER_V 0x000001FFU -#define PMU_DG_HP_PD_WAIT_TIMER_S 23 +#define PMU_DG_HP_WAIT_TIMER 0x000001FFU +#define PMU_DG_HP_WAIT_TIMER_M (PMU_DG_HP_WAIT_TIMER_V << PMU_DG_HP_WAIT_TIMER_S) +#define PMU_DG_HP_WAIT_TIMER_V 0x000001FFU +#define PMU_DG_HP_WAIT_TIMER_S 23 /** PMU_POWER_WAIT_TIMER1_REG register * need_des */ #define PMU_POWER_WAIT_TIMER1_REG (DR_REG_PMU_BASE + 0xf0) -/** PMU_DG_LP_POWERDOWN_TIMER : R/W; bitpos: [15:9]; default: 63; +/** PMU_DG_LP_POWERDOWN_TIMER : R/W; bitpos: [15:9]; default: 255; * need_des */ #define PMU_DG_LP_POWERDOWN_TIMER 0x0000007FU #define PMU_DG_LP_POWERDOWN_TIMER_M (PMU_DG_LP_POWERDOWN_TIMER_V << PMU_DG_LP_POWERDOWN_TIMER_S) #define PMU_DG_LP_POWERDOWN_TIMER_V 0x0000007FU #define PMU_DG_LP_POWERDOWN_TIMER_S 9 -/** PMU_DG_LP_POWERUP_TIMER : R/W; bitpos: [22:16]; default: 63; +/** PMU_DG_LP_POWERUP_TIMER : R/W; bitpos: [22:16]; default: 255; * need_des */ #define PMU_DG_LP_POWERUP_TIMER 0x0000007FU #define PMU_DG_LP_POWERUP_TIMER_M (PMU_DG_LP_POWERUP_TIMER_V << PMU_DG_LP_POWERUP_TIMER_S) #define PMU_DG_LP_POWERUP_TIMER_V 0x0000007FU #define PMU_DG_LP_POWERUP_TIMER_S 16 -/** PMU_DG_LP_PD_WAIT_TIMER : R/W; bitpos: [31:23]; default: 255; +/** PMU_DG_LP_WAIT_TIMER : R/W; bitpos: [31:23]; default: 255; * need_des */ -#define PMU_DG_LP_PD_WAIT_TIMER 0x000001FFU -#define PMU_DG_LP_PD_WAIT_TIMER_M (PMU_DG_LP_PD_WAIT_TIMER_V << PMU_DG_LP_PD_WAIT_TIMER_S) -#define PMU_DG_LP_PD_WAIT_TIMER_V 0x000001FFU -#define PMU_DG_LP_PD_WAIT_TIMER_S 23 - -/** PMU_POWER_WAIT_TIMER2_REG register - * need_des - */ -#define PMU_POWER_WAIT_TIMER2_REG (DR_REG_PMU_BASE + 0xf4) -/** PMU_DG_LP_ISO_WAIT_TIMER : R/W; bitpos: [7:0]; default: 255; - * need_des - */ -#define PMU_DG_LP_ISO_WAIT_TIMER 0x000000FFU -#define PMU_DG_LP_ISO_WAIT_TIMER_M (PMU_DG_LP_ISO_WAIT_TIMER_V << PMU_DG_LP_ISO_WAIT_TIMER_S) -#define PMU_DG_LP_ISO_WAIT_TIMER_V 0x000000FFU -#define PMU_DG_LP_ISO_WAIT_TIMER_S 0 -/** PMU_DG_LP_RST_WAIT_TIMER : R/W; bitpos: [15:8]; default: 255; - * need_des - */ -#define PMU_DG_LP_RST_WAIT_TIMER 0x000000FFU -#define PMU_DG_LP_RST_WAIT_TIMER_M (PMU_DG_LP_RST_WAIT_TIMER_V << PMU_DG_LP_RST_WAIT_TIMER_S) -#define PMU_DG_LP_RST_WAIT_TIMER_V 0x000000FFU -#define PMU_DG_LP_RST_WAIT_TIMER_S 8 -/** PMU_DG_HP_ISO_WAIT_TIMER : R/W; bitpos: [23:16]; default: 255; - * need_des - */ -#define PMU_DG_HP_ISO_WAIT_TIMER 0x000000FFU -#define PMU_DG_HP_ISO_WAIT_TIMER_M (PMU_DG_HP_ISO_WAIT_TIMER_V << PMU_DG_HP_ISO_WAIT_TIMER_S) -#define PMU_DG_HP_ISO_WAIT_TIMER_V 0x000000FFU -#define PMU_DG_HP_ISO_WAIT_TIMER_S 16 -/** PMU_DG_HP_RST_WAIT_TIMER : R/W; bitpos: [31:24]; default: 255; - * need_des - */ -#define PMU_DG_HP_RST_WAIT_TIMER 0x000000FFU -#define PMU_DG_HP_RST_WAIT_TIMER_M (PMU_DG_HP_RST_WAIT_TIMER_V << PMU_DG_HP_RST_WAIT_TIMER_S) -#define PMU_DG_HP_RST_WAIT_TIMER_V 0x000000FFU -#define PMU_DG_HP_RST_WAIT_TIMER_S 24 +#define PMU_DG_LP_WAIT_TIMER 0x000001FFU +#define PMU_DG_LP_WAIT_TIMER_M (PMU_DG_LP_WAIT_TIMER_V << PMU_DG_LP_WAIT_TIMER_S) +#define PMU_DG_LP_WAIT_TIMER_V 0x000001FFU +#define PMU_DG_LP_WAIT_TIMER_S 23 /** PMU_POWER_PD_TOP_CNTL_REG register * need_des */ -#define PMU_POWER_PD_TOP_CNTL_REG (DR_REG_PMU_BASE + 0xf8) +#define PMU_POWER_PD_TOP_CNTL_REG (DR_REG_PMU_BASE + 0xf4) /** PMU_FORCE_TOP_RESET : R/W; bitpos: [0]; default: 0; * need_des */ @@ -1745,7 +1927,7 @@ extern "C" { /** PMU_POWER_PD_HPAON_CNTL_REG register * need_des */ -#define PMU_POWER_PD_HPAON_CNTL_REG (DR_REG_PMU_BASE + 0xfc) +#define PMU_POWER_PD_HPAON_CNTL_REG (DR_REG_PMU_BASE + 0xf8) /** PMU_FORCE_HP_AON_RESET : R/W; bitpos: [0]; default: 0; * need_des */ @@ -1806,7 +1988,7 @@ extern "C" { /** PMU_POWER_PD_HPCPU_CNTL_REG register * need_des */ -#define PMU_POWER_PD_HPCPU_CNTL_REG (DR_REG_PMU_BASE + 0x100) +#define PMU_POWER_PD_HPCPU_CNTL_REG (DR_REG_PMU_BASE + 0xfc) /** PMU_FORCE_HP_CPU_RESET : R/W; bitpos: [0]; default: 0; * need_des */ @@ -1867,68 +2049,19 @@ extern "C" { /** PMU_POWER_PD_HPPERI_RESERVE_REG register * need_des */ -#define PMU_POWER_PD_HPPERI_RESERVE_REG (DR_REG_PMU_BASE + 0x104) -/** PMU_FORCE_HP_PERI_RESET : R/W; bitpos: [0]; default: 0; - * need_des - */ -#define PMU_FORCE_HP_PERI_RESET (BIT(0)) -#define PMU_FORCE_HP_PERI_RESET_M (PMU_FORCE_HP_PERI_RESET_V << PMU_FORCE_HP_PERI_RESET_S) -#define PMU_FORCE_HP_PERI_RESET_V 0x00000001U -#define PMU_FORCE_HP_PERI_RESET_S 0 -/** PMU_FORCE_HP_PERI_ISO : R/W; bitpos: [1]; default: 0; +#define PMU_POWER_PD_HPPERI_RESERVE_REG (DR_REG_PMU_BASE + 0x100) +/** PMU_HP_PERI_RESERVE : WT; bitpos: [31:0]; default: 0; * need_des */ -#define PMU_FORCE_HP_PERI_ISO (BIT(1)) -#define PMU_FORCE_HP_PERI_ISO_M (PMU_FORCE_HP_PERI_ISO_V << PMU_FORCE_HP_PERI_ISO_S) -#define PMU_FORCE_HP_PERI_ISO_V 0x00000001U -#define PMU_FORCE_HP_PERI_ISO_S 1 -/** PMU_FORCE_HP_PERI_PU : R/W; bitpos: [2]; default: 1; - * need_des - */ -#define PMU_FORCE_HP_PERI_PU (BIT(2)) -#define PMU_FORCE_HP_PERI_PU_M (PMU_FORCE_HP_PERI_PU_V << PMU_FORCE_HP_PERI_PU_S) -#define PMU_FORCE_HP_PERI_PU_V 0x00000001U -#define PMU_FORCE_HP_PERI_PU_S 2 -/** PMU_FORCE_HP_PERI_NO_RESET : R/W; bitpos: [3]; default: 1; - * need_des - */ -#define PMU_FORCE_HP_PERI_NO_RESET (BIT(3)) -#define PMU_FORCE_HP_PERI_NO_RESET_M (PMU_FORCE_HP_PERI_NO_RESET_V << PMU_FORCE_HP_PERI_NO_RESET_S) -#define PMU_FORCE_HP_PERI_NO_RESET_V 0x00000001U -#define PMU_FORCE_HP_PERI_NO_RESET_S 3 -/** PMU_FORCE_HP_PERI_NO_ISO : R/W; bitpos: [4]; default: 1; - * need_des - */ -#define PMU_FORCE_HP_PERI_NO_ISO (BIT(4)) -#define PMU_FORCE_HP_PERI_NO_ISO_M (PMU_FORCE_HP_PERI_NO_ISO_V << PMU_FORCE_HP_PERI_NO_ISO_S) -#define PMU_FORCE_HP_PERI_NO_ISO_V 0x00000001U -#define PMU_FORCE_HP_PERI_NO_ISO_S 4 -/** PMU_FORCE_HP_PERI_PD : R/W; bitpos: [5]; default: 0; - * need_des - */ -#define PMU_FORCE_HP_PERI_PD (BIT(5)) -#define PMU_FORCE_HP_PERI_PD_M (PMU_FORCE_HP_PERI_PD_V << PMU_FORCE_HP_PERI_PD_S) -#define PMU_FORCE_HP_PERI_PD_V 0x00000001U -#define PMU_FORCE_HP_PERI_PD_S 5 -/** PMU_PD_HP_PERI_MASK : R/W; bitpos: [10:6]; default: 0; - * need_des - */ -#define PMU_PD_HP_PERI_MASK 0x0000001FU -#define PMU_PD_HP_PERI_MASK_M (PMU_PD_HP_PERI_MASK_V << PMU_PD_HP_PERI_MASK_S) -#define PMU_PD_HP_PERI_MASK_V 0x0000001FU -#define PMU_PD_HP_PERI_MASK_S 6 -/** PMU_PD_HP_PERI_PD_MASK : R/W; bitpos: [31:27]; default: 0; - * need_des - */ -#define PMU_PD_HP_PERI_PD_MASK 0x0000001FU -#define PMU_PD_HP_PERI_PD_MASK_M (PMU_PD_HP_PERI_PD_MASK_V << PMU_PD_HP_PERI_PD_MASK_S) -#define PMU_PD_HP_PERI_PD_MASK_V 0x0000001FU -#define PMU_PD_HP_PERI_PD_MASK_S 27 +#define PMU_HP_PERI_RESERVE 0xFFFFFFFFU +#define PMU_HP_PERI_RESERVE_M (PMU_HP_PERI_RESERVE_V << PMU_HP_PERI_RESERVE_S) +#define PMU_HP_PERI_RESERVE_V 0xFFFFFFFFU +#define PMU_HP_PERI_RESERVE_S 0 /** PMU_POWER_PD_HPWIFI_CNTL_REG register * need_des */ -#define PMU_POWER_PD_HPWIFI_CNTL_REG (DR_REG_PMU_BASE + 0x108) +#define PMU_POWER_PD_HPWIFI_CNTL_REG (DR_REG_PMU_BASE + 0x104) /** PMU_FORCE_HP_WIFI_RESET : R/W; bitpos: [0]; default: 0; * need_des */ @@ -1989,7 +2122,7 @@ extern "C" { /** PMU_POWER_PD_LPPERI_CNTL_REG register * need_des */ -#define PMU_POWER_PD_LPPERI_CNTL_REG (DR_REG_PMU_BASE + 0x10c) +#define PMU_POWER_PD_LPPERI_CNTL_REG (DR_REG_PMU_BASE + 0x108) /** PMU_FORCE_LP_PERI_RESET : R/W; bitpos: [0]; default: 0; * need_des */ @@ -2036,7 +2169,7 @@ extern "C" { /** PMU_POWER_PD_MEM_CNTL_REG register * need_des */ -#define PMU_POWER_PD_MEM_CNTL_REG (DR_REG_PMU_BASE + 0x110) +#define PMU_POWER_PD_MEM_CNTL_REG (DR_REG_PMU_BASE + 0x10c) /** PMU_FORCE_HP_MEM_ISO : R/W; bitpos: [3:0]; default: 0; * need_des */ @@ -2069,7 +2202,7 @@ extern "C" { /** PMU_POWER_PD_MEM_MASK_REG register * need_des */ -#define PMU_POWER_PD_MEM_MASK_REG (DR_REG_PMU_BASE + 0x114) +#define PMU_POWER_PD_MEM_MASK_REG (DR_REG_PMU_BASE + 0x110) /** PMU_PD_HP_MEM2_PD_MASK : R/W; bitpos: [4:0]; default: 0; * need_des */ @@ -2116,7 +2249,7 @@ extern "C" { /** PMU_POWER_HP_PAD_REG register * need_des */ -#define PMU_POWER_HP_PAD_REG (DR_REG_PMU_BASE + 0x118) +#define PMU_POWER_HP_PAD_REG (DR_REG_PMU_BASE + 0x114) /** PMU_FORCE_HP_PAD_NO_ISO_ALL : R/W; bitpos: [0]; default: 0; * need_des */ @@ -2132,350 +2265,36 @@ extern "C" { #define PMU_FORCE_HP_PAD_ISO_ALL_V 0x00000001U #define PMU_FORCE_HP_PAD_ISO_ALL_S 1 -/** PMU_POWER_FLASH1P8_LDO_REG register - * need_des - */ -#define PMU_POWER_FLASH1P8_LDO_REG (DR_REG_PMU_BASE + 0x11c) -/** PMU_FLASH1P8_LDO_RDY : RO; bitpos: [0]; default: 1; - * need_des - */ -#define PMU_FLASH1P8_LDO_RDY (BIT(0)) -#define PMU_FLASH1P8_LDO_RDY_M (PMU_FLASH1P8_LDO_RDY_V << PMU_FLASH1P8_LDO_RDY_S) -#define PMU_FLASH1P8_LDO_RDY_V 0x00000001U -#define PMU_FLASH1P8_LDO_RDY_S 0 -/** PMU_FLASH1P8_SW_EN_XPD : R/W; bitpos: [1]; default: 0; - * need_des - */ -#define PMU_FLASH1P8_SW_EN_XPD (BIT(1)) -#define PMU_FLASH1P8_SW_EN_XPD_M (PMU_FLASH1P8_SW_EN_XPD_V << PMU_FLASH1P8_SW_EN_XPD_S) -#define PMU_FLASH1P8_SW_EN_XPD_V 0x00000001U -#define PMU_FLASH1P8_SW_EN_XPD_S 1 -/** PMU_FLASH1P8_SW_EN_THRU : R/W; bitpos: [2]; default: 0; - * need_des - */ -#define PMU_FLASH1P8_SW_EN_THRU (BIT(2)) -#define PMU_FLASH1P8_SW_EN_THRU_M (PMU_FLASH1P8_SW_EN_THRU_V << PMU_FLASH1P8_SW_EN_THRU_S) -#define PMU_FLASH1P8_SW_EN_THRU_V 0x00000001U -#define PMU_FLASH1P8_SW_EN_THRU_S 2 -/** PMU_FLASH1P8_SW_EN_STANDBY : R/W; bitpos: [3]; default: 0; - * need_des - */ -#define PMU_FLASH1P8_SW_EN_STANDBY (BIT(3)) -#define PMU_FLASH1P8_SW_EN_STANDBY_M (PMU_FLASH1P8_SW_EN_STANDBY_V << PMU_FLASH1P8_SW_EN_STANDBY_S) -#define PMU_FLASH1P8_SW_EN_STANDBY_V 0x00000001U -#define PMU_FLASH1P8_SW_EN_STANDBY_S 3 -/** PMU_FLASH1P8_SW_EN_POWER_ADJUST : R/W; bitpos: [4]; default: 0; - * need_des - */ -#define PMU_FLASH1P8_SW_EN_POWER_ADJUST (BIT(4)) -#define PMU_FLASH1P8_SW_EN_POWER_ADJUST_M (PMU_FLASH1P8_SW_EN_POWER_ADJUST_V << PMU_FLASH1P8_SW_EN_POWER_ADJUST_S) -#define PMU_FLASH1P8_SW_EN_POWER_ADJUST_V 0x00000001U -#define PMU_FLASH1P8_SW_EN_POWER_ADJUST_S 4 -/** PMU_FLASH1P8_SW_EN_ENDET : R/W; bitpos: [5]; default: 0; - * need_des - */ -#define PMU_FLASH1P8_SW_EN_ENDET (BIT(5)) -#define PMU_FLASH1P8_SW_EN_ENDET_M (PMU_FLASH1P8_SW_EN_ENDET_V << PMU_FLASH1P8_SW_EN_ENDET_S) -#define PMU_FLASH1P8_SW_EN_ENDET_V 0x00000001U -#define PMU_FLASH1P8_SW_EN_ENDET_S 5 -/** PMU_FLASH1P8_BYPASS_LDO_RDY : R/W; bitpos: [22]; default: 0; - * need_des - */ -#define PMU_FLASH1P8_BYPASS_LDO_RDY (BIT(22)) -#define PMU_FLASH1P8_BYPASS_LDO_RDY_M (PMU_FLASH1P8_BYPASS_LDO_RDY_V << PMU_FLASH1P8_BYPASS_LDO_RDY_S) -#define PMU_FLASH1P8_BYPASS_LDO_RDY_V 0x00000001U -#define PMU_FLASH1P8_BYPASS_LDO_RDY_S 22 -/** PMU_FLASH1P8_XPD : R/W; bitpos: [23]; default: 0; - * need_des - */ -#define PMU_FLASH1P8_XPD (BIT(23)) -#define PMU_FLASH1P8_XPD_M (PMU_FLASH1P8_XPD_V << PMU_FLASH1P8_XPD_S) -#define PMU_FLASH1P8_XPD_V 0x00000001U -#define PMU_FLASH1P8_XPD_S 23 -/** PMU_FLASH1P8_THRU : R/W; bitpos: [24]; default: 1; - * need_des - */ -#define PMU_FLASH1P8_THRU (BIT(24)) -#define PMU_FLASH1P8_THRU_M (PMU_FLASH1P8_THRU_V << PMU_FLASH1P8_THRU_S) -#define PMU_FLASH1P8_THRU_V 0x00000001U -#define PMU_FLASH1P8_THRU_S 24 -/** PMU_FLASH1P8_STANDBY : R/W; bitpos: [25]; default: 0; - * need_des - */ -#define PMU_FLASH1P8_STANDBY (BIT(25)) -#define PMU_FLASH1P8_STANDBY_M (PMU_FLASH1P8_STANDBY_V << PMU_FLASH1P8_STANDBY_S) -#define PMU_FLASH1P8_STANDBY_V 0x00000001U -#define PMU_FLASH1P8_STANDBY_S 25 -/** PMU_FLASH1P8_POWER_ADJUST : R/W; bitpos: [30:26]; default: 0; - * need_des - */ -#define PMU_FLASH1P8_POWER_ADJUST 0x0000001FU -#define PMU_FLASH1P8_POWER_ADJUST_M (PMU_FLASH1P8_POWER_ADJUST_V << PMU_FLASH1P8_POWER_ADJUST_S) -#define PMU_FLASH1P8_POWER_ADJUST_V 0x0000001FU -#define PMU_FLASH1P8_POWER_ADJUST_S 26 -/** PMU_FLASH1P8_ENDET : R/W; bitpos: [31]; default: 0; - * need_des - */ -#define PMU_FLASH1P8_ENDET (BIT(31)) -#define PMU_FLASH1P8_ENDET_M (PMU_FLASH1P8_ENDET_V << PMU_FLASH1P8_ENDET_S) -#define PMU_FLASH1P8_ENDET_V 0x00000001U -#define PMU_FLASH1P8_ENDET_S 31 - -/** PMU_POWER_FLASH1P2_LDO_REG register - * need_des - */ -#define PMU_POWER_FLASH1P2_LDO_REG (DR_REG_PMU_BASE + 0x120) -/** PMU_FLASH1P2_LDO_RDY : RO; bitpos: [0]; default: 1; - * need_des - */ -#define PMU_FLASH1P2_LDO_RDY (BIT(0)) -#define PMU_FLASH1P2_LDO_RDY_M (PMU_FLASH1P2_LDO_RDY_V << PMU_FLASH1P2_LDO_RDY_S) -#define PMU_FLASH1P2_LDO_RDY_V 0x00000001U -#define PMU_FLASH1P2_LDO_RDY_S 0 -/** PMU_FLASH1P2_SW_EN_XPD : R/W; bitpos: [1]; default: 0; - * need_des - */ -#define PMU_FLASH1P2_SW_EN_XPD (BIT(1)) -#define PMU_FLASH1P2_SW_EN_XPD_M (PMU_FLASH1P2_SW_EN_XPD_V << PMU_FLASH1P2_SW_EN_XPD_S) -#define PMU_FLASH1P2_SW_EN_XPD_V 0x00000001U -#define PMU_FLASH1P2_SW_EN_XPD_S 1 -/** PMU_FLASH1P2_SW_EN_THRU : R/W; bitpos: [2]; default: 0; - * need_des - */ -#define PMU_FLASH1P2_SW_EN_THRU (BIT(2)) -#define PMU_FLASH1P2_SW_EN_THRU_M (PMU_FLASH1P2_SW_EN_THRU_V << PMU_FLASH1P2_SW_EN_THRU_S) -#define PMU_FLASH1P2_SW_EN_THRU_V 0x00000001U -#define PMU_FLASH1P2_SW_EN_THRU_S 2 -/** PMU_FLASH1P2_SW_EN_STANDBY : R/W; bitpos: [3]; default: 0; - * need_des - */ -#define PMU_FLASH1P2_SW_EN_STANDBY (BIT(3)) -#define PMU_FLASH1P2_SW_EN_STANDBY_M (PMU_FLASH1P2_SW_EN_STANDBY_V << PMU_FLASH1P2_SW_EN_STANDBY_S) -#define PMU_FLASH1P2_SW_EN_STANDBY_V 0x00000001U -#define PMU_FLASH1P2_SW_EN_STANDBY_S 3 -/** PMU_FLASH1P2_SW_EN_POWER_ADJUST : R/W; bitpos: [4]; default: 0; - * need_des - */ -#define PMU_FLASH1P2_SW_EN_POWER_ADJUST (BIT(4)) -#define PMU_FLASH1P2_SW_EN_POWER_ADJUST_M (PMU_FLASH1P2_SW_EN_POWER_ADJUST_V << PMU_FLASH1P2_SW_EN_POWER_ADJUST_S) -#define PMU_FLASH1P2_SW_EN_POWER_ADJUST_V 0x00000001U -#define PMU_FLASH1P2_SW_EN_POWER_ADJUST_S 4 -/** PMU_FLASH1P2_SW_EN_ENDET : R/W; bitpos: [5]; default: 0; - * need_des - */ -#define PMU_FLASH1P2_SW_EN_ENDET (BIT(5)) -#define PMU_FLASH1P2_SW_EN_ENDET_M (PMU_FLASH1P2_SW_EN_ENDET_V << PMU_FLASH1P2_SW_EN_ENDET_S) -#define PMU_FLASH1P2_SW_EN_ENDET_V 0x00000001U -#define PMU_FLASH1P2_SW_EN_ENDET_S 5 -/** PMU_FLASH1P2_BYPASS_LDO_RDY : R/W; bitpos: [22]; default: 0; - * need_des - */ -#define PMU_FLASH1P2_BYPASS_LDO_RDY (BIT(22)) -#define PMU_FLASH1P2_BYPASS_LDO_RDY_M (PMU_FLASH1P2_BYPASS_LDO_RDY_V << PMU_FLASH1P2_BYPASS_LDO_RDY_S) -#define PMU_FLASH1P2_BYPASS_LDO_RDY_V 0x00000001U -#define PMU_FLASH1P2_BYPASS_LDO_RDY_S 22 -/** PMU_FLASH1P2_XPD : R/W; bitpos: [23]; default: 0; - * need_des - */ -#define PMU_FLASH1P2_XPD (BIT(23)) -#define PMU_FLASH1P2_XPD_M (PMU_FLASH1P2_XPD_V << PMU_FLASH1P2_XPD_S) -#define PMU_FLASH1P2_XPD_V 0x00000001U -#define PMU_FLASH1P2_XPD_S 23 -/** PMU_FLASH1P2_THRU : R/W; bitpos: [24]; default: 1; - * need_des - */ -#define PMU_FLASH1P2_THRU (BIT(24)) -#define PMU_FLASH1P2_THRU_M (PMU_FLASH1P2_THRU_V << PMU_FLASH1P2_THRU_S) -#define PMU_FLASH1P2_THRU_V 0x00000001U -#define PMU_FLASH1P2_THRU_S 24 -/** PMU_FLASH1P2_STANDBY : R/W; bitpos: [25]; default: 0; - * need_des - */ -#define PMU_FLASH1P2_STANDBY (BIT(25)) -#define PMU_FLASH1P2_STANDBY_M (PMU_FLASH1P2_STANDBY_V << PMU_FLASH1P2_STANDBY_S) -#define PMU_FLASH1P2_STANDBY_V 0x00000001U -#define PMU_FLASH1P2_STANDBY_S 25 -/** PMU_FLASH1P2_POWER_ADJUST : R/W; bitpos: [30:26]; default: 0; - * need_des - */ -#define PMU_FLASH1P2_POWER_ADJUST 0x0000001FU -#define PMU_FLASH1P2_POWER_ADJUST_M (PMU_FLASH1P2_POWER_ADJUST_V << PMU_FLASH1P2_POWER_ADJUST_S) -#define PMU_FLASH1P2_POWER_ADJUST_V 0x0000001FU -#define PMU_FLASH1P2_POWER_ADJUST_S 26 -/** PMU_FLASH1P2_ENDET : R/W; bitpos: [31]; default: 0; - * need_des - */ -#define PMU_FLASH1P2_ENDET (BIT(31)) -#define PMU_FLASH1P2_ENDET_M (PMU_FLASH1P2_ENDET_V << PMU_FLASH1P2_ENDET_S) -#define PMU_FLASH1P2_ENDET_V 0x00000001U -#define PMU_FLASH1P2_ENDET_S 31 - -/** PMU_POWER_VDD_FLASH_REG register - * need_des - */ -#define PMU_POWER_VDD_FLASH_REG (DR_REG_PMU_BASE + 0x124) -/** PMU_FLASH_LDO_SW_EN_TIEL : R/W; bitpos: [22]; default: 0; - * need_des - */ -#define PMU_FLASH_LDO_SW_EN_TIEL (BIT(22)) -#define PMU_FLASH_LDO_SW_EN_TIEL_M (PMU_FLASH_LDO_SW_EN_TIEL_V << PMU_FLASH_LDO_SW_EN_TIEL_S) -#define PMU_FLASH_LDO_SW_EN_TIEL_V 0x00000001U -#define PMU_FLASH_LDO_SW_EN_TIEL_S 22 -/** PMU_FLASH_LDO_POWER_SEL : R/W; bitpos: [23]; default: 0; +/** PMU_POWER_VDD_SPI_CNTL_REG register * need_des */ -#define PMU_FLASH_LDO_POWER_SEL (BIT(23)) -#define PMU_FLASH_LDO_POWER_SEL_M (PMU_FLASH_LDO_POWER_SEL_V << PMU_FLASH_LDO_POWER_SEL_S) -#define PMU_FLASH_LDO_POWER_SEL_V 0x00000001U -#define PMU_FLASH_LDO_POWER_SEL_S 23 -/** PMU_FLASH_LDO_SW_EN_POWER_SEL : R/W; bitpos: [24]; default: 0; +#define PMU_POWER_VDD_SPI_CNTL_REG (DR_REG_PMU_BASE + 0x118) +/** PMU_VDD_SPI_PWR_WAIT : R/W; bitpos: [28:18]; default: 255; * need_des */ -#define PMU_FLASH_LDO_SW_EN_POWER_SEL (BIT(24)) -#define PMU_FLASH_LDO_SW_EN_POWER_SEL_M (PMU_FLASH_LDO_SW_EN_POWER_SEL_V << PMU_FLASH_LDO_SW_EN_POWER_SEL_S) -#define PMU_FLASH_LDO_SW_EN_POWER_SEL_V 0x00000001U -#define PMU_FLASH_LDO_SW_EN_POWER_SEL_S 24 -/** PMU_FLASH_LDO_WAIT_TARGET : R/W; bitpos: [28:25]; default: 15; +#define PMU_VDD_SPI_PWR_WAIT 0x000007FFU +#define PMU_VDD_SPI_PWR_WAIT_M (PMU_VDD_SPI_PWR_WAIT_V << PMU_VDD_SPI_PWR_WAIT_S) +#define PMU_VDD_SPI_PWR_WAIT_V 0x000007FFU +#define PMU_VDD_SPI_PWR_WAIT_S 18 +/** PMU_VDD_SPI_PWR_SW : R/W; bitpos: [30:29]; default: 3; * need_des */ -#define PMU_FLASH_LDO_WAIT_TARGET 0x0000000FU -#define PMU_FLASH_LDO_WAIT_TARGET_M (PMU_FLASH_LDO_WAIT_TARGET_V << PMU_FLASH_LDO_WAIT_TARGET_S) -#define PMU_FLASH_LDO_WAIT_TARGET_V 0x0000000FU -#define PMU_FLASH_LDO_WAIT_TARGET_S 25 -/** PMU_FLASH_LDO_TIEL_EN : R/W; bitpos: [29]; default: 0; +#define PMU_VDD_SPI_PWR_SW 0x00000003U +#define PMU_VDD_SPI_PWR_SW_M (PMU_VDD_SPI_PWR_SW_V << PMU_VDD_SPI_PWR_SW_S) +#define PMU_VDD_SPI_PWR_SW_V 0x00000003U +#define PMU_VDD_SPI_PWR_SW_S 29 +/** PMU_VDD_SPI_PWR_SEL_SW : R/W; bitpos: [31]; default: 0; * need_des */ -#define PMU_FLASH_LDO_TIEL_EN (BIT(29)) -#define PMU_FLASH_LDO_TIEL_EN_M (PMU_FLASH_LDO_TIEL_EN_V << PMU_FLASH_LDO_TIEL_EN_S) -#define PMU_FLASH_LDO_TIEL_EN_V 0x00000001U -#define PMU_FLASH_LDO_TIEL_EN_S 29 -/** PMU_FLASH_LDO_TIEL : R/W; bitpos: [30]; default: 0; - * need_des - */ -#define PMU_FLASH_LDO_TIEL (BIT(30)) -#define PMU_FLASH_LDO_TIEL_M (PMU_FLASH_LDO_TIEL_V << PMU_FLASH_LDO_TIEL_S) -#define PMU_FLASH_LDO_TIEL_V 0x00000001U -#define PMU_FLASH_LDO_TIEL_S 30 -/** PMU_FLASH_LDO_SW_UPDATE : WT; bitpos: [31]; default: 0; - * need_des - */ -#define PMU_FLASH_LDO_SW_UPDATE (BIT(31)) -#define PMU_FLASH_LDO_SW_UPDATE_M (PMU_FLASH_LDO_SW_UPDATE_V << PMU_FLASH_LDO_SW_UPDATE_S) -#define PMU_FLASH_LDO_SW_UPDATE_V 0x00000001U -#define PMU_FLASH_LDO_SW_UPDATE_S 31 - -/** PMU_POWER_IO_LDO_REG register - * need_des - */ -#define PMU_POWER_IO_LDO_REG (DR_REG_PMU_BASE + 0x128) -/** PMU_IO_LDO_RDY : RO; bitpos: [0]; default: 1; - * need_des - */ -#define PMU_IO_LDO_RDY (BIT(0)) -#define PMU_IO_LDO_RDY_M (PMU_IO_LDO_RDY_V << PMU_IO_LDO_RDY_S) -#define PMU_IO_LDO_RDY_V 0x00000001U -#define PMU_IO_LDO_RDY_S 0 -/** PMU_IO_SW_EN_XPD : R/W; bitpos: [1]; default: 0; - * need_des - */ -#define PMU_IO_SW_EN_XPD (BIT(1)) -#define PMU_IO_SW_EN_XPD_M (PMU_IO_SW_EN_XPD_V << PMU_IO_SW_EN_XPD_S) -#define PMU_IO_SW_EN_XPD_V 0x00000001U -#define PMU_IO_SW_EN_XPD_S 1 -/** PMU_IO_SW_EN_THRU : R/W; bitpos: [3]; default: 0; - * need_des - */ -#define PMU_IO_SW_EN_THRU (BIT(3)) -#define PMU_IO_SW_EN_THRU_M (PMU_IO_SW_EN_THRU_V << PMU_IO_SW_EN_THRU_S) -#define PMU_IO_SW_EN_THRU_V 0x00000001U -#define PMU_IO_SW_EN_THRU_S 3 -/** PMU_IO_SW_EN_STANDBY : R/W; bitpos: [4]; default: 0; - * need_des - */ -#define PMU_IO_SW_EN_STANDBY (BIT(4)) -#define PMU_IO_SW_EN_STANDBY_M (PMU_IO_SW_EN_STANDBY_V << PMU_IO_SW_EN_STANDBY_S) -#define PMU_IO_SW_EN_STANDBY_V 0x00000001U -#define PMU_IO_SW_EN_STANDBY_S 4 -/** PMU_IO_SW_EN_POWER_ADJUST : R/W; bitpos: [5]; default: 0; - * need_des - */ -#define PMU_IO_SW_EN_POWER_ADJUST (BIT(5)) -#define PMU_IO_SW_EN_POWER_ADJUST_M (PMU_IO_SW_EN_POWER_ADJUST_V << PMU_IO_SW_EN_POWER_ADJUST_S) -#define PMU_IO_SW_EN_POWER_ADJUST_V 0x00000001U -#define PMU_IO_SW_EN_POWER_ADJUST_S 5 -/** PMU_IO_SW_EN_ENDET : R/W; bitpos: [6]; default: 0; - * need_des - */ -#define PMU_IO_SW_EN_ENDET (BIT(6)) -#define PMU_IO_SW_EN_ENDET_M (PMU_IO_SW_EN_ENDET_V << PMU_IO_SW_EN_ENDET_S) -#define PMU_IO_SW_EN_ENDET_V 0x00000001U -#define PMU_IO_SW_EN_ENDET_S 6 -/** PMU_IO_BYPASS_LDO_RDY : R/W; bitpos: [22]; default: 0; - * need_des - */ -#define PMU_IO_BYPASS_LDO_RDY (BIT(22)) -#define PMU_IO_BYPASS_LDO_RDY_M (PMU_IO_BYPASS_LDO_RDY_V << PMU_IO_BYPASS_LDO_RDY_S) -#define PMU_IO_BYPASS_LDO_RDY_V 0x00000001U -#define PMU_IO_BYPASS_LDO_RDY_S 22 -/** PMU_IO_XPD : R/W; bitpos: [23]; default: 0; - * need_des - */ -#define PMU_IO_XPD (BIT(23)) -#define PMU_IO_XPD_M (PMU_IO_XPD_V << PMU_IO_XPD_S) -#define PMU_IO_XPD_V 0x00000001U -#define PMU_IO_XPD_S 23 -/** PMU_IO_THRU : R/W; bitpos: [24]; default: 1; - * need_des - */ -#define PMU_IO_THRU (BIT(24)) -#define PMU_IO_THRU_M (PMU_IO_THRU_V << PMU_IO_THRU_S) -#define PMU_IO_THRU_V 0x00000001U -#define PMU_IO_THRU_S 24 -/** PMU_IO_STANDBY : R/W; bitpos: [25]; default: 0; - * need_des - */ -#define PMU_IO_STANDBY (BIT(25)) -#define PMU_IO_STANDBY_M (PMU_IO_STANDBY_V << PMU_IO_STANDBY_S) -#define PMU_IO_STANDBY_V 0x00000001U -#define PMU_IO_STANDBY_S 25 -/** PMU_IO_POWER_ADJUST : R/W; bitpos: [30:26]; default: 0; - * need_des - */ -#define PMU_IO_POWER_ADJUST 0x0000001FU -#define PMU_IO_POWER_ADJUST_M (PMU_IO_POWER_ADJUST_V << PMU_IO_POWER_ADJUST_S) -#define PMU_IO_POWER_ADJUST_V 0x0000001FU -#define PMU_IO_POWER_ADJUST_S 26 -/** PMU_IO_ENDET : R/W; bitpos: [31]; default: 0; - * need_des - */ -#define PMU_IO_ENDET (BIT(31)) -#define PMU_IO_ENDET_M (PMU_IO_ENDET_V << PMU_IO_ENDET_S) -#define PMU_IO_ENDET_V 0x00000001U -#define PMU_IO_ENDET_S 31 - -/** PMU_POWER_VDD_IO_REG register - * need_des - */ -#define PMU_POWER_VDD_IO_REG (DR_REG_PMU_BASE + 0x12c) -/** PMU_IO_LDO_POWER_SEL : R/W; bitpos: [23]; default: 0; - * need_des - */ -#define PMU_IO_LDO_POWER_SEL (BIT(23)) -#define PMU_IO_LDO_POWER_SEL_M (PMU_IO_LDO_POWER_SEL_V << PMU_IO_LDO_POWER_SEL_S) -#define PMU_IO_LDO_POWER_SEL_V 0x00000001U -#define PMU_IO_LDO_POWER_SEL_S 23 -/** PMU_IO_LDO_SW_EN_POWER_SEL : R/W; bitpos: [24]; default: 0; - * need_des - */ -#define PMU_IO_LDO_SW_EN_POWER_SEL (BIT(24)) -#define PMU_IO_LDO_SW_EN_POWER_SEL_M (PMU_IO_LDO_SW_EN_POWER_SEL_V << PMU_IO_LDO_SW_EN_POWER_SEL_S) -#define PMU_IO_LDO_SW_EN_POWER_SEL_V 0x00000001U -#define PMU_IO_LDO_SW_EN_POWER_SEL_S 24 +#define PMU_VDD_SPI_PWR_SEL_SW (BIT(31)) +#define PMU_VDD_SPI_PWR_SEL_SW_M (PMU_VDD_SPI_PWR_SEL_SW_V << PMU_VDD_SPI_PWR_SEL_SW_S) +#define PMU_VDD_SPI_PWR_SEL_SW_V 0x00000001U +#define PMU_VDD_SPI_PWR_SEL_SW_S 31 /** PMU_POWER_CK_WAIT_CNTL_REG register * need_des */ -#define PMU_POWER_CK_WAIT_CNTL_REG (DR_REG_PMU_BASE + 0x130) +#define PMU_POWER_CK_WAIT_CNTL_REG (DR_REG_PMU_BASE + 0x11c) /** PMU_WAIT_XTL_STABLE : R/W; bitpos: [15:0]; default: 256; * need_des */ @@ -2494,7 +2313,7 @@ extern "C" { /** PMU_SLP_WAKEUP_CNTL0_REG register * need_des */ -#define PMU_SLP_WAKEUP_CNTL0_REG (DR_REG_PMU_BASE + 0x134) +#define PMU_SLP_WAKEUP_CNTL0_REG (DR_REG_PMU_BASE + 0x120) /** PMU_SLEEP_REQ : WT; bitpos: [31]; default: 0; * need_des */ @@ -2506,7 +2325,7 @@ extern "C" { /** PMU_SLP_WAKEUP_CNTL1_REG register * need_des */ -#define PMU_SLP_WAKEUP_CNTL1_REG (DR_REG_PMU_BASE + 0x138) +#define PMU_SLP_WAKEUP_CNTL1_REG (DR_REG_PMU_BASE + 0x124) /** PMU_SLEEP_REJECT_ENA : R/W; bitpos: [30:0]; default: 0; * need_des */ @@ -2525,7 +2344,7 @@ extern "C" { /** PMU_SLP_WAKEUP_CNTL2_REG register * need_des */ -#define PMU_SLP_WAKEUP_CNTL2_REG (DR_REG_PMU_BASE + 0x13c) +#define PMU_SLP_WAKEUP_CNTL2_REG (DR_REG_PMU_BASE + 0x128) /** PMU_WAKEUP_ENA : R/W; bitpos: [31:0]; default: 0; * need_des */ @@ -2537,7 +2356,7 @@ extern "C" { /** PMU_SLP_WAKEUP_CNTL3_REG register * need_des */ -#define PMU_SLP_WAKEUP_CNTL3_REG (DR_REG_PMU_BASE + 0x140) +#define PMU_SLP_WAKEUP_CNTL3_REG (DR_REG_PMU_BASE + 0x12c) /** PMU_LP_MIN_SLP_VAL : R/W; bitpos: [7:0]; default: 0; * need_des */ @@ -2563,7 +2382,7 @@ extern "C" { /** PMU_SLP_WAKEUP_CNTL4_REG register * need_des */ -#define PMU_SLP_WAKEUP_CNTL4_REG (DR_REG_PMU_BASE + 0x144) +#define PMU_SLP_WAKEUP_CNTL4_REG (DR_REG_PMU_BASE + 0x130) /** PMU_SLP_REJECT_CAUSE_CLR : WT; bitpos: [31]; default: 0; * need_des */ @@ -2575,7 +2394,7 @@ extern "C" { /** PMU_SLP_WAKEUP_CNTL5_REG register * need_des */ -#define PMU_SLP_WAKEUP_CNTL5_REG (DR_REG_PMU_BASE + 0x148) +#define PMU_SLP_WAKEUP_CNTL5_REG (DR_REG_PMU_BASE + 0x134) /** PMU_MODEM_WAIT_TARGET : R/W; bitpos: [19:0]; default: 128; * need_des */ @@ -2594,7 +2413,7 @@ extern "C" { /** PMU_SLP_WAKEUP_CNTL6_REG register * need_des */ -#define PMU_SLP_WAKEUP_CNTL6_REG (DR_REG_PMU_BASE + 0x14c) +#define PMU_SLP_WAKEUP_CNTL6_REG (DR_REG_PMU_BASE + 0x138) /** PMU_SOC_WAKEUP_WAIT : R/W; bitpos: [19:0]; default: 128; * need_des */ @@ -2613,14 +2432,7 @@ extern "C" { /** PMU_SLP_WAKEUP_CNTL7_REG register * need_des */ -#define PMU_SLP_WAKEUP_CNTL7_REG (DR_REG_PMU_BASE + 0x150) -/** PMU_ANA_WAIT_CLK_SEL : R/W; bitpos: [15]; default: 0; - * need_des - */ -#define PMU_ANA_WAIT_CLK_SEL (BIT(15)) -#define PMU_ANA_WAIT_CLK_SEL_M (PMU_ANA_WAIT_CLK_SEL_V << PMU_ANA_WAIT_CLK_SEL_S) -#define PMU_ANA_WAIT_CLK_SEL_V 0x00000001U -#define PMU_ANA_WAIT_CLK_SEL_S 15 +#define PMU_SLP_WAKEUP_CNTL7_REG (DR_REG_PMU_BASE + 0x13c) /** PMU_ANA_WAIT_TARGET : R/W; bitpos: [31:16]; default: 1; * need_des */ @@ -2632,7 +2444,7 @@ extern "C" { /** PMU_SLP_WAKEUP_STATUS0_REG register * need_des */ -#define PMU_SLP_WAKEUP_STATUS0_REG (DR_REG_PMU_BASE + 0x154) +#define PMU_SLP_WAKEUP_STATUS0_REG (DR_REG_PMU_BASE + 0x140) /** PMU_WAKEUP_CAUSE : RO; bitpos: [31:0]; default: 0; * need_des */ @@ -2644,7 +2456,7 @@ extern "C" { /** PMU_SLP_WAKEUP_STATUS1_REG register * need_des */ -#define PMU_SLP_WAKEUP_STATUS1_REG (DR_REG_PMU_BASE + 0x158) +#define PMU_SLP_WAKEUP_STATUS1_REG (DR_REG_PMU_BASE + 0x144) /** PMU_REJECT_CAUSE : RO; bitpos: [31:0]; default: 0; * need_des */ @@ -2656,7 +2468,7 @@ extern "C" { /** PMU_HP_CK_POWERON_REG register * need_des */ -#define PMU_HP_CK_POWERON_REG (DR_REG_PMU_BASE + 0x15c) +#define PMU_HP_CK_POWERON_REG (DR_REG_PMU_BASE + 0x148) /** PMU_I2C_POR_WAIT_TARGET : R/W; bitpos: [7:0]; default: 50; * need_des */ @@ -2668,7 +2480,7 @@ extern "C" { /** PMU_HP_CK_CNTL_REG register * need_des */ -#define PMU_HP_CK_CNTL_REG (DR_REG_PMU_BASE + 0x160) +#define PMU_HP_CK_CNTL_REG (DR_REG_PMU_BASE + 0x14c) /** PMU_MODIFY_ICG_CNTL_WAIT : R/W; bitpos: [7:0]; default: 10; * need_des */ @@ -2687,8 +2499,8 @@ extern "C" { /** PMU_POR_STATUS_REG register * need_des */ -#define PMU_POR_STATUS_REG (DR_REG_PMU_BASE + 0x164) -/** PMU_POR_DONE : RO; bitpos: [31]; default: 0; +#define PMU_POR_STATUS_REG (DR_REG_PMU_BASE + 0x150) +/** PMU_POR_DONE : RO; bitpos: [31]; default: 1; * need_des */ #define PMU_POR_DONE (BIT(31)) @@ -2699,14 +2511,7 @@ extern "C" { /** PMU_RF_PWC_REG register * need_des */ -#define PMU_RF_PWC_REG (DR_REG_PMU_BASE + 0x168) -/** PMU_XPD_FORCE_RFTX : R/W; bitpos: [26]; default: 0; - * need_des - */ -#define PMU_XPD_FORCE_RFTX (BIT(26)) -#define PMU_XPD_FORCE_RFTX_M (PMU_XPD_FORCE_RFTX_V << PMU_XPD_FORCE_RFTX_S) -#define PMU_XPD_FORCE_RFTX_V 0x00000001U -#define PMU_XPD_FORCE_RFTX_S 26 +#define PMU_RF_PWC_REG (DR_REG_PMU_BASE + 0x154) /** PMU_XPD_PERIF_I2C : R/W; bitpos: [27]; default: 1; * need_des */ @@ -2746,7 +2551,7 @@ extern "C" { /** PMU_VDDBAT_CFG_REG register * need_des */ -#define PMU_VDDBAT_CFG_REG (DR_REG_PMU_BASE + 0x16c) +#define PMU_VDDBAT_CFG_REG (DR_REG_PMU_BASE + 0x158) /** PMU_VDDBAT_MODE : RO; bitpos: [1:0]; default: 0; * need_des */ @@ -2765,7 +2570,7 @@ extern "C" { /** PMU_BACKUP_CFG_REG register * need_des */ -#define PMU_BACKUP_CFG_REG (DR_REG_PMU_BASE + 0x170) +#define PMU_BACKUP_CFG_REG (DR_REG_PMU_BASE + 0x15c) /** PMU_BACKUP_SYS_CLK_NO_DIV : R/W; bitpos: [31]; default: 1; * need_des */ @@ -2777,7 +2582,7 @@ extern "C" { /** PMU_INT_RAW_REG register * need_des */ -#define PMU_INT_RAW_REG (DR_REG_PMU_BASE + 0x174) +#define PMU_INT_RAW_REG (DR_REG_PMU_BASE + 0x160) /** PMU_LP_CPU_EXC_INT_RAW : R/WTC/SS; bitpos: [27]; default: 0; * need_des */ @@ -2817,7 +2622,7 @@ extern "C" { /** PMU_HP_INT_ST_REG register * need_des */ -#define PMU_HP_INT_ST_REG (DR_REG_PMU_BASE + 0x178) +#define PMU_HP_INT_ST_REG (DR_REG_PMU_BASE + 0x164) /** PMU_LP_CPU_EXC_INT_ST : RO; bitpos: [27]; default: 0; * need_des */ @@ -2857,7 +2662,7 @@ extern "C" { /** PMU_HP_INT_ENA_REG register * need_des */ -#define PMU_HP_INT_ENA_REG (DR_REG_PMU_BASE + 0x17c) +#define PMU_HP_INT_ENA_REG (DR_REG_PMU_BASE + 0x168) /** PMU_LP_CPU_EXC_INT_ENA : R/W; bitpos: [27]; default: 0; * need_des */ @@ -2897,7 +2702,7 @@ extern "C" { /** PMU_HP_INT_CLR_REG register * need_des */ -#define PMU_HP_INT_CLR_REG (DR_REG_PMU_BASE + 0x180) +#define PMU_HP_INT_CLR_REG (DR_REG_PMU_BASE + 0x16c) /** PMU_LP_CPU_EXC_INT_CLR : WT; bitpos: [27]; default: 0; * need_des */ @@ -2937,7 +2742,7 @@ extern "C" { /** PMU_LP_INT_RAW_REG register * need_des */ -#define PMU_LP_INT_RAW_REG (DR_REG_PMU_BASE + 0x184) +#define PMU_LP_INT_RAW_REG (DR_REG_PMU_BASE + 0x170) /** PMU_LP_CPU_WAKEUP_INT_RAW : R/WTC/SS; bitpos: [20]; default: 0; * need_des */ @@ -3026,7 +2831,7 @@ extern "C" { /** PMU_LP_INT_ST_REG register * need_des */ -#define PMU_LP_INT_ST_REG (DR_REG_PMU_BASE + 0x188) +#define PMU_LP_INT_ST_REG (DR_REG_PMU_BASE + 0x174) /** PMU_LP_CPU_WAKEUP_INT_ST : RO; bitpos: [20]; default: 0; * need_des */ @@ -3115,7 +2920,7 @@ extern "C" { /** PMU_LP_INT_ENA_REG register * need_des */ -#define PMU_LP_INT_ENA_REG (DR_REG_PMU_BASE + 0x18c) +#define PMU_LP_INT_ENA_REG (DR_REG_PMU_BASE + 0x178) /** PMU_LP_CPU_WAKEUP_INT_ENA : R/W; bitpos: [20]; default: 0; * need_des */ @@ -3204,7 +3009,7 @@ extern "C" { /** PMU_LP_INT_CLR_REG register * need_des */ -#define PMU_LP_INT_CLR_REG (DR_REG_PMU_BASE + 0x190) +#define PMU_LP_INT_CLR_REG (DR_REG_PMU_BASE + 0x17c) /** PMU_LP_CPU_WAKEUP_INT_CLR : WT; bitpos: [20]; default: 0; * need_des */ @@ -3293,7 +3098,7 @@ extern "C" { /** PMU_LP_CPU_PWR0_REG register * need_des */ -#define PMU_LP_CPU_PWR0_REG (DR_REG_PMU_BASE + 0x194) +#define PMU_LP_CPU_PWR0_REG (DR_REG_PMU_BASE + 0x180) /** PMU_LP_CPU_WAITI_RDY : RO; bitpos: [0]; default: 0; * need_des */ @@ -3361,7 +3166,7 @@ extern "C" { /** PMU_LP_CPU_PWR1_REG register * need_des */ -#define PMU_LP_CPU_PWR1_REG (DR_REG_PMU_BASE + 0x198) +#define PMU_LP_CPU_PWR1_REG (DR_REG_PMU_BASE + 0x184) /** PMU_LP_CPU_WAKEUP_EN : R/W; bitpos: [15:0]; default: 0; * need_des */ @@ -3380,7 +3185,7 @@ extern "C" { /** PMU_HP_LP_CPU_COMM_REG register * need_des */ -#define PMU_HP_LP_CPU_COMM_REG (DR_REG_PMU_BASE + 0x19c) +#define PMU_HP_LP_CPU_COMM_REG (DR_REG_PMU_BASE + 0x188) /** PMU_LP_TRIGGER_HP : WT; bitpos: [30]; default: 0; * need_des */ @@ -3399,7 +3204,7 @@ extern "C" { /** PMU_HP_REGULATOR_CFG_REG register * need_des */ -#define PMU_HP_REGULATOR_CFG_REG (DR_REG_PMU_BASE + 0x1a0) +#define PMU_HP_REGULATOR_CFG_REG (DR_REG_PMU_BASE + 0x18c) /** PMU_DIG_REGULATOR_EN_CAL : R/W; bitpos: [31]; default: 0; * need_des */ @@ -3411,8 +3216,8 @@ extern "C" { /** PMU_MAIN_STATE_REG register * need_des */ -#define PMU_MAIN_STATE_REG (DR_REG_PMU_BASE + 0x1a4) -/** PMU_MAIN_LAST_ST_STATE : RO; bitpos: [17:11]; default: 256; +#define PMU_MAIN_STATE_REG (DR_REG_PMU_BASE + 0x190) +/** PMU_MAIN_LAST_ST_STATE : RO; bitpos: [17:11]; default: 1; * need_des */ #define PMU_MAIN_LAST_ST_STATE 0x0000007FU @@ -3426,7 +3231,7 @@ extern "C" { #define PMU_MAIN_TAR_ST_STATE_M (PMU_MAIN_TAR_ST_STATE_V << PMU_MAIN_TAR_ST_STATE_S) #define PMU_MAIN_TAR_ST_STATE_V 0x0000007FU #define PMU_MAIN_TAR_ST_STATE_S 18 -/** PMU_MAIN_CUR_ST_STATE : RO; bitpos: [31:25]; default: 1; +/** PMU_MAIN_CUR_ST_STATE : RO; bitpos: [31:25]; default: 4; * need_des */ #define PMU_MAIN_CUR_ST_STATE 0x0000007FU @@ -3437,7 +3242,7 @@ extern "C" { /** PMU_PWR_STATE_REG register * need_des */ -#define PMU_PWR_STATE_REG (DR_REG_PMU_BASE + 0x1a8) +#define PMU_PWR_STATE_REG (DR_REG_PMU_BASE + 0x194) /** PMU_BACKUP_ST_STATE : RO; bitpos: [17:13]; default: 1; * need_des */ @@ -3463,15 +3268,15 @@ extern "C" { /** PMU_CLK_STATE0_REG register * need_des */ -#define PMU_CLK_STATE0_REG (DR_REG_PMU_BASE + 0x1ac) -/** PMU_STABLE_XPD_BBPLL_STATE : RO; bitpos: [0]; default: 0; +#define PMU_CLK_STATE0_REG (DR_REG_PMU_BASE + 0x198) +/** PMU_STABLE_XPD_BBPLL_STATE : RO; bitpos: [0]; default: 1; * need_des */ #define PMU_STABLE_XPD_BBPLL_STATE (BIT(0)) #define PMU_STABLE_XPD_BBPLL_STATE_M (PMU_STABLE_XPD_BBPLL_STATE_V << PMU_STABLE_XPD_BBPLL_STATE_S) #define PMU_STABLE_XPD_BBPLL_STATE_V 0x00000001U #define PMU_STABLE_XPD_BBPLL_STATE_S 0 -/** PMU_STABLE_XPD_XTAL_STATE : RO; bitpos: [1]; default: 0; +/** PMU_STABLE_XPD_XTAL_STATE : RO; bitpos: [1]; default: 1; * need_des */ #define PMU_STABLE_XPD_XTAL_STATE (BIT(1)) @@ -3499,7 +3304,7 @@ extern "C" { #define PMU_SYS_CLK_NO_DIV_STATE_M (PMU_SYS_CLK_NO_DIV_STATE_V << PMU_SYS_CLK_NO_DIV_STATE_S) #define PMU_SYS_CLK_NO_DIV_STATE_V 0x00000001U #define PMU_SYS_CLK_NO_DIV_STATE_S 18 -/** PMU_ICG_SYS_CLK_EN_STATE : RO; bitpos: [19]; default: 1; +/** PMU_ICG_SYS_CLK_EN_STATE : RO; bitpos: [19]; default: 0; * need_des */ #define PMU_ICG_SYS_CLK_EN_STATE (BIT(19)) @@ -3576,7 +3381,7 @@ extern "C" { #define PMU_ANA_XPD_BBPLL_STATE_M (PMU_ANA_XPD_BBPLL_STATE_V << PMU_ANA_XPD_BBPLL_STATE_S) #define PMU_ANA_XPD_BBPLL_STATE_V 0x00000001U #define PMU_ANA_XPD_BBPLL_STATE_S 30 -/** PMU_ANA_XPD_XTAL_STATE : RO; bitpos: [31]; default: 1; +/** PMU_ANA_XPD_XTAL_STATE : RO; bitpos: [31]; default: 0; * need_des */ #define PMU_ANA_XPD_XTAL_STATE (BIT(31)) @@ -3587,7 +3392,7 @@ extern "C" { /** PMU_CLK_STATE1_REG register * need_des */ -#define PMU_CLK_STATE1_REG (DR_REG_PMU_BASE + 0x1b0) +#define PMU_CLK_STATE1_REG (DR_REG_PMU_BASE + 0x19c) /** PMU_ICG_FUNC_EN_STATE : RO; bitpos: [31:0]; default: 4294967295; * need_des */ @@ -3599,7 +3404,7 @@ extern "C" { /** PMU_CLK_STATE2_REG register * need_des */ -#define PMU_CLK_STATE2_REG (DR_REG_PMU_BASE + 0x1b4) +#define PMU_CLK_STATE2_REG (DR_REG_PMU_BASE + 0x1a0) /** PMU_ICG_APB_EN_STATE : RO; bitpos: [31:0]; default: 4294967295; * need_des */ @@ -3608,112 +3413,23 @@ extern "C" { #define PMU_ICG_APB_EN_STATE_V 0xFFFFFFFFU #define PMU_ICG_APB_EN_STATE_S 0 -/** PMU_DCM_CTRL_REG register - * need_des - */ -#define PMU_DCM_CTRL_REG (DR_REG_PMU_BASE + 0x1b8) -/** PMU_DSFMOS_USE_POR : R/W; bitpos: [0]; default: 1; - * need_des - */ -#define PMU_DSFMOS_USE_POR (BIT(0)) -#define PMU_DSFMOS_USE_POR_M (PMU_DSFMOS_USE_POR_V << PMU_DSFMOS_USE_POR_S) -#define PMU_DSFMOS_USE_POR_V 0x00000001U -#define PMU_DSFMOS_USE_POR_S 0 -/** PMU_DCDC_DCM_UPDATE : WT; bitpos: [22]; default: 0; - * need_des - */ -#define PMU_DCDC_DCM_UPDATE (BIT(22)) -#define PMU_DCDC_DCM_UPDATE_M (PMU_DCDC_DCM_UPDATE_V << PMU_DCDC_DCM_UPDATE_S) -#define PMU_DCDC_DCM_UPDATE_V 0x00000001U -#define PMU_DCDC_DCM_UPDATE_S 22 -/** PMU_DCDC_PCUR_LIMIT : R/W; bitpos: [25:23]; default: 1; - * need_des - */ -#define PMU_DCDC_PCUR_LIMIT 0x00000007U -#define PMU_DCDC_PCUR_LIMIT_M (PMU_DCDC_PCUR_LIMIT_V << PMU_DCDC_PCUR_LIMIT_S) -#define PMU_DCDC_PCUR_LIMIT_V 0x00000007U -#define PMU_DCDC_PCUR_LIMIT_S 23 -/** PMU_DCDC_BIAS_CAL_DONE : RO; bitpos: [26]; default: 1; - * need_des - */ -#define PMU_DCDC_BIAS_CAL_DONE (BIT(26)) -#define PMU_DCDC_BIAS_CAL_DONE_M (PMU_DCDC_BIAS_CAL_DONE_V << PMU_DCDC_BIAS_CAL_DONE_S) -#define PMU_DCDC_BIAS_CAL_DONE_V 0x00000001U -#define PMU_DCDC_BIAS_CAL_DONE_S 26 -/** PMU_DCDC_CCM_SW_EN : R/W; bitpos: [27]; default: 0; - * need_des - */ -#define PMU_DCDC_CCM_SW_EN (BIT(27)) -#define PMU_DCDC_CCM_SW_EN_M (PMU_DCDC_CCM_SW_EN_V << PMU_DCDC_CCM_SW_EN_S) -#define PMU_DCDC_CCM_SW_EN_V 0x00000001U -#define PMU_DCDC_CCM_SW_EN_S 27 -/** PMU_DCDC_VCM_ENB : R/W; bitpos: [28]; default: 0; - * need_des - */ -#define PMU_DCDC_VCM_ENB (BIT(28)) -#define PMU_DCDC_VCM_ENB_M (PMU_DCDC_VCM_ENB_V << PMU_DCDC_VCM_ENB_S) -#define PMU_DCDC_VCM_ENB_V 0x00000001U -#define PMU_DCDC_VCM_ENB_S 28 -/** PMU_DCDC_CCM_RDY : RO; bitpos: [29]; default: 0; - * need_des - */ -#define PMU_DCDC_CCM_RDY (BIT(29)) -#define PMU_DCDC_CCM_RDY_M (PMU_DCDC_CCM_RDY_V << PMU_DCDC_CCM_RDY_S) -#define PMU_DCDC_CCM_RDY_V 0x00000001U -#define PMU_DCDC_CCM_RDY_S 29 -/** PMU_DCDC_VCM_RDY : RO; bitpos: [30]; default: 1; - * need_des - */ -#define PMU_DCDC_VCM_RDY (BIT(30)) -#define PMU_DCDC_VCM_RDY_M (PMU_DCDC_VCM_RDY_V << PMU_DCDC_VCM_RDY_S) -#define PMU_DCDC_VCM_RDY_V 0x00000001U -#define PMU_DCDC_VCM_RDY_S 30 -/** PMU_DCDC_RDY_CLR : R/W; bitpos: [31]; default: 0; - * need_des - */ -#define PMU_DCDC_RDY_CLR (BIT(31)) -#define PMU_DCDC_RDY_CLR_M (PMU_DCDC_RDY_CLR_V << PMU_DCDC_RDY_CLR_S) -#define PMU_DCDC_RDY_CLR_V 0x00000001U -#define PMU_DCDC_RDY_CLR_S 31 - -/** PMU_TOUCH_PWR_CTRL_REG register - * need_des - */ -#define PMU_TOUCH_PWR_CTRL_REG (DR_REG_PMU_BASE + 0x1bc) -/** PMU_TOUCH_SLEEP_CYCLES : R/W; bitpos: [15:0]; default: 0; - * need_des - */ -#define PMU_TOUCH_SLEEP_CYCLES 0x0000FFFFU -#define PMU_TOUCH_SLEEP_CYCLES_M (PMU_TOUCH_SLEEP_CYCLES_V << PMU_TOUCH_SLEEP_CYCLES_S) -#define PMU_TOUCH_SLEEP_CYCLES_V 0x0000FFFFU -#define PMU_TOUCH_SLEEP_CYCLES_S 0 -/** PMU_TOUCH_WAIT_CYCLES : R/W; bitpos: [29:21]; default: 0; - * need_des - */ -#define PMU_TOUCH_WAIT_CYCLES 0x000001FFU -#define PMU_TOUCH_WAIT_CYCLES_M (PMU_TOUCH_WAIT_CYCLES_V << PMU_TOUCH_WAIT_CYCLES_S) -#define PMU_TOUCH_WAIT_CYCLES_V 0x000001FFU -#define PMU_TOUCH_WAIT_CYCLES_S 21 -/** PMU_TOUCH_SLEEP_TIMER_EN : R/W; bitpos: [30]; default: 0; +/** PMU_VDD_SPI_STATUS_REG register * need_des */ -#define PMU_TOUCH_SLEEP_TIMER_EN (BIT(30)) -#define PMU_TOUCH_SLEEP_TIMER_EN_M (PMU_TOUCH_SLEEP_TIMER_EN_V << PMU_TOUCH_SLEEP_TIMER_EN_S) -#define PMU_TOUCH_SLEEP_TIMER_EN_V 0x00000001U -#define PMU_TOUCH_SLEEP_TIMER_EN_S 30 -/** PMU_TOUCH_FORCE_DONE : R/W; bitpos: [31]; default: 0; +#define PMU_VDD_SPI_STATUS_REG (DR_REG_PMU_BASE + 0x1a4) +/** PMU_STABLE_VDD_SPI_PWR_DRV : RO; bitpos: [31]; default: 0; * need_des */ -#define PMU_TOUCH_FORCE_DONE (BIT(31)) -#define PMU_TOUCH_FORCE_DONE_M (PMU_TOUCH_FORCE_DONE_V << PMU_TOUCH_FORCE_DONE_S) -#define PMU_TOUCH_FORCE_DONE_V 0x00000001U -#define PMU_TOUCH_FORCE_DONE_S 31 +#define PMU_STABLE_VDD_SPI_PWR_DRV (BIT(31)) +#define PMU_STABLE_VDD_SPI_PWR_DRV_M (PMU_STABLE_VDD_SPI_PWR_DRV_V << PMU_STABLE_VDD_SPI_PWR_DRV_S) +#define PMU_STABLE_VDD_SPI_PWR_DRV_V 0x00000001U +#define PMU_STABLE_VDD_SPI_PWR_DRV_S 31 /** PMU_DATE_REG register * need_des */ #define PMU_DATE_REG (DR_REG_PMU_BASE + 0x3fc) -/** PMU_PMU_DATE : R/W; bitpos: [30:0]; default: 37814400; +/** PMU_PMU_DATE : R/W; bitpos: [30:0]; default: 35688960; * need_des */ #define PMU_PMU_DATE 0x7FFFFFFFU diff --git a/components/soc/esp32h21/register/soc/pmu_struct.h b/components/soc/esp32h21/register/soc/pmu_struct.h index 92561a1d4f4..178613d23b7 100644 --- a/components/soc/esp32h21/register/soc/pmu_struct.h +++ b/components/soc/esp32h21/register/soc/pmu_struct.h @@ -6,2946 +6,765 @@ #pragma once #include +#include "soc/pmu_reg.h" #ifdef __cplusplus extern "C" { #endif -/** Group: configure_register */ -/** Type of hp_active_dig_power register - * need_des - */ -typedef union { - struct { - uint32_t reserved_0:18; - /** hp_active_vdd_flash_mode : R/W; bitpos: [21:18]; default: 0; - * need_des - */ - uint32_t hp_active_vdd_flash_mode:4; - /** hp_active_hp_mem_dslp : R/W; bitpos: [22]; default: 0; - * need_des - */ - uint32_t hp_active_hp_mem_dslp:1; - /** hp_active_pd_hp_mem_pd_en : R/W; bitpos: [26:23]; default: 0; - * need_des - */ - uint32_t hp_active_pd_hp_mem_pd_en:4; - /** hp_active_pd_hp_wifi_pd_en : R/W; bitpos: [27]; default: 0; - * need_des - */ - uint32_t hp_active_pd_hp_wifi_pd_en:1; - /** hp_active_pd_hp_peri_pd_en : R/W; bitpos: [28]; default: 0; - * need_des - */ - uint32_t hp_active_pd_hp_peri_pd_en:1; - /** hp_active_pd_hp_cpu_pd_en : R/W; bitpos: [29]; default: 0; - * need_des - */ - uint32_t hp_active_pd_hp_cpu_pd_en:1; - /** hp_active_pd_hp_aon_pd_en : R/W; bitpos: [30]; default: 0; - * need_des - */ - uint32_t hp_active_pd_hp_aon_pd_en:1; - /** hp_active_pd_top_pd_en : R/W; bitpos: [31]; default: 0; - * need_des - */ - uint32_t hp_active_pd_top_pd_en:1; - }; - uint32_t val; -} pmu_hp_active_dig_power_reg_t; - -/** Type of hp_active_icg_hp_func register - * need_des - */ -typedef union { - struct { - /** hp_active_dig_icg_func_en : R/W; bitpos: [31:0]; default: 4294967295; - * need_des - */ - uint32_t hp_active_dig_icg_func_en:32; - }; - uint32_t val; -} pmu_hp_active_icg_hp_func_reg_t; - -/** Type of hp_active_icg_hp_apb register - * need_des - */ -typedef union { - struct { - /** hp_active_dig_icg_apb_en : R/W; bitpos: [31:0]; default: 4294967295; - * need_des - */ - uint32_t hp_active_dig_icg_apb_en:32; - }; - uint32_t val; -} pmu_hp_active_icg_hp_apb_reg_t; - -/** Type of hp_active_icg_modem register - * need_des - */ -typedef union { - struct { - uint32_t reserved_0:30; - /** hp_active_dig_icg_modem_code : R/W; bitpos: [31:30]; default: 0; - * need_des - */ - uint32_t hp_active_dig_icg_modem_code:2; - }; - uint32_t val; -} pmu_hp_active_icg_modem_reg_t; - -/** Type of hp_active_hp_sys_cntl register - * need_des - */ -typedef union { - struct { - uint32_t reserved_0:24; - /** hp_active_uart_wakeup_en : R/W; bitpos: [24]; default: 0; - * need_des - */ - uint32_t hp_active_uart_wakeup_en:1; - /** hp_active_lp_pad_hold_all : R/W; bitpos: [25]; default: 0; - * need_des - */ - uint32_t hp_active_lp_pad_hold_all:1; - /** hp_active_hp_pad_hold_all : R/W; bitpos: [26]; default: 0; - * need_des - */ - uint32_t hp_active_hp_pad_hold_all:1; - /** hp_active_dig_pad_slp_sel : R/W; bitpos: [27]; default: 0; - * need_des - */ - uint32_t hp_active_dig_pad_slp_sel:1; - /** hp_active_dig_pause_wdt : R/W; bitpos: [28]; default: 0; - * need_des - */ - uint32_t hp_active_dig_pause_wdt:1; - /** hp_active_dig_cpu_stall : R/W; bitpos: [29]; default: 0; - * need_des - */ - uint32_t hp_active_dig_cpu_stall:1; - uint32_t reserved_30:2; - }; - uint32_t val; -} pmu_hp_active_hp_sys_cntl_reg_t; - -/** Type of hp_active_hp_ck_power register - * need_des - */ -typedef union { - struct { - uint32_t reserved_0:26; - /** hp_active_i2c_iso_en : R/W; bitpos: [26]; default: 0; - * need_des - */ - uint32_t hp_active_i2c_iso_en:1; - /** hp_active_i2c_retention : R/W; bitpos: [27]; default: 0; - * need_des - */ - uint32_t hp_active_i2c_retention:1; - /** hp_active_xpd_bb_i2c : R/W; bitpos: [28]; default: 0; - * need_des - */ - uint32_t hp_active_xpd_bb_i2c:1; - /** hp_active_xpd_bbpll_i2c : R/W; bitpos: [29]; default: 0; - * need_des - */ - uint32_t hp_active_xpd_bbpll_i2c:1; - /** hp_active_xpd_bbpll : R/W; bitpos: [30]; default: 0; - * need_des - */ - uint32_t hp_active_xpd_bbpll:1; - uint32_t reserved_31:1; - }; - uint32_t val; -} pmu_hp_active_hp_ck_power_reg_t; - -/** Type of hp_active_bias register - * need_des - */ -typedef union { - struct { - uint32_t reserved_0:9; - /** hp_active_dcdc_ccm_enb : R/W; bitpos: [9]; default: 1; - * need_des - */ - uint32_t hp_active_dcdc_ccm_enb:1; - /** hp_active_dcdc_clear_rdy : R/W; bitpos: [10]; default: 0; - * need_des - */ - uint32_t hp_active_dcdc_clear_rdy:1; - /** hp_active_dig_pmu_dpcur_bias : R/W; bitpos: [12:11]; default: 3; - * need_des - */ - uint32_t hp_active_dig_pmu_dpcur_bias:2; - /** hp_active_dig_pmu_dsfmos : R/W; bitpos: [16:13]; default: 6; - * need_des - */ - uint32_t hp_active_dig_pmu_dsfmos:4; - /** hp_active_dcm_vset : R/W; bitpos: [21:17]; default: 23; - * need_des - */ - uint32_t hp_active_dcm_vset:5; - /** hp_active_dcm_mode : R/W; bitpos: [23:22]; default: 0; - * need_des - */ - uint32_t hp_active_dcm_mode:2; - /** hp_active_xpd_trx : R/W; bitpos: [24]; default: 1; - * need_des - */ - uint32_t hp_active_xpd_trx:1; - /** hp_active_xpd_bias : R/W; bitpos: [25]; default: 0; - * need_des - */ - uint32_t hp_active_xpd_bias:1; - uint32_t reserved_26:3; - /** hp_active_discnnt_dig_rtc : R/W; bitpos: [29]; default: 0; - * need_des - */ - uint32_t hp_active_discnnt_dig_rtc:1; - /** hp_active_pd_cur : R/W; bitpos: [30]; default: 0; - * need_des - */ - uint32_t hp_active_pd_cur:1; - /** hp_active_bias_sleep : R/W; bitpos: [31]; default: 0; - * need_des - */ - uint32_t hp_active_bias_sleep:1; - }; - uint32_t val; -} pmu_hp_active_bias_reg_t; - -/** Type of hp_active_backup register - * need_des - */ -typedef union { - struct { - uint32_t reserved_0:4; - /** hp_sleep2active_backup_modem_clk_code : R/W; bitpos: [5:4]; default: 0; - * need_des - */ - uint32_t hp_sleep2active_backup_modem_clk_code:2; - /** hp_modem2active_backup_modem_clk_code : R/W; bitpos: [7:6]; default: 0; - * need_des - */ - uint32_t hp_modem2active_backup_modem_clk_code:2; - uint32_t reserved_8:6; - /** hp_sleep2active_backup_clk_sel : R/W; bitpos: [15:14]; default: 0; - * need_des - */ - uint32_t hp_sleep2active_backup_clk_sel:2; - /** hp_modem2active_backup_clk_sel : R/W; bitpos: [17:16]; default: 0; - * need_des - */ - uint32_t hp_modem2active_backup_clk_sel:2; - /** hp_sleep2active_backup_mode : R/W; bitpos: [22:18]; default: 0; - * need_des - */ - uint32_t hp_sleep2active_backup_mode:5; - /** hp_modem2active_backup_mode : R/W; bitpos: [27:23]; default: 0; - * need_des - */ - uint32_t hp_modem2active_backup_mode:5; - uint32_t reserved_28:1; - /** hp_sleep2active_backup_en : R/W; bitpos: [29]; default: 0; - * need_des - */ - uint32_t hp_sleep2active_backup_en:1; - /** hp_modem2active_backup_en : R/W; bitpos: [30]; default: 0; - * need_des - */ - uint32_t hp_modem2active_backup_en:1; - uint32_t reserved_31:1; - }; - uint32_t val; -} pmu_hp_active_backup_reg_t; - -/** Type of hp_active_backup_clk register - * need_des - */ -typedef union { - struct { - /** hp_active_backup_icg_func_en : R/W; bitpos: [31:0]; default: 0; - * need_des - */ - uint32_t hp_active_backup_icg_func_en:32; - }; - uint32_t val; -} pmu_hp_active_backup_clk_reg_t; - -/** Type of hp_active_sysclk register - * need_des - */ -typedef union { - struct { - uint32_t reserved_0:26; - /** hp_active_dig_sys_clk_no_div : R/W; bitpos: [26]; default: 0; - * need_des - */ - uint32_t hp_active_dig_sys_clk_no_div:1; - /** hp_active_icg_sys_clock_en : R/W; bitpos: [27]; default: 0; - * need_des - */ - uint32_t hp_active_icg_sys_clock_en:1; - /** hp_active_sys_clk_slp_sel : R/W; bitpos: [28]; default: 0; - * need_des - */ - uint32_t hp_active_sys_clk_slp_sel:1; - /** hp_active_icg_slp_sel : R/W; bitpos: [29]; default: 0; - * need_des - */ - uint32_t hp_active_icg_slp_sel:1; - /** hp_active_dig_sys_clk_sel : R/W; bitpos: [31:30]; default: 0; - * need_des - */ - uint32_t hp_active_dig_sys_clk_sel:2; - }; - uint32_t val; -} pmu_hp_active_sysclk_reg_t; - -/** Type of hp_active_hp_regulator0 register - * need_des - */ -typedef union { - struct { - /** hp_active_hp_power_det_bypass : R/W; bitpos: [0]; default: 0; - * need_des - */ - uint32_t hp_active_hp_power_det_bypass:1; - uint32_t reserved_1:3; - /** lp_dbias_vol : RO; bitpos: [8:4]; default: 24; - * need_des - */ - uint32_t lp_dbias_vol:5; - /** hp_dbias_vol : RO; bitpos: [13:9]; default: 24; - * need_des - */ - uint32_t hp_dbias_vol:5; - /** dig_regulator0_dbias_sel : R/W; bitpos: [14]; default: 1; - * need_des - */ - uint32_t dig_regulator0_dbias_sel:1; - /** dig_dbias_init : WT; bitpos: [15]; default: 0; - * need_des - */ - uint32_t dig_dbias_init:1; - /** hp_active_hp_regulator_slp_mem_xpd : R/W; bitpos: [16]; default: 1; - * need_des - */ - uint32_t hp_active_hp_regulator_slp_mem_xpd:1; - /** hp_active_hp_regulator_slp_logic_xpd : R/W; bitpos: [17]; default: 1; - * need_des - */ - uint32_t hp_active_hp_regulator_slp_logic_xpd:1; - /** hp_active_hp_regulator_xpd : R/W; bitpos: [18]; default: 1; - * need_des - */ - uint32_t hp_active_hp_regulator_xpd:1; - /** hp_active_hp_regulator_slp_mem_dbias : R/W; bitpos: [22:19]; default: 8; - * need_des - */ - uint32_t hp_active_hp_regulator_slp_mem_dbias:4; - /** hp_active_hp_regulator_slp_logic_dbias : R/W; bitpos: [26:23]; default: 8; - * need_des - */ - uint32_t hp_active_hp_regulator_slp_logic_dbias:4; - /** hp_active_hp_regulator_dbias : R/W; bitpos: [31:27]; default: 16; - * need_des - */ - uint32_t hp_active_hp_regulator_dbias:5; - }; - uint32_t val; -} pmu_hp_active_hp_regulator0_reg_t; - -/** Type of hp_active_hp_regulator1 register - * need_des - */ -typedef union { - struct { - uint32_t reserved_0:8; - /** hp_active_hp_regulator_drv_b : R/W; bitpos: [31:8]; default: 0; - * need_des - */ - uint32_t hp_active_hp_regulator_drv_b:24; - }; - uint32_t val; -} pmu_hp_active_hp_regulator1_reg_t; - -/** Type of hp_active_xtal register - * need_des - */ -typedef union { - struct { - uint32_t reserved_0:30; - /** hp_active_xpd_xtalx2 : R/W; bitpos: [30]; default: 1; - * need_des - */ - uint32_t hp_active_xpd_xtalx2:1; - /** hp_active_xpd_xtal : R/W; bitpos: [31]; default: 1; - * need_des - */ - uint32_t hp_active_xpd_xtal:1; - }; - uint32_t val; -} pmu_hp_active_xtal_reg_t; - -/** Type of hp_sleep_dig_power register - * need_des - */ -typedef union { - struct { - uint32_t reserved_0:18; - /** hp_sleep_vdd_flash_mode : R/W; bitpos: [21:18]; default: 0; - * need_des - */ - uint32_t hp_sleep_vdd_flash_mode:4; - /** hp_sleep_hp_mem_dslp : R/W; bitpos: [22]; default: 0; - * need_des - */ - uint32_t hp_sleep_hp_mem_dslp:1; - /** hp_sleep_pd_hp_mem_pd_en : R/W; bitpos: [26:23]; default: 0; - * need_des - */ - uint32_t hp_sleep_pd_hp_mem_pd_en:4; - /** hp_sleep_pd_hp_wifi_pd_en : R/W; bitpos: [27]; default: 0; - * need_des - */ - uint32_t hp_sleep_pd_hp_wifi_pd_en:1; - /** hp_sleep_pd_hp_peri_pd_en : R/W; bitpos: [28]; default: 0; - * need_des - */ - uint32_t hp_sleep_pd_hp_peri_pd_en:1; - /** hp_sleep_pd_hp_cpu_pd_en : R/W; bitpos: [29]; default: 0; - * need_des - */ - uint32_t hp_sleep_pd_hp_cpu_pd_en:1; - /** hp_sleep_pd_hp_aon_pd_en : R/W; bitpos: [30]; default: 0; - * need_des - */ - uint32_t hp_sleep_pd_hp_aon_pd_en:1; - /** hp_sleep_pd_top_pd_en : R/W; bitpos: [31]; default: 0; - * need_des - */ - uint32_t hp_sleep_pd_top_pd_en:1; - }; - uint32_t val; -} pmu_hp_sleep_dig_power_reg_t; - -/** Type of hp_sleep_icg_hp_func register - * need_des - */ typedef union { struct { - /** hp_sleep_dig_icg_func_en : R/W; bitpos: [31:0]; default: 4294967295; - * need_des - */ - uint32_t hp_sleep_dig_icg_func_en:32; + uint32_t reserved0 : 21; + uint32_t vdd_spi_pd_en: 1; + uint32_t mem_dslp : 1; + uint32_t mem_pd_en : 4; + uint32_t wifi_pd_en : 1; + uint32_t reserved1 : 1; + uint32_t cpu_pd_en : 1; + uint32_t aon_pd_en : 1; + uint32_t top_pd_en : 1; }; uint32_t val; -} pmu_hp_sleep_icg_hp_func_reg_t; +} pmu_hp_dig_power_reg_t; -/** Type of hp_sleep_icg_hp_apb register - * need_des - */ typedef union { struct { - /** hp_sleep_dig_icg_apb_en : R/W; bitpos: [31:0]; default: 4294967295; - * need_des - */ - uint32_t hp_sleep_dig_icg_apb_en:32; + uint32_t reserved0: 30; + uint32_t code : 2; }; uint32_t val; -} pmu_hp_sleep_icg_hp_apb_reg_t; +} pmu_hp_icg_modem_reg_t; -/** Type of hp_sleep_icg_modem register - * need_des - */ typedef union { struct { - uint32_t reserved_0:30; - /** hp_sleep_dig_icg_modem_code : R/W; bitpos: [31:30]; default: 0; - * need_des - */ - uint32_t hp_sleep_dig_icg_modem_code:2; + uint32_t reserved0 : 24; + uint32_t uart_wakeup_en : 1; + uint32_t lp_pad_hold_all: 1; + uint32_t hp_pad_hold_all: 1; + uint32_t dig_pad_slp_sel: 1; + uint32_t dig_pause_wdt : 1; + uint32_t dig_cpu_stall : 1; + uint32_t reserved1 : 2; }; uint32_t val; -} pmu_hp_sleep_icg_modem_reg_t; +} pmu_hp_sys_cntl_reg_t; -/** Type of hp_sleep_hp_sys_cntl register - * need_des - */ typedef union { struct { - uint32_t reserved_0:24; - /** hp_sleep_uart_wakeup_en : R/W; bitpos: [24]; default: 0; - * need_des - */ - uint32_t hp_sleep_uart_wakeup_en:1; - /** hp_sleep_lp_pad_hold_all : R/W; bitpos: [25]; default: 0; - * need_des - */ - uint32_t hp_sleep_lp_pad_hold_all:1; - /** hp_sleep_hp_pad_hold_all : R/W; bitpos: [26]; default: 0; - * need_des - */ - uint32_t hp_sleep_hp_pad_hold_all:1; - /** hp_sleep_dig_pad_slp_sel : R/W; bitpos: [27]; default: 0; - * need_des - */ - uint32_t hp_sleep_dig_pad_slp_sel:1; - /** hp_sleep_dig_pause_wdt : R/W; bitpos: [28]; default: 0; - * need_des - */ - uint32_t hp_sleep_dig_pause_wdt:1; - /** hp_sleep_dig_cpu_stall : R/W; bitpos: [29]; default: 0; - * need_des - */ - uint32_t hp_sleep_dig_cpu_stall:1; - uint32_t reserved_30:2; + uint32_t reserved0 : 26; + uint32_t i2c_iso_en : 1; + uint32_t i2c_retention: 1; + uint32_t xpd_bb_i2c : 1; + uint32_t xpd_bbpll_i2c: 1; + uint32_t xpd_bbpll : 1; + uint32_t reserved1 : 1; }; uint32_t val; -} pmu_hp_sleep_hp_sys_cntl_reg_t; +} pmu_hp_clk_power_reg_t; -/** Type of hp_sleep_hp_ck_power register - * need_des - */ typedef union { struct { - uint32_t reserved_0:26; - /** hp_sleep_i2c_iso_en : R/W; bitpos: [26]; default: 0; - * need_des - */ - uint32_t hp_sleep_i2c_iso_en:1; - /** hp_sleep_i2c_retention : R/W; bitpos: [27]; default: 0; - * need_des - */ - uint32_t hp_sleep_i2c_retention:1; - /** hp_sleep_xpd_bb_i2c : R/W; bitpos: [28]; default: 0; - * need_des - */ - uint32_t hp_sleep_xpd_bb_i2c:1; - /** hp_sleep_xpd_bbpll_i2c : R/W; bitpos: [29]; default: 0; - * need_des - */ - uint32_t hp_sleep_xpd_bbpll_i2c:1; - /** hp_sleep_xpd_bbpll : R/W; bitpos: [30]; default: 0; - * need_des - */ - uint32_t hp_sleep_xpd_bbpll:1; - uint32_t reserved_31:1; + uint32_t reserved0 : 24; + uint32_t xpd_trx : 1; + uint32_t xpd_bias : 1; + uint32_t reserved1 : 4; + uint32_t pd_cur : 1; + uint32_t bias_sleep: 1; }; uint32_t val; -} pmu_hp_sleep_hp_ck_power_reg_t; +} pmu_hp_bias_reg_t; -/** Type of hp_sleep_bias register - * need_des - */ typedef union { - struct { - uint32_t reserved_0:9; - /** hp_sleep_dcdc_ccm_enb : R/W; bitpos: [9]; default: 1; - * need_des - */ - uint32_t hp_sleep_dcdc_ccm_enb:1; - /** hp_sleep_dcdc_clear_rdy : R/W; bitpos: [10]; default: 0; - * need_des - */ - uint32_t hp_sleep_dcdc_clear_rdy:1; - /** hp_sleep_dig_pmu_dpcur_bias : R/W; bitpos: [12:11]; default: 1; - * need_des - */ - uint32_t hp_sleep_dig_pmu_dpcur_bias:2; - /** hp_sleep_dig_pmu_dsfmos : R/W; bitpos: [16:13]; default: 4; - * need_des - */ - uint32_t hp_sleep_dig_pmu_dsfmos:4; - /** hp_sleep_dcm_vset : R/W; bitpos: [21:17]; default: 23; - * need_des - */ - uint32_t hp_sleep_dcm_vset:5; - /** hp_sleep_dcm_mode : R/W; bitpos: [23:22]; default: 0; - * need_des - */ - uint32_t hp_sleep_dcm_mode:2; - /** hp_sleep_xpd_trx : R/W; bitpos: [24]; default: 1; - * need_des - */ - uint32_t hp_sleep_xpd_trx:1; - /** hp_sleep_xpd_bias : R/W; bitpos: [25]; default: 0; - * need_des - */ - uint32_t hp_sleep_xpd_bias:1; - uint32_t reserved_26:3; - /** hp_sleep_discnnt_dig_rtc : R/W; bitpos: [29]; default: 0; - * need_des - */ - uint32_t hp_sleep_discnnt_dig_rtc:1; - /** hp_sleep_pd_cur : R/W; bitpos: [30]; default: 0; - * need_des - */ - uint32_t hp_sleep_pd_cur:1; - /** hp_sleep_bias_sleep : R/W; bitpos: [31]; default: 0; - * need_des - */ - uint32_t hp_sleep_bias_sleep:1; + struct { /* HP: Active State */ + uint32_t reserved0 : 4; + uint32_t hp_sleep2active_backup_modem_clk_code: 2; + uint32_t hp_modem2active_backup_modem_clk_code: 2; + uint32_t reserved1 : 2; + uint32_t hp_active_retention_mode : 1; + uint32_t hp_sleep2active_retention_en : 1; + uint32_t hp_modem2active_retention_en : 1; + uint32_t reserved2 : 1; + uint32_t hp_sleep2active_backup_clk_sel : 2; + uint32_t hp_modem2active_backup_clk_sel : 2; + uint32_t reserved3 : 2; + uint32_t hp_sleep2active_backup_mode : 3; + uint32_t hp_modem2active_backup_mode : 3; + uint32_t reserved4 : 3; + uint32_t hp_sleep2active_backup_en : 1; + uint32_t hp_modem2active_backup_en : 1; + uint32_t reserved5 : 1; }; - uint32_t val; -} pmu_hp_sleep_bias_reg_t; - -/** Type of hp_sleep_backup register - * need_des - */ -typedef union { - struct { - uint32_t reserved_0:6; - /** hp_modem2sleep_backup_modem_clk_code : R/W; bitpos: [7:6]; default: 0; - * need_des - */ - uint32_t hp_modem2sleep_backup_modem_clk_code:2; - /** hp_active2sleep_backup_modem_clk_code : R/W; bitpos: [9:8]; default: 0; - * need_des - */ - uint32_t hp_active2sleep_backup_modem_clk_code:2; - uint32_t reserved_10:6; - /** hp_modem2sleep_backup_clk_sel : R/W; bitpos: [17:16]; default: 0; - * need_des - */ - uint32_t hp_modem2sleep_backup_clk_sel:2; - /** hp_active2sleep_backup_clk_sel : R/W; bitpos: [19:18]; default: 0; - * need_des - */ - uint32_t hp_active2sleep_backup_clk_sel:2; - /** hp_modem2sleep_backup_mode : R/W; bitpos: [24:20]; default: 0; - * need_des - */ - uint32_t hp_modem2sleep_backup_mode:5; - /** hp_active2sleep_backup_mode : R/W; bitpos: [29:25]; default: 0; - * need_des - */ - uint32_t hp_active2sleep_backup_mode:5; - /** hp_modem2sleep_backup_en : R/W; bitpos: [30]; default: 0; - * need_des - */ - uint32_t hp_modem2sleep_backup_en:1; - /** hp_active2sleep_backup_en : R/W; bitpos: [31]; default: 0; - * need_des - */ - uint32_t hp_active2sleep_backup_en:1; + struct { /* HP: Modem State */ + uint32_t reserved6 : 4; + uint32_t hp_sleep2modem_backup_modem_clk_code : 2; + uint32_t reserved7 : 4; + uint32_t hp_modem_retention_mode : 1; + uint32_t hp_sleep2modem_retention_en : 1; + uint32_t reserved8 : 2; + uint32_t hp_sleep2modem_backup_clk_sel : 2; + uint32_t reserved9 : 4; + uint32_t hp_sleep2modem_backup_mode : 3; + uint32_t reserved10 : 6; + uint32_t hp_sleep2modem_backup_en : 1; + uint32_t reserved11 : 2; }; - uint32_t val; -} pmu_hp_sleep_backup_reg_t; - -/** Type of hp_sleep_backup_clk register - * need_des - */ -typedef union { - struct { - /** hp_sleep_backup_icg_func_en : R/W; bitpos: [31:0]; default: 0; - * need_des - */ - uint32_t hp_sleep_backup_icg_func_en:32; + struct { /* HP: Sleep State */ + uint32_t reserved12 : 6; + uint32_t hp_modem2sleep_backup_modem_clk_code : 2; + uint32_t hp_active2sleep_backup_modem_clk_code: 2; + uint32_t hp_sleep_retention_mode : 1; + uint32_t reserved13 : 1; + uint32_t hp_modem2sleep_retention_en : 1; + uint32_t hp_active2sleep_retention_en : 1; + uint32_t reserved14 : 2; + uint32_t hp_modem2sleep_backup_clk_sel : 2; + uint32_t hp_active2sleep_backup_clk_sel : 2; + uint32_t reserved15 : 3; + uint32_t hp_modem2sleep_backup_mode : 3; + uint32_t hp_active2sleep_backup_mode : 3; + uint32_t reserved16 : 1; + uint32_t hp_modem2sleep_backup_en : 1; + uint32_t hp_active2sleep_backup_en : 1; }; uint32_t val; -} pmu_hp_sleep_backup_clk_reg_t; +} pmu_hp_backup_reg_t; -/** Type of hp_sleep_sysclk register - * need_des - */ typedef union { struct { - uint32_t reserved_0:26; - /** hp_sleep_dig_sys_clk_no_div : R/W; bitpos: [26]; default: 0; - * need_des - */ - uint32_t hp_sleep_dig_sys_clk_no_div:1; - /** hp_sleep_icg_sys_clock_en : R/W; bitpos: [27]; default: 0; - * need_des - */ - uint32_t hp_sleep_icg_sys_clock_en:1; - /** hp_sleep_sys_clk_slp_sel : R/W; bitpos: [28]; default: 0; - * need_des - */ - uint32_t hp_sleep_sys_clk_slp_sel:1; - /** hp_sleep_icg_slp_sel : R/W; bitpos: [29]; default: 0; - * need_des - */ - uint32_t hp_sleep_icg_slp_sel:1; - /** hp_sleep_dig_sys_clk_sel : R/W; bitpos: [31:30]; default: 0; - * need_des - */ - uint32_t hp_sleep_dig_sys_clk_sel:2; + uint32_t reserved0 : 26; + uint32_t dig_sysclk_nodiv: 1; + uint32_t icg_sysclk_en : 1; + uint32_t sysclk_slp_sel : 1; + uint32_t icg_slp_sel : 1; + uint32_t dig_sysclk_sel : 2; }; uint32_t val; -} pmu_hp_sleep_sysclk_reg_t; +} pmu_hp_sysclk_reg_t; -/** Type of hp_sleep_hp_regulator0 register - * need_des - */ typedef union { struct { - /** hp_sleep_hp_power_det_bypass : R/W; bitpos: [0]; default: 0; - * need_des - */ - uint32_t hp_sleep_hp_power_det_bypass:1; - uint32_t reserved_1:15; - /** hp_sleep_hp_regulator_slp_mem_xpd : R/W; bitpos: [16]; default: 1; - * need_des - */ - uint32_t hp_sleep_hp_regulator_slp_mem_xpd:1; - /** hp_sleep_hp_regulator_slp_logic_xpd : R/W; bitpos: [17]; default: 1; - * need_des - */ - uint32_t hp_sleep_hp_regulator_slp_logic_xpd:1; - /** hp_sleep_hp_regulator_xpd : R/W; bitpos: [18]; default: 1; - * need_des - */ - uint32_t hp_sleep_hp_regulator_xpd:1; - /** hp_sleep_hp_regulator_slp_mem_dbias : R/W; bitpos: [22:19]; default: 8; - * need_des - */ - uint32_t hp_sleep_hp_regulator_slp_mem_dbias:4; - /** hp_sleep_hp_regulator_slp_logic_dbias : R/W; bitpos: [26:23]; default: 8; - * need_des - */ - uint32_t hp_sleep_hp_regulator_slp_logic_dbias:4; - /** hp_sleep_hp_regulator_dbias : R/W; bitpos: [31:27]; default: 16; - * need_des - */ - uint32_t hp_sleep_hp_regulator_dbias:5; + uint32_t power_det_bypass : 1; + uint32_t reserved0 : 3; /* Only HP_ACTIVE modem under hp system is valid */ + uint32_t lp_dbias_vol : 5; /* Only HP_ACTIVE modem under hp system is valid */ + uint32_t hp_dbias_vol : 5; /* Only HP_ACTIVE modem under hp system is valid */ + uint32_t dbias_sel : 1; /* Only HP_ACTIVE modem under hp system is valid */ + uint32_t dbias_init : 1; /* Only HP_ACTIVE modem under hp system is valid */ + uint32_t slp_mem_xpd : 1; + uint32_t slp_logic_xpd : 1; + uint32_t xpd : 1; + uint32_t slp_mem_dbias : 4; + uint32_t slp_logic_dbias : 4; + uint32_t dbias : 5; }; uint32_t val; -} pmu_hp_sleep_hp_regulator0_reg_t; +} pmu_hp_regulator0_reg_t; -/** Type of hp_sleep_hp_regulator1 register - * need_des - */ typedef union { struct { - uint32_t reserved_0:8; - /** hp_sleep_hp_regulator_drv_b : R/W; bitpos: [31:8]; default: 0; - * need_des - */ - uint32_t hp_sleep_hp_regulator_drv_b:24; + uint32_t reserved0: 8; + uint32_t drv_b : 24; }; uint32_t val; -} pmu_hp_sleep_hp_regulator1_reg_t; +} pmu_hp_regulator1_reg_t; -/** Type of hp_sleep_xtal register - * need_des - */ typedef union { struct { - uint32_t reserved_0:30; - /** hp_sleep_xpd_xtalx2 : R/W; bitpos: [30]; default: 1; - * need_des - */ - uint32_t hp_sleep_xpd_xtalx2:1; - /** hp_sleep_xpd_xtal : R/W; bitpos: [31]; default: 1; - * need_des - */ - uint32_t hp_sleep_xpd_xtal:1; + uint32_t reserved0: 31; + uint32_t xpd_xtal : 1; }; uint32_t val; -} pmu_hp_sleep_xtal_reg_t; +} pmu_hp_xtal_reg_t; -/** Type of hp_sleep_lp_regulator0 register - * need_des - */ -typedef union { - struct { - uint32_t reserved_0:21; - /** hp_sleep_lp_regulator_slp_xpd : R/W; bitpos: [21]; default: 1; - * need_des - */ - uint32_t hp_sleep_lp_regulator_slp_xpd:1; - /** hp_sleep_lp_regulator_xpd : R/W; bitpos: [22]; default: 1; - * need_des - */ - uint32_t hp_sleep_lp_regulator_xpd:1; - /** hp_sleep_lp_regulator_slp_dbias : R/W; bitpos: [26:23]; default: 8; - * need_des - */ - uint32_t hp_sleep_lp_regulator_slp_dbias:4; - /** hp_sleep_lp_regulator_dbias : R/W; bitpos: [31:27]; default: 0; - * need_des - */ - uint32_t hp_sleep_lp_regulator_dbias:5; - }; - uint32_t val; -} pmu_hp_sleep_lp_regulator0_reg_t; +typedef struct pmu_hp_hw_regmap_t{ + pmu_hp_dig_power_reg_t dig_power; + uint32_t icg_func; + uint32_t icg_apb; + pmu_hp_icg_modem_reg_t icg_modem; + pmu_hp_sys_cntl_reg_t syscntl; + pmu_hp_clk_power_reg_t clk_power; + pmu_hp_bias_reg_t bias; + pmu_hp_backup_reg_t backup; + uint32_t backup_clk; + pmu_hp_sysclk_reg_t sysclk; + pmu_hp_regulator0_reg_t regulator0; + pmu_hp_regulator1_reg_t regulator1; + pmu_hp_xtal_reg_t xtal; +} pmu_hp_hw_regmap_t; -/** Type of hp_sleep_lp_regulator1 register - * need_des - */ +/** */ typedef union { struct { - uint32_t reserved_0:28; - /** hp_sleep_lp_regulator_drv_b : R/W; bitpos: [31:28]; default: 0; - * need_des - */ - uint32_t hp_sleep_lp_regulator_drv_b:4; + uint32_t reserved0: 21; + uint32_t slp_xpd : 1; + uint32_t xpd : 1; + uint32_t slp_dbias: 4; + uint32_t dbias : 5; }; uint32_t val; -} pmu_hp_sleep_lp_regulator1_reg_t; +} pmu_lp_regulator0_reg_t; -/** Type of hp_sleep_lp_dig_power register - * need_des - */ typedef union { struct { - uint32_t reserved_0:23; - /** hp_sleep_vdd_io_mode : R/W; bitpos: [26:23]; default: 0; - * need_des - */ - uint32_t hp_sleep_vdd_io_mode:4; - /** hp_sleep_bod_source_sel : R/W; bitpos: [27]; default: 0; - * need_des - */ - uint32_t hp_sleep_bod_source_sel:1; - /** hp_sleep_vddbat_mode : R/W; bitpos: [29:28]; default: 0; - * need_des - */ - uint32_t hp_sleep_vddbat_mode:2; - /** hp_sleep_lp_mem_dslp : R/W; bitpos: [30]; default: 0; - * need_des - */ - uint32_t hp_sleep_lp_mem_dslp:1; - /** hp_sleep_pd_lp_peri_pd_en : R/W; bitpos: [31]; default: 0; - * need_des - */ - uint32_t hp_sleep_pd_lp_peri_pd_en:1; + uint32_t reserved0: 28; + uint32_t drv_b : 4; }; uint32_t val; -} pmu_hp_sleep_lp_dig_power_reg_t; +} pmu_lp_regulator1_reg_t; -/** Type of hp_sleep_lp_ck_power register - * need_des - */ typedef union { struct { - uint32_t reserved_0:27; - /** hp_sleep_xpd_lppll : R/W; bitpos: [27]; default: 0; - * need_des - */ - uint32_t hp_sleep_xpd_lppll:1; - /** hp_sleep_xpd_xtal32k : R/W; bitpos: [28]; default: 0; - * need_des - */ - uint32_t hp_sleep_xpd_xtal32k:1; - /** hp_sleep_xpd_rc32k : R/W; bitpos: [29]; default: 0; - * need_des - */ - uint32_t hp_sleep_xpd_rc32k:1; - /** hp_sleep_xpd_fosc_clk : R/W; bitpos: [30]; default: 1; - * need_des - */ - uint32_t hp_sleep_xpd_fosc_clk:1; - /** hp_sleep_pd_osc_clk : R/W; bitpos: [31]; default: 0; - * need_des - */ - uint32_t hp_sleep_pd_osc_clk:1; + uint32_t reserved0: 31; + uint32_t xpd_xtal : 1; }; uint32_t val; -} pmu_hp_sleep_lp_ck_power_reg_t; +} pmu_lp_xtal_reg_t; -/** Type of lp_sleep_lp_regulator0 register - * need_des - */ typedef union { struct { - uint32_t reserved_0:21; - /** lp_sleep_lp_regulator_slp_xpd : R/W; bitpos: [21]; default: 1; - * need_des - */ - uint32_t lp_sleep_lp_regulator_slp_xpd:1; - /** lp_sleep_lp_regulator_xpd : R/W; bitpos: [22]; default: 1; - * need_des - */ - uint32_t lp_sleep_lp_regulator_xpd:1; - /** lp_sleep_lp_regulator_slp_dbias : R/W; bitpos: [26:23]; default: 8; - * need_des - */ - uint32_t lp_sleep_lp_regulator_slp_dbias:4; - /** lp_sleep_lp_regulator_dbias : R/W; bitpos: [31:27]; default: 0; - * need_des - */ - uint32_t lp_sleep_lp_regulator_dbias:5; + uint32_t reserved0 : 27; + uint32_t bod_source_sel : 1; + uint32_t vddbat_mode : 2; + uint32_t mem_dslp : 1; + uint32_t peri_pd_en : 1; }; uint32_t val; -} pmu_lp_sleep_lp_regulator0_reg_t; +} pmu_lp_dig_power_reg_t; -/** Type of lp_sleep_lp_regulator1 register - * need_des - */ typedef union { struct { - uint32_t reserved_0:28; - /** lp_sleep_lp_regulator_drv_b : R/W; bitpos: [31:28]; default: 0; - * need_des - */ - uint32_t lp_sleep_lp_regulator_drv_b:4; + uint32_t reserved0 : 27; + uint32_t xpd_lppll : 1; + uint32_t xpd_xtal32k: 1; + uint32_t xpd_rc32k : 1; + uint32_t xpd_fosc : 1; + uint32_t pd_osc : 1; }; uint32_t val; -} pmu_lp_sleep_lp_regulator1_reg_t; +} pmu_lp_clk_power_reg_t; -/** Type of lp_sleep_xtal register - * need_des - */ typedef union { struct { - uint32_t reserved_0:30; - /** lp_sleep_xpd_xtalx2 : R/W; bitpos: [30]; default: 1; - * need_des - */ - uint32_t lp_sleep_xpd_xtalx2:1; - /** lp_sleep_xpd_xtal : R/W; bitpos: [31]; default: 1; - * need_des - */ - uint32_t lp_sleep_xpd_xtal:1; + uint32_t reserved0 : 25; + uint32_t xpd_bias : 1; + uint32_t reserved1 : 4; + uint32_t pd_cur : 1; + uint32_t bias_sleep: 1; }; uint32_t val; -} pmu_lp_sleep_xtal_reg_t; +} pmu_lp_bias_reg_t; -/** Type of lp_sleep_lp_dig_power register - * need_des - */ -typedef union { - struct { - uint32_t reserved_0:23; - /** lp_sleep_vdd_io_mode : R/W; bitpos: [26:23]; default: 0; - * need_des - */ - uint32_t lp_sleep_vdd_io_mode:4; - /** lp_sleep_bod_source_sel : R/W; bitpos: [27]; default: 0; - * need_des - */ - uint32_t lp_sleep_bod_source_sel:1; - /** lp_sleep_vddbat_mode : R/W; bitpos: [29:28]; default: 0; - * need_des - */ - uint32_t lp_sleep_vddbat_mode:2; - /** lp_sleep_lp_mem_dslp : R/W; bitpos: [30]; default: 0; - * need_des - */ - uint32_t lp_sleep_lp_mem_dslp:1; - /** lp_sleep_pd_lp_peri_pd_en : R/W; bitpos: [31]; default: 0; - * need_des - */ - uint32_t lp_sleep_pd_lp_peri_pd_en:1; - }; - uint32_t val; -} pmu_lp_sleep_lp_dig_power_reg_t; +typedef struct pmu_lp_hw_regmap_t{ + pmu_lp_regulator0_reg_t regulator0; + pmu_lp_regulator1_reg_t regulator1; + pmu_lp_xtal_reg_t xtal; /* Only LP_SLEEP mode under lp system is valid */ + pmu_lp_dig_power_reg_t dig_power; + pmu_lp_clk_power_reg_t clk_power; + pmu_lp_bias_reg_t bias; /* Only LP_SLEEP mode under lp system is valid */ +} pmu_lp_hw_regmap_t; -/** Type of lp_sleep_lp_ck_power register - * need_des - */ -typedef union { - struct { - uint32_t reserved_0:27; - /** lp_sleep_xpd_lppll : R/W; bitpos: [27]; default: 0; - * need_des - */ - uint32_t lp_sleep_xpd_lppll:1; - /** lp_sleep_xpd_xtal32k : R/W; bitpos: [28]; default: 0; - * need_des - */ - uint32_t lp_sleep_xpd_xtal32k:1; - /** lp_sleep_xpd_rc32k : R/W; bitpos: [29]; default: 0; - * need_des - */ - uint32_t lp_sleep_xpd_rc32k:1; - /** lp_sleep_xpd_fosc_clk : R/W; bitpos: [30]; default: 1; - * need_des - */ - uint32_t lp_sleep_xpd_fosc_clk:1; - /** lp_sleep_pd_osc_clk : R/W; bitpos: [31]; default: 0; - * need_des - */ - uint32_t lp_sleep_pd_osc_clk:1; - }; - uint32_t val; -} pmu_lp_sleep_lp_ck_power_reg_t; -/** Type of lp_sleep_bias register - * need_des - */ typedef union { struct { - uint32_t reserved_0:9; - /** lp_sleep_dcdc_ccm_enb : R/W; bitpos: [9]; default: 1; - * need_des - */ - uint32_t lp_sleep_dcdc_ccm_enb:1; - /** lp_sleep_dcdc_clear_rdy : R/W; bitpos: [10]; default: 0; - * need_des - */ - uint32_t lp_sleep_dcdc_clear_rdy:1; - /** lp_sleep_dig_pmu_dpcur_bias : R/W; bitpos: [12:11]; default: 1; - * need_des - */ - uint32_t lp_sleep_dig_pmu_dpcur_bias:2; - /** lp_sleep_dig_pmu_dsfmos : R/W; bitpos: [16:13]; default: 4; - * need_des - */ - uint32_t lp_sleep_dig_pmu_dsfmos:4; - /** lp_sleep_dcm_vset : R/W; bitpos: [21:17]; default: 23; - * need_des - */ - uint32_t lp_sleep_dcm_vset:5; - /** lp_sleep_dcm_mode : R/W; bitpos: [23:22]; default: 0; - * need_des - */ - uint32_t lp_sleep_dcm_mode:2; - uint32_t reserved_24:1; - /** lp_sleep_xpd_bias : R/W; bitpos: [25]; default: 0; - * need_des - */ - uint32_t lp_sleep_xpd_bias:1; - uint32_t reserved_26:3; - /** lp_sleep_discnnt_dig_rtc : R/W; bitpos: [29]; default: 0; - * need_des - */ - uint32_t lp_sleep_discnnt_dig_rtc:1; - /** lp_sleep_pd_cur : R/W; bitpos: [30]; default: 0; - * need_des - */ - uint32_t lp_sleep_pd_cur:1; - /** lp_sleep_bias_sleep : R/W; bitpos: [31]; default: 0; - * need_des - */ - uint32_t lp_sleep_bias_sleep:1; + uint32_t tie_low_global_bbpll_icg : 1; + uint32_t tie_low_global_xtal_icg : 1; + uint32_t tie_low_i2c_retention : 1; + uint32_t tie_low_xpd_bb_i2c : 1; + uint32_t tie_low_xpd_bbpll_i2c : 1; + uint32_t tie_low_xpd_bbpll : 1; + uint32_t tie_low_xpd_xtal : 1; + uint32_t reserved0 : 18; + uint32_t tie_high_global_bbpll_icg: 1; + uint32_t tie_high_global_xtal_icg : 1; + uint32_t tie_high_i2c_retention : 1; + uint32_t tie_high_xpd_bb_i2c : 1; + uint32_t tie_high_xpd_bbpll_i2c : 1; + uint32_t tie_high_xpd_bbpll : 1; + uint32_t tie_high_xpd_xtal : 1; }; uint32_t val; -} pmu_lp_sleep_bias_reg_t; +} pmu_imm_hp_clk_power_reg_t; -/** Type of imm_hp_ck_power register - * need_des - */ typedef union { struct { - /** tie_low_global_bbpll_icg : WT; bitpos: [0]; default: 0; - * need_des - */ - uint32_t tie_low_global_bbpll_icg:1; - /** tie_low_global_xtal_icg : WT; bitpos: [1]; default: 0; - * need_des - */ - uint32_t tie_low_global_xtal_icg:1; - /** tie_low_i2c_retention : WT; bitpos: [2]; default: 0; - * need_des - */ - uint32_t tie_low_i2c_retention:1; - /** tie_low_xpd_bb_i2c : WT; bitpos: [3]; default: 0; - * need_des - */ - uint32_t tie_low_xpd_bb_i2c:1; - /** tie_low_xpd_bbpll_i2c : WT; bitpos: [4]; default: 0; - * need_des - */ - uint32_t tie_low_xpd_bbpll_i2c:1; - /** tie_low_xpd_bbpll : WT; bitpos: [5]; default: 0; - * need_des - */ - uint32_t tie_low_xpd_bbpll:1; - /** tie_low_xpd_xtal : WT; bitpos: [6]; default: 0; - * need_des - */ - uint32_t tie_low_xpd_xtal:1; - /** tie_low_global_xtalx2_icg : WT; bitpos: [7]; default: 0; - * need_des - */ - uint32_t tie_low_global_xtalx2_icg:1; - /** tie_low_xpd_xtalx2 : WT; bitpos: [8]; default: 0; - * need_des - */ - uint32_t tie_low_xpd_xtalx2:1; - uint32_t reserved_9:14; - /** tie_high_xtalx2 : WT; bitpos: [23]; default: 0; - * need_des - */ - uint32_t tie_high_xtalx2:1; - /** tie_high_global_xtalx2_icg : WT; bitpos: [24]; default: 0; - * need_des - */ - uint32_t tie_high_global_xtalx2_icg:1; - /** tie_high_global_bbpll_icg : WT; bitpos: [25]; default: 0; - * need_des - */ - uint32_t tie_high_global_bbpll_icg:1; - /** tie_high_global_xtal_icg : WT; bitpos: [26]; default: 0; - * need_des - */ - uint32_t tie_high_global_xtal_icg:1; - /** tie_high_i2c_retention : WT; bitpos: [27]; default: 0; - * need_des - */ - uint32_t tie_high_i2c_retention:1; - /** tie_high_xpd_bb_i2c : WT; bitpos: [28]; default: 0; - * need_des - */ - uint32_t tie_high_xpd_bb_i2c:1; - /** tie_high_xpd_bbpll_i2c : WT; bitpos: [29]; default: 0; - * need_des - */ - uint32_t tie_high_xpd_bbpll_i2c:1; - /** tie_high_xpd_bbpll : WT; bitpos: [30]; default: 0; - * need_des - */ - uint32_t tie_high_xpd_bbpll:1; - /** tie_high_xpd_xtal : WT; bitpos: [31]; default: 0; - * need_des - */ - uint32_t tie_high_xpd_xtal:1; - }; - uint32_t val; -} pmu_imm_hp_ck_power_reg_t; - -/** Type of imm_sleep_sysclk register - * need_des - */ -typedef union { - struct { - uint32_t reserved_0:28; - /** update_dig_icg_switch : WT; bitpos: [28]; default: 0; - * need_des - */ - uint32_t update_dig_icg_switch:1; - /** tie_low_icg_slp_sel : WT; bitpos: [29]; default: 0; - * need_des - */ - uint32_t tie_low_icg_slp_sel:1; - /** tie_high_icg_slp_sel : WT; bitpos: [30]; default: 0; - * need_des - */ - uint32_t tie_high_icg_slp_sel:1; - /** update_dig_sys_clk_sel : WT; bitpos: [31]; default: 0; - * need_des - */ - uint32_t update_dig_sys_clk_sel:1; + uint32_t reserved0 : 28; + uint32_t update_dig_icg_switch: 1; + uint32_t tie_low_icg_slp_sel : 1; + uint32_t tie_high_icg_slp_sel : 1; + uint32_t update_dig_sysclk_sel: 1; }; uint32_t val; } pmu_imm_sleep_sysclk_reg_t; -/** Type of imm_hp_func_icg register - * need_des - */ typedef union { struct { - uint32_t reserved_0:31; - /** update_dig_icg_func_en : WT; bitpos: [31]; default: 0; - * need_des - */ - uint32_t update_dig_icg_func_en:1; + uint32_t reserved0 : 31; + uint32_t update_dig_icg_func_en: 1; }; uint32_t val; } pmu_imm_hp_func_icg_reg_t; -/** Type of imm_hp_apb_icg register - * need_des - */ typedef union { struct { - uint32_t reserved_0:31; - /** update_dig_icg_apb_en : WT; bitpos: [31]; default: 0; - * need_des - */ - uint32_t update_dig_icg_apb_en:1; + uint32_t reserved0 : 31; + uint32_t update_dig_icg_apb_en: 1; }; uint32_t val; } pmu_imm_hp_apb_icg_reg_t; -/** Type of imm_modem_icg register - * need_des - */ typedef union { struct { - uint32_t reserved_0:31; - /** update_dig_icg_modem_en : WT; bitpos: [31]; default: 0; - * need_des - */ - uint32_t update_dig_icg_modem_en:1; + uint32_t reserved0 : 31; + uint32_t update_dig_icg_modem_en: 1; }; uint32_t val; } pmu_imm_modem_icg_reg_t; -/** Type of imm_lp_icg register - * need_des - */ typedef union { struct { - uint32_t reserved_0:30; - /** tie_low_lp_rootclk_sel : WT; bitpos: [30]; default: 0; - * need_des - */ - uint32_t tie_low_lp_rootclk_sel:1; - /** tie_high_lp_rootclk_sel : WT; bitpos: [31]; default: 0; - * need_des - */ - uint32_t tie_high_lp_rootclk_sel:1; + uint32_t reserved0 : 30; + uint32_t tie_low_lp_rootclk_sel : 1; + uint32_t tie_high_lp_rootclk_sel: 1; }; uint32_t val; } pmu_imm_lp_icg_reg_t; -/** Type of imm_pad_hold_all register - * need_des - */ typedef union { struct { - uint32_t reserved_0:26; - /** tie_high_dig_pad_slp_sel : WT; bitpos: [26]; default: 0; - * need_des - */ - uint32_t tie_high_dig_pad_slp_sel:1; - /** tie_low_dig_pad_slp_sel : WT; bitpos: [27]; default: 0; - * need_des - */ - uint32_t tie_low_dig_pad_slp_sel:1; - /** tie_high_lp_pad_hold_all : WT; bitpos: [28]; default: 0; - * need_des - */ - uint32_t tie_high_lp_pad_hold_all:1; - /** tie_low_lp_pad_hold_all : WT; bitpos: [29]; default: 0; - * need_des - */ - uint32_t tie_low_lp_pad_hold_all:1; - /** tie_high_hp_pad_hold_all : WT; bitpos: [30]; default: 0; - * need_des - */ - uint32_t tie_high_hp_pad_hold_all:1; - /** tie_low_hp_pad_hold_all : WT; bitpos: [31]; default: 0; - * need_des - */ - uint32_t tie_low_hp_pad_hold_all:1; + uint32_t reserved0 : 28; + uint32_t tie_high_lp_pad_hold_all: 1; + uint32_t tie_low_lp_pad_hold_all : 1; + uint32_t tie_high_hp_pad_hold_all: 1; + uint32_t tie_low_hp_pad_hold_all : 1; }; uint32_t val; } pmu_imm_pad_hold_all_reg_t; -/** Type of imm_i2c_iso register - * need_des - */ typedef union { struct { - uint32_t reserved_0:30; - /** tie_high_i2c_iso_en : WT; bitpos: [30]; default: 0; - * need_des - */ - uint32_t tie_high_i2c_iso_en:1; - /** tie_low_i2c_iso_en : WT; bitpos: [31]; default: 0; - * need_des - */ - uint32_t tie_low_i2c_iso_en:1; + uint32_t reserved0 : 30; + uint32_t tie_high_i2c_iso_en: 1; + uint32_t tie_low_i2c_iso_en : 1; }; uint32_t val; -} pmu_imm_i2c_iso_reg_t; +} pmu_imm_i2c_isolate_reg_t; + +typedef struct pmu_imm_hw_regmap_t{ + pmu_imm_hp_clk_power_reg_t clk_power; + pmu_imm_sleep_sysclk_reg_t sleep_sysclk; + pmu_imm_hp_func_icg_reg_t hp_func_icg; + pmu_imm_hp_apb_icg_reg_t hp_apb_icg; + pmu_imm_modem_icg_reg_t modem_icg; + pmu_imm_lp_icg_reg_t lp_icg; + pmu_imm_pad_hold_all_reg_t pad_hold_all; + pmu_imm_i2c_isolate_reg_t i2c_iso; +} pmu_imm_hw_regmap_t; -/** Type of power_wait_timer0 register - * need_des - */ typedef union { struct { - uint32_t reserved_0:5; - /** dg_hp_powerdown_timer : R/W; bitpos: [13:5]; default: 255; - * need_des - */ - uint32_t dg_hp_powerdown_timer:9; - /** dg_hp_powerup_timer : R/W; bitpos: [22:14]; default: 255; - * need_des - */ - uint32_t dg_hp_powerup_timer:9; - /** dg_hp_pd_wait_timer : R/W; bitpos: [31:23]; default: 255; - * need_des - */ - uint32_t dg_hp_pd_wait_timer:9; + uint32_t reserved0 : 5; + uint32_t powerdown_timer: 9; + uint32_t powerup_timer : 9; + uint32_t wait_timer : 9; }; uint32_t val; } pmu_power_wait_timer0_reg_t; -/** Type of power_wait_timer1 register - * need_des - */ typedef union { struct { - uint32_t reserved_0:9; - /** dg_lp_powerdown_timer : R/W; bitpos: [15:9]; default: 63; - * need_des - */ - uint32_t dg_lp_powerdown_timer:7; - /** dg_lp_powerup_timer : R/W; bitpos: [22:16]; default: 63; - * need_des - */ - uint32_t dg_lp_powerup_timer:7; - /** dg_lp_pd_wait_timer : R/W; bitpos: [31:23]; default: 255; - * need_des - */ - uint32_t dg_lp_pd_wait_timer:9; + uint32_t reserved0 : 9; + uint32_t powerdown_timer: 7; + uint32_t powerup_timer : 7; + uint32_t wait_timer : 9; }; uint32_t val; } pmu_power_wait_timer1_reg_t; -/** Type of power_wait_timer2 register - * need_des - */ -typedef union { - struct { - /** dg_lp_iso_wait_timer : R/W; bitpos: [7:0]; default: 255; - * need_des - */ - uint32_t dg_lp_iso_wait_timer:8; - /** dg_lp_rst_wait_timer : R/W; bitpos: [15:8]; default: 255; - * need_des - */ - uint32_t dg_lp_rst_wait_timer:8; - /** dg_hp_iso_wait_timer : R/W; bitpos: [23:16]; default: 255; - * need_des - */ - uint32_t dg_hp_iso_wait_timer:8; - /** dg_hp_rst_wait_timer : R/W; bitpos: [31:24]; default: 255; - * need_des - */ - uint32_t dg_hp_rst_wait_timer:8; - }; - uint32_t val; -} pmu_power_wait_timer2_reg_t; - -/** Type of power_pd_top_cntl register - * need_des - */ -typedef union { - struct { - /** force_top_reset : R/W; bitpos: [0]; default: 0; - * need_des - */ - uint32_t force_top_reset:1; - /** force_top_iso : R/W; bitpos: [1]; default: 0; - * need_des - */ - uint32_t force_top_iso:1; - /** force_top_pu : R/W; bitpos: [2]; default: 1; - * need_des - */ - uint32_t force_top_pu:1; - /** force_top_no_reset : R/W; bitpos: [3]; default: 1; - * need_des - */ - uint32_t force_top_no_reset:1; - /** force_top_no_iso : R/W; bitpos: [4]; default: 1; - * need_des - */ - uint32_t force_top_no_iso:1; - /** force_top_pd : R/W; bitpos: [5]; default: 0; - * need_des - */ - uint32_t force_top_pd:1; - /** pd_top_mask : R/W; bitpos: [10:6]; default: 0; - * need_des - */ - uint32_t pd_top_mask:5; - uint32_t reserved_11:16; - /** pd_top_pd_mask : R/W; bitpos: [31:27]; default: 0; - * need_des - */ - uint32_t pd_top_pd_mask:5; - }; - uint32_t val; -} pmu_power_pd_top_cntl_reg_t; - -/** Type of power_pd_hpaon_cntl register - * need_des - */ -typedef union { - struct { - /** force_hp_aon_reset : R/W; bitpos: [0]; default: 0; - * need_des - */ - uint32_t force_hp_aon_reset:1; - /** force_hp_aon_iso : R/W; bitpos: [1]; default: 0; - * need_des - */ - uint32_t force_hp_aon_iso:1; - /** force_hp_aon_pu : R/W; bitpos: [2]; default: 1; - * need_des - */ - uint32_t force_hp_aon_pu:1; - /** force_hp_aon_no_reset : R/W; bitpos: [3]; default: 1; - * need_des - */ - uint32_t force_hp_aon_no_reset:1; - /** force_hp_aon_no_iso : R/W; bitpos: [4]; default: 1; - * need_des - */ - uint32_t force_hp_aon_no_iso:1; - /** force_hp_aon_pd : R/W; bitpos: [5]; default: 0; - * need_des - */ - uint32_t force_hp_aon_pd:1; - /** pd_hp_aon_mask : R/W; bitpos: [10:6]; default: 0; - * need_des - */ - uint32_t pd_hp_aon_mask:5; - uint32_t reserved_11:16; - /** pd_hp_aon_pd_mask : R/W; bitpos: [31:27]; default: 0; - * need_des - */ - uint32_t pd_hp_aon_pd_mask:5; - }; - uint32_t val; -} pmu_power_pd_hpaon_cntl_reg_t; - -/** Type of power_pd_hpcpu_cntl register - * need_des - */ -typedef union { - struct { - /** force_hp_cpu_reset : R/W; bitpos: [0]; default: 0; - * need_des - */ - uint32_t force_hp_cpu_reset:1; - /** force_hp_cpu_iso : R/W; bitpos: [1]; default: 0; - * need_des - */ - uint32_t force_hp_cpu_iso:1; - /** force_hp_cpu_pu : R/W; bitpos: [2]; default: 1; - * need_des - */ - uint32_t force_hp_cpu_pu:1; - /** force_hp_cpu_no_reset : R/W; bitpos: [3]; default: 1; - * need_des - */ - uint32_t force_hp_cpu_no_reset:1; - /** force_hp_cpu_no_iso : R/W; bitpos: [4]; default: 1; - * need_des - */ - uint32_t force_hp_cpu_no_iso:1; - /** force_hp_cpu_pd : R/W; bitpos: [5]; default: 0; - * need_des - */ - uint32_t force_hp_cpu_pd:1; - /** pd_hp_cpu_mask : R/W; bitpos: [10:6]; default: 0; - * need_des - */ - uint32_t pd_hp_cpu_mask:5; - uint32_t reserved_11:16; - /** pd_hp_cpu_pd_mask : R/W; bitpos: [31:27]; default: 0; - * need_des - */ - uint32_t pd_hp_cpu_pd_mask:5; - }; - uint32_t val; -} pmu_power_pd_hpcpu_cntl_reg_t; - -/** Type of power_pd_hpperi_reserve register - * need_des - */ -typedef union { - struct { - /** force_hp_peri_reset : R/W; bitpos: [0]; default: 0; - * need_des - */ - uint32_t force_hp_peri_reset:1; - /** force_hp_peri_iso : R/W; bitpos: [1]; default: 0; - * need_des - */ - uint32_t force_hp_peri_iso:1; - /** force_hp_peri_pu : R/W; bitpos: [2]; default: 1; - * need_des - */ - uint32_t force_hp_peri_pu:1; - /** force_hp_peri_no_reset : R/W; bitpos: [3]; default: 1; - * need_des - */ - uint32_t force_hp_peri_no_reset:1; - /** force_hp_peri_no_iso : R/W; bitpos: [4]; default: 1; - * need_des - */ - uint32_t force_hp_peri_no_iso:1; - /** force_hp_peri_pd : R/W; bitpos: [5]; default: 0; - * need_des - */ - uint32_t force_hp_peri_pd:1; - /** pd_hp_peri_mask : R/W; bitpos: [10:6]; default: 0; - * need_des - */ - uint32_t pd_hp_peri_mask:5; - uint32_t reserved_11:16; - /** pd_hp_peri_pd_mask : R/W; bitpos: [31:27]; default: 0; - * need_des - */ - uint32_t pd_hp_peri_pd_mask:5; - }; - uint32_t val; -} pmu_power_pd_hpperi_reserve_reg_t; - -/** Type of power_pd_hpwifi_cntl register - * need_des - */ typedef union { struct { - /** force_hp_wifi_reset : R/W; bitpos: [0]; default: 0; - * need_des - */ - uint32_t force_hp_wifi_reset:1; - /** force_hp_wifi_iso : R/W; bitpos: [1]; default: 0; - * need_des - */ - uint32_t force_hp_wifi_iso:1; - /** force_hp_wifi_pu : R/W; bitpos: [2]; default: 1; - * need_des - */ - uint32_t force_hp_wifi_pu:1; - /** force_hp_wifi_no_reset : R/W; bitpos: [3]; default: 1; - * need_des - */ - uint32_t force_hp_wifi_no_reset:1; - /** force_hp_wifi_no_iso : R/W; bitpos: [4]; default: 1; - * need_des - */ - uint32_t force_hp_wifi_no_iso:1; - /** force_hp_wifi_pd : R/W; bitpos: [5]; default: 0; - * need_des - */ - uint32_t force_hp_wifi_pd:1; - /** pd_hp_wifi_mask : R/W; bitpos: [10:6]; default: 0; - * need_des - */ - uint32_t pd_hp_wifi_mask:5; - uint32_t reserved_11:16; - /** pd_hp_wifi_pd_mask : R/W; bitpos: [31:27]; default: 0; - * need_des - */ - uint32_t pd_hp_wifi_pd_mask:5; + uint32_t force_reset : 1; + uint32_t force_iso : 1; + uint32_t force_pu : 1; + uint32_t force_no_reset: 1; + uint32_t force_no_iso : 1; + uint32_t force_pd : 1; + uint32_t mask : 5; /* Invalid of lp peripherals */ + uint32_t reserved0 : 16; /* Invalid of lp peripherals */ + uint32_t pd_mask : 5; /* Invalid of lp peripherals */ }; uint32_t val; -} pmu_power_pd_hpwifi_cntl_reg_t; +} pmu_power_domain_cntl_reg_t; -/** Type of power_pd_lpperi_cntl register - * need_des - */ -typedef union { - struct { - /** force_lp_peri_reset : R/W; bitpos: [0]; default: 0; - * need_des - */ - uint32_t force_lp_peri_reset:1; - /** force_lp_peri_iso : R/W; bitpos: [1]; default: 0; - * need_des - */ - uint32_t force_lp_peri_iso:1; - /** force_lp_peri_pu : R/W; bitpos: [2]; default: 1; - * need_des - */ - uint32_t force_lp_peri_pu:1; - /** force_lp_peri_no_reset : R/W; bitpos: [3]; default: 1; - * need_des - */ - uint32_t force_lp_peri_no_reset:1; - /** force_lp_peri_no_iso : R/W; bitpos: [4]; default: 1; - * need_des - */ - uint32_t force_lp_peri_no_iso:1; - /** force_lp_peri_pd : R/W; bitpos: [5]; default: 0; - * need_des - */ - uint32_t force_lp_peri_pd:1; - uint32_t reserved_6:26; - }; - uint32_t val; -} pmu_power_pd_lpperi_cntl_reg_t; - -/** Type of power_pd_mem_cntl register - * need_des - */ typedef union { struct { - /** force_hp_mem_iso : R/W; bitpos: [3:0]; default: 0; - * need_des - */ - uint32_t force_hp_mem_iso:4; - /** force_hp_mem_pd : R/W; bitpos: [7:4]; default: 0; - * need_des - */ - uint32_t force_hp_mem_pd:4; - uint32_t reserved_8:16; - /** force_hp_mem_no_iso : R/W; bitpos: [27:24]; default: 15; - * need_des - */ - uint32_t force_hp_mem_no_iso:4; - /** force_hp_mem_pu : R/W; bitpos: [31:28]; default: 15; - * need_des - */ - uint32_t force_hp_mem_pu:4; + uint32_t force_hp_mem_iso : 4; + uint32_t force_hp_mem_pd : 4; + uint32_t reserved0 : 16; + uint32_t force_hp_mem_no_iso: 4; + uint32_t force_hp_mem_pu : 4; }; uint32_t val; -} pmu_power_pd_mem_cntl_reg_t; +} pmu_power_memory_cntl_reg_t; -/** Type of power_pd_mem_mask register - * need_des - */ typedef union { struct { - /** pd_hp_mem2_pd_mask : R/W; bitpos: [4:0]; default: 0; - * need_des - */ - uint32_t pd_hp_mem2_pd_mask:5; - /** pd_hp_mem1_pd_mask : R/W; bitpos: [9:5]; default: 0; - * need_des - */ - uint32_t pd_hp_mem1_pd_mask:5; - /** pd_hp_mem0_pd_mask : R/W; bitpos: [14:10]; default: 0; - * need_des - */ - uint32_t pd_hp_mem0_pd_mask:5; - uint32_t reserved_15:2; - /** pd_hp_mem2_mask : R/W; bitpos: [21:17]; default: 0; - * need_des - */ - uint32_t pd_hp_mem2_mask:5; - /** pd_hp_mem1_mask : R/W; bitpos: [26:22]; default: 0; - * need_des - */ - uint32_t pd_hp_mem1_mask:5; - /** pd_hp_mem0_mask : R/W; bitpos: [31:27]; default: 0; - * need_des - */ - uint32_t pd_hp_mem0_mask:5; + uint32_t mem2_pd_mask: 5; + uint32_t mem1_pd_mask: 5; + uint32_t mem0_pd_mask: 5; + uint32_t reserved0 : 2; + uint32_t mem2_mask : 5; + uint32_t mem1_mask : 5; + uint32_t mem0_mask : 5; }; uint32_t val; -} pmu_power_pd_mem_mask_reg_t; +} pmu_power_memory_mask_reg_t; -/** Type of power_hp_pad register - * need_des - */ typedef union { struct { - /** force_hp_pad_no_iso_all : R/W; bitpos: [0]; default: 0; - * need_des - */ - uint32_t force_hp_pad_no_iso_all:1; - /** force_hp_pad_iso_all : R/W; bitpos: [1]; default: 0; - * need_des - */ - uint32_t force_hp_pad_iso_all:1; - uint32_t reserved_2:30; + uint32_t force_hp_pad_no_iso_all: 1; + uint32_t force_hp_pad_iso_all : 1; + uint32_t reserved0 : 30; }; uint32_t val; } pmu_power_hp_pad_reg_t; -/** Type of power_flash1p8_ldo register - * need_des - */ typedef union { struct { - /** flash1p8_ldo_rdy : RO; bitpos: [0]; default: 1; - * need_des - */ - uint32_t flash1p8_ldo_rdy:1; - /** flash1p8_sw_en_xpd : R/W; bitpos: [1]; default: 0; - * need_des - */ - uint32_t flash1p8_sw_en_xpd:1; - /** flash1p8_sw_en_thru : R/W; bitpos: [2]; default: 0; - * need_des - */ - uint32_t flash1p8_sw_en_thru:1; - /** flash1p8_sw_en_standby : R/W; bitpos: [3]; default: 0; - * need_des - */ - uint32_t flash1p8_sw_en_standby:1; - /** flash1p8_sw_en_power_adjust : R/W; bitpos: [4]; default: 0; - * need_des - */ - uint32_t flash1p8_sw_en_power_adjust:1; - /** flash1p8_sw_en_endet : R/W; bitpos: [5]; default: 0; - * need_des - */ - uint32_t flash1p8_sw_en_endet:1; - uint32_t reserved_6:16; - /** flash1p8_bypass_ldo_rdy : R/W; bitpos: [22]; default: 0; - * need_des - */ - uint32_t flash1p8_bypass_ldo_rdy:1; - /** flash1p8_xpd : R/W; bitpos: [23]; default: 0; - * need_des - */ - uint32_t flash1p8_xpd:1; - /** flash1p8_thru : R/W; bitpos: [24]; default: 1; - * need_des - */ - uint32_t flash1p8_thru:1; - /** flash1p8_standby : R/W; bitpos: [25]; default: 0; - * need_des - */ - uint32_t flash1p8_standby:1; - /** flash1p8_power_adjust : R/W; bitpos: [30:26]; default: 0; - * need_des - */ - uint32_t flash1p8_power_adjust:5; - /** flash1p8_endet : R/W; bitpos: [31]; default: 0; - * need_des - */ - uint32_t flash1p8_endet:1; + uint32_t reserved0 : 18; + uint32_t pwr_wait : 11; + uint32_t pwr_sw : 2; + uint32_t pwr_sel_sw: 1; }; uint32_t val; -} pmu_power_flash1p8_ldo_reg_t; +} pmu_power_vdd_spi_cntl_reg_t; -/** Type of power_flash1p2_ldo register - * need_des - */ typedef union { struct { - /** flash1p2_ldo_rdy : RO; bitpos: [0]; default: 1; - * need_des - */ - uint32_t flash1p2_ldo_rdy:1; - /** flash1p2_sw_en_xpd : R/W; bitpos: [1]; default: 0; - * need_des - */ - uint32_t flash1p2_sw_en_xpd:1; - /** flash1p2_sw_en_thru : R/W; bitpos: [2]; default: 0; - * need_des - */ - uint32_t flash1p2_sw_en_thru:1; - /** flash1p2_sw_en_standby : R/W; bitpos: [3]; default: 0; - * need_des - */ - uint32_t flash1p2_sw_en_standby:1; - /** flash1p2_sw_en_power_adjust : R/W; bitpos: [4]; default: 0; - * need_des - */ - uint32_t flash1p2_sw_en_power_adjust:1; - /** flash1p2_sw_en_endet : R/W; bitpos: [5]; default: 0; - * need_des - */ - uint32_t flash1p2_sw_en_endet:1; - uint32_t reserved_6:16; - /** flash1p2_bypass_ldo_rdy : R/W; bitpos: [22]; default: 0; - * need_des - */ - uint32_t flash1p2_bypass_ldo_rdy:1; - /** flash1p2_xpd : R/W; bitpos: [23]; default: 0; - * need_des - */ - uint32_t flash1p2_xpd:1; - /** flash1p2_thru : R/W; bitpos: [24]; default: 1; - * need_des - */ - uint32_t flash1p2_thru:1; - /** flash1p2_standby : R/W; bitpos: [25]; default: 0; - * need_des - */ - uint32_t flash1p2_standby:1; - /** flash1p2_power_adjust : R/W; bitpos: [30:26]; default: 0; - * need_des - */ - uint32_t flash1p2_power_adjust:5; - /** flash1p2_endet : R/W; bitpos: [31]; default: 0; - * need_des - */ - uint32_t flash1p2_endet:1; + uint32_t wait_xtal_stable: 16; + uint32_t wait_pll_stable : 16; }; uint32_t val; -} pmu_power_flash1p2_ldo_reg_t; +} pmu_power_clk_wait_cntl_reg_t; -/** Type of power_vdd_flash register - * need_des - */ -typedef union { - struct { - uint32_t reserved_0:22; - /** flash_ldo_sw_en_tiel : R/W; bitpos: [22]; default: 0; - * need_des - */ - uint32_t flash_ldo_sw_en_tiel:1; - /** flash_ldo_power_sel : R/W; bitpos: [23]; default: 0; - * need_des - */ - uint32_t flash_ldo_power_sel:1; - /** flash_ldo_sw_en_power_sel : R/W; bitpos: [24]; default: 0; - * need_des - */ - uint32_t flash_ldo_sw_en_power_sel:1; - /** flash_ldo_wait_target : R/W; bitpos: [28:25]; default: 15; - * need_des - */ - uint32_t flash_ldo_wait_target:4; - /** flash_ldo_tiel_en : R/W; bitpos: [29]; default: 0; - * need_des - */ - uint32_t flash_ldo_tiel_en:1; - /** flash_ldo_tiel : R/W; bitpos: [30]; default: 0; - * need_des - */ - uint32_t flash_ldo_tiel:1; - /** flash_ldo_sw_update : WT; bitpos: [31]; default: 0; - * need_des - */ - uint32_t flash_ldo_sw_update:1; - }; - uint32_t val; -} pmu_power_vdd_flash_reg_t; +typedef struct pmu_power_hw_regmap_t{ + pmu_power_wait_timer0_reg_t wait_timer0; + pmu_power_wait_timer1_reg_t wait_timer1; + pmu_power_domain_cntl_reg_t hp_pd[5]; + pmu_power_domain_cntl_reg_t lp_peri; + pmu_power_memory_cntl_reg_t mem_cntl; + pmu_power_memory_mask_reg_t mem_mask; + pmu_power_hp_pad_reg_t hp_pad; + pmu_power_vdd_spi_cntl_reg_t vdd_spi; + pmu_power_clk_wait_cntl_reg_t clk_wait; +} pmu_power_hw_regmap_t; -/** Type of power_io_ldo register - * need_des - */ typedef union { struct { - /** io_ldo_rdy : RO; bitpos: [0]; default: 1; - * need_des - */ - uint32_t io_ldo_rdy:1; - /** io_sw_en_xpd : R/W; bitpos: [1]; default: 0; - * need_des - */ - uint32_t io_sw_en_xpd:1; - uint32_t reserved_2:1; - /** io_sw_en_thru : R/W; bitpos: [3]; default: 0; - * need_des - */ - uint32_t io_sw_en_thru:1; - /** io_sw_en_standby : R/W; bitpos: [4]; default: 0; - * need_des - */ - uint32_t io_sw_en_standby:1; - /** io_sw_en_power_adjust : R/W; bitpos: [5]; default: 0; - * need_des - */ - uint32_t io_sw_en_power_adjust:1; - /** io_sw_en_endet : R/W; bitpos: [6]; default: 0; - * need_des - */ - uint32_t io_sw_en_endet:1; - uint32_t reserved_7:15; - /** io_bypass_ldo_rdy : R/W; bitpos: [22]; default: 0; - * need_des - */ - uint32_t io_bypass_ldo_rdy:1; - /** io_xpd : R/W; bitpos: [23]; default: 0; - * need_des - */ - uint32_t io_xpd:1; - /** io_thru : R/W; bitpos: [24]; default: 1; - * need_des - */ - uint32_t io_thru:1; - /** io_standby : R/W; bitpos: [25]; default: 0; - * need_des - */ - uint32_t io_standby:1; - /** io_power_adjust : R/W; bitpos: [30:26]; default: 0; - * need_des - */ - uint32_t io_power_adjust:5; - /** io_endet : R/W; bitpos: [31]; default: 0; - * need_des - */ - uint32_t io_endet:1; - }; - uint32_t val; -} pmu_power_io_ldo_reg_t; - -/** Type of power_vdd_io register - * need_des - */ -typedef union { - struct { - uint32_t reserved_0:23; - /** io_ldo_power_sel : R/W; bitpos: [23]; default: 0; - * need_des - */ - uint32_t io_ldo_power_sel:1; - /** io_ldo_sw_en_power_sel : R/W; bitpos: [24]; default: 0; - * need_des - */ - uint32_t io_ldo_sw_en_power_sel:1; - uint32_t reserved_25:7; - }; - uint32_t val; -} pmu_power_vdd_io_reg_t; - -/** Type of power_ck_wait_cntl register - * need_des - */ -typedef union { - struct { - /** wait_xtl_stable : R/W; bitpos: [15:0]; default: 256; - * need_des - */ - uint32_t wait_xtl_stable:16; - /** wait_pll_stable : R/W; bitpos: [31:16]; default: 256; - * need_des - */ - uint32_t wait_pll_stable:16; - }; - uint32_t val; -} pmu_power_ck_wait_cntl_reg_t; - -/** Type of slp_wakeup_cntl0 register - * need_des - */ -typedef union { - struct { - uint32_t reserved_0:31; - /** sleep_req : WT; bitpos: [31]; default: 0; - * need_des - */ - uint32_t sleep_req:1; + uint32_t reserved0: 31; + uint32_t sleep_req: 1; }; uint32_t val; } pmu_slp_wakeup_cntl0_reg_t; -/** Type of slp_wakeup_cntl1 register - * need_des - */ typedef union { struct { - /** sleep_reject_ena : R/W; bitpos: [30:0]; default: 0; - * need_des - */ - uint32_t sleep_reject_ena:31; - /** slp_reject_en : R/W; bitpos: [31]; default: 0; - * need_des - */ - uint32_t slp_reject_en:1; + uint32_t sleep_reject_ena: 31; + uint32_t slp_reject_en : 1; }; uint32_t val; } pmu_slp_wakeup_cntl1_reg_t; -/** Type of slp_wakeup_cntl2 register - * need_des - */ typedef union { struct { - /** wakeup_ena : R/W; bitpos: [31:0]; default: 0; - * need_des - */ - uint32_t wakeup_ena:32; - }; - uint32_t val; -} pmu_slp_wakeup_cntl2_reg_t; - -/** Type of slp_wakeup_cntl3 register - * need_des - */ -typedef union { - struct { - /** lp_min_slp_val : R/W; bitpos: [7:0]; default: 0; - * need_des - */ - uint32_t lp_min_slp_val:8; - /** hp_min_slp_val : R/W; bitpos: [15:8]; default: 0; - * need_des - */ - uint32_t hp_min_slp_val:8; - /** sleep_prt_sel : R/W; bitpos: [17:16]; default: 0; - * need_des - */ - uint32_t sleep_prt_sel:2; - uint32_t reserved_18:14; + uint32_t lp_min_slp_val: 8; + uint32_t hp_min_slp_val: 8; + uint32_t sleep_prt_sel : 2; + uint32_t reserved0 : 14; }; uint32_t val; } pmu_slp_wakeup_cntl3_reg_t; -/** Type of slp_wakeup_cntl4 register - * need_des - */ typedef union { struct { - uint32_t reserved_0:31; - /** slp_reject_cause_clr : WT; bitpos: [31]; default: 0; - * need_des - */ - uint32_t slp_reject_cause_clr:1; + uint32_t reserved0 : 31; + uint32_t slp_reject_cause_clr: 1; }; uint32_t val; } pmu_slp_wakeup_cntl4_reg_t; -/** Type of slp_wakeup_cntl5 register - * need_des - */ typedef union { struct { - /** modem_wait_target : R/W; bitpos: [19:0]; default: 128; - * need_des - */ - uint32_t modem_wait_target:20; - uint32_t reserved_20:4; - /** lp_ana_wait_target : R/W; bitpos: [31:24]; default: 1; - * need_des - */ - uint32_t lp_ana_wait_target:8; + uint32_t modem_wait_target : 20; + uint32_t reserved0 : 4; + uint32_t lp_ana_wait_target: 8; }; uint32_t val; } pmu_slp_wakeup_cntl5_reg_t; -/** Type of slp_wakeup_cntl6 register - * need_des - */ typedef union { struct { - /** soc_wakeup_wait : R/W; bitpos: [19:0]; default: 128; - * need_des - */ - uint32_t soc_wakeup_wait:20; - uint32_t reserved_20:10; - /** soc_wakeup_wait_cfg : R/W; bitpos: [31:30]; default: 0; - * need_des - */ - uint32_t soc_wakeup_wait_cfg:2; + uint32_t soc_wakeup_wait : 20; + uint32_t reserved0 : 10; + uint32_t soc_wakeup_wait_cfg: 2; }; uint32_t val; } pmu_slp_wakeup_cntl6_reg_t; -/** Type of slp_wakeup_cntl7 register - * need_des - */ typedef union { struct { - uint32_t reserved_0:15; - /** ana_wait_clk_sel : R/W; bitpos: [15]; default: 0; - * need_des - */ - uint32_t ana_wait_clk_sel:1; - /** ana_wait_target : R/W; bitpos: [31:16]; default: 1; - * need_des - */ - uint32_t ana_wait_target:16; + uint32_t reserved0 : 16; + uint32_t ana_wait_target: 16; }; uint32_t val; } pmu_slp_wakeup_cntl7_reg_t; -/** Type of slp_wakeup_status0 register - * need_des - */ -typedef union { - struct { - /** wakeup_cause : RO; bitpos: [31:0]; default: 0; - * need_des - */ - uint32_t wakeup_cause:32; - }; - uint32_t val; -} pmu_slp_wakeup_status0_reg_t; - -/** Type of slp_wakeup_status1 register - * need_des - */ -typedef union { - struct { - /** reject_cause : RO; bitpos: [31:0]; default: 0; - * need_des - */ - uint32_t reject_cause:32; - }; - uint32_t val; -} pmu_slp_wakeup_status1_reg_t; +typedef struct pmu_wakeup_hw_regmap_t{ + pmu_slp_wakeup_cntl0_reg_t cntl0; + pmu_slp_wakeup_cntl1_reg_t cntl1; + uint32_t cntl2; + pmu_slp_wakeup_cntl3_reg_t cntl3; + pmu_slp_wakeup_cntl4_reg_t cntl4; + pmu_slp_wakeup_cntl5_reg_t cntl5; + pmu_slp_wakeup_cntl6_reg_t cntl6; + pmu_slp_wakeup_cntl7_reg_t cntl7; + uint32_t status0; + uint32_t status1; +} pmu_wakeup_hw_regmap_t; -/** Type of hp_ck_poweron register - * need_des - */ typedef union { struct { - /** i2c_por_wait_target : R/W; bitpos: [7:0]; default: 50; - * need_des - */ - uint32_t i2c_por_wait_target:8; - uint32_t reserved_8:24; + uint32_t i2c_por_wait_target: 8; + uint32_t reserved0 : 24; }; uint32_t val; -} pmu_hp_ck_poweron_reg_t; +} pmu_hp_clk_poweron_reg_t; -/** Type of hp_ck_cntl register - * need_des - */ typedef union { struct { - /** modify_icg_cntl_wait : R/W; bitpos: [7:0]; default: 10; - * need_des - */ - uint32_t modify_icg_cntl_wait:8; - /** switch_icg_cntl_wait : R/W; bitpos: [15:8]; default: 10; - * need_des - */ - uint32_t switch_icg_cntl_wait:8; - uint32_t reserved_16:16; + uint32_t modify_icg_cntl_wait: 8; + uint32_t switch_icg_cntl_wait: 8; + uint32_t reserved0 : 16; }; uint32_t val; -} pmu_hp_ck_cntl_reg_t; +} pmu_hp_clk_cntl_reg_t; -/** Type of por_status register - * need_des - */ typedef union { struct { - uint32_t reserved_0:31; - /** por_done : RO; bitpos: [31]; default: 0; - * need_des - */ - uint32_t por_done:1; + uint32_t reserved0: 31; + uint32_t por_done : 1; }; uint32_t val; } pmu_por_status_reg_t; -/** Type of rf_pwc register - * need_des - */ typedef union { struct { - uint32_t reserved_0:26; - /** xpd_force_rftx : R/W; bitpos: [26]; default: 0; - * need_des - */ - uint32_t xpd_force_rftx:1; - /** xpd_perif_i2c : R/W; bitpos: [27]; default: 1; - * need_des - */ - uint32_t xpd_perif_i2c:1; - /** xpd_rftx_i2c : R/W; bitpos: [28]; default: 0; - * need_des - */ - uint32_t xpd_rftx_i2c:1; - /** xpd_rfrx_i2c : R/W; bitpos: [29]; default: 0; - * need_des - */ - uint32_t xpd_rfrx_i2c:1; - /** xpd_rfpll : R/W; bitpos: [30]; default: 0; - * need_des - */ - uint32_t xpd_rfpll:1; - /** xpd_force_rfpll : R/W; bitpos: [31]; default: 0; - * need_des - */ - uint32_t xpd_force_rfpll:1; + uint32_t reserved0 : 27; + uint32_t xpd_perif_i2c : 1; + uint32_t xpd_rftx_i2c : 1; + uint32_t xpd_rfrx_i2c : 1; + uint32_t xpd_rfpll : 1; + uint32_t xpd_force_rfpll: 1; }; uint32_t val; } pmu_rf_pwc_reg_t; -/** Type of vddbat_cfg register - * need_des - */ typedef union { struct { - /** vddbat_mode : RO; bitpos: [1:0]; default: 0; - * need_des - */ - uint32_t vddbat_mode:2; - uint32_t reserved_2:29; - /** vddbat_sw_update : WT; bitpos: [31]; default: 0; - * need_des - */ - uint32_t vddbat_sw_update:1; + uint32_t ana_vddbat_mode : 2; + uint32_t reserved2 : 29; + uint32_t vddbat_sw_update : 1; }; uint32_t val; } pmu_vddbat_cfg_reg_t; -/** Type of backup_cfg register - * need_des - */ typedef union { struct { - uint32_t reserved_0:31; - /** backup_sys_clk_no_div : R/W; bitpos: [31]; default: 1; - * need_des - */ - uint32_t backup_sys_clk_no_div:1; + uint32_t reserved0 : 31; + uint32_t backup_sysclk_nodiv: 1; }; uint32_t val; } pmu_backup_cfg_reg_t; -/** Type of int_raw register - * need_des - */ -typedef union { - struct { - uint32_t reserved_0:27; - /** lp_cpu_exc_int_raw : R/WTC/SS; bitpos: [27]; default: 0; - * need_des - */ - uint32_t lp_cpu_exc_int_raw:1; - /** sdio_idle_int_raw : R/WTC/SS; bitpos: [28]; default: 0; - * need_des - */ - uint32_t sdio_idle_int_raw:1; - /** sw_int_raw : R/WTC/SS; bitpos: [29]; default: 0; - * need_des - */ - uint32_t sw_int_raw:1; - /** soc_sleep_reject_int_raw : R/WTC/SS; bitpos: [30]; default: 0; - * need_des - */ - uint32_t soc_sleep_reject_int_raw:1; - /** soc_wakeup_int_raw : R/WTC/SS; bitpos: [31]; default: 0; - * need_des - */ - uint32_t soc_wakeup_int_raw:1; - }; - uint32_t val; -} pmu_int_raw_reg_t; - -/** Type of hp_int_st register - * need_des - */ -typedef union { - struct { - uint32_t reserved_0:27; - /** lp_cpu_exc_int_st : RO; bitpos: [27]; default: 0; - * need_des - */ - uint32_t lp_cpu_exc_int_st:1; - /** sdio_idle_int_st : RO; bitpos: [28]; default: 0; - * need_des - */ - uint32_t sdio_idle_int_st:1; - /** sw_int_st : RO; bitpos: [29]; default: 0; - * need_des - */ - uint32_t sw_int_st:1; - /** soc_sleep_reject_int_st : RO; bitpos: [30]; default: 0; - * need_des - */ - uint32_t soc_sleep_reject_int_st:1; - /** soc_wakeup_int_st : RO; bitpos: [31]; default: 0; - * need_des - */ - uint32_t soc_wakeup_int_st:1; - }; - uint32_t val; -} pmu_hp_int_st_reg_t; - -/** Type of hp_int_ena register - * need_des - */ -typedef union { - struct { - uint32_t reserved_0:27; - /** lp_cpu_exc_int_ena : R/W; bitpos: [27]; default: 0; - * need_des - */ - uint32_t lp_cpu_exc_int_ena:1; - /** sdio_idle_int_ena : R/W; bitpos: [28]; default: 0; - * need_des - */ - uint32_t sdio_idle_int_ena:1; - /** sw_int_ena : R/W; bitpos: [29]; default: 0; - * need_des - */ - uint32_t sw_int_ena:1; - /** soc_sleep_reject_int_ena : R/W; bitpos: [30]; default: 0; - * need_des - */ - uint32_t soc_sleep_reject_int_ena:1; - /** soc_wakeup_int_ena : R/W; bitpos: [31]; default: 0; - * need_des - */ - uint32_t soc_wakeup_int_ena:1; - }; - uint32_t val; -} pmu_hp_int_ena_reg_t; - -/** Type of hp_int_clr register - * need_des - */ -typedef union { - struct { - uint32_t reserved_0:27; - /** lp_cpu_exc_int_clr : WT; bitpos: [27]; default: 0; - * need_des - */ - uint32_t lp_cpu_exc_int_clr:1; - /** sdio_idle_int_clr : WT; bitpos: [28]; default: 0; - * need_des - */ - uint32_t sdio_idle_int_clr:1; - /** sw_int_clr : WT; bitpos: [29]; default: 0; - * need_des - */ - uint32_t sw_int_clr:1; - /** soc_sleep_reject_int_clr : WT; bitpos: [30]; default: 0; - * need_des - */ - uint32_t soc_sleep_reject_int_clr:1; - /** soc_wakeup_int_clr : WT; bitpos: [31]; default: 0; - * need_des - */ - uint32_t soc_wakeup_int_clr:1; - }; - uint32_t val; -} pmu_hp_int_clr_reg_t; - -/** Type of lp_int_raw register - * need_des - */ -typedef union { - struct { - uint32_t reserved_0:20; - /** lp_cpu_wakeup_int_raw : R/WTC/SS; bitpos: [20]; default: 0; - * need_des - */ - uint32_t lp_cpu_wakeup_int_raw:1; - /** modem_switch_active_end_int_raw : R/WTC/SS; bitpos: [21]; default: 0; - * need_des - */ - uint32_t modem_switch_active_end_int_raw:1; - /** sleep_switch_active_end_int_raw : R/WTC/SS; bitpos: [22]; default: 0; - * need_des - */ - uint32_t sleep_switch_active_end_int_raw:1; - /** sleep_switch_modem_end_int_raw : R/WTC/SS; bitpos: [23]; default: 0; - * need_des - */ - uint32_t sleep_switch_modem_end_int_raw:1; - /** modem_switch_sleep_end_int_raw : R/WTC/SS; bitpos: [24]; default: 0; - * need_des - */ - uint32_t modem_switch_sleep_end_int_raw:1; - /** active_switch_sleep_end_int_raw : R/WTC/SS; bitpos: [25]; default: 0; - * need_des - */ - uint32_t active_switch_sleep_end_int_raw:1; - /** modem_switch_active_start_int_raw : R/WTC/SS; bitpos: [26]; default: 0; - * need_des - */ - uint32_t modem_switch_active_start_int_raw:1; - /** sleep_switch_active_start_int_raw : R/WTC/SS; bitpos: [27]; default: 0; - * need_des - */ - uint32_t sleep_switch_active_start_int_raw:1; - /** sleep_switch_modem_start_int_raw : R/WTC/SS; bitpos: [28]; default: 0; - * need_des - */ - uint32_t sleep_switch_modem_start_int_raw:1; - /** modem_switch_sleep_start_int_raw : R/WTC/SS; bitpos: [29]; default: 0; - * need_des - */ - uint32_t modem_switch_sleep_start_int_raw:1; - /** active_switch_sleep_start_int_raw : R/WTC/SS; bitpos: [30]; default: 0; - * need_des - */ - uint32_t active_switch_sleep_start_int_raw:1; - /** hp_sw_trigger_int_raw : R/WTC/SS; bitpos: [31]; default: 0; - * need_des - */ - uint32_t hp_sw_trigger_int_raw:1; - }; - uint32_t val; -} pmu_lp_int_raw_reg_t; - -/** Type of lp_int_st register - * need_des - */ typedef union { struct { - uint32_t reserved_0:20; - /** lp_cpu_wakeup_int_st : RO; bitpos: [20]; default: 0; - * need_des - */ - uint32_t lp_cpu_wakeup_int_st:1; - /** modem_switch_active_end_int_st : RO; bitpos: [21]; default: 0; - * need_des - */ - uint32_t modem_switch_active_end_int_st:1; - /** sleep_switch_active_end_int_st : RO; bitpos: [22]; default: 0; - * need_des - */ - uint32_t sleep_switch_active_end_int_st:1; - /** sleep_switch_modem_end_int_st : RO; bitpos: [23]; default: 0; - * need_des - */ - uint32_t sleep_switch_modem_end_int_st:1; - /** modem_switch_sleep_end_int_st : RO; bitpos: [24]; default: 0; - * need_des - */ - uint32_t modem_switch_sleep_end_int_st:1; - /** active_switch_sleep_end_int_st : RO; bitpos: [25]; default: 0; - * need_des - */ - uint32_t active_switch_sleep_end_int_st:1; - /** modem_switch_active_start_int_st : RO; bitpos: [26]; default: 0; - * need_des - */ - uint32_t modem_switch_active_start_int_st:1; - /** sleep_switch_active_start_int_st : RO; bitpos: [27]; default: 0; - * need_des - */ - uint32_t sleep_switch_active_start_int_st:1; - /** sleep_switch_modem_start_int_st : RO; bitpos: [28]; default: 0; - * need_des - */ - uint32_t sleep_switch_modem_start_int_st:1; - /** modem_switch_sleep_start_int_st : RO; bitpos: [29]; default: 0; - * need_des - */ - uint32_t modem_switch_sleep_start_int_st:1; - /** active_switch_sleep_start_int_st : RO; bitpos: [30]; default: 0; - * need_des - */ - uint32_t active_switch_sleep_start_int_st:1; - /** hp_sw_trigger_int_st : RO; bitpos: [31]; default: 0; - * need_des - */ - uint32_t hp_sw_trigger_int_st:1; + uint32_t reserved0 : 27; + uint32_t lp_exception: 1; + uint32_t sdio_idle: 1; + uint32_t sw : 1; + uint32_t reject : 1; + uint32_t wakeup : 1; }; uint32_t val; -} pmu_lp_int_st_reg_t; +} pmu_hp_intr_reg_t; -/** Type of lp_int_ena register - * need_des - */ -typedef union { - struct { - uint32_t reserved_0:20; - /** lp_cpu_wakeup_int_ena : R/W; bitpos: [20]; default: 0; - * need_des - */ - uint32_t lp_cpu_wakeup_int_ena:1; - /** modem_switch_active_end_int_ena : R/W; bitpos: [21]; default: 0; - * need_des - */ - uint32_t modem_switch_active_end_int_ena:1; - /** sleep_switch_active_end_int_ena : R/W; bitpos: [22]; default: 0; - * need_des - */ - uint32_t sleep_switch_active_end_int_ena:1; - /** sleep_switch_modem_end_int_ena : R/W; bitpos: [23]; default: 0; - * need_des - */ - uint32_t sleep_switch_modem_end_int_ena:1; - /** modem_switch_sleep_end_int_ena : R/W; bitpos: [24]; default: 0; - * need_des - */ - uint32_t modem_switch_sleep_end_int_ena:1; - /** active_switch_sleep_end_int_ena : R/W; bitpos: [25]; default: 0; - * need_des - */ - uint32_t active_switch_sleep_end_int_ena:1; - /** modem_switch_active_start_int_ena : R/W; bitpos: [26]; default: 0; - * need_des - */ - uint32_t modem_switch_active_start_int_ena:1; - /** sleep_switch_active_start_int_ena : R/W; bitpos: [27]; default: 0; - * need_des - */ - uint32_t sleep_switch_active_start_int_ena:1; - /** sleep_switch_modem_start_int_ena : R/W; bitpos: [28]; default: 0; - * need_des - */ - uint32_t sleep_switch_modem_start_int_ena:1; - /** modem_switch_sleep_start_int_ena : R/W; bitpos: [29]; default: 0; - * need_des - */ - uint32_t modem_switch_sleep_start_int_ena:1; - /** active_switch_sleep_start_int_ena : R/W; bitpos: [30]; default: 0; - * need_des - */ - uint32_t active_switch_sleep_start_int_ena:1; - /** hp_sw_trigger_int_ena : R/W; bitpos: [31]; default: 0; - * need_des - */ - uint32_t hp_sw_trigger_int_ena:1; - }; - uint32_t val; -} pmu_lp_int_ena_reg_t; +typedef struct pmu_hp_ext_hw_regmap_t{ + pmu_hp_clk_poweron_reg_t clk_poweron; + pmu_hp_clk_cntl_reg_t clk_cntl; + pmu_por_status_reg_t por_status; + pmu_rf_pwc_reg_t rf_pwc; + pmu_vddbat_cfg_reg_t vddbat_cfg; + pmu_backup_cfg_reg_t backup_cfg; + pmu_hp_intr_reg_t int_raw; + pmu_hp_intr_reg_t int_st; + pmu_hp_intr_reg_t int_ena; + pmu_hp_intr_reg_t int_clr; +} pmu_hp_ext_hw_regmap_t; -/** Type of lp_int_clr register - * need_des - */ typedef union { struct { - uint32_t reserved_0:20; - /** lp_cpu_wakeup_int_clr : WT; bitpos: [20]; default: 0; - * need_des - */ - uint32_t lp_cpu_wakeup_int_clr:1; - /** modem_switch_active_end_int_clr : WT; bitpos: [21]; default: 0; - * need_des - */ - uint32_t modem_switch_active_end_int_clr:1; - /** sleep_switch_active_end_int_clr : WT; bitpos: [22]; default: 0; - * need_des - */ - uint32_t sleep_switch_active_end_int_clr:1; - /** sleep_switch_modem_end_int_clr : WT; bitpos: [23]; default: 0; - * need_des - */ - uint32_t sleep_switch_modem_end_int_clr:1; - /** modem_switch_sleep_end_int_clr : WT; bitpos: [24]; default: 0; - * need_des - */ - uint32_t modem_switch_sleep_end_int_clr:1; - /** active_switch_sleep_end_int_clr : WT; bitpos: [25]; default: 0; - * need_des - */ - uint32_t active_switch_sleep_end_int_clr:1; - /** modem_switch_active_start_int_clr : WT; bitpos: [26]; default: 0; - * need_des - */ - uint32_t modem_switch_active_start_int_clr:1; - /** sleep_switch_active_start_int_clr : WT; bitpos: [27]; default: 0; - * need_des - */ - uint32_t sleep_switch_active_start_int_clr:1; - /** sleep_switch_modem_start_int_clr : WT; bitpos: [28]; default: 0; - * need_des - */ - uint32_t sleep_switch_modem_start_int_clr:1; - /** modem_switch_sleep_start_int_clr : WT; bitpos: [29]; default: 0; - * need_des - */ - uint32_t modem_switch_sleep_start_int_clr:1; - /** active_switch_sleep_start_int_clr : WT; bitpos: [30]; default: 0; - * need_des - */ - uint32_t active_switch_sleep_start_int_clr:1; - /** hp_sw_trigger_int_clr : WT; bitpos: [31]; default: 0; - * need_des - */ - uint32_t hp_sw_trigger_int_clr:1; + uint32_t reserved0 : 20; + uint32_t lp_wakeup : 1; + uint32_t modem_switch_active_end : 1; + uint32_t sleep_switch_active_end : 1; + uint32_t sleep_switch_modem_end : 1; + uint32_t modem_switch_sleep_end : 1; + uint32_t active_switch_sleep_end : 1; + uint32_t modem_switch_active_start: 1; + uint32_t sleep_switch_active_start: 1; + uint32_t sleep_switch_modem_start : 1; + uint32_t modem_switch_sleep_start : 1; + uint32_t active_switch_sleep_start: 1; + uint32_t hp_sw_trigger : 1; }; uint32_t val; -} pmu_lp_int_clr_reg_t; +} pmu_lp_intr_reg_t; -/** Type of lp_cpu_pwr0 register - * need_des - */ typedef union { struct { - /** lp_cpu_waiti_rdy : RO; bitpos: [0]; default: 0; - * need_des - */ - uint32_t lp_cpu_waiti_rdy:1; - /** lp_cpu_stall_rdy : RO; bitpos: [1]; default: 0; - * need_des - */ - uint32_t lp_cpu_stall_rdy:1; - uint32_t reserved_2:16; - /** lp_cpu_force_stall : R/W; bitpos: [18]; default: 0; - * need_des - */ - uint32_t lp_cpu_force_stall:1; - /** lp_cpu_slp_waiti_flag_en : R/W; bitpos: [19]; default: 0; - * need_des - */ - uint32_t lp_cpu_slp_waiti_flag_en:1; - /** lp_cpu_slp_stall_flag_en : R/W; bitpos: [20]; default: 1; - * need_des - */ - uint32_t lp_cpu_slp_stall_flag_en:1; - /** lp_cpu_slp_stall_wait : R/W; bitpos: [28:21]; default: 255; - * need_des - */ - uint32_t lp_cpu_slp_stall_wait:8; - /** lp_cpu_slp_stall_en : R/W; bitpos: [29]; default: 0; - * need_des - */ - uint32_t lp_cpu_slp_stall_en:1; - /** lp_cpu_slp_reset_en : R/W; bitpos: [30]; default: 0; - * need_des - */ - uint32_t lp_cpu_slp_reset_en:1; - /** lp_cpu_slp_bypass_intr_en : R/W; bitpos: [31]; default: 0; - * need_des - */ - uint32_t lp_cpu_slp_bypass_intr_en:1; + uint32_t waiti_rdy : 1; + uint32_t stall_rdy : 1; + uint32_t reserved0 : 16; + uint32_t force_stall : 1; + uint32_t slp_waiti_flag_en : 1; + uint32_t slp_stall_flag_en : 1; + uint32_t slp_stall_wait : 8; + uint32_t slp_stall_en : 1; + uint32_t slp_reset_en : 1; + uint32_t slp_bypass_intr_en: 1; }; uint32_t val; } pmu_lp_cpu_pwr0_reg_t; -/** Type of lp_cpu_pwr1 register - * need_des - */ typedef union { struct { - /** lp_cpu_wakeup_en : R/W; bitpos: [15:0]; default: 0; - * need_des - */ - uint32_t lp_cpu_wakeup_en:16; - uint32_t reserved_16:15; - /** lp_cpu_sleep_req : WT; bitpos: [31]; default: 0; - * need_des - */ - uint32_t lp_cpu_sleep_req:1; + uint32_t wakeup_en: 16; + uint32_t reserved0: 15; + uint32_t sleep_req: 1; }; uint32_t val; } pmu_lp_cpu_pwr1_reg_t; -/** Type of hp_lp_cpu_comm register - * need_des - */ -typedef union { - struct { - uint32_t reserved_0:30; - /** lp_trigger_hp : WT; bitpos: [30]; default: 0; - * need_des - */ - uint32_t lp_trigger_hp:1; - /** hp_trigger_lp : WT; bitpos: [31]; default: 0; - * need_des - */ - uint32_t hp_trigger_lp:1; - }; - uint32_t val; -} pmu_hp_lp_cpu_comm_reg_t; - -/** Type of hp_regulator_cfg register - * need_des - */ -typedef union { - struct { - uint32_t reserved_0:31; - /** dig_regulator_en_cal : R/W; bitpos: [31]; default: 0; - * need_des - */ - uint32_t dig_regulator_en_cal:1; - }; - uint32_t val; -} pmu_hp_regulator_cfg_reg_t; - -/** Type of main_state register - * need_des - */ -typedef union { - struct { - uint32_t reserved_0:11; - /** main_last_st_state : RO; bitpos: [17:11]; default: 256; - * need_des - */ - uint32_t main_last_st_state:7; - /** main_tar_st_state : RO; bitpos: [24:18]; default: 4; - * need_des - */ - uint32_t main_tar_st_state:7; - /** main_cur_st_state : RO; bitpos: [31:25]; default: 1; - * need_des - */ - uint32_t main_cur_st_state:7; - }; - uint32_t val; -} pmu_main_state_reg_t; - -/** Type of pwr_state register - * need_des - */ -typedef union { - struct { - uint32_t reserved_0:13; - /** backup_st_state : RO; bitpos: [17:13]; default: 1; - * need_des - */ - uint32_t backup_st_state:5; - /** lp_pwr_st_state : RO; bitpos: [22:18]; default: 0; - * need_des - */ - uint32_t lp_pwr_st_state:5; - /** hp_pwr_st_state : RO; bitpos: [31:23]; default: 1; - * need_des - */ - uint32_t hp_pwr_st_state:9; - }; - uint32_t val; -} pmu_pwr_state_reg_t; - -/** Type of dcm_ctrl register - * need_des - */ -typedef union { - struct { - /** dsfmos_use_por : R/W; bitpos: [0]; default: 1; - * need_des - */ - uint32_t dsfmos_use_por:1; - uint32_t reserved_1:21; - /** dcdc_dcm_update : WT; bitpos: [22]; default: 0; - * need_des - */ - uint32_t dcdc_dcm_update:1; - /** dcdc_pcur_limit : R/W; bitpos: [25:23]; default: 1; - * need_des - */ - uint32_t dcdc_pcur_limit:3; - /** dcdc_bias_cal_done : RO; bitpos: [26]; default: 1; - * need_des - */ - uint32_t dcdc_bias_cal_done:1; - /** dcdc_ccm_sw_en : R/W; bitpos: [27]; default: 0; - * need_des - */ - uint32_t dcdc_ccm_sw_en:1; - /** dcdc_vcm_enb : R/W; bitpos: [28]; default: 0; - * need_des - */ - uint32_t dcdc_vcm_enb:1; - /** dcdc_ccm_rdy : RO; bitpos: [29]; default: 0; - * need_des - */ - uint32_t dcdc_ccm_rdy:1; - /** dcdc_vcm_rdy : RO; bitpos: [30]; default: 1; - * need_des - */ - uint32_t dcdc_vcm_rdy:1; - /** dcdc_rdy_clr : R/W; bitpos: [31]; default: 0; - * need_des - */ - uint32_t dcdc_rdy_clr:1; - }; - uint32_t val; -} pmu_dcm_ctrl_reg_t; - -/** Type of touch_pwr_ctrl register - * need_des - */ -typedef union { - struct { - /** touch_sleep_cycles : R/W; bitpos: [15:0]; default: 0; - * need_des - */ - uint32_t touch_sleep_cycles:16; - uint32_t reserved_16:5; - /** touch_wait_cycles : R/W; bitpos: [29:21]; default: 0; - * need_des - */ - uint32_t touch_wait_cycles:9; - /** touch_sleep_timer_en : R/W; bitpos: [30]; default: 0; - * need_des - */ - uint32_t touch_sleep_timer_en:1; - /** touch_force_done : R/W; bitpos: [31]; default: 0; - * need_des - */ - uint32_t touch_force_done:1; - }; - uint32_t val; -} pmu_touch_pwr_ctrl_reg_t; - -/** Type of date register - * need_des - */ -typedef union { - struct { - /** pmu_date : R/W; bitpos: [30:0]; default: 37814400; - * need_des - */ - uint32_t pmu_date:31; - /** clk_en : R/W; bitpos: [31]; default: 0; - * need_des - */ - uint32_t clk_en:1; - }; - uint32_t val; -} pmu_date_reg_t; - - -/** Group: status_register */ -/** Type of clk_state0 register - * need_des - */ -typedef union { - struct { - /** stable_xpd_bbpll_state : RO; bitpos: [0]; default: 0; - * need_des - */ - uint32_t stable_xpd_bbpll_state:1; - /** stable_xpd_xtal_state : RO; bitpos: [1]; default: 0; - * need_des - */ - uint32_t stable_xpd_xtal_state:1; - uint32_t reserved_2:13; - /** sys_clk_slp_sel_state : RO; bitpos: [15]; default: 0; - * need_des - */ - uint32_t sys_clk_slp_sel_state:1; - /** sys_clk_sel_state : RO; bitpos: [17:16]; default: 0; - * need_des - */ - uint32_t sys_clk_sel_state:2; - /** sys_clk_no_div_state : RO; bitpos: [18]; default: 0; - * need_des - */ - uint32_t sys_clk_no_div_state:1; - /** icg_sys_clk_en_state : RO; bitpos: [19]; default: 1; - * need_des - */ - uint32_t icg_sys_clk_en_state:1; - /** icg_modem_switch_state : RO; bitpos: [20]; default: 0; - * need_des - */ - uint32_t icg_modem_switch_state:1; - /** icg_modem_code_state : RO; bitpos: [22:21]; default: 0; - * need_des - */ - uint32_t icg_modem_code_state:2; - /** icg_slp_sel_state : RO; bitpos: [23]; default: 0; - * need_des - */ - uint32_t icg_slp_sel_state:1; - /** icg_global_xtal_state : RO; bitpos: [24]; default: 0; - * need_des - */ - uint32_t icg_global_xtal_state:1; - /** icg_global_pll_state : RO; bitpos: [25]; default: 0; - * need_des - */ - uint32_t icg_global_pll_state:1; - /** ana_i2c_iso_en_state : RO; bitpos: [26]; default: 0; - * need_des - */ - uint32_t ana_i2c_iso_en_state:1; - /** ana_i2c_retention_state : RO; bitpos: [27]; default: 0; - * need_des - */ - uint32_t ana_i2c_retention_state:1; - /** ana_xpd_bb_i2c_state : RO; bitpos: [28]; default: 0; - * need_des - */ - uint32_t ana_xpd_bb_i2c_state:1; - /** ana_xpd_bbpll_i2c_state : RO; bitpos: [29]; default: 0; - * need_des - */ - uint32_t ana_xpd_bbpll_i2c_state:1; - /** ana_xpd_bbpll_state : RO; bitpos: [30]; default: 0; - * need_des - */ - uint32_t ana_xpd_bbpll_state:1; - /** ana_xpd_xtal_state : RO; bitpos: [31]; default: 1; - * need_des - */ - uint32_t ana_xpd_xtal_state:1; - }; - uint32_t val; -} pmu_clk_state0_reg_t; - -/** Type of clk_state1 register - * need_des - */ -typedef union { - struct { - /** icg_func_en_state : RO; bitpos: [31:0]; default: 4294967295; - * need_des - */ - uint32_t icg_func_en_state:32; - }; - uint32_t val; -} pmu_clk_state1_reg_t; - -/** Type of clk_state2 register - * need_des - */ -typedef union { - struct { - /** icg_apb_en_state : RO; bitpos: [31:0]; default: 4294967295; - * need_des - */ - uint32_t icg_apb_en_state:32; - }; - uint32_t val; -} pmu_clk_state2_reg_t; - +typedef struct pmu_lp_ext_hw_regmap_t{ + pmu_lp_intr_reg_t int_raw; + pmu_lp_intr_reg_t int_st; + pmu_lp_intr_reg_t int_ena; + pmu_lp_intr_reg_t int_clr; + pmu_lp_cpu_pwr0_reg_t pwr0; + pmu_lp_cpu_pwr1_reg_t pwr1; +} pmu_lp_ext_hw_regmap_t; typedef struct { - volatile pmu_hp_active_dig_power_reg_t hp_active_dig_power; - volatile pmu_hp_active_icg_hp_func_reg_t hp_active_icg_hp_func; - volatile pmu_hp_active_icg_hp_apb_reg_t hp_active_icg_hp_apb; - volatile pmu_hp_active_icg_modem_reg_t hp_active_icg_modem; - volatile pmu_hp_active_hp_sys_cntl_reg_t hp_active_hp_sys_cntl; - volatile pmu_hp_active_hp_ck_power_reg_t hp_active_hp_ck_power; - volatile pmu_hp_active_bias_reg_t hp_active_bias; - volatile pmu_hp_active_backup_reg_t hp_active_backup; - volatile pmu_hp_active_backup_clk_reg_t hp_active_backup_clk; - volatile pmu_hp_active_sysclk_reg_t hp_active_sysclk; - volatile pmu_hp_active_hp_regulator0_reg_t hp_active_hp_regulator0; - volatile pmu_hp_active_hp_regulator1_reg_t hp_active_hp_regulator1; - volatile pmu_hp_active_xtal_reg_t hp_active_xtal; - uint32_t reserved_034[13]; - volatile pmu_hp_sleep_dig_power_reg_t hp_sleep_dig_power; - volatile pmu_hp_sleep_icg_hp_func_reg_t hp_sleep_icg_hp_func; - volatile pmu_hp_sleep_icg_hp_apb_reg_t hp_sleep_icg_hp_apb; - volatile pmu_hp_sleep_icg_modem_reg_t hp_sleep_icg_modem; - volatile pmu_hp_sleep_hp_sys_cntl_reg_t hp_sleep_hp_sys_cntl; - volatile pmu_hp_sleep_hp_ck_power_reg_t hp_sleep_hp_ck_power; - volatile pmu_hp_sleep_bias_reg_t hp_sleep_bias; - volatile pmu_hp_sleep_backup_reg_t hp_sleep_backup; - volatile pmu_hp_sleep_backup_clk_reg_t hp_sleep_backup_clk; - volatile pmu_hp_sleep_sysclk_reg_t hp_sleep_sysclk; - volatile pmu_hp_sleep_hp_regulator0_reg_t hp_sleep_hp_regulator0; - volatile pmu_hp_sleep_hp_regulator1_reg_t hp_sleep_hp_regulator1; - volatile pmu_hp_sleep_xtal_reg_t hp_sleep_xtal; - volatile pmu_hp_sleep_lp_regulator0_reg_t hp_sleep_lp_regulator0; - volatile pmu_hp_sleep_lp_regulator1_reg_t hp_sleep_lp_regulator1; - uint32_t reserved_0a4; - volatile pmu_hp_sleep_lp_dig_power_reg_t hp_sleep_lp_dig_power; - volatile pmu_hp_sleep_lp_ck_power_reg_t hp_sleep_lp_ck_power; - uint32_t reserved_0b0; - volatile pmu_lp_sleep_lp_regulator0_reg_t lp_sleep_lp_regulator0; - volatile pmu_lp_sleep_lp_regulator1_reg_t lp_sleep_lp_regulator1; - volatile pmu_lp_sleep_xtal_reg_t lp_sleep_xtal; - volatile pmu_lp_sleep_lp_dig_power_reg_t lp_sleep_lp_dig_power; - volatile pmu_lp_sleep_lp_ck_power_reg_t lp_sleep_lp_ck_power; - volatile pmu_lp_sleep_bias_reg_t lp_sleep_bias; - volatile pmu_imm_hp_ck_power_reg_t imm_hp_ck_power; - volatile pmu_imm_sleep_sysclk_reg_t imm_sleep_sysclk; - volatile pmu_imm_hp_func_icg_reg_t imm_hp_func_icg; - volatile pmu_imm_hp_apb_icg_reg_t imm_hp_apb_icg; - volatile pmu_imm_modem_icg_reg_t imm_modem_icg; - volatile pmu_imm_lp_icg_reg_t imm_lp_icg; - volatile pmu_imm_pad_hold_all_reg_t imm_pad_hold_all; - volatile pmu_imm_i2c_iso_reg_t imm_i2c_iso; - volatile pmu_power_wait_timer0_reg_t power_wait_timer0; - volatile pmu_power_wait_timer1_reg_t power_wait_timer1; - volatile pmu_power_wait_timer2_reg_t power_wait_timer2; - volatile pmu_power_pd_top_cntl_reg_t power_pd_top_cntl; - volatile pmu_power_pd_hpaon_cntl_reg_t power_pd_hpaon_cntl; - volatile pmu_power_pd_hpcpu_cntl_reg_t power_pd_hpcpu_cntl; - volatile pmu_power_pd_hpperi_reserve_reg_t power_pd_hpperi_reserve; - volatile pmu_power_pd_hpwifi_cntl_reg_t power_pd_hpwifi_cntl; - volatile pmu_power_pd_lpperi_cntl_reg_t power_pd_lpperi_cntl; - volatile pmu_power_pd_mem_cntl_reg_t power_pd_mem_cntl; - volatile pmu_power_pd_mem_mask_reg_t power_pd_mem_mask; - volatile pmu_power_hp_pad_reg_t power_hp_pad; - volatile pmu_power_flash1p8_ldo_reg_t power_flash1p8_ldo; - volatile pmu_power_flash1p2_ldo_reg_t power_flash1p2_ldo; - volatile pmu_power_vdd_flash_reg_t power_vdd_flash; - volatile pmu_power_io_ldo_reg_t power_io_ldo; - volatile pmu_power_vdd_io_reg_t power_vdd_io; - volatile pmu_power_ck_wait_cntl_reg_t power_ck_wait_cntl; - volatile pmu_slp_wakeup_cntl0_reg_t slp_wakeup_cntl0; - volatile pmu_slp_wakeup_cntl1_reg_t slp_wakeup_cntl1; - volatile pmu_slp_wakeup_cntl2_reg_t slp_wakeup_cntl2; - volatile pmu_slp_wakeup_cntl3_reg_t slp_wakeup_cntl3; - volatile pmu_slp_wakeup_cntl4_reg_t slp_wakeup_cntl4; - volatile pmu_slp_wakeup_cntl5_reg_t slp_wakeup_cntl5; - volatile pmu_slp_wakeup_cntl6_reg_t slp_wakeup_cntl6; - volatile pmu_slp_wakeup_cntl7_reg_t slp_wakeup_cntl7; - volatile pmu_slp_wakeup_status0_reg_t slp_wakeup_status0; - volatile pmu_slp_wakeup_status1_reg_t slp_wakeup_status1; - volatile pmu_hp_ck_poweron_reg_t hp_ck_poweron; - volatile pmu_hp_ck_cntl_reg_t hp_ck_cntl; - volatile pmu_por_status_reg_t por_status; - volatile pmu_rf_pwc_reg_t rf_pwc; - volatile pmu_vddbat_cfg_reg_t vddbat_cfg; - volatile pmu_backup_cfg_reg_t backup_cfg; - volatile pmu_int_raw_reg_t int_raw; - volatile pmu_hp_int_st_reg_t hp_int_st; - volatile pmu_hp_int_ena_reg_t hp_int_ena; - volatile pmu_hp_int_clr_reg_t hp_int_clr; - volatile pmu_lp_int_raw_reg_t lp_int_raw; - volatile pmu_lp_int_st_reg_t lp_int_st; - volatile pmu_lp_int_ena_reg_t lp_int_ena; - volatile pmu_lp_int_clr_reg_t lp_int_clr; - volatile pmu_lp_cpu_pwr0_reg_t lp_cpu_pwr0; - volatile pmu_lp_cpu_pwr1_reg_t lp_cpu_pwr1; - volatile pmu_hp_lp_cpu_comm_reg_t hp_lp_cpu_comm; - volatile pmu_hp_regulator_cfg_reg_t hp_regulator_cfg; - volatile pmu_main_state_reg_t main_state; - volatile pmu_pwr_state_reg_t pwr_state; - volatile pmu_clk_state0_reg_t clk_state0; - volatile pmu_clk_state1_reg_t clk_state1; - volatile pmu_clk_state2_reg_t clk_state2; - volatile pmu_dcm_ctrl_reg_t dcm_ctrl; - volatile pmu_touch_pwr_ctrl_reg_t touch_pwr_ctrl; - uint32_t reserved_1c0[143]; - volatile pmu_date_reg_t date; + volatile struct { + } common; +} pmu_hp_lp_hw_regmap_t; + +typedef struct pmu_dev_t{ + volatile pmu_hp_hw_regmap_t hp_sys[3]; + volatile pmu_lp_hw_regmap_t lp_sys[2]; + volatile pmu_imm_hw_regmap_t imm; + volatile pmu_power_hw_regmap_t power; + volatile pmu_wakeup_hw_regmap_t wakeup; + volatile pmu_hp_ext_hw_regmap_t hp_ext; + volatile pmu_lp_ext_hw_regmap_t lp_ext; + + union { + struct { + uint32_t reserved0 : 30; + volatile uint32_t lp_trigger_hp: 1; + volatile uint32_t hp_trigger_lp: 1; + }; + volatile uint32_t val; + } hp_lp_cpu_comm; + + union { + struct { + uint32_t reserved0 : 31; + volatile uint32_t dig_regulator_en_cal: 1; + }; + volatile uint32_t val; + } hp_regulator_cfg; + + union { + struct { + uint32_t reserved0 : 11; + volatile uint32_t last_st : 7; + volatile uint32_t target_st : 7; + volatile uint32_t current_st: 7; + }; + volatile uint32_t val; + } main_state; + + union { + struct { + uint32_t reserved0: 13; + volatile uint32_t backup_st: 5; + volatile uint32_t lp_pwr_st: 5; + volatile uint32_t hp_pwr_st: 9; + }; + volatile uint32_t val; + } pwr_state; + + union { + struct { + volatile uint32_t stable_xpd_bbpll : 1; + volatile uint32_t stable_xpd_xtal : 1; + volatile uint32_t reserved0 : 13; + volatile uint32_t sysclk_slp_sel : 1; + volatile uint32_t sysclk_sel : 2; + volatile uint32_t sysclk_nodiv : 1; + volatile uint32_t icg_sysclk_en : 1; + volatile uint32_t icg_modem_switch : 1; + volatile uint32_t icg_modem_code : 2; + volatile uint32_t icg_slp_sel : 1; + volatile uint32_t icg_global_xtal : 1; + volatile uint32_t icg_global_pll : 1; + volatile uint32_t ana_i2c_iso_en : 1; + volatile uint32_t ana_i2c_retention: 1; + volatile uint32_t ana_xpd_bb_i2c : 1; + volatile uint32_t ana_xpd_bbpll_i2c: 1; + volatile uint32_t ana_xpd_bbpll : 1; + volatile uint32_t ana_xpd_xtal : 1; + }; + volatile uint32_t val; + } clk_state0; + + volatile uint32_t clk_state1; + volatile uint32_t clk_state2; + + union { + struct { + uint32_t reserved0 : 31; + volatile uint32_t stable_vdd_spi_pwr_drv: 1; + }; + volatile uint32_t val; + } vdd_spi_status; + + uint32_t reserved[149]; + + union { + struct { + volatile uint32_t pmu_date: 31; + volatile uint32_t clk_en : 1; + }; + volatile uint32_t val; + } date; } pmu_dev_t; extern pmu_dev_t PMU; #ifndef __cplusplus _Static_assert(sizeof(pmu_dev_t) == 0x400, "Invalid size of pmu_dev_t structure"); + +// _Static_assert(offsetof(pmu_dev_t, reserved) == (PMU_VDD_SPI_STATUS_REG - DR_REG_PMU_BASE) + 4, "Invalid size of pmu_dev_t structure"); + #endif #ifdef __cplusplus diff --git a/components/soc/esp32h21/register/soc/spi1_mem_reg.h b/components/soc/esp32h21/register/soc/spi1_mem_reg.h index b17d087a9a9..1f3373b5144 100644 --- a/components/soc/esp32h21/register/soc/spi1_mem_reg.h +++ b/components/soc/esp32h21/register/soc/spi1_mem_reg.h @@ -14,7 +14,7 @@ extern "C" { /** SPI_MEM_CMD_REG register * SPI1 memory command register */ -#define SPI_MEM_CMD_REG(i) (REG_SPI_MEM_BASE(i) + 0x0) +#define SPI_MEM_CMD_REG(i) (DR_REG_SPI_MEM_BASE(i) + 0x0) /** SPI_MEM_MST_ST : RO; bitpos: [3:0]; default: 0; * The current status of SPI1 master FSM. */ @@ -172,7 +172,7 @@ extern "C" { /** SPI_MEM_ADDR_REG register * SPI1 address register */ -#define SPI_MEM_ADDR_REG(i) (REG_SPI_MEM_BASE(i) + 0x4) +#define SPI_MEM_ADDR_REG(i) (DR_REG_SPI_MEM_BASE(i) + 0x4) /** SPI_MEM_USR_ADDR_VALUE : R/W; bitpos: [31:0]; default: 0; * In user mode, it is the memory address. other then the bit0-bit23 is the memory * address, the bit24-bit31 are the byte length of a transfer. @@ -185,7 +185,7 @@ extern "C" { /** SPI_MEM_CTRL_REG register * SPI1 control register. */ -#define SPI_MEM_CTRL_REG(i) (REG_SPI_MEM_BASE(i) + 0x8) +#define SPI_MEM_CTRL_REG(i) (DR_REG_SPI_MEM_BASE(i) + 0x8) /** SPI_MEM_FDUMMY_RIN : R/W; bitpos: [2]; default: 1; * In the dummy phase of a MSPI read data transfer when accesses to flash, the signal * level of SPI bus is output by the MSPI controller. @@ -335,7 +335,7 @@ extern "C" { /** SPI_MEM_CTRL1_REG register * SPI1 control1 register. */ -#define SPI_MEM_CTRL1_REG(i) (REG_SPI_MEM_BASE(i) + 0xc) +#define SPI_MEM_CTRL1_REG(i) (DR_REG_SPI_MEM_BASE(i) + 0xc) /** SPI_MEM_CLK_MODE : R/W; bitpos: [1:0]; default: 0; * SPI clock mode bits. 0: SPI clock is off when CS inactive 1: SPI clock is delayed * one cycle after CS inactive 2: SPI clock is delayed two cycles after CS inactive 3: @@ -365,7 +365,7 @@ extern "C" { /** SPI_MEM_CTRL2_REG register * SPI1 control2 register. */ -#define SPI_MEM_CTRL2_REG(i) (REG_SPI_MEM_BASE(i) + 0x10) +#define SPI_MEM_CTRL2_REG(i) (DR_REG_SPI_MEM_BASE(i) + 0x10) /** SPI_MEM_SYNC_RESET : WT; bitpos: [31]; default: 0; * The FSM will be reset. */ @@ -377,7 +377,7 @@ extern "C" { /** SPI_MEM_CLOCK_REG register * SPI1 clock division control register. */ -#define SPI_MEM_CLOCK_REG(i) (REG_SPI_MEM_BASE(i) + 0x14) +#define SPI_MEM_CLOCK_REG(i) (DR_REG_SPI_MEM_BASE(i) + 0x14) /** SPI_MEM_CLKCNT_L : R/W; bitpos: [7:0]; default: 3; * In the master mode it must be equal to SPI_MEM_CLKCNT_N. */ @@ -411,7 +411,7 @@ extern "C" { /** SPI_MEM_USER_REG register * SPI1 user register. */ -#define SPI_MEM_USER_REG(i) (REG_SPI_MEM_BASE(i) + 0x18) +#define SPI_MEM_USER_REG(i) (DR_REG_SPI_MEM_BASE(i) + 0x18) /** SPI_MEM_CK_OUT_EDGE : R/W; bitpos: [9]; default: 0; * the bit combined with spi_mem_mosi_delay_mode bits to set mosi signal delay mode. */ @@ -511,7 +511,7 @@ extern "C" { /** SPI_MEM_USER1_REG register * SPI1 user1 register. */ -#define SPI_MEM_USER1_REG(i) (REG_SPI_MEM_BASE(i) + 0x1c) +#define SPI_MEM_USER1_REG(i) (DR_REG_SPI_MEM_BASE(i) + 0x1c) /** SPI_MEM_USR_DUMMY_CYCLELEN : R/W; bitpos: [5:0]; default: 7; * The length in spi_mem_clk cycles of dummy phase. The register value shall be * (cycle_num-1). @@ -531,7 +531,7 @@ extern "C" { /** SPI_MEM_USER2_REG register * SPI1 user2 register. */ -#define SPI_MEM_USER2_REG(i) (REG_SPI_MEM_BASE(i) + 0x20) +#define SPI_MEM_USER2_REG(i) (DR_REG_SPI_MEM_BASE(i) + 0x20) /** SPI_MEM_USR_COMMAND_VALUE : R/W; bitpos: [15:0]; default: 0; * The value of command. */ @@ -550,7 +550,7 @@ extern "C" { /** SPI_MEM_MOSI_DLEN_REG register * SPI1 send data bit length control register. */ -#define SPI_MEM_MOSI_DLEN_REG(i) (REG_SPI_MEM_BASE(i) + 0x24) +#define SPI_MEM_MOSI_DLEN_REG(i) (DR_REG_SPI_MEM_BASE(i) + 0x24) /** SPI_MEM_USR_MOSI_DBITLEN : R/W; bitpos: [9:0]; default: 0; * The length in bits of write-data. The register value shall be (bit_num-1). */ @@ -562,7 +562,7 @@ extern "C" { /** SPI_MEM_MISO_DLEN_REG register * SPI1 receive data bit length control register. */ -#define SPI_MEM_MISO_DLEN_REG(i) (REG_SPI_MEM_BASE(i) + 0x28) +#define SPI_MEM_MISO_DLEN_REG(i) (DR_REG_SPI_MEM_BASE(i) + 0x28) /** SPI_MEM_USR_MISO_DBITLEN : R/W; bitpos: [9:0]; default: 0; * The length in bits of read-data. The register value shall be (bit_num-1). */ @@ -574,7 +574,7 @@ extern "C" { /** SPI_MEM_RD_STATUS_REG register * SPI1 status register. */ -#define SPI_MEM_RD_STATUS_REG(i) (REG_SPI_MEM_BASE(i) + 0x2c) +#define SPI_MEM_RD_STATUS_REG(i) (DR_REG_SPI_MEM_BASE(i) + 0x2c) /** SPI_MEM_STATUS : R/W/SS; bitpos: [15:0]; default: 0; * The value is stored when set spi_mem_flash_rdsr bit and spi_mem_flash_res bit. */ @@ -610,7 +610,7 @@ extern "C" { /** SPI_MEM_MISC_REG register * SPI1 misc register */ -#define SPI_MEM_MISC_REG(i) (REG_SPI_MEM_BASE(i) + 0x34) +#define SPI_MEM_MISC_REG(i) (DR_REG_SPI_MEM_BASE(i) + 0x34) /** SPI_MEM_CS0_DIS : R/W; bitpos: [0]; default: 0; * SPI_CS0 pin enable, 1: disable SPI_CS0, 0: SPI_CS0 pin is active to select SPI * device, such as flash, external RAM and so on. @@ -647,7 +647,7 @@ extern "C" { * This register is only for internal debugging purposes. Do not use it in * applications. */ -#define SPI_MEM_TX_CRC_REG(i) (REG_SPI_MEM_BASE(i) + 0x38) +#define SPI_MEM_TX_CRC_REG(i) (DR_REG_SPI_MEM_BASE(i) + 0x38) /** SPI_MEM_TX_CRC_DATA : RO; bitpos: [31:0]; default: 4294967295; * For SPI1, the value of crc32. * This field is only for internal debugging purposes. Do not use it in applications. @@ -662,7 +662,7 @@ extern "C" { * This register is only for internal debugging purposes. Do not use it in * applications. */ -#define SPI_MEM_CACHE_FCTRL_REG(i) (REG_SPI_MEM_BASE(i) + 0x3c) +#define SPI_MEM_CACHE_FCTRL_REG(i) (DR_REG_SPI_MEM_BASE(i) + 0x3c) /** SPI_MEM_CACHE_USR_ADDR_4BYTE : R/W; bitpos: [1]; default: 0; * For SPI1, cache read flash with 4 bytes address, 1: enable, 0:disable. * This field is only for internal debugging purposes. Do not use it in applications. @@ -729,7 +729,7 @@ extern "C" { /** SPI_MEM_W0_REG register * SPI1 memory data buffer0 */ -#define SPI_MEM_W0_REG(i) (REG_SPI_MEM_BASE(i) + 0x58) +#define SPI_MEM_W0_REG(i) (DR_REG_SPI_MEM_BASE(i) + 0x58) /** SPI_MEM_BUF0 : R/W/SS; bitpos: [31:0]; default: 0; * data buffer */ @@ -741,7 +741,7 @@ extern "C" { /** SPI_MEM_W1_REG register * SPI1 memory data buffer1 */ -#define SPI_MEM_W1_REG(i) (REG_SPI_MEM_BASE(i) + 0x5c) +#define SPI_MEM_W1_REG(i) (DR_REG_SPI_MEM_BASE(i) + 0x5c) /** SPI_MEM_BUF1 : R/W/SS; bitpos: [31:0]; default: 0; * data buffer */ @@ -753,7 +753,7 @@ extern "C" { /** SPI_MEM_W2_REG register * SPI1 memory data buffer2 */ -#define SPI_MEM_W2_REG(i) (REG_SPI_MEM_BASE(i) + 0x60) +#define SPI_MEM_W2_REG(i) (DR_REG_SPI_MEM_BASE(i) + 0x60) /** SPI_MEM_BUF2 : R/W/SS; bitpos: [31:0]; default: 0; * data buffer */ @@ -765,7 +765,7 @@ extern "C" { /** SPI_MEM_W3_REG register * SPI1 memory data buffer3 */ -#define SPI_MEM_W3_REG(i) (REG_SPI_MEM_BASE(i) + 0x64) +#define SPI_MEM_W3_REG(i) (DR_REG_SPI_MEM_BASE(i) + 0x64) /** SPI_MEM_BUF3 : R/W/SS; bitpos: [31:0]; default: 0; * data buffer */ @@ -777,7 +777,7 @@ extern "C" { /** SPI_MEM_W4_REG register * SPI1 memory data buffer4 */ -#define SPI_MEM_W4_REG(i) (REG_SPI_MEM_BASE(i) + 0x68) +#define SPI_MEM_W4_REG(i) (DR_REG_SPI_MEM_BASE(i) + 0x68) /** SPI_MEM_BUF4 : R/W/SS; bitpos: [31:0]; default: 0; * data buffer */ @@ -789,7 +789,7 @@ extern "C" { /** SPI_MEM_W5_REG register * SPI1 memory data buffer5 */ -#define SPI_MEM_W5_REG(i) (REG_SPI_MEM_BASE(i) + 0x6c) +#define SPI_MEM_W5_REG(i) (DR_REG_SPI_MEM_BASE(i) + 0x6c) /** SPI_MEM_BUF5 : R/W/SS; bitpos: [31:0]; default: 0; * data buffer */ @@ -801,7 +801,7 @@ extern "C" { /** SPI_MEM_W6_REG register * SPI1 memory data buffer6 */ -#define SPI_MEM_W6_REG(i) (REG_SPI_MEM_BASE(i) + 0x70) +#define SPI_MEM_W6_REG(i) (DR_REG_SPI_MEM_BASE(i) + 0x70) /** SPI_MEM_BUF6 : R/W/SS; bitpos: [31:0]; default: 0; * data buffer */ @@ -813,7 +813,7 @@ extern "C" { /** SPI_MEM_W7_REG register * SPI1 memory data buffer7 */ -#define SPI_MEM_W7_REG(i) (REG_SPI_MEM_BASE(i) + 0x74) +#define SPI_MEM_W7_REG(i) (DR_REG_SPI_MEM_BASE(i) + 0x74) /** SPI_MEM_BUF7 : R/W/SS; bitpos: [31:0]; default: 0; * data buffer */ @@ -825,7 +825,7 @@ extern "C" { /** SPI_MEM_W8_REG register * SPI1 memory data buffer8 */ -#define SPI_MEM_W8_REG(i) (REG_SPI_MEM_BASE(i) + 0x78) +#define SPI_MEM_W8_REG(i) (DR_REG_SPI_MEM_BASE(i) + 0x78) /** SPI_MEM_BUF8 : R/W/SS; bitpos: [31:0]; default: 0; * data buffer */ @@ -837,7 +837,7 @@ extern "C" { /** SPI_MEM_W9_REG register * SPI1 memory data buffer9 */ -#define SPI_MEM_W9_REG(i) (REG_SPI_MEM_BASE(i) + 0x7c) +#define SPI_MEM_W9_REG(i) (DR_REG_SPI_MEM_BASE(i) + 0x7c) /** SPI_MEM_BUF9 : R/W/SS; bitpos: [31:0]; default: 0; * data buffer */ @@ -849,7 +849,7 @@ extern "C" { /** SPI_MEM_W10_REG register * SPI1 memory data buffer10 */ -#define SPI_MEM_W10_REG(i) (REG_SPI_MEM_BASE(i) + 0x80) +#define SPI_MEM_W10_REG(i) (DR_REG_SPI_MEM_BASE(i) + 0x80) /** SPI_MEM_BUF10 : R/W/SS; bitpos: [31:0]; default: 0; * data buffer */ @@ -861,7 +861,7 @@ extern "C" { /** SPI_MEM_W11_REG register * SPI1 memory data buffer11 */ -#define SPI_MEM_W11_REG(i) (REG_SPI_MEM_BASE(i) + 0x84) +#define SPI_MEM_W11_REG(i) (DR_REG_SPI_MEM_BASE(i) + 0x84) /** SPI_MEM_BUF11 : R/W/SS; bitpos: [31:0]; default: 0; * data buffer */ @@ -873,7 +873,7 @@ extern "C" { /** SPI_MEM_W12_REG register * SPI1 memory data buffer12 */ -#define SPI_MEM_W12_REG(i) (REG_SPI_MEM_BASE(i) + 0x88) +#define SPI_MEM_W12_REG(i) (DR_REG_SPI_MEM_BASE(i) + 0x88) /** SPI_MEM_BUF12 : R/W/SS; bitpos: [31:0]; default: 0; * data buffer */ @@ -885,7 +885,7 @@ extern "C" { /** SPI_MEM_W13_REG register * SPI1 memory data buffer13 */ -#define SPI_MEM_W13_REG(i) (REG_SPI_MEM_BASE(i) + 0x8c) +#define SPI_MEM_W13_REG(i) (DR_REG_SPI_MEM_BASE(i) + 0x8c) /** SPI_MEM_BUF13 : R/W/SS; bitpos: [31:0]; default: 0; * data buffer */ @@ -897,7 +897,7 @@ extern "C" { /** SPI_MEM_W14_REG register * SPI1 memory data buffer14 */ -#define SPI_MEM_W14_REG(i) (REG_SPI_MEM_BASE(i) + 0x90) +#define SPI_MEM_W14_REG(i) (DR_REG_SPI_MEM_BASE(i) + 0x90) /** SPI_MEM_BUF14 : R/W/SS; bitpos: [31:0]; default: 0; * data buffer */ @@ -909,7 +909,7 @@ extern "C" { /** SPI_MEM_W15_REG register * SPI1 memory data buffer15 */ -#define SPI_MEM_W15_REG(i) (REG_SPI_MEM_BASE(i) + 0x94) +#define SPI_MEM_W15_REG(i) (DR_REG_SPI_MEM_BASE(i) + 0x94) /** SPI_MEM_BUF15 : R/W/SS; bitpos: [31:0]; default: 0; * data buffer */ @@ -921,7 +921,7 @@ extern "C" { /** SPI_MEM_FLASH_WAITI_CTRL_REG register * SPI1 wait idle control register */ -#define SPI_MEM_FLASH_WAITI_CTRL_REG(i) (REG_SPI_MEM_BASE(i) + 0x98) +#define SPI_MEM_FLASH_WAITI_CTRL_REG(i) (DR_REG_SPI_MEM_BASE(i) + 0x98) /** SPI_MEM_WAITI_EN : R/W; bitpos: [0]; default: 1; * 1: The hardware will wait idle after SE/PP/WRSR automatically, and hardware auto * Suspend/Resume can be enabled. 0: The functions of hardware wait idle and auto @@ -980,7 +980,7 @@ extern "C" { /** SPI_MEM_FLASH_SUS_CTRL_REG register * SPI1 flash suspend control register */ -#define SPI_MEM_FLASH_SUS_CTRL_REG(i) (REG_SPI_MEM_BASE(i) + 0x9c) +#define SPI_MEM_FLASH_SUS_CTRL_REG(i) (DR_REG_SPI_MEM_BASE(i) + 0x9c) /** SPI_MEM_FLASH_PER : R/W/SC; bitpos: [0]; default: 0; * program erase resume bit, program erase suspend operation will be triggered when * the bit is set. The bit will be cleared once the operation done.1: enable 0: @@ -1078,7 +1078,7 @@ extern "C" { /** SPI_MEM_FLASH_SUS_CMD_REG register * SPI1 flash suspend command register */ -#define SPI_MEM_FLASH_SUS_CMD_REG(i) (REG_SPI_MEM_BASE(i) + 0xa0) +#define SPI_MEM_FLASH_SUS_CMD_REG(i) (DR_REG_SPI_MEM_BASE(i) + 0xa0) /** SPI_MEM_FLASH_PES_COMMAND : R/W; bitpos: [15:0]; default: 30069; * Program/Erase suspend command. */ @@ -1098,7 +1098,7 @@ extern "C" { /** SPI_MEM_SUS_STATUS_REG register * SPI1 flash suspend status register */ -#define SPI_MEM_SUS_STATUS_REG(i) (REG_SPI_MEM_BASE(i) + 0xa4) +#define SPI_MEM_SUS_STATUS_REG(i) (DR_REG_SPI_MEM_BASE(i) + 0xa4) /** SPI_MEM_FLASH_SUS : R/W/SS/SC; bitpos: [0]; default: 0; * The status of flash suspend, only used in SPI1. */ @@ -1187,7 +1187,7 @@ extern "C" { /** SPI_MEM_FLASH_WAITI_CTRL1_REG register * SPI1 wait idle control register */ -#define SPI_MEM_FLASH_WAITI_CTRL1_REG(i) (REG_SPI_MEM_BASE(i) + 0xac) +#define SPI_MEM_FLASH_WAITI_CTRL1_REG(i) (DR_REG_SPI_MEM_BASE(i) + 0xac) /** SPI_MEM_WAITI_IDLE_DELAY_TIME : R/W; bitpos: [9:0]; default: 0; * SPI1 wait idle gap time configuration. SPI1 slv fsm will count during SPI1 IDLE. */ @@ -1206,7 +1206,7 @@ extern "C" { /** SPI_MEM_INT_ENA_REG register * SPI1 interrupt enable register */ -#define SPI_MEM_INT_ENA_REG(i) (REG_SPI_MEM_BASE(i) + 0xc0) +#define SPI_MEM_INT_ENA_REG(i) (DR_REG_SPI_MEM_BASE(i) + 0xc0) /** SPI_MEM_PER_END_INT_ENA : R/W; bitpos: [0]; default: 0; * The enable bit for SPI_MEM_PER_END_INT interrupt. */ @@ -1253,7 +1253,7 @@ extern "C" { /** SPI_MEM_INT_CLR_REG register * SPI1 interrupt clear register */ -#define SPI_MEM_INT_CLR_REG(i) (REG_SPI_MEM_BASE(i) + 0xc4) +#define SPI_MEM_INT_CLR_REG(i) (DR_REG_SPI_MEM_BASE(i) + 0xc4) /** SPI_MEM_PER_END_INT_CLR : WT; bitpos: [0]; default: 0; * The clear bit for SPI_MEM_PER_END_INT interrupt. */ @@ -1300,7 +1300,7 @@ extern "C" { /** SPI_MEM_INT_RAW_REG register * SPI1 interrupt raw register */ -#define SPI_MEM_INT_RAW_REG(i) (REG_SPI_MEM_BASE(i) + 0xc8) +#define SPI_MEM_INT_RAW_REG(i) (DR_REG_SPI_MEM_BASE(i) + 0xc8) /** SPI_MEM_PER_END_INT_RAW : R/WTC/SS; bitpos: [0]; default: 0; * The raw bit for SPI_MEM_PER_END_INT interrupt. 1: Triggered when Auto Resume * command (0x7A) is sent and flash is resumed successfully. 0: Others. @@ -1356,7 +1356,7 @@ extern "C" { /** SPI_MEM_INT_ST_REG register * SPI1 interrupt status register */ -#define SPI_MEM_INT_ST_REG(i) (REG_SPI_MEM_BASE(i) + 0xcc) +#define SPI_MEM_INT_ST_REG(i) (DR_REG_SPI_MEM_BASE(i) + 0xcc) /** SPI_MEM_PER_END_INT_ST : RO; bitpos: [0]; default: 0; * The status bit for SPI_MEM_PER_END_INT interrupt. */ @@ -1403,7 +1403,7 @@ extern "C" { /** SPI_MEM_DDR_REG register * SPI1 DDR control register */ -#define SPI_MEM_DDR_REG(i) (REG_SPI_MEM_BASE(i) + 0xd4) +#define SPI_MEM_DDR_REG(i) (DR_REG_SPI_MEM_BASE(i) + 0xd4) /** SPI_FMEM_DDR_EN : HRO; bitpos: [0]; default: 0; * 1: in ddr mode, 0 in sdr mode */ @@ -1512,7 +1512,7 @@ extern "C" { /** SPI_MEM_TIMING_CALI_REG register * SPI1 timing control register */ -#define SPI_MEM_TIMING_CALI_REG(i) (REG_SPI_MEM_BASE(i) + 0x180) +#define SPI_MEM_TIMING_CALI_REG(i) (DR_REG_SPI_MEM_BASE(i) + 0x180) /** SPI_MEM_TIMING_CALI : R/W; bitpos: [1]; default: 0; * The bit is used to enable timing auto-calibration for all reading operations. */ @@ -1531,7 +1531,7 @@ extern "C" { /** SPI_MEM_CLOCK_GATE_REG register * SPI1 clk_gate register */ -#define SPI_MEM_CLOCK_GATE_REG(i) (REG_SPI_MEM_BASE(i) + 0x200) +#define SPI_MEM_CLOCK_GATE_REG(i) (DR_REG_SPI_MEM_BASE(i) + 0x200) /** SPI_MEM_CLK_EN : R/W; bitpos: [0]; default: 1; * Register clock gate enable signal. 1: Enable. 0: Disable. */ @@ -1543,7 +1543,7 @@ extern "C" { /** SPI_MEM_DATE_REG register * Version control register */ -#define SPI_MEM_DATE_REG(i) (REG_SPI_MEM_BASE(i) + 0x3fc) +#define SPI_MEM_DATE_REG(i) (DR_REG_SPI_MEM_BASE(i) + 0x3fc) /** SPI_MEM_DATE : R/W; bitpos: [27:0]; default: 37786176; * Version control register */ diff --git a/components/soc/esp32h21/register/soc/spi_mem_c_reg.h b/components/soc/esp32h21/register/soc/spi_mem_c_reg.h index 2e78ce42068..04d77b6a1a8 100644 --- a/components/soc/esp32h21/register/soc/spi_mem_c_reg.h +++ b/components/soc/esp32h21/register/soc/spi_mem_c_reg.h @@ -14,7 +14,7 @@ extern "C" { /** SPI_MEM_CMD_REG register * SPI0 FSM status register */ -#define SPI_MEM_CMD_REG(i) (REG_SPI_MEM_BASE(i) + 0x0) +#define SPI_MEM_CMD_REG(i) (DR_REG_SPI_MEM_BASE(i) + 0x0) /** SPI_MEM_MST_ST : RO; bitpos: [3:0]; default: 0; * The current status of SPI0 master FSM: spi0_mst_st. 0: idle state, 1:SPI0_GRANT , * 2: program/erase suspend state, 3: SPI0 read data state, 4: wait cache/EDMA sent @@ -46,7 +46,7 @@ extern "C" { /** SPI_MEM_ADDR_REG register * SPI0 USR_CMD address register */ -#define SPI_MEM_ADDR_REG(i) (REG_SPI_MEM_BASE(i) + 0x4) +#define SPI_MEM_ADDR_REG(i) (DR_REG_SPI_MEM_BASE(i) + 0x4) /** SPI_MEM_USR_ADDR_VALUE : HRO; bitpos: [31:0]; default: 0; * In SPI0 USR_CMD mode when SPI_MEM_USR is set, it is the memory address. */ @@ -58,7 +58,7 @@ extern "C" { /** SPI_MEM_CTRL_REG register * SPI0 control register. */ -#define SPI_MEM_CTRL_REG(i) (REG_SPI_MEM_BASE(i) + 0x8) +#define SPI_MEM_CTRL_REG(i) (DR_REG_SPI_MEM_BASE(i) + 0x8) /** SPI_MEM_WDUMMY_DQS_ALWAYS_OUT : HRO; bitpos: [0]; default: 0; * In the dummy phase of an MSPI write data transfer when accesses to flash, the level * of SPI_DQS is output by the MSPI controller. @@ -207,7 +207,7 @@ extern "C" { /** SPI_MEM_CTRL1_REG register * SPI0 control1 register. */ -#define SPI_MEM_CTRL1_REG(i) (REG_SPI_MEM_BASE(i) + 0xc) +#define SPI_MEM_CTRL1_REG(i) (DR_REG_SPI_MEM_BASE(i) + 0xc) /** SPI_MEM_CLK_MODE : R/W; bitpos: [1:0]; default: 0; * SPI clock mode bits. 0: SPI clock is off when CS inactive 1: SPI clock is delayed * one cycle after CS inactive 2: SPI clock is delayed two cycles after CS inactive 3: @@ -302,7 +302,7 @@ extern "C" { /** SPI_MEM_CTRL2_REG register * SPI0 control2 register. */ -#define SPI_MEM_CTRL2_REG(i) (REG_SPI_MEM_BASE(i) + 0x10) +#define SPI_MEM_CTRL2_REG(i) (DR_REG_SPI_MEM_BASE(i) + 0x10) /** SPI_MEM_CS_SETUP_TIME : R/W; bitpos: [4:0]; default: 1; * (cycles-1) of prepare phase by SPI Bus clock, this bits are combined with * SPI_MEM_CS_SETUP bit. @@ -372,7 +372,7 @@ extern "C" { /** SPI_MEM_CLOCK_REG register * SPI clock division control register. */ -#define SPI_MEM_CLOCK_REG(i) (REG_SPI_MEM_BASE(i) + 0x14) +#define SPI_MEM_CLOCK_REG(i) (DR_REG_SPI_MEM_BASE(i) + 0x14) /** SPI_MEM_CLKCNT_L : R/W; bitpos: [7:0]; default: 3; * In the master mode it must be equal to SPI_MEM_CLKCNT_N. */ @@ -407,7 +407,7 @@ extern "C" { /** SPI_MEM_USER_REG register * SPI0 user register. */ -#define SPI_MEM_USER_REG(i) (REG_SPI_MEM_BASE(i) + 0x18) +#define SPI_MEM_USER_REG(i) (DR_REG_SPI_MEM_BASE(i) + 0x18) /** SPI_MEM_CS_HOLD : R/W; bitpos: [6]; default: 0; * spi cs keep low when spi is in done phase. 1: enable 0: disable. */ @@ -447,7 +447,7 @@ extern "C" { /** SPI_MEM_USER1_REG register * SPI0 user1 register. */ -#define SPI_MEM_USER1_REG(i) (REG_SPI_MEM_BASE(i) + 0x1c) +#define SPI_MEM_USER1_REG(i) (DR_REG_SPI_MEM_BASE(i) + 0x1c) /** SPI_MEM_USR_DUMMY_CYCLELEN : R/W; bitpos: [5:0]; default: 7; * The length in spi_mem_clk cycles of dummy phase. The register value shall be * (cycle_num-1). @@ -474,7 +474,7 @@ extern "C" { /** SPI_MEM_USER2_REG register * SPI0 user2 register. */ -#define SPI_MEM_USER2_REG(i) (REG_SPI_MEM_BASE(i) + 0x20) +#define SPI_MEM_USER2_REG(i) (DR_REG_SPI_MEM_BASE(i) + 0x20) /** SPI_MEM_USR_COMMAND_VALUE : R/W; bitpos: [15:0]; default: 0; * The value of command. */ @@ -493,7 +493,7 @@ extern "C" { /** SPI_MEM_MISC_REG register * SPI0 misc register */ -#define SPI_MEM_MISC_REG(i) (REG_SPI_MEM_BASE(i) + 0x34) +#define SPI_MEM_MISC_REG(i) (DR_REG_SPI_MEM_BASE(i) + 0x34) /** SPI_MEM_FSUB_PIN : HRO; bitpos: [7]; default: 0; * For SPI0, flash is connected to SUBPINs. */ @@ -526,7 +526,7 @@ extern "C" { /** SPI_MEM_CACHE_FCTRL_REG register * SPI0 bit mode control register. */ -#define SPI_MEM_CACHE_FCTRL_REG(i) (REG_SPI_MEM_BASE(i) + 0x3c) +#define SPI_MEM_CACHE_FCTRL_REG(i) (DR_REG_SPI_MEM_BASE(i) + 0x3c) /** SPI_SAME_AW_AR_ADDR_CHK_EN : HRO; bitpos: [30]; default: 1; * Set this bit to check AXI read/write the same address region. */ @@ -546,7 +546,7 @@ extern "C" { /** SPI_MEM_SRAM_CMD_REG register * SPI0 external RAM mode control register */ -#define SPI_MEM_SRAM_CMD_REG(i) (REG_SPI_MEM_BASE(i) + 0x44) +#define SPI_MEM_SRAM_CMD_REG(i) (DR_REG_SPI_MEM_BASE(i) + 0x44) /** SPI_SMEM_WDUMMY_DQS_ALWAYS_OUT : HRO; bitpos: [24]; default: 0; * In the dummy phase of an MSPI write data transfer when accesses to external RAM, * the level of SPI_DQS is output by the MSPI controller. @@ -583,7 +583,7 @@ extern "C" { /** SPI_MEM_FSM_REG register * SPI0 FSM status register */ -#define SPI_MEM_FSM_REG(i) (REG_SPI_MEM_BASE(i) + 0x54) +#define SPI_MEM_FSM_REG(i) (DR_REG_SPI_MEM_BASE(i) + 0x54) /** SPI_MEM_LOCK_DELAY_TIME : R/W; bitpos: [18:7]; default: 4; * The lock delay time of SPI0/1 arbiter by spi0_slv_st, after PER is sent by SPI1. */ @@ -609,7 +609,7 @@ extern "C" { /** SPI_MEM_INT_ENA_REG register * SPI0 interrupt enable register */ -#define SPI_MEM_INT_ENA_REG(i) (REG_SPI_MEM_BASE(i) + 0xc0) +#define SPI_MEM_INT_ENA_REG(i) (DR_REG_SPI_MEM_BASE(i) + 0xc0) /** SPI_MEM_SLV_ST_END_INT_ENA : R/W; bitpos: [3]; default: 0; * The enable bit for SPI_MEM_SLV_ST_END_INT interrupt. */ @@ -677,7 +677,7 @@ extern "C" { /** SPI_MEM_INT_CLR_REG register * SPI0 interrupt clear register */ -#define SPI_MEM_INT_CLR_REG(i) (REG_SPI_MEM_BASE(i) + 0xc4) +#define SPI_MEM_INT_CLR_REG(i) (DR_REG_SPI_MEM_BASE(i) + 0xc4) /** SPI_MEM_SLV_ST_END_INT_CLR : WT; bitpos: [3]; default: 0; * The clear bit for SPI_MEM_SLV_ST_END_INT interrupt. */ @@ -745,7 +745,7 @@ extern "C" { /** SPI_MEM_INT_RAW_REG register * SPI0 interrupt raw register */ -#define SPI_MEM_INT_RAW_REG(i) (REG_SPI_MEM_BASE(i) + 0xc8) +#define SPI_MEM_INT_RAW_REG(i) (DR_REG_SPI_MEM_BASE(i) + 0xc8) /** SPI_MEM_SLV_ST_END_INT_RAW : R/WTC/SS; bitpos: [3]; default: 0; * The raw bit for SPI_MEM_SLV_ST_END_INT interrupt. 1: Triggered when spi0_slv_st is * changed from non idle state to idle state. It means that SPI_CS raises high. 0: @@ -831,7 +831,7 @@ extern "C" { /** SPI_MEM_INT_ST_REG register * SPI0 interrupt status register */ -#define SPI_MEM_INT_ST_REG(i) (REG_SPI_MEM_BASE(i) + 0xcc) +#define SPI_MEM_INT_ST_REG(i) (DR_REG_SPI_MEM_BASE(i) + 0xcc) /** SPI_MEM_SLV_ST_END_INT_ST : RO; bitpos: [3]; default: 0; * The status bit for SPI_MEM_SLV_ST_END_INT interrupt. */ @@ -899,7 +899,7 @@ extern "C" { /** SPI_MEM_DDR_REG register * SPI0 flash DDR mode control register */ -#define SPI_MEM_DDR_REG(i) (REG_SPI_MEM_BASE(i) + 0xd4) +#define SPI_MEM_DDR_REG(i) (DR_REG_SPI_MEM_BASE(i) + 0xd4) /** SPI_FMEM_DDR_EN : HRO; bitpos: [0]; default: 0; * 1: in DDR mode, 0 in SDR mode */ @@ -1024,7 +1024,7 @@ extern "C" { /** SPI_SMEM_DDR_REG register * SPI0 external RAM DDR mode control register */ -#define SPI_SMEM_DDR_REG(i) (REG_SPI_MEM_BASE(i) + 0xd8) +#define SPI_SMEM_DDR_REG(i) (DR_REG_SPI_MEM_BASE(i) + 0xd8) /** SPI_SMEM_DDR_EN : HRO; bitpos: [0]; default: 0; * 1: in DDR mode, 0 in SDR mode */ @@ -1150,7 +1150,7 @@ extern "C" { /** SPI_FMEM_PMS0_ATTR_REG register * SPI1 flash PMS section 0 attribute register */ -#define SPI_FMEM_PMS0_ATTR_REG(i) (REG_SPI_MEM_BASE(i) + 0x100) +#define SPI_FMEM_PMS0_ATTR_REG(i) (DR_REG_SPI_MEM_BASE(i) + 0x100) /** SPI_FMEM_PMS0_RD_ATTR : R/W; bitpos: [0]; default: 1; * 1: SPI1 flash PMS section 0 read accessible. 0: Not allowed. */ @@ -1178,7 +1178,7 @@ extern "C" { /** SPI_FMEM_PMS1_ATTR_REG register * SPI1 flash PMS section 1 attribute register */ -#define SPI_FMEM_PMS1_ATTR_REG(i) (REG_SPI_MEM_BASE(i) + 0x104) +#define SPI_FMEM_PMS1_ATTR_REG(i) (DR_REG_SPI_MEM_BASE(i) + 0x104) /** SPI_FMEM_PMS1_RD_ATTR : R/W; bitpos: [0]; default: 1; * 1: SPI1 flash PMS section 1 read accessible. 0: Not allowed. */ @@ -1206,7 +1206,7 @@ extern "C" { /** SPI_FMEM_PMS2_ATTR_REG register * SPI1 flash PMS section 2 attribute register */ -#define SPI_FMEM_PMS2_ATTR_REG(i) (REG_SPI_MEM_BASE(i) + 0x108) +#define SPI_FMEM_PMS2_ATTR_REG(i) (DR_REG_SPI_MEM_BASE(i) + 0x108) /** SPI_FMEM_PMS2_RD_ATTR : R/W; bitpos: [0]; default: 1; * 1: SPI1 flash PMS section 2 read accessible. 0: Not allowed. */ @@ -1234,7 +1234,7 @@ extern "C" { /** SPI_FMEM_PMS3_ATTR_REG register * SPI1 flash PMS section 3 attribute register */ -#define SPI_FMEM_PMS3_ATTR_REG(i) (REG_SPI_MEM_BASE(i) + 0x10c) +#define SPI_FMEM_PMS3_ATTR_REG(i) (DR_REG_SPI_MEM_BASE(i) + 0x10c) /** SPI_FMEM_PMS3_RD_ATTR : R/W; bitpos: [0]; default: 1; * 1: SPI1 flash PMS section 3 read accessible. 0: Not allowed. */ @@ -1262,7 +1262,7 @@ extern "C" { /** SPI_FMEM_PMS0_ADDR_REG register * SPI1 flash PMS section 0 start address register */ -#define SPI_FMEM_PMS0_ADDR_REG(i) (REG_SPI_MEM_BASE(i) + 0x110) +#define SPI_FMEM_PMS0_ADDR_REG(i) (DR_REG_SPI_MEM_BASE(i) + 0x110) /** SPI_FMEM_PMS0_ADDR_S : R/W; bitpos: [28:0]; default: 0; * SPI1 flash PMS section 0 start address value */ @@ -1274,7 +1274,7 @@ extern "C" { /** SPI_FMEM_PMS1_ADDR_REG register * SPI1 flash PMS section 1 start address register */ -#define SPI_FMEM_PMS1_ADDR_REG(i) (REG_SPI_MEM_BASE(i) + 0x114) +#define SPI_FMEM_PMS1_ADDR_REG(i) (DR_REG_SPI_MEM_BASE(i) + 0x114) /** SPI_FMEM_PMS1_ADDR_S : R/W; bitpos: [28:0]; default: 0; * SPI1 flash PMS section 1 start address value */ @@ -1286,7 +1286,7 @@ extern "C" { /** SPI_FMEM_PMS2_ADDR_REG register * SPI1 flash PMS section 2 start address register */ -#define SPI_FMEM_PMS2_ADDR_REG(i) (REG_SPI_MEM_BASE(i) + 0x118) +#define SPI_FMEM_PMS2_ADDR_REG(i) (DR_REG_SPI_MEM_BASE(i) + 0x118) /** SPI_FMEM_PMS2_ADDR_S : R/W; bitpos: [28:0]; default: 0; * SPI1 flash PMS section 2 start address value */ @@ -1298,7 +1298,7 @@ extern "C" { /** SPI_FMEM_PMS3_ADDR_REG register * SPI1 flash PMS section 3 start address register */ -#define SPI_FMEM_PMS3_ADDR_REG(i) (REG_SPI_MEM_BASE(i) + 0x11c) +#define SPI_FMEM_PMS3_ADDR_REG(i) (DR_REG_SPI_MEM_BASE(i) + 0x11c) /** SPI_FMEM_PMS3_ADDR_S : R/W; bitpos: [28:0]; default: 0; * SPI1 flash PMS section 3 start address value */ @@ -1310,7 +1310,7 @@ extern "C" { /** SPI_FMEM_PMS0_SIZE_REG register * SPI1 flash PMS section 0 start address register */ -#define SPI_FMEM_PMS0_SIZE_REG(i) (REG_SPI_MEM_BASE(i) + 0x120) +#define SPI_FMEM_PMS0_SIZE_REG(i) (DR_REG_SPI_MEM_BASE(i) + 0x120) /** SPI_FMEM_PMS0_SIZE : R/W; bitpos: [16:0]; default: 4096; * SPI1 flash PMS section 0 address region is (SPI_FMEM_PMS0_ADDR_S, * SPI_FMEM_PMS0_ADDR_S + SPI_FMEM_PMS0_SIZE) @@ -1323,7 +1323,7 @@ extern "C" { /** SPI_FMEM_PMS1_SIZE_REG register * SPI1 flash PMS section 1 start address register */ -#define SPI_FMEM_PMS1_SIZE_REG(i) (REG_SPI_MEM_BASE(i) + 0x124) +#define SPI_FMEM_PMS1_SIZE_REG(i) (DR_REG_SPI_MEM_BASE(i) + 0x124) /** SPI_FMEM_PMS1_SIZE : R/W; bitpos: [16:0]; default: 4096; * SPI1 flash PMS section 1 address region is (SPI_FMEM_PMS1_ADDR_S, * SPI_FMEM_PMS1_ADDR_S + SPI_FMEM_PMS1_SIZE) @@ -1336,7 +1336,7 @@ extern "C" { /** SPI_FMEM_PMS2_SIZE_REG register * SPI1 flash PMS section 2 start address register */ -#define SPI_FMEM_PMS2_SIZE_REG(i) (REG_SPI_MEM_BASE(i) + 0x128) +#define SPI_FMEM_PMS2_SIZE_REG(i) (DR_REG_SPI_MEM_BASE(i) + 0x128) /** SPI_FMEM_PMS2_SIZE : R/W; bitpos: [16:0]; default: 4096; * SPI1 flash PMS section 2 address region is (SPI_FMEM_PMS2_ADDR_S, * SPI_FMEM_PMS2_ADDR_S + SPI_FMEM_PMS2_SIZE) @@ -1349,7 +1349,7 @@ extern "C" { /** SPI_FMEM_PMS3_SIZE_REG register * SPI1 flash PMS section 3 start address register */ -#define SPI_FMEM_PMS3_SIZE_REG(i) (REG_SPI_MEM_BASE(i) + 0x12c) +#define SPI_FMEM_PMS3_SIZE_REG(i) (DR_REG_SPI_MEM_BASE(i) + 0x12c) /** SPI_FMEM_PMS3_SIZE : R/W; bitpos: [16:0]; default: 4096; * SPI1 flash PMS section 3 address region is (SPI_FMEM_PMS3_ADDR_S, * SPI_FMEM_PMS3_ADDR_S + SPI_FMEM_PMS3_SIZE) @@ -1362,7 +1362,7 @@ extern "C" { /** SPI_SMEM_PMS0_ATTR_REG register * SPI1 external RAM PMS section 0 attribute register */ -#define SPI_SMEM_PMS0_ATTR_REG(i) (REG_SPI_MEM_BASE(i) + 0x130) +#define SPI_SMEM_PMS0_ATTR_REG(i) (DR_REG_SPI_MEM_BASE(i) + 0x130) /** SPI_SMEM_PMS0_RD_ATTR : R/W; bitpos: [0]; default: 1; * 1: SPI1 external RAM PMS section 0 read accessible. 0: Not allowed. */ @@ -1390,7 +1390,7 @@ extern "C" { /** SPI_SMEM_PMS1_ATTR_REG register * SPI1 external RAM PMS section 1 attribute register */ -#define SPI_SMEM_PMS1_ATTR_REG(i) (REG_SPI_MEM_BASE(i) + 0x134) +#define SPI_SMEM_PMS1_ATTR_REG(i) (DR_REG_SPI_MEM_BASE(i) + 0x134) /** SPI_SMEM_PMS1_RD_ATTR : R/W; bitpos: [0]; default: 1; * 1: SPI1 external RAM PMS section 1 read accessible. 0: Not allowed. */ @@ -1418,7 +1418,7 @@ extern "C" { /** SPI_SMEM_PMS2_ATTR_REG register * SPI1 external RAM PMS section 2 attribute register */ -#define SPI_SMEM_PMS2_ATTR_REG(i) (REG_SPI_MEM_BASE(i) + 0x138) +#define SPI_SMEM_PMS2_ATTR_REG(i) (DR_REG_SPI_MEM_BASE(i) + 0x138) /** SPI_SMEM_PMS2_RD_ATTR : R/W; bitpos: [0]; default: 1; * 1: SPI1 external RAM PMS section 2 read accessible. 0: Not allowed. */ @@ -1446,7 +1446,7 @@ extern "C" { /** SPI_SMEM_PMS3_ATTR_REG register * SPI1 external RAM PMS section 3 attribute register */ -#define SPI_SMEM_PMS3_ATTR_REG(i) (REG_SPI_MEM_BASE(i) + 0x13c) +#define SPI_SMEM_PMS3_ATTR_REG(i) (DR_REG_SPI_MEM_BASE(i) + 0x13c) /** SPI_SMEM_PMS3_RD_ATTR : R/W; bitpos: [0]; default: 1; * 1: SPI1 external RAM PMS section 3 read accessible. 0: Not allowed. */ @@ -1474,7 +1474,7 @@ extern "C" { /** SPI_SMEM_PMS0_ADDR_REG register * SPI1 external RAM PMS section 0 start address register */ -#define SPI_SMEM_PMS0_ADDR_REG(i) (REG_SPI_MEM_BASE(i) + 0x140) +#define SPI_SMEM_PMS0_ADDR_REG(i) (DR_REG_SPI_MEM_BASE(i) + 0x140) /** SPI_SMEM_PMS0_ADDR_S : HRO; bitpos: [28:0]; default: 0; * SPI1 external RAM PMS section 0 start address value */ @@ -1486,7 +1486,7 @@ extern "C" { /** SPI_SMEM_PMS1_ADDR_REG register * SPI1 external RAM PMS section 1 start address register */ -#define SPI_SMEM_PMS1_ADDR_REG(i) (REG_SPI_MEM_BASE(i) + 0x144) +#define SPI_SMEM_PMS1_ADDR_REG(i) (DR_REG_SPI_MEM_BASE(i) + 0x144) /** SPI_SMEM_PMS1_ADDR_S : HRO; bitpos: [28:0]; default: 0; * SPI1 external RAM PMS section 1 start address value */ @@ -1498,7 +1498,7 @@ extern "C" { /** SPI_SMEM_PMS2_ADDR_REG register * SPI1 external RAM PMS section 2 start address register */ -#define SPI_SMEM_PMS2_ADDR_REG(i) (REG_SPI_MEM_BASE(i) + 0x148) +#define SPI_SMEM_PMS2_ADDR_REG(i) (DR_REG_SPI_MEM_BASE(i) + 0x148) /** SPI_SMEM_PMS2_ADDR_S : HRO; bitpos: [28:0]; default: 0; * SPI1 external RAM PMS section 2 start address value */ @@ -1510,7 +1510,7 @@ extern "C" { /** SPI_SMEM_PMS3_ADDR_REG register * SPI1 external RAM PMS section 3 start address register */ -#define SPI_SMEM_PMS3_ADDR_REG(i) (REG_SPI_MEM_BASE(i) + 0x14c) +#define SPI_SMEM_PMS3_ADDR_REG(i) (DR_REG_SPI_MEM_BASE(i) + 0x14c) /** SPI_SMEM_PMS3_ADDR_S : HRO; bitpos: [28:0]; default: 0; * SPI1 external RAM PMS section 3 start address value */ @@ -1522,7 +1522,7 @@ extern "C" { /** SPI_SMEM_PMS0_SIZE_REG register * SPI1 external RAM PMS section 0 start address register */ -#define SPI_SMEM_PMS0_SIZE_REG(i) (REG_SPI_MEM_BASE(i) + 0x150) +#define SPI_SMEM_PMS0_SIZE_REG(i) (DR_REG_SPI_MEM_BASE(i) + 0x150) /** SPI_SMEM_PMS0_SIZE : HRO; bitpos: [16:0]; default: 4096; * SPI1 external RAM PMS section 0 address region is (SPI_SMEM_PMS0_ADDR_S, * SPI_SMEM_PMS0_ADDR_S + SPI_SMEM_PMS0_SIZE) @@ -1535,7 +1535,7 @@ extern "C" { /** SPI_SMEM_PMS1_SIZE_REG register * SPI1 external RAM PMS section 1 start address register */ -#define SPI_SMEM_PMS1_SIZE_REG(i) (REG_SPI_MEM_BASE(i) + 0x154) +#define SPI_SMEM_PMS1_SIZE_REG(i) (DR_REG_SPI_MEM_BASE(i) + 0x154) /** SPI_SMEM_PMS1_SIZE : HRO; bitpos: [16:0]; default: 4096; * SPI1 external RAM PMS section 1 address region is (SPI_SMEM_PMS1_ADDR_S, * SPI_SMEM_PMS1_ADDR_S + SPI_SMEM_PMS1_SIZE) @@ -1548,7 +1548,7 @@ extern "C" { /** SPI_SMEM_PMS2_SIZE_REG register * SPI1 external RAM PMS section 2 start address register */ -#define SPI_SMEM_PMS2_SIZE_REG(i) (REG_SPI_MEM_BASE(i) + 0x158) +#define SPI_SMEM_PMS2_SIZE_REG(i) (DR_REG_SPI_MEM_BASE(i) + 0x158) /** SPI_SMEM_PMS2_SIZE : HRO; bitpos: [16:0]; default: 4096; * SPI1 external RAM PMS section 2 address region is (SPI_SMEM_PMS2_ADDR_S, * SPI_SMEM_PMS2_ADDR_S + SPI_SMEM_PMS2_SIZE) @@ -1561,7 +1561,7 @@ extern "C" { /** SPI_SMEM_PMS3_SIZE_REG register * SPI1 external RAM PMS section 3 start address register */ -#define SPI_SMEM_PMS3_SIZE_REG(i) (REG_SPI_MEM_BASE(i) + 0x15c) +#define SPI_SMEM_PMS3_SIZE_REG(i) (DR_REG_SPI_MEM_BASE(i) + 0x15c) /** SPI_SMEM_PMS3_SIZE : HRO; bitpos: [16:0]; default: 4096; * SPI1 external RAM PMS section 3 address region is (SPI_SMEM_PMS3_ADDR_S, * SPI_SMEM_PMS3_ADDR_S + SPI_SMEM_PMS3_SIZE) @@ -1574,7 +1574,7 @@ extern "C" { /** SPI_MEM_PMS_REJECT_REG register * SPI1 access reject register */ -#define SPI_MEM_PMS_REJECT_REG(i) (REG_SPI_MEM_BASE(i) + 0x160) +#define SPI_MEM_PMS_REJECT_REG(i) (DR_REG_SPI_MEM_BASE(i) + 0x160) /** SPI_MEM_PM_EN : R/W; bitpos: [27]; default: 0; * Set this bit to enable SPI0/1 transfer permission control function. */ @@ -1618,7 +1618,7 @@ extern "C" { /** SPI_MEM_PMS_REJECT_ADDR_REG register * SPI1 access reject addr register */ -#define SPI_MEM_PMS_REJECT_ADDR_REG(i) (REG_SPI_MEM_BASE(i) + 0x164) +#define SPI_MEM_PMS_REJECT_ADDR_REG(i) (DR_REG_SPI_MEM_BASE(i) + 0x164) /** SPI_MEM_REJECT_ADDR : R/SS/WTC; bitpos: [28:0]; default: 0; * This bits show the first SPI1 access error address. It is cleared by when * SPI_MEM_PMS_REJECT_INT_CLR bit is set. @@ -1631,7 +1631,7 @@ extern "C" { /** SPI_MEM_ECC_CTRL_REG register * MSPI ECC control register */ -#define SPI_MEM_ECC_CTRL_REG(i) (REG_SPI_MEM_BASE(i) + 0x168) +#define SPI_MEM_ECC_CTRL_REG(i) (DR_REG_SPI_MEM_BASE(i) + 0x168) /** SPI_MEM_ECC_ERR_CNT : HRO; bitpos: [10:5]; default: 0; * This bits show the error times of MSPI ECC read. It is cleared by when * SPI_MEM_ECC_ERR_INT_CLR bit is set. @@ -1699,7 +1699,7 @@ extern "C" { /** SPI_MEM_ECC_ERR_ADDR_REG register * MSPI ECC error address register */ -#define SPI_MEM_ECC_ERR_ADDR_REG(i) (REG_SPI_MEM_BASE(i) + 0x16c) +#define SPI_MEM_ECC_ERR_ADDR_REG(i) (DR_REG_SPI_MEM_BASE(i) + 0x16c) /** SPI_MEM_ECC_ERR_ADDR : HRO; bitpos: [28:0]; default: 0; * This bits show the first MSPI ECC error address. It is cleared by when * SPI_MEM_ECC_ERR_INT_CLR bit is set. @@ -1712,7 +1712,7 @@ extern "C" { /** SPI_MEM_AXI_ERR_ADDR_REG register * SPI0 AXI request error address. */ -#define SPI_MEM_AXI_ERR_ADDR_REG(i) (REG_SPI_MEM_BASE(i) + 0x170) +#define SPI_MEM_AXI_ERR_ADDR_REG(i) (DR_REG_SPI_MEM_BASE(i) + 0x170) /** SPI_MEM_AXI_ERR_ADDR : R/SS/WTC; bitpos: [28:0]; default: 0; * This bits show the first AXI write/read invalid error or AXI write flash error * address. It is cleared by when SPI_MEM_AXI_WADDR_ERR_INT_CLR, @@ -1726,7 +1726,7 @@ extern "C" { /** SPI_SMEM_ECC_CTRL_REG register * MSPI ECC control register */ -#define SPI_SMEM_ECC_CTRL_REG(i) (REG_SPI_MEM_BASE(i) + 0x174) +#define SPI_SMEM_ECC_CTRL_REG(i) (DR_REG_SPI_MEM_BASE(i) + 0x174) /** SPI_SMEM_ECC_ERR_INT_EN : HRO; bitpos: [17]; default: 0; * Set this bit to calculate the error times of MSPI ECC read when accesses to * external RAM. @@ -1756,7 +1756,7 @@ extern "C" { /** SPI_SMEM_AXI_ADDR_CTRL_REG register * SPI0 AXI address control register */ -#define SPI_SMEM_AXI_ADDR_CTRL_REG(i) (REG_SPI_MEM_BASE(i) + 0x178) +#define SPI_SMEM_AXI_ADDR_CTRL_REG(i) (DR_REG_SPI_MEM_BASE(i) + 0x178) /** SPI_MEM_ALL_FIFO_EMPTY : RO; bitpos: [26]; default: 1; * The empty status of all AFIFO and SYNC_FIFO in MSPI module. 1: All AXI transfers * and SPI0 transfers are done. 0: Others. @@ -1805,7 +1805,7 @@ extern "C" { /** SPI_MEM_AXI_ERR_RESP_EN_REG register * SPI0 AXI error response enable register */ -#define SPI_MEM_AXI_ERR_RESP_EN_REG(i) (REG_SPI_MEM_BASE(i) + 0x17c) +#define SPI_MEM_AXI_ERR_RESP_EN_REG(i) (DR_REG_SPI_MEM_BASE(i) + 0x17c) /** SPI_MEM_AW_RESP_EN_MMU_VLD : R/W; bitpos: [0]; default: 0; * Set this bit to enable AXI response function for mmu valid err in axi write trans. */ @@ -1895,7 +1895,7 @@ extern "C" { /** SPI_MEM_TIMING_CALI_REG register * SPI0 flash timing calibration register */ -#define SPI_MEM_TIMING_CALI_REG(i) (REG_SPI_MEM_BASE(i) + 0x180) +#define SPI_MEM_TIMING_CALI_REG(i) (DR_REG_SPI_MEM_BASE(i) + 0x180) /** SPI_MEM_TIMING_CLK_ENA : R/W; bitpos: [0]; default: 1; * The bit is used to enable timing adjust clock for all reading operations. */ @@ -1936,7 +1936,7 @@ extern "C" { /** SPI_MEM_DIN_MODE_REG register * MSPI flash input timing delay mode control register */ -#define SPI_MEM_DIN_MODE_REG(i) (REG_SPI_MEM_BASE(i) + 0x184) +#define SPI_MEM_DIN_MODE_REG(i) (DR_REG_SPI_MEM_BASE(i) + 0x184) /** SPI_MEM_DIN0_MODE : R/W; bitpos: [2:0]; default: 0; * the input signals are delayed by system clock cycles, 0: input without delayed, 1: * input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input @@ -2026,7 +2026,7 @@ extern "C" { /** SPI_MEM_DIN_NUM_REG register * MSPI flash input timing delay number control register */ -#define SPI_MEM_DIN_NUM_REG(i) (REG_SPI_MEM_BASE(i) + 0x188) +#define SPI_MEM_DIN_NUM_REG(i) (DR_REG_SPI_MEM_BASE(i) + 0x188) /** SPI_MEM_DIN0_NUM : R/W; bitpos: [1:0]; default: 0; * the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: * delayed by 2 cycles,... @@ -2103,7 +2103,7 @@ extern "C" { /** SPI_MEM_DOUT_MODE_REG register * MSPI flash output timing adjustment control register */ -#define SPI_MEM_DOUT_MODE_REG(i) (REG_SPI_MEM_BASE(i) + 0x18c) +#define SPI_MEM_DOUT_MODE_REG(i) (DR_REG_SPI_MEM_BASE(i) + 0x18c) /** SPI_MEM_DOUT0_MODE : R/W; bitpos: [0]; default: 0; * the output signals are delayed by system clock cycles, 0: output without delayed, * 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: @@ -2193,7 +2193,7 @@ extern "C" { /** SPI_SMEM_TIMING_CALI_REG register * MSPI external RAM timing calibration register */ -#define SPI_SMEM_TIMING_CALI_REG(i) (REG_SPI_MEM_BASE(i) + 0x190) +#define SPI_SMEM_TIMING_CALI_REG(i) (DR_REG_SPI_MEM_BASE(i) + 0x190) /** SPI_SMEM_TIMING_CLK_ENA : HRO; bitpos: [0]; default: 1; * For sram, the bit is used to enable timing adjust clock for all reading operations. */ @@ -2244,7 +2244,7 @@ extern "C" { /** SPI_SMEM_DIN_MODE_REG register * MSPI external RAM input timing delay mode control register */ -#define SPI_SMEM_DIN_MODE_REG(i) (REG_SPI_MEM_BASE(i) + 0x194) +#define SPI_SMEM_DIN_MODE_REG(i) (DR_REG_SPI_MEM_BASE(i) + 0x194) /** SPI_SMEM_DIN0_MODE : HRO; bitpos: [2:0]; default: 0; * the input signals are delayed by system clock cycles, 0: input without delayed, 1: * input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input @@ -2339,7 +2339,7 @@ extern "C" { /** SPI_SMEM_DIN_NUM_REG register * MSPI external RAM input timing delay number control register */ -#define SPI_SMEM_DIN_NUM_REG(i) (REG_SPI_MEM_BASE(i) + 0x198) +#define SPI_SMEM_DIN_NUM_REG(i) (DR_REG_SPI_MEM_BASE(i) + 0x198) /** SPI_SMEM_DIN0_NUM : HRO; bitpos: [1:0]; default: 0; * the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: * delayed by 2 cycles,... @@ -2416,7 +2416,7 @@ extern "C" { /** SPI_SMEM_DOUT_MODE_REG register * MSPI external RAM output timing adjustment control register */ -#define SPI_SMEM_DOUT_MODE_REG(i) (REG_SPI_MEM_BASE(i) + 0x19c) +#define SPI_SMEM_DOUT_MODE_REG(i) (DR_REG_SPI_MEM_BASE(i) + 0x19c) /** SPI_SMEM_DOUT0_MODE : HRO; bitpos: [0]; default: 0; * the output signals are delayed by system clock cycles, 0: output without delayed, * 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: @@ -2511,7 +2511,7 @@ extern "C" { /** SPI_SMEM_AC_REG register * MSPI external RAM ECC and SPI CS timing control register */ -#define SPI_SMEM_AC_REG(i) (REG_SPI_MEM_BASE(i) + 0x1a0) +#define SPI_SMEM_AC_REG(i) (DR_REG_SPI_MEM_BASE(i) + 0x1a0) /** SPI_SMEM_CS_SETUP : HRO; bitpos: [0]; default: 0; * For SPI0 and SPI1, spi cs is enable when spi is in prepare phase. 1: enable 0: * disable. @@ -2589,7 +2589,7 @@ extern "C" { /** SPI_MEM_CLOCK_GATE_REG register * SPI0 clock gate register */ -#define SPI_MEM_CLOCK_GATE_REG(i) (REG_SPI_MEM_BASE(i) + 0x200) +#define SPI_MEM_CLOCK_GATE_REG(i) (DR_REG_SPI_MEM_BASE(i) + 0x200) /** SPI_CLK_EN : R/W; bitpos: [0]; default: 1; * Register clock gate enable signal. 1: Enable. 0: Disable. */ @@ -2608,7 +2608,7 @@ extern "C" { /** SPI_MEM_NAND_FLASH_EN_REG register * NAND FLASH control register */ -#define SPI_MEM_NAND_FLASH_EN_REG(i) (REG_SPI_MEM_BASE(i) + 0x204) +#define SPI_MEM_NAND_FLASH_EN_REG(i) (DR_REG_SPI_MEM_BASE(i) + 0x204) /** SPI_MEM_NAND_FLASH_EN : HRO; bitpos: [0]; default: 0; * NAND FLASH function enable signal. 1: Enable NAND FLASH, Disable NOR FLASH. 0: * Disable NAND FLASH, Enable NOR FLASH. @@ -2652,7 +2652,7 @@ extern "C" { /** SPI_MEM_NAND_FLASH_SR_ADDR0_REG register * NAND FLASH SPI SEQ control register */ -#define SPI_MEM_NAND_FLASH_SR_ADDR0_REG(i) (REG_SPI_MEM_BASE(i) + 0x208) +#define SPI_MEM_NAND_FLASH_SR_ADDR0_REG(i) (DR_REG_SPI_MEM_BASE(i) + 0x208) /** SPI_MEM_NAND_FLASH_SR_ADDR0 : HRO; bitpos: [7:0]; default: 0; * configure state register address for SPI SEQ need. If OIP is in address C0H , user * could configure C0H into this register @@ -2689,7 +2689,7 @@ extern "C" { /** SPI_MEM_NAND_FLASH_SR_DIN0_REG register * NAND FLASH SPI SEQ control register */ -#define SPI_MEM_NAND_FLASH_SR_DIN0_REG(i) (REG_SPI_MEM_BASE(i) + 0x20c) +#define SPI_MEM_NAND_FLASH_SR_DIN0_REG(i) (DR_REG_SPI_MEM_BASE(i) + 0x20c) /** SPI_MEM_NAND_FLASH_SR_DIN0 : RO; bitpos: [7:0]; default: 0; * spi read state register data to this register for SPI SEQ need. * SPI_MEM_NAND_FLASH_SR_DIN0_REG corresponds to SPI_MEM_NAND_FLASH_SR_ADDR0_REG. @@ -2726,7 +2726,7 @@ extern "C" { /** SPI_MEM_NAND_FLASH_CFG_DATA0_REG register * NAND FLASH SPI SEQ control register */ -#define SPI_MEM_NAND_FLASH_CFG_DATA0_REG(i) (REG_SPI_MEM_BASE(i) + 0x210) +#define SPI_MEM_NAND_FLASH_CFG_DATA0_REG(i) (DR_REG_SPI_MEM_BASE(i) + 0x210) /** SPI_MEM_NAND_FLASH_CFG_DATA0 : HRO; bitpos: [15:0]; default: 0; * configure data for SPI SEQ din/dout need. The data could be use to configure NAND * FLASH or compare read data @@ -2747,7 +2747,7 @@ extern "C" { /** SPI_MEM_NAND_FLASH_CFG_DATA1_REG register * NAND FLASH SPI SEQ control register */ -#define SPI_MEM_NAND_FLASH_CFG_DATA1_REG(i) (REG_SPI_MEM_BASE(i) + 0x214) +#define SPI_MEM_NAND_FLASH_CFG_DATA1_REG(i) (DR_REG_SPI_MEM_BASE(i) + 0x214) /** SPI_MEM_NAND_FLASH_CFG_DATA2 : HRO; bitpos: [15:0]; default: 0; * configure data for SPI SEQ din/dout need. The data could be use to configure NAND * FLASH or compare read data @@ -2768,7 +2768,7 @@ extern "C" { /** SPI_MEM_NAND_FLASH_CFG_DATA2_REG register * NAND FLASH SPI SEQ control register */ -#define SPI_MEM_NAND_FLASH_CFG_DATA2_REG(i) (REG_SPI_MEM_BASE(i) + 0x218) +#define SPI_MEM_NAND_FLASH_CFG_DATA2_REG(i) (DR_REG_SPI_MEM_BASE(i) + 0x218) /** SPI_MEM_NAND_FLASH_CFG_DATA4 : HRO; bitpos: [15:0]; default: 0; * configure data for SPI SEQ din/dout need. The data could be use to configure NAND * FLASH or compare read data @@ -2789,7 +2789,7 @@ extern "C" { /** SPI_MEM_NAND_FLASH_CMD_LUT0_REG register * MSPI NAND FLASH CMD LUT control register */ -#define SPI_MEM_NAND_FLASH_CMD_LUT0_REG(i) (REG_SPI_MEM_BASE(i) + 0x240) +#define SPI_MEM_NAND_FLASH_CMD_LUT0_REG(i) (DR_REG_SPI_MEM_BASE(i) + 0x240) /** SPI_MEM_NAND_FLASH_LUT_CMD_VALUE0 : HRO; bitpos: [15:0]; default: 0; * MSPI NAND FLASH config cmd value at cmd lut address 0. */ @@ -2841,7 +2841,7 @@ extern "C" { /** SPI_MEM_NAND_FLASH_CMD_LUT1_REG register * MSPI NAND FLASH CMD LUT control register */ -#define SPI_MEM_NAND_FLASH_CMD_LUT1_REG(i) (REG_SPI_MEM_BASE(i) + 0x244) +#define SPI_MEM_NAND_FLASH_CMD_LUT1_REG(i) (DR_REG_SPI_MEM_BASE(i) + 0x244) /** SPI_MEM_NAND_FLASH_LUT_CMD_VALUE1 : HRO; bitpos: [15:0]; default: 0; * MSPI NAND FLASH config cmd value at cmd lut address 1. */ @@ -2893,7 +2893,7 @@ extern "C" { /** SPI_MEM_NAND_FLASH_CMD_LUT2_REG register * MSPI NAND FLASH CMD LUT control register */ -#define SPI_MEM_NAND_FLASH_CMD_LUT2_REG(i) (REG_SPI_MEM_BASE(i) + 0x248) +#define SPI_MEM_NAND_FLASH_CMD_LUT2_REG(i) (DR_REG_SPI_MEM_BASE(i) + 0x248) /** SPI_MEM_NAND_FLASH_LUT_CMD_VALUE2 : HRO; bitpos: [15:0]; default: 0; * MSPI NAND FLASH config cmd value at cmd lut address 2. */ @@ -2945,7 +2945,7 @@ extern "C" { /** SPI_MEM_NAND_FLASH_CMD_LUT3_REG register * MSPI NAND FLASH CMD LUT control register */ -#define SPI_MEM_NAND_FLASH_CMD_LUT3_REG(i) (REG_SPI_MEM_BASE(i) + 0x24c) +#define SPI_MEM_NAND_FLASH_CMD_LUT3_REG(i) (DR_REG_SPI_MEM_BASE(i) + 0x24c) /** SPI_MEM_NAND_FLASH_LUT_CMD_VALUE3 : HRO; bitpos: [15:0]; default: 0; * MSPI NAND FLASH config cmd value at cmd lut address 3. */ @@ -2997,7 +2997,7 @@ extern "C" { /** SPI_MEM_NAND_FLASH_CMD_LUT4_REG register * MSPI NAND FLASH CMD LUT control register */ -#define SPI_MEM_NAND_FLASH_CMD_LUT4_REG(i) (REG_SPI_MEM_BASE(i) + 0x250) +#define SPI_MEM_NAND_FLASH_CMD_LUT4_REG(i) (DR_REG_SPI_MEM_BASE(i) + 0x250) /** SPI_MEM_NAND_FLASH_LUT_CMD_VALUE4 : HRO; bitpos: [15:0]; default: 0; * MSPI NAND FLASH config cmd value at cmd lut address 4. */ @@ -3049,7 +3049,7 @@ extern "C" { /** SPI_MEM_NAND_FLASH_CMD_LUT5_REG register * MSPI NAND FLASH CMD LUT control register */ -#define SPI_MEM_NAND_FLASH_CMD_LUT5_REG(i) (REG_SPI_MEM_BASE(i) + 0x254) +#define SPI_MEM_NAND_FLASH_CMD_LUT5_REG(i) (DR_REG_SPI_MEM_BASE(i) + 0x254) /** SPI_MEM_NAND_FLASH_LUT_CMD_VALUE5 : HRO; bitpos: [15:0]; default: 0; * MSPI NAND FLASH config cmd value at cmd lut address 5. */ @@ -3101,7 +3101,7 @@ extern "C" { /** SPI_MEM_NAND_FLASH_CMD_LUT6_REG register * MSPI NAND FLASH CMD LUT control register */ -#define SPI_MEM_NAND_FLASH_CMD_LUT6_REG(i) (REG_SPI_MEM_BASE(i) + 0x258) +#define SPI_MEM_NAND_FLASH_CMD_LUT6_REG(i) (DR_REG_SPI_MEM_BASE(i) + 0x258) /** SPI_MEM_NAND_FLASH_LUT_CMD_VALUE6 : HRO; bitpos: [15:0]; default: 0; * MSPI NAND FLASH config cmd value at cmd lut address 6. */ @@ -3153,7 +3153,7 @@ extern "C" { /** SPI_MEM_NAND_FLASH_CMD_LUT7_REG register * MSPI NAND FLASH CMD LUT control register */ -#define SPI_MEM_NAND_FLASH_CMD_LUT7_REG(i) (REG_SPI_MEM_BASE(i) + 0x25c) +#define SPI_MEM_NAND_FLASH_CMD_LUT7_REG(i) (DR_REG_SPI_MEM_BASE(i) + 0x25c) /** SPI_MEM_NAND_FLASH_LUT_CMD_VALUE7 : HRO; bitpos: [15:0]; default: 0; * MSPI NAND FLASH config cmd value at cmd lut address 7. */ @@ -3205,7 +3205,7 @@ extern "C" { /** SPI_MEM_NAND_FLASH_CMD_LUT8_REG register * MSPI NAND FLASH CMD LUT control register */ -#define SPI_MEM_NAND_FLASH_CMD_LUT8_REG(i) (REG_SPI_MEM_BASE(i) + 0x260) +#define SPI_MEM_NAND_FLASH_CMD_LUT8_REG(i) (DR_REG_SPI_MEM_BASE(i) + 0x260) /** SPI_MEM_NAND_FLASH_LUT_CMD_VALUE8 : HRO; bitpos: [15:0]; default: 0; * MSPI NAND FLASH config cmd value at cmd lut address 8. */ @@ -3257,7 +3257,7 @@ extern "C" { /** SPI_MEM_NAND_FLASH_CMD_LUT9_REG register * MSPI NAND FLASH CMD LUT control register */ -#define SPI_MEM_NAND_FLASH_CMD_LUT9_REG(i) (REG_SPI_MEM_BASE(i) + 0x264) +#define SPI_MEM_NAND_FLASH_CMD_LUT9_REG(i) (DR_REG_SPI_MEM_BASE(i) + 0x264) /** SPI_MEM_NAND_FLASH_LUT_CMD_VALUE9 : HRO; bitpos: [15:0]; default: 0; * MSPI NAND FLASH config cmd value at cmd lut address 9. */ @@ -3309,7 +3309,7 @@ extern "C" { /** SPI_MEM_NAND_FLASH_CMD_LUT10_REG register * MSPI NAND FLASH CMD LUT control register */ -#define SPI_MEM_NAND_FLASH_CMD_LUT10_REG(i) (REG_SPI_MEM_BASE(i) + 0x268) +#define SPI_MEM_NAND_FLASH_CMD_LUT10_REG(i) (DR_REG_SPI_MEM_BASE(i) + 0x268) /** SPI_MEM_NAND_FLASH_LUT_CMD_VALUE10 : HRO; bitpos: [15:0]; default: 0; * MSPI NAND FLASH config cmd value at cmd lut address 10. */ @@ -3361,7 +3361,7 @@ extern "C" { /** SPI_MEM_NAND_FLASH_CMD_LUT11_REG register * MSPI NAND FLASH CMD LUT control register */ -#define SPI_MEM_NAND_FLASH_CMD_LUT11_REG(i) (REG_SPI_MEM_BASE(i) + 0x26c) +#define SPI_MEM_NAND_FLASH_CMD_LUT11_REG(i) (DR_REG_SPI_MEM_BASE(i) + 0x26c) /** SPI_MEM_NAND_FLASH_LUT_CMD_VALUE11 : HRO; bitpos: [15:0]; default: 0; * MSPI NAND FLASH config cmd value at cmd lut address 11. */ @@ -3413,7 +3413,7 @@ extern "C" { /** SPI_MEM_NAND_FLASH_CMD_LUT12_REG register * MSPI NAND FLASH CMD LUT control register */ -#define SPI_MEM_NAND_FLASH_CMD_LUT12_REG(i) (REG_SPI_MEM_BASE(i) + 0x270) +#define SPI_MEM_NAND_FLASH_CMD_LUT12_REG(i) (DR_REG_SPI_MEM_BASE(i) + 0x270) /** SPI_MEM_NAND_FLASH_LUT_CMD_VALUE12 : HRO; bitpos: [15:0]; default: 0; * MSPI NAND FLASH config cmd value at cmd lut address 12. */ @@ -3465,7 +3465,7 @@ extern "C" { /** SPI_MEM_NAND_FLASH_CMD_LUT13_REG register * MSPI NAND FLASH CMD LUT control register */ -#define SPI_MEM_NAND_FLASH_CMD_LUT13_REG(i) (REG_SPI_MEM_BASE(i) + 0x274) +#define SPI_MEM_NAND_FLASH_CMD_LUT13_REG(i) (DR_REG_SPI_MEM_BASE(i) + 0x274) /** SPI_MEM_NAND_FLASH_LUT_CMD_VALUE13 : HRO; bitpos: [15:0]; default: 0; * MSPI NAND FLASH config cmd value at cmd lut address 13. */ @@ -3517,7 +3517,7 @@ extern "C" { /** SPI_MEM_NAND_FLASH_CMD_LUT14_REG register * MSPI NAND FLASH CMD LUT control register */ -#define SPI_MEM_NAND_FLASH_CMD_LUT14_REG(i) (REG_SPI_MEM_BASE(i) + 0x278) +#define SPI_MEM_NAND_FLASH_CMD_LUT14_REG(i) (DR_REG_SPI_MEM_BASE(i) + 0x278) /** SPI_MEM_NAND_FLASH_LUT_CMD_VALUE14 : HRO; bitpos: [15:0]; default: 0; * MSPI NAND FLASH config cmd value at cmd lut address 14. */ @@ -3569,7 +3569,7 @@ extern "C" { /** SPI_MEM_NAND_FLASH_CMD_LUT15_REG register * MSPI NAND FLASH CMD LUT control register */ -#define SPI_MEM_NAND_FLASH_CMD_LUT15_REG(i) (REG_SPI_MEM_BASE(i) + 0x27c) +#define SPI_MEM_NAND_FLASH_CMD_LUT15_REG(i) (DR_REG_SPI_MEM_BASE(i) + 0x27c) /** SPI_MEM_NAND_FLASH_LUT_CMD_VALUE15 : HRO; bitpos: [15:0]; default: 0; * MSPI NAND FLASH config cmd value at cmd lut address 15. */ @@ -3621,7 +3621,7 @@ extern "C" { /** SPI_MEM_NAND_FLASH_SPI_SEQ0_REG register * NAND FLASH SPI SEQ control register */ -#define SPI_MEM_NAND_FLASH_SPI_SEQ0_REG(i) (REG_SPI_MEM_BASE(i) + 0x280) +#define SPI_MEM_NAND_FLASH_SPI_SEQ0_REG(i) (DR_REG_SPI_MEM_BASE(i) + 0x280) /** SPI_MEM_NAND_FLASH_SEQ_TAIL_FLG0 : HRO; bitpos: [0]; default: 0; * MSPI NAND FLASH config seq_tail_flg at spi seq index 0.1: The last index for * sequence. 0: Not the last index. @@ -3675,7 +3675,7 @@ extern "C" { /** SPI_MEM_NAND_FLASH_SPI_SEQ1_REG register * NAND FLASH SPI SEQ control register */ -#define SPI_MEM_NAND_FLASH_SPI_SEQ1_REG(i) (REG_SPI_MEM_BASE(i) + 0x284) +#define SPI_MEM_NAND_FLASH_SPI_SEQ1_REG(i) (DR_REG_SPI_MEM_BASE(i) + 0x284) /** SPI_MEM_NAND_FLASH_SEQ_TAIL_FLG1 : HRO; bitpos: [0]; default: 0; * MSPI NAND FLASH config seq_tail_flg at spi seq index 1.1: The last index for * sequence. 0: Not the last index. @@ -3729,7 +3729,7 @@ extern "C" { /** SPI_MEM_NAND_FLASH_SPI_SEQ2_REG register * NAND FLASH SPI SEQ control register */ -#define SPI_MEM_NAND_FLASH_SPI_SEQ2_REG(i) (REG_SPI_MEM_BASE(i) + 0x288) +#define SPI_MEM_NAND_FLASH_SPI_SEQ2_REG(i) (DR_REG_SPI_MEM_BASE(i) + 0x288) /** SPI_MEM_NAND_FLASH_SEQ_TAIL_FLG2 : HRO; bitpos: [0]; default: 0; * MSPI NAND FLASH config seq_tail_flg at spi seq index 2.1: The last index for * sequence. 0: Not the last index. @@ -3783,7 +3783,7 @@ extern "C" { /** SPI_MEM_NAND_FLASH_SPI_SEQ3_REG register * NAND FLASH SPI SEQ control register */ -#define SPI_MEM_NAND_FLASH_SPI_SEQ3_REG(i) (REG_SPI_MEM_BASE(i) + 0x28c) +#define SPI_MEM_NAND_FLASH_SPI_SEQ3_REG(i) (DR_REG_SPI_MEM_BASE(i) + 0x28c) /** SPI_MEM_NAND_FLASH_SEQ_TAIL_FLG3 : HRO; bitpos: [0]; default: 0; * MSPI NAND FLASH config seq_tail_flg at spi seq index 3.1: The last index for * sequence. 0: Not the last index. @@ -3837,7 +3837,7 @@ extern "C" { /** SPI_MEM_NAND_FLASH_SPI_SEQ4_REG register * NAND FLASH SPI SEQ control register */ -#define SPI_MEM_NAND_FLASH_SPI_SEQ4_REG(i) (REG_SPI_MEM_BASE(i) + 0x290) +#define SPI_MEM_NAND_FLASH_SPI_SEQ4_REG(i) (DR_REG_SPI_MEM_BASE(i) + 0x290) /** SPI_MEM_NAND_FLASH_SEQ_TAIL_FLG4 : HRO; bitpos: [0]; default: 0; * MSPI NAND FLASH config seq_tail_flg at spi seq index 4.1: The last index for * sequence. 0: Not the last index. @@ -3891,7 +3891,7 @@ extern "C" { /** SPI_MEM_NAND_FLASH_SPI_SEQ5_REG register * NAND FLASH SPI SEQ control register */ -#define SPI_MEM_NAND_FLASH_SPI_SEQ5_REG(i) (REG_SPI_MEM_BASE(i) + 0x294) +#define SPI_MEM_NAND_FLASH_SPI_SEQ5_REG(i) (DR_REG_SPI_MEM_BASE(i) + 0x294) /** SPI_MEM_NAND_FLASH_SEQ_TAIL_FLG5 : HRO; bitpos: [0]; default: 0; * MSPI NAND FLASH config seq_tail_flg at spi seq index 5.1: The last index for * sequence. 0: Not the last index. @@ -3945,7 +3945,7 @@ extern "C" { /** SPI_MEM_NAND_FLASH_SPI_SEQ6_REG register * NAND FLASH SPI SEQ control register */ -#define SPI_MEM_NAND_FLASH_SPI_SEQ6_REG(i) (REG_SPI_MEM_BASE(i) + 0x298) +#define SPI_MEM_NAND_FLASH_SPI_SEQ6_REG(i) (DR_REG_SPI_MEM_BASE(i) + 0x298) /** SPI_MEM_NAND_FLASH_SEQ_TAIL_FLG6 : HRO; bitpos: [0]; default: 0; * MSPI NAND FLASH config seq_tail_flg at spi seq index 6.1: The last index for * sequence. 0: Not the last index. @@ -3999,7 +3999,7 @@ extern "C" { /** SPI_MEM_NAND_FLASH_SPI_SEQ7_REG register * NAND FLASH SPI SEQ control register */ -#define SPI_MEM_NAND_FLASH_SPI_SEQ7_REG(i) (REG_SPI_MEM_BASE(i) + 0x29c) +#define SPI_MEM_NAND_FLASH_SPI_SEQ7_REG(i) (DR_REG_SPI_MEM_BASE(i) + 0x29c) /** SPI_MEM_NAND_FLASH_SEQ_TAIL_FLG7 : HRO; bitpos: [0]; default: 0; * MSPI NAND FLASH config seq_tail_flg at spi seq index 7.1: The last index for * sequence. 0: Not the last index. @@ -4053,7 +4053,7 @@ extern "C" { /** SPI_MEM_NAND_FLASH_SPI_SEQ8_REG register * NAND FLASH SPI SEQ control register */ -#define SPI_MEM_NAND_FLASH_SPI_SEQ8_REG(i) (REG_SPI_MEM_BASE(i) + 0x2a0) +#define SPI_MEM_NAND_FLASH_SPI_SEQ8_REG(i) (DR_REG_SPI_MEM_BASE(i) + 0x2a0) /** SPI_MEM_NAND_FLASH_SEQ_TAIL_FLG8 : HRO; bitpos: [0]; default: 0; * MSPI NAND FLASH config seq_tail_flg at spi seq index 8.1: The last index for * sequence. 0: Not the last index. @@ -4107,7 +4107,7 @@ extern "C" { /** SPI_MEM_NAND_FLASH_SPI_SEQ9_REG register * NAND FLASH SPI SEQ control register */ -#define SPI_MEM_NAND_FLASH_SPI_SEQ9_REG(i) (REG_SPI_MEM_BASE(i) + 0x2a4) +#define SPI_MEM_NAND_FLASH_SPI_SEQ9_REG(i) (DR_REG_SPI_MEM_BASE(i) + 0x2a4) /** SPI_MEM_NAND_FLASH_SEQ_TAIL_FLG9 : HRO; bitpos: [0]; default: 0; * MSPI NAND FLASH config seq_tail_flg at spi seq index 9.1: The last index for * sequence. 0: Not the last index. @@ -4161,7 +4161,7 @@ extern "C" { /** SPI_MEM_NAND_FLASH_SPI_SEQ10_REG register * NAND FLASH SPI SEQ control register */ -#define SPI_MEM_NAND_FLASH_SPI_SEQ10_REG(i) (REG_SPI_MEM_BASE(i) + 0x2a8) +#define SPI_MEM_NAND_FLASH_SPI_SEQ10_REG(i) (DR_REG_SPI_MEM_BASE(i) + 0x2a8) /** SPI_MEM_NAND_FLASH_SEQ_TAIL_FLG10 : HRO; bitpos: [0]; default: 0; * MSPI NAND FLASH config seq_tail_flg at spi seq index 10.1: The last index for * sequence. 0: Not the last index. @@ -4215,7 +4215,7 @@ extern "C" { /** SPI_MEM_NAND_FLASH_SPI_SEQ11_REG register * NAND FLASH SPI SEQ control register */ -#define SPI_MEM_NAND_FLASH_SPI_SEQ11_REG(i) (REG_SPI_MEM_BASE(i) + 0x2ac) +#define SPI_MEM_NAND_FLASH_SPI_SEQ11_REG(i) (DR_REG_SPI_MEM_BASE(i) + 0x2ac) /** SPI_MEM_NAND_FLASH_SEQ_TAIL_FLG11 : HRO; bitpos: [0]; default: 0; * MSPI NAND FLASH config seq_tail_flg at spi seq index 11.1: The last index for * sequence. 0: Not the last index. @@ -4269,7 +4269,7 @@ extern "C" { /** SPI_MEM_NAND_FLASH_SPI_SEQ12_REG register * NAND FLASH SPI SEQ control register */ -#define SPI_MEM_NAND_FLASH_SPI_SEQ12_REG(i) (REG_SPI_MEM_BASE(i) + 0x2b0) +#define SPI_MEM_NAND_FLASH_SPI_SEQ12_REG(i) (DR_REG_SPI_MEM_BASE(i) + 0x2b0) /** SPI_MEM_NAND_FLASH_SEQ_TAIL_FLG12 : HRO; bitpos: [0]; default: 0; * MSPI NAND FLASH config seq_tail_flg at spi seq index 12.1: The last index for * sequence. 0: Not the last index. @@ -4323,7 +4323,7 @@ extern "C" { /** SPI_MEM_NAND_FLASH_SPI_SEQ13_REG register * NAND FLASH SPI SEQ control register */ -#define SPI_MEM_NAND_FLASH_SPI_SEQ13_REG(i) (REG_SPI_MEM_BASE(i) + 0x2b4) +#define SPI_MEM_NAND_FLASH_SPI_SEQ13_REG(i) (DR_REG_SPI_MEM_BASE(i) + 0x2b4) /** SPI_MEM_NAND_FLASH_SEQ_TAIL_FLG13 : HRO; bitpos: [0]; default: 0; * MSPI NAND FLASH config seq_tail_flg at spi seq index 13.1: The last index for * sequence. 0: Not the last index. @@ -4377,7 +4377,7 @@ extern "C" { /** SPI_MEM_NAND_FLASH_SPI_SEQ14_REG register * NAND FLASH SPI SEQ control register */ -#define SPI_MEM_NAND_FLASH_SPI_SEQ14_REG(i) (REG_SPI_MEM_BASE(i) + 0x2b8) +#define SPI_MEM_NAND_FLASH_SPI_SEQ14_REG(i) (DR_REG_SPI_MEM_BASE(i) + 0x2b8) /** SPI_MEM_NAND_FLASH_SEQ_TAIL_FLG14 : HRO; bitpos: [0]; default: 0; * MSPI NAND FLASH config seq_tail_flg at spi seq index 14.1: The last index for * sequence. 0: Not the last index. @@ -4431,7 +4431,7 @@ extern "C" { /** SPI_MEM_NAND_FLASH_SPI_SEQ15_REG register * NAND FLASH SPI SEQ control register */ -#define SPI_MEM_NAND_FLASH_SPI_SEQ15_REG(i) (REG_SPI_MEM_BASE(i) + 0x2bc) +#define SPI_MEM_NAND_FLASH_SPI_SEQ15_REG(i) (DR_REG_SPI_MEM_BASE(i) + 0x2bc) /** SPI_MEM_NAND_FLASH_SEQ_TAIL_FLG15 : HRO; bitpos: [0]; default: 0; * MSPI NAND FLASH config seq_tail_flg at spi seq index 15.1: The last index for * sequence. 0: Not the last index. @@ -4485,7 +4485,7 @@ extern "C" { /** SPI_MEM_NAND_FLASH_SPI_SEQ16_REG register * NAND FLASH SPI SEQ control register */ -#define SPI_MEM_NAND_FLASH_SPI_SEQ16_REG(i) (REG_SPI_MEM_BASE(i) + 0x2c0) +#define SPI_MEM_NAND_FLASH_SPI_SEQ16_REG(i) (DR_REG_SPI_MEM_BASE(i) + 0x2c0) /** SPI_MEM_NAND_FLASH_SEQ_TAIL_FLG16 : HRO; bitpos: [0]; default: 0; * MSPI NAND FLASH config seq_tail_flg at spi seq index 16.1: The last index for * sequence. 0: Not the last index. @@ -4539,7 +4539,7 @@ extern "C" { /** SPI_MEM_NAND_FLASH_SPI_SEQ17_REG register * NAND FLASH SPI SEQ control register */ -#define SPI_MEM_NAND_FLASH_SPI_SEQ17_REG(i) (REG_SPI_MEM_BASE(i) + 0x2c4) +#define SPI_MEM_NAND_FLASH_SPI_SEQ17_REG(i) (DR_REG_SPI_MEM_BASE(i) + 0x2c4) /** SPI_MEM_NAND_FLASH_SEQ_TAIL_FLG17 : HRO; bitpos: [0]; default: 0; * MSPI NAND FLASH config seq_tail_flg at spi seq index 17.1: The last index for * sequence. 0: Not the last index. @@ -4593,7 +4593,7 @@ extern "C" { /** SPI_MEM_NAND_FLASH_SPI_SEQ18_REG register * NAND FLASH SPI SEQ control register */ -#define SPI_MEM_NAND_FLASH_SPI_SEQ18_REG(i) (REG_SPI_MEM_BASE(i) + 0x2c8) +#define SPI_MEM_NAND_FLASH_SPI_SEQ18_REG(i) (DR_REG_SPI_MEM_BASE(i) + 0x2c8) /** SPI_MEM_NAND_FLASH_SEQ_TAIL_FLG18 : HRO; bitpos: [0]; default: 0; * MSPI NAND FLASH config seq_tail_flg at spi seq index 18.1: The last index for * sequence. 0: Not the last index. @@ -4647,7 +4647,7 @@ extern "C" { /** SPI_MEM_NAND_FLASH_SPI_SEQ19_REG register * NAND FLASH SPI SEQ control register */ -#define SPI_MEM_NAND_FLASH_SPI_SEQ19_REG(i) (REG_SPI_MEM_BASE(i) + 0x2cc) +#define SPI_MEM_NAND_FLASH_SPI_SEQ19_REG(i) (DR_REG_SPI_MEM_BASE(i) + 0x2cc) /** SPI_MEM_NAND_FLASH_SEQ_TAIL_FLG19 : HRO; bitpos: [0]; default: 0; * MSPI NAND FLASH config seq_tail_flg at spi seq index 19.1: The last index for * sequence. 0: Not the last index. @@ -4701,7 +4701,7 @@ extern "C" { /** SPI_MEM_NAND_FLASH_SPI_SEQ20_REG register * NAND FLASH SPI SEQ control register */ -#define SPI_MEM_NAND_FLASH_SPI_SEQ20_REG(i) (REG_SPI_MEM_BASE(i) + 0x2d0) +#define SPI_MEM_NAND_FLASH_SPI_SEQ20_REG(i) (DR_REG_SPI_MEM_BASE(i) + 0x2d0) /** SPI_MEM_NAND_FLASH_SEQ_TAIL_FLG20 : HRO; bitpos: [0]; default: 0; * MSPI NAND FLASH config seq_tail_flg at spi seq index 20.1: The last index for * sequence. 0: Not the last index. @@ -4755,7 +4755,7 @@ extern "C" { /** SPI_MEM_NAND_FLASH_SPI_SEQ21_REG register * NAND FLASH SPI SEQ control register */ -#define SPI_MEM_NAND_FLASH_SPI_SEQ21_REG(i) (REG_SPI_MEM_BASE(i) + 0x2d4) +#define SPI_MEM_NAND_FLASH_SPI_SEQ21_REG(i) (DR_REG_SPI_MEM_BASE(i) + 0x2d4) /** SPI_MEM_NAND_FLASH_SEQ_TAIL_FLG21 : HRO; bitpos: [0]; default: 0; * MSPI NAND FLASH config seq_tail_flg at spi seq index 21.1: The last index for * sequence. 0: Not the last index. @@ -4809,7 +4809,7 @@ extern "C" { /** SPI_MEM_NAND_FLASH_SPI_SEQ22_REG register * NAND FLASH SPI SEQ control register */ -#define SPI_MEM_NAND_FLASH_SPI_SEQ22_REG(i) (REG_SPI_MEM_BASE(i) + 0x2d8) +#define SPI_MEM_NAND_FLASH_SPI_SEQ22_REG(i) (DR_REG_SPI_MEM_BASE(i) + 0x2d8) /** SPI_MEM_NAND_FLASH_SEQ_TAIL_FLG22 : HRO; bitpos: [0]; default: 0; * MSPI NAND FLASH config seq_tail_flg at spi seq index 22.1: The last index for * sequence. 0: Not the last index. @@ -4863,7 +4863,7 @@ extern "C" { /** SPI_MEM_NAND_FLASH_SPI_SEQ23_REG register * NAND FLASH SPI SEQ control register */ -#define SPI_MEM_NAND_FLASH_SPI_SEQ23_REG(i) (REG_SPI_MEM_BASE(i) + 0x2dc) +#define SPI_MEM_NAND_FLASH_SPI_SEQ23_REG(i) (DR_REG_SPI_MEM_BASE(i) + 0x2dc) /** SPI_MEM_NAND_FLASH_SEQ_TAIL_FLG23 : HRO; bitpos: [0]; default: 0; * MSPI NAND FLASH config seq_tail_flg at spi seq index 23.1: The last index for * sequence. 0: Not the last index. @@ -4917,7 +4917,7 @@ extern "C" { /** SPI_MEM_NAND_FLASH_SPI_SEQ24_REG register * NAND FLASH SPI SEQ control register */ -#define SPI_MEM_NAND_FLASH_SPI_SEQ24_REG(i) (REG_SPI_MEM_BASE(i) + 0x2e0) +#define SPI_MEM_NAND_FLASH_SPI_SEQ24_REG(i) (DR_REG_SPI_MEM_BASE(i) + 0x2e0) /** SPI_MEM_NAND_FLASH_SEQ_TAIL_FLG24 : HRO; bitpos: [0]; default: 0; * MSPI NAND FLASH config seq_tail_flg at spi seq index 24.1: The last index for * sequence. 0: Not the last index. @@ -4971,7 +4971,7 @@ extern "C" { /** SPI_MEM_NAND_FLASH_SPI_SEQ25_REG register * NAND FLASH SPI SEQ control register */ -#define SPI_MEM_NAND_FLASH_SPI_SEQ25_REG(i) (REG_SPI_MEM_BASE(i) + 0x2e4) +#define SPI_MEM_NAND_FLASH_SPI_SEQ25_REG(i) (DR_REG_SPI_MEM_BASE(i) + 0x2e4) /** SPI_MEM_NAND_FLASH_SEQ_TAIL_FLG25 : HRO; bitpos: [0]; default: 0; * MSPI NAND FLASH config seq_tail_flg at spi seq index 25.1: The last index for * sequence. 0: Not the last index. @@ -5025,7 +5025,7 @@ extern "C" { /** SPI_MEM_NAND_FLASH_SPI_SEQ26_REG register * NAND FLASH SPI SEQ control register */ -#define SPI_MEM_NAND_FLASH_SPI_SEQ26_REG(i) (REG_SPI_MEM_BASE(i) + 0x2e8) +#define SPI_MEM_NAND_FLASH_SPI_SEQ26_REG(i) (DR_REG_SPI_MEM_BASE(i) + 0x2e8) /** SPI_MEM_NAND_FLASH_SEQ_TAIL_FLG26 : HRO; bitpos: [0]; default: 0; * MSPI NAND FLASH config seq_tail_flg at spi seq index 26.1: The last index for * sequence. 0: Not the last index. @@ -5079,7 +5079,7 @@ extern "C" { /** SPI_MEM_NAND_FLASH_SPI_SEQ27_REG register * NAND FLASH SPI SEQ control register */ -#define SPI_MEM_NAND_FLASH_SPI_SEQ27_REG(i) (REG_SPI_MEM_BASE(i) + 0x2ec) +#define SPI_MEM_NAND_FLASH_SPI_SEQ27_REG(i) (DR_REG_SPI_MEM_BASE(i) + 0x2ec) /** SPI_MEM_NAND_FLASH_SEQ_TAIL_FLG27 : HRO; bitpos: [0]; default: 0; * MSPI NAND FLASH config seq_tail_flg at spi seq index 27.1: The last index for * sequence. 0: Not the last index. @@ -5133,7 +5133,7 @@ extern "C" { /** SPI_MEM_NAND_FLASH_SPI_SEQ28_REG register * NAND FLASH SPI SEQ control register */ -#define SPI_MEM_NAND_FLASH_SPI_SEQ28_REG(i) (REG_SPI_MEM_BASE(i) + 0x2f0) +#define SPI_MEM_NAND_FLASH_SPI_SEQ28_REG(i) (DR_REG_SPI_MEM_BASE(i) + 0x2f0) /** SPI_MEM_NAND_FLASH_SEQ_TAIL_FLG28 : HRO; bitpos: [0]; default: 0; * MSPI NAND FLASH config seq_tail_flg at spi seq index 28.1: The last index for * sequence. 0: Not the last index. @@ -5187,7 +5187,7 @@ extern "C" { /** SPI_MEM_NAND_FLASH_SPI_SEQ29_REG register * NAND FLASH SPI SEQ control register */ -#define SPI_MEM_NAND_FLASH_SPI_SEQ29_REG(i) (REG_SPI_MEM_BASE(i) + 0x2f4) +#define SPI_MEM_NAND_FLASH_SPI_SEQ29_REG(i) (DR_REG_SPI_MEM_BASE(i) + 0x2f4) /** SPI_MEM_NAND_FLASH_SEQ_TAIL_FLG29 : HRO; bitpos: [0]; default: 0; * MSPI NAND FLASH config seq_tail_flg at spi seq index 29.1: The last index for * sequence. 0: Not the last index. @@ -5241,7 +5241,7 @@ extern "C" { /** SPI_MEM_NAND_FLASH_SPI_SEQ30_REG register * NAND FLASH SPI SEQ control register */ -#define SPI_MEM_NAND_FLASH_SPI_SEQ30_REG(i) (REG_SPI_MEM_BASE(i) + 0x2f8) +#define SPI_MEM_NAND_FLASH_SPI_SEQ30_REG(i) (DR_REG_SPI_MEM_BASE(i) + 0x2f8) /** SPI_MEM_NAND_FLASH_SEQ_TAIL_FLG30 : HRO; bitpos: [0]; default: 0; * MSPI NAND FLASH config seq_tail_flg at spi seq index 30.1: The last index for * sequence. 0: Not the last index. @@ -5295,7 +5295,7 @@ extern "C" { /** SPI_MEM_NAND_FLASH_SPI_SEQ31_REG register * NAND FLASH SPI SEQ control register */ -#define SPI_MEM_NAND_FLASH_SPI_SEQ31_REG(i) (REG_SPI_MEM_BASE(i) + 0x2fc) +#define SPI_MEM_NAND_FLASH_SPI_SEQ31_REG(i) (DR_REG_SPI_MEM_BASE(i) + 0x2fc) /** SPI_MEM_NAND_FLASH_SEQ_TAIL_FLG31 : HRO; bitpos: [0]; default: 0; * MSPI NAND FLASH config seq_tail_flg at spi seq index 31.1: The last index for * sequence. 0: Not the last index. @@ -5349,7 +5349,7 @@ extern "C" { /** SPI_MEM_XTS_PLAIN_BASE_REG register * The base address of the memory that stores plaintext in Manual Encryption */ -#define SPI_MEM_XTS_PLAIN_BASE_REG(i) (REG_SPI_MEM_BASE(i) + 0x300) +#define SPI_MEM_XTS_PLAIN_BASE_REG(i) (DR_REG_SPI_MEM_BASE(i) + 0x300) /** SPI_XTS_PLAIN : R/W; bitpos: [31:0]; default: 0; * This field is only used to generate include file in c case. This field is useless. * Please do not use this field. @@ -5362,7 +5362,7 @@ extern "C" { /** SPI_MEM_XTS_LINESIZE_REG register * Manual Encryption Line-Size register */ -#define SPI_MEM_XTS_LINESIZE_REG(i) (REG_SPI_MEM_BASE(i) + 0x340) +#define SPI_MEM_XTS_LINESIZE_REG(i) (DR_REG_SPI_MEM_BASE(i) + 0x340) /** SPI_XTS_LINESIZE : R/W; bitpos: [1:0]; default: 0; * This bits stores the line-size parameter which will be used in manual encryption * calculation. It decides how many bytes will be encrypted one time. 0: 16-bytes, 1: @@ -5376,7 +5376,7 @@ extern "C" { /** SPI_MEM_XTS_DESTINATION_REG register * Manual Encryption destination register */ -#define SPI_MEM_XTS_DESTINATION_REG(i) (REG_SPI_MEM_BASE(i) + 0x344) +#define SPI_MEM_XTS_DESTINATION_REG(i) (DR_REG_SPI_MEM_BASE(i) + 0x344) /** SPI_XTS_DESTINATION : R/W; bitpos: [0]; default: 0; * This bit stores the destination parameter which will be used in manual encryption * calculation. 0: flash(default), 1: psram(reserved). Only default value can be used. @@ -5389,7 +5389,7 @@ extern "C" { /** SPI_MEM_XTS_PHYSICAL_ADDRESS_REG register * Manual Encryption physical address register */ -#define SPI_MEM_XTS_PHYSICAL_ADDRESS_REG(i) (REG_SPI_MEM_BASE(i) + 0x348) +#define SPI_MEM_XTS_PHYSICAL_ADDRESS_REG(i) (DR_REG_SPI_MEM_BASE(i) + 0x348) /** SPI_XTS_PHYSICAL_ADDRESS : R/W; bitpos: [29:0]; default: 0; * This bits stores the physical-address parameter which will be used in manual * encryption calculation. This value should aligned with byte number decided by @@ -5403,7 +5403,7 @@ extern "C" { /** SPI_MEM_XTS_TRIGGER_REG register * Manual Encryption physical address register */ -#define SPI_MEM_XTS_TRIGGER_REG(i) (REG_SPI_MEM_BASE(i) + 0x34c) +#define SPI_MEM_XTS_TRIGGER_REG(i) (DR_REG_SPI_MEM_BASE(i) + 0x34c) /** SPI_XTS_TRIGGER : WT; bitpos: [0]; default: 0; * Set this bit to trigger the process of manual encryption calculation. This action * should only be asserted when manual encryption status is 0. After this action, @@ -5418,7 +5418,7 @@ extern "C" { /** SPI_MEM_XTS_RELEASE_REG register * Manual Encryption physical address register */ -#define SPI_MEM_XTS_RELEASE_REG(i) (REG_SPI_MEM_BASE(i) + 0x350) +#define SPI_MEM_XTS_RELEASE_REG(i) (DR_REG_SPI_MEM_BASE(i) + 0x350) /** SPI_XTS_RELEASE : WT; bitpos: [0]; default: 0; * Set this bit to release encrypted result to mspi. This action should only be * asserted when manual encryption status is 2. After this action, manual encryption @@ -5432,7 +5432,7 @@ extern "C" { /** SPI_MEM_XTS_DESTROY_REG register * Manual Encryption physical address register */ -#define SPI_MEM_XTS_DESTROY_REG(i) (REG_SPI_MEM_BASE(i) + 0x354) +#define SPI_MEM_XTS_DESTROY_REG(i) (DR_REG_SPI_MEM_BASE(i) + 0x354) /** SPI_XTS_DESTROY : WT; bitpos: [0]; default: 0; * Set this bit to destroy encrypted result. This action should be asserted only when * manual encryption status is 3. After this action, manual encryption status will @@ -5446,7 +5446,7 @@ extern "C" { /** SPI_MEM_XTS_STATE_REG register * Manual Encryption physical address register */ -#define SPI_MEM_XTS_STATE_REG(i) (REG_SPI_MEM_BASE(i) + 0x358) +#define SPI_MEM_XTS_STATE_REG(i) (DR_REG_SPI_MEM_BASE(i) + 0x358) /** SPI_XTS_STATE : RO; bitpos: [1:0]; default: 0; * This bits stores the status of manual encryption. 0: idle, 1: busy of encryption * calculation, 2: encryption calculation is done but the encrypted result is @@ -5460,7 +5460,7 @@ extern "C" { /** SPI_MEM_XTS_DATE_REG register * Manual Encryption version register */ -#define SPI_MEM_XTS_DATE_REG(i) (REG_SPI_MEM_BASE(i) + 0x35c) +#define SPI_MEM_XTS_DATE_REG(i) (DR_REG_SPI_MEM_BASE(i) + 0x35c) /** SPI_XTS_DATE : R/W; bitpos: [29:0]; default: 539035911; * This bits stores the last modified-time of manual encryption feature. */ @@ -5472,7 +5472,7 @@ extern "C" { /** SPI_MEM_MMU_ITEM_CONTENT_REG register * MSPI-MMU item content register */ -#define SPI_MEM_MMU_ITEM_CONTENT_REG(i) (REG_SPI_MEM_BASE(i) + 0x37c) +#define SPI_MEM_MMU_ITEM_CONTENT_REG(i) (DR_REG_SPI_MEM_BASE(i) + 0x37c) /** SPI_MMU_ITEM_CONTENT : R/W; bitpos: [31:0]; default: 892; * MSPI-MMU item content */ @@ -5484,7 +5484,7 @@ extern "C" { /** SPI_MEM_MMU_ITEM_INDEX_REG register * MSPI-MMU item index register */ -#define SPI_MEM_MMU_ITEM_INDEX_REG(i) (REG_SPI_MEM_BASE(i) + 0x380) +#define SPI_MEM_MMU_ITEM_INDEX_REG(i) (DR_REG_SPI_MEM_BASE(i) + 0x380) /** SPI_MMU_ITEM_INDEX : R/W; bitpos: [31:0]; default: 0; * MSPI-MMU item index */ @@ -5496,7 +5496,7 @@ extern "C" { /** SPI_MEM_MMU_POWER_CTRL_REG register * MSPI MMU power control register */ -#define SPI_MEM_MMU_POWER_CTRL_REG(i) (REG_SPI_MEM_BASE(i) + 0x384) +#define SPI_MEM_MMU_POWER_CTRL_REG(i) (DR_REG_SPI_MEM_BASE(i) + 0x384) /** SPI_MMU_MEM_FORCE_ON : R/W; bitpos: [0]; default: 0; * Set this bit to enable mmu-memory clock force on */ @@ -5537,7 +5537,7 @@ extern "C" { /** SPI_MEM_DPA_CTRL_REG register * SPI memory cryption DPA register */ -#define SPI_MEM_DPA_CTRL_REG(i) (REG_SPI_MEM_BASE(i) + 0x388) +#define SPI_MEM_DPA_CTRL_REG(i) (DR_REG_SPI_MEM_BASE(i) + 0x388) /** SPI_CRYPT_SECURITY_LEVEL : R/W; bitpos: [2:0]; default: 7; * Set the security level of spi mem cryption. 0: Shut off cryption DPA function. 1-7: * The bigger the number is, the more secure the cryption is. (Note that the @@ -5568,7 +5568,7 @@ extern "C" { /** SPI_MEM_XTS_PSEUDO_ROUND_CONF_REG register * SPI memory cryption PSEUDO register */ -#define SPI_MEM_XTS_PSEUDO_ROUND_CONF_REG(i) (REG_SPI_MEM_BASE(i) + 0x38c) +#define SPI_MEM_XTS_PSEUDO_ROUND_CONF_REG(i) (DR_REG_SPI_MEM_BASE(i) + 0x38c) /** SPI_MEM_MODE_PSEUDO : R/W; bitpos: [1:0]; default: 0; * Set the mode of pseudo. 2'b00: crypto without pseudo. 2'b01: state T with pseudo * and state D without pseudo. 2'b10: state T with pseudo and state D with few pseudo. @@ -5604,7 +5604,7 @@ extern "C" { /** SPI_MEM_DATE_REG register * SPI0 version control register */ -#define SPI_MEM_DATE_REG(i) (REG_SPI_MEM_BASE(i) + 0x3fc) +#define SPI_MEM_DATE_REG(i) (DR_REG_SPI_MEM_BASE(i) + 0x3fc) /** SPI_MEM_DATE : R/W; bitpos: [27:0]; default: 37814608; * SPI0 register version. */ diff --git a/components/soc/esp32h21/register/soc/spi_struct.h b/components/soc/esp32h21/register/soc/spi_struct.h index a47c7b374e8..46ed7a70d0c 100644 --- a/components/soc/esp32h21/register/soc/spi_struct.h +++ b/components/soc/esp32h21/register/soc/spi_struct.h @@ -1550,214 +1550,18 @@ typedef union { /** Group: CPU-controlled data buffer */ -/** Type of w0 register - * SPI CPU-controlled buffer0 +/** Type of wn register + * SPI CPU-controlled buffer */ typedef union { struct { /** buf0 : R/W/SS; bitpos: [31:0]; default: 0; * 32-bit data buffer $n. */ - uint32_t buf0:32; + uint32_t buf:32; }; uint32_t val; -} spi_w0_reg_t; - -/** Type of w1 register - * SPI CPU-controlled buffer1 - */ -typedef union { - struct { - /** buf1 : R/W/SS; bitpos: [31:0]; default: 0; - * 32-bit data buffer $n. - */ - uint32_t buf1:32; - }; - uint32_t val; -} spi_w1_reg_t; - -/** Type of w2 register - * SPI CPU-controlled buffer2 - */ -typedef union { - struct { - /** buf2 : R/W/SS; bitpos: [31:0]; default: 0; - * 32-bit data buffer $n. - */ - uint32_t buf2:32; - }; - uint32_t val; -} spi_w2_reg_t; - -/** Type of w3 register - * SPI CPU-controlled buffer3 - */ -typedef union { - struct { - /** buf3 : R/W/SS; bitpos: [31:0]; default: 0; - * 32-bit data buffer $n. - */ - uint32_t buf3:32; - }; - uint32_t val; -} spi_w3_reg_t; - -/** Type of w4 register - * SPI CPU-controlled buffer4 - */ -typedef union { - struct { - /** buf4 : R/W/SS; bitpos: [31:0]; default: 0; - * 32-bit data buffer $n. - */ - uint32_t buf4:32; - }; - uint32_t val; -} spi_w4_reg_t; - -/** Type of w5 register - * SPI CPU-controlled buffer5 - */ -typedef union { - struct { - /** buf5 : R/W/SS; bitpos: [31:0]; default: 0; - * 32-bit data buffer $n. - */ - uint32_t buf5:32; - }; - uint32_t val; -} spi_w5_reg_t; - -/** Type of w6 register - * SPI CPU-controlled buffer6 - */ -typedef union { - struct { - /** buf6 : R/W/SS; bitpos: [31:0]; default: 0; - * 32-bit data buffer $n. - */ - uint32_t buf6:32; - }; - uint32_t val; -} spi_w6_reg_t; - -/** Type of w7 register - * SPI CPU-controlled buffer7 - */ -typedef union { - struct { - /** buf7 : R/W/SS; bitpos: [31:0]; default: 0; - * 32-bit data buffer $n. - */ - uint32_t buf7:32; - }; - uint32_t val; -} spi_w7_reg_t; - -/** Type of w8 register - * SPI CPU-controlled buffer8 - */ -typedef union { - struct { - /** buf8 : R/W/SS; bitpos: [31:0]; default: 0; - * 32-bit data buffer $n. - */ - uint32_t buf8:32; - }; - uint32_t val; -} spi_w8_reg_t; - -/** Type of w9 register - * SPI CPU-controlled buffer9 - */ -typedef union { - struct { - /** buf9 : R/W/SS; bitpos: [31:0]; default: 0; - * 32-bit data buffer $n. - */ - uint32_t buf9:32; - }; - uint32_t val; -} spi_w9_reg_t; - -/** Type of w10 register - * SPI CPU-controlled buffer10 - */ -typedef union { - struct { - /** buf10 : R/W/SS; bitpos: [31:0]; default: 0; - * 32-bit data buffer $n. - */ - uint32_t buf10:32; - }; - uint32_t val; -} spi_w10_reg_t; - -/** Type of w11 register - * SPI CPU-controlled buffer11 - */ -typedef union { - struct { - /** buf11 : R/W/SS; bitpos: [31:0]; default: 0; - * 32-bit data buffer $n. - */ - uint32_t buf11:32; - }; - uint32_t val; -} spi_w11_reg_t; - -/** Type of w12 register - * SPI CPU-controlled buffer12 - */ -typedef union { - struct { - /** buf12 : R/W/SS; bitpos: [31:0]; default: 0; - * 32-bit data buffer $n. - */ - uint32_t buf12:32; - }; - uint32_t val; -} spi_w12_reg_t; - -/** Type of w13 register - * SPI CPU-controlled buffer13 - */ -typedef union { - struct { - /** buf13 : R/W/SS; bitpos: [31:0]; default: 0; - * 32-bit data buffer $n. - */ - uint32_t buf13:32; - }; - uint32_t val; -} spi_w13_reg_t; - -/** Type of w14 register - * SPI CPU-controlled buffer14 - */ -typedef union { - struct { - /** buf14 : R/W/SS; bitpos: [31:0]; default: 0; - * 32-bit data buffer $n. - */ - uint32_t buf14:32; - }; - uint32_t val; -} spi_w14_reg_t; - -/** Type of w15 register - * SPI CPU-controlled buffer15 - */ -typedef union { - struct { - /** buf15 : R/W/SS; bitpos: [31:0]; default: 0; - * 32-bit data buffer $n. - */ - uint32_t buf15:32; - }; - uint32_t val; -} spi_w15_reg_t; - +} spi_wn_reg_t; /** Group: Version register */ /** Type of date register @@ -1795,22 +1599,7 @@ typedef struct { volatile spi_dma_int_st_reg_t dma_int_st; volatile spi_dma_int_set_reg_t dma_int_set; uint32_t reserved_048[20]; - volatile spi_w0_reg_t w0; - volatile spi_w1_reg_t w1; - volatile spi_w2_reg_t w2; - volatile spi_w3_reg_t w3; - volatile spi_w4_reg_t w4; - volatile spi_w5_reg_t w5; - volatile spi_w6_reg_t w6; - volatile spi_w7_reg_t w7; - volatile spi_w8_reg_t w8; - volatile spi_w9_reg_t w9; - volatile spi_w10_reg_t w10; - volatile spi_w11_reg_t w11; - volatile spi_w12_reg_t w12; - volatile spi_w13_reg_t w13; - volatile spi_w14_reg_t w14; - volatile spi_w15_reg_t w15; + volatile spi_wn_reg_t data_buf[16]; uint32_t reserved_0d8[2]; volatile spi_slave_reg_t slave; volatile spi_slave1_reg_t slave1; diff --git a/components/soc/esp32h21/register/soc/system_reg.h b/components/soc/esp32h21/register/soc/system_reg.h new file mode 100644 index 00000000000..86453435e09 --- /dev/null +++ b/components/soc/esp32h21/register/soc/system_reg.h @@ -0,0 +1,11 @@ +/* + * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include "soc/hp_system_reg.h" +#include "intpri_reg.h" + +#define SYSTEM_CPU_INTR_FROM_CPU_0_REG INTPRI_CPU_INTR_FROM_CPU_0_REG +#define SYSTEM_CPU_INTR_FROM_CPU_0 INTPRI_CPU_INTR_FROM_CPU_0 diff --git a/components/soc/esp32h21/register/soc/systimer_struct.h b/components/soc/esp32h21/register/soc/systimer_struct.h index f69a7f69c96..d136c6bcce5 100644 --- a/components/soc/esp32h21/register/soc/systimer_struct.h +++ b/components/soc/esp32h21/register/soc/systimer_struct.h @@ -68,24 +68,24 @@ typedef union { /** Group: SYSTEM TIMER UNIT0 CONTROL AND CONFIGURATION REGISTER */ -/** Type of unit0_op register - * system timer unit0 value update register +/** Type of unit_op register + * system timer unit value update register */ typedef union { struct { uint32_t reserved_0:29; - /** timer_unit0_value_valid : R/SS/WTC; bitpos: [29]; default: 0; + /** timer_unit_value_valid : R/SS/WTC; bitpos: [29]; default: 0; * timer value is sync and valid */ - uint32_t timer_unit0_value_valid:1; - /** timer_unit0_update : WT; bitpos: [30]; default: 0; + uint32_t timer_unit_value_valid:1; + /** timer_unit_update : WT; bitpos: [30]; default: 0; * update timer_unit0 */ - uint32_t timer_unit0_update:1; + uint32_t timer_unit_update:1; uint32_t reserved_31:1; }; uint32_t val; -} systimer_unit0_op_reg_t; +} systimer_unit_op_reg_t; /** Type of unit0_load_hi register * system timer unit0 value high load register @@ -95,7 +95,7 @@ typedef union { /** timer_unit0_load_hi : R/W; bitpos: [19:0]; default: 0; * timer unit0 load high 20 bits */ - uint32_t timer_unit0_load_hi:20; + uint32_t timer_unit_load_hi:20; uint32_t reserved_20:12; }; uint32_t val; @@ -106,10 +106,10 @@ typedef union { */ typedef union { struct { - /** timer_unit0_load_lo : R/W; bitpos: [31:0]; default: 0; - * timer unit0 load low 32 bits + /** timer_unit_load_lo : R/W; bitpos: [31:0]; default: 0; + * timer unit load low 32 bits */ - uint32_t timer_unit0_load_lo:32; + uint32_t timer_unit_load_lo:32; }; uint32_t val; } systimer_unit0_load_lo_reg_t; @@ -119,10 +119,10 @@ typedef union { */ typedef union { struct { - /** timer_unit0_value_hi : RO; bitpos: [19:0]; default: 0; + /** timer_unit_value_hi : RO; bitpos: [19:0]; default: 0; * timer read value high 20bits */ - uint32_t timer_unit0_value_hi:20; + uint32_t timer_unit_value_hi:20; uint32_t reserved_20:12; }; uint32_t val; @@ -133,48 +133,27 @@ typedef union { */ typedef union { struct { - /** timer_unit0_value_lo : RO; bitpos: [31:0]; default: 0; + /** timer_unit_value_lo : RO; bitpos: [31:0]; default: 0; * timer read value low 32bits */ - uint32_t timer_unit0_value_lo:32; + uint32_t timer_unit_value_lo:32; }; uint32_t val; } systimer_unit0_value_lo_reg_t; -/** Type of unit0_load register - * system timer unit0 conf sync register +/** Type of unit_load register + * system timer unit conf sync register */ typedef union { struct { - /** timer_unit0_load : WT; bitpos: [0]; default: 0; - * timer unit0 sync enable signal + /** timer_unit_load : WT; bitpos: [0]; default: 0; + * timer unit sync enable signal */ uint32_t timer_unit0_load:1; uint32_t reserved_1:31; }; uint32_t val; -} systimer_unit0_load_reg_t; - - -/** Group: SYSTEM TIMER UNIT1 CONTROL AND CONFIGURATION REGISTER */ -/** Type of unit1_op register - * system timer unit1 value update register - */ -typedef union { - struct { - uint32_t reserved_0:29; - /** timer_unit1_value_valid : R/SS/WTC; bitpos: [29]; default: 0; - * timer value is sync and valid - */ - uint32_t timer_unit1_value_valid:1; - /** timer_unit1_update : WT; bitpos: [30]; default: 0; - * update timer unit1 - */ - uint32_t timer_unit1_update:1; - uint32_t reserved_31:1; - }; - uint32_t val; -} systimer_unit1_op_reg_t; +} systimer_unit_load_reg_t; /** Type of unit1_load_hi register * system timer unit1 value high load register @@ -230,31 +209,16 @@ typedef union { uint32_t val; } systimer_unit1_value_lo_reg_t; -/** Type of unit1_load register - * system timer unit1 conf sync register - */ -typedef union { - struct { - /** timer_unit1_load : WT; bitpos: [0]; default: 0; - * timer unit1 sync enable signal - */ - uint32_t timer_unit1_load:1; - uint32_t reserved_1:31; - }; - uint32_t val; -} systimer_unit1_load_reg_t; - - /** Group: SYSTEM TIMER COMP0 CONTROL AND CONFIGURATION REGISTER */ /** Type of target0_hi register * system timer comp0 value high register */ typedef union { struct { - /** timer_target0_hi : R/W; bitpos: [19:0]; default: 0; + /** timer_target_hi : R/W; bitpos: [19:0]; default: 0; * timer taget0 high 20 bits */ - uint32_t timer_target0_hi:20; + uint32_t timer_target_hi:20; uint32_t reserved_20:12; }; uint32_t val; @@ -265,49 +229,49 @@ typedef union { */ typedef union { struct { - /** timer_target0_lo : R/W; bitpos: [31:0]; default: 0; - * timer taget0 low 32 bits + /** timer_target_lo : R/W; bitpos: [31:0]; default: 0; + * timer target low 32 bits */ - uint32_t timer_target0_lo:32; + uint32_t timer_target_lo:32; }; uint32_t val; } systimer_target0_lo_reg_t; -/** Type of target0_conf register +/** Type of target_conf register * system timer comp0 target mode register */ typedef union { struct { - /** target0_period : R/W; bitpos: [25:0]; default: 0; - * target0 period + /** target_period : R/W; bitpos: [25:0]; default: 0; + * target period */ - uint32_t target0_period:26; + uint32_t target_period:26; uint32_t reserved_26:4; - /** target0_period_mode : R/W; bitpos: [30]; default: 0; - * Set target0 to period mode + /** target_period_mode : R/W; bitpos: [30]; default: 0; + * Set target to period mode */ - uint32_t target0_period_mode:1; + uint32_t target_period_mode:1; /** target0_timer_unit_sel : R/W; bitpos: [31]; default: 0; * select which unit to compare */ - uint32_t target0_timer_unit_sel:1; + uint32_t target_timer_unit_sel:1; }; uint32_t val; -} systimer_target0_conf_reg_t; +} systimer_target_conf_reg_t; -/** Type of comp0_load register - * system timer comp0 conf sync register +/** Type of comp_load register + * system timer comp conf sync register */ typedef union { struct { - /** timer_comp0_load : WT; bitpos: [0]; default: 0; - * timer comp0 sync enable signal + /** timer_comp_load : WT; bitpos: [0]; default: 0; + * timer comp sync enable signal */ uint32_t timer_comp0_load:1; uint32_t reserved_1:31; }; uint32_t val; -} systimer_comp0_load_reg_t; +} systimer_comp_load_reg_t; /** Group: SYSTEM TIMER COMP1 CONTROL AND CONFIGURATION REGISTER */ @@ -360,21 +324,6 @@ typedef union { uint32_t val; } systimer_target1_conf_reg_t; -/** Type of comp1_load register - * system timer comp1 conf sync register - */ -typedef union { - struct { - /** timer_comp1_load : WT; bitpos: [0]; default: 0; - * timer comp1 sync enable signal - */ - uint32_t timer_comp1_load:1; - uint32_t reserved_1:31; - }; - uint32_t val; -} systimer_comp1_load_reg_t; - - /** Group: SYSTEM TIMER COMP2 CONTROL AND CONFIGURATION REGISTER */ /** Type of target2_hi register * system timer comp2 value high register @@ -403,43 +352,6 @@ typedef union { uint32_t val; } systimer_target2_lo_reg_t; -/** Type of target2_conf register - * system timer comp2 target mode register - */ -typedef union { - struct { - /** target2_period : R/W; bitpos: [25:0]; default: 0; - * target2 period - */ - uint32_t target2_period:26; - uint32_t reserved_26:4; - /** target2_period_mode : R/W; bitpos: [30]; default: 0; - * Set target2 to period mode - */ - uint32_t target2_period_mode:1; - /** target2_timer_unit_sel : R/W; bitpos: [31]; default: 0; - * select which unit to compare - */ - uint32_t target2_timer_unit_sel:1; - }; - uint32_t val; -} systimer_target2_conf_reg_t; - -/** Type of comp2_load register - * system timer comp2 conf sync register - */ -typedef union { - struct { - /** timer_comp2_load : WT; bitpos: [0]; default: 0; - * timer comp2 sync enable signal - */ - uint32_t timer_comp2_load:1; - uint32_t reserved_1:31; - }; - uint32_t val; -} systimer_comp2_load_reg_t; - - /** Group: SYSTEM TIMER INTERRUPT REGISTER */ /** Type of int_ena register * systimer interrupt enable register @@ -631,43 +543,44 @@ typedef union { uint32_t val; } systimer_date_reg_t; - -typedef struct { +typedef struct systimer_unit_load_val_reg +{ + systimer_unit0_load_hi_reg_t hi; + systimer_unit0_load_lo_reg_t lo; +} systimer_unit_load_val_reg_t; + +typedef struct systimer_target_val_reg +{ + systimer_target0_hi_reg_t hi; + systimer_target0_lo_reg_t lo; +} systimer_target_val_reg_t; + +typedef struct systimer_unit_value_reg +{ + systimer_unit0_value_hi_reg_t hi; + systimer_unit0_value_lo_reg_t lo; +} systimer_unit_value_reg_t; + +typedef struct systimer_real_target_reg +{ + systimer_real_target0_lo_reg_t lo; + systimer_real_target0_hi_reg_t hi; +} systimer_real_target_reg_t; + +typedef struct systimer_dev_t{ volatile systimer_conf_reg_t conf; - volatile systimer_unit0_op_reg_t unit0_op; - volatile systimer_unit1_op_reg_t unit1_op; - volatile systimer_unit0_load_hi_reg_t unit0_load_hi; - volatile systimer_unit0_load_lo_reg_t unit0_load_lo; - volatile systimer_unit1_load_hi_reg_t unit1_load_hi; - volatile systimer_unit1_load_lo_reg_t unit1_load_lo; - volatile systimer_target0_hi_reg_t target0_hi; - volatile systimer_target0_lo_reg_t target0_lo; - volatile systimer_target1_hi_reg_t target1_hi; - volatile systimer_target1_lo_reg_t target1_lo; - volatile systimer_target2_hi_reg_t target2_hi; - volatile systimer_target2_lo_reg_t target2_lo; - volatile systimer_target0_conf_reg_t target0_conf; - volatile systimer_target1_conf_reg_t target1_conf; - volatile systimer_target2_conf_reg_t target2_conf; - volatile systimer_unit0_value_hi_reg_t unit0_value_hi; - volatile systimer_unit0_value_lo_reg_t unit0_value_lo; - volatile systimer_unit1_value_hi_reg_t unit1_value_hi; - volatile systimer_unit1_value_lo_reg_t unit1_value_lo; - volatile systimer_comp0_load_reg_t comp0_load; - volatile systimer_comp1_load_reg_t comp1_load; - volatile systimer_comp2_load_reg_t comp2_load; - volatile systimer_unit0_load_reg_t unit0_load; - volatile systimer_unit1_load_reg_t unit1_load; + volatile systimer_unit_op_reg_t unit_op[2]; + volatile systimer_unit_load_val_reg_t unit_load_val[2]; + volatile systimer_target_val_reg_t target_val[3]; + volatile systimer_target_conf_reg_t target_conf[3]; + volatile systimer_unit_value_reg_t unit_val[2]; + volatile systimer_comp_load_reg_t comp_load[3]; + volatile systimer_unit_load_reg_t unit_load[2]; volatile systimer_int_ena_reg_t int_ena; volatile systimer_int_raw_reg_t int_raw; volatile systimer_int_clr_reg_t int_clr; volatile systimer_int_st_reg_t int_st; - volatile systimer_real_target0_lo_reg_t real_target0_lo; - volatile systimer_real_target0_hi_reg_t real_target0_hi; - volatile systimer_real_target1_lo_reg_t real_target1_lo; - volatile systimer_real_target1_hi_reg_t real_target1_hi; - volatile systimer_real_target2_lo_reg_t real_target2_lo; - volatile systimer_real_target2_hi_reg_t real_target2_hi; + volatile systimer_real_target_reg_t real_target[3]; uint32_t reserved_08c[28]; volatile systimer_date_reg_t date; } systimer_dev_t; diff --git a/components/soc/esp32h21/register/soc/timer_group_struct.h b/components/soc/esp32h21/register/soc/timer_group_struct.h index 81eefe5cb57..c5360f1c0b0 100644 --- a/components/soc/esp32h21/register/soc/timer_group_struct.h +++ b/components/soc/esp32h21/register/soc/timer_group_struct.h @@ -519,17 +519,20 @@ typedef union { uint32_t val; } timg_regclk_reg_t; +typedef struct { + volatile timg_txconfig_reg_t config; + volatile timg_txlo_reg_t lo; + volatile timg_txhi_reg_t hi; + volatile timg_txupdate_reg_t update; + volatile timg_txalarmlo_reg_t alarmlo; + volatile timg_txalarmhi_reg_t alarmhi; + volatile timg_txloadlo_reg_t loadlo; + volatile timg_txloadhi_reg_t loadhi; + volatile timg_txload_reg_t load; +} timg_hwtimer_reg_t; typedef struct { - volatile timg_txconfig_reg_t t0config; - volatile timg_txlo_reg_t t0lo; - volatile timg_txhi_reg_t t0hi; - volatile timg_txupdate_reg_t t0update; - volatile timg_txalarmlo_reg_t t0alarmlo; - volatile timg_txalarmhi_reg_t t0alarmhi; - volatile timg_txloadlo_reg_t t0loadlo; - volatile timg_txloadhi_reg_t t0loadhi; - volatile timg_txload_reg_t t0load; + volatile timg_hwtimer_reg_t hw_timer[1]; uint32_t reserved_024[9]; volatile timg_wdtconfig0_reg_t wdtconfig0; volatile timg_wdtconfig1_reg_t wdtconfig1; diff --git a/components/soc/esp32h21/register/soc/uart_reg.h b/components/soc/esp32h21/register/soc/uart_reg.h index 1a614cf327c..149160e0047 100644 --- a/components/soc/esp32h21/register/soc/uart_reg.h +++ b/components/soc/esp32h21/register/soc/uart_reg.h @@ -14,7 +14,7 @@ extern "C" { /** UART_FIFO_REG register * FIFO data register */ -#define UART_FIFO_REG(i) (REG_UART_BASE(i) + 0x0) +#define UART_FIFO_REG(i) (DR_REG_UART_BASE(i) + 0x0) /** UART_RXFIFO_RD_BYTE : RO; bitpos: [7:0]; default: 0; * UART $n accesses FIFO via this register. */ @@ -26,7 +26,7 @@ extern "C" { /** UART_INT_RAW_REG register * Raw interrupt status */ -#define UART_INT_RAW_REG(i) (REG_UART_BASE(i) + 0x4) +#define UART_INT_RAW_REG(i) (DR_REG_UART_BASE(i) + 0x4) /** UART_RXFIFO_FULL_INT_RAW : R/WTC/SS; bitpos: [0]; default: 0; * This interrupt raw bit turns to high level when receiver receives more data than * what rxfifo_full_thrhd specifies. @@ -191,7 +191,7 @@ extern "C" { /** UART_INT_ST_REG register * Masked interrupt status */ -#define UART_INT_ST_REG(i) (REG_UART_BASE(i) + 0x8) +#define UART_INT_ST_REG(i) (DR_REG_UART_BASE(i) + 0x8) /** UART_RXFIFO_FULL_INT_ST : RO; bitpos: [0]; default: 0; * This is the status bit for rxfifo_full_int_raw when rxfifo_full_int_ena is set to 1. */ @@ -341,7 +341,7 @@ extern "C" { /** UART_INT_ENA_REG register * Interrupt enable bits */ -#define UART_INT_ENA_REG(i) (REG_UART_BASE(i) + 0xc) +#define UART_INT_ENA_REG(i) (DR_REG_UART_BASE(i) + 0xc) /** UART_RXFIFO_FULL_INT_ENA : R/W; bitpos: [0]; default: 0; * This is the enable bit for rxfifo_full_int_st register. */ @@ -486,7 +486,7 @@ extern "C" { /** UART_INT_CLR_REG register * Interrupt clear bits */ -#define UART_INT_CLR_REG(i) (REG_UART_BASE(i) + 0x10) +#define UART_INT_CLR_REG(i) (DR_REG_UART_BASE(i) + 0x10) /** UART_RXFIFO_FULL_INT_CLR : WT; bitpos: [0]; default: 0; * Set this bit to clear the rxfifo_full_int_raw interrupt. */ @@ -631,7 +631,7 @@ extern "C" { /** UART_CLKDIV_SYNC_REG register * Clock divider configuration */ -#define UART_CLKDIV_SYNC_REG(i) (REG_UART_BASE(i) + 0x14) +#define UART_CLKDIV_SYNC_REG(i) (DR_REG_UART_BASE(i) + 0x14) /** UART_CLKDIV : R/W; bitpos: [11:0]; default: 694; * The integral part of the frequency divider factor. */ @@ -650,7 +650,7 @@ extern "C" { /** UART_RX_FILT_REG register * Rx Filter configuration */ -#define UART_RX_FILT_REG(i) (REG_UART_BASE(i) + 0x18) +#define UART_RX_FILT_REG(i) (DR_REG_UART_BASE(i) + 0x18) /** UART_GLITCH_FILT : R/W; bitpos: [7:0]; default: 8; * when input pulse width is lower than this value the pulse is ignored. */ @@ -669,7 +669,7 @@ extern "C" { /** UART_STATUS_REG register * UART status register */ -#define UART_STATUS_REG(i) (REG_UART_BASE(i) + 0x1c) +#define UART_STATUS_REG(i) (DR_REG_UART_BASE(i) + 0x1c) /** UART_RXFIFO_CNT : RO; bitpos: [7:0]; default: 0; * Stores the byte number of valid data in Rx-FIFO. */ @@ -730,7 +730,7 @@ extern "C" { /** UART_CONF0_SYNC_REG register * a */ -#define UART_CONF0_SYNC_REG(i) (REG_UART_BASE(i) + 0x20) +#define UART_CONF0_SYNC_REG(i) (DR_REG_UART_BASE(i) + 0x20) /** UART_PARITY : R/W; bitpos: [0]; default: 0; * This register is used to configure the parity check mode. */ @@ -893,7 +893,7 @@ extern "C" { /** UART_CONF1_REG register * Configuration register 1 */ -#define UART_CONF1_REG(i) (REG_UART_BASE(i) + 0x24) +#define UART_CONF1_REG(i) (DR_REG_UART_BASE(i) + 0x24) /** UART_RXFIFO_FULL_THRHD : R/W; bitpos: [7:0]; default: 96; * It will produce rxfifo_full_int interrupt when receiver receives more data than * this register value. @@ -958,7 +958,7 @@ extern "C" { /** UART_HWFC_CONF_SYNC_REG register * Hardware flow-control configuration */ -#define UART_HWFC_CONF_SYNC_REG(i) (REG_UART_BASE(i) + 0x2c) +#define UART_HWFC_CONF_SYNC_REG(i) (DR_REG_UART_BASE(i) + 0x2c) /** UART_RX_FLOW_THRHD : R/W; bitpos: [7:0]; default: 0; * This register is used to configure the maximum amount of data that can be received * when hardware flow control works. @@ -978,7 +978,7 @@ extern "C" { /** UART_SLEEP_CONF0_REG register * UART sleep configure register 0 */ -#define UART_SLEEP_CONF0_REG(i) (REG_UART_BASE(i) + 0x30) +#define UART_SLEEP_CONF0_REG(i) (DR_REG_UART_BASE(i) + 0x30) /** UART_WK_CHAR1 : R/W; bitpos: [7:0]; default: 0; * This register restores the specified wake up char1 to wake up */ @@ -1011,7 +1011,7 @@ extern "C" { /** UART_SLEEP_CONF1_REG register * UART sleep configure register 1 */ -#define UART_SLEEP_CONF1_REG(i) (REG_UART_BASE(i) + 0x34) +#define UART_SLEEP_CONF1_REG(i) (DR_REG_UART_BASE(i) + 0x34) /** UART_WK_CHAR0 : R/W; bitpos: [7:0]; default: 0; * This register restores the specified char0 to wake up */ @@ -1023,7 +1023,7 @@ extern "C" { /** UART_SLEEP_CONF2_REG register * UART sleep configure register 2 */ -#define UART_SLEEP_CONF2_REG(i) (REG_UART_BASE(i) + 0x38) +#define UART_SLEEP_CONF2_REG(i) (DR_REG_UART_BASE(i) + 0x38) /** UART_ACTIVE_THRESHOLD : R/W; bitpos: [9:0]; default: 240; * The uart is activated from light sleeping mode when the input rxd edge changes more * times than this register value. @@ -1066,7 +1066,7 @@ extern "C" { /** UART_SWFC_CONF0_SYNC_REG register * Software flow-control character configuration */ -#define UART_SWFC_CONF0_SYNC_REG(i) (REG_UART_BASE(i) + 0x3c) +#define UART_SWFC_CONF0_SYNC_REG(i) (DR_REG_UART_BASE(i) + 0x3c) /** UART_XON_CHAR : R/W; bitpos: [7:0]; default: 17; * This register stores the Xon flow control char. */ @@ -1138,7 +1138,7 @@ extern "C" { /** UART_SWFC_CONF1_REG register * Software flow-control character configuration */ -#define UART_SWFC_CONF1_REG(i) (REG_UART_BASE(i) + 0x40) +#define UART_SWFC_CONF1_REG(i) (DR_REG_UART_BASE(i) + 0x40) /** UART_XON_THRESHOLD : R/W; bitpos: [7:0]; default: 0; * When the data amount in Rx-FIFO is less than this register value with * uart_sw_flow_con_en set to 1 it will send a Xon char. @@ -1159,7 +1159,7 @@ extern "C" { /** UART_TXBRK_CONF_SYNC_REG register * Tx Break character configuration */ -#define UART_TXBRK_CONF_SYNC_REG(i) (REG_UART_BASE(i) + 0x44) +#define UART_TXBRK_CONF_SYNC_REG(i) (DR_REG_UART_BASE(i) + 0x44) /** UART_TX_BRK_NUM : R/W; bitpos: [7:0]; default: 10; * This register is used to configure the number of 0 to be sent after the process of * sending data is done. It is active when txd_brk is set to 1. @@ -1172,7 +1172,7 @@ extern "C" { /** UART_IDLE_CONF_SYNC_REG register * Frame-end idle configuration */ -#define UART_IDLE_CONF_SYNC_REG(i) (REG_UART_BASE(i) + 0x48) +#define UART_IDLE_CONF_SYNC_REG(i) (DR_REG_UART_BASE(i) + 0x48) /** UART_RX_IDLE_THRHD : R/W; bitpos: [9:0]; default: 256; * It will produce frame end signal when receiver takes more time to receive one byte * data than this register value. @@ -1192,7 +1192,7 @@ extern "C" { /** UART_RS485_CONF_SYNC_REG register * RS485 mode configuration */ -#define UART_RS485_CONF_SYNC_REG(i) (REG_UART_BASE(i) + 0x4c) +#define UART_RS485_CONF_SYNC_REG(i) (DR_REG_UART_BASE(i) + 0x4c) /** UART_RS485_EN : R/W; bitpos: [0]; default: 0; * Set this bit to choose the rs485 mode. */ @@ -1247,7 +1247,7 @@ extern "C" { /** UART_AT_CMD_PRECNT_SYNC_REG register * Pre-sequence timing configuration */ -#define UART_AT_CMD_PRECNT_SYNC_REG(i) (REG_UART_BASE(i) + 0x50) +#define UART_AT_CMD_PRECNT_SYNC_REG(i) (DR_REG_UART_BASE(i) + 0x50) /** UART_PRE_IDLE_NUM : R/W; bitpos: [15:0]; default: 2305; * This register is used to configure the idle duration time before the first at_cmd * is received by receiver. @@ -1260,7 +1260,7 @@ extern "C" { /** UART_AT_CMD_POSTCNT_SYNC_REG register * Post-sequence timing configuration */ -#define UART_AT_CMD_POSTCNT_SYNC_REG(i) (REG_UART_BASE(i) + 0x54) +#define UART_AT_CMD_POSTCNT_SYNC_REG(i) (DR_REG_UART_BASE(i) + 0x54) /** UART_POST_IDLE_NUM : R/W; bitpos: [15:0]; default: 2305; * This register is used to configure the duration time between the last at_cmd and * the next data. @@ -1273,7 +1273,7 @@ extern "C" { /** UART_AT_CMD_GAPTOUT_SYNC_REG register * Timeout configuration */ -#define UART_AT_CMD_GAPTOUT_SYNC_REG(i) (REG_UART_BASE(i) + 0x58) +#define UART_AT_CMD_GAPTOUT_SYNC_REG(i) (DR_REG_UART_BASE(i) + 0x58) /** UART_RX_GAP_TOUT : R/W; bitpos: [15:0]; default: 11; * This register is used to configure the duration time between the at_cmd chars. */ @@ -1285,7 +1285,7 @@ extern "C" { /** UART_AT_CMD_CHAR_SYNC_REG register * AT escape sequence detection configuration */ -#define UART_AT_CMD_CHAR_SYNC_REG(i) (REG_UART_BASE(i) + 0x5c) +#define UART_AT_CMD_CHAR_SYNC_REG(i) (DR_REG_UART_BASE(i) + 0x5c) /** UART_AT_CMD_CHAR : R/W; bitpos: [7:0]; default: 43; * This register is used to configure the content of at_cmd char. */ @@ -1305,7 +1305,7 @@ extern "C" { /** UART_MEM_CONF_REG register * UART memory power configuration */ -#define UART_MEM_CONF_REG(i) (REG_UART_BASE(i) + 0x60) +#define UART_MEM_CONF_REG(i) (DR_REG_UART_BASE(i) + 0x60) /** UART_MEM_FORCE_PD : R/W; bitpos: [25]; default: 0; * Set this bit to force power down UART memory. */ @@ -1324,7 +1324,7 @@ extern "C" { /** UART_TOUT_CONF_SYNC_REG register * UART threshold and allocation configuration */ -#define UART_TOUT_CONF_SYNC_REG(i) (REG_UART_BASE(i) + 0x64) +#define UART_TOUT_CONF_SYNC_REG(i) (DR_REG_UART_BASE(i) + 0x64) /** UART_RX_TOUT_EN : R/W; bitpos: [0]; default: 0; * This is the enable bit for uart receiver's timeout function. */ @@ -1352,7 +1352,7 @@ extern "C" { /** UART_MEM_TX_STATUS_REG register * Tx-SRAM write and read offset address. */ -#define UART_MEM_TX_STATUS_REG(i) (REG_UART_BASE(i) + 0x68) +#define UART_MEM_TX_STATUS_REG(i) (DR_REG_UART_BASE(i) + 0x68) /** UART_TX_SRAM_WADDR : RO; bitpos: [7:0]; default: 0; * This register stores the offset write address in Tx-SRAM. */ @@ -1371,7 +1371,7 @@ extern "C" { /** UART_MEM_RX_STATUS_REG register * Rx-SRAM write and read offset address. */ -#define UART_MEM_RX_STATUS_REG(i) (REG_UART_BASE(i) + 0x6c) +#define UART_MEM_RX_STATUS_REG(i) (DR_REG_UART_BASE(i) + 0x6c) /** UART_RX_SRAM_RADDR : RO; bitpos: [7:0]; default: 128; * This register stores the offset read address in RX-SRAM. */ @@ -1390,7 +1390,7 @@ extern "C" { /** UART_FSM_STATUS_REG register * UART transmit and receive status. */ -#define UART_FSM_STATUS_REG(i) (REG_UART_BASE(i) + 0x70) +#define UART_FSM_STATUS_REG(i) (DR_REG_UART_BASE(i) + 0x70) /** UART_ST_URX_OUT : RO; bitpos: [3:0]; default: 0; * This is the status register of receiver. */ @@ -1409,7 +1409,7 @@ extern "C" { /** UART_POSPULSE_REG register * Autobaud high pulse register */ -#define UART_POSPULSE_REG(i) (REG_UART_BASE(i) + 0x74) +#define UART_POSPULSE_REG(i) (DR_REG_UART_BASE(i) + 0x74) /** UART_POSEDGE_MIN_CNT : RO; bitpos: [11:0]; default: 4095; * This register stores the minimal input clock count between two positive edges. It * is used in boudrate-detect process. @@ -1422,7 +1422,7 @@ extern "C" { /** UART_NEGPULSE_REG register * Autobaud low pulse register */ -#define UART_NEGPULSE_REG(i) (REG_UART_BASE(i) + 0x78) +#define UART_NEGPULSE_REG(i) (DR_REG_UART_BASE(i) + 0x78) /** UART_NEGEDGE_MIN_CNT : RO; bitpos: [11:0]; default: 4095; * This register stores the minimal input clock count between two negative edges. It * is used in boudrate-detect process. @@ -1435,7 +1435,7 @@ extern "C" { /** UART_LOWPULSE_REG register * Autobaud minimum low pulse duration register */ -#define UART_LOWPULSE_REG(i) (REG_UART_BASE(i) + 0x7c) +#define UART_LOWPULSE_REG(i) (DR_REG_UART_BASE(i) + 0x7c) /** UART_LOWPULSE_MIN_CNT : RO; bitpos: [11:0]; default: 4095; * This register stores the value of the minimum duration time of the low level pulse. * It is used in baud rate-detect process. @@ -1448,7 +1448,7 @@ extern "C" { /** UART_HIGHPULSE_REG register * Autobaud minimum high pulse duration register */ -#define UART_HIGHPULSE_REG(i) (REG_UART_BASE(i) + 0x80) +#define UART_HIGHPULSE_REG(i) (DR_REG_UART_BASE(i) + 0x80) /** UART_HIGHPULSE_MIN_CNT : RO; bitpos: [11:0]; default: 4095; * This register stores the value of the maximum duration time for the high level * pulse. It is used in baud rate-detect process. @@ -1461,7 +1461,7 @@ extern "C" { /** UART_RXD_CNT_REG register * Autobaud edge change count register */ -#define UART_RXD_CNT_REG(i) (REG_UART_BASE(i) + 0x84) +#define UART_RXD_CNT_REG(i) (DR_REG_UART_BASE(i) + 0x84) /** UART_RXD_EDGE_CNT : RO; bitpos: [9:0]; default: 0; * This register stores the count of rxd edge change. It is used in baud rate-detect * process. @@ -1474,7 +1474,7 @@ extern "C" { /** UART_CLK_CONF_REG register * UART core clock configuration */ -#define UART_CLK_CONF_REG(i) (REG_UART_BASE(i) + 0x88) +#define UART_CLK_CONF_REG(i) (DR_REG_UART_BASE(i) + 0x88) /** UART_TX_SCLK_EN : R/W; bitpos: [24]; default: 1; * Set this bit to enable UART Tx clock. */ @@ -1507,7 +1507,7 @@ extern "C" { /** UART_DATE_REG register * UART Version register */ -#define UART_DATE_REG(i) (REG_UART_BASE(i) + 0x8c) +#define UART_DATE_REG(i) (DR_REG_UART_BASE(i) + 0x8c) /** UART_DATE : R/W; bitpos: [31:0]; default: 35680848; * This is the version register. */ @@ -1519,7 +1519,7 @@ extern "C" { /** UART_AFIFO_STATUS_REG register * UART AFIFO Status */ -#define UART_AFIFO_STATUS_REG(i) (REG_UART_BASE(i) + 0x90) +#define UART_AFIFO_STATUS_REG(i) (DR_REG_UART_BASE(i) + 0x90) /** UART_TX_AFIFO_FULL : RO; bitpos: [0]; default: 0; * Full signal of APB TX AFIFO. */ @@ -1552,7 +1552,7 @@ extern "C" { /** UART_REG_UPDATE_REG register * UART Registers Configuration Update register */ -#define UART_REG_UPDATE_REG(i) (REG_UART_BASE(i) + 0x98) +#define UART_REG_UPDATE_REG(i) (DR_REG_UART_BASE(i) + 0x98) /** UART_REG_UPDATE : R/W/SC; bitpos: [0]; default: 0; * Software write 1 would synchronize registers into UART Core clock domain and would * be cleared by hardware after synchronization is done. @@ -1565,7 +1565,7 @@ extern "C" { /** UART_ID_REG register * UART ID register */ -#define UART_ID_REG(i) (REG_UART_BASE(i) + 0x9c) +#define UART_ID_REG(i) (DR_REG_UART_BASE(i) + 0x9c) /** UART_ID : R/W; bitpos: [31:0]; default: 1280; * This register is used to configure the uart_id. */ diff --git a/components/soc/esp32h21/register/soc/xts_aes_reg.h b/components/soc/esp32h21/register/soc/xts_aes_reg.h new file mode 100644 index 00000000000..599aaf3486c --- /dev/null +++ b/components/soc/esp32h21/register/soc/xts_aes_reg.h @@ -0,0 +1,129 @@ +/** + * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#include "soc/soc.h" +#ifdef __cplusplus +extern "C" { +#endif + +#define XTS_AES_PLAIN_MEM(i) (REG_SPI_MEM_BASE(i) + 0x300) +/* XTS_AES_PLAIN : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: This field is only used to generate include file in c case. This field is useles +s. Please do not use this field..*/ +#define XTS_AES_PLAIN 0xFFFFFFFF +#define XTS_AES_PLAIN_M ((XTS_AES_PLAIN_V)<<(XTS_AES_PLAIN_S)) +#define XTS_AES_PLAIN_V 0xFFFFFFFF +#define XTS_AES_PLAIN_S 0 + +#define XTS_AES_LINESIZE_REG(i) (REG_SPI_MEM_BASE(i) + 0x340) +/* XTS_AES_LINESIZE : R/W ;bitpos:[1:0] ;default: 2'h0 ; */ +/*description: This bits stores the line-size parameter which will be used in manual encryption + calculation. It decides how many bytes will be encrypted one time. 0: 16-bytes, + 1: 32-bytes, 2: 64-bytes, 3:reserved..*/ +#define XTS_AES_LINESIZE 0x00000003 +#define XTS_AES_LINESIZE_M ((XTS_AES_LINESIZE_V)<<(XTS_AES_LINESIZE_S)) +#define XTS_AES_LINESIZE_V 0x3 +#define XTS_AES_LINESIZE_S 0 + +#define XTS_AES_DESTINATION_REG(i) (REG_SPI_MEM_BASE(i) + 0x344) +/* XTS_AES_DESTINATION : R/W ;bitpos:[0] ;default: 1'b0 ; */ +/*description: This bit stores the destination parameter which will be used in manual encryption +n calculation. 0: flash(default), 1: psram(reserved). Only default value can be +used..*/ +#define XTS_AES_DESTINATION (BIT(0)) +#define XTS_AES_DESTINATION_M (BIT(0)) +#define XTS_AES_DESTINATION_V 0x1 +#define XTS_AES_DESTINATION_S 0 + +#define XTS_AES_PHYSICAL_ADDRESS_REG(i) (REG_SPI_MEM_BASE(i) + 0x348) +/* XTS_AES_PHYSICAL_ADDRESS : R/W ;bitpos:[25:0] ;default: 26'h0 ; */ +/*description: This bits stores the physical-address parameter which will be used in manual enc +ryption calculation. This value should aligned with byte number decided by line- +size parameter..*/ +#define XTS_AES_PHYSICAL_ADDRESS 0x03FFFFFF +#define XTS_AES_PHYSICAL_ADDRESS_M ((XTS_AES_PHYSICAL_ADDRESS_V)<<(XTS_AES_PHYSICAL_ADDRESS_S)) +#define XTS_AES_PHYSICAL_ADDRESS_V 0x3FFFFFF +#define XTS_AES_PHYSICAL_ADDRESS_S 0 + +#define XTS_AES_TRIGGER_REG(i) (REG_SPI_MEM_BASE(i) + 0x34C) +/* XTS_AES_TRIGGER : WT ;bitpos:[0] ;default: 1'b0 ; */ +/*description: Set this bit to trigger the process of manual encryption calculation. This actio +n should only be asserted when manual encryption status is 0. After this action, + manual encryption status becomes 1. After calculation is done, manual encryption +n status becomes 2..*/ +#define XTS_AES_TRIGGER (BIT(0)) +#define XTS_AES_TRIGGER_M (BIT(0)) +#define XTS_AES_TRIGGER_V 0x1 +#define XTS_AES_TRIGGER_S 0 + +#define XTS_AES_RELEASE_REG(i) (REG_SPI_MEM_BASE(i) + 0x350) +/* XTS_AES_RELEASE : WT ;bitpos:[0] ;default: 1'b0 ; */ +/*description: Set this bit to release encrypted result to mspi. This action should only be ass +erted when manual encryption status is 2. After this action, manual encryption s +tatus will become 3..*/ +#define XTS_AES_RELEASE (BIT(0)) +#define XTS_AES_RELEASE_M (BIT(0)) +#define XTS_AES_RELEASE_V 0x1 +#define XTS_AES_RELEASE_S 0 + +#define XTS_AES_DESTROY_REG(i) (REG_SPI_MEM_BASE(i) + 0x354) +/* XTS_AES_DESTROY : WT ;bitpos:[0] ;default: 1'b0 ; */ +/*description: Set this bit to destroy encrypted result. This action should be asserted only wh +en manual encryption status is 3. After this action, manual encryption status wi +ll become 0..*/ +#define XTS_AES_DESTROY (BIT(0)) +#define XTS_AES_DESTROY_M (BIT(0)) +#define XTS_AES_DESTROY_V 0x1 +#define XTS_AES_DESTROY_S 0 + +#define XTS_AES_STATE_REG(i) (REG_SPI_MEM_BASE(i) + 0x358) +/* XTS_AES_STATE : RO ;bitpos:[1:0] ;default: 2'h0 ; */ +/*description: This bits stores the status of manual encryption. 0: idle, 1: busy of encryption + calculation, 2: encryption calculation is done but the encrypted result is invi +sible to mspi, 3: the encrypted result is visible to mspi..*/ +#define XTS_AES_STATE 0x00000003 +#define XTS_AES_STATE_M ((XTS_AES_STATE_V)<<(XTS_AES_STATE_S)) +#define XTS_AES_STATE_V 0x3 +#define XTS_AES_STATE_S 0 + +#define XTS_AES_DATE_REG(i) (REG_SPI_MEM_BASE(i) + 0x35C) +/* XTS_AES_DATE : R/W ;bitpos:[29:0] ;default: 30'h20201010 ; */ +/*description: This bits stores the last modified-time of manual encryption feature..*/ +#define XTS_AES_DATE 0x3FFFFFFF +#define XTS_AES_DATE_M ((XTS_AES_DATE_V)<<(XTS_AES_DATE_S)) +#define XTS_AES_DATE_V 0x3FFFFFFF +#define XTS_AES_DATE_S 0 + +#define XTS_AES_DPA_CTRL_REG(i) (REG_SPI_MEM_BASE(i) + 0x388) +/* XTS_AES_CRYPT_DPA_SELECT_REGISTER : R/W ;bitpos:[4] ;default: 1'b0 ; */ +/*description: 1: MSPI XTS DPA clock gate is controlled by SPI_CRYPT_CALC_D_DPA_EN and SPI_CRYP +T_SECURITY_LEVEL. 0: Controlled by efuse bits..*/ +#define XTS_AES_CRYPT_DPA_SELECT_REGISTER (BIT(4)) +#define XTS_AES_CRYPT_DPA_SELECT_REGISTER_M (BIT(4)) +#define XTS_AES_CRYPT_DPA_SELECT_REGISTER_V 0x1 +#define XTS_AES_CRYPT_DPA_SELECT_REGISTER_S 4 +/* XTS_AES_CRYPT_CALC_D_DPA_EN : R/W ;bitpos:[3] ;default: 1'b1 ; */ +/*description: Only available when SPI_CRYPT_SECURITY_LEVEL is not 0. 1: Enable DPA in the calc +ulation that using key 1 or key 2. 0: Enable DPA only in the calculation that us +ing key 1..*/ +#define XTS_AES_CRYPT_CALC_D_DPA_EN (BIT(3)) +#define XTS_AES_CRYPT_CALC_D_DPA_EN_M (BIT(3)) +#define XTS_AES_CRYPT_CALC_D_DPA_EN_V 0x1 +#define XTS_AES_CRYPT_CALC_D_DPA_EN_S 3 +/* XTS_AES_CRYPT_SECURITY_LEVEL : R/W ;bitpos:[2:0] ;default: 3'd7 ; */ +/*description: Set the security level of spi mem cryption. 0: Shut off cryption DPA function. 1- +7: The bigger the number is, the more secure the cryption is. (Note that the per +formance of cryption will decrease together with this number increasing).*/ +#define XTS_AES_CRYPT_SECURITY_LEVEL 0x00000007 +#define XTS_AES_CRYPT_SECURITY_LEVEL_M ((XTS_AES_CRYPT_SECURITY_LEVEL_V)<<(XTS_AES_CRYPT_SECURITY_LEVEL_S)) +#define XTS_AES_CRYPT_SECURITY_LEVEL_V 0x7 +#define XTS_AES_CRYPT_SECURITY_LEVEL_S 0 + +#ifdef __cplusplus +} +#endif From d798f6f1a77aa0385d89cc19be9c57dd90c0ea2c Mon Sep 17 00:00:00 2001 From: gaoxu Date: Thu, 12 Dec 2024 18:26:35 +0800 Subject: [PATCH 070/118] feat(esp32h21): update pmu reg and struct files (stage 2-3) --- .../soc/esp32h21/register/soc/pmu_reg.h | 1114 ++++++++++++++--- .../soc/esp32h21/register/soc/pmu_struct.h | 995 +++++++++------ 2 files changed, 1552 insertions(+), 557 deletions(-) diff --git a/components/soc/esp32h21/register/soc/pmu_reg.h b/components/soc/esp32h21/register/soc/pmu_reg.h index 4394e9e1249..7f6a61fda8f 100644 --- a/components/soc/esp32h21/register/soc/pmu_reg.h +++ b/components/soc/esp32h21/register/soc/pmu_reg.h @@ -15,13 +15,13 @@ extern "C" { * need_des */ #define PMU_HP_ACTIVE_DIG_POWER_REG (DR_REG_PMU_BASE + 0x0) -/** PMU_HP_ACTIVE_VDD_SPI_PD_EN : R/W; bitpos: [21]; default: 0; +/** PMU_HP_ACTIVE_VDD_FLASH_MODE : R/W; bitpos: [21:18]; default: 0; * need_des */ -#define PMU_HP_ACTIVE_VDD_SPI_PD_EN (BIT(21)) -#define PMU_HP_ACTIVE_VDD_SPI_PD_EN_M (PMU_HP_ACTIVE_VDD_SPI_PD_EN_V << PMU_HP_ACTIVE_VDD_SPI_PD_EN_S) -#define PMU_HP_ACTIVE_VDD_SPI_PD_EN_V 0x00000001U -#define PMU_HP_ACTIVE_VDD_SPI_PD_EN_S 21 +#define PMU_HP_ACTIVE_VDD_FLASH_MODE 0x0000000FU +#define PMU_HP_ACTIVE_VDD_FLASH_MODE_M (PMU_HP_ACTIVE_VDD_FLASH_MODE_V << PMU_HP_ACTIVE_VDD_FLASH_MODE_S) +#define PMU_HP_ACTIVE_VDD_FLASH_MODE_V 0x0000000FU +#define PMU_HP_ACTIVE_VDD_FLASH_MODE_S 18 /** PMU_HP_ACTIVE_HP_MEM_DSLP : R/W; bitpos: [22]; default: 0; * need_des */ @@ -43,6 +43,13 @@ extern "C" { #define PMU_HP_ACTIVE_PD_HP_WIFI_PD_EN_M (PMU_HP_ACTIVE_PD_HP_WIFI_PD_EN_V << PMU_HP_ACTIVE_PD_HP_WIFI_PD_EN_S) #define PMU_HP_ACTIVE_PD_HP_WIFI_PD_EN_V 0x00000001U #define PMU_HP_ACTIVE_PD_HP_WIFI_PD_EN_S 27 +/** PMU_HP_ACTIVE_PD_HP_PERI_PD_EN : R/W; bitpos: [28]; default: 0; + * need_des + */ +#define PMU_HP_ACTIVE_PD_HP_PERI_PD_EN (BIT(28)) +#define PMU_HP_ACTIVE_PD_HP_PERI_PD_EN_M (PMU_HP_ACTIVE_PD_HP_PERI_PD_EN_V << PMU_HP_ACTIVE_PD_HP_PERI_PD_EN_S) +#define PMU_HP_ACTIVE_PD_HP_PERI_PD_EN_V 0x00000001U +#define PMU_HP_ACTIVE_PD_HP_PERI_PD_EN_S 28 /** PMU_HP_ACTIVE_PD_HP_CPU_PD_EN : R/W; bitpos: [29]; default: 0; * need_des */ @@ -192,6 +199,48 @@ extern "C" { * need_des */ #define PMU_HP_ACTIVE_BIAS_REG (DR_REG_PMU_BASE + 0x18) +/** PMU_HP_ACTIVE_DCDC_CCM_ENB : R/W; bitpos: [9]; default: 1; + * need_des + */ +#define PMU_HP_ACTIVE_DCDC_CCM_ENB (BIT(9)) +#define PMU_HP_ACTIVE_DCDC_CCM_ENB_M (PMU_HP_ACTIVE_DCDC_CCM_ENB_V << PMU_HP_ACTIVE_DCDC_CCM_ENB_S) +#define PMU_HP_ACTIVE_DCDC_CCM_ENB_V 0x00000001U +#define PMU_HP_ACTIVE_DCDC_CCM_ENB_S 9 +/** PMU_HP_ACTIVE_DCDC_CLEAR_RDY : R/W; bitpos: [10]; default: 0; + * need_des + */ +#define PMU_HP_ACTIVE_DCDC_CLEAR_RDY (BIT(10)) +#define PMU_HP_ACTIVE_DCDC_CLEAR_RDY_M (PMU_HP_ACTIVE_DCDC_CLEAR_RDY_V << PMU_HP_ACTIVE_DCDC_CLEAR_RDY_S) +#define PMU_HP_ACTIVE_DCDC_CLEAR_RDY_V 0x00000001U +#define PMU_HP_ACTIVE_DCDC_CLEAR_RDY_S 10 +/** PMU_HP_ACTIVE_DIG_PMU_DPCUR_BIAS : R/W; bitpos: [12:11]; default: 3; + * need_des + */ +#define PMU_HP_ACTIVE_DIG_PMU_DPCUR_BIAS 0x00000003U +#define PMU_HP_ACTIVE_DIG_PMU_DPCUR_BIAS_M (PMU_HP_ACTIVE_DIG_PMU_DPCUR_BIAS_V << PMU_HP_ACTIVE_DIG_PMU_DPCUR_BIAS_S) +#define PMU_HP_ACTIVE_DIG_PMU_DPCUR_BIAS_V 0x00000003U +#define PMU_HP_ACTIVE_DIG_PMU_DPCUR_BIAS_S 11 +/** PMU_HP_ACTIVE_DIG_PMU_DSFMOS : R/W; bitpos: [16:13]; default: 6; + * need_des + */ +#define PMU_HP_ACTIVE_DIG_PMU_DSFMOS 0x0000000FU +#define PMU_HP_ACTIVE_DIG_PMU_DSFMOS_M (PMU_HP_ACTIVE_DIG_PMU_DSFMOS_V << PMU_HP_ACTIVE_DIG_PMU_DSFMOS_S) +#define PMU_HP_ACTIVE_DIG_PMU_DSFMOS_V 0x0000000FU +#define PMU_HP_ACTIVE_DIG_PMU_DSFMOS_S 13 +/** PMU_HP_ACTIVE_DCM_VSET : R/W; bitpos: [21:17]; default: 23; + * need_des + */ +#define PMU_HP_ACTIVE_DCM_VSET 0x0000001FU +#define PMU_HP_ACTIVE_DCM_VSET_M (PMU_HP_ACTIVE_DCM_VSET_V << PMU_HP_ACTIVE_DCM_VSET_S) +#define PMU_HP_ACTIVE_DCM_VSET_V 0x0000001FU +#define PMU_HP_ACTIVE_DCM_VSET_S 17 +/** PMU_HP_ACTIVE_DCM_MODE : R/W; bitpos: [23:22]; default: 0; + * need_des + */ +#define PMU_HP_ACTIVE_DCM_MODE 0x00000003U +#define PMU_HP_ACTIVE_DCM_MODE_M (PMU_HP_ACTIVE_DCM_MODE_V << PMU_HP_ACTIVE_DCM_MODE_S) +#define PMU_HP_ACTIVE_DCM_MODE_V 0x00000003U +#define PMU_HP_ACTIVE_DCM_MODE_S 22 /** PMU_HP_ACTIVE_XPD_TRX : R/W; bitpos: [24]; default: 1; * need_des */ @@ -206,6 +255,13 @@ extern "C" { #define PMU_HP_ACTIVE_XPD_BIAS_M (PMU_HP_ACTIVE_XPD_BIAS_V << PMU_HP_ACTIVE_XPD_BIAS_S) #define PMU_HP_ACTIVE_XPD_BIAS_V 0x00000001U #define PMU_HP_ACTIVE_XPD_BIAS_S 25 +/** PMU_HP_ACTIVE_DISCNNT_DIG_RTC : R/W; bitpos: [29]; default: 0; + * need_des + */ +#define PMU_HP_ACTIVE_DISCNNT_DIG_RTC (BIT(29)) +#define PMU_HP_ACTIVE_DISCNNT_DIG_RTC_M (PMU_HP_ACTIVE_DISCNNT_DIG_RTC_V << PMU_HP_ACTIVE_DISCNNT_DIG_RTC_S) +#define PMU_HP_ACTIVE_DISCNNT_DIG_RTC_V 0x00000001U +#define PMU_HP_ACTIVE_DISCNNT_DIG_RTC_S 29 /** PMU_HP_ACTIVE_PD_CUR : R/W; bitpos: [30]; default: 0; * need_des */ @@ -239,27 +295,6 @@ extern "C" { #define PMU_HP_MODEM2ACTIVE_BACKUP_MODEM_CLK_CODE_M (PMU_HP_MODEM2ACTIVE_BACKUP_MODEM_CLK_CODE_V << PMU_HP_MODEM2ACTIVE_BACKUP_MODEM_CLK_CODE_S) #define PMU_HP_MODEM2ACTIVE_BACKUP_MODEM_CLK_CODE_V 0x00000003U #define PMU_HP_MODEM2ACTIVE_BACKUP_MODEM_CLK_CODE_S 6 -/** PMU_HP_ACTIVE_RETENTION_MODE : R/W; bitpos: [10]; default: 0; - * need_des - */ -#define PMU_HP_ACTIVE_RETENTION_MODE (BIT(10)) -#define PMU_HP_ACTIVE_RETENTION_MODE_M (PMU_HP_ACTIVE_RETENTION_MODE_V << PMU_HP_ACTIVE_RETENTION_MODE_S) -#define PMU_HP_ACTIVE_RETENTION_MODE_V 0x00000001U -#define PMU_HP_ACTIVE_RETENTION_MODE_S 10 -/** PMU_HP_SLEEP2ACTIVE_RETENTION_EN : R/W; bitpos: [11]; default: 0; - * need_des - */ -#define PMU_HP_SLEEP2ACTIVE_RETENTION_EN (BIT(11)) -#define PMU_HP_SLEEP2ACTIVE_RETENTION_EN_M (PMU_HP_SLEEP2ACTIVE_RETENTION_EN_V << PMU_HP_SLEEP2ACTIVE_RETENTION_EN_S) -#define PMU_HP_SLEEP2ACTIVE_RETENTION_EN_V 0x00000001U -#define PMU_HP_SLEEP2ACTIVE_RETENTION_EN_S 11 -/** PMU_HP_MODEM2ACTIVE_RETENTION_EN : R/W; bitpos: [12]; default: 0; - * need_des - */ -#define PMU_HP_MODEM2ACTIVE_RETENTION_EN (BIT(12)) -#define PMU_HP_MODEM2ACTIVE_RETENTION_EN_M (PMU_HP_MODEM2ACTIVE_RETENTION_EN_V << PMU_HP_MODEM2ACTIVE_RETENTION_EN_S) -#define PMU_HP_MODEM2ACTIVE_RETENTION_EN_V 0x00000001U -#define PMU_HP_MODEM2ACTIVE_RETENTION_EN_S 12 /** PMU_HP_SLEEP2ACTIVE_BACKUP_CLK_SEL : R/W; bitpos: [15:14]; default: 0; * need_des */ @@ -274,19 +309,19 @@ extern "C" { #define PMU_HP_MODEM2ACTIVE_BACKUP_CLK_SEL_M (PMU_HP_MODEM2ACTIVE_BACKUP_CLK_SEL_V << PMU_HP_MODEM2ACTIVE_BACKUP_CLK_SEL_S) #define PMU_HP_MODEM2ACTIVE_BACKUP_CLK_SEL_V 0x00000003U #define PMU_HP_MODEM2ACTIVE_BACKUP_CLK_SEL_S 16 -/** PMU_HP_SLEEP2ACTIVE_BACKUP_MODE : R/W; bitpos: [22:20]; default: 0; +/** PMU_HP_SLEEP2ACTIVE_BACKUP_MODE : R/W; bitpos: [22:18]; default: 0; * need_des */ -#define PMU_HP_SLEEP2ACTIVE_BACKUP_MODE 0x00000007U +#define PMU_HP_SLEEP2ACTIVE_BACKUP_MODE 0x0000001FU #define PMU_HP_SLEEP2ACTIVE_BACKUP_MODE_M (PMU_HP_SLEEP2ACTIVE_BACKUP_MODE_V << PMU_HP_SLEEP2ACTIVE_BACKUP_MODE_S) -#define PMU_HP_SLEEP2ACTIVE_BACKUP_MODE_V 0x00000007U -#define PMU_HP_SLEEP2ACTIVE_BACKUP_MODE_S 20 -/** PMU_HP_MODEM2ACTIVE_BACKUP_MODE : R/W; bitpos: [25:23]; default: 0; +#define PMU_HP_SLEEP2ACTIVE_BACKUP_MODE_V 0x0000001FU +#define PMU_HP_SLEEP2ACTIVE_BACKUP_MODE_S 18 +/** PMU_HP_MODEM2ACTIVE_BACKUP_MODE : R/W; bitpos: [27:23]; default: 0; * need_des */ -#define PMU_HP_MODEM2ACTIVE_BACKUP_MODE 0x00000007U +#define PMU_HP_MODEM2ACTIVE_BACKUP_MODE 0x0000001FU #define PMU_HP_MODEM2ACTIVE_BACKUP_MODE_M (PMU_HP_MODEM2ACTIVE_BACKUP_MODE_V << PMU_HP_MODEM2ACTIVE_BACKUP_MODE_S) -#define PMU_HP_MODEM2ACTIVE_BACKUP_MODE_V 0x00000007U +#define PMU_HP_MODEM2ACTIVE_BACKUP_MODE_V 0x0000001FU #define PMU_HP_MODEM2ACTIVE_BACKUP_MODE_S 23 /** PMU_HP_SLEEP2ACTIVE_BACKUP_EN : R/W; bitpos: [29]; default: 0; * need_des @@ -366,14 +401,14 @@ extern "C" { #define PMU_HP_ACTIVE_HP_POWER_DET_BYPASS_M (PMU_HP_ACTIVE_HP_POWER_DET_BYPASS_V << PMU_HP_ACTIVE_HP_POWER_DET_BYPASS_S) #define PMU_HP_ACTIVE_HP_POWER_DET_BYPASS_V 0x00000001U #define PMU_HP_ACTIVE_HP_POWER_DET_BYPASS_S 0 -/** PMU_LP_DBIAS_VOL : RO; bitpos: [8:4]; default: 17; +/** PMU_LP_DBIAS_VOL : RO; bitpos: [8:4]; default: 24; * need_des */ #define PMU_LP_DBIAS_VOL 0x0000001FU #define PMU_LP_DBIAS_VOL_M (PMU_LP_DBIAS_VOL_V << PMU_LP_DBIAS_VOL_S) #define PMU_LP_DBIAS_VOL_V 0x0000001FU #define PMU_LP_DBIAS_VOL_S 4 -/** PMU_HP_DBIAS_VOL : RO; bitpos: [13:9]; default: 16; +/** PMU_HP_DBIAS_VOL : RO; bitpos: [13:9]; default: 24; * need_des */ #define PMU_HP_DBIAS_VOL 0x0000001FU @@ -453,6 +488,13 @@ extern "C" { * need_des */ #define PMU_HP_ACTIVE_XTAL_REG (DR_REG_PMU_BASE + 0x30) +/** PMU_HP_ACTIVE_XPD_XTALX2 : R/W; bitpos: [30]; default: 1; + * need_des + */ +#define PMU_HP_ACTIVE_XPD_XTALX2 (BIT(30)) +#define PMU_HP_ACTIVE_XPD_XTALX2_M (PMU_HP_ACTIVE_XPD_XTALX2_V << PMU_HP_ACTIVE_XPD_XTALX2_S) +#define PMU_HP_ACTIVE_XPD_XTALX2_V 0x00000001U +#define PMU_HP_ACTIVE_XPD_XTALX2_S 30 /** PMU_HP_ACTIVE_XPD_XTAL : R/W; bitpos: [31]; default: 1; * need_des */ @@ -465,13 +507,13 @@ extern "C" { * need_des */ #define PMU_HP_MODEM_DIG_POWER_REG (DR_REG_PMU_BASE + 0x34) -/** PMU_HP_MODEM_VDD_SPI_PD_EN : R/W; bitpos: [21]; default: 0; +/** PMU_HP_MODEM_VDD_FLASH_MODE : R/W; bitpos: [21:18]; default: 0; * need_des */ -#define PMU_HP_MODEM_VDD_SPI_PD_EN (BIT(21)) -#define PMU_HP_MODEM_VDD_SPI_PD_EN_M (PMU_HP_MODEM_VDD_SPI_PD_EN_V << PMU_HP_MODEM_VDD_SPI_PD_EN_S) -#define PMU_HP_MODEM_VDD_SPI_PD_EN_V 0x00000001U -#define PMU_HP_MODEM_VDD_SPI_PD_EN_S 21 +#define PMU_HP_MODEM_VDD_FLASH_MODE 0x0000000FU +#define PMU_HP_MODEM_VDD_FLASH_MODE_M (PMU_HP_MODEM_VDD_FLASH_MODE_V << PMU_HP_MODEM_VDD_FLASH_MODE_S) +#define PMU_HP_MODEM_VDD_FLASH_MODE_V 0x0000000FU +#define PMU_HP_MODEM_VDD_FLASH_MODE_S 18 /** PMU_HP_MODEM_HP_MEM_DSLP : R/W; bitpos: [22]; default: 0; * need_des */ @@ -493,6 +535,13 @@ extern "C" { #define PMU_HP_MODEM_PD_HP_WIFI_PD_EN_M (PMU_HP_MODEM_PD_HP_WIFI_PD_EN_V << PMU_HP_MODEM_PD_HP_WIFI_PD_EN_S) #define PMU_HP_MODEM_PD_HP_WIFI_PD_EN_V 0x00000001U #define PMU_HP_MODEM_PD_HP_WIFI_PD_EN_S 27 +/** PMU_HP_MODEM_PD_HP_PERI_PD_EN : R/W; bitpos: [28]; default: 0; + * need_des + */ +#define PMU_HP_MODEM_PD_HP_PERI_PD_EN (BIT(28)) +#define PMU_HP_MODEM_PD_HP_PERI_PD_EN_M (PMU_HP_MODEM_PD_HP_PERI_PD_EN_V << PMU_HP_MODEM_PD_HP_PERI_PD_EN_S) +#define PMU_HP_MODEM_PD_HP_PERI_PD_EN_V 0x00000001U +#define PMU_HP_MODEM_PD_HP_PERI_PD_EN_S 28 /** PMU_HP_MODEM_PD_HP_CPU_PD_EN : R/W; bitpos: [29]; default: 0; * need_des */ @@ -642,6 +691,48 @@ extern "C" { * need_des */ #define PMU_HP_MODEM_BIAS_REG (DR_REG_PMU_BASE + 0x4c) +/** PMU_HP_MODEM_DCDC_CCM_ENB : R/W; bitpos: [9]; default: 1; + * need_des + */ +#define PMU_HP_MODEM_DCDC_CCM_ENB (BIT(9)) +#define PMU_HP_MODEM_DCDC_CCM_ENB_M (PMU_HP_MODEM_DCDC_CCM_ENB_V << PMU_HP_MODEM_DCDC_CCM_ENB_S) +#define PMU_HP_MODEM_DCDC_CCM_ENB_V 0x00000001U +#define PMU_HP_MODEM_DCDC_CCM_ENB_S 9 +/** PMU_HP_MODEM_DCDC_CLEAR_RDY : R/W; bitpos: [10]; default: 0; + * need_des + */ +#define PMU_HP_MODEM_DCDC_CLEAR_RDY (BIT(10)) +#define PMU_HP_MODEM_DCDC_CLEAR_RDY_M (PMU_HP_MODEM_DCDC_CLEAR_RDY_V << PMU_HP_MODEM_DCDC_CLEAR_RDY_S) +#define PMU_HP_MODEM_DCDC_CLEAR_RDY_V 0x00000001U +#define PMU_HP_MODEM_DCDC_CLEAR_RDY_S 10 +/** PMU_HP_MODEM_DIG_PMU_DPCUR_BIAS : R/W; bitpos: [12:11]; default: 1; + * need_des + */ +#define PMU_HP_MODEM_DIG_PMU_DPCUR_BIAS 0x00000003U +#define PMU_HP_MODEM_DIG_PMU_DPCUR_BIAS_M (PMU_HP_MODEM_DIG_PMU_DPCUR_BIAS_V << PMU_HP_MODEM_DIG_PMU_DPCUR_BIAS_S) +#define PMU_HP_MODEM_DIG_PMU_DPCUR_BIAS_V 0x00000003U +#define PMU_HP_MODEM_DIG_PMU_DPCUR_BIAS_S 11 +/** PMU_HP_MODEM_DIG_PMU_DSFMOS : R/W; bitpos: [16:13]; default: 4; + * need_des + */ +#define PMU_HP_MODEM_DIG_PMU_DSFMOS 0x0000000FU +#define PMU_HP_MODEM_DIG_PMU_DSFMOS_M (PMU_HP_MODEM_DIG_PMU_DSFMOS_V << PMU_HP_MODEM_DIG_PMU_DSFMOS_S) +#define PMU_HP_MODEM_DIG_PMU_DSFMOS_V 0x0000000FU +#define PMU_HP_MODEM_DIG_PMU_DSFMOS_S 13 +/** PMU_HP_MODEM_DCM_VSET : R/W; bitpos: [21:17]; default: 23; + * need_des + */ +#define PMU_HP_MODEM_DCM_VSET 0x0000001FU +#define PMU_HP_MODEM_DCM_VSET_M (PMU_HP_MODEM_DCM_VSET_V << PMU_HP_MODEM_DCM_VSET_S) +#define PMU_HP_MODEM_DCM_VSET_V 0x0000001FU +#define PMU_HP_MODEM_DCM_VSET_S 17 +/** PMU_HP_MODEM_DCM_MODE : R/W; bitpos: [23:22]; default: 0; + * need_des + */ +#define PMU_HP_MODEM_DCM_MODE 0x00000003U +#define PMU_HP_MODEM_DCM_MODE_M (PMU_HP_MODEM_DCM_MODE_V << PMU_HP_MODEM_DCM_MODE_S) +#define PMU_HP_MODEM_DCM_MODE_V 0x00000003U +#define PMU_HP_MODEM_DCM_MODE_S 22 /** PMU_HP_MODEM_XPD_TRX : R/W; bitpos: [24]; default: 1; * need_des */ @@ -656,6 +747,13 @@ extern "C" { #define PMU_HP_MODEM_XPD_BIAS_M (PMU_HP_MODEM_XPD_BIAS_V << PMU_HP_MODEM_XPD_BIAS_S) #define PMU_HP_MODEM_XPD_BIAS_V 0x00000001U #define PMU_HP_MODEM_XPD_BIAS_S 25 +/** PMU_HP_MODEM_DISCNNT_DIG_RTC : R/W; bitpos: [29]; default: 0; + * need_des + */ +#define PMU_HP_MODEM_DISCNNT_DIG_RTC (BIT(29)) +#define PMU_HP_MODEM_DISCNNT_DIG_RTC_M (PMU_HP_MODEM_DISCNNT_DIG_RTC_V << PMU_HP_MODEM_DISCNNT_DIG_RTC_S) +#define PMU_HP_MODEM_DISCNNT_DIG_RTC_V 0x00000001U +#define PMU_HP_MODEM_DISCNNT_DIG_RTC_S 29 /** PMU_HP_MODEM_PD_CUR : R/W; bitpos: [30]; default: 0; * need_des */ @@ -682,20 +780,6 @@ extern "C" { #define PMU_HP_SLEEP2MODEM_BACKUP_MODEM_CLK_CODE_M (PMU_HP_SLEEP2MODEM_BACKUP_MODEM_CLK_CODE_V << PMU_HP_SLEEP2MODEM_BACKUP_MODEM_CLK_CODE_S) #define PMU_HP_SLEEP2MODEM_BACKUP_MODEM_CLK_CODE_V 0x00000003U #define PMU_HP_SLEEP2MODEM_BACKUP_MODEM_CLK_CODE_S 4 -/** PMU_HP_MODEM_RETENTION_MODE : R/W; bitpos: [10]; default: 0; - * need_des - */ -#define PMU_HP_MODEM_RETENTION_MODE (BIT(10)) -#define PMU_HP_MODEM_RETENTION_MODE_M (PMU_HP_MODEM_RETENTION_MODE_V << PMU_HP_MODEM_RETENTION_MODE_S) -#define PMU_HP_MODEM_RETENTION_MODE_V 0x00000001U -#define PMU_HP_MODEM_RETENTION_MODE_S 10 -/** PMU_HP_SLEEP2MODEM_RETENTION_EN : R/W; bitpos: [11]; default: 0; - * need_des - */ -#define PMU_HP_SLEEP2MODEM_RETENTION_EN (BIT(11)) -#define PMU_HP_SLEEP2MODEM_RETENTION_EN_M (PMU_HP_SLEEP2MODEM_RETENTION_EN_V << PMU_HP_SLEEP2MODEM_RETENTION_EN_S) -#define PMU_HP_SLEEP2MODEM_RETENTION_EN_V 0x00000001U -#define PMU_HP_SLEEP2MODEM_RETENTION_EN_S 11 /** PMU_HP_SLEEP2MODEM_BACKUP_CLK_SEL : R/W; bitpos: [15:14]; default: 0; * need_des */ @@ -703,12 +787,12 @@ extern "C" { #define PMU_HP_SLEEP2MODEM_BACKUP_CLK_SEL_M (PMU_HP_SLEEP2MODEM_BACKUP_CLK_SEL_V << PMU_HP_SLEEP2MODEM_BACKUP_CLK_SEL_S) #define PMU_HP_SLEEP2MODEM_BACKUP_CLK_SEL_V 0x00000003U #define PMU_HP_SLEEP2MODEM_BACKUP_CLK_SEL_S 14 -/** PMU_HP_SLEEP2MODEM_BACKUP_MODE : R/W; bitpos: [22:20]; default: 0; +/** PMU_HP_SLEEP2MODEM_BACKUP_MODE : R/W; bitpos: [24:20]; default: 0; * need_des */ -#define PMU_HP_SLEEP2MODEM_BACKUP_MODE 0x00000007U +#define PMU_HP_SLEEP2MODEM_BACKUP_MODE 0x0000001FU #define PMU_HP_SLEEP2MODEM_BACKUP_MODE_M (PMU_HP_SLEEP2MODEM_BACKUP_MODE_V << PMU_HP_SLEEP2MODEM_BACKUP_MODE_S) -#define PMU_HP_SLEEP2MODEM_BACKUP_MODE_V 0x00000007U +#define PMU_HP_SLEEP2MODEM_BACKUP_MODE_V 0x0000001FU #define PMU_HP_SLEEP2MODEM_BACKUP_MODE_S 20 /** PMU_HP_SLEEP2MODEM_BACKUP_EN : R/W; bitpos: [29]; default: 0; * need_des @@ -840,6 +924,13 @@ extern "C" { * need_des */ #define PMU_HP_MODEM_XTAL_REG (DR_REG_PMU_BASE + 0x64) +/** PMU_HP_MODEM_XPD_XTALX2 : R/W; bitpos: [30]; default: 1; + * need_des + */ +#define PMU_HP_MODEM_XPD_XTALX2 (BIT(30)) +#define PMU_HP_MODEM_XPD_XTALX2_M (PMU_HP_MODEM_XPD_XTALX2_V << PMU_HP_MODEM_XPD_XTALX2_S) +#define PMU_HP_MODEM_XPD_XTALX2_V 0x00000001U +#define PMU_HP_MODEM_XPD_XTALX2_S 30 /** PMU_HP_MODEM_XPD_XTAL : R/W; bitpos: [31]; default: 1; * need_des */ @@ -852,13 +943,13 @@ extern "C" { * need_des */ #define PMU_HP_SLEEP_DIG_POWER_REG (DR_REG_PMU_BASE + 0x68) -/** PMU_HP_SLEEP_VDD_SPI_PD_EN : R/W; bitpos: [21]; default: 0; +/** PMU_HP_SLEEP_VDD_FLASH_MODE : R/W; bitpos: [21:18]; default: 0; * need_des */ -#define PMU_HP_SLEEP_VDD_SPI_PD_EN (BIT(21)) -#define PMU_HP_SLEEP_VDD_SPI_PD_EN_M (PMU_HP_SLEEP_VDD_SPI_PD_EN_V << PMU_HP_SLEEP_VDD_SPI_PD_EN_S) -#define PMU_HP_SLEEP_VDD_SPI_PD_EN_V 0x00000001U -#define PMU_HP_SLEEP_VDD_SPI_PD_EN_S 21 +#define PMU_HP_SLEEP_VDD_FLASH_MODE 0x0000000FU +#define PMU_HP_SLEEP_VDD_FLASH_MODE_M (PMU_HP_SLEEP_VDD_FLASH_MODE_V << PMU_HP_SLEEP_VDD_FLASH_MODE_S) +#define PMU_HP_SLEEP_VDD_FLASH_MODE_V 0x0000000FU +#define PMU_HP_SLEEP_VDD_FLASH_MODE_S 18 /** PMU_HP_SLEEP_HP_MEM_DSLP : R/W; bitpos: [22]; default: 0; * need_des */ @@ -880,6 +971,13 @@ extern "C" { #define PMU_HP_SLEEP_PD_HP_WIFI_PD_EN_M (PMU_HP_SLEEP_PD_HP_WIFI_PD_EN_V << PMU_HP_SLEEP_PD_HP_WIFI_PD_EN_S) #define PMU_HP_SLEEP_PD_HP_WIFI_PD_EN_V 0x00000001U #define PMU_HP_SLEEP_PD_HP_WIFI_PD_EN_S 27 +/** PMU_HP_SLEEP_PD_HP_PERI_PD_EN : R/W; bitpos: [28]; default: 0; + * need_des + */ +#define PMU_HP_SLEEP_PD_HP_PERI_PD_EN (BIT(28)) +#define PMU_HP_SLEEP_PD_HP_PERI_PD_EN_M (PMU_HP_SLEEP_PD_HP_PERI_PD_EN_V << PMU_HP_SLEEP_PD_HP_PERI_PD_EN_S) +#define PMU_HP_SLEEP_PD_HP_PERI_PD_EN_V 0x00000001U +#define PMU_HP_SLEEP_PD_HP_PERI_PD_EN_S 28 /** PMU_HP_SLEEP_PD_HP_CPU_PD_EN : R/W; bitpos: [29]; default: 0; * need_des */ @@ -1029,6 +1127,48 @@ extern "C" { * need_des */ #define PMU_HP_SLEEP_BIAS_REG (DR_REG_PMU_BASE + 0x80) +/** PMU_HP_SLEEP_DCDC_CCM_ENB : R/W; bitpos: [9]; default: 1; + * need_des + */ +#define PMU_HP_SLEEP_DCDC_CCM_ENB (BIT(9)) +#define PMU_HP_SLEEP_DCDC_CCM_ENB_M (PMU_HP_SLEEP_DCDC_CCM_ENB_V << PMU_HP_SLEEP_DCDC_CCM_ENB_S) +#define PMU_HP_SLEEP_DCDC_CCM_ENB_V 0x00000001U +#define PMU_HP_SLEEP_DCDC_CCM_ENB_S 9 +/** PMU_HP_SLEEP_DCDC_CLEAR_RDY : R/W; bitpos: [10]; default: 0; + * need_des + */ +#define PMU_HP_SLEEP_DCDC_CLEAR_RDY (BIT(10)) +#define PMU_HP_SLEEP_DCDC_CLEAR_RDY_M (PMU_HP_SLEEP_DCDC_CLEAR_RDY_V << PMU_HP_SLEEP_DCDC_CLEAR_RDY_S) +#define PMU_HP_SLEEP_DCDC_CLEAR_RDY_V 0x00000001U +#define PMU_HP_SLEEP_DCDC_CLEAR_RDY_S 10 +/** PMU_HP_SLEEP_DIG_PMU_DPCUR_BIAS : R/W; bitpos: [12:11]; default: 1; + * need_des + */ +#define PMU_HP_SLEEP_DIG_PMU_DPCUR_BIAS 0x00000003U +#define PMU_HP_SLEEP_DIG_PMU_DPCUR_BIAS_M (PMU_HP_SLEEP_DIG_PMU_DPCUR_BIAS_V << PMU_HP_SLEEP_DIG_PMU_DPCUR_BIAS_S) +#define PMU_HP_SLEEP_DIG_PMU_DPCUR_BIAS_V 0x00000003U +#define PMU_HP_SLEEP_DIG_PMU_DPCUR_BIAS_S 11 +/** PMU_HP_SLEEP_DIG_PMU_DSFMOS : R/W; bitpos: [16:13]; default: 4; + * need_des + */ +#define PMU_HP_SLEEP_DIG_PMU_DSFMOS 0x0000000FU +#define PMU_HP_SLEEP_DIG_PMU_DSFMOS_M (PMU_HP_SLEEP_DIG_PMU_DSFMOS_V << PMU_HP_SLEEP_DIG_PMU_DSFMOS_S) +#define PMU_HP_SLEEP_DIG_PMU_DSFMOS_V 0x0000000FU +#define PMU_HP_SLEEP_DIG_PMU_DSFMOS_S 13 +/** PMU_HP_SLEEP_DCM_VSET : R/W; bitpos: [21:17]; default: 23; + * need_des + */ +#define PMU_HP_SLEEP_DCM_VSET 0x0000001FU +#define PMU_HP_SLEEP_DCM_VSET_M (PMU_HP_SLEEP_DCM_VSET_V << PMU_HP_SLEEP_DCM_VSET_S) +#define PMU_HP_SLEEP_DCM_VSET_V 0x0000001FU +#define PMU_HP_SLEEP_DCM_VSET_S 17 +/** PMU_HP_SLEEP_DCM_MODE : R/W; bitpos: [23:22]; default: 0; + * need_des + */ +#define PMU_HP_SLEEP_DCM_MODE 0x00000003U +#define PMU_HP_SLEEP_DCM_MODE_M (PMU_HP_SLEEP_DCM_MODE_V << PMU_HP_SLEEP_DCM_MODE_S) +#define PMU_HP_SLEEP_DCM_MODE_V 0x00000003U +#define PMU_HP_SLEEP_DCM_MODE_S 22 /** PMU_HP_SLEEP_XPD_TRX : R/W; bitpos: [24]; default: 1; * need_des */ @@ -1043,6 +1183,13 @@ extern "C" { #define PMU_HP_SLEEP_XPD_BIAS_M (PMU_HP_SLEEP_XPD_BIAS_V << PMU_HP_SLEEP_XPD_BIAS_S) #define PMU_HP_SLEEP_XPD_BIAS_V 0x00000001U #define PMU_HP_SLEEP_XPD_BIAS_S 25 +/** PMU_HP_SLEEP_DISCNNT_DIG_RTC : R/W; bitpos: [29]; default: 0; + * need_des + */ +#define PMU_HP_SLEEP_DISCNNT_DIG_RTC (BIT(29)) +#define PMU_HP_SLEEP_DISCNNT_DIG_RTC_M (PMU_HP_SLEEP_DISCNNT_DIG_RTC_V << PMU_HP_SLEEP_DISCNNT_DIG_RTC_S) +#define PMU_HP_SLEEP_DISCNNT_DIG_RTC_V 0x00000001U +#define PMU_HP_SLEEP_DISCNNT_DIG_RTC_S 29 /** PMU_HP_SLEEP_PD_CUR : R/W; bitpos: [30]; default: 0; * need_des */ @@ -1076,27 +1223,6 @@ extern "C" { #define PMU_HP_ACTIVE2SLEEP_BACKUP_MODEM_CLK_CODE_M (PMU_HP_ACTIVE2SLEEP_BACKUP_MODEM_CLK_CODE_V << PMU_HP_ACTIVE2SLEEP_BACKUP_MODEM_CLK_CODE_S) #define PMU_HP_ACTIVE2SLEEP_BACKUP_MODEM_CLK_CODE_V 0x00000003U #define PMU_HP_ACTIVE2SLEEP_BACKUP_MODEM_CLK_CODE_S 8 -/** PMU_HP_SLEEP_RETENTION_MODE : R/W; bitpos: [10]; default: 0; - * need_des - */ -#define PMU_HP_SLEEP_RETENTION_MODE (BIT(10)) -#define PMU_HP_SLEEP_RETENTION_MODE_M (PMU_HP_SLEEP_RETENTION_MODE_V << PMU_HP_SLEEP_RETENTION_MODE_S) -#define PMU_HP_SLEEP_RETENTION_MODE_V 0x00000001U -#define PMU_HP_SLEEP_RETENTION_MODE_S 10 -/** PMU_HP_MODEM2SLEEP_RETENTION_EN : R/W; bitpos: [12]; default: 0; - * need_des - */ -#define PMU_HP_MODEM2SLEEP_RETENTION_EN (BIT(12)) -#define PMU_HP_MODEM2SLEEP_RETENTION_EN_M (PMU_HP_MODEM2SLEEP_RETENTION_EN_V << PMU_HP_MODEM2SLEEP_RETENTION_EN_S) -#define PMU_HP_MODEM2SLEEP_RETENTION_EN_V 0x00000001U -#define PMU_HP_MODEM2SLEEP_RETENTION_EN_S 12 -/** PMU_HP_ACTIVE2SLEEP_RETENTION_EN : R/W; bitpos: [13]; default: 0; - * need_des - */ -#define PMU_HP_ACTIVE2SLEEP_RETENTION_EN (BIT(13)) -#define PMU_HP_ACTIVE2SLEEP_RETENTION_EN_M (PMU_HP_ACTIVE2SLEEP_RETENTION_EN_V << PMU_HP_ACTIVE2SLEEP_RETENTION_EN_S) -#define PMU_HP_ACTIVE2SLEEP_RETENTION_EN_V 0x00000001U -#define PMU_HP_ACTIVE2SLEEP_RETENTION_EN_S 13 /** PMU_HP_MODEM2SLEEP_BACKUP_CLK_SEL : R/W; bitpos: [17:16]; default: 0; * need_des */ @@ -1111,20 +1237,20 @@ extern "C" { #define PMU_HP_ACTIVE2SLEEP_BACKUP_CLK_SEL_M (PMU_HP_ACTIVE2SLEEP_BACKUP_CLK_SEL_V << PMU_HP_ACTIVE2SLEEP_BACKUP_CLK_SEL_S) #define PMU_HP_ACTIVE2SLEEP_BACKUP_CLK_SEL_V 0x00000003U #define PMU_HP_ACTIVE2SLEEP_BACKUP_CLK_SEL_S 18 -/** PMU_HP_MODEM2SLEEP_BACKUP_MODE : R/W; bitpos: [25:23]; default: 0; +/** PMU_HP_MODEM2SLEEP_BACKUP_MODE : R/W; bitpos: [24:20]; default: 0; * need_des */ -#define PMU_HP_MODEM2SLEEP_BACKUP_MODE 0x00000007U +#define PMU_HP_MODEM2SLEEP_BACKUP_MODE 0x0000001FU #define PMU_HP_MODEM2SLEEP_BACKUP_MODE_M (PMU_HP_MODEM2SLEEP_BACKUP_MODE_V << PMU_HP_MODEM2SLEEP_BACKUP_MODE_S) -#define PMU_HP_MODEM2SLEEP_BACKUP_MODE_V 0x00000007U -#define PMU_HP_MODEM2SLEEP_BACKUP_MODE_S 23 -/** PMU_HP_ACTIVE2SLEEP_BACKUP_MODE : R/W; bitpos: [28:26]; default: 0; +#define PMU_HP_MODEM2SLEEP_BACKUP_MODE_V 0x0000001FU +#define PMU_HP_MODEM2SLEEP_BACKUP_MODE_S 20 +/** PMU_HP_ACTIVE2SLEEP_BACKUP_MODE : R/W; bitpos: [29:25]; default: 0; * need_des */ -#define PMU_HP_ACTIVE2SLEEP_BACKUP_MODE 0x00000007U +#define PMU_HP_ACTIVE2SLEEP_BACKUP_MODE 0x0000001FU #define PMU_HP_ACTIVE2SLEEP_BACKUP_MODE_M (PMU_HP_ACTIVE2SLEEP_BACKUP_MODE_V << PMU_HP_ACTIVE2SLEEP_BACKUP_MODE_S) -#define PMU_HP_ACTIVE2SLEEP_BACKUP_MODE_V 0x00000007U -#define PMU_HP_ACTIVE2SLEEP_BACKUP_MODE_S 26 +#define PMU_HP_ACTIVE2SLEEP_BACKUP_MODE_V 0x0000001FU +#define PMU_HP_ACTIVE2SLEEP_BACKUP_MODE_S 25 /** PMU_HP_MODEM2SLEEP_BACKUP_EN : R/W; bitpos: [30]; default: 0; * need_des */ @@ -1262,6 +1388,13 @@ extern "C" { * need_des */ #define PMU_HP_SLEEP_XTAL_REG (DR_REG_PMU_BASE + 0x98) +/** PMU_HP_SLEEP_XPD_XTALX2 : R/W; bitpos: [30]; default: 1; + * need_des + */ +#define PMU_HP_SLEEP_XPD_XTALX2 (BIT(30)) +#define PMU_HP_SLEEP_XPD_XTALX2_M (PMU_HP_SLEEP_XPD_XTALX2_V << PMU_HP_SLEEP_XPD_XTALX2_S) +#define PMU_HP_SLEEP_XPD_XTALX2_V 0x00000001U +#define PMU_HP_SLEEP_XPD_XTALX2_S 30 /** PMU_HP_SLEEP_XPD_XTAL : R/W; bitpos: [31]; default: 1; * need_des */ @@ -1295,7 +1428,7 @@ extern "C" { #define PMU_HP_SLEEP_LP_REGULATOR_SLP_DBIAS_M (PMU_HP_SLEEP_LP_REGULATOR_SLP_DBIAS_V << PMU_HP_SLEEP_LP_REGULATOR_SLP_DBIAS_S) #define PMU_HP_SLEEP_LP_REGULATOR_SLP_DBIAS_V 0x0000000FU #define PMU_HP_SLEEP_LP_REGULATOR_SLP_DBIAS_S 23 -/** PMU_HP_SLEEP_LP_REGULATOR_DBIAS : R/W; bitpos: [31:27]; default: 17; +/** PMU_HP_SLEEP_LP_REGULATOR_DBIAS : R/W; bitpos: [31:27]; default: 0; * need_des */ #define PMU_HP_SLEEP_LP_REGULATOR_DBIAS 0x0000001FU @@ -1331,6 +1464,13 @@ extern "C" { * need_des */ #define PMU_HP_SLEEP_LP_DIG_POWER_REG (DR_REG_PMU_BASE + 0xa8) +/** PMU_HP_SLEEP_VDD_IO_MODE : R/W; bitpos: [26:23]; default: 0; + * need_des + */ +#define PMU_HP_SLEEP_VDD_IO_MODE 0x0000000FU +#define PMU_HP_SLEEP_VDD_IO_MODE_M (PMU_HP_SLEEP_VDD_IO_MODE_V << PMU_HP_SLEEP_VDD_IO_MODE_S) +#define PMU_HP_SLEEP_VDD_IO_MODE_V 0x0000000FU +#define PMU_HP_SLEEP_VDD_IO_MODE_S 23 /** PMU_HP_SLEEP_BOD_SOURCE_SEL : R/W; bitpos: [27]; default: 0; * need_des */ @@ -1437,7 +1577,7 @@ extern "C" { #define PMU_LP_SLEEP_LP_REGULATOR_SLP_DBIAS_M (PMU_LP_SLEEP_LP_REGULATOR_SLP_DBIAS_V << PMU_LP_SLEEP_LP_REGULATOR_SLP_DBIAS_S) #define PMU_LP_SLEEP_LP_REGULATOR_SLP_DBIAS_V 0x0000000FU #define PMU_LP_SLEEP_LP_REGULATOR_SLP_DBIAS_S 23 -/** PMU_LP_SLEEP_LP_REGULATOR_DBIAS : R/W; bitpos: [31:27]; default: 17; +/** PMU_LP_SLEEP_LP_REGULATOR_DBIAS : R/W; bitpos: [31:27]; default: 0; * need_des */ #define PMU_LP_SLEEP_LP_REGULATOR_DBIAS 0x0000001FU @@ -1461,6 +1601,13 @@ extern "C" { * need_des */ #define PMU_LP_SLEEP_XTAL_REG (DR_REG_PMU_BASE + 0xbc) +/** PMU_LP_SLEEP_XPD_XTALX2 : R/W; bitpos: [30]; default: 1; + * need_des + */ +#define PMU_LP_SLEEP_XPD_XTALX2 (BIT(30)) +#define PMU_LP_SLEEP_XPD_XTALX2_M (PMU_LP_SLEEP_XPD_XTALX2_V << PMU_LP_SLEEP_XPD_XTALX2_S) +#define PMU_LP_SLEEP_XPD_XTALX2_V 0x00000001U +#define PMU_LP_SLEEP_XPD_XTALX2_S 30 /** PMU_LP_SLEEP_XPD_XTAL : R/W; bitpos: [31]; default: 1; * need_des */ @@ -1473,6 +1620,13 @@ extern "C" { * need_des */ #define PMU_LP_SLEEP_LP_DIG_POWER_REG (DR_REG_PMU_BASE + 0xc0) +/** PMU_LP_SLEEP_VDD_IO_MODE : R/W; bitpos: [26:23]; default: 0; + * need_des + */ +#define PMU_LP_SLEEP_VDD_IO_MODE 0x0000000FU +#define PMU_LP_SLEEP_VDD_IO_MODE_M (PMU_LP_SLEEP_VDD_IO_MODE_V << PMU_LP_SLEEP_VDD_IO_MODE_S) +#define PMU_LP_SLEEP_VDD_IO_MODE_V 0x0000000FU +#define PMU_LP_SLEEP_VDD_IO_MODE_S 23 /** PMU_LP_SLEEP_BOD_SOURCE_SEL : R/W; bitpos: [27]; default: 0; * need_des */ @@ -1546,6 +1700,48 @@ extern "C" { * need_des */ #define PMU_LP_SLEEP_BIAS_REG (DR_REG_PMU_BASE + 0xc8) +/** PMU_LP_SLEEP_DCDC_CCM_ENB : R/W; bitpos: [9]; default: 1; + * need_des + */ +#define PMU_LP_SLEEP_DCDC_CCM_ENB (BIT(9)) +#define PMU_LP_SLEEP_DCDC_CCM_ENB_M (PMU_LP_SLEEP_DCDC_CCM_ENB_V << PMU_LP_SLEEP_DCDC_CCM_ENB_S) +#define PMU_LP_SLEEP_DCDC_CCM_ENB_V 0x00000001U +#define PMU_LP_SLEEP_DCDC_CCM_ENB_S 9 +/** PMU_LP_SLEEP_DCDC_CLEAR_RDY : R/W; bitpos: [10]; default: 0; + * need_des + */ +#define PMU_LP_SLEEP_DCDC_CLEAR_RDY (BIT(10)) +#define PMU_LP_SLEEP_DCDC_CLEAR_RDY_M (PMU_LP_SLEEP_DCDC_CLEAR_RDY_V << PMU_LP_SLEEP_DCDC_CLEAR_RDY_S) +#define PMU_LP_SLEEP_DCDC_CLEAR_RDY_V 0x00000001U +#define PMU_LP_SLEEP_DCDC_CLEAR_RDY_S 10 +/** PMU_LP_SLEEP_DIG_PMU_DPCUR_BIAS : R/W; bitpos: [12:11]; default: 1; + * need_des + */ +#define PMU_LP_SLEEP_DIG_PMU_DPCUR_BIAS 0x00000003U +#define PMU_LP_SLEEP_DIG_PMU_DPCUR_BIAS_M (PMU_LP_SLEEP_DIG_PMU_DPCUR_BIAS_V << PMU_LP_SLEEP_DIG_PMU_DPCUR_BIAS_S) +#define PMU_LP_SLEEP_DIG_PMU_DPCUR_BIAS_V 0x00000003U +#define PMU_LP_SLEEP_DIG_PMU_DPCUR_BIAS_S 11 +/** PMU_LP_SLEEP_DIG_PMU_DSFMOS : R/W; bitpos: [16:13]; default: 4; + * need_des + */ +#define PMU_LP_SLEEP_DIG_PMU_DSFMOS 0x0000000FU +#define PMU_LP_SLEEP_DIG_PMU_DSFMOS_M (PMU_LP_SLEEP_DIG_PMU_DSFMOS_V << PMU_LP_SLEEP_DIG_PMU_DSFMOS_S) +#define PMU_LP_SLEEP_DIG_PMU_DSFMOS_V 0x0000000FU +#define PMU_LP_SLEEP_DIG_PMU_DSFMOS_S 13 +/** PMU_LP_SLEEP_DCM_VSET : R/W; bitpos: [21:17]; default: 23; + * need_des + */ +#define PMU_LP_SLEEP_DCM_VSET 0x0000001FU +#define PMU_LP_SLEEP_DCM_VSET_M (PMU_LP_SLEEP_DCM_VSET_V << PMU_LP_SLEEP_DCM_VSET_S) +#define PMU_LP_SLEEP_DCM_VSET_V 0x0000001FU +#define PMU_LP_SLEEP_DCM_VSET_S 17 +/** PMU_LP_SLEEP_DCM_MODE : R/W; bitpos: [23:22]; default: 0; + * need_des + */ +#define PMU_LP_SLEEP_DCM_MODE 0x00000003U +#define PMU_LP_SLEEP_DCM_MODE_M (PMU_LP_SLEEP_DCM_MODE_V << PMU_LP_SLEEP_DCM_MODE_S) +#define PMU_LP_SLEEP_DCM_MODE_V 0x00000003U +#define PMU_LP_SLEEP_DCM_MODE_S 22 /** PMU_LP_SLEEP_XPD_BIAS : R/W; bitpos: [25]; default: 0; * need_des */ @@ -1553,6 +1749,13 @@ extern "C" { #define PMU_LP_SLEEP_XPD_BIAS_M (PMU_LP_SLEEP_XPD_BIAS_V << PMU_LP_SLEEP_XPD_BIAS_S) #define PMU_LP_SLEEP_XPD_BIAS_V 0x00000001U #define PMU_LP_SLEEP_XPD_BIAS_S 25 +/** PMU_LP_SLEEP_DISCNNT_DIG_RTC : R/W; bitpos: [29]; default: 0; + * need_des + */ +#define PMU_LP_SLEEP_DISCNNT_DIG_RTC (BIT(29)) +#define PMU_LP_SLEEP_DISCNNT_DIG_RTC_M (PMU_LP_SLEEP_DISCNNT_DIG_RTC_V << PMU_LP_SLEEP_DISCNNT_DIG_RTC_S) +#define PMU_LP_SLEEP_DISCNNT_DIG_RTC_V 0x00000001U +#define PMU_LP_SLEEP_DISCNNT_DIG_RTC_S 29 /** PMU_LP_SLEEP_PD_CUR : R/W; bitpos: [30]; default: 0; * need_des */ @@ -1621,6 +1824,34 @@ extern "C" { #define PMU_TIE_LOW_XPD_XTAL_M (PMU_TIE_LOW_XPD_XTAL_V << PMU_TIE_LOW_XPD_XTAL_S) #define PMU_TIE_LOW_XPD_XTAL_V 0x00000001U #define PMU_TIE_LOW_XPD_XTAL_S 6 +/** PMU_TIE_LOW_GLOBAL_XTALX2_ICG : WT; bitpos: [7]; default: 0; + * need_des + */ +#define PMU_TIE_LOW_GLOBAL_XTALX2_ICG (BIT(7)) +#define PMU_TIE_LOW_GLOBAL_XTALX2_ICG_M (PMU_TIE_LOW_GLOBAL_XTALX2_ICG_V << PMU_TIE_LOW_GLOBAL_XTALX2_ICG_S) +#define PMU_TIE_LOW_GLOBAL_XTALX2_ICG_V 0x00000001U +#define PMU_TIE_LOW_GLOBAL_XTALX2_ICG_S 7 +/** PMU_TIE_LOW_XPD_XTALX2 : WT; bitpos: [8]; default: 0; + * need_des + */ +#define PMU_TIE_LOW_XPD_XTALX2 (BIT(8)) +#define PMU_TIE_LOW_XPD_XTALX2_M (PMU_TIE_LOW_XPD_XTALX2_V << PMU_TIE_LOW_XPD_XTALX2_S) +#define PMU_TIE_LOW_XPD_XTALX2_V 0x00000001U +#define PMU_TIE_LOW_XPD_XTALX2_S 8 +/** PMU_TIE_HIGH_XTALX2 : WT; bitpos: [23]; default: 0; + * need_des + */ +#define PMU_TIE_HIGH_XTALX2 (BIT(23)) +#define PMU_TIE_HIGH_XTALX2_M (PMU_TIE_HIGH_XTALX2_V << PMU_TIE_HIGH_XTALX2_S) +#define PMU_TIE_HIGH_XTALX2_V 0x00000001U +#define PMU_TIE_HIGH_XTALX2_S 23 +/** PMU_TIE_HIGH_GLOBAL_XTALX2_ICG : WT; bitpos: [24]; default: 0; + * need_des + */ +#define PMU_TIE_HIGH_GLOBAL_XTALX2_ICG (BIT(24)) +#define PMU_TIE_HIGH_GLOBAL_XTALX2_ICG_M (PMU_TIE_HIGH_GLOBAL_XTALX2_ICG_V << PMU_TIE_HIGH_GLOBAL_XTALX2_ICG_S) +#define PMU_TIE_HIGH_GLOBAL_XTALX2_ICG_V 0x00000001U +#define PMU_TIE_HIGH_GLOBAL_XTALX2_ICG_S 24 /** PMU_TIE_HIGH_GLOBAL_BBPLL_ICG : WT; bitpos: [25]; default: 0; * need_des */ @@ -1763,6 +1994,20 @@ extern "C" { * need_des */ #define PMU_IMM_PAD_HOLD_ALL_REG (DR_REG_PMU_BASE + 0xe4) +/** PMU_TIE_HIGH_DIG_PAD_SLP_SEL : WT; bitpos: [26]; default: 0; + * need_des + */ +#define PMU_TIE_HIGH_DIG_PAD_SLP_SEL (BIT(26)) +#define PMU_TIE_HIGH_DIG_PAD_SLP_SEL_M (PMU_TIE_HIGH_DIG_PAD_SLP_SEL_V << PMU_TIE_HIGH_DIG_PAD_SLP_SEL_S) +#define PMU_TIE_HIGH_DIG_PAD_SLP_SEL_V 0x00000001U +#define PMU_TIE_HIGH_DIG_PAD_SLP_SEL_S 26 +/** PMU_TIE_LOW_DIG_PAD_SLP_SEL : WT; bitpos: [27]; default: 0; + * need_des + */ +#define PMU_TIE_LOW_DIG_PAD_SLP_SEL (BIT(27)) +#define PMU_TIE_LOW_DIG_PAD_SLP_SEL_M (PMU_TIE_LOW_DIG_PAD_SLP_SEL_V << PMU_TIE_LOW_DIG_PAD_SLP_SEL_S) +#define PMU_TIE_LOW_DIG_PAD_SLP_SEL_V 0x00000001U +#define PMU_TIE_LOW_DIG_PAD_SLP_SEL_S 27 /** PMU_TIE_HIGH_LP_PAD_HOLD_ALL : WT; bitpos: [28]; default: 0; * need_des */ @@ -1829,44 +2074,77 @@ extern "C" { #define PMU_DG_HP_POWERUP_TIMER_M (PMU_DG_HP_POWERUP_TIMER_V << PMU_DG_HP_POWERUP_TIMER_S) #define PMU_DG_HP_POWERUP_TIMER_V 0x000001FFU #define PMU_DG_HP_POWERUP_TIMER_S 14 -/** PMU_DG_HP_WAIT_TIMER : R/W; bitpos: [31:23]; default: 255; +/** PMU_DG_HP_PD_WAIT_TIMER : R/W; bitpos: [31:23]; default: 255; * need_des */ -#define PMU_DG_HP_WAIT_TIMER 0x000001FFU -#define PMU_DG_HP_WAIT_TIMER_M (PMU_DG_HP_WAIT_TIMER_V << PMU_DG_HP_WAIT_TIMER_S) -#define PMU_DG_HP_WAIT_TIMER_V 0x000001FFU -#define PMU_DG_HP_WAIT_TIMER_S 23 +#define PMU_DG_HP_PD_WAIT_TIMER 0x000001FFU +#define PMU_DG_HP_PD_WAIT_TIMER_M (PMU_DG_HP_PD_WAIT_TIMER_V << PMU_DG_HP_PD_WAIT_TIMER_S) +#define PMU_DG_HP_PD_WAIT_TIMER_V 0x000001FFU +#define PMU_DG_HP_PD_WAIT_TIMER_S 23 /** PMU_POWER_WAIT_TIMER1_REG register * need_des */ #define PMU_POWER_WAIT_TIMER1_REG (DR_REG_PMU_BASE + 0xf0) -/** PMU_DG_LP_POWERDOWN_TIMER : R/W; bitpos: [15:9]; default: 255; +/** PMU_DG_LP_POWERDOWN_TIMER : R/W; bitpos: [15:9]; default: 63; * need_des */ #define PMU_DG_LP_POWERDOWN_TIMER 0x0000007FU #define PMU_DG_LP_POWERDOWN_TIMER_M (PMU_DG_LP_POWERDOWN_TIMER_V << PMU_DG_LP_POWERDOWN_TIMER_S) #define PMU_DG_LP_POWERDOWN_TIMER_V 0x0000007FU #define PMU_DG_LP_POWERDOWN_TIMER_S 9 -/** PMU_DG_LP_POWERUP_TIMER : R/W; bitpos: [22:16]; default: 255; +/** PMU_DG_LP_POWERUP_TIMER : R/W; bitpos: [22:16]; default: 63; * need_des */ #define PMU_DG_LP_POWERUP_TIMER 0x0000007FU #define PMU_DG_LP_POWERUP_TIMER_M (PMU_DG_LP_POWERUP_TIMER_V << PMU_DG_LP_POWERUP_TIMER_S) #define PMU_DG_LP_POWERUP_TIMER_V 0x0000007FU #define PMU_DG_LP_POWERUP_TIMER_S 16 -/** PMU_DG_LP_WAIT_TIMER : R/W; bitpos: [31:23]; default: 255; +/** PMU_DG_LP_PD_WAIT_TIMER : R/W; bitpos: [31:23]; default: 255; * need_des */ -#define PMU_DG_LP_WAIT_TIMER 0x000001FFU -#define PMU_DG_LP_WAIT_TIMER_M (PMU_DG_LP_WAIT_TIMER_V << PMU_DG_LP_WAIT_TIMER_S) -#define PMU_DG_LP_WAIT_TIMER_V 0x000001FFU -#define PMU_DG_LP_WAIT_TIMER_S 23 +#define PMU_DG_LP_PD_WAIT_TIMER 0x000001FFU +#define PMU_DG_LP_PD_WAIT_TIMER_M (PMU_DG_LP_PD_WAIT_TIMER_V << PMU_DG_LP_PD_WAIT_TIMER_S) +#define PMU_DG_LP_PD_WAIT_TIMER_V 0x000001FFU +#define PMU_DG_LP_PD_WAIT_TIMER_S 23 + +/** PMU_POWER_WAIT_TIMER2_REG register + * need_des + */ +#define PMU_POWER_WAIT_TIMER2_REG (DR_REG_PMU_BASE + 0xf4) +/** PMU_DG_LP_ISO_WAIT_TIMER : R/W; bitpos: [7:0]; default: 255; + * need_des + */ +#define PMU_DG_LP_ISO_WAIT_TIMER 0x000000FFU +#define PMU_DG_LP_ISO_WAIT_TIMER_M (PMU_DG_LP_ISO_WAIT_TIMER_V << PMU_DG_LP_ISO_WAIT_TIMER_S) +#define PMU_DG_LP_ISO_WAIT_TIMER_V 0x000000FFU +#define PMU_DG_LP_ISO_WAIT_TIMER_S 0 +/** PMU_DG_LP_RST_WAIT_TIMER : R/W; bitpos: [15:8]; default: 255; + * need_des + */ +#define PMU_DG_LP_RST_WAIT_TIMER 0x000000FFU +#define PMU_DG_LP_RST_WAIT_TIMER_M (PMU_DG_LP_RST_WAIT_TIMER_V << PMU_DG_LP_RST_WAIT_TIMER_S) +#define PMU_DG_LP_RST_WAIT_TIMER_V 0x000000FFU +#define PMU_DG_LP_RST_WAIT_TIMER_S 8 +/** PMU_DG_HP_ISO_WAIT_TIMER : R/W; bitpos: [23:16]; default: 255; + * need_des + */ +#define PMU_DG_HP_ISO_WAIT_TIMER 0x000000FFU +#define PMU_DG_HP_ISO_WAIT_TIMER_M (PMU_DG_HP_ISO_WAIT_TIMER_V << PMU_DG_HP_ISO_WAIT_TIMER_S) +#define PMU_DG_HP_ISO_WAIT_TIMER_V 0x000000FFU +#define PMU_DG_HP_ISO_WAIT_TIMER_S 16 +/** PMU_DG_HP_RST_WAIT_TIMER : R/W; bitpos: [31:24]; default: 255; + * need_des + */ +#define PMU_DG_HP_RST_WAIT_TIMER 0x000000FFU +#define PMU_DG_HP_RST_WAIT_TIMER_M (PMU_DG_HP_RST_WAIT_TIMER_V << PMU_DG_HP_RST_WAIT_TIMER_S) +#define PMU_DG_HP_RST_WAIT_TIMER_V 0x000000FFU +#define PMU_DG_HP_RST_WAIT_TIMER_S 24 /** PMU_POWER_PD_TOP_CNTL_REG register * need_des */ -#define PMU_POWER_PD_TOP_CNTL_REG (DR_REG_PMU_BASE + 0xf4) +#define PMU_POWER_PD_TOP_CNTL_REG (DR_REG_PMU_BASE + 0xf8) /** PMU_FORCE_TOP_RESET : R/W; bitpos: [0]; default: 0; * need_des */ @@ -1927,7 +2205,7 @@ extern "C" { /** PMU_POWER_PD_HPAON_CNTL_REG register * need_des */ -#define PMU_POWER_PD_HPAON_CNTL_REG (DR_REG_PMU_BASE + 0xf8) +#define PMU_POWER_PD_HPAON_CNTL_REG (DR_REG_PMU_BASE + 0xfc) /** PMU_FORCE_HP_AON_RESET : R/W; bitpos: [0]; default: 0; * need_des */ @@ -1988,7 +2266,7 @@ extern "C" { /** PMU_POWER_PD_HPCPU_CNTL_REG register * need_des */ -#define PMU_POWER_PD_HPCPU_CNTL_REG (DR_REG_PMU_BASE + 0xfc) +#define PMU_POWER_PD_HPCPU_CNTL_REG (DR_REG_PMU_BASE + 0x100) /** PMU_FORCE_HP_CPU_RESET : R/W; bitpos: [0]; default: 0; * need_des */ @@ -2049,19 +2327,68 @@ extern "C" { /** PMU_POWER_PD_HPPERI_RESERVE_REG register * need_des */ -#define PMU_POWER_PD_HPPERI_RESERVE_REG (DR_REG_PMU_BASE + 0x100) -/** PMU_HP_PERI_RESERVE : WT; bitpos: [31:0]; default: 0; +#define PMU_POWER_PD_HPPERI_RESERVE_REG (DR_REG_PMU_BASE + 0x104) +/** PMU_FORCE_HP_PERI_RESET : R/W; bitpos: [0]; default: 0; + * need_des + */ +#define PMU_FORCE_HP_PERI_RESET (BIT(0)) +#define PMU_FORCE_HP_PERI_RESET_M (PMU_FORCE_HP_PERI_RESET_V << PMU_FORCE_HP_PERI_RESET_S) +#define PMU_FORCE_HP_PERI_RESET_V 0x00000001U +#define PMU_FORCE_HP_PERI_RESET_S 0 +/** PMU_FORCE_HP_PERI_ISO : R/W; bitpos: [1]; default: 0; + * need_des + */ +#define PMU_FORCE_HP_PERI_ISO (BIT(1)) +#define PMU_FORCE_HP_PERI_ISO_M (PMU_FORCE_HP_PERI_ISO_V << PMU_FORCE_HP_PERI_ISO_S) +#define PMU_FORCE_HP_PERI_ISO_V 0x00000001U +#define PMU_FORCE_HP_PERI_ISO_S 1 +/** PMU_FORCE_HP_PERI_PU : R/W; bitpos: [2]; default: 1; + * need_des + */ +#define PMU_FORCE_HP_PERI_PU (BIT(2)) +#define PMU_FORCE_HP_PERI_PU_M (PMU_FORCE_HP_PERI_PU_V << PMU_FORCE_HP_PERI_PU_S) +#define PMU_FORCE_HP_PERI_PU_V 0x00000001U +#define PMU_FORCE_HP_PERI_PU_S 2 +/** PMU_FORCE_HP_PERI_NO_RESET : R/W; bitpos: [3]; default: 1; + * need_des + */ +#define PMU_FORCE_HP_PERI_NO_RESET (BIT(3)) +#define PMU_FORCE_HP_PERI_NO_RESET_M (PMU_FORCE_HP_PERI_NO_RESET_V << PMU_FORCE_HP_PERI_NO_RESET_S) +#define PMU_FORCE_HP_PERI_NO_RESET_V 0x00000001U +#define PMU_FORCE_HP_PERI_NO_RESET_S 3 +/** PMU_FORCE_HP_PERI_NO_ISO : R/W; bitpos: [4]; default: 1; + * need_des + */ +#define PMU_FORCE_HP_PERI_NO_ISO (BIT(4)) +#define PMU_FORCE_HP_PERI_NO_ISO_M (PMU_FORCE_HP_PERI_NO_ISO_V << PMU_FORCE_HP_PERI_NO_ISO_S) +#define PMU_FORCE_HP_PERI_NO_ISO_V 0x00000001U +#define PMU_FORCE_HP_PERI_NO_ISO_S 4 +/** PMU_FORCE_HP_PERI_PD : R/W; bitpos: [5]; default: 0; + * need_des + */ +#define PMU_FORCE_HP_PERI_PD (BIT(5)) +#define PMU_FORCE_HP_PERI_PD_M (PMU_FORCE_HP_PERI_PD_V << PMU_FORCE_HP_PERI_PD_S) +#define PMU_FORCE_HP_PERI_PD_V 0x00000001U +#define PMU_FORCE_HP_PERI_PD_S 5 +/** PMU_PD_HP_PERI_MASK : R/W; bitpos: [10:6]; default: 0; + * need_des + */ +#define PMU_PD_HP_PERI_MASK 0x0000001FU +#define PMU_PD_HP_PERI_MASK_M (PMU_PD_HP_PERI_MASK_V << PMU_PD_HP_PERI_MASK_S) +#define PMU_PD_HP_PERI_MASK_V 0x0000001FU +#define PMU_PD_HP_PERI_MASK_S 6 +/** PMU_PD_HP_PERI_PD_MASK : R/W; bitpos: [31:27]; default: 0; * need_des */ -#define PMU_HP_PERI_RESERVE 0xFFFFFFFFU -#define PMU_HP_PERI_RESERVE_M (PMU_HP_PERI_RESERVE_V << PMU_HP_PERI_RESERVE_S) -#define PMU_HP_PERI_RESERVE_V 0xFFFFFFFFU -#define PMU_HP_PERI_RESERVE_S 0 +#define PMU_PD_HP_PERI_PD_MASK 0x0000001FU +#define PMU_PD_HP_PERI_PD_MASK_M (PMU_PD_HP_PERI_PD_MASK_V << PMU_PD_HP_PERI_PD_MASK_S) +#define PMU_PD_HP_PERI_PD_MASK_V 0x0000001FU +#define PMU_PD_HP_PERI_PD_MASK_S 27 /** PMU_POWER_PD_HPWIFI_CNTL_REG register * need_des */ -#define PMU_POWER_PD_HPWIFI_CNTL_REG (DR_REG_PMU_BASE + 0x104) +#define PMU_POWER_PD_HPWIFI_CNTL_REG (DR_REG_PMU_BASE + 0x108) /** PMU_FORCE_HP_WIFI_RESET : R/W; bitpos: [0]; default: 0; * need_des */ @@ -2122,7 +2449,7 @@ extern "C" { /** PMU_POWER_PD_LPPERI_CNTL_REG register * need_des */ -#define PMU_POWER_PD_LPPERI_CNTL_REG (DR_REG_PMU_BASE + 0x108) +#define PMU_POWER_PD_LPPERI_CNTL_REG (DR_REG_PMU_BASE + 0x10c) /** PMU_FORCE_LP_PERI_RESET : R/W; bitpos: [0]; default: 0; * need_des */ @@ -2169,7 +2496,7 @@ extern "C" { /** PMU_POWER_PD_MEM_CNTL_REG register * need_des */ -#define PMU_POWER_PD_MEM_CNTL_REG (DR_REG_PMU_BASE + 0x10c) +#define PMU_POWER_PD_MEM_CNTL_REG (DR_REG_PMU_BASE + 0x110) /** PMU_FORCE_HP_MEM_ISO : R/W; bitpos: [3:0]; default: 0; * need_des */ @@ -2202,7 +2529,7 @@ extern "C" { /** PMU_POWER_PD_MEM_MASK_REG register * need_des */ -#define PMU_POWER_PD_MEM_MASK_REG (DR_REG_PMU_BASE + 0x110) +#define PMU_POWER_PD_MEM_MASK_REG (DR_REG_PMU_BASE + 0x114) /** PMU_PD_HP_MEM2_PD_MASK : R/W; bitpos: [4:0]; default: 0; * need_des */ @@ -2249,7 +2576,7 @@ extern "C" { /** PMU_POWER_HP_PAD_REG register * need_des */ -#define PMU_POWER_HP_PAD_REG (DR_REG_PMU_BASE + 0x114) +#define PMU_POWER_HP_PAD_REG (DR_REG_PMU_BASE + 0x118) /** PMU_FORCE_HP_PAD_NO_ISO_ALL : R/W; bitpos: [0]; default: 0; * need_des */ @@ -2265,36 +2592,350 @@ extern "C" { #define PMU_FORCE_HP_PAD_ISO_ALL_V 0x00000001U #define PMU_FORCE_HP_PAD_ISO_ALL_S 1 -/** PMU_POWER_VDD_SPI_CNTL_REG register +/** PMU_POWER_FLASH1P8_LDO_REG register * need_des */ -#define PMU_POWER_VDD_SPI_CNTL_REG (DR_REG_PMU_BASE + 0x118) -/** PMU_VDD_SPI_PWR_WAIT : R/W; bitpos: [28:18]; default: 255; +#define PMU_POWER_FLASH1P8_LDO_REG (DR_REG_PMU_BASE + 0x11c) +/** PMU_FLASH1P8_LDO_RDY : RO; bitpos: [0]; default: 1; * need_des */ -#define PMU_VDD_SPI_PWR_WAIT 0x000007FFU -#define PMU_VDD_SPI_PWR_WAIT_M (PMU_VDD_SPI_PWR_WAIT_V << PMU_VDD_SPI_PWR_WAIT_S) -#define PMU_VDD_SPI_PWR_WAIT_V 0x000007FFU -#define PMU_VDD_SPI_PWR_WAIT_S 18 -/** PMU_VDD_SPI_PWR_SW : R/W; bitpos: [30:29]; default: 3; +#define PMU_FLASH1P8_LDO_RDY (BIT(0)) +#define PMU_FLASH1P8_LDO_RDY_M (PMU_FLASH1P8_LDO_RDY_V << PMU_FLASH1P8_LDO_RDY_S) +#define PMU_FLASH1P8_LDO_RDY_V 0x00000001U +#define PMU_FLASH1P8_LDO_RDY_S 0 +/** PMU_FLASH1P8_SW_EN_XPD : R/W; bitpos: [1]; default: 0; * need_des */ -#define PMU_VDD_SPI_PWR_SW 0x00000003U -#define PMU_VDD_SPI_PWR_SW_M (PMU_VDD_SPI_PWR_SW_V << PMU_VDD_SPI_PWR_SW_S) -#define PMU_VDD_SPI_PWR_SW_V 0x00000003U -#define PMU_VDD_SPI_PWR_SW_S 29 -/** PMU_VDD_SPI_PWR_SEL_SW : R/W; bitpos: [31]; default: 0; +#define PMU_FLASH1P8_SW_EN_XPD (BIT(1)) +#define PMU_FLASH1P8_SW_EN_XPD_M (PMU_FLASH1P8_SW_EN_XPD_V << PMU_FLASH1P8_SW_EN_XPD_S) +#define PMU_FLASH1P8_SW_EN_XPD_V 0x00000001U +#define PMU_FLASH1P8_SW_EN_XPD_S 1 +/** PMU_FLASH1P8_SW_EN_THRU : R/W; bitpos: [2]; default: 0; * need_des */ -#define PMU_VDD_SPI_PWR_SEL_SW (BIT(31)) -#define PMU_VDD_SPI_PWR_SEL_SW_M (PMU_VDD_SPI_PWR_SEL_SW_V << PMU_VDD_SPI_PWR_SEL_SW_S) -#define PMU_VDD_SPI_PWR_SEL_SW_V 0x00000001U -#define PMU_VDD_SPI_PWR_SEL_SW_S 31 +#define PMU_FLASH1P8_SW_EN_THRU (BIT(2)) +#define PMU_FLASH1P8_SW_EN_THRU_M (PMU_FLASH1P8_SW_EN_THRU_V << PMU_FLASH1P8_SW_EN_THRU_S) +#define PMU_FLASH1P8_SW_EN_THRU_V 0x00000001U +#define PMU_FLASH1P8_SW_EN_THRU_S 2 +/** PMU_FLASH1P8_SW_EN_STANDBY : R/W; bitpos: [3]; default: 0; + * need_des + */ +#define PMU_FLASH1P8_SW_EN_STANDBY (BIT(3)) +#define PMU_FLASH1P8_SW_EN_STANDBY_M (PMU_FLASH1P8_SW_EN_STANDBY_V << PMU_FLASH1P8_SW_EN_STANDBY_S) +#define PMU_FLASH1P8_SW_EN_STANDBY_V 0x00000001U +#define PMU_FLASH1P8_SW_EN_STANDBY_S 3 +/** PMU_FLASH1P8_SW_EN_POWER_ADJUST : R/W; bitpos: [4]; default: 0; + * need_des + */ +#define PMU_FLASH1P8_SW_EN_POWER_ADJUST (BIT(4)) +#define PMU_FLASH1P8_SW_EN_POWER_ADJUST_M (PMU_FLASH1P8_SW_EN_POWER_ADJUST_V << PMU_FLASH1P8_SW_EN_POWER_ADJUST_S) +#define PMU_FLASH1P8_SW_EN_POWER_ADJUST_V 0x00000001U +#define PMU_FLASH1P8_SW_EN_POWER_ADJUST_S 4 +/** PMU_FLASH1P8_SW_EN_ENDET : R/W; bitpos: [5]; default: 0; + * need_des + */ +#define PMU_FLASH1P8_SW_EN_ENDET (BIT(5)) +#define PMU_FLASH1P8_SW_EN_ENDET_M (PMU_FLASH1P8_SW_EN_ENDET_V << PMU_FLASH1P8_SW_EN_ENDET_S) +#define PMU_FLASH1P8_SW_EN_ENDET_V 0x00000001U +#define PMU_FLASH1P8_SW_EN_ENDET_S 5 +/** PMU_FLASH1P8_BYPASS_LDO_RDY : R/W; bitpos: [22]; default: 0; + * need_des + */ +#define PMU_FLASH1P8_BYPASS_LDO_RDY (BIT(22)) +#define PMU_FLASH1P8_BYPASS_LDO_RDY_M (PMU_FLASH1P8_BYPASS_LDO_RDY_V << PMU_FLASH1P8_BYPASS_LDO_RDY_S) +#define PMU_FLASH1P8_BYPASS_LDO_RDY_V 0x00000001U +#define PMU_FLASH1P8_BYPASS_LDO_RDY_S 22 +/** PMU_FLASH1P8_XPD : R/W; bitpos: [23]; default: 0; + * need_des + */ +#define PMU_FLASH1P8_XPD (BIT(23)) +#define PMU_FLASH1P8_XPD_M (PMU_FLASH1P8_XPD_V << PMU_FLASH1P8_XPD_S) +#define PMU_FLASH1P8_XPD_V 0x00000001U +#define PMU_FLASH1P8_XPD_S 23 +/** PMU_FLASH1P8_THRU : R/W; bitpos: [24]; default: 1; + * need_des + */ +#define PMU_FLASH1P8_THRU (BIT(24)) +#define PMU_FLASH1P8_THRU_M (PMU_FLASH1P8_THRU_V << PMU_FLASH1P8_THRU_S) +#define PMU_FLASH1P8_THRU_V 0x00000001U +#define PMU_FLASH1P8_THRU_S 24 +/** PMU_FLASH1P8_STANDBY : R/W; bitpos: [25]; default: 0; + * need_des + */ +#define PMU_FLASH1P8_STANDBY (BIT(25)) +#define PMU_FLASH1P8_STANDBY_M (PMU_FLASH1P8_STANDBY_V << PMU_FLASH1P8_STANDBY_S) +#define PMU_FLASH1P8_STANDBY_V 0x00000001U +#define PMU_FLASH1P8_STANDBY_S 25 +/** PMU_FLASH1P8_POWER_ADJUST : R/W; bitpos: [30:26]; default: 0; + * need_des + */ +#define PMU_FLASH1P8_POWER_ADJUST 0x0000001FU +#define PMU_FLASH1P8_POWER_ADJUST_M (PMU_FLASH1P8_POWER_ADJUST_V << PMU_FLASH1P8_POWER_ADJUST_S) +#define PMU_FLASH1P8_POWER_ADJUST_V 0x0000001FU +#define PMU_FLASH1P8_POWER_ADJUST_S 26 +/** PMU_FLASH1P8_ENDET : R/W; bitpos: [31]; default: 0; + * need_des + */ +#define PMU_FLASH1P8_ENDET (BIT(31)) +#define PMU_FLASH1P8_ENDET_M (PMU_FLASH1P8_ENDET_V << PMU_FLASH1P8_ENDET_S) +#define PMU_FLASH1P8_ENDET_V 0x00000001U +#define PMU_FLASH1P8_ENDET_S 31 + +/** PMU_POWER_FLASH1P2_LDO_REG register + * need_des + */ +#define PMU_POWER_FLASH1P2_LDO_REG (DR_REG_PMU_BASE + 0x120) +/** PMU_FLASH1P2_LDO_RDY : RO; bitpos: [0]; default: 1; + * need_des + */ +#define PMU_FLASH1P2_LDO_RDY (BIT(0)) +#define PMU_FLASH1P2_LDO_RDY_M (PMU_FLASH1P2_LDO_RDY_V << PMU_FLASH1P2_LDO_RDY_S) +#define PMU_FLASH1P2_LDO_RDY_V 0x00000001U +#define PMU_FLASH1P2_LDO_RDY_S 0 +/** PMU_FLASH1P2_SW_EN_XPD : R/W; bitpos: [1]; default: 0; + * need_des + */ +#define PMU_FLASH1P2_SW_EN_XPD (BIT(1)) +#define PMU_FLASH1P2_SW_EN_XPD_M (PMU_FLASH1P2_SW_EN_XPD_V << PMU_FLASH1P2_SW_EN_XPD_S) +#define PMU_FLASH1P2_SW_EN_XPD_V 0x00000001U +#define PMU_FLASH1P2_SW_EN_XPD_S 1 +/** PMU_FLASH1P2_SW_EN_THRU : R/W; bitpos: [2]; default: 0; + * need_des + */ +#define PMU_FLASH1P2_SW_EN_THRU (BIT(2)) +#define PMU_FLASH1P2_SW_EN_THRU_M (PMU_FLASH1P2_SW_EN_THRU_V << PMU_FLASH1P2_SW_EN_THRU_S) +#define PMU_FLASH1P2_SW_EN_THRU_V 0x00000001U +#define PMU_FLASH1P2_SW_EN_THRU_S 2 +/** PMU_FLASH1P2_SW_EN_STANDBY : R/W; bitpos: [3]; default: 0; + * need_des + */ +#define PMU_FLASH1P2_SW_EN_STANDBY (BIT(3)) +#define PMU_FLASH1P2_SW_EN_STANDBY_M (PMU_FLASH1P2_SW_EN_STANDBY_V << PMU_FLASH1P2_SW_EN_STANDBY_S) +#define PMU_FLASH1P2_SW_EN_STANDBY_V 0x00000001U +#define PMU_FLASH1P2_SW_EN_STANDBY_S 3 +/** PMU_FLASH1P2_SW_EN_POWER_ADJUST : R/W; bitpos: [4]; default: 0; + * need_des + */ +#define PMU_FLASH1P2_SW_EN_POWER_ADJUST (BIT(4)) +#define PMU_FLASH1P2_SW_EN_POWER_ADJUST_M (PMU_FLASH1P2_SW_EN_POWER_ADJUST_V << PMU_FLASH1P2_SW_EN_POWER_ADJUST_S) +#define PMU_FLASH1P2_SW_EN_POWER_ADJUST_V 0x00000001U +#define PMU_FLASH1P2_SW_EN_POWER_ADJUST_S 4 +/** PMU_FLASH1P2_SW_EN_ENDET : R/W; bitpos: [5]; default: 0; + * need_des + */ +#define PMU_FLASH1P2_SW_EN_ENDET (BIT(5)) +#define PMU_FLASH1P2_SW_EN_ENDET_M (PMU_FLASH1P2_SW_EN_ENDET_V << PMU_FLASH1P2_SW_EN_ENDET_S) +#define PMU_FLASH1P2_SW_EN_ENDET_V 0x00000001U +#define PMU_FLASH1P2_SW_EN_ENDET_S 5 +/** PMU_FLASH1P2_BYPASS_LDO_RDY : R/W; bitpos: [22]; default: 0; + * need_des + */ +#define PMU_FLASH1P2_BYPASS_LDO_RDY (BIT(22)) +#define PMU_FLASH1P2_BYPASS_LDO_RDY_M (PMU_FLASH1P2_BYPASS_LDO_RDY_V << PMU_FLASH1P2_BYPASS_LDO_RDY_S) +#define PMU_FLASH1P2_BYPASS_LDO_RDY_V 0x00000001U +#define PMU_FLASH1P2_BYPASS_LDO_RDY_S 22 +/** PMU_FLASH1P2_XPD : R/W; bitpos: [23]; default: 0; + * need_des + */ +#define PMU_FLASH1P2_XPD (BIT(23)) +#define PMU_FLASH1P2_XPD_M (PMU_FLASH1P2_XPD_V << PMU_FLASH1P2_XPD_S) +#define PMU_FLASH1P2_XPD_V 0x00000001U +#define PMU_FLASH1P2_XPD_S 23 +/** PMU_FLASH1P2_THRU : R/W; bitpos: [24]; default: 1; + * need_des + */ +#define PMU_FLASH1P2_THRU (BIT(24)) +#define PMU_FLASH1P2_THRU_M (PMU_FLASH1P2_THRU_V << PMU_FLASH1P2_THRU_S) +#define PMU_FLASH1P2_THRU_V 0x00000001U +#define PMU_FLASH1P2_THRU_S 24 +/** PMU_FLASH1P2_STANDBY : R/W; bitpos: [25]; default: 0; + * need_des + */ +#define PMU_FLASH1P2_STANDBY (BIT(25)) +#define PMU_FLASH1P2_STANDBY_M (PMU_FLASH1P2_STANDBY_V << PMU_FLASH1P2_STANDBY_S) +#define PMU_FLASH1P2_STANDBY_V 0x00000001U +#define PMU_FLASH1P2_STANDBY_S 25 +/** PMU_FLASH1P2_POWER_ADJUST : R/W; bitpos: [30:26]; default: 0; + * need_des + */ +#define PMU_FLASH1P2_POWER_ADJUST 0x0000001FU +#define PMU_FLASH1P2_POWER_ADJUST_M (PMU_FLASH1P2_POWER_ADJUST_V << PMU_FLASH1P2_POWER_ADJUST_S) +#define PMU_FLASH1P2_POWER_ADJUST_V 0x0000001FU +#define PMU_FLASH1P2_POWER_ADJUST_S 26 +/** PMU_FLASH1P2_ENDET : R/W; bitpos: [31]; default: 0; + * need_des + */ +#define PMU_FLASH1P2_ENDET (BIT(31)) +#define PMU_FLASH1P2_ENDET_M (PMU_FLASH1P2_ENDET_V << PMU_FLASH1P2_ENDET_S) +#define PMU_FLASH1P2_ENDET_V 0x00000001U +#define PMU_FLASH1P2_ENDET_S 31 + +/** PMU_POWER_VDD_FLASH_REG register + * need_des + */ +#define PMU_POWER_VDD_FLASH_REG (DR_REG_PMU_BASE + 0x124) +/** PMU_FLASH_LDO_SW_EN_TIEL : R/W; bitpos: [22]; default: 0; + * need_des + */ +#define PMU_FLASH_LDO_SW_EN_TIEL (BIT(22)) +#define PMU_FLASH_LDO_SW_EN_TIEL_M (PMU_FLASH_LDO_SW_EN_TIEL_V << PMU_FLASH_LDO_SW_EN_TIEL_S) +#define PMU_FLASH_LDO_SW_EN_TIEL_V 0x00000001U +#define PMU_FLASH_LDO_SW_EN_TIEL_S 22 +/** PMU_FLASH_LDO_POWER_SEL : R/W; bitpos: [23]; default: 0; + * need_des + */ +#define PMU_FLASH_LDO_POWER_SEL (BIT(23)) +#define PMU_FLASH_LDO_POWER_SEL_M (PMU_FLASH_LDO_POWER_SEL_V << PMU_FLASH_LDO_POWER_SEL_S) +#define PMU_FLASH_LDO_POWER_SEL_V 0x00000001U +#define PMU_FLASH_LDO_POWER_SEL_S 23 +/** PMU_FLASH_LDO_SW_EN_POWER_SEL : R/W; bitpos: [24]; default: 0; + * need_des + */ +#define PMU_FLASH_LDO_SW_EN_POWER_SEL (BIT(24)) +#define PMU_FLASH_LDO_SW_EN_POWER_SEL_M (PMU_FLASH_LDO_SW_EN_POWER_SEL_V << PMU_FLASH_LDO_SW_EN_POWER_SEL_S) +#define PMU_FLASH_LDO_SW_EN_POWER_SEL_V 0x00000001U +#define PMU_FLASH_LDO_SW_EN_POWER_SEL_S 24 +/** PMU_FLASH_LDO_WAIT_TARGET : R/W; bitpos: [28:25]; default: 15; + * need_des + */ +#define PMU_FLASH_LDO_WAIT_TARGET 0x0000000FU +#define PMU_FLASH_LDO_WAIT_TARGET_M (PMU_FLASH_LDO_WAIT_TARGET_V << PMU_FLASH_LDO_WAIT_TARGET_S) +#define PMU_FLASH_LDO_WAIT_TARGET_V 0x0000000FU +#define PMU_FLASH_LDO_WAIT_TARGET_S 25 +/** PMU_FLASH_LDO_TIEL_EN : R/W; bitpos: [29]; default: 0; + * need_des + */ +#define PMU_FLASH_LDO_TIEL_EN (BIT(29)) +#define PMU_FLASH_LDO_TIEL_EN_M (PMU_FLASH_LDO_TIEL_EN_V << PMU_FLASH_LDO_TIEL_EN_S) +#define PMU_FLASH_LDO_TIEL_EN_V 0x00000001U +#define PMU_FLASH_LDO_TIEL_EN_S 29 +/** PMU_FLASH_LDO_TIEL : R/W; bitpos: [30]; default: 0; + * need_des + */ +#define PMU_FLASH_LDO_TIEL (BIT(30)) +#define PMU_FLASH_LDO_TIEL_M (PMU_FLASH_LDO_TIEL_V << PMU_FLASH_LDO_TIEL_S) +#define PMU_FLASH_LDO_TIEL_V 0x00000001U +#define PMU_FLASH_LDO_TIEL_S 30 +/** PMU_FLASH_LDO_SW_UPDATE : WT; bitpos: [31]; default: 0; + * need_des + */ +#define PMU_FLASH_LDO_SW_UPDATE (BIT(31)) +#define PMU_FLASH_LDO_SW_UPDATE_M (PMU_FLASH_LDO_SW_UPDATE_V << PMU_FLASH_LDO_SW_UPDATE_S) +#define PMU_FLASH_LDO_SW_UPDATE_V 0x00000001U +#define PMU_FLASH_LDO_SW_UPDATE_S 31 + +/** PMU_POWER_IO_LDO_REG register + * need_des + */ +#define PMU_POWER_IO_LDO_REG (DR_REG_PMU_BASE + 0x128) +/** PMU_IO_LDO_RDY : RO; bitpos: [0]; default: 1; + * need_des + */ +#define PMU_IO_LDO_RDY (BIT(0)) +#define PMU_IO_LDO_RDY_M (PMU_IO_LDO_RDY_V << PMU_IO_LDO_RDY_S) +#define PMU_IO_LDO_RDY_V 0x00000001U +#define PMU_IO_LDO_RDY_S 0 +/** PMU_IO_SW_EN_XPD : R/W; bitpos: [1]; default: 0; + * need_des + */ +#define PMU_IO_SW_EN_XPD (BIT(1)) +#define PMU_IO_SW_EN_XPD_M (PMU_IO_SW_EN_XPD_V << PMU_IO_SW_EN_XPD_S) +#define PMU_IO_SW_EN_XPD_V 0x00000001U +#define PMU_IO_SW_EN_XPD_S 1 +/** PMU_IO_SW_EN_THRU : R/W; bitpos: [3]; default: 0; + * need_des + */ +#define PMU_IO_SW_EN_THRU (BIT(3)) +#define PMU_IO_SW_EN_THRU_M (PMU_IO_SW_EN_THRU_V << PMU_IO_SW_EN_THRU_S) +#define PMU_IO_SW_EN_THRU_V 0x00000001U +#define PMU_IO_SW_EN_THRU_S 3 +/** PMU_IO_SW_EN_STANDBY : R/W; bitpos: [4]; default: 0; + * need_des + */ +#define PMU_IO_SW_EN_STANDBY (BIT(4)) +#define PMU_IO_SW_EN_STANDBY_M (PMU_IO_SW_EN_STANDBY_V << PMU_IO_SW_EN_STANDBY_S) +#define PMU_IO_SW_EN_STANDBY_V 0x00000001U +#define PMU_IO_SW_EN_STANDBY_S 4 +/** PMU_IO_SW_EN_POWER_ADJUST : R/W; bitpos: [5]; default: 0; + * need_des + */ +#define PMU_IO_SW_EN_POWER_ADJUST (BIT(5)) +#define PMU_IO_SW_EN_POWER_ADJUST_M (PMU_IO_SW_EN_POWER_ADJUST_V << PMU_IO_SW_EN_POWER_ADJUST_S) +#define PMU_IO_SW_EN_POWER_ADJUST_V 0x00000001U +#define PMU_IO_SW_EN_POWER_ADJUST_S 5 +/** PMU_IO_SW_EN_ENDET : R/W; bitpos: [6]; default: 0; + * need_des + */ +#define PMU_IO_SW_EN_ENDET (BIT(6)) +#define PMU_IO_SW_EN_ENDET_M (PMU_IO_SW_EN_ENDET_V << PMU_IO_SW_EN_ENDET_S) +#define PMU_IO_SW_EN_ENDET_V 0x00000001U +#define PMU_IO_SW_EN_ENDET_S 6 +/** PMU_IO_BYPASS_LDO_RDY : R/W; bitpos: [22]; default: 0; + * need_des + */ +#define PMU_IO_BYPASS_LDO_RDY (BIT(22)) +#define PMU_IO_BYPASS_LDO_RDY_M (PMU_IO_BYPASS_LDO_RDY_V << PMU_IO_BYPASS_LDO_RDY_S) +#define PMU_IO_BYPASS_LDO_RDY_V 0x00000001U +#define PMU_IO_BYPASS_LDO_RDY_S 22 +/** PMU_IO_XPD : R/W; bitpos: [23]; default: 0; + * need_des + */ +#define PMU_IO_XPD (BIT(23)) +#define PMU_IO_XPD_M (PMU_IO_XPD_V << PMU_IO_XPD_S) +#define PMU_IO_XPD_V 0x00000001U +#define PMU_IO_XPD_S 23 +/** PMU_IO_THRU : R/W; bitpos: [24]; default: 1; + * need_des + */ +#define PMU_IO_THRU (BIT(24)) +#define PMU_IO_THRU_M (PMU_IO_THRU_V << PMU_IO_THRU_S) +#define PMU_IO_THRU_V 0x00000001U +#define PMU_IO_THRU_S 24 +/** PMU_IO_STANDBY : R/W; bitpos: [25]; default: 0; + * need_des + */ +#define PMU_IO_STANDBY (BIT(25)) +#define PMU_IO_STANDBY_M (PMU_IO_STANDBY_V << PMU_IO_STANDBY_S) +#define PMU_IO_STANDBY_V 0x00000001U +#define PMU_IO_STANDBY_S 25 +/** PMU_IO_POWER_ADJUST : R/W; bitpos: [30:26]; default: 0; + * need_des + */ +#define PMU_IO_POWER_ADJUST 0x0000001FU +#define PMU_IO_POWER_ADJUST_M (PMU_IO_POWER_ADJUST_V << PMU_IO_POWER_ADJUST_S) +#define PMU_IO_POWER_ADJUST_V 0x0000001FU +#define PMU_IO_POWER_ADJUST_S 26 +/** PMU_IO_ENDET : R/W; bitpos: [31]; default: 0; + * need_des + */ +#define PMU_IO_ENDET (BIT(31)) +#define PMU_IO_ENDET_M (PMU_IO_ENDET_V << PMU_IO_ENDET_S) +#define PMU_IO_ENDET_V 0x00000001U +#define PMU_IO_ENDET_S 31 + +/** PMU_POWER_VDD_IO_REG register + * need_des + */ +#define PMU_POWER_VDD_IO_REG (DR_REG_PMU_BASE + 0x12c) +/** PMU_IO_LDO_POWER_SEL : R/W; bitpos: [23]; default: 0; + * need_des + */ +#define PMU_IO_LDO_POWER_SEL (BIT(23)) +#define PMU_IO_LDO_POWER_SEL_M (PMU_IO_LDO_POWER_SEL_V << PMU_IO_LDO_POWER_SEL_S) +#define PMU_IO_LDO_POWER_SEL_V 0x00000001U +#define PMU_IO_LDO_POWER_SEL_S 23 +/** PMU_IO_LDO_SW_EN_POWER_SEL : R/W; bitpos: [24]; default: 0; + * need_des + */ +#define PMU_IO_LDO_SW_EN_POWER_SEL (BIT(24)) +#define PMU_IO_LDO_SW_EN_POWER_SEL_M (PMU_IO_LDO_SW_EN_POWER_SEL_V << PMU_IO_LDO_SW_EN_POWER_SEL_S) +#define PMU_IO_LDO_SW_EN_POWER_SEL_V 0x00000001U +#define PMU_IO_LDO_SW_EN_POWER_SEL_S 24 /** PMU_POWER_CK_WAIT_CNTL_REG register * need_des */ -#define PMU_POWER_CK_WAIT_CNTL_REG (DR_REG_PMU_BASE + 0x11c) +#define PMU_POWER_CK_WAIT_CNTL_REG (DR_REG_PMU_BASE + 0x130) /** PMU_WAIT_XTL_STABLE : R/W; bitpos: [15:0]; default: 256; * need_des */ @@ -2313,7 +2954,7 @@ extern "C" { /** PMU_SLP_WAKEUP_CNTL0_REG register * need_des */ -#define PMU_SLP_WAKEUP_CNTL0_REG (DR_REG_PMU_BASE + 0x120) +#define PMU_SLP_WAKEUP_CNTL0_REG (DR_REG_PMU_BASE + 0x134) /** PMU_SLEEP_REQ : WT; bitpos: [31]; default: 0; * need_des */ @@ -2325,7 +2966,7 @@ extern "C" { /** PMU_SLP_WAKEUP_CNTL1_REG register * need_des */ -#define PMU_SLP_WAKEUP_CNTL1_REG (DR_REG_PMU_BASE + 0x124) +#define PMU_SLP_WAKEUP_CNTL1_REG (DR_REG_PMU_BASE + 0x138) /** PMU_SLEEP_REJECT_ENA : R/W; bitpos: [30:0]; default: 0; * need_des */ @@ -2344,7 +2985,7 @@ extern "C" { /** PMU_SLP_WAKEUP_CNTL2_REG register * need_des */ -#define PMU_SLP_WAKEUP_CNTL2_REG (DR_REG_PMU_BASE + 0x128) +#define PMU_SLP_WAKEUP_CNTL2_REG (DR_REG_PMU_BASE + 0x13c) /** PMU_WAKEUP_ENA : R/W; bitpos: [31:0]; default: 0; * need_des */ @@ -2356,7 +2997,7 @@ extern "C" { /** PMU_SLP_WAKEUP_CNTL3_REG register * need_des */ -#define PMU_SLP_WAKEUP_CNTL3_REG (DR_REG_PMU_BASE + 0x12c) +#define PMU_SLP_WAKEUP_CNTL3_REG (DR_REG_PMU_BASE + 0x140) /** PMU_LP_MIN_SLP_VAL : R/W; bitpos: [7:0]; default: 0; * need_des */ @@ -2382,7 +3023,7 @@ extern "C" { /** PMU_SLP_WAKEUP_CNTL4_REG register * need_des */ -#define PMU_SLP_WAKEUP_CNTL4_REG (DR_REG_PMU_BASE + 0x130) +#define PMU_SLP_WAKEUP_CNTL4_REG (DR_REG_PMU_BASE + 0x144) /** PMU_SLP_REJECT_CAUSE_CLR : WT; bitpos: [31]; default: 0; * need_des */ @@ -2394,7 +3035,7 @@ extern "C" { /** PMU_SLP_WAKEUP_CNTL5_REG register * need_des */ -#define PMU_SLP_WAKEUP_CNTL5_REG (DR_REG_PMU_BASE + 0x134) +#define PMU_SLP_WAKEUP_CNTL5_REG (DR_REG_PMU_BASE + 0x148) /** PMU_MODEM_WAIT_TARGET : R/W; bitpos: [19:0]; default: 128; * need_des */ @@ -2413,7 +3054,7 @@ extern "C" { /** PMU_SLP_WAKEUP_CNTL6_REG register * need_des */ -#define PMU_SLP_WAKEUP_CNTL6_REG (DR_REG_PMU_BASE + 0x138) +#define PMU_SLP_WAKEUP_CNTL6_REG (DR_REG_PMU_BASE + 0x14c) /** PMU_SOC_WAKEUP_WAIT : R/W; bitpos: [19:0]; default: 128; * need_des */ @@ -2432,7 +3073,14 @@ extern "C" { /** PMU_SLP_WAKEUP_CNTL7_REG register * need_des */ -#define PMU_SLP_WAKEUP_CNTL7_REG (DR_REG_PMU_BASE + 0x13c) +#define PMU_SLP_WAKEUP_CNTL7_REG (DR_REG_PMU_BASE + 0x150) +/** PMU_ANA_WAIT_CLK_SEL : R/W; bitpos: [15]; default: 0; + * need_des + */ +#define PMU_ANA_WAIT_CLK_SEL (BIT(15)) +#define PMU_ANA_WAIT_CLK_SEL_M (PMU_ANA_WAIT_CLK_SEL_V << PMU_ANA_WAIT_CLK_SEL_S) +#define PMU_ANA_WAIT_CLK_SEL_V 0x00000001U +#define PMU_ANA_WAIT_CLK_SEL_S 15 /** PMU_ANA_WAIT_TARGET : R/W; bitpos: [31:16]; default: 1; * need_des */ @@ -2444,7 +3092,7 @@ extern "C" { /** PMU_SLP_WAKEUP_STATUS0_REG register * need_des */ -#define PMU_SLP_WAKEUP_STATUS0_REG (DR_REG_PMU_BASE + 0x140) +#define PMU_SLP_WAKEUP_STATUS0_REG (DR_REG_PMU_BASE + 0x154) /** PMU_WAKEUP_CAUSE : RO; bitpos: [31:0]; default: 0; * need_des */ @@ -2456,7 +3104,7 @@ extern "C" { /** PMU_SLP_WAKEUP_STATUS1_REG register * need_des */ -#define PMU_SLP_WAKEUP_STATUS1_REG (DR_REG_PMU_BASE + 0x144) +#define PMU_SLP_WAKEUP_STATUS1_REG (DR_REG_PMU_BASE + 0x158) /** PMU_REJECT_CAUSE : RO; bitpos: [31:0]; default: 0; * need_des */ @@ -2468,7 +3116,7 @@ extern "C" { /** PMU_HP_CK_POWERON_REG register * need_des */ -#define PMU_HP_CK_POWERON_REG (DR_REG_PMU_BASE + 0x148) +#define PMU_HP_CK_POWERON_REG (DR_REG_PMU_BASE + 0x15c) /** PMU_I2C_POR_WAIT_TARGET : R/W; bitpos: [7:0]; default: 50; * need_des */ @@ -2480,7 +3128,7 @@ extern "C" { /** PMU_HP_CK_CNTL_REG register * need_des */ -#define PMU_HP_CK_CNTL_REG (DR_REG_PMU_BASE + 0x14c) +#define PMU_HP_CK_CNTL_REG (DR_REG_PMU_BASE + 0x160) /** PMU_MODIFY_ICG_CNTL_WAIT : R/W; bitpos: [7:0]; default: 10; * need_des */ @@ -2499,8 +3147,8 @@ extern "C" { /** PMU_POR_STATUS_REG register * need_des */ -#define PMU_POR_STATUS_REG (DR_REG_PMU_BASE + 0x150) -/** PMU_POR_DONE : RO; bitpos: [31]; default: 1; +#define PMU_POR_STATUS_REG (DR_REG_PMU_BASE + 0x164) +/** PMU_POR_DONE : RO; bitpos: [31]; default: 0; * need_des */ #define PMU_POR_DONE (BIT(31)) @@ -2511,7 +3159,14 @@ extern "C" { /** PMU_RF_PWC_REG register * need_des */ -#define PMU_RF_PWC_REG (DR_REG_PMU_BASE + 0x154) +#define PMU_RF_PWC_REG (DR_REG_PMU_BASE + 0x168) +/** PMU_XPD_FORCE_RFTX : R/W; bitpos: [26]; default: 0; + * need_des + */ +#define PMU_XPD_FORCE_RFTX (BIT(26)) +#define PMU_XPD_FORCE_RFTX_M (PMU_XPD_FORCE_RFTX_V << PMU_XPD_FORCE_RFTX_S) +#define PMU_XPD_FORCE_RFTX_V 0x00000001U +#define PMU_XPD_FORCE_RFTX_S 26 /** PMU_XPD_PERIF_I2C : R/W; bitpos: [27]; default: 1; * need_des */ @@ -2551,7 +3206,7 @@ extern "C" { /** PMU_VDDBAT_CFG_REG register * need_des */ -#define PMU_VDDBAT_CFG_REG (DR_REG_PMU_BASE + 0x158) +#define PMU_VDDBAT_CFG_REG (DR_REG_PMU_BASE + 0x16c) /** PMU_VDDBAT_MODE : RO; bitpos: [1:0]; default: 0; * need_des */ @@ -2570,7 +3225,7 @@ extern "C" { /** PMU_BACKUP_CFG_REG register * need_des */ -#define PMU_BACKUP_CFG_REG (DR_REG_PMU_BASE + 0x15c) +#define PMU_BACKUP_CFG_REG (DR_REG_PMU_BASE + 0x170) /** PMU_BACKUP_SYS_CLK_NO_DIV : R/W; bitpos: [31]; default: 1; * need_des */ @@ -2582,7 +3237,7 @@ extern "C" { /** PMU_INT_RAW_REG register * need_des */ -#define PMU_INT_RAW_REG (DR_REG_PMU_BASE + 0x160) +#define PMU_INT_RAW_REG (DR_REG_PMU_BASE + 0x174) /** PMU_LP_CPU_EXC_INT_RAW : R/WTC/SS; bitpos: [27]; default: 0; * need_des */ @@ -2622,7 +3277,7 @@ extern "C" { /** PMU_HP_INT_ST_REG register * need_des */ -#define PMU_HP_INT_ST_REG (DR_REG_PMU_BASE + 0x164) +#define PMU_HP_INT_ST_REG (DR_REG_PMU_BASE + 0x178) /** PMU_LP_CPU_EXC_INT_ST : RO; bitpos: [27]; default: 0; * need_des */ @@ -2662,7 +3317,7 @@ extern "C" { /** PMU_HP_INT_ENA_REG register * need_des */ -#define PMU_HP_INT_ENA_REG (DR_REG_PMU_BASE + 0x168) +#define PMU_HP_INT_ENA_REG (DR_REG_PMU_BASE + 0x17c) /** PMU_LP_CPU_EXC_INT_ENA : R/W; bitpos: [27]; default: 0; * need_des */ @@ -2702,7 +3357,7 @@ extern "C" { /** PMU_HP_INT_CLR_REG register * need_des */ -#define PMU_HP_INT_CLR_REG (DR_REG_PMU_BASE + 0x16c) +#define PMU_HP_INT_CLR_REG (DR_REG_PMU_BASE + 0x180) /** PMU_LP_CPU_EXC_INT_CLR : WT; bitpos: [27]; default: 0; * need_des */ @@ -2742,7 +3397,7 @@ extern "C" { /** PMU_LP_INT_RAW_REG register * need_des */ -#define PMU_LP_INT_RAW_REG (DR_REG_PMU_BASE + 0x170) +#define PMU_LP_INT_RAW_REG (DR_REG_PMU_BASE + 0x184) /** PMU_LP_CPU_WAKEUP_INT_RAW : R/WTC/SS; bitpos: [20]; default: 0; * need_des */ @@ -2831,7 +3486,7 @@ extern "C" { /** PMU_LP_INT_ST_REG register * need_des */ -#define PMU_LP_INT_ST_REG (DR_REG_PMU_BASE + 0x174) +#define PMU_LP_INT_ST_REG (DR_REG_PMU_BASE + 0x188) /** PMU_LP_CPU_WAKEUP_INT_ST : RO; bitpos: [20]; default: 0; * need_des */ @@ -2920,7 +3575,7 @@ extern "C" { /** PMU_LP_INT_ENA_REG register * need_des */ -#define PMU_LP_INT_ENA_REG (DR_REG_PMU_BASE + 0x178) +#define PMU_LP_INT_ENA_REG (DR_REG_PMU_BASE + 0x18c) /** PMU_LP_CPU_WAKEUP_INT_ENA : R/W; bitpos: [20]; default: 0; * need_des */ @@ -3009,7 +3664,7 @@ extern "C" { /** PMU_LP_INT_CLR_REG register * need_des */ -#define PMU_LP_INT_CLR_REG (DR_REG_PMU_BASE + 0x17c) +#define PMU_LP_INT_CLR_REG (DR_REG_PMU_BASE + 0x190) /** PMU_LP_CPU_WAKEUP_INT_CLR : WT; bitpos: [20]; default: 0; * need_des */ @@ -3098,7 +3753,7 @@ extern "C" { /** PMU_LP_CPU_PWR0_REG register * need_des */ -#define PMU_LP_CPU_PWR0_REG (DR_REG_PMU_BASE + 0x180) +#define PMU_LP_CPU_PWR0_REG (DR_REG_PMU_BASE + 0x194) /** PMU_LP_CPU_WAITI_RDY : RO; bitpos: [0]; default: 0; * need_des */ @@ -3166,7 +3821,7 @@ extern "C" { /** PMU_LP_CPU_PWR1_REG register * need_des */ -#define PMU_LP_CPU_PWR1_REG (DR_REG_PMU_BASE + 0x184) +#define PMU_LP_CPU_PWR1_REG (DR_REG_PMU_BASE + 0x198) /** PMU_LP_CPU_WAKEUP_EN : R/W; bitpos: [15:0]; default: 0; * need_des */ @@ -3185,7 +3840,7 @@ extern "C" { /** PMU_HP_LP_CPU_COMM_REG register * need_des */ -#define PMU_HP_LP_CPU_COMM_REG (DR_REG_PMU_BASE + 0x188) +#define PMU_HP_LP_CPU_COMM_REG (DR_REG_PMU_BASE + 0x19c) /** PMU_LP_TRIGGER_HP : WT; bitpos: [30]; default: 0; * need_des */ @@ -3204,7 +3859,7 @@ extern "C" { /** PMU_HP_REGULATOR_CFG_REG register * need_des */ -#define PMU_HP_REGULATOR_CFG_REG (DR_REG_PMU_BASE + 0x18c) +#define PMU_HP_REGULATOR_CFG_REG (DR_REG_PMU_BASE + 0x1a0) /** PMU_DIG_REGULATOR_EN_CAL : R/W; bitpos: [31]; default: 0; * need_des */ @@ -3216,8 +3871,8 @@ extern "C" { /** PMU_MAIN_STATE_REG register * need_des */ -#define PMU_MAIN_STATE_REG (DR_REG_PMU_BASE + 0x190) -/** PMU_MAIN_LAST_ST_STATE : RO; bitpos: [17:11]; default: 1; +#define PMU_MAIN_STATE_REG (DR_REG_PMU_BASE + 0x1a4) +/** PMU_MAIN_LAST_ST_STATE : RO; bitpos: [17:11]; default: 256; * need_des */ #define PMU_MAIN_LAST_ST_STATE 0x0000007FU @@ -3231,7 +3886,7 @@ extern "C" { #define PMU_MAIN_TAR_ST_STATE_M (PMU_MAIN_TAR_ST_STATE_V << PMU_MAIN_TAR_ST_STATE_S) #define PMU_MAIN_TAR_ST_STATE_V 0x0000007FU #define PMU_MAIN_TAR_ST_STATE_S 18 -/** PMU_MAIN_CUR_ST_STATE : RO; bitpos: [31:25]; default: 4; +/** PMU_MAIN_CUR_ST_STATE : RO; bitpos: [31:25]; default: 1; * need_des */ #define PMU_MAIN_CUR_ST_STATE 0x0000007FU @@ -3242,7 +3897,7 @@ extern "C" { /** PMU_PWR_STATE_REG register * need_des */ -#define PMU_PWR_STATE_REG (DR_REG_PMU_BASE + 0x194) +#define PMU_PWR_STATE_REG (DR_REG_PMU_BASE + 0x1a8) /** PMU_BACKUP_ST_STATE : RO; bitpos: [17:13]; default: 1; * need_des */ @@ -3268,15 +3923,15 @@ extern "C" { /** PMU_CLK_STATE0_REG register * need_des */ -#define PMU_CLK_STATE0_REG (DR_REG_PMU_BASE + 0x198) -/** PMU_STABLE_XPD_BBPLL_STATE : RO; bitpos: [0]; default: 1; +#define PMU_CLK_STATE0_REG (DR_REG_PMU_BASE + 0x1ac) +/** PMU_STABLE_XPD_BBPLL_STATE : RO; bitpos: [0]; default: 0; * need_des */ #define PMU_STABLE_XPD_BBPLL_STATE (BIT(0)) #define PMU_STABLE_XPD_BBPLL_STATE_M (PMU_STABLE_XPD_BBPLL_STATE_V << PMU_STABLE_XPD_BBPLL_STATE_S) #define PMU_STABLE_XPD_BBPLL_STATE_V 0x00000001U #define PMU_STABLE_XPD_BBPLL_STATE_S 0 -/** PMU_STABLE_XPD_XTAL_STATE : RO; bitpos: [1]; default: 1; +/** PMU_STABLE_XPD_XTAL_STATE : RO; bitpos: [1]; default: 0; * need_des */ #define PMU_STABLE_XPD_XTAL_STATE (BIT(1)) @@ -3304,7 +3959,7 @@ extern "C" { #define PMU_SYS_CLK_NO_DIV_STATE_M (PMU_SYS_CLK_NO_DIV_STATE_V << PMU_SYS_CLK_NO_DIV_STATE_S) #define PMU_SYS_CLK_NO_DIV_STATE_V 0x00000001U #define PMU_SYS_CLK_NO_DIV_STATE_S 18 -/** PMU_ICG_SYS_CLK_EN_STATE : RO; bitpos: [19]; default: 0; +/** PMU_ICG_SYS_CLK_EN_STATE : RO; bitpos: [19]; default: 1; * need_des */ #define PMU_ICG_SYS_CLK_EN_STATE (BIT(19)) @@ -3381,7 +4036,7 @@ extern "C" { #define PMU_ANA_XPD_BBPLL_STATE_M (PMU_ANA_XPD_BBPLL_STATE_V << PMU_ANA_XPD_BBPLL_STATE_S) #define PMU_ANA_XPD_BBPLL_STATE_V 0x00000001U #define PMU_ANA_XPD_BBPLL_STATE_S 30 -/** PMU_ANA_XPD_XTAL_STATE : RO; bitpos: [31]; default: 0; +/** PMU_ANA_XPD_XTAL_STATE : RO; bitpos: [31]; default: 1; * need_des */ #define PMU_ANA_XPD_XTAL_STATE (BIT(31)) @@ -3392,7 +4047,7 @@ extern "C" { /** PMU_CLK_STATE1_REG register * need_des */ -#define PMU_CLK_STATE1_REG (DR_REG_PMU_BASE + 0x19c) +#define PMU_CLK_STATE1_REG (DR_REG_PMU_BASE + 0x1b0) /** PMU_ICG_FUNC_EN_STATE : RO; bitpos: [31:0]; default: 4294967295; * need_des */ @@ -3404,7 +4059,7 @@ extern "C" { /** PMU_CLK_STATE2_REG register * need_des */ -#define PMU_CLK_STATE2_REG (DR_REG_PMU_BASE + 0x1a0) +#define PMU_CLK_STATE2_REG (DR_REG_PMU_BASE + 0x1b4) /** PMU_ICG_APB_EN_STATE : RO; bitpos: [31:0]; default: 4294967295; * need_des */ @@ -3413,23 +4068,112 @@ extern "C" { #define PMU_ICG_APB_EN_STATE_V 0xFFFFFFFFU #define PMU_ICG_APB_EN_STATE_S 0 -/** PMU_VDD_SPI_STATUS_REG register +/** PMU_DCM_CTRL_REG register + * need_des + */ +#define PMU_DCM_CTRL_REG (DR_REG_PMU_BASE + 0x1b8) +/** PMU_DSFMOS_USE_POR : R/W; bitpos: [0]; default: 1; + * need_des + */ +#define PMU_DSFMOS_USE_POR (BIT(0)) +#define PMU_DSFMOS_USE_POR_M (PMU_DSFMOS_USE_POR_V << PMU_DSFMOS_USE_POR_S) +#define PMU_DSFMOS_USE_POR_V 0x00000001U +#define PMU_DSFMOS_USE_POR_S 0 +/** PMU_DCDC_DCM_UPDATE : WT; bitpos: [22]; default: 0; + * need_des + */ +#define PMU_DCDC_DCM_UPDATE (BIT(22)) +#define PMU_DCDC_DCM_UPDATE_M (PMU_DCDC_DCM_UPDATE_V << PMU_DCDC_DCM_UPDATE_S) +#define PMU_DCDC_DCM_UPDATE_V 0x00000001U +#define PMU_DCDC_DCM_UPDATE_S 22 +/** PMU_DCDC_PCUR_LIMIT : R/W; bitpos: [25:23]; default: 1; + * need_des + */ +#define PMU_DCDC_PCUR_LIMIT 0x00000007U +#define PMU_DCDC_PCUR_LIMIT_M (PMU_DCDC_PCUR_LIMIT_V << PMU_DCDC_PCUR_LIMIT_S) +#define PMU_DCDC_PCUR_LIMIT_V 0x00000007U +#define PMU_DCDC_PCUR_LIMIT_S 23 +/** PMU_DCDC_BIAS_CAL_DONE : RO; bitpos: [26]; default: 1; + * need_des + */ +#define PMU_DCDC_BIAS_CAL_DONE (BIT(26)) +#define PMU_DCDC_BIAS_CAL_DONE_M (PMU_DCDC_BIAS_CAL_DONE_V << PMU_DCDC_BIAS_CAL_DONE_S) +#define PMU_DCDC_BIAS_CAL_DONE_V 0x00000001U +#define PMU_DCDC_BIAS_CAL_DONE_S 26 +/** PMU_DCDC_CCM_SW_EN : R/W; bitpos: [27]; default: 0; + * need_des + */ +#define PMU_DCDC_CCM_SW_EN (BIT(27)) +#define PMU_DCDC_CCM_SW_EN_M (PMU_DCDC_CCM_SW_EN_V << PMU_DCDC_CCM_SW_EN_S) +#define PMU_DCDC_CCM_SW_EN_V 0x00000001U +#define PMU_DCDC_CCM_SW_EN_S 27 +/** PMU_DCDC_VCM_ENB : R/W; bitpos: [28]; default: 0; + * need_des + */ +#define PMU_DCDC_VCM_ENB (BIT(28)) +#define PMU_DCDC_VCM_ENB_M (PMU_DCDC_VCM_ENB_V << PMU_DCDC_VCM_ENB_S) +#define PMU_DCDC_VCM_ENB_V 0x00000001U +#define PMU_DCDC_VCM_ENB_S 28 +/** PMU_DCDC_CCM_RDY : RO; bitpos: [29]; default: 0; + * need_des + */ +#define PMU_DCDC_CCM_RDY (BIT(29)) +#define PMU_DCDC_CCM_RDY_M (PMU_DCDC_CCM_RDY_V << PMU_DCDC_CCM_RDY_S) +#define PMU_DCDC_CCM_RDY_V 0x00000001U +#define PMU_DCDC_CCM_RDY_S 29 +/** PMU_DCDC_VCM_RDY : RO; bitpos: [30]; default: 1; + * need_des + */ +#define PMU_DCDC_VCM_RDY (BIT(30)) +#define PMU_DCDC_VCM_RDY_M (PMU_DCDC_VCM_RDY_V << PMU_DCDC_VCM_RDY_S) +#define PMU_DCDC_VCM_RDY_V 0x00000001U +#define PMU_DCDC_VCM_RDY_S 30 +/** PMU_DCDC_RDY_CLR : R/W; bitpos: [31]; default: 0; + * need_des + */ +#define PMU_DCDC_RDY_CLR (BIT(31)) +#define PMU_DCDC_RDY_CLR_M (PMU_DCDC_RDY_CLR_V << PMU_DCDC_RDY_CLR_S) +#define PMU_DCDC_RDY_CLR_V 0x00000001U +#define PMU_DCDC_RDY_CLR_S 31 + +/** PMU_TOUCH_PWR_CTRL_REG register + * need_des + */ +#define PMU_TOUCH_PWR_CTRL_REG (DR_REG_PMU_BASE + 0x1bc) +/** PMU_TOUCH_SLEEP_CYCLES : R/W; bitpos: [15:0]; default: 0; + * need_des + */ +#define PMU_TOUCH_SLEEP_CYCLES 0x0000FFFFU +#define PMU_TOUCH_SLEEP_CYCLES_M (PMU_TOUCH_SLEEP_CYCLES_V << PMU_TOUCH_SLEEP_CYCLES_S) +#define PMU_TOUCH_SLEEP_CYCLES_V 0x0000FFFFU +#define PMU_TOUCH_SLEEP_CYCLES_S 0 +/** PMU_TOUCH_WAIT_CYCLES : R/W; bitpos: [29:21]; default: 0; + * need_des + */ +#define PMU_TOUCH_WAIT_CYCLES 0x000001FFU +#define PMU_TOUCH_WAIT_CYCLES_M (PMU_TOUCH_WAIT_CYCLES_V << PMU_TOUCH_WAIT_CYCLES_S) +#define PMU_TOUCH_WAIT_CYCLES_V 0x000001FFU +#define PMU_TOUCH_WAIT_CYCLES_S 21 +/** PMU_TOUCH_SLEEP_TIMER_EN : R/W; bitpos: [30]; default: 0; * need_des */ -#define PMU_VDD_SPI_STATUS_REG (DR_REG_PMU_BASE + 0x1a4) -/** PMU_STABLE_VDD_SPI_PWR_DRV : RO; bitpos: [31]; default: 0; +#define PMU_TOUCH_SLEEP_TIMER_EN (BIT(30)) +#define PMU_TOUCH_SLEEP_TIMER_EN_M (PMU_TOUCH_SLEEP_TIMER_EN_V << PMU_TOUCH_SLEEP_TIMER_EN_S) +#define PMU_TOUCH_SLEEP_TIMER_EN_V 0x00000001U +#define PMU_TOUCH_SLEEP_TIMER_EN_S 30 +/** PMU_TOUCH_FORCE_DONE : R/W; bitpos: [31]; default: 0; * need_des */ -#define PMU_STABLE_VDD_SPI_PWR_DRV (BIT(31)) -#define PMU_STABLE_VDD_SPI_PWR_DRV_M (PMU_STABLE_VDD_SPI_PWR_DRV_V << PMU_STABLE_VDD_SPI_PWR_DRV_S) -#define PMU_STABLE_VDD_SPI_PWR_DRV_V 0x00000001U -#define PMU_STABLE_VDD_SPI_PWR_DRV_S 31 +#define PMU_TOUCH_FORCE_DONE (BIT(31)) +#define PMU_TOUCH_FORCE_DONE_M (PMU_TOUCH_FORCE_DONE_V << PMU_TOUCH_FORCE_DONE_S) +#define PMU_TOUCH_FORCE_DONE_V 0x00000001U +#define PMU_TOUCH_FORCE_DONE_S 31 /** PMU_DATE_REG register * need_des */ #define PMU_DATE_REG (DR_REG_PMU_BASE + 0x3fc) -/** PMU_PMU_DATE : R/W; bitpos: [30:0]; default: 35688960; +/** PMU_PMU_DATE : R/W; bitpos: [30:0]; default: 37814400; * need_des */ #define PMU_PMU_DATE 0x7FFFFFFFU diff --git a/components/soc/esp32h21/register/soc/pmu_struct.h b/components/soc/esp32h21/register/soc/pmu_struct.h index 178613d23b7..06a55454bcf 100644 --- a/components/soc/esp32h21/register/soc/pmu_struct.h +++ b/components/soc/esp32h21/register/soc/pmu_struct.h @@ -6,36 +6,46 @@ #pragma once #include -#include "soc/pmu_reg.h" +#include #ifdef __cplusplus -extern "C" { +extern "C" +{ #endif -typedef union { - struct { - uint32_t reserved0 : 21; - uint32_t vdd_spi_pd_en: 1; - uint32_t mem_dslp : 1; - uint32_t mem_pd_en : 4; - uint32_t wifi_pd_en : 1; - uint32_t reserved1 : 1; - uint32_t cpu_pd_en : 1; - uint32_t aon_pd_en : 1; - uint32_t top_pd_en : 1; +#include "soc.h" +#include "soc/pmu_reg.h" + +typedef union +{ + struct + { + uint32_t reserved0 : 18; + uint32_t vdd_flash_mode: 4; + uint32_t mem_dslp : 1; + uint32_t mem_pd_en : 4; + uint32_t wifi_pd_en : 1; + uint32_t peri_pd_en : 1; + uint32_t cpu_pd_en : 1; + uint32_t aon_pd_en : 1; + uint32_t top_pd_en : 1; }; uint32_t val; } pmu_hp_dig_power_reg_t; -typedef union { - struct { +typedef union +{ + struct + { uint32_t reserved0: 30; uint32_t code : 2; }; uint32_t val; } pmu_hp_icg_modem_reg_t; -typedef union { - struct { +typedef union +{ + struct + { uint32_t reserved0 : 24; uint32_t uart_wakeup_en : 1; uint32_t lp_pad_hold_all: 1; @@ -48,8 +58,10 @@ typedef union { uint32_t val; } pmu_hp_sys_cntl_reg_t; -typedef union { - struct { +typedef union +{ + struct + { uint32_t reserved0 : 26; uint32_t i2c_iso_en : 1; uint32_t i2c_retention: 1; @@ -61,75 +73,76 @@ typedef union { uint32_t val; } pmu_hp_clk_power_reg_t; -typedef union { - struct { - uint32_t reserved0 : 24; - uint32_t xpd_trx : 1; - uint32_t xpd_bias : 1; - uint32_t reserved1 : 4; - uint32_t pd_cur : 1; - uint32_t bias_sleep: 1; +typedef union +{ + struct + { + uint32_t reserved0 : 9; + uint32_t dcdc_ccm_enb : 1; + uint32_t dcdc_clear_rdy : 1; + uint32_t dig_reg_dpcur_bias: 2; + uint32_t dig_reg_dsfmos : 4; + uint32_t dcm_vset : 5; + uint32_t dcm_mode : 2; + uint32_t xpd_trx : 1; + uint32_t xpd_bias : 1; + uint32_t reserved1 : 3; + uint32_t discnnt_dig_rtc : 1; + uint32_t pd_cur : 1; + uint32_t bias_sleep : 1; }; uint32_t val; } pmu_hp_bias_reg_t; -typedef union { - struct { /* HP: Active State */ +typedef union +{ + struct + { /* HP: Active State */ uint32_t reserved0 : 4; uint32_t hp_sleep2active_backup_modem_clk_code: 2; uint32_t hp_modem2active_backup_modem_clk_code: 2; - uint32_t reserved1 : 2; - uint32_t hp_active_retention_mode : 1; - uint32_t hp_sleep2active_retention_en : 1; - uint32_t hp_modem2active_retention_en : 1; - uint32_t reserved2 : 1; + uint32_t reserved1 : 6; uint32_t hp_sleep2active_backup_clk_sel : 2; uint32_t hp_modem2active_backup_clk_sel : 2; - uint32_t reserved3 : 2; - uint32_t hp_sleep2active_backup_mode : 3; - uint32_t hp_modem2active_backup_mode : 3; - uint32_t reserved4 : 3; + uint32_t hp_sleep2active_backup_mode : 5; + uint32_t hp_modem2active_backup_mode : 5; + uint32_t reserved2 : 1; uint32_t hp_sleep2active_backup_en : 1; uint32_t hp_modem2active_backup_en : 1; - uint32_t reserved5 : 1; - }; - struct { /* HP: Modem State */ - uint32_t reserved6 : 4; - uint32_t hp_sleep2modem_backup_modem_clk_code : 2; - uint32_t reserved7 : 4; - uint32_t hp_modem_retention_mode : 1; - uint32_t hp_sleep2modem_retention_en : 1; - uint32_t reserved8 : 2; - uint32_t hp_sleep2modem_backup_clk_sel : 2; - uint32_t reserved9 : 4; - uint32_t hp_sleep2modem_backup_mode : 3; - uint32_t reserved10 : 6; - uint32_t hp_sleep2modem_backup_en : 1; - uint32_t reserved11 : 2; - }; - struct { /* HP: Sleep State */ - uint32_t reserved12 : 6; + uint32_t reserved3 : 1; + }; + struct + { /* HP: Modem State */ + uint32_t reserved4 : 4; + uint32_t hp_sleep2modem_backup_modem_clk_code: 2; + uint32_t reserved5 : 8; + uint32_t hp_sleep2modem_backup_clk_sel : 2; + uint32_t reserved6 : 4; + uint32_t hp_sleep2modem_backup_mode : 5; + uint32_t reserved7 : 4; + uint32_t hp_sleep2modem_backup_en : 1; + uint32_t reserved8 : 2; + }; + struct + { /* HP: Sleep State */ + uint32_t reserved9 : 6; uint32_t hp_modem2sleep_backup_modem_clk_code : 2; uint32_t hp_active2sleep_backup_modem_clk_code: 2; - uint32_t hp_sleep_retention_mode : 1; - uint32_t reserved13 : 1; - uint32_t hp_modem2sleep_retention_en : 1; - uint32_t hp_active2sleep_retention_en : 1; - uint32_t reserved14 : 2; + uint32_t reserved10 : 6; uint32_t hp_modem2sleep_backup_clk_sel : 2; uint32_t hp_active2sleep_backup_clk_sel : 2; - uint32_t reserved15 : 3; - uint32_t hp_modem2sleep_backup_mode : 3; - uint32_t hp_active2sleep_backup_mode : 3; - uint32_t reserved16 : 1; + uint32_t hp_modem2sleep_backup_mode : 5; + uint32_t hp_active2sleep_backup_mode : 5; uint32_t hp_modem2sleep_backup_en : 1; uint32_t hp_active2sleep_backup_en : 1; }; uint32_t val; } pmu_hp_backup_reg_t; -typedef union { - struct { +typedef union +{ + struct + { uint32_t reserved0 : 26; uint32_t dig_sysclk_nodiv: 1; uint32_t icg_sysclk_en : 1; @@ -140,97 +153,116 @@ typedef union { uint32_t val; } pmu_hp_sysclk_reg_t; -typedef union { - struct { - uint32_t power_det_bypass : 1; - uint32_t reserved0 : 3; /* Only HP_ACTIVE modem under hp system is valid */ - uint32_t lp_dbias_vol : 5; /* Only HP_ACTIVE modem under hp system is valid */ - uint32_t hp_dbias_vol : 5; /* Only HP_ACTIVE modem under hp system is valid */ - uint32_t dbias_sel : 1; /* Only HP_ACTIVE modem under hp system is valid */ - uint32_t dbias_init : 1; /* Only HP_ACTIVE modem under hp system is valid */ - uint32_t slp_mem_xpd : 1; - uint32_t slp_logic_xpd : 1; - uint32_t xpd : 1; - uint32_t slp_mem_dbias : 4; - uint32_t slp_logic_dbias : 4; - uint32_t dbias : 5; +typedef union +{ + struct + { + uint32_t power_det_bypass: 1; + uint32_t reserved0 : 3; + uint32_t lp_dbias_vol : 5; /* Only HP_ACTIVE mode under hp system is valid */ + uint32_t hp_dbias_vol : 5; /* Only HP_ACTIVE mode under hp system is valid */ + uint32_t dbias_sel : 1; /* Only HP_ACTIVE mode under hp system is valid */ + uint32_t dbias_init : 1; /* Only HP_ACTIVE mode under hp system is valid */ + uint32_t slp_mem_xpd : 1; + uint32_t slp_logic_xpd : 1; + uint32_t xpd : 1; + uint32_t slp_mem_dbias : 4; + uint32_t slp_logic_dbias : 4; + uint32_t dbias : 5; }; uint32_t val; } pmu_hp_regulator0_reg_t; -typedef union { - struct { +typedef union +{ + struct + { uint32_t reserved0: 8; uint32_t drv_b : 24; }; uint32_t val; } pmu_hp_regulator1_reg_t; -typedef union { - struct { - uint32_t reserved0: 31; - uint32_t xpd_xtal : 1; +typedef union +{ + struct + { + uint32_t reserved0 : 30; + uint32_t xpd_xtalx2: 1; + uint32_t xpd_xtal : 1; }; uint32_t val; } pmu_hp_xtal_reg_t; -typedef struct pmu_hp_hw_regmap_t{ - pmu_hp_dig_power_reg_t dig_power; - uint32_t icg_func; - uint32_t icg_apb; - pmu_hp_icg_modem_reg_t icg_modem; - pmu_hp_sys_cntl_reg_t syscntl; - pmu_hp_clk_power_reg_t clk_power; - pmu_hp_bias_reg_t bias; - pmu_hp_backup_reg_t backup; - uint32_t backup_clk; - pmu_hp_sysclk_reg_t sysclk; - pmu_hp_regulator0_reg_t regulator0; - pmu_hp_regulator1_reg_t regulator1; - pmu_hp_xtal_reg_t xtal; +typedef struct pmu_hp_hw_regmap_t +{ + pmu_hp_dig_power_reg_t dig_power; + uint32_t icg_func; + uint32_t icg_apb; + pmu_hp_icg_modem_reg_t icg_modem; + pmu_hp_sys_cntl_reg_t syscntl; + pmu_hp_clk_power_reg_t clk_power; + pmu_hp_bias_reg_t bias; + pmu_hp_backup_reg_t backup; + uint32_t backup_clk; + pmu_hp_sysclk_reg_t sysclk; + pmu_hp_regulator0_reg_t regulator0; + pmu_hp_regulator1_reg_t regulator1; + pmu_hp_xtal_reg_t xtal; } pmu_hp_hw_regmap_t; -/** */ -typedef union { - struct { +typedef union +{ + struct + { uint32_t reserved0: 21; uint32_t slp_xpd : 1; - uint32_t xpd : 1; + uint32_t xpd : 1; uint32_t slp_dbias: 4; uint32_t dbias : 5; }; uint32_t val; } pmu_lp_regulator0_reg_t; -typedef union { - struct { +typedef union +{ + struct + { uint32_t reserved0: 28; uint32_t drv_b : 4; }; uint32_t val; } pmu_lp_regulator1_reg_t; -typedef union { - struct { - uint32_t reserved0: 31; - uint32_t xpd_xtal : 1; +typedef union +{ + struct + { + uint32_t reserved0 : 30; + uint32_t xpd_xtalx2: 1; + uint32_t xpd_xtal : 1; }; uint32_t val; } pmu_lp_xtal_reg_t; -typedef union { - struct { - uint32_t reserved0 : 27; - uint32_t bod_source_sel : 1; - uint32_t vddbat_mode : 2; - uint32_t mem_dslp : 1; - uint32_t peri_pd_en : 1; +typedef union +{ + struct + { + uint32_t reserved0 : 23; + uint32_t vdd_io_mode : 4; + uint32_t bod_source_sel: 1; + uint32_t vddbat_mode : 2; + uint32_t mem_dslp : 1; + uint32_t peri_pd_en : 1; }; uint32_t val; } pmu_lp_dig_power_reg_t; -typedef union { - struct { +typedef union +{ + struct + { uint32_t reserved0 : 27; uint32_t xpd_lppll : 1; uint32_t xpd_xtal32k: 1; @@ -241,50 +273,68 @@ typedef union { uint32_t val; } pmu_lp_clk_power_reg_t; -typedef union { - struct { - uint32_t reserved0 : 25; - uint32_t xpd_bias : 1; - uint32_t reserved1 : 4; - uint32_t pd_cur : 1; - uint32_t bias_sleep: 1; +typedef union +{ + struct + { + uint32_t reserved0 : 9; + uint32_t dcdc_ccm_enb : 1; + uint32_t dcdc_clear_rdy : 1; + uint32_t dig_reg_dpcur_bias: 2; + uint32_t dig_reg_dsfmos : 4; + uint32_t dcm_vset : 5; + uint32_t dcm_mode : 2; + uint32_t reserved1 : 1; + uint32_t xpd_bias : 1; + uint32_t reserved2 : 3; + uint32_t discnnt_dig_rtc : 1; + uint32_t pd_cur : 1; + uint32_t bias_sleep : 1; }; uint32_t val; } pmu_lp_bias_reg_t; -typedef struct pmu_lp_hw_regmap_t{ - pmu_lp_regulator0_reg_t regulator0; - pmu_lp_regulator1_reg_t regulator1; - pmu_lp_xtal_reg_t xtal; /* Only LP_SLEEP mode under lp system is valid */ - pmu_lp_dig_power_reg_t dig_power; - pmu_lp_clk_power_reg_t clk_power; - pmu_lp_bias_reg_t bias; /* Only LP_SLEEP mode under lp system is valid */ +typedef struct pmu_lp_hw_regmap_t +{ + pmu_lp_regulator0_reg_t regulator0; + pmu_lp_regulator1_reg_t regulator1; + pmu_lp_xtal_reg_t xtal; /* Only LP_SLEEP mode under lp system, xtal is valid */ + pmu_lp_dig_power_reg_t dig_power; + pmu_lp_clk_power_reg_t clk_power; + pmu_lp_bias_reg_t bias; /* Only LP_SLEEP mode under lp system, bias is valid */ } pmu_lp_hw_regmap_t; - -typedef union { - struct { - uint32_t tie_low_global_bbpll_icg : 1; - uint32_t tie_low_global_xtal_icg : 1; - uint32_t tie_low_i2c_retention : 1; - uint32_t tie_low_xpd_bb_i2c : 1; - uint32_t tie_low_xpd_bbpll_i2c : 1; - uint32_t tie_low_xpd_bbpll : 1; - uint32_t tie_low_xpd_xtal : 1; - uint32_t reserved0 : 18; - uint32_t tie_high_global_bbpll_icg: 1; - uint32_t tie_high_global_xtal_icg : 1; - uint32_t tie_high_i2c_retention : 1; - uint32_t tie_high_xpd_bb_i2c : 1; - uint32_t tie_high_xpd_bbpll_i2c : 1; - uint32_t tie_high_xpd_bbpll : 1; - uint32_t tie_high_xpd_xtal : 1; +typedef union +{ + struct + { + uint32_t tie_low_global_bbpll_icg : 1; + uint32_t tie_low_global_xtal_icg : 1; + uint32_t tie_low_i2c_retention : 1; + uint32_t tie_low_xpd_bb_i2c : 1; + uint32_t tie_low_xpd_bbpll_i2c : 1; + uint32_t tie_low_xpd_bbpll : 1; + uint32_t tie_low_xpd_xtal : 1; + uint32_t tie_low_global_xtalx2_icg : 1; + uint32_t tie_low_xpd_xtalx2 : 1; + uint32_t reserved0 : 14; + uint32_t tie_high_xtalx2 : 1; + uint32_t tie_high_global_xtalx2_icg: 1; + uint32_t tie_high_global_bbpll_icg : 1; + uint32_t tie_high_global_xtal_icg : 1; + uint32_t tie_high_i2c_retention : 1; + uint32_t tie_high_xpd_bb_i2c : 1; + uint32_t tie_high_xpd_bbpll_i2c : 1; + uint32_t tie_high_xpd_bbpll : 1; + uint32_t tie_high_xpd_xtal : 1; }; uint32_t val; } pmu_imm_hp_clk_power_reg_t; -typedef union { - struct { +typedef union +{ + struct + { uint32_t reserved0 : 28; uint32_t update_dig_icg_switch: 1; uint32_t tie_low_icg_slp_sel : 1; @@ -294,32 +344,40 @@ typedef union { uint32_t val; } pmu_imm_sleep_sysclk_reg_t; -typedef union { - struct { +typedef union +{ + struct + { uint32_t reserved0 : 31; uint32_t update_dig_icg_func_en: 1; }; uint32_t val; } pmu_imm_hp_func_icg_reg_t; -typedef union { - struct { +typedef union +{ + struct + { uint32_t reserved0 : 31; uint32_t update_dig_icg_apb_en: 1; }; uint32_t val; } pmu_imm_hp_apb_icg_reg_t; -typedef union { - struct { +typedef union +{ + struct + { uint32_t reserved0 : 31; uint32_t update_dig_icg_modem_en: 1; }; uint32_t val; } pmu_imm_modem_icg_reg_t; -typedef union { - struct { +typedef union +{ + struct + { uint32_t reserved0 : 30; uint32_t tie_low_lp_rootclk_sel : 1; uint32_t tie_high_lp_rootclk_sel: 1; @@ -327,9 +385,13 @@ typedef union { uint32_t val; } pmu_imm_lp_icg_reg_t; -typedef union { - struct { - uint32_t reserved0 : 28; +typedef union +{ + struct + { + uint32_t reserved0 : 26; + uint32_t tie_high_dig_pad_slp_sel: 1; + uint32_t tie_low_dig_pad_slp_sel : 1; uint32_t tie_high_lp_pad_hold_all: 1; uint32_t tie_low_lp_pad_hold_all : 1; uint32_t tie_high_hp_pad_hold_all: 1; @@ -338,8 +400,10 @@ typedef union { uint32_t val; } pmu_imm_pad_hold_all_reg_t; -typedef union { - struct { +typedef union +{ + struct + { uint32_t reserved0 : 30; uint32_t tie_high_i2c_iso_en: 1; uint32_t tie_low_i2c_iso_en : 1; @@ -347,19 +411,22 @@ typedef union { uint32_t val; } pmu_imm_i2c_isolate_reg_t; -typedef struct pmu_imm_hw_regmap_t{ - pmu_imm_hp_clk_power_reg_t clk_power; - pmu_imm_sleep_sysclk_reg_t sleep_sysclk; - pmu_imm_hp_func_icg_reg_t hp_func_icg; - pmu_imm_hp_apb_icg_reg_t hp_apb_icg; - pmu_imm_modem_icg_reg_t modem_icg; - pmu_imm_lp_icg_reg_t lp_icg; - pmu_imm_pad_hold_all_reg_t pad_hold_all; - pmu_imm_i2c_isolate_reg_t i2c_iso; +typedef struct pmu_imm_hw_regmap_t +{ + pmu_imm_hp_clk_power_reg_t clk_power; + pmu_imm_sleep_sysclk_reg_t sleep_sysclk; + pmu_imm_hp_func_icg_reg_t hp_func_icg; + pmu_imm_hp_apb_icg_reg_t hp_apb_icg; + pmu_imm_modem_icg_reg_t modem_icg; + pmu_imm_lp_icg_reg_t lp_icg; + pmu_imm_pad_hold_all_reg_t pad_hold_all; + pmu_imm_i2c_isolate_reg_t i2c_iso; } pmu_imm_hw_regmap_t; -typedef union { - struct { +typedef union +{ + struct + { uint32_t reserved0 : 5; uint32_t powerdown_timer: 9; uint32_t powerup_timer : 9; @@ -368,8 +435,10 @@ typedef union { uint32_t val; } pmu_power_wait_timer0_reg_t; -typedef union { - struct { +typedef union +{ + struct + { uint32_t reserved0 : 9; uint32_t powerdown_timer: 7; uint32_t powerup_timer : 7; @@ -378,23 +447,39 @@ typedef union { uint32_t val; } pmu_power_wait_timer1_reg_t; -typedef union { - struct { +typedef union +{ + struct + { + uint32_t lp_iso_wait_timer : 8; + uint32_t lp_rst_wait_timer : 8; + uint32_t hp_iso_wait_timer : 8; + uint32_t hp_rst_wait_timer : 8; + }; + uint32_t val; +} pmu_power_wait_timer2_reg_t; + +typedef union +{ + struct + { uint32_t force_reset : 1; uint32_t force_iso : 1; uint32_t force_pu : 1; uint32_t force_no_reset: 1; uint32_t force_no_iso : 1; uint32_t force_pd : 1; - uint32_t mask : 5; /* Invalid of lp peripherals */ - uint32_t reserved0 : 16; /* Invalid of lp peripherals */ - uint32_t pd_mask : 5; /* Invalid of lp peripherals */ + uint32_t mask : 5; /* Invalid of lp peripherals */ + uint32_t reserved0 : 16; /* Invalid of lp peripherals */ + uint32_t pd_mask : 5; /* Invalid of lp peripherals */ }; uint32_t val; } pmu_power_domain_cntl_reg_t; -typedef union { - struct { +typedef union +{ + struct + { uint32_t force_hp_mem_iso : 4; uint32_t force_hp_mem_pd : 4; uint32_t reserved0 : 16; @@ -404,8 +489,10 @@ typedef union { uint32_t val; } pmu_power_memory_cntl_reg_t; -typedef union { - struct { +typedef union +{ + struct + { uint32_t mem2_pd_mask: 5; uint32_t mem1_pd_mask: 5; uint32_t mem0_pd_mask: 5; @@ -417,8 +504,10 @@ typedef union { uint32_t val; } pmu_power_memory_mask_reg_t; -typedef union { - struct { +typedef union +{ + struct + { uint32_t force_hp_pad_no_iso_all: 1; uint32_t force_hp_pad_iso_all : 1; uint32_t reserved0 : 30; @@ -426,54 +515,128 @@ typedef union { uint32_t val; } pmu_power_hp_pad_reg_t; -typedef union { - struct { - uint32_t reserved0 : 18; - uint32_t pwr_wait : 11; - uint32_t pwr_sw : 2; - uint32_t pwr_sel_sw: 1; - }; - uint32_t val; -} pmu_power_vdd_spi_cntl_reg_t; - -typedef union { - struct { +typedef union +{ + struct + { + uint32_t ldo_rdy : 1; + uint32_t sw_en_xpd : 1; + uint32_t sw_en_through : 1; + uint32_t sw_en_standby : 1; + uint32_t sw_en_power_adjust: 1; + uint32_t sw_en_endet : 1; + uint32_t reserved0 : 16; + uint32_t bypass_ldo_rdy : 1; + uint32_t xpd : 1; + uint32_t through : 1; + uint32_t standby : 1; + uint32_t power_adjust : 5; + uint32_t endet : 1; + }; + uint32_t val; +} pmu_power_flash_ldo_reg_t; + +typedef union +{ + struct + { + uint32_t reserved0 : 22; + uint32_t ldo_sw_en_tiel : 1; + uint32_t ldo_power_sel : 1; + uint32_t ldo_sw_en_power_sel: 1; + uint32_t ldo_wait_target : 4; + uint32_t ldo_tiel_en : 1; + uint32_t ldo_tiel : 1; + uint32_t ldo_sw_update : 1; + }; + uint32_t val; +} pmu_power_vdd_flash_reg_t; + +typedef union +{ + struct + { + uint32_t ldo_rdy : 1; + uint32_t sw_en_xpd : 1; + uint32_t reserved0 : 1; + uint32_t sw_en_through : 1; + uint32_t sw_en_standby : 1; + uint32_t sw_en_power_adjust: 1; + uint32_t sw_en_endet : 1; + uint32_t reserved1 : 15; + uint32_t bypass_ldo_rdy : 1; + uint32_t xpd : 1; + uint32_t through : 1; + uint32_t standby : 1; + uint32_t power_adjust : 5; + uint32_t endet : 1; + }; + uint32_t val; +} pmu_power_io_ldo_reg_t; + +typedef union +{ + struct + { + uint32_t reserved0 : 23; + uint32_t ldo_power_sel : 1; + uint32_t ldo_sw_en_power_sel: 1; + uint32_t reserved1 : 7; + }; + uint32_t val; +} pmu_power_vdd_io_reg_t; + +typedef union +{ + struct + { uint32_t wait_xtal_stable: 16; uint32_t wait_pll_stable : 16; }; uint32_t val; } pmu_power_clk_wait_cntl_reg_t; -typedef struct pmu_power_hw_regmap_t{ - pmu_power_wait_timer0_reg_t wait_timer0; - pmu_power_wait_timer1_reg_t wait_timer1; - pmu_power_domain_cntl_reg_t hp_pd[5]; - pmu_power_domain_cntl_reg_t lp_peri; - pmu_power_memory_cntl_reg_t mem_cntl; - pmu_power_memory_mask_reg_t mem_mask; - pmu_power_hp_pad_reg_t hp_pad; - pmu_power_vdd_spi_cntl_reg_t vdd_spi; - pmu_power_clk_wait_cntl_reg_t clk_wait; +typedef struct pmu_power_hw_regmap_t +{ + pmu_power_wait_timer0_reg_t wait_timer0; + pmu_power_wait_timer1_reg_t wait_timer1; + pmu_power_wait_timer2_reg_t wait_timer2; + pmu_power_domain_cntl_reg_t hp_pd[5]; /* for TOP, HPAON, HPCPU, HPPERI and HPWIFI domain power controller */ + pmu_power_domain_cntl_reg_t lp_peri; + pmu_power_memory_cntl_reg_t mem_cntl; + pmu_power_memory_mask_reg_t mem_mask; + pmu_power_hp_pad_reg_t hp_pad; + pmu_power_flash_ldo_reg_t flash_ldo[2]; + pmu_power_vdd_flash_reg_t vdd_flash; + pmu_power_io_ldo_reg_t io_ldo; + pmu_power_vdd_io_reg_t vdd_io; + pmu_power_clk_wait_cntl_reg_t clk_wait; } pmu_power_hw_regmap_t; -typedef union { - struct { +typedef union +{ + struct + { uint32_t reserved0: 31; uint32_t sleep_req: 1; }; uint32_t val; } pmu_slp_wakeup_cntl0_reg_t; -typedef union { - struct { +typedef union +{ + struct + { uint32_t sleep_reject_ena: 31; uint32_t slp_reject_en : 1; }; uint32_t val; } pmu_slp_wakeup_cntl1_reg_t; -typedef union { - struct { +typedef union +{ + struct + { uint32_t lp_min_slp_val: 8; uint32_t hp_min_slp_val: 8; uint32_t sleep_prt_sel : 2; @@ -482,16 +645,20 @@ typedef union { uint32_t val; } pmu_slp_wakeup_cntl3_reg_t; -typedef union { - struct { +typedef union +{ + struct + { uint32_t reserved0 : 31; uint32_t slp_reject_cause_clr: 1; }; uint32_t val; } pmu_slp_wakeup_cntl4_reg_t; -typedef union { - struct { +typedef union +{ + struct + { uint32_t modem_wait_target : 20; uint32_t reserved0 : 4; uint32_t lp_ana_wait_target: 8; @@ -499,8 +666,10 @@ typedef union { uint32_t val; } pmu_slp_wakeup_cntl5_reg_t; -typedef union { - struct { +typedef union +{ + struct + { uint32_t soc_wakeup_wait : 20; uint32_t reserved0 : 10; uint32_t soc_wakeup_wait_cfg: 2; @@ -508,37 +677,45 @@ typedef union { uint32_t val; } pmu_slp_wakeup_cntl6_reg_t; -typedef union { - struct { - uint32_t reserved0 : 16; - uint32_t ana_wait_target: 16; +typedef union +{ + struct + { + uint32_t reserved0 : 15; + uint32_t ana_wait_clk_sel: 1; + uint32_t ana_wait_target : 16; }; uint32_t val; } pmu_slp_wakeup_cntl7_reg_t; -typedef struct pmu_wakeup_hw_regmap_t{ - pmu_slp_wakeup_cntl0_reg_t cntl0; - pmu_slp_wakeup_cntl1_reg_t cntl1; - uint32_t cntl2; - pmu_slp_wakeup_cntl3_reg_t cntl3; - pmu_slp_wakeup_cntl4_reg_t cntl4; - pmu_slp_wakeup_cntl5_reg_t cntl5; - pmu_slp_wakeup_cntl6_reg_t cntl6; - pmu_slp_wakeup_cntl7_reg_t cntl7; - uint32_t status0; - uint32_t status1; +typedef struct pmu_wakeup_hw_regmap_t +{ + pmu_slp_wakeup_cntl0_reg_t cntl0; + pmu_slp_wakeup_cntl1_reg_t cntl1; + uint32_t cntl2; + pmu_slp_wakeup_cntl3_reg_t cntl3; + pmu_slp_wakeup_cntl4_reg_t cntl4; + pmu_slp_wakeup_cntl5_reg_t cntl5; + pmu_slp_wakeup_cntl6_reg_t cntl6; + pmu_slp_wakeup_cntl7_reg_t cntl7; + uint32_t status0; + uint32_t status1; } pmu_wakeup_hw_regmap_t; -typedef union { - struct { +typedef union +{ + struct + { uint32_t i2c_por_wait_target: 8; uint32_t reserved0 : 24; }; uint32_t val; } pmu_hp_clk_poweron_reg_t; -typedef union { - struct { +typedef union +{ + struct + { uint32_t modify_icg_cntl_wait: 8; uint32_t switch_icg_cntl_wait: 8; uint32_t reserved0 : 16; @@ -546,17 +723,22 @@ typedef union { uint32_t val; } pmu_hp_clk_cntl_reg_t; -typedef union { - struct { +typedef union +{ + struct + { uint32_t reserved0: 31; uint32_t por_done : 1; }; uint32_t val; } pmu_por_status_reg_t; -typedef union { - struct { - uint32_t reserved0 : 27; +typedef union +{ + struct + { + uint32_t reserved0 : 26; + uint32_t xpd_force_rftx : 1; uint32_t xpd_perif_i2c : 1; uint32_t xpd_rftx_i2c : 1; uint32_t xpd_rfrx_i2c : 1; @@ -566,57 +748,66 @@ typedef union { uint32_t val; } pmu_rf_pwc_reg_t; -typedef union { - struct { - uint32_t ana_vddbat_mode : 2; - uint32_t reserved2 : 29; - uint32_t vddbat_sw_update : 1; +typedef union +{ + struct + { + uint32_t vddbat_mode : 2; + uint32_t reserved0 : 29; + uint32_t vddbat_sw_update: 1; }; uint32_t val; } pmu_vddbat_cfg_reg_t; -typedef union { - struct { +typedef union +{ + struct + { uint32_t reserved0 : 31; uint32_t backup_sysclk_nodiv: 1; }; uint32_t val; } pmu_backup_cfg_reg_t; -typedef union { - struct { - uint32_t reserved0 : 27; - uint32_t lp_exception: 1; - uint32_t sdio_idle: 1; - uint32_t sw : 1; - uint32_t reject : 1; - uint32_t wakeup : 1; +typedef union +{ + struct + { + uint32_t reserved0 : 27; + uint32_t lp_cpu_exc : 1; + uint32_t sdio_idle : 1; + uint32_t sw : 1; + uint32_t soc_sleep_reject: 1; + uint32_t soc_wakeup : 1; }; uint32_t val; } pmu_hp_intr_reg_t; -typedef struct pmu_hp_ext_hw_regmap_t{ - pmu_hp_clk_poweron_reg_t clk_poweron; - pmu_hp_clk_cntl_reg_t clk_cntl; - pmu_por_status_reg_t por_status; - pmu_rf_pwc_reg_t rf_pwc; - pmu_vddbat_cfg_reg_t vddbat_cfg; - pmu_backup_cfg_reg_t backup_cfg; - pmu_hp_intr_reg_t int_raw; - pmu_hp_intr_reg_t int_st; - pmu_hp_intr_reg_t int_ena; - pmu_hp_intr_reg_t int_clr; +typedef struct pmu_hp_ext_hw_regmap_t +{ + pmu_hp_clk_poweron_reg_t clk_poweron; + pmu_hp_clk_cntl_reg_t clk_cntl; + pmu_por_status_reg_t por_status; + pmu_rf_pwc_reg_t rf_pwc; + pmu_vddbat_cfg_reg_t vddbat_cfg; + pmu_backup_cfg_reg_t backup_cfg; + pmu_hp_intr_reg_t int_raw; + pmu_hp_intr_reg_t int_st; + pmu_hp_intr_reg_t int_ena; + pmu_hp_intr_reg_t int_clr; } pmu_hp_ext_hw_regmap_t; -typedef union { - struct { +typedef union +{ + struct + { uint32_t reserved0 : 20; - uint32_t lp_wakeup : 1; + uint32_t lp_cpu_wakeup : 1; uint32_t modem_switch_active_end : 1; uint32_t sleep_switch_active_end : 1; uint32_t sleep_switch_modem_end : 1; uint32_t modem_switch_sleep_end : 1; - uint32_t active_switch_sleep_end : 1; + uint32_t active_swtich_sleep_end : 1; uint32_t modem_switch_active_start: 1; uint32_t sleep_switch_active_start: 1; uint32_t sleep_switch_modem_start : 1; @@ -627,8 +818,10 @@ typedef union { uint32_t val; } pmu_lp_intr_reg_t; -typedef union { - struct { +typedef union +{ + struct + { uint32_t waiti_rdy : 1; uint32_t stall_rdy : 1; uint32_t reserved0 : 16; @@ -643,8 +836,10 @@ typedef union { uint32_t val; } pmu_lp_cpu_pwr0_reg_t; -typedef union { - struct { +typedef union +{ + struct + { uint32_t wakeup_en: 16; uint32_t reserved0: 15; uint32_t sleep_req: 1; @@ -652,21 +847,136 @@ typedef union { uint32_t val; } pmu_lp_cpu_pwr1_reg_t; -typedef struct pmu_lp_ext_hw_regmap_t{ - pmu_lp_intr_reg_t int_raw; - pmu_lp_intr_reg_t int_st; - pmu_lp_intr_reg_t int_ena; - pmu_lp_intr_reg_t int_clr; - pmu_lp_cpu_pwr0_reg_t pwr0; - pmu_lp_cpu_pwr1_reg_t pwr1; +typedef struct pmu_lp_ext_hw_regmap_t +{ + pmu_lp_intr_reg_t int_raw; + pmu_lp_intr_reg_t int_st; + pmu_lp_intr_reg_t int_ena; + pmu_lp_intr_reg_t int_clr; + pmu_lp_cpu_pwr0_reg_t pwr0; + pmu_lp_cpu_pwr1_reg_t pwr1; } pmu_lp_ext_hw_regmap_t; -typedef struct { - volatile struct { - } common; -} pmu_hp_lp_hw_regmap_t; +typedef union +{ + struct + { + uint32_t reserved0 : 30; + uint32_t lp_trigger_hp: 1; + uint32_t hp_trigger_lp: 1; + }; + uint32_t val; +} pmu_hp_lp_cpu_comm_reg_t; + +typedef union +{ + struct + { + uint32_t reserved0 : 31; + uint32_t dig_regulator_en_cal: 1; + }; + uint32_t val; +} pmu_hp_regulator_cfg_reg_t; + +typedef union +{ + struct + { + uint32_t reserved0 : 11; + uint32_t last_st : 7; + uint32_t target_st : 7; + uint32_t current_st: 7; + }; + uint32_t val; +} pmu_main_state_reg_t; + +typedef union +{ + struct + { + uint32_t reserved0: 13; + uint32_t backup_st: 5; + uint32_t lp_pwr_st: 5; + uint32_t hp_pwr_st: 9; + }; + uint32_t val; +} pmu_pwr_state_reg_t; + +typedef union +{ + struct + { + uint32_t stable_xpd_bbpll : 1; + uint32_t stable_xpd_xtal : 1; + uint32_t reserved0 : 13; + uint32_t sysclk_slp_sel : 1; + uint32_t sysclk_sel : 2; + uint32_t sysclk_nodiv : 1; + uint32_t icg_sysclk_en : 1; + uint32_t icg_modem_switch : 1; + uint32_t icg_modem_code : 2; + uint32_t icg_slp_sel : 1; + uint32_t icg_global_xtal : 1; + uint32_t icg_global_pll : 1; + uint32_t ana_i2c_iso_en : 1; + uint32_t ana_i2c_retention: 1; + uint32_t ana_xpd_bb_i2c : 1; + uint32_t ana_xpd_bbpll_i2c: 1; + uint32_t ana_xpd_bbpll : 1; + uint32_t ana_xpd_xtal : 1; + }; + uint32_t val; +} pmu_clk_state0_reg_t; + +typedef union +{ + struct { + uint32_t icg_func_en: 32; + }; + uint32_t val; +} pmu_clk_state1_reg_t; + +typedef union +{ + struct { + uint32_t icg_apb_en: 32; + }; + uint32_t val; +} pmu_clk_state2_reg_t; + +typedef union +{ + struct + { + uint32_t dsfmos_use_por : 1; + uint32_t reserved0 : 21; + uint32_t dcdc_dcm_update : 1; + uint32_t dcdc_pcur_limit : 3; + uint32_t dcdc_bias_cal_done: 1; + uint32_t dcdc_ccm_sw_en : 1; + uint32_t dcdc_vcm_enb : 1; + uint32_t dcdc_ccm_rdy : 1; + uint32_t dcdc_vcm_rdy : 1; + uint32_t dcdc_rdy_clr : 1; + }; + uint32_t val; +} pmu_dcm_ctrl_reg_t; + +typedef union +{ + struct + { + uint32_t sleep_cycles : 16; + uint32_t reserved0 : 5; + uint32_t wait_cycles : 9; + uint32_t sleep_timer_en: 1; + uint32_t force_done : 1; + }; + volatile uint32_t val; +} pmu_touch_pwr_ctrl_reg_t; -typedef struct pmu_dev_t{ +typedef struct pmu_dev_t +{ volatile pmu_hp_hw_regmap_t hp_sys[3]; volatile pmu_lp_hw_regmap_t lp_sys[2]; volatile pmu_imm_hw_regmap_t imm; @@ -675,86 +985,28 @@ typedef struct pmu_dev_t{ volatile pmu_hp_ext_hw_regmap_t hp_ext; volatile pmu_lp_ext_hw_regmap_t lp_ext; - union { - struct { - uint32_t reserved0 : 30; - volatile uint32_t lp_trigger_hp: 1; - volatile uint32_t hp_trigger_lp: 1; - }; - volatile uint32_t val; - } hp_lp_cpu_comm; - - union { - struct { - uint32_t reserved0 : 31; - volatile uint32_t dig_regulator_en_cal: 1; - }; - volatile uint32_t val; - } hp_regulator_cfg; - - union { - struct { - uint32_t reserved0 : 11; - volatile uint32_t last_st : 7; - volatile uint32_t target_st : 7; - volatile uint32_t current_st: 7; - }; - volatile uint32_t val; - } main_state; - - union { - struct { - uint32_t reserved0: 13; - volatile uint32_t backup_st: 5; - volatile uint32_t lp_pwr_st: 5; - volatile uint32_t hp_pwr_st: 9; - }; - volatile uint32_t val; - } pwr_state; - - union { - struct { - volatile uint32_t stable_xpd_bbpll : 1; - volatile uint32_t stable_xpd_xtal : 1; - volatile uint32_t reserved0 : 13; - volatile uint32_t sysclk_slp_sel : 1; - volatile uint32_t sysclk_sel : 2; - volatile uint32_t sysclk_nodiv : 1; - volatile uint32_t icg_sysclk_en : 1; - volatile uint32_t icg_modem_switch : 1; - volatile uint32_t icg_modem_code : 2; - volatile uint32_t icg_slp_sel : 1; - volatile uint32_t icg_global_xtal : 1; - volatile uint32_t icg_global_pll : 1; - volatile uint32_t ana_i2c_iso_en : 1; - volatile uint32_t ana_i2c_retention: 1; - volatile uint32_t ana_xpd_bb_i2c : 1; - volatile uint32_t ana_xpd_bbpll_i2c: 1; - volatile uint32_t ana_xpd_bbpll : 1; - volatile uint32_t ana_xpd_xtal : 1; - }; - volatile uint32_t val; - } clk_state0; + volatile pmu_hp_lp_cpu_comm_reg_t hp_lp_cpu_comm; + volatile pmu_hp_regulator_cfg_reg_t hp_regulator_cfg; - volatile uint32_t clk_state1; - volatile uint32_t clk_state2; + volatile pmu_main_state_reg_t main_state; + volatile pmu_pwr_state_reg_t pwr_state; + volatile pmu_clk_state0_reg_t clk_state0; + volatile pmu_clk_state1_reg_t clk_state1; + volatile pmu_clk_state2_reg_t clk_state2; - union { - struct { - uint32_t reserved0 : 31; - volatile uint32_t stable_vdd_spi_pwr_drv: 1; - }; - volatile uint32_t val; - } vdd_spi_status; + volatile pmu_dcm_ctrl_reg_t dcm_ctrl; + volatile pmu_touch_pwr_ctrl_reg_t touch_pwr_ctrl; - uint32_t reserved[149]; + uint32_t reserved[143]; - union { - struct { - volatile uint32_t pmu_date: 31; - volatile uint32_t clk_en : 1; + union + { + struct + { + uint32_t pmu_date : 31; + uint32_t clk_en : 1; }; - volatile uint32_t val; + uint32_t val; } date; } pmu_dev_t; @@ -763,8 +1015,7 @@ extern pmu_dev_t PMU; #ifndef __cplusplus _Static_assert(sizeof(pmu_dev_t) == 0x400, "Invalid size of pmu_dev_t structure"); -// _Static_assert(offsetof(pmu_dev_t, reserved) == (PMU_VDD_SPI_STATUS_REG - DR_REG_PMU_BASE) + 4, "Invalid size of pmu_dev_t structure"); - +_Static_assert(offsetof(pmu_dev_t, reserved) == (PMU_TOUCH_PWR_CTRL_REG - DR_REG_PMU_BASE) + 4, "Invalid size of pmu_dev_t structure"); #endif #ifdef __cplusplus From 30a050e9ae2cd4aadfc1ed87530d40642f6ba2cf Mon Sep 17 00:00:00 2001 From: Alex Bethel Date: Sat, 14 Dec 2024 13:01:08 -0700 Subject: [PATCH 071/118] docs: Fix `gpio_dump_io_configuration` typo in docs The mentioned `gpio_dump_all_io_configuration` function doesn't exist, the correct function is `gpio_dump_io_configuration`. --- docs/en/api-reference/peripherals/gpio.rst | 2 +- docs/zh_CN/api-reference/peripherals/gpio.rst | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/docs/en/api-reference/peripherals/gpio.rst b/docs/en/api-reference/peripherals/gpio.rst index a56786033e0..38c2ee688d1 100644 --- a/docs/en/api-reference/peripherals/gpio.rst +++ b/docs/en/api-reference/peripherals/gpio.rst @@ -81,7 +81,7 @@ In addition, if you would like to dump the configurations of all IOs, you can us :: - gpio_dump_all_io_configuration(stdout, SOC_GPIO_VALID_GPIO_MASK); + gpio_dump_io_configuration(stdout, SOC_GPIO_VALID_GPIO_MASK); If an IO pin is routed to a peripheral signal through the GPIO matrix, the signal ID printed in the dump information is defined in the :component_file:`soc/{IDF_TARGET_PATH_NAME}/include/soc/gpio_sig_map.h` header file. The word ``**RESERVED**`` indicates the IO is occupied by either SPI flash or PSRAM. It is strongly not recommended to reconfigure them for other application purposes. diff --git a/docs/zh_CN/api-reference/peripherals/gpio.rst b/docs/zh_CN/api-reference/peripherals/gpio.rst index 4fc0489c3d7..c9732320f5f 100644 --- a/docs/zh_CN/api-reference/peripherals/gpio.rst +++ b/docs/zh_CN/api-reference/peripherals/gpio.rst @@ -81,7 +81,7 @@ GPIO 驱动提供了一个函数 :cpp:func:`gpio_dump_io_configuration` 用来 :: - gpio_dump_all_io_configuration(stdout, SOC_GPIO_VALID_GPIO_MASK); + gpio_dump_io_configuration(stdout, SOC_GPIO_VALID_GPIO_MASK); 如果 IO 管脚通过 GPIO 交换矩阵连接到内部外设信号，输出信息打印中的外设信号 ID 定义可以在 :component_file:`soc/{IDF_TARGET_PATH_NAME}/include/soc/gpio_sig_map.h` 头文件中查看。``**RESERVED**`` 字样则表示此 IO 用于连接 SPI flash 或 PSRAM，强烈建议不要重新配置这些管脚用于其他功能。 From f6dde85e45e832f93fe36911b39ec05a67f700d1 Mon Sep 17 00:00:00 2001 From: Zhang Shuxian Date: Fri, 29 Nov 2024 10:45:22 +0800 Subject: [PATCH 072/118] docs: Update CN translation for heap debug --- docs/en/api-reference/system/heap_debug.rst | 7 +- .../zh_CN/api-reference/system/heap_debug.rst | 230 +++++++++++++----- 2 files changed, 176 insertions(+), 61 deletions(-) diff --git a/docs/en/api-reference/system/heap_debug.rst b/docs/en/api-reference/system/heap_debug.rst index 7a00a7115ac..472c9d3ccf7 100644 --- a/docs/en/api-reference/system/heap_debug.rst +++ b/docs/en/api-reference/system/heap_debug.rst @@ -137,6 +137,7 @@ Temporarily increasing the heap corruption detection level can give more detaile In the project configuration menu, under ``Component config``, there is a menu ``Heap memory debugging``. The option :ref:`CONFIG_HEAP_CORRUPTION_DETECTION` can be set to one of the following three levels: + Basic (No Poisoning) ++++++++++++++++++++ @@ -146,6 +147,7 @@ If assertions are enabled, an assertion will also trigger if a double-free occur Calling :cpp:func:`heap_caps_check_integrity` in Basic mode checks the integrity of all heap structures, and print errors if any appear to be corrupted. + Light Impact ++++++++++++ @@ -165,6 +167,7 @@ In both cases, the functions involve checking that the first 4 bytes of an alloc Different values usually indicate buffer underrun or overrun. Overrun indicates that when writing to memory, the data written exceeds the size of the allocated memory, resulting in writing to an unallocated memory area; underrun indicates that when reading memory, the data read exceeds the allocated memory and reads data from an unallocated memory area. + Comprehensive +++++++++++++ @@ -172,7 +175,7 @@ This level incorporates the "Light Impact" detection features. Additionally, it Enabling Comprehensive mode has a substantial impact on runtime performance, as all memory needs to be set to the allocation patterns each time a :cpp:func:`heap_caps_malloc` or :cpp:func:`heap_caps_free` completes, and the memory also needs to be checked each time. However, this mode allows easier detection of memory corruptions which are much more subtle to find otherwise. It is recommended to only enable this mode when debugging, not in production. -The checks for allocated and free patterns (``0xCE`` and respectively ``0xFE``) are also done when calling :cpp:func:`heap_caps_check_integrity` or :cpp:func:`heap_caps_check_integrity_all`. +The checks for allocated and free patterns (``0xCE`` and ``0xFE``, respectively) are also done when calling :cpp:func:`heap_caps_check_integrity` or :cpp:func:`heap_caps_check_integrity_all`. Crashes in Comprehensive Mode ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ @@ -404,7 +407,7 @@ For this reason, the option to use a hashmap mechanism to store records is avail Each hashmap entry is a singly linked list of records sharing the same hash ID. -Each record hash ID is calculated based on the pointer to the memory they track. The hash function used is based on the Fowler-Noll-Vo hash function modified to ensure an even spread of all records in the range [0 ; hashmap size[ where hashmap size can be defined by setting ``Component config`` > ``Heap Memory Debugging`` > :ref:`CONFIG_HEAP_TRACE_HASH_MAP_SIZE` in the project configuration menu. +Each record hash ID is calculated based on the pointer to the memory they track. The hash function used is based on the Fowler-Noll-Vo hash function modified to ensure an even spread of all records in the range [0, hashmap size[ where hashmap size can be defined by setting ``Component config`` > ``Heap Memory Debugging`` > :ref:`CONFIG_HEAP_TRACE_HASH_MAP_SIZE` in the project configuration menu. .. note:: diff --git a/docs/zh_CN/api-reference/system/heap_debug.rst b/docs/zh_CN/api-reference/system/heap_debug.rst index 86c7cf18f72..7e94300c4c3 100644 --- a/docs/zh_CN/api-reference/system/heap_debug.rst +++ b/docs/zh_CN/api-reference/system/heap_debug.rst @@ -30,7 +30,7 @@ ESP-IDF 集成了用于请求 :ref:`堆内存信息 `、:ref:` 堆内存分配与释放钩子函数 --------------------------------------- -通过堆内存分配及释放检测钩子，可获取每次堆内存分配及释放操作成功的提示： +你可以使用堆内存分配和释放检测钩子，接收每次成功分配或释放堆内存操作的通知： - 定义 :cpp:func:`esp_heap_trace_alloc_hook` 获取堆内存分配操作成功的提示 - 定义 :cpp:func:`esp_heap_trace_free_hook` 获取堆内存释放操作成功的提示 @@ -56,31 +56,14 @@ ESP-IDF 集成了用于请求 :ref:`堆内存信息 `、:ref:` void app_main() { - ... + ... } -.. _heap-corruption: - -堆内存损坏检测 -------------------------- - -堆内存损坏检测可检测到各类堆内存错误，包括： - -- 越界写入和缓冲区溢出 -- 写入已释放的内存 -- 从已释放或未初始化的内存读取 - -断言 -^^^^^^^^^^ -如 :component_file:`heap/multi_heap.c` 等堆的实现方式包含许多断言，堆内存损坏则断言失败。为高效检测堆内存损坏，请确保在项目配置中通过 :ref:`CONFIG_COMPILER_OPTIMIZATION_ASSERTION_LEVEL` 选项启用断言。 - -如果堆完整性断言失败，将打印一行类似 ``CORRUPT HEAP: multi_heap.c:225 detected at 0x3ffbb71c`` 的内容，打印的内存地址即内容损坏的堆结构地址。 - -调用 :cpp:func:`heap_caps_check_integrity_all` 或相关函数可手动检测堆内存完整性，该函数可以检测所有请求的堆内存完整性，在禁用断言时仍可生效。若此完整性检测检测到错误，将打印相应错误及内容损坏的堆内存结构地址。 +.. _heap-allocation-failed: 内存分配失败钩子 -^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ +------------------ 用户可以使用 :cpp:func:`heap_caps_register_failed_alloc_callback` 注册回调函数，每次内存分配操作失败时都会调用该函数。 @@ -106,6 +89,34 @@ ESP-IDF 集成了用于请求 :ref:`堆内存信息 `、:ref:` ... } + +.. _heap-corruption: + +检测堆内存损坏 +------------------ + +堆内存损坏检测可检测到各类堆内存错误，包括： + +- 越界写入和缓冲区溢出 +- 对已释放内存的写操作 +- 对已释放或未初始化内存的读操作 + +堆内存损坏检测共有三个级别，在下方列表中，后一级别比前一级别提供更精细的检测： + +.. list:: + - `基本模式（无 canary 标记）`_ + - `轻量级模式`_ + - `全面检测模式`_ + +断言 +^^^^^^^^^^ + +如 :component_file:`heap/multi_heap.c` 等堆的实现方式包含许多断言，堆内存损坏则断言失败。为高效检测堆内存损坏，请确保在项目配置中通过 :ref:`CONFIG_COMPILER_OPTIMIZATION_ASSERTION_LEVEL` 选项启用断言。 + +如果堆完整性断言失败，将打印一行类似 ``CORRUPT HEAP: multi_heap.c:225 detected at 0x3ffbb71c`` 的内容，打印的内存地址即内容损坏的堆结构地址。 + +调用 :cpp:func:`heap_caps_check_integrity_all` 或相关函数可手动检测堆的完整性。该函数可以检测所有指定的堆内存是否完整，在禁用断言时仍可生效。若此完整性检测发现错误，将打印相应错误及损坏的堆结构地址。 + 定位堆内存损坏 ^^^^^^^^^^^^^^^^^^^^^^^ @@ -126,8 +137,9 @@ ESP-IDF 集成了用于请求 :ref:`堆内存信息 `、:ref:` 在项目配置菜单中，可以在 ``Component config`` 下找到 ``Heap memory debugging`` 菜单，其中的 :ref:`CONFIG_HEAP_CORRUPTION_DETECTION` 选项可以设置为以下三种级别： -基本模式（无污染） -+++++++++++++++++++++++++ + +基本模式（无 canary 标记） +++++++++++++++++++++++++++++++++ 此为默认级别，默认情况下，不会启用任何特殊的堆内存损坏检测功能。但会启用提供的断言。如果堆的任何内部数据结构出现覆盖或损坏，就会打印出一个堆内存损坏错误。这通常表示缓冲区溢出或越界写入。 @@ -135,32 +147,36 @@ ESP-IDF 集成了用于请求 :ref:`堆内存信息 `、:ref:` 在基本模式调用 :cpp:func:`heap_caps_check_integrity`，可以检查所有堆结构的完整性，并在出错时打印错误信息。 -轻微影响模式 + +轻量级模式 +++++++++++++++++ -在此级别下，每个分配的内存块都会在头尾加入“canary 字节”进行“污染”。如果应用程序在已分配缓冲区的边界外写入数据，则会破坏这些 canary 字节，导致完整性检查失败。 +此级别包含“基本模式”中的所有检测功能。此外，每个分配的内存块都会在头部和尾部添加 canary 字节进行“污染”标记。如果应用程序写入了这些 canary 字节，则会被视为已损坏，导致完整性检查失败。 头 canary 字的值为 ``0xABBA1234`` （按字节顺序为 ``3412BAAB``），尾 canary 字的值为 ``0xBAAD5678`` （按字节顺序为 ``7856ADBA``）。 -基本模式下的堆内存损坏检测可以检测到大多数越界写入，在检测到错误前的越界字节数取决于堆属性。但轻微影响模式更精确，可以检测到单个字节的越界写入。 +基本模式下的堆内存损坏检测可以检测到大多数越界写入，在检测到错误前的越界字节数取决于堆属性。但轻量级模式更精确，可以检测到单个字节的越界写入。 -启用轻微影响模式检测会增加内存使用量，每次内存分配需要 9 至 12 个额外的字节，具体取决于对齐方式。 +启用轻量级模式检测会增加内存使用量，因为每次内存分配都会使用额外的元数据字节。 -在轻微影响模式下，每次调用 :cpp:func:`heap_caps_free` 时，都会检查要释放的缓冲区头尾 canary 字节是否匹配预期值。 +在轻量级模式下，每次调用 :cpp:func:`heap_caps_free` 时，都会检查要释放的缓冲区头尾 canary 字节是否匹配预期值。 -调用 :cpp:func:`heap_caps_check_integrity` 时，会检查所有已分配的堆内存块的 canary 字节是否匹配预期值。 +调用 :cpp:func:`heap_caps_check_integrity` 或 :cpp:func:`heap_caps_check_integrity_all` 时，会检查所有已分配的堆内存块的 canary 字节是否匹配预期值。 以上两种情况检查的是，在缓冲区返回给用户之前，已分配块的前 4 个字节是否为 ``0xABBA1234``，以及在缓冲区返回给用户之后，最后 4 个字节是否为 ``0xBAAD5678``。 如果检查到字节与上述值不同，通常表示缓冲区越界或下溢。其中越界表示在写入内存时，写入的数据超过了所分配内存的大小，导致写入到了未分配的内存区域；下溢表示在读取内存时，读取的数据超出了所分配内存的范围，读取了未分配的内存区域的数据。 + 全面检测模式 +++++++++++++++++++ -此级别包含了轻微影响模式的检测功能，此外还会检查未初始化访问和使用已释放内存产生的错误。此模式会将所有新分配的内存填充为 ``0xCE``，将所有已释放的内存填充为 ``0xFE``。 +此级别包含了轻量级模式的检测功能，此外还会检查未初始化访问和使用已释放内存产生的错误。此模式会将所有新分配的内存填充为 ``0xCE``，将所有已释放的内存填充为 ``0xFE``。 启用全面检测模式会对运行性能产生实质影响，因为每次 :cpp:func:`heap_caps_malloc` 或 :cpp:func:`heap_caps_free` 操作完成时，都需要将所有内存设置为分配模式，并检查内存。但是，此模式更容易检测到其他方式难以发现的内存损坏错误。建议只在调试时启用此模式，请勿在生产环境中启用。 +在调用 :cpp:func:`heap_caps_check_integrity` 或 :cpp:func:`heap_caps_check_integrity_all` 时，还会对已分配和释放模式（分别为 ``0xCE`` 和 ``0xFE``）进行检查。 + 全面检测模式下程序崩溃 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ @@ -173,10 +189,11 @@ ESP-IDF 集成了用于请求 :ref:`堆内存信息 `、:ref:` 全面检测模式下手动堆内存检测 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -调用 :cpp:func:`heap_caps_check_integrity` 会打印与 ``0xFEFEFEFE``、``0xABBA1234``、或 ``0xBAAD5678`` 相关的错误。在不同情况下，检测器均会检测给定模式，若未找到，则输出相应错误： +调用 :cpp:func:`heap_caps_check_integrity` 或 :cpp:func:`heap_caps_check_integrity_all` 会打印与 ``0xFEFEFEFE``、``0xABBA1234``、或 ``0xBAAD5678`` 相关的错误。在不同情况下，检测器均会检测给定模式，若未找到，则输出相应错误： - 对于已释放的堆内存块，检测器会检查是否所有字节都设置为 ``0xFE``，检测到任何其他值都表示错误写入了已释放内存。 -- 对于已分配的堆内存块，检测器的检查模式与轻微影响模式相同，即在每个分配的缓冲区头部和尾部检查 canary 字节 ``0xABBA1234`` 和 ``0xBAAD5678``，检测到任何其他字节都表示缓冲区越界或下溢。 +- 对于已分配的堆内存块，检测器的检查模式与轻量级模式相同，即在每个分配的缓冲区头部和尾部检查 canary 字节 ``0xABBA1234`` 和 ``0xBAAD5678``，检测到任何其他字节都表示缓冲区越界或下溢。 + .. _heap-task-tracking: @@ -187,6 +204,7 @@ ESP-IDF 集成了用于请求 :ref:`堆内存信息 `、:ref:` 示例代码可参考 :example:`system/heap_task_tracking`。 + .. _heap-tracing: 堆内存跟踪 @@ -209,7 +227,7 @@ ESP-IDF 集成了用于请求 :ref:`堆内存信息 `、:ref:` 独立模式 -+++++++++++++++ +^^^^^^^^^^^^^ 确定存在泄漏的代码后，请执行以下步骤： @@ -253,39 +271,107 @@ ESP-IDF 集成了用于请求 :ref:`堆内存信息 `、:ref:` .. only:: CONFIG_IDF_TARGET_ARCH_XTENSA - .. code-block:: none + .. code-block:: none - 2 allocations trace (100 entry buffer) - 32 bytes (@ 0x3ffaf214) allocated CPU 0 ccount 0x2e9b7384 caller 0x400d276d:0x400d27c1 - 0x400d276d: leak_some_memory at /path/to/idf/examples/get-started/blink/main/./blink.c:27 + ====== Heap Trace: 8 records (8 capacity) ====== + 6 bytes (@ 0x3fc9f620, Internal) allocated CPU 0 ccount 0x1a31ac84 caller 0x40376321:0x40376379 + 0x40376321: heap_caps_malloc at /path/to/idf/examples/components/heap/heap_caps.c:84 + 0x40376379: heap_caps_malloc_default at /path/to/idf/examples/components/heap/heap_caps.c:110 - 0x400d27c1: blink_task at /path/to/idf/examples/get-started/blink/main/./blink.c:52 + freed by 0x403839e4:0x42008096 + 0x403839e4: free at /path/to/idf/examples/components/newlib/heap.c:40 + 0x42008096: test_func_74 at /path/to/idf/examples/components/heap/test_apps/heap_tests/main/test_heap_trace.c:104 (discriminator 3) - 8 bytes (@ 0x3ffaf804) allocated CPU 0 ccount 0x2e9b79c0 caller 0x400d2776:0x400d27c1 - 0x400d2776: leak_some_memory at /path/to/idf/examples/get-started/blink/main/./blink.c:29 + 9 bytes (@ 0x3fc9f630, Internal) allocated CPU 0 ccount 0x1a31b618 caller 0x40376321:0x40376379 + 0x40376321: heap_caps_malloc at /path/to/idf/examples/components/heap/heap_caps.c:84 + 0x40376379: heap_caps_malloc_default at /path/to/idf/examples/components/heap/heap_caps.c:110 - 0x400d27c1: blink_task at /path/to/idf/examples/get-started/blink/main/./blink.c:52 + freed by 0x403839e4:0x42008096 + 0x403839e4: free at /path/to/idf/examples/components/newlib/heap.c:40 + 0x42008096: test_func_74 at /path/to/idf/examples/components/heap/test_apps/heap_tests/main/test_heap_trace.c:104 (discriminator 3) - 40 bytes 'leaked' in trace (2 allocations) - total allocations 2 total frees 0 + 12 bytes (@ 0x3fc9f640, Internal) allocated CPU 0 ccount 0x1a31bfac caller 0x40376321:0x40376379 + 0x40376321: heap_caps_malloc at /path/to/idf/examples/components/heap/heap_caps.c:84 + 0x40376379: heap_caps_malloc_default at /path/to/idf/examples/components/heap/heap_caps.c:110 -.. only:: CONFIG_IDF_TARGET_ARCH_RISCV + freed by 0x403839e4:0x42008096 + 0x403839e4: free at /path/to/idf/examples/components/newlib/heap.c:40 + 0x42008096: test_func_74 at /path/to/idf/examples/components/heap/test_apps/heap_tests/main/test_heap_trace.c:104 (discriminator 3) + + 15 bytes (@ 0x3fc9f650, Internal) allocated CPU 0 ccount 0x1a31c940 caller 0x40376321:0x40376379 + 0x40376321: heap_caps_malloc at /path/to/idf/examples/components/heap/heap_caps.c:84 + 0x40376379: heap_caps_malloc_default at /path/to/idf/examples/components/heap/heap_caps.c:110 + + freed by 0x403839e4:0x42008096 + 0x403839e4: free at /path/to/idf/examples/components/newlib/heap.c:40 + 0x42008096: test_func_74 at /path/to/idf/examples/components/heap/test_apps/heap_tests/main/test_heap_trace.c:104 (discriminator 3) + + 18 bytes (@ 0x3fc9f664, Internal) allocated CPU 0 ccount 0x1a31d2d4 caller 0x40376321:0x40376379 + 0x40376321: heap_caps_malloc at /path/to/idf/examples/components/heap/heap_caps.c:84 + 0x40376379: heap_caps_malloc_default at /path/to/idf/examples/components/heap/heap_caps.c:110 + + freed by 0x403839e4:0x42008096 + 0x403839e4: free at /path/to/idf/examples/components/newlib/heap.c:40 + 0x42008096: test_func_74 at /path/to/idf/examples/components/heap/test_apps/heap_tests/main/test_heap_trace.c:104 (discriminator 3) + + 21 bytes (@ 0x3fc9f67c, Internal) allocated CPU 0 ccount 0x1a31dc68 caller 0x40376321:0x40376379 + 0x40376321: heap_caps_malloc at /path/to/idf/examples/components/heap/heap_caps.c:84 + 0x40376379: heap_caps_malloc_default at /path/to/idf/examples/components/heap/heap_caps.c:110 + + freed by 0x403839e4:0x42008096 + 0x403839e4: free at /path/to/idf/examples/components/newlib/heap.c:40 + 0x42008096: test_func_74 at /path/to/idf/examples/components/heap/test_apps/heap_tests/main/test_heap_trace.c:104 (discriminator 3) + + 24 bytes (@ 0x3fc9f698, Internal) allocated CPU 0 ccount 0x1a31e600 caller 0x40376321:0x40376379 + 0x40376321: heap_caps_malloc at /path/to/idf/examples/components/heap/heap_caps.c:84 + 0x40376379: heap_caps_malloc_default at /path/to/idf/examples/components/heap/heap_caps.c:110 + + freed by 0x403839e4:0x42008096 + 0x403839e4: free at /path/to/idf/examples/components/newlib/heap.c:40 + 0x42008096: test_func_74 at /path/to/idf/examples/components/heap/test_apps/heap_tests/main/test_heap_trace.c:104 (discriminator 3) - .. code-block:: none + 6 bytes (@ 0x3fc9f6b4, Internal) allocated CPU 0 ccount 0x1a320698 caller 0x40376321:0x40376379 + 0x40376321: heap_caps_malloc at /path/to/idf/examples/components/heap/heap_caps.c:84 + 0x40376379: heap_caps_malloc_default at /path/to/idf/examples/components/heap/heap_caps.c:110 - 2 allocations trace (100 entry buffer) - 32 bytes (@ 0x3ffaf214) allocated CPU 0 ccount 0x2e9b7384 caller - 8 bytes (@ 0x3ffaf804) allocated CPU 0 ccount 0x2e9b79c0 caller - 40 bytes 'leaked' in trace (2 allocations) - total allocations 2 total frees 0 + ====== Heap Trace Summary ====== + Mode: Heap Trace All + 6 bytes alive in trace (1/8 allocations) + records: 8 (8 capacity, 8 high water mark) + total allocations: 9 + total frees: 8 + ================================ + +.. only:: CONFIG_IDF_TARGET_ARCH_RISCV + + .. code-block:: none + + ====== Heap Trace: 8 records (8 capacity) ====== + 3 bytes (@ 0x3fcb26f8, Internal) allocated CPU 0 ccount 0x1e7af728 freed + 6 bytes (@ 0x3fcb4ff0, Internal) allocated CPU 0 ccount 0x1e7afc38 freed + 9 bytes (@ 0x3fcb5000, Internal) allocated CPU 0 ccount 0x1e7b01d4 freed + 12 bytes (@ 0x3fcb5010, Internal) allocated CPU 0 ccount 0x1e7b0778 freed + 15 bytes (@ 0x3fcb5020, Internal) allocated CPU 0 ccount 0x1e7b0d18 freed + 18 bytes (@ 0x3fcb5034, Internal) allocated CPU 0 ccount 0x1e7b12b8 freed + 21 bytes (@ 0x3fcb504c, Internal) allocated CPU 0 ccount 0x1e7b1858 freed + 24 bytes (@ 0x3fcb5068, Internal) allocated CPU 0 ccount 0x1e7b1dfc freed + ====== Heap Trace Summary ====== + Mode: Heap Trace All + 0 bytes alive in trace (0/8 allocations) + records: 8 (8 capacity, 8 high water mark) + total allocations: 8 + total frees: 8 + ================================ .. note:: 以上示例输出使用 :doc:`IDF 监视器 `，自动将 PC 地址解码为其源文件和行号。 -第一行表示与缓冲区的总大小相比，缓冲区内的分配条目数量。 + 如果记录列表溢出，将输出 ``(NB: Internal Buffer has overflowed, so trace data is incomplete.)``。如果看到此日志，请考虑缩短追踪周期或增加追踪缓冲区中的记录数量。 -在 ``HEAP_TRACE_LEAKS`` 模式下，对跟踪的每个未释放的已分配内存，打印的信息中都会包含以下内容： + 如果在调用 :cpp:func:`heap_trace_dump` 或 :cpp:func:`heap_trace_dump_caps` 时有新条目被追踪，将输出 ``(NB: New entries were traced while dumping, so trace dump may have duplicate entries.)``。 + +在 ``HEAP_TRACE_LEAKS`` 或 ``HEAP_TRACE_ALL`` 模式下，对跟踪的每个未释放的已分配内存，打印的信息中都会包含以下内容： .. list:: @@ -294,25 +380,51 @@ ESP-IDF 集成了用于请求 :ref:`堆内存信息 `、:ref:` - ``Internal`` 或 ``PSRAM``：分配内存的一般位置。 - ``CPU x``：分配过程中运行的 CPU（CPU 0 或 CPU 1）。 - ``ccount 0x...``：分配时的 CCOUNT（CPU 循环计数器）寄存器值，CPU 0 与 CPU 1 中的这一值不同。 - :CONFIG_IDF_TARGET_ARCH_XTENSA: - ``caller 0x...`` 作为 PC 地址列表，给出 :cpp:func:`heap_caps_malloc` 或 :cpp:func:`heap_caps_free` 的调用栈，可解码到源文件和行号，如上文所示。 + :CONFIG_IDF_TARGET_ARCH_XTENSA: - ``caller 0x...`` 以 PC 地址列表的形式，提供 :cpp:func:`heap_caps_malloc` 的调用栈信息。这些地址可以解码为源文件和行号，如上文所示。 + +在 ``HEAP_TRACE_LEAKS`` 模式下，释放内存后，相关的记录会被丢弃。 -.. only:: not CONFIG_IDF_TARGET_ARCH_RISCV +在 ``HEAP_TRACE_ALL`` 模式下： + +.. list:: + + :CONFIG_IDF_TARGET_ARCH_RISCV: - 释放内存后，相关记录会保留在列表中，其字段 ``freed`` 设置为 true。 + :CONFIG_IDF_TARGET_ARCH_XTENSA: - 释放内存后，相关记录的字段 ``freed by`` 会填充为 :cpp:func:`heap_caps_free` 的调用栈（以 PC 地址列表的形式）。这些地址可以解码为源文件和行号，如上所示。 + - 在达到最大记录数后，会丢弃旧记录，用新记录替换。 + +.. only:: CONFIG_IDF_TARGET_ARCH_XTENSA 每个跟踪条目记录的调用栈深度可以在项目配置菜单下进行配置，选择 ``Heap Memory Debugging`` > ``Enable heap tracing`` > :ref:`CONFIG_HEAP_TRACING_STACK_DEPTH`。每个内存分配最多可以记录 32 个栈帧（默认为 2），每增加一个栈帧，每个 ``heap_trace_record_t`` 记录的内存使用量将增加 8 个字节。 最后，将打印“泄漏”的总字节数（即在跟踪期间分配但未释放的总字节数），以及它所代表的总分配次数。 -如果跟踪缓冲区不足以容纳所有分配，则会打印警告。如果看到此警告，请考虑缩短跟踪时间，或增加跟踪缓冲区中记录的数量。 +使用哈希表提高性能 +++++++++++++++++++++ + +默认情况下，堆追踪使用一个静态分配的双向链表来存储追踪记录。这种方式的缺点是，当链表中的记录条目数量增加时，查找特定记录的耗时也会随之增加，从而导致运行性能下降。因此，在需要存储大量记录时，双向链表的使用效率很低（甚至可能导致功能无法使用，因为从列表中检索条目所需的时间会阻碍应用程序的正常运行）。 + +为了解决这个问题，可以前往 ``Component config`` > ``Heap Memory Debugging`` 配置菜单 > 启用 :ref:`CONFIG_HEAP_TRACE_HASH_MAP` 选项，使用哈希表机制来存储记录。这样就可以在不严重影响性能的情况下追踪大量记录。 + +每个哈希表条目是一个单向链表，用于存储具有相同哈希 ID 的记录。 + +每条记录的哈希 ID 是基于它们追踪的内存指针计算的。使用的哈希函数基于修改后的 Fowler-Noll-Vo 哈希函数，确保了所有记录在范围 [0, 哈希表大小) 内均匀分布。其中哈希表大小可以前往项目配置菜单 ``Component config`` > ``Heap Memory Debugging`` > 设置 :ref:`CONFIG_HEAP_TRACE_HASH_MAP_SIZE` 来定义。 + +.. note:: + + .. list:: + - 选项 :ref:`CONFIG_HEAP_TRACE_HASH_MAP_SIZE` 定义了哈希表中的条目数量。记录的总数量仍由用户在调用 :cpp:func:`heap_trace_init_standalone` 时定义。如果最大记录数为 ``N``，而哈希表的条目数为 ``H``，那么每个条目最多可包含 ``N / H`` 条记录。 + - 哈希表是对双向链表的补充，而无法替代双向链表。因为使用哈希表可能会导致显著的内存开销。 + :SOC_SPIRAM_SUPPORTED: - 存储哈希表所用的内存是动态分配的（默认分配在内部内存中），但用户可以通过前往 ``Component config`` > ``Heap Memory Debugging`` > 设置:ref:`CONFIG_HEAP_TRACE_HASH_MAP_IN_EXT_RAM` 选项，将哈希表强制存储在外部内存中（此选项仅在启用了 :ref:`CONFIG_SPIRAM` 的条件下可用）。 主机模式 -+++++++++++++++ +^^^^^^^^^^^^^^^ 确定存在泄漏的代码后，请执行以下步骤： -- 在项目配置菜单中，导航至 ``Component settings`` > ``Heap Memory Debugging`` > :ref:`CONFIG_HEAP_TRACING_DEST` 并选择 ``Host-Based``。 -- 在项目配置菜单中，导航至 ``Component settings`` > ``Application Level Tracing`` > :ref:`CONFIG_APPTRACE_DESTINATION1` 并选择 ``Trace memory``。 -- 在项目配置菜单中，导航至 ``Component settings`` > ``Application Level Tracing`` > ``FreeRTOS SystemView Tracing`` 并启用 :ref:`CONFIG_APPTRACE_SV_ENABLE`。 +- 在项目配置菜单中，前往 ``Component config`` > ``Heap Memory Debugging`` > :ref:`CONFIG_HEAP_TRACING_DEST` 并选择 ``Host-Based``。 +- 在项目配置菜单中，前往 ``Component config`` > ``Application Level Tracing`` > :ref:`CONFIG_APPTRACE_DESTINATION1` 并选择 ``Trace memory``。 +- 在项目配置菜单中，前往 ``Component config`` > ``Application Level Tracing`` > ``FreeRTOS SystemView Tracing`` 并启用 :ref:`CONFIG_APPTRACE_SV_ENABLE`。 - 在程序早期，调用函数 :cpp:func:`heap_trace_init_tohost`，初始化 JTAG 堆内存跟踪模块。 - 在有内存泄漏之嫌的代码块前，调用函数 :cpp:func:`heap_trace_start` 开始记录系统中的内存分配和释放操作。 From a1c89bb7df4e5b4a88ee76a8d1cc251e85213e7b Mon Sep 17 00:00:00 2001 From: xiongweichao Date: Thu, 12 Dec 2024 15:27:26 +0800 Subject: [PATCH 073/118] fix(ble): fixed that the resolvable private address does not change when light sleep is enabled --- components/bt/controller/lib_esp32c3_family | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/components/bt/controller/lib_esp32c3_family b/components/bt/controller/lib_esp32c3_family index c57c0b11c3c..4c16da1a1a7 160000 --- a/components/bt/controller/lib_esp32c3_family +++ b/components/bt/controller/lib_esp32c3_family @@ -1 +1 @@ -Subproject commit c57c0b11c3c0065a16b66685715100a189ef9b27 +Subproject commit 4c16da1a1a76b439e2cf981d2f915d94df364e58 From f8648f2ee60e578ae5e8d19358ccb5e3aa970887 Mon Sep 17 00:00:00 2001 From: Xu Si Yu Date: Mon, 16 Dec 2024 16:38:39 +0800 Subject: [PATCH 074/118] fix(openthread): fix a naming error of kconfig --- components/openthread/Kconfig | 2 +- examples/openthread/ot_br/sdkconfig.ci.spiram | 6 ++++++ 2 files changed, 7 insertions(+), 1 deletion(-) create mode 100644 examples/openthread/ot_br/sdkconfig.ci.spiram diff --git a/components/openthread/Kconfig b/components/openthread/Kconfig index 9217d55c39e..f34a3a0228b 100644 --- a/components/openthread/Kconfig +++ b/components/openthread/Kconfig @@ -328,7 +328,7 @@ menu "OpenThread" menu "Thread Memory Allocation" depends on (SPIRAM_USE_CAPS_ALLOC || SPIRAM_USE_MALLOC) - config OPENTHREAD_MEM_ALLOC_EXTERNAL + config OPENTHREAD_PLATFORM_MALLOC_CAP_SPIRAM bool 'Allocate memory from PSRAM' default y help diff --git a/examples/openthread/ot_br/sdkconfig.ci.spiram b/examples/openthread/ot_br/sdkconfig.ci.spiram new file mode 100644 index 00000000000..f4b071ddb0b --- /dev/null +++ b/examples/openthread/ot_br/sdkconfig.ci.spiram @@ -0,0 +1,6 @@ +CONFIG_IDF_TARGET="esp32s3" +CONFIG_IDF_TARGET_ESP32S3=y +CONFIG_SPIRAM=y +CONFIG_SPIRAM_USE_MALLOC=y +CONFIG_OPENTHREAD_PLATFORM_MALLOC_CAP_SPIRAM=y +CONFIG_OPENTHREAD_PLATFORM_MSGPOOL_MANAGEMENT=y From 8e8e577d2ca002c22a61662bf3520e3a9fa095e2 Mon Sep 17 00:00:00 2001 From: xiongweichao Date: Thu, 5 Dec 2024 15:09:02 +0800 Subject: [PATCH 075/118] fix(bt): Fixed some controller bugs - Fix epr not being initiated after authentication is completed - Fixed the issue HCI_READ_CLOCK returned parameter in slot - Fixed the missmatching of CLKN and FCNT after clock update --- components/bt/controller/lib_esp32 | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/components/bt/controller/lib_esp32 b/components/bt/controller/lib_esp32 index e20022bf772..ffb8fad8e0f 160000 --- a/components/bt/controller/lib_esp32 +++ b/components/bt/controller/lib_esp32 @@ -1 +1 @@ -Subproject commit e20022bf7724edb14506b50ea47cbf5b7a5bdd88 +Subproject commit ffb8fad8e0ff68f565bae8728cc68ebb49ae33b4 From 0b780835954ec195b5d753e00cb64df7e5ee24e7 Mon Sep 17 00:00:00 2001 From: Marek Fiala Date: Tue, 10 Dec 2024 13:33:00 +0100 Subject: [PATCH 076/118] fix(tools): fixed test_create_project_with_idf_readonly on Win --- tools/idf_py_actions/create_ext.py | 10 ++++++---- 1 file changed, 6 insertions(+), 4 deletions(-) diff --git a/tools/idf_py_actions/create_ext.py b/tools/idf_py_actions/create_ext.py index 3d97147854a..9634bd8ccc4 100644 --- a/tools/idf_py_actions/create_ext.py +++ b/tools/idf_py_actions/create_ext.py @@ -1,9 +1,9 @@ -# SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD +# SPDX-FileCopyrightText: 2022-2024 Espressif Systems (Shanghai) CO LTD # SPDX-License-Identifier: Apache-2.0 import os import re import sys -from shutil import copy +from shutil import copyfile from shutil import copytree from typing import Dict @@ -42,7 +42,8 @@ def create_project(target_path: str, name: str) -> None: copytree( os.path.join(os.environ['IDF_PATH'], 'tools', 'templates', 'sample_project'), target_path, - copy_function=copy, + # 'copyfile' ensures only data are copied, without any metadata (file permissions) + copy_function=copyfile, dirs_exist_ok=True, ) main_folder = os.path.join(target_path, 'main') @@ -55,7 +56,8 @@ def create_component(target_path: str, name: str) -> None: copytree( os.path.join(os.environ['IDF_PATH'], 'tools', 'templates', 'sample_component'), target_path, - copy_function=copy, + # 'copyfile' ensures only data are copied, without any metadata (file permissions) + copy_function=copyfile, dirs_exist_ok=True, ) os.rename(os.path.join(target_path, 'main.c'), os.path.join(target_path, '.'.join((name, 'c')))) From 5930a422d7cf31b96ae465e7bd89b528712e676f Mon Sep 17 00:00:00 2001 From: Marek Fiala Date: Mon, 16 Dec 2024 10:20:24 +0100 Subject: [PATCH 077/118] fix(tools): Fixed timeout and path bug for test_cli_installer_win --- .gitlab/ci/test-win.yml | 1 + tools/test_idf_tools/test_idf_tools.py | 5 +++-- 2 files changed, 4 insertions(+), 2 deletions(-) diff --git a/.gitlab/ci/test-win.yml b/.gitlab/ci/test-win.yml index 42e24469333..3b8d3d18074 100644 --- a/.gitlab/ci/test-win.yml +++ b/.gitlab/ci/test-win.yml @@ -29,6 +29,7 @@ test_cli_installer_win: expire_in: 1 week variables: IDF_PATH: "$CI_PROJECT_DIR" + timeout: 3h script: # Tools must be downloaded for testing - python ${IDF_PATH}\tools\idf_tools.py download required qemu-riscv32 qemu-xtensa cmake diff --git a/tools/test_idf_tools/test_idf_tools.py b/tools/test_idf_tools/test_idf_tools.py index 87eab1dee0c..00a82635d33 100755 --- a/tools/test_idf_tools/test_idf_tools.py +++ b/tools/test_idf_tools/test_idf_tools.py @@ -322,8 +322,9 @@ def test_export_with_required_tools_check_skipped(self): self.run_idf_tools_with_action(['install', OPENOCD]) output = self.run_idf_tools_with_action(['export']) - self.assertIn('%s/tools/openocd-esp32/%s/openocd-esp32/bin' % - (self.temp_tools_dir, OPENOCD_VERSION), output) + self.assertIn(os.path.join( + self.temp_tools_dir, 'tools', 'openocd-esp32', OPENOCD_VERSION, 'openocd-esp32', 'bin' + ), output) # TestUsageUnix tests installed tools on UNIX platforms From 5e53f2975ee389c86a922d1860bf5dc7ed20419a Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Tom=C3=A1=C5=A1=20Rohl=C3=ADnek?= Date: Mon, 16 Dec 2024 15:06:26 +0100 Subject: [PATCH 078/118] fix(storage/vfs): incorrect log level in esp_vfs_register_fd_range Closes https://github.com/espressif/esp-idf/issues/14327 --- components/vfs/vfs.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/components/vfs/vfs.c b/components/vfs/vfs.c index 82307a629e7..49581c71362 100644 --- a/components/vfs/vfs.c +++ b/components/vfs/vfs.c @@ -529,7 +529,7 @@ esp_err_t esp_vfs_register_fd_range(const esp_vfs_t *vfs, void *ctx, int min_fd, } } _lock_release(&s_fd_table_lock); - ESP_LOGD(TAG, "esp_vfs_register_fd_range cannot set fd %d (used by other VFS)", i); + ESP_LOGW(TAG, "esp_vfs_register_fd_range cannot set fd %d (used by other VFS)", i); return ESP_ERR_INVALID_ARG; } s_fd_table[i].permanent = true; @@ -538,7 +538,7 @@ esp_err_t esp_vfs_register_fd_range(const esp_vfs_t *vfs, void *ctx, int min_fd, } _lock_release(&s_fd_table_lock); - ESP_LOGW(TAG, "esp_vfs_register_fd_range is successful for range <%d; %d) and VFS ID %d", min_fd, max_fd, index); + ESP_LOGD(TAG, "esp_vfs_register_fd_range is successful for range <%d; %d) and VFS ID %d", min_fd, max_fd, index); } return ret; From 3cef3baeba52cdba43885a70dbd8292a0a111b32 Mon Sep 17 00:00:00 2001 From: "peter.marcisovsky" Date: Wed, 6 Nov 2024 15:15:08 +0100 Subject: [PATCH 079/118] feat(usb_host): Mock USB device open/close - CMock callbacks for USB device opening and closing --- components/usb/private_include/usb_private.h | 3 +- components/usb/usb_private.c | 10 +- tools/mocks/usb/CMakeLists.txt | 6 + tools/mocks/usb/include/mock_add_usb_device.h | 294 ++++++++++++++ tools/mocks/usb/mock/mock_config.yaml | 1 + tools/mocks/usb/mock_add_usb_device.c | 376 ++++++++++++++++++ 6 files changed, 688 insertions(+), 2 deletions(-) create mode 100644 tools/mocks/usb/include/mock_add_usb_device.h create mode 100644 tools/mocks/usb/mock_add_usb_device.c diff --git a/components/usb/private_include/usb_private.h b/components/usb/private_include/usb_private.h index 71fb23db7ef..7295883dd13 100644 --- a/components/usb/private_include/usb_private.h +++ b/components/usb/private_include/usb_private.h @@ -10,6 +10,7 @@ #include #include #include +#include "esp_assert.h" #include "usb/usb_types_ch9.h" #include "usb/usb_types_stack.h" @@ -34,7 +35,7 @@ typedef struct { int num_isoc_packets; usb_isoc_packet_desc_t isoc_packet_desc[0]; } usb_transfer_dummy_t; -_Static_assert(sizeof(usb_transfer_dummy_t) == sizeof(usb_transfer_t), "usb_transfer_dummy_t does not match usb_transfer_t"); +ESP_STATIC_ASSERT(sizeof(usb_transfer_dummy_t) == sizeof(usb_transfer_t), "usb_transfer_dummy_t does not match usb_transfer_t"); struct urb_s { TAILQ_ENTRY(urb_s) tailq_entry; diff --git a/components/usb/usb_private.c b/components/usb/usb_private.c index 56d6b3d719d..0eeef5da615 100644 --- a/components/usb/usb_private.c +++ b/components/usb/usb_private.c @@ -15,10 +15,18 @@ urb_t *urb_alloc(size_t data_buffer_size, int num_isoc_packets) if (urb == NULL || data_buffer == NULL) { goto err; } + +#if CONFIG_IDF_TARGET_LINUX + // heap_caps_get_allocated_size() return 0 on Linux target + const size_t allocated_size = data_buffer_size; +#else + const size_t allocated_size = heap_caps_get_allocated_size(data_buffer); +#endif + // Cast as dummy transfer so that we can assign to const fields usb_transfer_dummy_t *dummy_transfer = (usb_transfer_dummy_t *)&urb->transfer; dummy_transfer->data_buffer = data_buffer; - dummy_transfer->data_buffer_size = heap_caps_get_allocated_size(data_buffer); + dummy_transfer->data_buffer_size = allocated_size; dummy_transfer->num_isoc_packets = num_isoc_packets; return urb; err: diff --git a/tools/mocks/usb/CMakeLists.txt b/tools/mocks/usb/CMakeLists.txt index 2ae39ff7b50..0e0d0b0e0ce 100644 --- a/tools/mocks/usb/CMakeLists.txt +++ b/tools/mocks/usb/CMakeLists.txt @@ -8,6 +8,7 @@ idf_component_mock(INCLUDE_DIRS "${original_usb_dir}/include" "${original_usb_dir}/include/esp_private" "${original_usb_dir}/include/usb" "${original_usb_dir}/private_include" + "include" MOCK_HEADER_FILES ${original_usb_dir}/include/usb/usb_host.h ${original_usb_dir}/include/esp_private/usb_phy.h REQUIRES freertos) @@ -16,3 +17,8 @@ idf_component_mock(INCLUDE_DIRS "${original_usb_dir}/include" # We do not mock usb_helpers. We use the original implementation. # This way, we can test Class drivers descriptor parsing target_sources(${COMPONENT_LIB} PRIVATE "${original_usb_dir}/usb_helpers.c") +# Original implementation of usb_private.c to allocate memory for transfers +target_sources(${COMPONENT_LIB} PRIVATE "${original_usb_dir}/usb_private.c") + +# Add the extra src files for USB device mocking +target_sources(${COMPONENT_LIB} PRIVATE "mock_add_usb_device.c") diff --git a/tools/mocks/usb/include/mock_add_usb_device.h b/tools/mocks/usb/include/mock_add_usb_device.h new file mode 100644 index 00000000000..bf49e3bfa86 --- /dev/null +++ b/tools/mocks/usb/include/mock_add_usb_device.h @@ -0,0 +1,294 @@ +/* + * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#pragma once + +#include +#include "usb_host.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @brief Add mocked USB device to device list + * + * @param[in] dev_address device address + * @param[in] dev_desc device descriptor + * @param[in] config_desc configuration descriptor + * + * @return + * - ESP_OK: Mocked device added successfully + * - ESP_ERR_INVALID_ARG: Invalid input argument(s) + */ +esp_err_t usb_host_mock_add_device(uint8_t dev_address, const usb_device_desc_t *dev_desc, const usb_config_desc_t *config_desc); + +/** + * @brief Get number of mocked USB devices in device list + * + * @return number of devices in devices list + */ +int usb_host_mock_get_devs_count(void); + +/** + * @brief Print mocked devices info + * @note if 0xFF is passed as dev_address, function prints all the mocked devices + * + * - printf all info about mocked device(s) + * - device handler, device address, opened status, device descriptor, configuration descriptor + * + * @param[in] dev_address device address (if 0xFF is passed as dev_address, function prints all the mocked devices) + * + * @return + * - ESP_OK: Mocked device found and info printed + * - ESP_ERR_INVALID_SIZE: Mocked devices list empty + * - ESP_ERR_INVALID_ARG: Mocked device does not exist at the provided address + */ +esp_err_t usb_host_mock_print_mocked_devices(uint8_t dev_address); + +/** + * @brief Initialize mocked devices list before use + */ +void usb_host_mock_dev_list_init(void); + +/** + * @brief Get Mocked device config descriptor by address + * + * @param[in] dev_address device address + * @param[in] config_desc configuration descriptor + * + * @return + * - ESP_OK: Configuration descriptor successfully provided + * - ESP_ERR_INVALID_ARG: Invalid input argument(s), or Mocked device does not exist at the provided address + * - ESP_ERR_INVALID_SIZE: Mocked devices list empty + */ +esp_err_t usb_host_mock_get_config_descriptor_by_address(uint8_t dev_address, const usb_config_desc_t **config_desc); + +/** + * @brief Get Mocked device device descriptor by address + * + * @param[in] dev_address device address + * @param[in] config_desc device descriptor + * + * @return + * - ESP_OK: Device descriptor successfully provided + * - ESP_ERR_INVALID_ARG: Invalid input argument(s), or Mocked device does not exist at the provided address + * - ESP_ERR_INVALID_SIZE: Mocked devices list empty + */ +esp_err_t usb_host_mock_get_device_descriptor_by_address(uint8_t dev_address, const usb_device_desc_t **device_desc); + +// ------------------------------------------------- CMock callback functions ------------------------------------------ + +/** + * @brief Allocate a transfer object + * @note CMock callback function, registered to usb_host_transfer_alloc() + * + * @param[in] data_buffer_size Size of the transfer's data buffer + * @param[in] num_isoc_packets Number of isochronous packets in transfer (set to 0 for non-isochronous transfers) + * @param[out] transfer Transfer object + * @param[out] call_count Call count of the callback function (CMock mandatory argument) + * + * @return + * - ESP_OK: Transfer object allocated successfully + * - ESP_ERR_NO_MEM: Insufficient memory + */ +esp_err_t usb_host_transfer_alloc_mock_callback(size_t data_buffer_size, int num_isoc_packets, usb_transfer_t **transfer, int call_count); + +/** + * @brief Free a transfer object + * @note CMock callback function, registered to usb_host_transfer_free() + * + * @param[in] transfer Transfer object + * @param[out] call_count Call count of the callback function (CMock mandatory argument) + * + * @return + * - ESP_OK: Transfer object freed successfully + */ +esp_err_t usb_host_transfer_free_mock_callback(usb_transfer_t *transfer, int call_count); + +/** + * @brief Register Mocked USB Host client + * @note CMock callback function, registered to usb_host_client_register() + * + * @param[in] client_config USB Host client config + * @param[out] client_hdl_ret USB Host client handle + * @param[out] call_count Call count of the callback function (CMock mandatory argument) + * + * @return + * - ESP_OK: Client registered successfully + * - ESP_ERR_INVALID_ARG: Invalid argument + * - ESP_ERR_NO_MEM: Insufficient memory + */ +esp_err_t usb_host_client_register_mock_callback(const usb_host_client_config_t *client_config, usb_host_client_handle_t *client_hdl_ret, int call_count); + +/** + * @brief Mocked USB Host Library client processing function + * @note CMock callback function, registered to usb_host_client_handle_events() + * + * - This function just blocks indefinitely, so the cdc_acm_client_task() does not loop + * - If we only had usb_host_client_handle_events_ExpectAnyArgsAndReturn(ESP_OK) instead of this callback, the cdc_acm_client_task() would loop infinitely + * - The only event implemented (for now) is client unblock, while uninstalling CDC-ACM driver + * + * @note This function can block + * @param[in] client_hdl Client handle + * @param[in] timeout_ticks Timeout in ticks to wait for an event to occur + * @param[out] call_count Call count of the callback function (CMock mandatory argument) + * + * @return + * - ESP_OK: No event to be handled + * - ESP_ERR_INVALID_ARG: Invalid argument + * - ESP_ERR_TIMEOUT: Semaphore waiting for events has timed out + */ +esp_err_t usb_host_client_handle_events_mock_callback(usb_host_client_handle_t client_hdl, TickType_t timeout_ticks, int call_count); + +/** + * @brief Unblock a Mocked client + * @note CMock callback function, registered to usb_host_client_unblock() + * + * @param[in] client_hdl Client handle + * @param[out] call_count Call count of the callback function (CMock mandatory argument) + * + * @return + * - ESP_OK: Client unblocked successfully + * - ESP_ERR_INVALID_ARG: Invalid argument + */ +esp_err_t usb_host_client_unblock_mock_callback(usb_host_client_handle_t client_hdl, int call_count); + +/** + * @brief Deregister a Mocked client + * @note CMock callback function, registered to usb_host_client_deregister() + * + * @param[in] client_hdl Client handle + * @param[out] call_count Call count of the callback function (CMock mandatory argument) + * + * @return + * - ESP_OK: Client deregistered successfully + * - ESP_ERR_INVALID_ARG: Invalid argument + */ +esp_err_t usb_host_client_deregister_mock_callback(usb_host_client_handle_t client_hdl, int call_count); + +/** + * @brief Open a device + * @note CMock callback function, registered to usb_host_device_open() + * + * @param[in] client_hdl Client handle + * @param[in] dev_address Device's address + * @param[out] dev_hdl_ret Device's handle + * @param[out] call_count Call count of the callback function (CMock mandatory argument) + * + * @return + * - ESP_OK: Device opened successfully + * - ESP_ERR_INVALID_ARG: Invalid argument + * - ESP_ERR_NOT_FOUND: Device with specified dev_address not found + */ +esp_err_t usb_host_device_open_mock_callback(usb_host_client_handle_t client_hdl, uint8_t dev_address, usb_device_handle_t *dev_hdl_ret, int call_count); + +/** + * @brief Close a device + * @note CMock callback function, registered to usb_host_device_close() + * + * @param[in] client_hdl Client handle + * @param[in] dev_hdl Device's handle + * @param[out] call_count Call count of the callback function (CMock mandatory argument) + * + * @return + * - ESP_OK: Device closed successfully + * - ESP_ERR_INVALID_ARG: Invalid argument + * - ESP_ERR_INVALID_STATE: Device was never opened + */ +esp_err_t usb_host_device_close_mock_callback(usb_host_client_handle_t client_hdl, usb_device_handle_t dev_hdl, int call_count); + +/** + * @brief Fill a list of device address + * @note CMock callback function, registered to usb_host_device_addr_list_fill() + * + * @param[in] list_len Length of the empty list + * @param[inout] dev_addr_list Empty list to be filled + * @param[out] num_dev_ret Number of devices + * @param[out] call_count Call count of the callback function (CMock mandatory argument) + * + * @return + * - ESP_OK: Device list filled successfully + * - ESP_ERR_INVALID_ARG: Invalid argument + */ +esp_err_t usb_host_device_addr_list_fill_mock_callback(int list_len, uint8_t *dev_addr_list, int *num_dev_ret, int call_count); + +/** + * @brief Get device's device descriptor + * @note CMock callback function, registered to usb_host_get_device_descriptor() + * + * @param[in] dev_hdl Device handle + * @param[out] device_desc Device descriptor + * @param[out] call_count Call count of the callback function (CMock mandatory argument) + * + * @return + * - ESP_OK: Device descriptor obtained successfully + * - ESP_ERR_INVALID_ARG: Invalid argument + */ +esp_err_t usb_host_get_device_descriptor_mock_callback(usb_device_handle_t dev_hdl, const usb_device_desc_t **device_desc, int call_count); + +/** + * @brief Get device's active configuration descriptor + * @note CMock callback function, registered to usb_host_get_active_config_descriptor() + * + * @param[in] dev_hdl Device handle + * @param[out] config_desc Configuration descriptor + * @param[out] call_count Call count of the callback function (CMock mandatory argument) + * + * @return + * - ESP_OK: Active configuration descriptor obtained successfully + * - ESP_ERR_INVALID_ARG: Invalid argument + */ +esp_err_t usb_host_get_active_config_descriptor_mock_callback(usb_device_handle_t dev_hdl, const usb_config_desc_t **config_desc, int call_count); + +/** + * @brief Submit data transfer successfully + * @note CMock callback function, registered to usb_host_transfer_submit() + * + * Transfer callback is called, transfer status marked as completed, correct number of transferred bytes + * + * @param[in] transfer Pointer to USB transfer + * @param[out] call_count Call count of the callback function (CMock mandatory argument) + * + * @return + * - ESP_OK: Transfer submitted + * - ESP_ERR_INVALID_ARG: Invalid input argument + */ +esp_err_t usb_host_transfer_submit_success_mock_callback(usb_transfer_t *transfer, int call_count); + +/** + * @brief Submit data transfer, but fail to deliver + * @note CMock callback function, registered to usb_host_transfer_submit() + * + * Transfer callback is called, transfer status marked as error, incorrect number of transferred bytes + * + * @param[in] transfer Pointer to USB transfer + * @param[out] call_count Call count of the callback function (CMock mandatory argument) + * + * @return + * - ESP_OK: Transfer submitted + * - ESP_ERR_INVALID_ARG: Invalid input argument + */ +esp_err_t usb_host_transfer_submit_invalid_response_mock_callback(usb_transfer_t *transfer, int call_count); + +/** + * @brief Submit data transfer, time the transfer out + * @note CMock callback function, registered to usb_host_transfer_submit() + * + * Transfer callback is not called, because transfer timeout is not implemented in the USB Host Library + * + * @param[in] transfer Pointer to USB transfer + * @param[out] call_count Call count of the callback function (CMock mandatory argument) + * + * @return + * - ESP_OK: Transfer submitted + * - ESP_ERR_INVALID_ARG: Invalid input argument + */ +esp_err_t usb_host_transfer_submit_timeout_mock_callback(usb_transfer_t *transfer, int call_count); + +#ifdef __cplusplus +} +#endif diff --git a/tools/mocks/usb/mock/mock_config.yaml b/tools/mocks/usb/mock/mock_config.yaml index bbca5f4e3c2..da27941d516 100644 --- a/tools/mocks/usb/mock/mock_config.yaml +++ b/tools/mocks/usb/mock/mock_config.yaml @@ -5,3 +5,4 @@ - return_thru_ptr - ignore - ignore_arg + - callback diff --git a/tools/mocks/usb/mock_add_usb_device.c b/tools/mocks/usb/mock_add_usb_device.c new file mode 100644 index 00000000000..b8a0e5fba94 --- /dev/null +++ b/tools/mocks/usb/mock_add_usb_device.c @@ -0,0 +1,376 @@ +/* + * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include "esp_log.h" +#include "usb_private.h" +#include "usb/usb_types_ch9.h" +#include "mock_add_usb_device.h" + +#include "freertos/FreeRTOS.h" +#include "freertos/semphr.h" + + +#define MOCK_CHECK(cond, ret_val) ({ \ + if (!(cond)) { \ + return (ret_val); \ + } \ +}) + +#define MOCK_CHECK_EMPTY_DEV_LIST ({ \ + if (!mocked_devices_count) { \ + ESP_LOGW(MOCK_TAG, "Mocked devices list empty"); \ + return ESP_ERR_INVALID_SIZE; \ + } \ +}) + +#define MAX_DEV_COUNT 128 +#define IS_VALID_ADDRESS(address) ((address) != 0xFF) +#define IS_EMPTY_ADDRESS(address) ((address) == 0xFF) + + +const char *MOCK_TAG_CB = "USB MOCK CB"; // Tag for callback functions +const char *MOCK_TAG = "USB MOCK"; // Tag for the rest of the functions + +typedef struct client_s client_t; +struct client_s { + struct { + SemaphoreHandle_t event_sem; + } constant; +}; + +/** + * @brief Mocked devices structure + */ +typedef struct { + int address; /*!< Device address */ + unsigned opened; /*!< Device opened status */ + const usb_device_desc_t *dev_desc; /*!< Device descriptor */ + const usb_config_desc_t *config_desc; /*!< Config descriptor */ +} device_list_t; + +static device_list_t device_list[MAX_DEV_COUNT]; +static unsigned mocked_devices_count = 0; + + +void usb_host_mock_dev_list_init(void) +{ + for(int index = 0; index < MAX_DEV_COUNT; index++) { + device_list[index].address = 0xFF; + device_list[index].opened = 0; + device_list[index].dev_desc = NULL; + device_list[index].config_desc = NULL; + } + mocked_devices_count = 0; +} + +int usb_host_mock_get_devs_count(void) +{ + return mocked_devices_count; +} + +esp_err_t usb_host_mock_add_device(uint8_t dev_address, const usb_device_desc_t *dev_desc, const usb_config_desc_t *config_desc) +{ + MOCK_CHECK(dev_address < MAX_DEV_COUNT && dev_desc != NULL && config_desc != NULL, ESP_ERR_INVALID_ARG); + + // Increase mocked_devices_count, only for new device addresses + if (IS_EMPTY_ADDRESS(device_list[dev_address].address)) { + mocked_devices_count++; + } + + // Fill device_list with new device parameters + device_list[dev_address].address = dev_address; + device_list[dev_address].opened = 0; + device_list[dev_address].dev_desc = dev_desc; + device_list[dev_address].config_desc = config_desc; + + return ESP_OK; +} + +/** + * @brief Print devices from device_list by index + * + * @param[in] index device index + */ +static void _print_mocked_device(int index) +{ + ESP_LOGI(MOCK_TAG, "Device handle = %p", (void*)(&device_list[index])); + ESP_LOGI(MOCK_TAG, "Device address = %d", device_list[index].address); + ESP_LOGI(MOCK_TAG, "Device opened by = %d clients", device_list[index].opened); + + usb_print_device_descriptor(device_list[index].dev_desc); + usb_print_config_descriptor(device_list[index].config_desc, NULL); + printf("\n"); +} + +esp_err_t usb_host_mock_print_mocked_devices(uint8_t dev_address) +{ + MOCK_CHECK_EMPTY_DEV_LIST; + + // dev_address is 0xFF, print all devices from device_list + if (IS_EMPTY_ADDRESS(dev_address)) { + for(int index = 0; index < MAX_DEV_COUNT; index++) { + if(IS_VALID_ADDRESS(device_list[index].address)) { + _print_mocked_device(index); + } + } + // Print only device at dev_address + } else { + if (IS_VALID_ADDRESS(device_list[dev_address].address)) { + _print_mocked_device(dev_address); + } else { + ESP_LOGE(MOCK_TAG, "Mocked device at address %d does not exist", dev_address); + return ESP_ERR_INVALID_ARG; + } + } + return ESP_OK; +} + +esp_err_t usb_host_mock_get_device_descriptor_by_address(uint8_t dev_address, const usb_device_desc_t **device_desc) +{ + MOCK_CHECK(device_desc != NULL && dev_address < MAX_DEV_COUNT, ESP_ERR_INVALID_ARG); + ESP_LOGD(MOCK_TAG_CB, "Get device descriptor by device address"); + MOCK_CHECK_EMPTY_DEV_LIST; + + if (IS_VALID_ADDRESS(device_list[dev_address].address)) { + *device_desc = device_list[dev_address].dev_desc; + } else { + ESP_LOGE(MOCK_TAG, "Mocked device at address %d does not exist", dev_address); + return ESP_ERR_INVALID_ARG; + } + + return ESP_OK; +} + +esp_err_t usb_host_mock_get_config_descriptor_by_address(uint8_t dev_address, const usb_config_desc_t **config_desc) +{ + MOCK_CHECK(config_desc != NULL && dev_address < MAX_DEV_COUNT, ESP_ERR_INVALID_ARG); + ESP_LOGD(MOCK_TAG_CB, "Get configuration descriptor by device address"); + MOCK_CHECK_EMPTY_DEV_LIST; + + if (IS_VALID_ADDRESS(device_list[dev_address].address)) { + *config_desc = device_list[dev_address].config_desc; + } else { + ESP_LOGE(MOCK_TAG, "Mocked device at address %d does not exist", dev_address); + return ESP_ERR_INVALID_ARG; + } + + return ESP_OK; +} + +// ------------------------------------------------- CMock callback functions ------------------------------------------ + +esp_err_t usb_host_transfer_alloc_mock_callback(size_t data_buffer_size, int num_isoc_packets, usb_transfer_t **transfer, int call_count) +{ + urb_t *urb = urb_alloc(data_buffer_size, num_isoc_packets); + if (urb == NULL) { + return ESP_ERR_NO_MEM; + } + *transfer = &urb->transfer; + + ESP_LOGD(MOCK_TAG_CB, "New transfer allocated: %p", *transfer); + return ESP_OK; +} + +esp_err_t usb_host_transfer_free_mock_callback(usb_transfer_t *transfer, int call_count) +{ + if (transfer == NULL) { + return ESP_OK; + } + + ESP_LOGD(MOCK_TAG_CB, "Transfer freed: %p", transfer); + urb_t *urb = __containerof(transfer, urb_t, transfer); + urb_free(urb); + return ESP_OK; +} + +esp_err_t usb_host_client_register_mock_callback(const usb_host_client_config_t *client_config, usb_host_client_handle_t *client_hdl_ret, int call_count) +{ + MOCK_CHECK(client_config != NULL && client_hdl_ret != NULL, ESP_ERR_INVALID_ARG); + + esp_err_t ret; + // Create client object + client_t *client_obj = (client_t*)calloc(1, sizeof(client_t)); + SemaphoreHandle_t event_sem = xSemaphoreCreateBinary(); + if (client_obj == NULL || event_sem == NULL) { + ret = ESP_ERR_NO_MEM; + goto alloc_err; + } + + client_obj->constant.event_sem = event_sem; + + ESP_LOGD(MOCK_TAG_CB, "USB Host client registered"); + + // Write back client handle + *client_hdl_ret = (usb_host_client_handle_t)client_obj; + ret = ESP_OK; + return ret; + +alloc_err: + if (event_sem) { + vSemaphoreDelete(event_sem); + } + free(client_obj); + return ret; +} + +esp_err_t usb_host_client_handle_events_mock_callback(usb_host_client_handle_t client_hdl, TickType_t timeout_ticks, int call_count) +{ + MOCK_CHECK(client_hdl != NULL, ESP_ERR_INVALID_ARG); + esp_err_t ret = (timeout_ticks == 0) ? ESP_OK : ESP_ERR_TIMEOUT; // We don't want to return ESP_ERR_TIMEOUT if we aren't blocking + client_t *client_obj = (client_t *)client_hdl; + + while (1) { + // Loop until there are no more events + if (xSemaphoreTake(client_obj->constant.event_sem, timeout_ticks) == pdFALSE) { + // Timed out waiting for semaphore or currently no events + break; + } + + ret = ESP_OK; + // Set timeout_ticks to 0 so that we can check for events again without blocking + timeout_ticks = 0; + } + return ret; +} + +esp_err_t usb_host_client_unblock_mock_callback(usb_host_client_handle_t client_hdl, int call_count) +{ + MOCK_CHECK(client_hdl != NULL, ESP_ERR_INVALID_ARG); + client_t *client_obj = (client_t *)client_hdl; + xSemaphoreGive(client_obj->constant.event_sem); + return ESP_OK; +} + +esp_err_t usb_host_client_deregister_mock_callback(usb_host_client_handle_t client_hdl, int call_count) +{ + MOCK_CHECK(client_hdl != NULL, ESP_ERR_INVALID_ARG); + client_t *client_obj = (client_t *)client_hdl; + + vSemaphoreDelete(client_obj->constant.event_sem); + free(client_obj); + return ESP_OK; +} + +esp_err_t usb_host_device_open_mock_callback(usb_host_client_handle_t client_hdl, uint8_t dev_address, usb_device_handle_t *dev_hdl_ret, int call_count) +{ + MOCK_CHECK(dev_address < MAX_DEV_COUNT && client_hdl != NULL && dev_hdl_ret != NULL, ESP_ERR_INVALID_ARG); + // Find a device in dev_list by dev_address + for (int index = 0; index < MAX_DEV_COUNT; index++) { + if(device_list[index].address == dev_address) { + + // We should check, if the device has not been opened by the same client + // But we are keeping this mock implementation simple + + // Device found in dev_list + *dev_hdl_ret = (usb_device_handle_t)(&device_list[index]); + device_list[index].opened++; + + return ESP_OK; + } + } + + // Device not found + ESP_LOGW(MOCK_TAG_CB, "Device not found: dev_address = %d", dev_address); + return ESP_ERR_NOT_FOUND; +} + +esp_err_t usb_host_device_close_mock_callback(usb_host_client_handle_t client_hdl, usb_device_handle_t dev_hdl, int call_count) +{ + MOCK_CHECK(dev_hdl != NULL && client_hdl != NULL, ESP_ERR_INVALID_ARG); + device_list_t* current_device = (device_list_t *) dev_hdl; + + if (current_device->opened == 0) { + // Device was never opened + ESP_LOGW(MOCK_TAG_CB, "Device was never opened: dev_address = %d", current_device->address); + return ESP_ERR_INVALID_STATE; + } + + // We should also check, if the device has been opened by this client + // But we are keeping this mock implementation simple + + // Closing the device + current_device->opened--; + ESP_LOGD(MOCK_TAG_CB, "Device closed: dev_address = %d, dev_hdl = %p", current_device->address, current_device); + return ESP_OK; +} + +esp_err_t usb_host_device_addr_list_fill_mock_callback(int list_len, uint8_t *dev_addr_list, int *num_dev_ret, int call_count) +{ + MOCK_CHECK(dev_addr_list != NULL && num_dev_ret != NULL, ESP_ERR_INVALID_ARG); + + int found_devices_count = 0; + for (int index = 0; index < MAX_DEV_COUNT; index++) { + if(IS_VALID_ADDRESS(device_list[index].address) && (found_devices_count < list_len)) { + dev_addr_list[found_devices_count++] = device_list[index].address; + } + } + + // Just print found devices + ESP_LOGD(MOCK_TAG_CB, "%d USB Devices found", found_devices_count); + for (int i = 0; i < found_devices_count; i++) { + ESP_LOGD(MOCK_TAG_CB, "dev_addr_list[%d] = %d", i, dev_addr_list[i]); + } + + *num_dev_ret = found_devices_count; + return ESP_OK; +} + +esp_err_t usb_host_get_device_descriptor_mock_callback(usb_device_handle_t dev_hdl, const usb_device_desc_t **device_desc, int call_count) +{ + MOCK_CHECK(dev_hdl != NULL && device_desc != NULL, ESP_ERR_INVALID_ARG); + ESP_LOGD(MOCK_TAG_CB, "Get device descriptor"); + + const device_list_t* current_device = (const device_list_t *) dev_hdl; + *device_desc = current_device->dev_desc; + return ESP_OK; +} + +esp_err_t usb_host_get_active_config_descriptor_mock_callback(usb_device_handle_t dev_hdl, const usb_config_desc_t **config_desc, int call_count) +{ + MOCK_CHECK(dev_hdl != NULL && config_desc != NULL, ESP_ERR_INVALID_ARG); + ESP_LOGD(MOCK_TAG_CB, "Get active config descriptor"); + + const device_list_t* current_device = (const device_list_t *) dev_hdl; + *config_desc = current_device->config_desc; + return ESP_OK; +} + +esp_err_t usb_host_transfer_submit_success_mock_callback(usb_transfer_t *transfer, int call_count) +{ + MOCK_CHECK(transfer != NULL, ESP_ERR_INVALID_ARG); + // Check that transfer and target endpoint are valid + MOCK_CHECK(transfer->device_handle != NULL, ESP_ERR_INVALID_ARG); // Target device must be set + MOCK_CHECK((transfer->bEndpointAddress & USB_B_ENDPOINT_ADDRESS_EP_NUM_MASK) != 0, ESP_ERR_INVALID_ARG); + transfer->callback(transfer); + transfer->status = USB_TRANSFER_STATUS_COMPLETED; + transfer->actual_num_bytes = transfer->num_bytes; + ESP_LOGD(MOCK_TAG_CB, "Mocked transfer submitted, buff len: %d, buff: %s", transfer->num_bytes, transfer->data_buffer); + return ESP_OK; +} + +esp_err_t usb_host_transfer_submit_invalid_response_mock_callback(usb_transfer_t *transfer, int call_count) +{ + MOCK_CHECK(transfer != NULL, ESP_ERR_INVALID_ARG); + // Check that transfer and target endpoint are valid + MOCK_CHECK(transfer->device_handle != NULL, ESP_ERR_INVALID_ARG); // Target device must be set + MOCK_CHECK((transfer->bEndpointAddress & USB_B_ENDPOINT_ADDRESS_EP_NUM_MASK) != 0, ESP_ERR_INVALID_ARG); + transfer->callback(transfer); + transfer->status = USB_TRANSFER_STATUS_ERROR; + transfer->actual_num_bytes = 0; + ESP_LOGD(MOCK_TAG_CB, "Mocked transfer submitted, buff len: %d, buff: %s", transfer->num_bytes, transfer->data_buffer); + ESP_LOGW(MOCK_TAG_CB, "Mocked transfer error"); + return ESP_OK; +} + +esp_err_t usb_host_transfer_submit_timeout_mock_callback(usb_transfer_t *transfer, int call_count) +{ + MOCK_CHECK(transfer != NULL, ESP_ERR_INVALID_ARG); + // Check that transfer and target endpoint are valid + MOCK_CHECK(transfer->device_handle != NULL, ESP_ERR_INVALID_ARG); // Target device must be set + MOCK_CHECK((transfer->bEndpointAddress & USB_B_ENDPOINT_ADDRESS_EP_NUM_MASK) != 0, ESP_ERR_INVALID_ARG); + return ESP_OK; +} From d75fdc74e8d6e0921a145e30174ab146bfd21bec Mon Sep 17 00:00:00 2001 From: Marius Vikhammer Date: Wed, 11 Dec 2024 17:48:02 +0800 Subject: [PATCH 080/118] ci(docs): revert d98e77a4a7 to simplify CI --- .gitlab/ci/common.yml | 2 +- .gitlab/ci/docs.yml | 72 ++++++++++++------------------------------- 2 files changed, 20 insertions(+), 54 deletions(-) diff --git a/.gitlab/ci/common.yml b/.gitlab/ci/common.yml index b655e651478..d8f1091db1a 100644 --- a/.gitlab/ci/common.yml +++ b/.gitlab/ci/common.yml @@ -6,9 +6,9 @@ stages: - pre_check - build - assign_test + - build_doc - target_test - host_test - - build_doc - test_deploy - deploy - post_deploy diff --git a/.gitlab/ci/docs.yml b/.gitlab/ci/docs.yml index 5faea6d96be..f66eae3d591 100644 --- a/.gitlab/ci/docs.yml +++ b/.gitlab/ci/docs.yml @@ -37,25 +37,16 @@ .if-dev-push: &if-dev-push if: '$CI_COMMIT_REF_NAME != "master" && $CI_COMMIT_BRANCH !~ /^release\/v/ && $CI_COMMIT_TAG !~ /^v\d+\.\d+(\.\d+)?($|-)/ && $CI_COMMIT_TAG !~ /^qa-test/ && ($CI_PIPELINE_SOURCE == "push" || $CI_PIPELINE_SOURCE == "merge_request_event")' -.if-schedule: &if-schedule - if: '$CI_PIPELINE_SOURCE == "schedule"' - .doc-rules:build:docs-full: rules: - <<: *if-qa-test-tag when: never - - <<: *if-schedule + - <<: *if-protected - <<: *if-label-build_docs - <<: *if-label-docs_full - <<: *if-dev-push changes: *patterns-docs-full -.doc-rules:build:docs-full-prod: - rules: - - <<: *if-qa-test-tag - when: never - - <<: *if-protected-no_label - .doc-rules:build:docs-partial: rules: - <<: *if-qa-test-tag @@ -92,13 +83,14 @@ check_docs_lang_sync: stage: build_doc tags: - build_docs + needs: + - job: fast_template_app + artifacts: false + optional: true script: - if [ -n "${BREATHE_ALT_INSTALL_URL}" ]; then pip uninstall -y breathe && pip install -U ${BREATHE_ALT_INSTALL_URL}; fi - cd docs - build-docs -t $DOCTGT -bs $DOC_BUILDERS -l $DOCLANG build - artifacts: - expire_in: 4 days - when: always parallel: matrix: - DOCLANG: ["en", "zh_CN"] @@ -119,26 +111,12 @@ build_docs_html_full: extends: - .build_docs_template - .doc-rules:build:docs-full - needs: - - job: fast_template_app - artifacts: false - optional: true - artifacts: - paths: - - docs/_build/*/*/*.txt - - docs/_build/*/*/html/* - variables: - DOC_BUILDERS: "html" - -build_docs_html_full_prod: - extends: - - .build_docs_template - - .doc-rules:build:docs-full-prod - dependencies: [] # Stop build_docs jobs from downloading all previous job's artifacts artifacts: + when: always paths: - docs/_build/*/*/*.txt - docs/_build/*/*/html/* + expire_in: 4 days variables: DOC_BUILDERS: "html" @@ -146,14 +124,12 @@ build_docs_html_partial: extends: - .build_docs_template - .doc-rules:build:docs-partial - needs: - - job: fast_template_app - artifacts: false - optional: true artifacts: + when: always paths: - docs/_build/*/*/*.txt - docs/_build/*/*/html/* + expire_in: 4 days variables: DOC_BUILDERS: "html" parallel: @@ -167,26 +143,12 @@ build_docs_pdf: extends: - .build_docs_template - .doc-rules:build:docs-full - needs: - - job: fast_template_app - artifacts: false - optional: true - allow_failure: true # TODO IDFCI-2216 artifacts: + when: always paths: - docs/_build/*/*/latex/* - variables: - DOC_BUILDERS: "latex" - -build_docs_pdf_prod: - extends: - - .build_docs_template - - .doc-rules:build:docs-full-prod - dependencies: [] # Stop build_docs jobs from downloading all previous job's artifacts + expire_in: 4 days allow_failure: true # TODO IDFCI-2216 - artifacts: - paths: - - docs/_build/*/*/latex/* variables: DOC_BUILDERS: "latex" @@ -234,12 +196,13 @@ deploy_docs_production: # The DOCS_PROD_* variables used by this job are "Protected" so these branches must all be marked "Protected" in Gitlab settings extends: - .deploy_docs_template - - .doc-rules:build:docs-full-prod + rules: + - <<: *if-protected-no_label stage: post_deploy dependencies: # set dependencies to null to avoid missing artifacts issue needs: # ensure runs after push_to_github succeeded - - build_docs_html_full_prod - - build_docs_pdf_prod + - build_docs_html_full + - build_docs_pdf - job: push_to_github artifacts: false variables: @@ -254,16 +217,19 @@ deploy_docs_production: check_doc_links: extends: - .build_docs_template - - .doc-rules:build:docs-full-prod + rules: + - <<: *if-protected-no_label stage: post_deploy needs: - job: deploy_docs_production artifacts: false tags: ["build", "amd64", "internet"] artifacts: + when: always paths: - docs/_build/*/*/*.txt - docs/_build/*/*/linkcheck/*.txt + expire_in: 1 week allow_failure: true script: - cd docs From 5cc3c09a152394f4727f2dfde6210c088f85d27f Mon Sep 17 00:00:00 2001 From: WanqQixiang Date: Tue, 17 Dec 2024 10:16:38 +0800 Subject: [PATCH 081/118] fix(openthread): Fix CI failure of ot_trel example build --- .../include/protocol_examples_thread_config.h | 10 ++++++++++ examples/openthread/ot_br/sdkconfig.defaults | 3 +++ examples/openthread/ot_trel/sdkconfig.defaults | 3 +++ 3 files changed, 16 insertions(+) diff --git a/examples/common_components/protocol_examples_common/include/protocol_examples_thread_config.h b/examples/common_components/protocol_examples_common/include/protocol_examples_thread_config.h index 306a9270cbf..532f828b65f 100644 --- a/examples/common_components/protocol_examples_common/include/protocol_examples_thread_config.h +++ b/examples/common_components/protocol_examples_common/include/protocol_examples_thread_config.h @@ -66,6 +66,11 @@ .intr_pin = CONFIG_EXAMPLE_THREAD_SPI_INTR_PIN, \ }, \ } +#else +#define ESP_OPENTHREAD_DEFAULT_RADIO_CONFIG() \ + { \ + .radio_mode = RADIO_MODE_TREL, \ + } #endif #if CONFIG_OPENTHREAD_CONSOLE_TYPE_UART @@ -95,6 +100,11 @@ .host_connection_mode = HOST_CONNECTION_MODE_CLI_USB, \ .host_usb_config = USB_SERIAL_JTAG_DRIVER_CONFIG_DEFAULT(), \ } +#else +#define ESP_OPENTHREAD_DEFAULT_HOST_CONFIG() \ + { \ + .host_connection_mode = HOST_CONNECTION_MODE_NONE, \ + } #endif #define ESP_OPENTHREAD_DEFAULT_PORT_CONFIG() \ diff --git a/examples/openthread/ot_br/sdkconfig.defaults b/examples/openthread/ot_br/sdkconfig.defaults index 619ab0f7e78..2b17031c2bf 100644 --- a/examples/openthread/ot_br/sdkconfig.defaults +++ b/examples/openthread/ot_br/sdkconfig.defaults @@ -47,6 +47,9 @@ CONFIG_LWIP_IPV6_AUTOCONFIG=y CONFIG_MDNS_MULTIPLE_INSTANCE=y # end of mDNS +# Example connect +CONFIG_EXAMPLE_CONNECT_THREAD=n + # # ESP System Settings # diff --git a/examples/openthread/ot_trel/sdkconfig.defaults b/examples/openthread/ot_trel/sdkconfig.defaults index 99f65081b92..07de5fdbf96 100644 --- a/examples/openthread/ot_trel/sdkconfig.defaults +++ b/examples/openthread/ot_trel/sdkconfig.defaults @@ -41,3 +41,6 @@ CONFIG_LWIP_IPV6_AUTOCONFIG=y # Configurations for optimizing the size of firmware # CONFIG_COMPILER_OPTIMIZATION_SIZE=y + +# Example connect +CONFIG_EXAMPLE_CONNECT_THREAD=n From 611e3fcb79727626f0da5f5c438bbda37b13470f Mon Sep 17 00:00:00 2001 From: Armando Date: Tue, 17 Dec 2024 11:35:42 +0800 Subject: [PATCH 082/118] fix(adc): fixed adc_cali_check_scheme wrong return on c2/h2/c6 --- components/esp_adc/adc_cali.c | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/components/esp_adc/adc_cali.c b/components/esp_adc/adc_cali.c index 89558f28d77..16e6eeaccdc 100644 --- a/components/esp_adc/adc_cali.c +++ b/components/esp_adc/adc_cali.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2020-2022 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2020-2024 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -15,6 +15,7 @@ #include "hal/adc_types.h" #include "esp_adc/adc_cali.h" #include "adc_cali_interface.h" +#include "adc_cali_schemes.h" const __attribute__((unused)) static char *TAG = "adc_cali"; @@ -22,9 +23,9 @@ esp_err_t adc_cali_check_scheme(adc_cali_scheme_ver_t *scheme_mask) { ESP_RETURN_ON_FALSE(scheme_mask, ESP_ERR_INVALID_ARG, TAG, "invalid argument: null pointer"); *scheme_mask = 0; -#if CONFIG_IDF_TARGET_ESP32 || CONFIG_IDF_TARGET_ESP32S2 +#if ADC_CALI_SCHEME_LINE_FITTING_SUPPORTED *scheme_mask |= ADC_CALI_SCHEME_VER_LINE_FITTING; -#elif CONFIG_IDF_TARGET_ESP32C3 || CONFIG_IDF_TARGET_ESP32S3 +#elif ADC_CALI_SCHEME_CURVE_FITTING_SUPPORTED *scheme_mask |= ADC_CALI_SCHEME_VER_CURVE_FITTING; #endif From d9f0e1201c98bc272138487aef1c20612dd442d9 Mon Sep 17 00:00:00 2001 From: Wei Yu Han Date: Tue, 17 Dec 2024 12:03:43 +0800 Subject: [PATCH 083/118] docs(ble): Added BLE Qualification Information to API Guides --- docs/conf_common.py | 3 +- docs/en/api-guides/ble/ble-qualification.rst | 78 +++++++++++++++++++ docs/en/api-guides/ble/index.rst | 7 +- docs/en/api-guides/classic-bt/index.rst | 6 +- .../api-guides/ble/ble-qualification.rst | 78 +++++++++++++++++++ docs/zh_CN/api-guides/ble/index.rst | 7 +- docs/zh_CN/api-guides/classic-bt/index.rst | 6 +- 7 files changed, 172 insertions(+), 13 deletions(-) create mode 100644 docs/en/api-guides/ble/ble-qualification.rst create mode 100644 docs/zh_CN/api-guides/ble/ble-qualification.rst diff --git a/docs/conf_common.py b/docs/conf_common.py index 9bcfa2ac16f..7892e2c07bd 100644 --- a/docs/conf_common.py +++ b/docs/conf_common.py @@ -27,11 +27,12 @@ 'api-guides/ble/overview.rst', 'api-guides/ble/ble-feature-support-status.rst', 'api-guides/ble/host-feature-support-status.rst', - 'api-reference/bluetooth/bt_le.rst', + 'api-guides/ble/ble-qualification.rst', 'api-guides/ble/get-started/ble-introduction.rst', 'api-guides/ble/get-started/ble-device-discovery.rst', 'api-guides/ble/get-started/ble-connection.rst', 'api-guides/ble/get-started/ble-data-exchange.rst', + 'api-reference/bluetooth/bt_le.rst', 'api-reference/bluetooth/esp_gap_ble.rst', 'api-reference/bluetooth/esp_gatt_defs.rst', 'api-reference/bluetooth/esp_gatts.rst', diff --git a/docs/en/api-guides/ble/ble-qualification.rst b/docs/en/api-guides/ble/ble-qualification.rst new file mode 100644 index 00000000000..62668e99196 --- /dev/null +++ b/docs/en/api-guides/ble/ble-qualification.rst @@ -0,0 +1,78 @@ +Bluetooth\ :sup:`®` SIG Qualification +====================================== + +:link_to_translation:`zh_CN:[中文]` + +Controller +^^^^^^^^^^^ + +The table below shows the latest qualification for Espressif Bluetooth LE Controller on each chip. For the qualification of Espressif modules, please check the `SIG Qualification Workspace `__. + +.. table:: + :widths: 70 20 10 + + +-----------------------------------------------------------------------+-------------------------------------------+------------------------------------------+ + | .. centered:: Chip Name |.. centered:: Design Number / |.. centered:: Specification | + | |.. centered:: Qualified Design ID [1]_ |.. centered:: Version [2]_ | + +=======================================================================+===========================================+==========================================+ + |ESP32 | | | + | |.. centered:: |141661| |.. centered:: 5.0 | + |(Bluetooth LE Mode) | | | + +-----------------------------------------------------------------------+-------------------------------------------+------------------------------------------+ + |ESP32 | | | + | |.. centered:: |147845| |.. centered:: 4.2 | + |(Dual Mode: Bluetooth Classic & Bluetooth LE) | | | + +-----------------------------------------------------------------------+-------------------------------------------+------------------------------------------+ + |ESP32-C2 (ESP8684) |.. centered:: |194009| |.. centered:: 5.3 | + +-----------------------------------------------------------------------+-------------------------------------------+------------------------------------------+ + |ESP32-C3 |.. centered:: |239440| |.. centered:: 5.4 | + +-----------------------------------------------------------------------+-------------------------------------------+------------------------------------------+ + |ESP32-C5 |.. centered:: |Q331318| |.. centered:: 6.0 | + +-----------------------------------------------------------------------+-------------------------------------------+------------------------------------------+ + |ESP32-C6 |.. centered:: |199258| |.. centered:: 5.3 | + +-----------------------------------------------------------------------+-------------------------------------------+------------------------------------------+ + |ESP32-C61 |.. centered:: |Q331318| |.. centered:: 6.0 | + +-----------------------------------------------------------------------+-------------------------------------------+------------------------------------------+ + |ESP32-S3 |.. centered:: |239440| |.. centered:: 5.4 | + +-----------------------------------------------------------------------+-------------------------------------------+------------------------------------------+ + |ESP32-H2 |.. centered:: |Q331318| |.. centered:: 6.0 | + +-----------------------------------------------------------------------+-------------------------------------------+------------------------------------------+ + + +Host +^^^^^^ + +The table below shows the latest qualification for Espressif Bluetooth LE Host. + +.. list-table:: + :width: 100% + :widths: auto + :header-rows: 1 + + * - .. centered:: Host + - .. centered:: Design Number / Qualified Design ID [1]_ + - .. centered:: Specification Version [2]_ + * - ESP-Bluedroid + - .. centered:: `198312 `__ + - .. centered:: 5.3 + * - ESP-NimBLE + - .. centered:: `141499 `__ + - .. centered:: 5.1 + +.. |141661| replace:: `141661 `__ +.. |147845| replace:: `147845 `__ +.. |239440| replace:: `239440 `__ +.. |194009| replace:: `194009 `__ +.. |199258| replace:: `199258 `__ +.. |198312| replace:: `198312 `__ +.. |141499| replace:: `141499 `__ +.. |Q331318| replace:: `Q331318 `__ + + +.. [1] + Since 1 July 2024, the identifying number for a new qualified design has changed from Qualified Design ID (QDID) to `Design Number (DN) `_. + Please log in to the `Bluetooth SIG website `__ to view Qualified Product Details, such as Design Details, TCRL Version, and ICS Details (passed cases) and etc. + +.. [2] + Some features of the Bluetooth Core Specification are optional. Therefore, passing the certification for a specific specification version does not necessarily mean supporting all the features specified in that version. + Please refer to :doc:`Major Feature Support Status ` for the supported Bluetooth LE features on each chip. diff --git a/docs/en/api-guides/ble/index.rst b/docs/en/api-guides/ble/index.rst index d70166c9cb9..2b855e43a1e 100644 --- a/docs/en/api-guides/ble/index.rst +++ b/docs/en/api-guides/ble/index.rst @@ -1,6 +1,6 @@ -####################### -Bluetooth® Low Energy -####################### +################################ +Bluetooth\ :sup:`®` Low Energy +################################ :link_to_translation:`zh_CN:[中文]` @@ -12,6 +12,7 @@ Overview overview ble-feature-support-status + ble-qualification *************** Get Started diff --git a/docs/en/api-guides/classic-bt/index.rst b/docs/en/api-guides/classic-bt/index.rst index e6e9141c70c..b0b2e9dab35 100644 --- a/docs/en/api-guides/classic-bt/index.rst +++ b/docs/en/api-guides/classic-bt/index.rst @@ -1,6 +1,6 @@ -####################### -Bluetooth® Classic -####################### +############################## +Bluetooth\ :sup:`®` Classic +############################## :link_to_translation:`zh_CN:[中文]` diff --git a/docs/zh_CN/api-guides/ble/ble-qualification.rst b/docs/zh_CN/api-guides/ble/ble-qualification.rst new file mode 100644 index 00000000000..bf3f5761bb1 --- /dev/null +++ b/docs/zh_CN/api-guides/ble/ble-qualification.rst @@ -0,0 +1,78 @@ +蓝牙\ :sup:`®` SIG 认证 +================================ + +:link_to_translation:`en:[English]` + +控制器 (Controller) +^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +参考下表可知乐鑫各芯片上最新的低功耗蓝牙控制器认证信息。 有关乐鑫模组的认证信息，请参阅 `SIG Qualification Workspace `__ 。 + +.. table:: + :widths: 50 25 25 + + +-----------------------------------------------------------------------+-------------------------------------------+------------------------------------------+ + |.. centered:: 芯片名称 |.. centered:: Design Number / |.. centered:: 协议版本 [2]_ | + | |.. centered:: Qualified Design ID [1]_ | | + +=======================================================================+===========================================+==========================================+ + |ESP32 |.. centered:: |141661| |.. centered:: 5.0 | + |（低功耗蓝牙模式） | | | + +-----------------------------------------------------------------------+-------------------------------------------+------------------------------------------+ + |ESP32 |.. centered:: |147845| |.. centered:: 4.2 | + |（双模模式: 经典蓝牙 & 低功耗蓝牙） | | | + +-----------------------------------------------------------------------+-------------------------------------------+------------------------------------------+ + |ESP32-C2 (ESP8684) |.. centered:: |194009| |.. centered:: 5.3 | + +-----------------------------------------------------------------------+-------------------------------------------+------------------------------------------+ + |ESP32-C3 |.. centered:: |239440| |.. centered:: 5.4 | + +-----------------------------------------------------------------------+-------------------------------------------+------------------------------------------+ + |ESP32-C5 |.. centered:: |Q331318| |.. centered:: 6.0 | + +-----------------------------------------------------------------------+-------------------------------------------+------------------------------------------+ + |ESP32-C6 |.. centered:: |199258| |.. centered:: 5.3 | + +-----------------------------------------------------------------------+-------------------------------------------+------------------------------------------+ + |ESP32-C61 |.. centered:: |Q331318| |.. centered:: 6.0 | + +-----------------------------------------------------------------------+-------------------------------------------+------------------------------------------+ + |ESP32-S3 |.. centered:: |239440| |.. centered:: 5.4 | + +-----------------------------------------------------------------------+-------------------------------------------+------------------------------------------+ + |ESP32-H2 |.. centered:: |Q331318| |.. centered:: 6.0 | + +-----------------------------------------------------------------------+-------------------------------------------+------------------------------------------+ + + +主机 (Host) +^^^^^^^^^^^^^^^ + +参考下表可知最新的低功耗蓝牙主机的认证信息。 + +.. list-table:: + :width: 100% + :widths: auto + :header-rows: 1 + + * - .. centered:: 主机 (Host) + - .. centered:: Design Number / Qualified Design ID [1]_ + - .. centered:: 协议版本 [2]_ + * - ESP-Bluedroid + - .. centered:: `198312 `__ + - .. centered:: 5.3 + * - ESP-NimBLE + - .. centered:: `141499 `__ + - .. centered:: 5.1 + +.. |141661| replace:: `141661 `__ +.. |147845| replace:: `147845 `__ +.. |239440| replace:: `239440 `__ +.. |194009| replace:: `194009 `__ +.. |199258| replace:: `199258 `__ +.. |198312| replace:: `198312 `__ +.. |141499| replace:: `141499 `__ +.. |Q331318| replace:: `Q331318 `__ + + + + +.. [1] + 自 2024 年 7 月 1 日起，蓝牙 SIG 新认证的设计识别编号已从 Qualified Deign ID (QDID) 更改为 `Design Number (DN) `__。 + 请登录 `Bluetooth SIG 官方网站 `__ 以获取合格产品的详细信息，例如设计详情、TCRL 版本和 ICS 详情（通过的测试用例）等。 + +.. [2] + 蓝牙协议中的某些功能是可选的，因此通过某个协议版本的认证并不意味着支持该版本协议中规定的所有功能 + 请参阅 :doc:`主要功能支持状态 ` 以获取各个芯片当前支持的低功耗蓝牙功能。 diff --git a/docs/zh_CN/api-guides/ble/index.rst b/docs/zh_CN/api-guides/ble/index.rst index 4739ef2d6d0..c785a73c7e6 100644 --- a/docs/zh_CN/api-guides/ble/index.rst +++ b/docs/zh_CN/api-guides/ble/index.rst @@ -1,6 +1,6 @@ -################ -低功耗蓝牙® -################ +##################### +低功耗蓝牙\ :sup:`®` +##################### :link_to_translation:`en:[English]` @@ -12,6 +12,7 @@ overview ble-feature-support-status + ble-qualification ********** 快速入门 diff --git a/docs/zh_CN/api-guides/classic-bt/index.rst b/docs/zh_CN/api-guides/classic-bt/index.rst index 57aba1ca5dc..e8528ab946b 100644 --- a/docs/zh_CN/api-guides/classic-bt/index.rst +++ b/docs/zh_CN/api-guides/classic-bt/index.rst @@ -1,6 +1,6 @@ -########### -经典蓝牙® -########### +################### +经典蓝牙\ :sup:`®` +################### :link_to_translation:`en:[English]` From b16abb49ab41f4d644e3646aba32a18872a8a4b9 Mon Sep 17 00:00:00 2001 From: Xu Si Yu Date: Tue, 17 Dec 2024 16:32:54 +0800 Subject: [PATCH 084/118] feat(openthread): update build test rules --- examples/openthread/.build-test-rules.yml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/examples/openthread/.build-test-rules.yml b/examples/openthread/.build-test-rules.yml index 9b109179895..78cbde9eff3 100644 --- a/examples/openthread/.build-test-rules.yml +++ b/examples/openthread/.build-test-rules.yml @@ -11,6 +11,8 @@ - lwip - openthread depends_filepatterns: + - examples/common_components/protocol_examples_common/* + - examples/common_components/protocol_examples_common/**/* - examples/openthread/* - examples/openthread/**/* From 4772f51437b1da240625c3391aca2c89550570da Mon Sep 17 00:00:00 2001 From: David Cermak Date: Mon, 16 Dec 2024 18:05:32 +0100 Subject: [PATCH 085/118] feat(lwip): Declare additional POSIX API if available Add support for socketpair() directly from lwip sockets (if sock-utils included) Add support for gai_strerror() directly from lwip netdb.h (if sock-utils included) Closes https://github.com/espressif/esp-idf/issues/13772 Closes https://github.com/espressif/esp-idf/issues/14849 fix(lwip): prevent socket.h to spellcheck --- components/lwip/include/lwip/netdb.h | 16 +++++++++++++++ components/lwip/include/lwip/sockets.h | 28 +++++++++++++++++++++++--- 2 files changed, 41 insertions(+), 3 deletions(-) diff --git a/components/lwip/include/lwip/netdb.h b/components/lwip/include/lwip/netdb.h index 8a9ec4d3164..6fabf707aa3 100644 --- a/components/lwip/include/lwip/netdb.h +++ b/components/lwip/include/lwip/netdb.h @@ -16,6 +16,22 @@ extern "C" { #endif +#if LWIP_NETDB_HAS_GAI_STRERROR +/** + * @brief If `LWIP_NETDB_HAS_GAI_STRERROR=1` lwip can declare gai_strerror() + * since it will be defined in en external dependency of lwip + */ + +/** +* @brief Returns a string representing the `getaddrinfo()` error code. +* +* @param[in] ecode Error code returned by `getaddrinfo()`. +* +* @return A pointer to a string describing the error. +*/ +const char * gai_strerror(int ecode); +#endif + static inline int gethostbyname_r(const char *name, struct hostent *ret, char *buf, size_t buflen, struct hostent **result, int *h_errnop) { return lwip_gethostbyname_r(name, ret, buf, buflen, result, h_errnop); } static inline struct hostent *gethostbyname(const char *name) diff --git a/components/lwip/include/lwip/sockets.h b/components/lwip/include/lwip/sockets.h index b0f3a6febe4..12625ddfb36 100644 --- a/components/lwip/include/lwip/sockets.h +++ b/components/lwip/include/lwip/sockets.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2022-2024 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -12,6 +12,28 @@ extern "C" { #endif +#if LWIP_SOCKET_HAS_SOCKETPAIR +/** + * @brief If `LWIP_SOCKET_HAS_SOCKETPAIR=1` lwip can declare socketpair() + * since it will be defined in en external dependency of lwip + */ +#define AF_UNIX 1 +#define PF_LOCAL AF_UNIX +/** + * @brief Creates a pair of connected sockets. + * + * @param[in] domain Communication domain (e.g., PF_LOCAL). + * @param[in] type Socket type (e.g., SOCK_STREAM). + * @param[in] protocol Protocol to be used (usually 0). + * @param[out] sv Array of two integers to store the file descriptors of the created sockets. + * + * @return + * - 0 on success. + * - -1 on failure, with `errno` set to indicate the error. + */ +int socketpair(int domain, int type, int protocol, int sv[2]); +#endif + static inline int accept(int s,struct sockaddr *addr,socklen_t *addrlen) { return lwip_accept(s,addr,addrlen); } static inline int bind(int s,const struct sockaddr *name, socklen_t namelen) @@ -42,8 +64,8 @@ static inline ssize_t send(int s,const void *dataptr,size_t size,int flags) { return lwip_send(s,dataptr,size,flags); } static inline ssize_t sendmsg(int s,const struct msghdr *message,int flags) { return lwip_sendmsg(s,message,flags); } -static inline ssize_t sendto(int s,const void *dataptr,size_t size,int flags,const struct sockaddr *to,socklen_t tolen) -{ return lwip_sendto(s,dataptr,size,flags,to,tolen); } +static inline ssize_t sendto(int s,const void *dataptr,size_t size,int flags,const struct sockaddr *to,socklen_t to_len) +{ return lwip_sendto(s,dataptr,size,flags,to,to_len); } static inline int socket(int domain,int type,int protocol) { return lwip_socket(domain,type,protocol); } static inline const char *inet_ntop(int af, const void *src, char *dst, socklen_t size) From d66b6e2749f098369b8c5c236e38dd01497ee68f Mon Sep 17 00:00:00 2001 From: David Cermak Date: Tue, 17 Dec 2024 07:16:07 +0100 Subject: [PATCH 086/118] feat(hints): Add hints on using external sock utilities --- tools/idf_py_actions/hints.yml | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/tools/idf_py_actions/hints.yml b/tools/idf_py_actions/hints.yml index 4236b08a286..46b415e566f 100644 --- a/tools/idf_py_actions/hints.yml +++ b/tools/idf_py_actions/hints.yml @@ -455,3 +455,13 @@ - re: "Configuration descriptor larger than control transfer max length" hint: "Connected USB device has a large Configuration descriptor.\nTo increase the transfer size, go to 'idf.py menuconfig' -> 'Component config' -> 'USB-OTG' -> 'Largest size of transfers to/from default endpoints' and set appropriate size." + +- + re: "error: implicit declaration of function '(socketpair|gai_strerror|getifaddrs|freeifaddrs)'" + hint: "{}() is not supported in IDF.\nTo use a simplified implementation of this function, add a dependency to sock_utils library 'idf.py add-dependency espressif/sock_utils'" + match_to_output: True + +- + re: "undefined reference to `(socketpair|gai_strerror|gethostname|getnameinfo|pipe|getifaddrs|freeifaddrs)'" + hint: "{}() is not supported in IDF.\nTo use a simplified implementation of this function, add a dependency to sock_utils library 'idf.py add-dependency espressif/sock_utils'" + match_to_output: True From 3140ce06e8eba0fa80da16f1bd94d06d4bf92b49 Mon Sep 17 00:00:00 2001 From: "C.S.M" Date: Tue, 17 Dec 2024 11:06:14 +0800 Subject: [PATCH 087/118] fix(i2c_slave): Support 10-bit address on esp32 --- components/hal/esp32/include/hal/i2c_ll.h | 4 ++-- components/soc/esp32/include/soc/Kconfig.soc_caps.in | 4 ++++ components/soc/esp32/include/soc/soc_caps.h | 1 + 3 files changed, 7 insertions(+), 2 deletions(-) diff --git a/components/hal/esp32/include/hal/i2c_ll.h b/components/hal/esp32/include/hal/i2c_ll.h index dcc24d803fd..617eeda1490 100644 --- a/components/hal/esp32/include/hal/i2c_ll.h +++ b/components/hal/esp32/include/hal/i2c_ll.h @@ -325,8 +325,8 @@ static inline void i2c_ll_set_slave_addr(i2c_dev_t *hw, uint16_t slave_addr, boo hw->slave_addr.en_10bit = addr_10bit_en; if (addr_10bit_en) { uint16_t addr_14_7 = (slave_addr & 0xff) << 7; - uint8_t addr_6_0 = ((slave_addr & 0x300) >> 8) || 0x78; - hw->slave_addr.addr = addr_14_7 || addr_6_0; + uint8_t addr_6_0 = ((slave_addr & 0x300) >> 8) | 0x78; + hw->slave_addr.addr = addr_14_7 | addr_6_0; } else { hw->slave_addr.addr = slave_addr; } diff --git a/components/soc/esp32/include/soc/Kconfig.soc_caps.in b/components/soc/esp32/include/soc/Kconfig.soc_caps.in index c15f33fa61f..fddab15bd57 100644 --- a/components/soc/esp32/include/soc/Kconfig.soc_caps.in +++ b/components/soc/esp32/include/soc/Kconfig.soc_caps.in @@ -387,6 +387,10 @@ config SOC_I2C_SUPPORT_APB bool default y +config SOC_I2C_SUPPORT_10BIT_ADDR + bool + default y + config SOC_I2C_STOP_INDEPENDENT bool default y diff --git a/components/soc/esp32/include/soc/soc_caps.h b/components/soc/esp32/include/soc/soc_caps.h index 60b621eeba0..8d3f86a29d2 100644 --- a/components/soc/esp32/include/soc/soc_caps.h +++ b/components/soc/esp32/include/soc/soc_caps.h @@ -206,6 +206,7 @@ #define SOC_I2C_SUPPORT_SLAVE (1) #define SOC_I2C_SUPPORT_APB (1) +#define SOC_I2C_SUPPORT_10BIT_ADDR (1) // On ESP32, the stop bit should be independent, we can't put trans data and stop command together #define SOC_I2C_STOP_INDEPENDENT (1) From 04e06f87d0c5471f713a88b1a085517b58e28281 Mon Sep 17 00:00:00 2001 From: Jan Beran Date: Tue, 3 Dec 2024 09:52:16 +0100 Subject: [PATCH 088/118] ci(pre-commit): bump kconfig checker pre-commit version to 2.4.1 --- .pre-commit-config.yaml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/.pre-commit-config.yaml b/.pre-commit-config.yaml index 4f66a6d13fa..9c3cba871a2 100644 --- a/.pre-commit-config.yaml +++ b/.pre-commit-config.yaml @@ -243,6 +243,6 @@ repos: name: Lint rST files in docs folder using Sphinx Lint files: ^(docs/en|docs/zh_CN)/.*\.(rst|inc)$ - repo: https://github.com/espressif/esp-idf-kconfig.git - rev: v2.3.0 + rev: v2.4.1 hooks: - id: check-kconfig-files From 88b137c121f2be480beaa8f35efe39e1b1ef2352 Mon Sep 17 00:00:00 2001 From: Erhan Kurubas Date: Wed, 11 Dec 2024 15:40:24 +0100 Subject: [PATCH 089/118] fix(system): avoid unexcpected hp_sys_wdt reset --- components/esp_system/port/soc/esp32p4/system_internal.c | 2 -- 1 file changed, 2 deletions(-) diff --git a/components/esp_system/port/soc/esp32p4/system_internal.c b/components/esp_system/port/soc/esp32p4/system_internal.c index 86981428ea5..3b51c539474 100644 --- a/components/esp_system/port/soc/esp32p4/system_internal.c +++ b/components/esp_system/port/soc/esp32p4/system_internal.c @@ -39,7 +39,6 @@ void IRAM_ATTR esp_system_reset_modules_on_exit(void) } // Set Peripheral clk rst - SET_PERI_REG_MASK(HP_SYS_CLKRST_HP_RST_EN1_REG, HP_SYS_CLKRST_REG_RST_EN_TIMERGRP0); SET_PERI_REG_MASK(HP_SYS_CLKRST_HP_RST_EN1_REG, HP_SYS_CLKRST_REG_RST_EN_TIMERGRP1); SET_PERI_REG_MASK(HP_SYS_CLKRST_HP_RST_EN1_REG, HP_SYS_CLKRST_REG_RST_EN_STIMER); SET_PERI_REG_MASK(HP_SYS_CLKRST_HP_RST_EN0_REG, HP_SYS_CLKRST_REG_RST_EN_DUAL_MSPI_AXI); @@ -53,7 +52,6 @@ void IRAM_ATTR esp_system_reset_modules_on_exit(void) SET_PERI_REG_MASK(HP_SYS_CLKRST_HP_RST_EN2_REG, HP_SYS_CLKRST_REG_RST_EN_ADC); // Clear Peripheral clk rst - CLEAR_PERI_REG_MASK(HP_SYS_CLKRST_HP_RST_EN1_REG, HP_SYS_CLKRST_REG_RST_EN_TIMERGRP0); CLEAR_PERI_REG_MASK(HP_SYS_CLKRST_HP_RST_EN1_REG, HP_SYS_CLKRST_REG_RST_EN_TIMERGRP1); CLEAR_PERI_REG_MASK(HP_SYS_CLKRST_HP_RST_EN1_REG, HP_SYS_CLKRST_REG_RST_EN_STIMER); CLEAR_PERI_REG_MASK(HP_SYS_CLKRST_HP_RST_EN0_REG, HP_SYS_CLKRST_REG_RST_EN_DUAL_MSPI_AXI); From 276087c4d364baa041727015a67567b1b1aaa207 Mon Sep 17 00:00:00 2001 From: yiwenxiu Date: Tue, 17 Dec 2024 16:16:18 +0800 Subject: [PATCH 090/118] feat(openthread): change wlan to ethernet --- examples/openthread/ot_ci_function.py | 29 ++++++++++++++++++++++++--- 1 file changed, 26 insertions(+), 3 deletions(-) diff --git a/examples/openthread/ot_ci_function.py b/examples/openthread/ot_ci_function.py index adf19683e9c..ddcdfa28c40 100644 --- a/examples/openthread/ot_ci_function.py +++ b/examples/openthread/ot_ci_function.py @@ -2,6 +2,7 @@ # SPDX-License-Identifier: Unlicense OR CC0-1.0 # !/usr/bin/env python3 # this file defines some functions for testing cli and br under pytest framework +import os import re import socket import struct @@ -11,6 +12,7 @@ import netifaces import pexpect +import yaml from pytest_embedded_idf.dut import IdfDut @@ -256,9 +258,30 @@ def init_interface_ipv6_address() -> None: def get_host_interface_name() -> str: - interfaces = netifaces.interfaces() - interface_name = [s for s in interfaces if 'wl' in s][0] - return str(interface_name) + home_dir = os.path.expanduser('~') + config_path = os.path.join(home_dir, 'config', 'env_config.yml') + try: + if os.path.exists(config_path): + with open(config_path, 'r') as file: + config = yaml.safe_load(file) + interface_name = config.get('interface_name') + if interface_name: + if interface_name == 'eth0': + print( + f"Warning: 'eth0' is not recommended as a valid network interface. " + f"Please check and update the 'interface_name' in the configuration file: " + f'{config_path}' + ) + else: + return str(interface_name) + else: + print("Warning: Configuration file found but 'interface_name' is not defined.") + except Exception as e: + print(f'Error: Failed to read or parse {config_path}. Details: {e}') + if 'eth1' in netifaces.interfaces(): + return 'eth1' + + raise Exception('Warning: No valid network interface detected. Please check your configuration.') def clean_buffer(dut:IdfDut) -> None: From 5bbc767f2e7983bc6633f416a7629323ba64df23 Mon Sep 17 00:00:00 2001 From: Aleksei Apaseev Date: Mon, 16 Dec 2024 11:21:01 +0800 Subject: [PATCH 091/118] ci: make app path relative to IDF_PATH minimum free heap size log --- conftest.py | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/conftest.py b/conftest.py index d26b135c9b6..fe53fe82ad5 100644 --- a/conftest.py +++ b/conftest.py @@ -357,7 +357,7 @@ def _check_perf(operator: str, standard_value: float) -> None: @pytest.fixture -def log_minimum_free_heap_size(dut: IdfDut, config: str) -> t.Callable[..., None]: +def log_minimum_free_heap_size(dut: IdfDut, config: str, idf_path: str) -> t.Callable[..., None]: def real_func() -> None: res = dut.expect(r'Minimum free heap size: (\d+) bytes') logging.info( @@ -368,7 +368,7 @@ def real_func() -> None: '[target] {}\n' '[minimum_free_heap_size] {} Bytes\n' '------ heap size end ------'.format( - dut.app.app_path, + dut.app.app_path.replace(idf_path, '').lstrip('/\\'), os.path.basename(dut.app.app_path), config, dut.target, From f1b0c5dcb4e3669edb7e0e380bb930e35a4d3f9b Mon Sep 17 00:00:00 2001 From: Armando Date: Wed, 18 Dec 2024 11:30:51 +0800 Subject: [PATCH 092/118] feat(cache): added cache invalidate all ll apis --- components/hal/esp32c2/include/hal/cache_ll.h | 15 +++- components/hal/esp32c3/include/hal/cache_ll.h | 15 +++- components/hal/esp32c5/include/hal/cache_ll.h | 13 ++++ components/hal/esp32c6/include/hal/cache_ll.h | 15 +++- .../hal/esp32c61/include/hal/cache_ll.h | 13 ++++ components/hal/esp32h2/include/hal/cache_ll.h | 15 +++- components/hal/esp32p4/include/hal/cache_ll.h | 74 +++++++++++++++++++ components/hal/esp32s2/include/hal/cache_ll.h | 25 +++++++ components/hal/esp32s3/include/hal/cache_ll.h | 26 +++++++ 9 files changed, 207 insertions(+), 4 deletions(-) diff --git a/components/hal/esp32c2/include/hal/cache_ll.h b/components/hal/esp32c2/include/hal/cache_ll.h index ba192c98b60..50a39523029 100644 --- a/components/hal/esp32c2/include/hal/cache_ll.h +++ b/components/hal/esp32c2/include/hal/cache_ll.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2022-2024 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -149,6 +149,19 @@ static inline void cache_ll_invalidate_addr(uint32_t cache_level, cache_type_t t Cache_Invalidate_Addr(vaddr, size); } +/** + * @brief Invalidate all + * + * @param cache_level level of the cache + * @param type see `cache_type_t` + * @param cache_id id of the cache in this type and level + */ +__attribute__((always_inline)) +static inline void cache_ll_invalidate_all(uint32_t cache_level, cache_type_t type, uint32_t cache_id) +{ + Cache_Invalidate_ICache_All(); +} + /** * @brief Get Cache line size, in bytes * diff --git a/components/hal/esp32c3/include/hal/cache_ll.h b/components/hal/esp32c3/include/hal/cache_ll.h index 71022d0121f..748548079ae 100644 --- a/components/hal/esp32c3/include/hal/cache_ll.h +++ b/components/hal/esp32c3/include/hal/cache_ll.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2022-2024 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -152,6 +152,19 @@ static inline void cache_ll_invalidate_addr(uint32_t cache_level, cache_type_t t Cache_Invalidate_Addr(vaddr, size); } +/** + * @brief Invalidate all + * + * @param cache_level level of the cache + * @param type see `cache_type_t` + * @param cache_id id of the cache in this type and level + */ +__attribute__((always_inline)) +static inline void cache_ll_invalidate_all(uint32_t cache_level, cache_type_t type, uint32_t cache_id) +{ + Cache_Invalidate_ICache_All(); +} + /** * @brief Get Cache line size, in bytes * diff --git a/components/hal/esp32c5/include/hal/cache_ll.h b/components/hal/esp32c5/include/hal/cache_ll.h index 01b0a0097aa..642de58d117 100644 --- a/components/hal/esp32c5/include/hal/cache_ll.h +++ b/components/hal/esp32c5/include/hal/cache_ll.h @@ -129,6 +129,19 @@ static inline void cache_ll_invalidate_addr(uint32_t cache_level, cache_type_t t Cache_Invalidate_Addr(vaddr, size); } +/** + * @brief Invalidate all + * + * @param cache_level level of the cache + * @param type see `cache_type_t` + * @param cache_id id of the cache in this type and level + */ +__attribute__((always_inline)) +static inline void cache_ll_invalidate_all(uint32_t cache_level, cache_type_t type, uint32_t cache_id) +{ + Cache_Invalidate_All(); +} + /** * @brief Writeback cache supported addr * diff --git a/components/hal/esp32c6/include/hal/cache_ll.h b/components/hal/esp32c6/include/hal/cache_ll.h index 6aa203eb45e..683aa3205b8 100644 --- a/components/hal/esp32c6/include/hal/cache_ll.h +++ b/components/hal/esp32c6/include/hal/cache_ll.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2022-2024 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -127,6 +127,19 @@ static inline void cache_ll_invalidate_addr(uint32_t cache_level, cache_type_t t Cache_Invalidate_Addr(vaddr, size); } +/** + * @brief Invalidate all + * + * @param cache_level level of the cache + * @param type see `cache_type_t` + * @param cache_id id of the cache in this type and level + */ +__attribute__((always_inline)) +static inline void cache_ll_invalidate_all(uint32_t cache_level, cache_type_t type, uint32_t cache_id) +{ + Cache_Invalidate_ICache_All(); +} + /** * @brief Freeze Cache * diff --git a/components/hal/esp32c61/include/hal/cache_ll.h b/components/hal/esp32c61/include/hal/cache_ll.h index b324b26792a..b636530415e 100644 --- a/components/hal/esp32c61/include/hal/cache_ll.h +++ b/components/hal/esp32c61/include/hal/cache_ll.h @@ -128,6 +128,19 @@ static inline void cache_ll_invalidate_addr(uint32_t cache_level, cache_type_t t Cache_Invalidate_Addr(vaddr, size); } +/** + * @brief Invalidate all + * + * @param cache_level level of the cache + * @param type see `cache_type_t` + * @param cache_id id of the cache in this type and level + */ +__attribute__((always_inline)) +static inline void cache_ll_invalidate_all(uint32_t cache_level, cache_type_t type, uint32_t cache_id) +{ + Cache_Invalidate_All(); +} + /** * @brief Writeback cache supported addr * diff --git a/components/hal/esp32h2/include/hal/cache_ll.h b/components/hal/esp32h2/include/hal/cache_ll.h index 280e4a489a8..f628fdea235 100644 --- a/components/hal/esp32h2/include/hal/cache_ll.h +++ b/components/hal/esp32h2/include/hal/cache_ll.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2022-2024 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -127,6 +127,19 @@ static inline void cache_ll_invalidate_addr(uint32_t cache_level, cache_type_t t Cache_Invalidate_Addr(vaddr, size); } +/** + * @brief Invalidate all + * + * @param cache_level level of the cache + * @param type see `cache_type_t` + * @param cache_id id of the cache in this type and level + */ +__attribute__((always_inline)) +static inline void cache_ll_invalidate_all(uint32_t cache_level, cache_type_t type, uint32_t cache_id) +{ + Cache_Invalidate_ICache_All(); +} + /** * @brief Freeze Cache * diff --git a/components/hal/esp32p4/include/hal/cache_ll.h b/components/hal/esp32p4/include/hal/cache_ll.h index 5e1a07130ee..03a5658008c 100644 --- a/components/hal/esp32p4/include/hal/cache_ll.h +++ b/components/hal/esp32p4/include/hal/cache_ll.h @@ -556,6 +556,80 @@ static inline void cache_ll_invalidate_addr(uint32_t cache_level, cache_type_t t } } +/** + * @brief Invalidate L1 ICache all + * + * @param cache_id id of the cache in this type and level + */ +__attribute__((always_inline)) +static inline void cache_ll_l1_invalidate_icache_all(uint32_t cache_id) +{ + if (cache_id == 0) { + Cache_Invalidate_All(CACHE_MAP_L1_ICACHE_0); + } else if (cache_id == 1) { + Cache_Invalidate_All(CACHE_MAP_L1_ICACHE_1); + } else if (cache_id == CACHE_LL_ID_ALL) { + Cache_Invalidate_All(CACHE_MAP_L1_ICACHE_MASK); + } +} + +/** + * @brief Invalidate L1 DCache all + * + * @param cache_id id of the cache in this type and level + */ +__attribute__((always_inline)) +static inline void cache_ll_l1_invalidate_dcache_all(uint32_t cache_id) +{ + if (cache_id == 0 || cache_id == CACHE_LL_ID_ALL) { + Cache_Invalidate_All(CACHE_MAP_L1_DCACHE); + } +} + +/** + * @brief Invalidate L2 Cache all + * + * @param cache_id id of the cache in this type and level + */ +__attribute__((always_inline)) +static inline void cache_ll_l2_invalidate_cache_all(uint32_t cache_id) +{ + if (cache_id == 0 || cache_id == CACHE_LL_ID_ALL) { + Cache_Invalidate_All(CACHE_MAP_L2_CACHE); + } +} + +/** + * @brief Invalidate all + * + * @param cache_level level of the cache + * @param type see `cache_type_t` + * @param cache_id id of the cache in this type and level + */ +__attribute__((always_inline)) +static inline void cache_ll_invalidate_all(uint32_t cache_level, cache_type_t type, uint32_t cache_id) +{ + if (cache_level == 1 || cache_level == 2 || cache_level == CACHE_LL_LEVEL_ALL) { + switch (type) { + case CACHE_TYPE_INSTRUCTION: + cache_ll_l1_invalidate_icache_all(cache_id); + break; + case CACHE_TYPE_DATA: + cache_ll_l1_invalidate_dcache_all(cache_id); + break; + case CACHE_TYPE_ALL: + default: + cache_ll_l1_invalidate_icache_all(cache_id); + cache_ll_l1_invalidate_dcache_all(cache_id); + break; + } + } + + if (cache_level == 2 || cache_level == CACHE_LL_LEVEL_ALL) { + cache_ll_l2_invalidate_cache_all(cache_id); + } +} + /*------------------------------------------------------------------------------ * Writeback *----------------------------------------------------------------------------*/ diff --git a/components/hal/esp32s2/include/hal/cache_ll.h b/components/hal/esp32s2/include/hal/cache_ll.h index 16f7a7fe900..0bccb5d3d40 100644 --- a/components/hal/esp32s2/include/hal/cache_ll.h +++ b/components/hal/esp32s2/include/hal/cache_ll.h @@ -350,6 +350,31 @@ static inline void cache_ll_invalidate_addr(uint32_t cache_level, cache_type_t t Cache_Invalidate_Addr(vaddr, size); } +/** + * @brief Invalidate all + * + * @param cache_level level of the cache + * @param type see `cache_type_t` + * @param cache_id id of the cache in this type and level + */ +__attribute__((always_inline)) +static inline void cache_ll_invalidate_all(uint32_t cache_level, cache_type_t type, uint32_t cache_id) +{ + switch (type) + { + case CACHE_TYPE_DATA: + Cache_Invalidate_DCache_All(); + break; + case CACHE_TYPE_INSTRUCTION: + Cache_Invalidate_ICache_All(); + break; + default: //CACHE_TYPE_ALL + Cache_Invalidate_ICache_All(); + Cache_Invalidate_DCache_All(); + break; + } +} + /** * @brief Writeback cache supported addr * diff --git a/components/hal/esp32s3/include/hal/cache_ll.h b/components/hal/esp32s3/include/hal/cache_ll.h index 9ab5b7f5ff6..b76e9fc816e 100644 --- a/components/hal/esp32s3/include/hal/cache_ll.h +++ b/components/hal/esp32s3/include/hal/cache_ll.h @@ -360,6 +360,32 @@ static inline void cache_ll_invalidate_addr(uint32_t cache_level, cache_type_t t Cache_Invalidate_Addr(vaddr, size); } +/** + * @brief Invalidate all + * + * @param cache_level level of the cache + * @param type see `cache_type_t` + * @param cache_id id of the cache in this type and level + */ +__attribute__((always_inline)) +static inline void cache_ll_invalidate_all(uint32_t cache_level, cache_type_t type, uint32_t cache_id) +{ + switch (type) + { + case CACHE_TYPE_DATA: + Cache_Invalidate_DCache_All(); + break; + case CACHE_TYPE_INSTRUCTION: + Cache_Invalidate_ICache_All(); + break; + default: //CACHE_TYPE_ALL + Cache_Invalidate_ICache_All(); + Cache_Invalidate_DCache_All(); + break; + } +} + + /** * @brief Writeback cache supported addr * From 3cb2d9c3c639216afb17f12f3fca4675b0bde30c Mon Sep 17 00:00:00 2001 From: zhanghaipeng Date: Tue, 17 Dec 2024 19:42:06 +0800 Subject: [PATCH 093/118] fix(ble/blufi): Fixed blufi example security issue --- .../common/btc/profile/esp/blufi/blufi_prf.c | 24 ++++++++++++++++++- 1 file changed, 23 insertions(+), 1 deletion(-) diff --git a/components/bt/common/btc/profile/esp/blufi/blufi_prf.c b/components/bt/common/btc/profile/esp/blufi/blufi_prf.c index 2c7be2127f9..81bb0308299 100644 --- a/components/bt/common/btc/profile/esp/blufi/blufi_prf.c +++ b/components/bt/common/btc/profile/esp/blufi/blufi_prf.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2015-2021 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2015-2024 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -95,7 +95,29 @@ void btc_blufi_report_error(esp_blufi_error_state_t state) void btc_blufi_recv_handler(uint8_t *data, int len) { + if (len < sizeof(struct blufi_hdr)) { + BTC_TRACE_ERROR("%s invalid data length: %d", __func__, len); + btc_blufi_report_error(ESP_BLUFI_DATA_FORMAT_ERROR); + return; + } + struct blufi_hdr *hdr = (struct blufi_hdr *)data; + + // Verify if the received data length matches the expected length based on the BLUFI protocol + int target_data_len; + + if (BLUFI_FC_IS_CHECK(hdr->fc)) { + target_data_len = hdr->data_len + 4 + 2; // Data + (Type + Frame Control + Sequence Number + Data Length) + Checksum + } else { + target_data_len = hdr->data_len + 4; // Data + (Type + Frame Control + Sequence Number + Data Length) + } + + if (len != target_data_len) { + BTC_TRACE_ERROR("%s: Invalid data length: %d, expected: %d", __func__, len, target_data_len); + btc_blufi_report_error(ESP_BLUFI_DATA_FORMAT_ERROR); + return; + } + uint16_t checksum, checksum_pkt; int ret; From d84ccadf905bcaadcfbdee0b61e8875775ff716f Mon Sep 17 00:00:00 2001 From: zhanghaipeng Date: Wed, 10 Jul 2024 14:58:34 +0800 Subject: [PATCH 094/118] docs(ble/bluedroid): Optimize doc for registering BLE callback functions --- .../bt/host/bluedroid/api/include/api/esp_gap_ble_api.h | 2 ++ .../bt/host/bluedroid/api/include/api/esp_gattc_api.h | 2 ++ .../bt/host/bluedroid/api/include/api/esp_gatts_api.h | 2 ++ .../bluetooth/bluedroid/ble/gatt_client/main/gattc_demo.c | 6 +++--- .../bluetooth/bluedroid/ble/gatt_server/main/gatts_demo.c | 2 +- 5 files changed, 10 insertions(+), 4 deletions(-) diff --git a/components/bt/host/bluedroid/api/include/api/esp_gap_ble_api.h b/components/bt/host/bluedroid/api/include/api/esp_gap_ble_api.h index 83fea16a99c..bc096abef78 100644 --- a/components/bt/host/bluedroid/api/include/api/esp_gap_ble_api.h +++ b/components/bt/host/bluedroid/api/include/api/esp_gap_ble_api.h @@ -1593,6 +1593,8 @@ typedef void (* esp_gap_ble_cb_t)(esp_gap_ble_cb_event_t event, esp_ble_gap_cb_p * * @param[in] callback: callback function * + * @note Avoid performing time-consuming operations within the callback functions. + * * @return * - ESP_OK : success * - other : failed diff --git a/components/bt/host/bluedroid/api/include/api/esp_gattc_api.h b/components/bt/host/bluedroid/api/include/api/esp_gattc_api.h index a4fd3c9574b..fe6f2e3cd39 100644 --- a/components/bt/host/bluedroid/api/include/api/esp_gattc_api.h +++ b/components/bt/host/bluedroid/api/include/api/esp_gattc_api.h @@ -266,6 +266,8 @@ typedef void (* esp_gattc_cb_t)(esp_gattc_cb_event_t event, esp_gatt_if_t gattc_ * * @param[in] callback : pointer to the application callback function. * + * @note Avoid performing time-consuming operations within the callback functions. + * * @return * - ESP_OK: success * - other: failed diff --git a/components/bt/host/bluedroid/api/include/api/esp_gatts_api.h b/components/bt/host/bluedroid/api/include/api/esp_gatts_api.h index 72ff694e4b6..5793270afd8 100644 --- a/components/bt/host/bluedroid/api/include/api/esp_gatts_api.h +++ b/components/bt/host/bluedroid/api/include/api/esp_gatts_api.h @@ -289,6 +289,8 @@ typedef void (* esp_gatts_cb_t)(esp_gatts_cb_event_t event, esp_gatt_if_t gatts_ * @brief This function is called to register application callbacks * with BTA GATTS module. * + * @note Avoid performing time-consuming operations within the callback functions. + * * @return * - ESP_OK : success * - other : failed diff --git a/examples/bluetooth/bluedroid/ble/gatt_client/main/gattc_demo.c b/examples/bluetooth/bluedroid/ble/gatt_client/main/gattc_demo.c index 136a6c9722a..302f9bf66d4 100644 --- a/examples/bluetooth/bluedroid/ble/gatt_client/main/gattc_demo.c +++ b/examples/bluetooth/bluedroid/ble/gatt_client/main/gattc_demo.c @@ -493,15 +493,15 @@ void app_main(void) ESP_LOGE(GATTC_TAG, "%s enable bluetooth failed: %s", __func__, esp_err_to_name(ret)); return; } - - //register the callback function to the gap module + // Note: Avoid performing time-consuming operations within callback functions. + // Register the callback function to the gap module ret = esp_ble_gap_register_callback(esp_gap_cb); if (ret){ ESP_LOGE(GATTC_TAG, "%s gap register failed, error code = %x", __func__, ret); return; } - //register the callback function to the gattc module + // Register the callback function to the gattc module ret = esp_ble_gattc_register_callback(esp_gattc_cb); if(ret){ ESP_LOGE(GATTC_TAG, "%s gattc register failed, error code = %x", __func__, ret); diff --git a/examples/bluetooth/bluedroid/ble/gatt_server/main/gatts_demo.c b/examples/bluetooth/bluedroid/ble/gatt_server/main/gatts_demo.c index 3b4febab21b..eb88a8886bf 100644 --- a/examples/bluetooth/bluedroid/ble/gatt_server/main/gatts_demo.c +++ b/examples/bluetooth/bluedroid/ble/gatt_server/main/gatts_demo.c @@ -725,7 +725,7 @@ void app_main(void) ESP_LOGE(GATTS_TAG, "%s enable bluetooth failed: %s", __func__, esp_err_to_name(ret)); return; } - + // Note: Avoid performing time-consuming operations within callback functions. ret = esp_ble_gatts_register_callback(gatts_event_handler); if (ret){ ESP_LOGE(GATTS_TAG, "gatts register error, error code = %x", ret); From 7dabe54814588f4ac4c99be34356ff8638272236 Mon Sep 17 00:00:00 2001 From: gaoxu Date: Tue, 17 Dec 2024 16:54:54 +0800 Subject: [PATCH 095/118] feat(esp32h21): add H21 efuse files (stage3) --- components/efuse/esp32h21/esp_efuse_fields.c | 53 + .../efuse/esp32h21/esp_efuse_rtc_calib.c | 51 + components/efuse/esp32h21/esp_efuse_table.c | 1726 +++++++++++++++++ components/efuse/esp32h21/esp_efuse_table.csv | 209 ++ components/efuse/esp32h21/esp_efuse_utility.c | 208 ++ .../efuse/esp32h21/include/esp_efuse_chip.h | 82 + .../esp32h21/include/esp_efuse_rtc_calib.h | 75 + .../efuse/esp32h21/include/esp_efuse_table.h | 256 +++ .../private_include/esp_efuse_utility.h | 21 + components/efuse/esp32h21/sources.cmake | 4 + 10 files changed, 2685 insertions(+) create mode 100644 components/efuse/esp32h21/esp_efuse_fields.c create mode 100644 components/efuse/esp32h21/esp_efuse_rtc_calib.c create mode 100644 components/efuse/esp32h21/esp_efuse_table.c create mode 100644 components/efuse/esp32h21/esp_efuse_table.csv create mode 100644 components/efuse/esp32h21/esp_efuse_utility.c create mode 100644 components/efuse/esp32h21/include/esp_efuse_chip.h create mode 100644 components/efuse/esp32h21/include/esp_efuse_rtc_calib.h create mode 100644 components/efuse/esp32h21/include/esp_efuse_table.h create mode 100644 components/efuse/esp32h21/private_include/esp_efuse_utility.h create mode 100644 components/efuse/esp32h21/sources.cmake diff --git a/components/efuse/esp32h21/esp_efuse_fields.c b/components/efuse/esp32h21/esp_efuse_fields.c new file mode 100644 index 00000000000..223fab34e30 --- /dev/null +++ b/components/efuse/esp32h21/esp_efuse_fields.c @@ -0,0 +1,53 @@ +/* + * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include "esp_efuse.h" +#include "esp_efuse_utility.h" +#include "esp_efuse_table.h" +#include "stdlib.h" +#include "esp_types.h" +#include "assert.h" +#include "esp_err.h" +#include "esp_log.h" +#include "soc/efuse_periph.h" +#include "sys/param.h" + +static __attribute__((unused)) const char *TAG = "efuse"; + +// Contains functions that provide access to efuse fields which are often used in IDF. + +// Returns chip package from efuse +uint32_t esp_efuse_get_pkg_ver(void) +{ + uint32_t pkg_ver = 0; + esp_efuse_read_field_blob(ESP_EFUSE_PKG_VERSION, &pkg_ver, ESP_EFUSE_PKG_VERSION[0]->bit_count); + return pkg_ver; +} + + +esp_err_t esp_efuse_set_rom_log_scheme(esp_efuse_rom_log_scheme_t log_scheme) +{ + int cur_log_scheme = 0; + esp_efuse_read_field_blob(ESP_EFUSE_UART_PRINT_CONTROL, &cur_log_scheme, 2); + if (!cur_log_scheme) { // not burned yet + return esp_efuse_write_field_blob(ESP_EFUSE_UART_PRINT_CONTROL, &log_scheme, 2); + } else { + return ESP_ERR_INVALID_STATE; + } +} + +esp_err_t esp_efuse_disable_rom_download_mode(void) +{ + return esp_efuse_write_field_bit(ESP_EFUSE_DIS_DOWNLOAD_MODE); +} + +esp_err_t esp_efuse_enable_rom_secure_download_mode(void) +{ + if (esp_efuse_read_field_bit(ESP_EFUSE_DIS_DOWNLOAD_MODE)) { + return ESP_ERR_INVALID_STATE; + } + return esp_efuse_write_field_bit(ESP_EFUSE_ENABLE_SECURITY_DOWNLOAD); +} diff --git a/components/efuse/esp32h21/esp_efuse_rtc_calib.c b/components/efuse/esp32h21/esp_efuse_rtc_calib.c new file mode 100644 index 00000000000..69830ec0f55 --- /dev/null +++ b/components/efuse/esp32h21/esp_efuse_rtc_calib.c @@ -0,0 +1,51 @@ +/* + * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include "esp_efuse.h" +#include "esp_efuse_table.h" +#include "esp_efuse_rtc_calib.h" +#include "hal/efuse_hal.h" + +// TODO: [ESP32H21] IDF-11590, file inherit from verify code, please check + +/** + * @brief Get the signed value by the raw data that read from eFuse + * @param data The raw data that read from eFuse + * @param sign_bit The index of the sign bit, start from 0 + */ +#define RTC_CALIB_GET_SIGNED_VAL(data, sign_bit) ((data & BIT##sign_bit) ? -(int)(data & ~BIT##sign_bit) : (int)data) + +int esp_efuse_rtc_calib_get_ver(void) +{ + uint32_t cali_version = 0; + // TODO: [ESP32H21] IDF-11590 + abort(); +} + +uint32_t esp_efuse_rtc_calib_get_init_code(int version, uint32_t adc_unit, int atten) +{ + // TODO: [ESP32H21] IDF-11590 + abort(); +} + +int esp_efuse_rtc_calib_get_chan_compens(int version, uint32_t adc_unit, uint32_t adc_channel, int atten) +{ + // TODO: [ESP32H21] IDF-11590 + abort(); +} + +esp_err_t esp_efuse_rtc_calib_get_cal_voltage(int version, uint32_t adc_unit, int atten, uint32_t* out_digi, uint32_t* out_vol_mv) +{ + // TODO: [ESP32H21] IDF-11590 + return ESP_OK; +} + +esp_err_t esp_efuse_rtc_calib_get_tsens_val(float* tsens_cal) +{ + // TODO: [ESP32H21] IDF-11624 + return ESP_OK; +} diff --git a/components/efuse/esp32h21/esp_efuse_table.c b/components/efuse/esp32h21/esp_efuse_table.c new file mode 100644 index 00000000000..29e8f1bde41 --- /dev/null +++ b/components/efuse/esp32h21/esp_efuse_table.c @@ -0,0 +1,1726 @@ +/* + * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include "sdkconfig.h" +#include "esp_efuse.h" +#include +#include "esp_efuse_table.h" + +// TODO: [ESP32H21] IDF-11556, file inherit from verify code, please check + +// md5_digest_table bedca3b10dd5d184f2e294291996a60e +// This file was generated from the file esp_efuse_table.csv. DO NOT CHANGE THIS FILE MANUALLY. +// If you want to change some fields, you need to change esp_efuse_table.csv file +// then run `efuse_common_table` or `efuse_custom_table` command it will generate this file. +// To show efuse_table run the command 'show_efuse_table'. + +static const esp_efuse_desc_t WR_DIS[] = { + {EFUSE_BLK0, 0, 32}, // [] Disable programming of individual eFuses, +}; + +static const esp_efuse_desc_t WR_DIS_RD_DIS[] = { + {EFUSE_BLK0, 0, 1}, // [] wr_dis of RD_DIS, +}; + +static const esp_efuse_desc_t WR_DIS_DIS_ICACHE[] = { + {EFUSE_BLK0, 2, 1}, // [] wr_dis of DIS_ICACHE, +}; + +static const esp_efuse_desc_t WR_DIS_DIS_USB_JTAG[] = { + {EFUSE_BLK0, 2, 1}, // [] wr_dis of DIS_USB_JTAG, +}; + +static const esp_efuse_desc_t WR_DIS_POWERGLITCH_EN[] = { + {EFUSE_BLK0, 2, 1}, // [] wr_dis of POWERGLITCH_EN, +}; + +static const esp_efuse_desc_t WR_DIS_DIS_FORCE_DOWNLOAD[] = { + {EFUSE_BLK0, 2, 1}, // [] wr_dis of DIS_FORCE_DOWNLOAD, +}; + +static const esp_efuse_desc_t WR_DIS_SPI_DOWNLOAD_MSPI_DIS[] = { + {EFUSE_BLK0, 2, 1}, // [] wr_dis of SPI_DOWNLOAD_MSPI_DIS, +}; + +static const esp_efuse_desc_t WR_DIS_DIS_TWAI[] = { + {EFUSE_BLK0, 2, 1}, // [WR_DIS.DIS_CAN] wr_dis of DIS_TWAI, +}; + +static const esp_efuse_desc_t WR_DIS_JTAG_SEL_ENABLE[] = { + {EFUSE_BLK0, 2, 1}, // [] wr_dis of JTAG_SEL_ENABLE, +}; + +static const esp_efuse_desc_t WR_DIS_DIS_PAD_JTAG[] = { + {EFUSE_BLK0, 2, 1}, // [] wr_dis of DIS_PAD_JTAG, +}; + +static const esp_efuse_desc_t WR_DIS_DIS_DOWNLOAD_MANUAL_ENCRYPT[] = { + {EFUSE_BLK0, 2, 1}, // [] wr_dis of DIS_DOWNLOAD_MANUAL_ENCRYPT, +}; + +static const esp_efuse_desc_t WR_DIS_WDT_DELAY_SEL[] = { + {EFUSE_BLK0, 3, 1}, // [] wr_dis of WDT_DELAY_SEL, +}; + +static const esp_efuse_desc_t WR_DIS_SPI_BOOT_CRYPT_CNT[] = { + {EFUSE_BLK0, 4, 1}, // [] wr_dis of SPI_BOOT_CRYPT_CNT, +}; + +static const esp_efuse_desc_t WR_DIS_SECURE_BOOT_KEY_REVOKE0[] = { + {EFUSE_BLK0, 5, 1}, // [] wr_dis of SECURE_BOOT_KEY_REVOKE0, +}; + +static const esp_efuse_desc_t WR_DIS_SECURE_BOOT_KEY_REVOKE1[] = { + {EFUSE_BLK0, 6, 1}, // [] wr_dis of SECURE_BOOT_KEY_REVOKE1, +}; + +static const esp_efuse_desc_t WR_DIS_SECURE_BOOT_KEY_REVOKE2[] = { + {EFUSE_BLK0, 7, 1}, // [] wr_dis of SECURE_BOOT_KEY_REVOKE2, +}; + +static const esp_efuse_desc_t WR_DIS_KEY_PURPOSE_0[] = { + {EFUSE_BLK0, 8, 1}, // [WR_DIS.KEY0_PURPOSE] wr_dis of KEY_PURPOSE_0, +}; + +static const esp_efuse_desc_t WR_DIS_KEY_PURPOSE_1[] = { + {EFUSE_BLK0, 9, 1}, // [WR_DIS.KEY1_PURPOSE] wr_dis of KEY_PURPOSE_1, +}; + +static const esp_efuse_desc_t WR_DIS_KEY_PURPOSE_2[] = { + {EFUSE_BLK0, 10, 1}, // [WR_DIS.KEY2_PURPOSE] wr_dis of KEY_PURPOSE_2, +}; + +static const esp_efuse_desc_t WR_DIS_KEY_PURPOSE_3[] = { + {EFUSE_BLK0, 11, 1}, // [WR_DIS.KEY3_PURPOSE] wr_dis of KEY_PURPOSE_3, +}; + +static const esp_efuse_desc_t WR_DIS_KEY_PURPOSE_4[] = { + {EFUSE_BLK0, 12, 1}, // [WR_DIS.KEY4_PURPOSE] wr_dis of KEY_PURPOSE_4, +}; + +static const esp_efuse_desc_t WR_DIS_KEY_PURPOSE_5[] = { + {EFUSE_BLK0, 13, 1}, // [WR_DIS.KEY5_PURPOSE] wr_dis of KEY_PURPOSE_5, +}; + +static const esp_efuse_desc_t WR_DIS_SEC_DPA_LEVEL[] = { + {EFUSE_BLK0, 14, 1}, // [] wr_dis of SEC_DPA_LEVEL, +}; + +static const esp_efuse_desc_t WR_DIS_CRYPT_DPA_ENABLE[] = { + {EFUSE_BLK0, 14, 1}, // [] wr_dis of CRYPT_DPA_ENABLE, +}; + +static const esp_efuse_desc_t WR_DIS_SECURE_BOOT_EN[] = { + {EFUSE_BLK0, 15, 1}, // [] wr_dis of SECURE_BOOT_EN, +}; + +static const esp_efuse_desc_t WR_DIS_SECURE_BOOT_AGGRESSIVE_REVOKE[] = { + {EFUSE_BLK0, 16, 1}, // [] wr_dis of SECURE_BOOT_AGGRESSIVE_REVOKE, +}; + +static const esp_efuse_desc_t WR_DIS_ECDSA_FORCE_USE_HARDWARE_K[] = { + {EFUSE_BLK0, 17, 1}, // [] wr_dis of ECDSA_FORCE_USE_HARDWARE_K, +}; + +static const esp_efuse_desc_t WR_DIS_FLASH_TPUW[] = { + {EFUSE_BLK0, 18, 1}, // [] wr_dis of FLASH_TPUW, +}; + +static const esp_efuse_desc_t WR_DIS_DIS_DOWNLOAD_MODE[] = { + {EFUSE_BLK0, 18, 1}, // [] wr_dis of DIS_DOWNLOAD_MODE, +}; + +static const esp_efuse_desc_t WR_DIS_DIS_DIRECT_BOOT[] = { + {EFUSE_BLK0, 18, 1}, // [] wr_dis of DIS_DIRECT_BOOT, +}; + +static const esp_efuse_desc_t WR_DIS_DIS_USB_SERIAL_JTAG_ROM_PRINT[] = { + {EFUSE_BLK0, 18, 1}, // [WR_DIS.DIS_USB_PRINT] wr_dis of DIS_USB_SERIAL_JTAG_ROM_PRINT, +}; + +static const esp_efuse_desc_t WR_DIS_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE[] = { + {EFUSE_BLK0, 18, 1}, // [] wr_dis of DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE, +}; + +static const esp_efuse_desc_t WR_DIS_ENABLE_SECURITY_DOWNLOAD[] = { + {EFUSE_BLK0, 18, 1}, // [] wr_dis of ENABLE_SECURITY_DOWNLOAD, +}; + +static const esp_efuse_desc_t WR_DIS_UART_PRINT_CONTROL[] = { + {EFUSE_BLK0, 18, 1}, // [] wr_dis of UART_PRINT_CONTROL, +}; + +static const esp_efuse_desc_t WR_DIS_FORCE_SEND_RESUME[] = { + {EFUSE_BLK0, 18, 1}, // [] wr_dis of FORCE_SEND_RESUME, +}; + +static const esp_efuse_desc_t WR_DIS_SECURE_VERSION[] = { + {EFUSE_BLK0, 18, 1}, // [] wr_dis of SECURE_VERSION, +}; + +static const esp_efuse_desc_t WR_DIS_SECURE_BOOT_DISABLE_FAST_WAKE[] = { + {EFUSE_BLK0, 18, 1}, // [] wr_dis of SECURE_BOOT_DISABLE_FAST_WAKE, +}; + +static const esp_efuse_desc_t WR_DIS_HYS_EN_PAD0[] = { + {EFUSE_BLK0, 19, 1}, // [] wr_dis of HYS_EN_PAD0, +}; + +static const esp_efuse_desc_t WR_DIS_HYS_EN_PAD1[] = { + {EFUSE_BLK0, 19, 1}, // [] wr_dis of HYS_EN_PAD1, +}; + +static const esp_efuse_desc_t WR_DIS_BLK1[] = { + {EFUSE_BLK0, 20, 1}, // [] wr_dis of BLOCK1, +}; + +static const esp_efuse_desc_t WR_DIS_MAC[] = { + {EFUSE_BLK0, 20, 1}, // [WR_DIS.MAC_FACTORY] wr_dis of MAC, +}; + +static const esp_efuse_desc_t WR_DIS_MAC_EXT[] = { + {EFUSE_BLK0, 20, 1}, // [] wr_dis of MAC_EXT, +}; + +static const esp_efuse_desc_t WR_DIS_RXIQ_VERSION[] = { + {EFUSE_BLK0, 20, 1}, // [] wr_dis of RXIQ_VERSION, +}; + +static const esp_efuse_desc_t WR_DIS_RXIQ_0[] = { + {EFUSE_BLK0, 20, 1}, // [] wr_dis of RXIQ_0, +}; + +static const esp_efuse_desc_t WR_DIS_RXIQ_1[] = { + {EFUSE_BLK0, 20, 1}, // [] wr_dis of RXIQ_1, +}; + +static const esp_efuse_desc_t WR_DIS_ACTIVE_HP_DBIAS[] = { + {EFUSE_BLK0, 20, 1}, // [] wr_dis of ACTIVE_HP_DBIAS, +}; + +static const esp_efuse_desc_t WR_DIS_ACTIVE_LP_DBIAS[] = { + {EFUSE_BLK0, 20, 1}, // [] wr_dis of ACTIVE_LP_DBIAS, +}; + +static const esp_efuse_desc_t WR_DIS_DSLP_DBIAS[] = { + {EFUSE_BLK0, 20, 1}, // [] wr_dis of DSLP_DBIAS, +}; + +static const esp_efuse_desc_t WR_DIS_DBIAS_VOL_GAP[] = { + {EFUSE_BLK0, 20, 1}, // [] wr_dis of DBIAS_VOL_GAP, +}; + +static const esp_efuse_desc_t WR_DIS_WAFER_VERSION_MINOR[] = { + {EFUSE_BLK0, 20, 1}, // [] wr_dis of WAFER_VERSION_MINOR, +}; + +static const esp_efuse_desc_t WR_DIS_WAFER_VERSION_MAJOR[] = { + {EFUSE_BLK0, 20, 1}, // [] wr_dis of WAFER_VERSION_MAJOR, +}; + +static const esp_efuse_desc_t WR_DIS_DISABLE_WAFER_VERSION_MAJOR[] = { + {EFUSE_BLK0, 20, 1}, // [] wr_dis of DISABLE_WAFER_VERSION_MAJOR, +}; + +static const esp_efuse_desc_t WR_DIS_FLASH_CAP[] = { + {EFUSE_BLK0, 20, 1}, // [] wr_dis of FLASH_CAP, +}; + +static const esp_efuse_desc_t WR_DIS_FLASH_TEMP[] = { + {EFUSE_BLK0, 20, 1}, // [] wr_dis of FLASH_TEMP, +}; + +static const esp_efuse_desc_t WR_DIS_FLASH_VENDOR[] = { + {EFUSE_BLK0, 20, 1}, // [] wr_dis of FLASH_VENDOR, +}; + +static const esp_efuse_desc_t WR_DIS_PKG_VERSION[] = { + {EFUSE_BLK0, 20, 1}, // [] wr_dis of PKG_VERSION, +}; + +static const esp_efuse_desc_t WR_DIS_SYS_DATA_PART1[] = { + {EFUSE_BLK0, 21, 1}, // [] wr_dis of BLOCK2, +}; + +static const esp_efuse_desc_t WR_DIS_OPTIONAL_UNIQUE_ID[] = { + {EFUSE_BLK0, 21, 1}, // [] wr_dis of OPTIONAL_UNIQUE_ID, +}; + +static const esp_efuse_desc_t WR_DIS_BLK_VERSION_MINOR[] = { + {EFUSE_BLK0, 21, 1}, // [] wr_dis of BLK_VERSION_MINOR, +}; + +static const esp_efuse_desc_t WR_DIS_BLK_VERSION_MAJOR[] = { + {EFUSE_BLK0, 21, 1}, // [] wr_dis of BLK_VERSION_MAJOR, +}; + +static const esp_efuse_desc_t WR_DIS_DISABLE_BLK_VERSION_MAJOR[] = { + {EFUSE_BLK0, 21, 1}, // [] wr_dis of DISABLE_BLK_VERSION_MAJOR, +}; + +static const esp_efuse_desc_t WR_DIS_TEMP_CALIB[] = { + {EFUSE_BLK0, 21, 1}, // [] wr_dis of TEMP_CALIB, +}; + +static const esp_efuse_desc_t WR_DIS_ADC1_AVE_INITCODE_ATTEN0[] = { + {EFUSE_BLK0, 21, 1}, // [] wr_dis of ADC1_AVE_INITCODE_ATTEN0, +}; + +static const esp_efuse_desc_t WR_DIS_ADC1_AVE_INITCODE_ATTEN1[] = { + {EFUSE_BLK0, 21, 1}, // [] wr_dis of ADC1_AVE_INITCODE_ATTEN1, +}; + +static const esp_efuse_desc_t WR_DIS_ADC1_AVE_INITCODE_ATTEN2[] = { + {EFUSE_BLK0, 21, 1}, // [] wr_dis of ADC1_AVE_INITCODE_ATTEN2, +}; + +static const esp_efuse_desc_t WR_DIS_ADC1_AVE_INITCODE_ATTEN3[] = { + {EFUSE_BLK0, 21, 1}, // [] wr_dis of ADC1_AVE_INITCODE_ATTEN3, +}; + +static const esp_efuse_desc_t WR_DIS_ADC1_HI_DOUT_ATTEN0[] = { + {EFUSE_BLK0, 21, 1}, // [] wr_dis of ADC1_HI_DOUT_ATTEN0, +}; + +static const esp_efuse_desc_t WR_DIS_ADC1_HI_DOUT_ATTEN1[] = { + {EFUSE_BLK0, 21, 1}, // [] wr_dis of ADC1_HI_DOUT_ATTEN1, +}; + +static const esp_efuse_desc_t WR_DIS_ADC1_HI_DOUT_ATTEN2[] = { + {EFUSE_BLK0, 21, 1}, // [] wr_dis of ADC1_HI_DOUT_ATTEN2, +}; + +static const esp_efuse_desc_t WR_DIS_ADC1_HI_DOUT_ATTEN3[] = { + {EFUSE_BLK0, 21, 1}, // [] wr_dis of ADC1_HI_DOUT_ATTEN3, +}; + +static const esp_efuse_desc_t WR_DIS_ADC1_CH0_ATTEN0_INITCODE_DIFF[] = { + {EFUSE_BLK0, 21, 1}, // [] wr_dis of ADC1_CH0_ATTEN0_INITCODE_DIFF, +}; + +static const esp_efuse_desc_t WR_DIS_ADC1_CH1_ATTEN0_INITCODE_DIFF[] = { + {EFUSE_BLK0, 21, 1}, // [] wr_dis of ADC1_CH1_ATTEN0_INITCODE_DIFF, +}; + +static const esp_efuse_desc_t WR_DIS_ADC1_CH2_ATTEN0_INITCODE_DIFF[] = { + {EFUSE_BLK0, 21, 1}, // [] wr_dis of ADC1_CH2_ATTEN0_INITCODE_DIFF, +}; + +static const esp_efuse_desc_t WR_DIS_ADC1_CH3_ATTEN0_INITCODE_DIFF[] = { + {EFUSE_BLK0, 21, 1}, // [] wr_dis of ADC1_CH3_ATTEN0_INITCODE_DIFF, +}; + +static const esp_efuse_desc_t WR_DIS_ADC1_CH4_ATTEN0_INITCODE_DIFF[] = { + {EFUSE_BLK0, 21, 1}, // [] wr_dis of ADC1_CH4_ATTEN0_INITCODE_DIFF, +}; + +static const esp_efuse_desc_t WR_DIS_BLOCK_USR_DATA[] = { + {EFUSE_BLK0, 22, 1}, // [WR_DIS.USER_DATA] wr_dis of BLOCK_USR_DATA, +}; + +static const esp_efuse_desc_t WR_DIS_CUSTOM_MAC[] = { + {EFUSE_BLK0, 22, 1}, // [WR_DIS.MAC_CUSTOM WR_DIS.USER_DATA_MAC_CUSTOM] wr_dis of CUSTOM_MAC, +}; + +static const esp_efuse_desc_t WR_DIS_BLOCK_KEY0[] = { + {EFUSE_BLK0, 23, 1}, // [WR_DIS.KEY0] wr_dis of BLOCK_KEY0, +}; + +static const esp_efuse_desc_t WR_DIS_BLOCK_KEY1[] = { + {EFUSE_BLK0, 24, 1}, // [WR_DIS.KEY1] wr_dis of BLOCK_KEY1, +}; + +static const esp_efuse_desc_t WR_DIS_BLOCK_KEY2[] = { + {EFUSE_BLK0, 25, 1}, // [WR_DIS.KEY2] wr_dis of BLOCK_KEY2, +}; + +static const esp_efuse_desc_t WR_DIS_BLOCK_KEY3[] = { + {EFUSE_BLK0, 26, 1}, // [WR_DIS.KEY3] wr_dis of BLOCK_KEY3, +}; + +static const esp_efuse_desc_t WR_DIS_BLOCK_KEY4[] = { + {EFUSE_BLK0, 27, 1}, // [WR_DIS.KEY4] wr_dis of BLOCK_KEY4, +}; + +static const esp_efuse_desc_t WR_DIS_BLOCK_KEY5[] = { + {EFUSE_BLK0, 28, 1}, // [WR_DIS.KEY5] wr_dis of BLOCK_KEY5, +}; + +static const esp_efuse_desc_t WR_DIS_BLOCK_SYS_DATA2[] = { + {EFUSE_BLK0, 29, 1}, // [WR_DIS.SYS_DATA_PART2] wr_dis of BLOCK_SYS_DATA2, +}; + +static const esp_efuse_desc_t WR_DIS_USB_EXCHG_PINS[] = { + {EFUSE_BLK0, 30, 1}, // [] wr_dis of USB_EXCHG_PINS, +}; + +static const esp_efuse_desc_t WR_DIS_VDD_SPI_AS_GPIO[] = { + {EFUSE_BLK0, 30, 1}, // [] wr_dis of VDD_SPI_AS_GPIO, +}; + +static const esp_efuse_desc_t WR_DIS_SOFT_DIS_JTAG[] = { + {EFUSE_BLK0, 31, 1}, // [] wr_dis of SOFT_DIS_JTAG, +}; + +static const esp_efuse_desc_t RD_DIS[] = { + {EFUSE_BLK0, 32, 7}, // [] Disable reading from BlOCK4-10, +}; + +static const esp_efuse_desc_t RD_DIS_BLOCK_KEY0[] = { + {EFUSE_BLK0, 32, 1}, // [RD_DIS.KEY0] rd_dis of BLOCK_KEY0, +}; + +static const esp_efuse_desc_t RD_DIS_BLOCK_KEY1[] = { + {EFUSE_BLK0, 33, 1}, // [RD_DIS.KEY1] rd_dis of BLOCK_KEY1, +}; + +static const esp_efuse_desc_t RD_DIS_BLOCK_KEY2[] = { + {EFUSE_BLK0, 34, 1}, // [RD_DIS.KEY2] rd_dis of BLOCK_KEY2, +}; + +static const esp_efuse_desc_t RD_DIS_BLOCK_KEY3[] = { + {EFUSE_BLK0, 35, 1}, // [RD_DIS.KEY3] rd_dis of BLOCK_KEY3, +}; + +static const esp_efuse_desc_t RD_DIS_BLOCK_KEY4[] = { + {EFUSE_BLK0, 36, 1}, // [RD_DIS.KEY4] rd_dis of BLOCK_KEY4, +}; + +static const esp_efuse_desc_t RD_DIS_BLOCK_KEY5[] = { + {EFUSE_BLK0, 37, 1}, // [RD_DIS.KEY5] rd_dis of BLOCK_KEY5, +}; + +static const esp_efuse_desc_t RD_DIS_BLOCK_SYS_DATA2[] = { + {EFUSE_BLK0, 38, 1}, // [RD_DIS.SYS_DATA_PART2] rd_dis of BLOCK_SYS_DATA2, +}; + +static const esp_efuse_desc_t PVT_GLITCH_EN[] = { + {EFUSE_BLK0, 39, 1}, // [] Represents whether pvt glitch is enabled, +}; + +static const esp_efuse_desc_t DIS_ICACHE[] = { + {EFUSE_BLK0, 40, 1}, // [] Represents whether icache is disabled, +}; + +static const esp_efuse_desc_t DIS_USB_JTAG[] = { + {EFUSE_BLK0, 41, 1}, // [] Represents whether the function of usb switch to jtag is disabled or enabled. 1: disabled. 0: enabled, +}; + +static const esp_efuse_desc_t POWERGLITCH_EN[] = { + {EFUSE_BLK0, 42, 1}, // [] Represents whether power glitch function is enabled. 1: enabled. 0: disabled, +}; + +static const esp_efuse_desc_t DIS_USJ[] = { + {EFUSE_BLK0, 43, 1}, // [] Represents whether usb serial jtag is disabled, +}; + +static const esp_efuse_desc_t DIS_FORCE_DOWNLOAD[] = { + {EFUSE_BLK0, 44, 1}, // [] Represents whether the function that forces chip into download mode is disabled or enabled. 1: disabled. 0: enabled, +}; + +static const esp_efuse_desc_t SPI_DOWNLOAD_MSPI_DIS[] = { + {EFUSE_BLK0, 45, 1}, // [] Represents whether SPI0 controller during boot_mode_download is disabled or enabled. 1: disabled. 0: enabled, +}; + +static const esp_efuse_desc_t DIS_TWAI[] = { + {EFUSE_BLK0, 46, 1}, // [DIS_CAN] Represents whether TWAI function is disabled or enabled. 1: disabled. 0: enabled, +}; + +static const esp_efuse_desc_t JTAG_SEL_ENABLE[] = { + {EFUSE_BLK0, 47, 1}, // [] Set this bit to enable selection between usb_to_jtag and pad_to_jtag through strapping gpio25 when both EFUSE_DIS_PAD_JTAG and EFUSE_DIS_USB_JTAG are equal to 0, +}; + +static const esp_efuse_desc_t SOFT_DIS_JTAG[] = { + {EFUSE_BLK0, 48, 3}, // [] Represents whether JTAG is disabled in soft way. Odd number: disabled. Even number: enabled, +}; + +static const esp_efuse_desc_t DIS_PAD_JTAG[] = { + {EFUSE_BLK0, 51, 1}, // [] Represents whether JTAG is disabled in the hard way(permanently). 1: disabled. 0: enabled, +}; + +static const esp_efuse_desc_t DIS_DOWNLOAD_MANUAL_ENCRYPT[] = { + {EFUSE_BLK0, 52, 1}, // [] Represents whether flash encrypt function is disabled or enabled(except in SPI boot mode). 1: disabled. 0: enabled, +}; + +static const esp_efuse_desc_t USB_DREFH[] = { + {EFUSE_BLK0, 53, 2}, // [] USB drefh, +}; + +static const esp_efuse_desc_t USB_DREFL[] = { + {EFUSE_BLK0, 55, 2}, // [] USB drefl, +}; + +static const esp_efuse_desc_t USB_EXCHG_PINS[] = { + {EFUSE_BLK0, 57, 1}, // [] Represents whether the D+ and D- pins is exchanged. 1: exchanged. 0: not exchanged, +}; + +static const esp_efuse_desc_t VDD_SPI_AS_GPIO[] = { + {EFUSE_BLK0, 58, 1}, // [] Represents whether vdd spi pin is functioned as gpio. 1: functioned. 0: not functioned, +}; + +static const esp_efuse_desc_t ECDSA_CURVE_MODE[] = { + {EFUSE_BLK0, 59, 2}, // [] ECDSA curve mode. 0: only P256. 1: only P192. 2: both P192 and P256. 3: only P256, +}; + +static const esp_efuse_desc_t ECC_FORCE_CONST_TIME[] = { + {EFUSE_BLK0, 61, 1}, // [] ECC force const time, +}; + +static const esp_efuse_desc_t XTS_DPA_PSEUDO_LEVEL[] = { + {EFUSE_BLK0, 62, 2}, // [] XTS DPA pseudo level, +}; + +static const esp_efuse_desc_t IO_LDO_ADJUST[] = { + {EFUSE_BLK0, 64, 8}, // [] Represents configuration of IO LDO mode and voltage., +}; + +static const esp_efuse_desc_t VDD_SPI_LDO_ADJUST[] = { + {EFUSE_BLK0, 72, 8}, // [] Represents configuration of FLASH LDO mode and voltage, +}; + +static const esp_efuse_desc_t WDT_DELAY_SEL[] = { + {EFUSE_BLK0, 80, 2}, // [] Represents whether RTC watchdog timeout threshold is selected at startup. 1: selected. 0: not selected, +}; + +static const esp_efuse_desc_t SPI_BOOT_CRYPT_CNT[] = { + {EFUSE_BLK0, 82, 3}, // [] Enables flash encryption when 1 or 3 bits are set and disables otherwise {0: "Disable"; 1: "Enable"; 3: "Disable"; 7: "Enable"}, +}; + +static const esp_efuse_desc_t SECURE_BOOT_KEY_REVOKE0[] = { + {EFUSE_BLK0, 85, 1}, // [] Revoke 1st secure boot key, +}; + +static const esp_efuse_desc_t SECURE_BOOT_KEY_REVOKE1[] = { + {EFUSE_BLK0, 86, 1}, // [] Revoke 2nd secure boot key, +}; + +static const esp_efuse_desc_t SECURE_BOOT_KEY_REVOKE2[] = { + {EFUSE_BLK0, 87, 1}, // [] Revoke 3rd secure boot key, +}; + +static const esp_efuse_desc_t KEY_PURPOSE_0[] = { + {EFUSE_BLK0, 88, 4}, // [KEY0_PURPOSE] Represents the purpose of Key0, +}; + +static const esp_efuse_desc_t KEY_PURPOSE_1[] = { + {EFUSE_BLK0, 92, 4}, // [KEY1_PURPOSE] Represents the purpose of Key1, +}; + +static const esp_efuse_desc_t KEY_PURPOSE_2[] = { + {EFUSE_BLK0, 96, 4}, // [KEY2_PURPOSE] Represents the purpose of Key2, +}; + +static const esp_efuse_desc_t KEY_PURPOSE_3[] = { + {EFUSE_BLK0, 100, 4}, // [KEY3_PURPOSE] Represents the purpose of Key3, +}; + +static const esp_efuse_desc_t KEY_PURPOSE_4[] = { + {EFUSE_BLK0, 104, 4}, // [KEY4_PURPOSE] Represents the purpose of Key4, +}; + +static const esp_efuse_desc_t KEY_PURPOSE_5[] = { + {EFUSE_BLK0, 108, 4}, // [KEY5_PURPOSE] Represents the purpose of Key5, +}; + +static const esp_efuse_desc_t SEC_DPA_LEVEL[] = { + {EFUSE_BLK0, 112, 2}, // [] Represents the spa secure level by configuring the clock random divide mode, +}; + +static const esp_efuse_desc_t IO_LDO_1P8[] = { + {EFUSE_BLK0, 114, 1}, // [] Represents select IO LDO voltage to 1.8V or 3.3V.\\ 1: 1.8V\\ 0: 3.3V, +}; + +static const esp_efuse_desc_t CRYPT_DPA_ENABLE[] = { + {EFUSE_BLK0, 115, 1}, // [] Represents whether anti-dpa attack is enabled. 1:enabled. 0: disabled, +}; + +static const esp_efuse_desc_t SECURE_BOOT_EN[] = { + {EFUSE_BLK0, 116, 1}, // [] Represents whether secure boot is enabled or disabled. 1: enabled. 0: disabled, +}; + +static const esp_efuse_desc_t SECURE_BOOT_AGGRESSIVE_REVOKE[] = { + {EFUSE_BLK0, 117, 1}, // [] Represents whether revoking aggressive secure boot is enabled or disabled. 1: enabled. 0: disabled, +}; + +static const esp_efuse_desc_t POWERGLITCH_EN1[] = { + {EFUSE_BLK0, 118, 5}, // [] Represents whether to enable power glitch function when chip power on, +}; + +static const esp_efuse_desc_t FLASH_TPUW[] = { + {EFUSE_BLK0, 124, 4}, // [] Represents the flash waiting time after power-up; in unit of ms. When the value less than 15; the waiting time is the programmed value. Otherwise; the waiting time is 2 times the programmed value, +}; + +static const esp_efuse_desc_t DIS_DOWNLOAD_MODE[] = { + {EFUSE_BLK0, 128, 1}, // [] Represents whether Download mode is disabled or enabled. 1: disabled. 0: enabled, +}; + +static const esp_efuse_desc_t DIS_DIRECT_BOOT[] = { + {EFUSE_BLK0, 129, 1}, // [] Represents whether direct boot mode is disabled or enabled. 1: disabled. 0: enabled, +}; + +static const esp_efuse_desc_t DIS_USB_SERIAL_JTAG_ROM_PRINT[] = { + {EFUSE_BLK0, 130, 1}, // [DIS_USB_PRINT] Set this bit to disable USB-Serial-JTAG print during rom boot, +}; + +static const esp_efuse_desc_t DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE[] = { + {EFUSE_BLK0, 132, 1}, // [] Represents whether the USB-Serial-JTAG download function is disabled or enabled. 1: disabled. 0: enabled, +}; + +static const esp_efuse_desc_t ENABLE_SECURITY_DOWNLOAD[] = { + {EFUSE_BLK0, 133, 1}, // [] Represents whether security download is enabled or disabled. 1: enabled. 0: disabled, +}; + +static const esp_efuse_desc_t UART_PRINT_CONTROL[] = { + {EFUSE_BLK0, 134, 2}, // [] Set the default UARTboot message output mode {0: "Enable"; 1: "Enable when GPIO8 is low at reset"; 2: "Enable when GPIO8 is high at reset"; 3: "Disable"}, +}; + +static const esp_efuse_desc_t FORCE_SEND_RESUME[] = { + {EFUSE_BLK0, 136, 1}, // [] Represents whether ROM code is forced to send a resume command during SPI boot. 1: forced. 0:not forced, +}; + +static const esp_efuse_desc_t SECURE_VERSION[] = { + {EFUSE_BLK0, 137, 16}, // [] Represents the version used by ESP-IDF anti-rollback feature, +}; + +static const esp_efuse_desc_t SECURE_BOOT_DISABLE_FAST_WAKE[] = { + {EFUSE_BLK0, 153, 1}, // [] Represents whether FAST VERIFY ON WAKE is disabled or enabled when Secure Boot is enabled. 1: disabled. 0: enabled, +}; + +static const esp_efuse_desc_t HYS_EN_PAD0[] = { + {EFUSE_BLK0, 154, 6}, // [] Set bits to enable hysteresis function of PAD0~5, +}; + +static const esp_efuse_desc_t HYS_EN_PAD1[] = { + {EFUSE_BLK0, 160, 22}, // [] Set bits to enable hysteresis function of PAD6~27, +}; + +static const esp_efuse_desc_t MAC[] = { + {EFUSE_BLK1, 40, 8}, // [MAC_FACTORY] MAC address, + {EFUSE_BLK1, 32, 8}, // [MAC_FACTORY] MAC address, + {EFUSE_BLK1, 24, 8}, // [MAC_FACTORY] MAC address, + {EFUSE_BLK1, 16, 8}, // [MAC_FACTORY] MAC address, + {EFUSE_BLK1, 8, 8}, // [MAC_FACTORY] MAC address, + {EFUSE_BLK1, 0, 8}, // [MAC_FACTORY] MAC address, +}; + +static const esp_efuse_desc_t MAC_EXT[] = { + {EFUSE_BLK1, 56, 8}, // [] Stores the extended bits of MAC address, + {EFUSE_BLK1, 48, 8}, // [] Stores the extended bits of MAC address, +}; + +static const esp_efuse_desc_t RXIQ_VERSION[] = { + {EFUSE_BLK1, 64, 3}, // [] Stores RF Calibration data. RXIQ version, +}; + +static const esp_efuse_desc_t RXIQ_0[] = { + {EFUSE_BLK1, 67, 7}, // [] Stores RF Calibration data. RXIQ data 0, +}; + +static const esp_efuse_desc_t RXIQ_1[] = { + {EFUSE_BLK1, 74, 7}, // [] Stores RF Calibration data. RXIQ data 1, +}; + +static const esp_efuse_desc_t ACTIVE_HP_DBIAS[] = { + {EFUSE_BLK1, 81, 5}, // [] Stores the PMU active hp dbias, +}; + +static const esp_efuse_desc_t ACTIVE_LP_DBIAS[] = { + {EFUSE_BLK1, 86, 5}, // [] Stores the PMU active lp dbias, +}; + +static const esp_efuse_desc_t DSLP_DBIAS[] = { + {EFUSE_BLK1, 91, 4}, // [] Stores the PMU sleep dbias, +}; + +static const esp_efuse_desc_t DBIAS_VOL_GAP[] = { + {EFUSE_BLK1, 95, 5}, // [] Stores the low 1 bit of dbias_vol_gap, +}; + +static const esp_efuse_desc_t WAFER_VERSION_MINOR[] = { + {EFUSE_BLK1, 114, 3}, // [] Stores the wafer version minor, +}; + +static const esp_efuse_desc_t WAFER_VERSION_MAJOR[] = { + {EFUSE_BLK1, 117, 2}, // [] Stores the wafer version major, +}; + +static const esp_efuse_desc_t DISABLE_WAFER_VERSION_MAJOR[] = { + {EFUSE_BLK1, 119, 1}, // [] Disables check of wafer version major, +}; + +static const esp_efuse_desc_t FLASH_CAP[] = { + {EFUSE_BLK1, 120, 3}, // [] Stores the flash cap, +}; + +static const esp_efuse_desc_t FLASH_TEMP[] = { + {EFUSE_BLK1, 123, 2}, // [] Stores the flash temp, +}; + +static const esp_efuse_desc_t FLASH_VENDOR[] = { + {EFUSE_BLK1, 125, 3}, // [] Stores the flash vendor, +}; + +static const esp_efuse_desc_t PKG_VERSION[] = { + {EFUSE_BLK1, 128, 3}, // [] Package version, +}; + +static const esp_efuse_desc_t OPTIONAL_UNIQUE_ID[] = { + {EFUSE_BLK2, 0, 128}, // [] Optional unique 128-bit ID, +}; + +static const esp_efuse_desc_t BLK_VERSION_MINOR[] = { + {EFUSE_BLK2, 130, 3}, // [] BLK_VERSION_MINOR of BLOCK2. 1: RF Calibration data in BLOCK1, +}; + +static const esp_efuse_desc_t BLK_VERSION_MAJOR[] = { + {EFUSE_BLK2, 133, 2}, // [] BLK_VERSION_MAJOR of BLOCK2, +}; + +static const esp_efuse_desc_t DISABLE_BLK_VERSION_MAJOR[] = { + {EFUSE_BLK2, 135, 1}, // [] Disables check of blk version major, +}; + +static const esp_efuse_desc_t TEMP_CALIB[] = { + {EFUSE_BLK2, 136, 9}, // [] Temperature calibration data, +}; + +static const esp_efuse_desc_t ADC1_AVE_INITCODE_ATTEN0[] = { + {EFUSE_BLK2, 145, 10}, // [] ADC1 calibration data, +}; + +static const esp_efuse_desc_t ADC1_AVE_INITCODE_ATTEN1[] = { + {EFUSE_BLK2, 155, 10}, // [] ADC1 calibration data, +}; + +static const esp_efuse_desc_t ADC1_AVE_INITCODE_ATTEN2[] = { + {EFUSE_BLK2, 165, 10}, // [] ADC1 calibration data, +}; + +static const esp_efuse_desc_t ADC1_AVE_INITCODE_ATTEN3[] = { + {EFUSE_BLK2, 175, 10}, // [] ADC1 calibration data, +}; + +static const esp_efuse_desc_t ADC1_HI_DOUT_ATTEN0[] = { + {EFUSE_BLK2, 185, 10}, // [] ADC1 calibration data, +}; + +static const esp_efuse_desc_t ADC1_HI_DOUT_ATTEN1[] = { + {EFUSE_BLK2, 195, 10}, // [] ADC1 calibration data, +}; + +static const esp_efuse_desc_t ADC1_HI_DOUT_ATTEN2[] = { + {EFUSE_BLK2, 205, 10}, // [] ADC1 calibration data, +}; + +static const esp_efuse_desc_t ADC1_HI_DOUT_ATTEN3[] = { + {EFUSE_BLK2, 215, 10}, // [] ADC1 calibration data, +}; + +static const esp_efuse_desc_t ADC1_CH0_ATTEN0_INITCODE_DIFF[] = { + {EFUSE_BLK2, 225, 4}, // [] ADC1 calibration data, +}; + +static const esp_efuse_desc_t ADC1_CH1_ATTEN0_INITCODE_DIFF[] = { + {EFUSE_BLK2, 229, 4}, // [] ADC1 calibration data, +}; + +static const esp_efuse_desc_t ADC1_CH2_ATTEN0_INITCODE_DIFF[] = { + {EFUSE_BLK2, 233, 4}, // [] ADC1 calibration data, +}; + +static const esp_efuse_desc_t ADC1_CH3_ATTEN0_INITCODE_DIFF[] = { + {EFUSE_BLK2, 237, 4}, // [] ADC1 calibration data, +}; + +static const esp_efuse_desc_t ADC1_CH4_ATTEN0_INITCODE_DIFF[] = { + {EFUSE_BLK2, 241, 4}, // [] ADC1 calibration data, +}; + +static const esp_efuse_desc_t USER_DATA[] = { + {EFUSE_BLK3, 0, 256}, // [BLOCK_USR_DATA] User data, +}; + +static const esp_efuse_desc_t USER_DATA_MAC_CUSTOM[] = { + {EFUSE_BLK3, 200, 48}, // [MAC_CUSTOM CUSTOM_MAC] Custom MAC, +}; + +static const esp_efuse_desc_t KEY0[] = { + {EFUSE_BLK4, 0, 256}, // [BLOCK_KEY0] Key0 or user data, +}; + +static const esp_efuse_desc_t KEY1[] = { + {EFUSE_BLK5, 0, 256}, // [BLOCK_KEY1] Key1 or user data, +}; + +static const esp_efuse_desc_t KEY2[] = { + {EFUSE_BLK6, 0, 256}, // [BLOCK_KEY2] Key2 or user data, +}; + +static const esp_efuse_desc_t KEY3[] = { + {EFUSE_BLK7, 0, 256}, // [BLOCK_KEY3] Key3 or user data, +}; + +static const esp_efuse_desc_t KEY4[] = { + {EFUSE_BLK8, 0, 256}, // [BLOCK_KEY4] Key4 or user data, +}; + +static const esp_efuse_desc_t KEY5[] = { + {EFUSE_BLK9, 0, 256}, // [BLOCK_KEY5] Key5 or user data, +}; + +static const esp_efuse_desc_t SYS_DATA_PART2[] = { + {EFUSE_BLK10, 0, 256}, // [BLOCK_SYS_DATA2] System data part 2 (reserved), +}; + + + + + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS[] = { + &WR_DIS[0], // [] Disable programming of individual eFuses + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_RD_DIS[] = { + &WR_DIS_RD_DIS[0], // [] wr_dis of RD_DIS + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_ICACHE[] = { + &WR_DIS_DIS_ICACHE[0], // [] wr_dis of DIS_ICACHE + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_USB_JTAG[] = { + &WR_DIS_DIS_USB_JTAG[0], // [] wr_dis of DIS_USB_JTAG + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_POWERGLITCH_EN[] = { + &WR_DIS_POWERGLITCH_EN[0], // [] wr_dis of POWERGLITCH_EN + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_FORCE_DOWNLOAD[] = { + &WR_DIS_DIS_FORCE_DOWNLOAD[0], // [] wr_dis of DIS_FORCE_DOWNLOAD + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SPI_DOWNLOAD_MSPI_DIS[] = { + &WR_DIS_SPI_DOWNLOAD_MSPI_DIS[0], // [] wr_dis of SPI_DOWNLOAD_MSPI_DIS + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_TWAI[] = { + &WR_DIS_DIS_TWAI[0], // [WR_DIS.DIS_CAN] wr_dis of DIS_TWAI + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_JTAG_SEL_ENABLE[] = { + &WR_DIS_JTAG_SEL_ENABLE[0], // [] wr_dis of JTAG_SEL_ENABLE + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_PAD_JTAG[] = { + &WR_DIS_DIS_PAD_JTAG[0], // [] wr_dis of DIS_PAD_JTAG + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_DOWNLOAD_MANUAL_ENCRYPT[] = { + &WR_DIS_DIS_DOWNLOAD_MANUAL_ENCRYPT[0], // [] wr_dis of DIS_DOWNLOAD_MANUAL_ENCRYPT + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_WDT_DELAY_SEL[] = { + &WR_DIS_WDT_DELAY_SEL[0], // [] wr_dis of WDT_DELAY_SEL + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SPI_BOOT_CRYPT_CNT[] = { + &WR_DIS_SPI_BOOT_CRYPT_CNT[0], // [] wr_dis of SPI_BOOT_CRYPT_CNT + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SECURE_BOOT_KEY_REVOKE0[] = { + &WR_DIS_SECURE_BOOT_KEY_REVOKE0[0], // [] wr_dis of SECURE_BOOT_KEY_REVOKE0 + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SECURE_BOOT_KEY_REVOKE1[] = { + &WR_DIS_SECURE_BOOT_KEY_REVOKE1[0], // [] wr_dis of SECURE_BOOT_KEY_REVOKE1 + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SECURE_BOOT_KEY_REVOKE2[] = { + &WR_DIS_SECURE_BOOT_KEY_REVOKE2[0], // [] wr_dis of SECURE_BOOT_KEY_REVOKE2 + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY_PURPOSE_0[] = { + &WR_DIS_KEY_PURPOSE_0[0], // [WR_DIS.KEY0_PURPOSE] wr_dis of KEY_PURPOSE_0 + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY_PURPOSE_1[] = { + &WR_DIS_KEY_PURPOSE_1[0], // [WR_DIS.KEY1_PURPOSE] wr_dis of KEY_PURPOSE_1 + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY_PURPOSE_2[] = { + &WR_DIS_KEY_PURPOSE_2[0], // [WR_DIS.KEY2_PURPOSE] wr_dis of KEY_PURPOSE_2 + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY_PURPOSE_3[] = { + &WR_DIS_KEY_PURPOSE_3[0], // [WR_DIS.KEY3_PURPOSE] wr_dis of KEY_PURPOSE_3 + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY_PURPOSE_4[] = { + &WR_DIS_KEY_PURPOSE_4[0], // [WR_DIS.KEY4_PURPOSE] wr_dis of KEY_PURPOSE_4 + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY_PURPOSE_5[] = { + &WR_DIS_KEY_PURPOSE_5[0], // [WR_DIS.KEY5_PURPOSE] wr_dis of KEY_PURPOSE_5 + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SEC_DPA_LEVEL[] = { + &WR_DIS_SEC_DPA_LEVEL[0], // [] wr_dis of SEC_DPA_LEVEL + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_CRYPT_DPA_ENABLE[] = { + &WR_DIS_CRYPT_DPA_ENABLE[0], // [] wr_dis of CRYPT_DPA_ENABLE + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SECURE_BOOT_EN[] = { + &WR_DIS_SECURE_BOOT_EN[0], // [] wr_dis of SECURE_BOOT_EN + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SECURE_BOOT_AGGRESSIVE_REVOKE[] = { + &WR_DIS_SECURE_BOOT_AGGRESSIVE_REVOKE[0], // [] wr_dis of SECURE_BOOT_AGGRESSIVE_REVOKE + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ECDSA_FORCE_USE_HARDWARE_K[] = { + &WR_DIS_ECDSA_FORCE_USE_HARDWARE_K[0], // [] wr_dis of ECDSA_FORCE_USE_HARDWARE_K + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_FLASH_TPUW[] = { + &WR_DIS_FLASH_TPUW[0], // [] wr_dis of FLASH_TPUW + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_DOWNLOAD_MODE[] = { + &WR_DIS_DIS_DOWNLOAD_MODE[0], // [] wr_dis of DIS_DOWNLOAD_MODE + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_DIRECT_BOOT[] = { + &WR_DIS_DIS_DIRECT_BOOT[0], // [] wr_dis of DIS_DIRECT_BOOT + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_USB_SERIAL_JTAG_ROM_PRINT[] = { + &WR_DIS_DIS_USB_SERIAL_JTAG_ROM_PRINT[0], // [WR_DIS.DIS_USB_PRINT] wr_dis of DIS_USB_SERIAL_JTAG_ROM_PRINT + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE[] = { + &WR_DIS_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE[0], // [] wr_dis of DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ENABLE_SECURITY_DOWNLOAD[] = { + &WR_DIS_ENABLE_SECURITY_DOWNLOAD[0], // [] wr_dis of ENABLE_SECURITY_DOWNLOAD + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_UART_PRINT_CONTROL[] = { + &WR_DIS_UART_PRINT_CONTROL[0], // [] wr_dis of UART_PRINT_CONTROL + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_FORCE_SEND_RESUME[] = { + &WR_DIS_FORCE_SEND_RESUME[0], // [] wr_dis of FORCE_SEND_RESUME + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SECURE_VERSION[] = { + &WR_DIS_SECURE_VERSION[0], // [] wr_dis of SECURE_VERSION + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SECURE_BOOT_DISABLE_FAST_WAKE[] = { + &WR_DIS_SECURE_BOOT_DISABLE_FAST_WAKE[0], // [] wr_dis of SECURE_BOOT_DISABLE_FAST_WAKE + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_HYS_EN_PAD0[] = { + &WR_DIS_HYS_EN_PAD0[0], // [] wr_dis of HYS_EN_PAD0 + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_HYS_EN_PAD1[] = { + &WR_DIS_HYS_EN_PAD1[0], // [] wr_dis of HYS_EN_PAD1 + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLK1[] = { + &WR_DIS_BLK1[0], // [] wr_dis of BLOCK1 + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_MAC[] = { + &WR_DIS_MAC[0], // [WR_DIS.MAC_FACTORY] wr_dis of MAC + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_MAC_EXT[] = { + &WR_DIS_MAC_EXT[0], // [] wr_dis of MAC_EXT + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_RXIQ_VERSION[] = { + &WR_DIS_RXIQ_VERSION[0], // [] wr_dis of RXIQ_VERSION + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_RXIQ_0[] = { + &WR_DIS_RXIQ_0[0], // [] wr_dis of RXIQ_0 + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_RXIQ_1[] = { + &WR_DIS_RXIQ_1[0], // [] wr_dis of RXIQ_1 + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ACTIVE_HP_DBIAS[] = { + &WR_DIS_ACTIVE_HP_DBIAS[0], // [] wr_dis of ACTIVE_HP_DBIAS + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ACTIVE_LP_DBIAS[] = { + &WR_DIS_ACTIVE_LP_DBIAS[0], // [] wr_dis of ACTIVE_LP_DBIAS + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DSLP_DBIAS[] = { + &WR_DIS_DSLP_DBIAS[0], // [] wr_dis of DSLP_DBIAS + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DBIAS_VOL_GAP[] = { + &WR_DIS_DBIAS_VOL_GAP[0], // [] wr_dis of DBIAS_VOL_GAP + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_WAFER_VERSION_MINOR[] = { + &WR_DIS_WAFER_VERSION_MINOR[0], // [] wr_dis of WAFER_VERSION_MINOR + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_WAFER_VERSION_MAJOR[] = { + &WR_DIS_WAFER_VERSION_MAJOR[0], // [] wr_dis of WAFER_VERSION_MAJOR + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DISABLE_WAFER_VERSION_MAJOR[] = { + &WR_DIS_DISABLE_WAFER_VERSION_MAJOR[0], // [] wr_dis of DISABLE_WAFER_VERSION_MAJOR + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_FLASH_CAP[] = { + &WR_DIS_FLASH_CAP[0], // [] wr_dis of FLASH_CAP + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_FLASH_TEMP[] = { + &WR_DIS_FLASH_TEMP[0], // [] wr_dis of FLASH_TEMP + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_FLASH_VENDOR[] = { + &WR_DIS_FLASH_VENDOR[0], // [] wr_dis of FLASH_VENDOR + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_PKG_VERSION[] = { + &WR_DIS_PKG_VERSION[0], // [] wr_dis of PKG_VERSION + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SYS_DATA_PART1[] = { + &WR_DIS_SYS_DATA_PART1[0], // [] wr_dis of BLOCK2 + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_OPTIONAL_UNIQUE_ID[] = { + &WR_DIS_OPTIONAL_UNIQUE_ID[0], // [] wr_dis of OPTIONAL_UNIQUE_ID + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLK_VERSION_MINOR[] = { + &WR_DIS_BLK_VERSION_MINOR[0], // [] wr_dis of BLK_VERSION_MINOR + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLK_VERSION_MAJOR[] = { + &WR_DIS_BLK_VERSION_MAJOR[0], // [] wr_dis of BLK_VERSION_MAJOR + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DISABLE_BLK_VERSION_MAJOR[] = { + &WR_DIS_DISABLE_BLK_VERSION_MAJOR[0], // [] wr_dis of DISABLE_BLK_VERSION_MAJOR + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_TEMP_CALIB[] = { + &WR_DIS_TEMP_CALIB[0], // [] wr_dis of TEMP_CALIB + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_AVE_INITCODE_ATTEN0[] = { + &WR_DIS_ADC1_AVE_INITCODE_ATTEN0[0], // [] wr_dis of ADC1_AVE_INITCODE_ATTEN0 + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_AVE_INITCODE_ATTEN1[] = { + &WR_DIS_ADC1_AVE_INITCODE_ATTEN1[0], // [] wr_dis of ADC1_AVE_INITCODE_ATTEN1 + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_AVE_INITCODE_ATTEN2[] = { + &WR_DIS_ADC1_AVE_INITCODE_ATTEN2[0], // [] wr_dis of ADC1_AVE_INITCODE_ATTEN2 + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_AVE_INITCODE_ATTEN3[] = { + &WR_DIS_ADC1_AVE_INITCODE_ATTEN3[0], // [] wr_dis of ADC1_AVE_INITCODE_ATTEN3 + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_HI_DOUT_ATTEN0[] = { + &WR_DIS_ADC1_HI_DOUT_ATTEN0[0], // [] wr_dis of ADC1_HI_DOUT_ATTEN0 + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_HI_DOUT_ATTEN1[] = { + &WR_DIS_ADC1_HI_DOUT_ATTEN1[0], // [] wr_dis of ADC1_HI_DOUT_ATTEN1 + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_HI_DOUT_ATTEN2[] = { + &WR_DIS_ADC1_HI_DOUT_ATTEN2[0], // [] wr_dis of ADC1_HI_DOUT_ATTEN2 + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_HI_DOUT_ATTEN3[] = { + &WR_DIS_ADC1_HI_DOUT_ATTEN3[0], // [] wr_dis of ADC1_HI_DOUT_ATTEN3 + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_CH0_ATTEN0_INITCODE_DIFF[] = { + &WR_DIS_ADC1_CH0_ATTEN0_INITCODE_DIFF[0], // [] wr_dis of ADC1_CH0_ATTEN0_INITCODE_DIFF + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_CH1_ATTEN0_INITCODE_DIFF[] = { + &WR_DIS_ADC1_CH1_ATTEN0_INITCODE_DIFF[0], // [] wr_dis of ADC1_CH1_ATTEN0_INITCODE_DIFF + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_CH2_ATTEN0_INITCODE_DIFF[] = { + &WR_DIS_ADC1_CH2_ATTEN0_INITCODE_DIFF[0], // [] wr_dis of ADC1_CH2_ATTEN0_INITCODE_DIFF + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_CH3_ATTEN0_INITCODE_DIFF[] = { + &WR_DIS_ADC1_CH3_ATTEN0_INITCODE_DIFF[0], // [] wr_dis of ADC1_CH3_ATTEN0_INITCODE_DIFF + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_CH4_ATTEN0_INITCODE_DIFF[] = { + &WR_DIS_ADC1_CH4_ATTEN0_INITCODE_DIFF[0], // [] wr_dis of ADC1_CH4_ATTEN0_INITCODE_DIFF + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLOCK_USR_DATA[] = { + &WR_DIS_BLOCK_USR_DATA[0], // [WR_DIS.USER_DATA] wr_dis of BLOCK_USR_DATA + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_CUSTOM_MAC[] = { + &WR_DIS_CUSTOM_MAC[0], // [WR_DIS.MAC_CUSTOM WR_DIS.USER_DATA_MAC_CUSTOM] wr_dis of CUSTOM_MAC + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLOCK_KEY0[] = { + &WR_DIS_BLOCK_KEY0[0], // [WR_DIS.KEY0] wr_dis of BLOCK_KEY0 + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLOCK_KEY1[] = { + &WR_DIS_BLOCK_KEY1[0], // [WR_DIS.KEY1] wr_dis of BLOCK_KEY1 + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLOCK_KEY2[] = { + &WR_DIS_BLOCK_KEY2[0], // [WR_DIS.KEY2] wr_dis of BLOCK_KEY2 + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLOCK_KEY3[] = { + &WR_DIS_BLOCK_KEY3[0], // [WR_DIS.KEY3] wr_dis of BLOCK_KEY3 + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLOCK_KEY4[] = { + &WR_DIS_BLOCK_KEY4[0], // [WR_DIS.KEY4] wr_dis of BLOCK_KEY4 + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLOCK_KEY5[] = { + &WR_DIS_BLOCK_KEY5[0], // [WR_DIS.KEY5] wr_dis of BLOCK_KEY5 + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLOCK_SYS_DATA2[] = { + &WR_DIS_BLOCK_SYS_DATA2[0], // [WR_DIS.SYS_DATA_PART2] wr_dis of BLOCK_SYS_DATA2 + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_USB_EXCHG_PINS[] = { + &WR_DIS_USB_EXCHG_PINS[0], // [] wr_dis of USB_EXCHG_PINS + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_VDD_SPI_AS_GPIO[] = { + &WR_DIS_VDD_SPI_AS_GPIO[0], // [] wr_dis of VDD_SPI_AS_GPIO + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SOFT_DIS_JTAG[] = { + &WR_DIS_SOFT_DIS_JTAG[0], // [] wr_dis of SOFT_DIS_JTAG + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_RD_DIS[] = { + &RD_DIS[0], // [] Disable reading from BlOCK4-10 + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_BLOCK_KEY0[] = { + &RD_DIS_BLOCK_KEY0[0], // [RD_DIS.KEY0] rd_dis of BLOCK_KEY0 + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_BLOCK_KEY1[] = { + &RD_DIS_BLOCK_KEY1[0], // [RD_DIS.KEY1] rd_dis of BLOCK_KEY1 + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_BLOCK_KEY2[] = { + &RD_DIS_BLOCK_KEY2[0], // [RD_DIS.KEY2] rd_dis of BLOCK_KEY2 + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_BLOCK_KEY3[] = { + &RD_DIS_BLOCK_KEY3[0], // [RD_DIS.KEY3] rd_dis of BLOCK_KEY3 + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_BLOCK_KEY4[] = { + &RD_DIS_BLOCK_KEY4[0], // [RD_DIS.KEY4] rd_dis of BLOCK_KEY4 + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_BLOCK_KEY5[] = { + &RD_DIS_BLOCK_KEY5[0], // [RD_DIS.KEY5] rd_dis of BLOCK_KEY5 + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_BLOCK_SYS_DATA2[] = { + &RD_DIS_BLOCK_SYS_DATA2[0], // [RD_DIS.SYS_DATA_PART2] rd_dis of BLOCK_SYS_DATA2 + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_PVT_GLITCH_EN[] = { + &PVT_GLITCH_EN[0], // [] Represents whether pvt glitch is enabled + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_DIS_ICACHE[] = { + &DIS_ICACHE[0], // [] Represents whether icache is disabled + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_DIS_USB_JTAG[] = { + &DIS_USB_JTAG[0], // [] Represents whether the function of usb switch to jtag is disabled or enabled. 1: disabled. 0: enabled + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_POWERGLITCH_EN[] = { + &POWERGLITCH_EN[0], // [] Represents whether power glitch function is enabled. 1: enabled. 0: disabled + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_DIS_USJ[] = { + &DIS_USJ[0], // [] Represents whether usb serial jtag is disabled + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_DIS_FORCE_DOWNLOAD[] = { + &DIS_FORCE_DOWNLOAD[0], // [] Represents whether the function that forces chip into download mode is disabled or enabled. 1: disabled. 0: enabled + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_SPI_DOWNLOAD_MSPI_DIS[] = { + &SPI_DOWNLOAD_MSPI_DIS[0], // [] Represents whether SPI0 controller during boot_mode_download is disabled or enabled. 1: disabled. 0: enabled + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_DIS_TWAI[] = { + &DIS_TWAI[0], // [DIS_CAN] Represents whether TWAI function is disabled or enabled. 1: disabled. 0: enabled + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_JTAG_SEL_ENABLE[] = { + &JTAG_SEL_ENABLE[0], // [] Set this bit to enable selection between usb_to_jtag and pad_to_jtag through strapping gpio25 when both EFUSE_DIS_PAD_JTAG and EFUSE_DIS_USB_JTAG are equal to 0 + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_SOFT_DIS_JTAG[] = { + &SOFT_DIS_JTAG[0], // [] Represents whether JTAG is disabled in soft way. Odd number: disabled. Even number: enabled + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_DIS_PAD_JTAG[] = { + &DIS_PAD_JTAG[0], // [] Represents whether JTAG is disabled in the hard way(permanently). 1: disabled. 0: enabled + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT[] = { + &DIS_DOWNLOAD_MANUAL_ENCRYPT[0], // [] Represents whether flash encrypt function is disabled or enabled(except in SPI boot mode). 1: disabled. 0: enabled + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_USB_DREFH[] = { + &USB_DREFH[0], // [] USB drefh + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_USB_DREFL[] = { + &USB_DREFL[0], // [] USB drefl + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_USB_EXCHG_PINS[] = { + &USB_EXCHG_PINS[0], // [] Represents whether the D+ and D- pins is exchanged. 1: exchanged. 0: not exchanged + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_VDD_SPI_AS_GPIO[] = { + &VDD_SPI_AS_GPIO[0], // [] Represents whether vdd spi pin is functioned as gpio. 1: functioned. 0: not functioned + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_ECDSA_CURVE_MODE[] = { + &ECDSA_CURVE_MODE[0], // [] ECDSA curve mode. 0: only P256. 1: only P192. 2: both P192 and P256. 3: only P256 + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_ECC_FORCE_CONST_TIME[] = { + &ECC_FORCE_CONST_TIME[0], // [] ECC force const time + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_XTS_DPA_PSEUDO_LEVEL[] = { + &XTS_DPA_PSEUDO_LEVEL[0], // [] XTS DPA pseudo level + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_IO_LDO_ADJUST[] = { + &IO_LDO_ADJUST[0], // [] Represents configuration of IO LDO mode and voltage. + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_VDD_SPI_LDO_ADJUST[] = { + &VDD_SPI_LDO_ADJUST[0], // [] Represents configuration of FLASH LDO mode and voltage + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WDT_DELAY_SEL[] = { + &WDT_DELAY_SEL[0], // [] Represents whether RTC watchdog timeout threshold is selected at startup. 1: selected. 0: not selected + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_SPI_BOOT_CRYPT_CNT[] = { + &SPI_BOOT_CRYPT_CNT[0], // [] Enables flash encryption when 1 or 3 bits are set and disables otherwise {0: "Disable"; 1: "Enable"; 3: "Disable"; 7: "Enable"} + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_SECURE_BOOT_KEY_REVOKE0[] = { + &SECURE_BOOT_KEY_REVOKE0[0], // [] Revoke 1st secure boot key + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_SECURE_BOOT_KEY_REVOKE1[] = { + &SECURE_BOOT_KEY_REVOKE1[0], // [] Revoke 2nd secure boot key + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_SECURE_BOOT_KEY_REVOKE2[] = { + &SECURE_BOOT_KEY_REVOKE2[0], // [] Revoke 3rd secure boot key + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_KEY_PURPOSE_0[] = { + &KEY_PURPOSE_0[0], // [KEY0_PURPOSE] Represents the purpose of Key0 + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_KEY_PURPOSE_1[] = { + &KEY_PURPOSE_1[0], // [KEY1_PURPOSE] Represents the purpose of Key1 + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_KEY_PURPOSE_2[] = { + &KEY_PURPOSE_2[0], // [KEY2_PURPOSE] Represents the purpose of Key2 + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_KEY_PURPOSE_3[] = { + &KEY_PURPOSE_3[0], // [KEY3_PURPOSE] Represents the purpose of Key3 + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_KEY_PURPOSE_4[] = { + &KEY_PURPOSE_4[0], // [KEY4_PURPOSE] Represents the purpose of Key4 + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_KEY_PURPOSE_5[] = { + &KEY_PURPOSE_5[0], // [KEY5_PURPOSE] Represents the purpose of Key5 + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_SEC_DPA_LEVEL[] = { + &SEC_DPA_LEVEL[0], // [] Represents the spa secure level by configuring the clock random divide mode + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_IO_LDO_1P8[] = { + &IO_LDO_1P8[0], // [] Represents select IO LDO voltage to 1.8V or 3.3V.\\ 1: 1.8V\\ 0: 3.3V + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_CRYPT_DPA_ENABLE[] = { + &CRYPT_DPA_ENABLE[0], // [] Represents whether anti-dpa attack is enabled. 1:enabled. 0: disabled + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_SECURE_BOOT_EN[] = { + &SECURE_BOOT_EN[0], // [] Represents whether secure boot is enabled or disabled. 1: enabled. 0: disabled + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE[] = { + &SECURE_BOOT_AGGRESSIVE_REVOKE[0], // [] Represents whether revoking aggressive secure boot is enabled or disabled. 1: enabled. 0: disabled + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_POWERGLITCH_EN1[] = { + &POWERGLITCH_EN1[0], // [] Represents whether to enable power glitch function when chip power on + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_FLASH_TPUW[] = { + &FLASH_TPUW[0], // [] Represents the flash waiting time after power-up; in unit of ms. When the value less than 15; the waiting time is the programmed value. Otherwise; the waiting time is 2 times the programmed value + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_DIS_DOWNLOAD_MODE[] = { + &DIS_DOWNLOAD_MODE[0], // [] Represents whether Download mode is disabled or enabled. 1: disabled. 0: enabled + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_DIS_DIRECT_BOOT[] = { + &DIS_DIRECT_BOOT[0], // [] Represents whether direct boot mode is disabled or enabled. 1: disabled. 0: enabled + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT[] = { + &DIS_USB_SERIAL_JTAG_ROM_PRINT[0], // [DIS_USB_PRINT] Set this bit to disable USB-Serial-JTAG print during rom boot + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE[] = { + &DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE[0], // [] Represents whether the USB-Serial-JTAG download function is disabled or enabled. 1: disabled. 0: enabled + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_ENABLE_SECURITY_DOWNLOAD[] = { + &ENABLE_SECURITY_DOWNLOAD[0], // [] Represents whether security download is enabled or disabled. 1: enabled. 0: disabled + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_UART_PRINT_CONTROL[] = { + &UART_PRINT_CONTROL[0], // [] Set the default UARTboot message output mode {0: "Enable"; 1: "Enable when GPIO8 is low at reset"; 2: "Enable when GPIO8 is high at reset"; 3: "Disable"} + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_FORCE_SEND_RESUME[] = { + &FORCE_SEND_RESUME[0], // [] Represents whether ROM code is forced to send a resume command during SPI boot. 1: forced. 0:not forced + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_SECURE_VERSION[] = { + &SECURE_VERSION[0], // [] Represents the version used by ESP-IDF anti-rollback feature + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_SECURE_BOOT_DISABLE_FAST_WAKE[] = { + &SECURE_BOOT_DISABLE_FAST_WAKE[0], // [] Represents whether FAST VERIFY ON WAKE is disabled or enabled when Secure Boot is enabled. 1: disabled. 0: enabled + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_HYS_EN_PAD0[] = { + &HYS_EN_PAD0[0], // [] Set bits to enable hysteresis function of PAD0~5 + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_HYS_EN_PAD1[] = { + &HYS_EN_PAD1[0], // [] Set bits to enable hysteresis function of PAD6~27 + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_MAC[] = { + &MAC[0], // [MAC_FACTORY] MAC address + &MAC[1], // [MAC_FACTORY] MAC address + &MAC[2], // [MAC_FACTORY] MAC address + &MAC[3], // [MAC_FACTORY] MAC address + &MAC[4], // [MAC_FACTORY] MAC address + &MAC[5], // [MAC_FACTORY] MAC address + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_MAC_EXT[] = { + &MAC_EXT[0], // [] Stores the extended bits of MAC address + &MAC_EXT[1], // [] Stores the extended bits of MAC address + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_RXIQ_VERSION[] = { + &RXIQ_VERSION[0], // [] Stores RF Calibration data. RXIQ version + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_RXIQ_0[] = { + &RXIQ_0[0], // [] Stores RF Calibration data. RXIQ data 0 + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_RXIQ_1[] = { + &RXIQ_1[0], // [] Stores RF Calibration data. RXIQ data 1 + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_ACTIVE_HP_DBIAS[] = { + &ACTIVE_HP_DBIAS[0], // [] Stores the PMU active hp dbias + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_ACTIVE_LP_DBIAS[] = { + &ACTIVE_LP_DBIAS[0], // [] Stores the PMU active lp dbias + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_DSLP_DBIAS[] = { + &DSLP_DBIAS[0], // [] Stores the PMU sleep dbias + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_DBIAS_VOL_GAP[] = { + &DBIAS_VOL_GAP[0], // [] Stores the low 1 bit of dbias_vol_gap + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WAFER_VERSION_MINOR[] = { + &WAFER_VERSION_MINOR[0], // [] Stores the wafer version minor + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WAFER_VERSION_MAJOR[] = { + &WAFER_VERSION_MAJOR[0], // [] Stores the wafer version major + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_DISABLE_WAFER_VERSION_MAJOR[] = { + &DISABLE_WAFER_VERSION_MAJOR[0], // [] Disables check of wafer version major + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_FLASH_CAP[] = { + &FLASH_CAP[0], // [] Stores the flash cap + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_FLASH_TEMP[] = { + &FLASH_TEMP[0], // [] Stores the flash temp + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_FLASH_VENDOR[] = { + &FLASH_VENDOR[0], // [] Stores the flash vendor + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_PKG_VERSION[] = { + &PKG_VERSION[0], // [] Package version + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_OPTIONAL_UNIQUE_ID[] = { + &OPTIONAL_UNIQUE_ID[0], // [] Optional unique 128-bit ID + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_BLK_VERSION_MINOR[] = { + &BLK_VERSION_MINOR[0], // [] BLK_VERSION_MINOR of BLOCK2. 1: RF Calibration data in BLOCK1 + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_BLK_VERSION_MAJOR[] = { + &BLK_VERSION_MAJOR[0], // [] BLK_VERSION_MAJOR of BLOCK2 + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_DISABLE_BLK_VERSION_MAJOR[] = { + &DISABLE_BLK_VERSION_MAJOR[0], // [] Disables check of blk version major + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_TEMP_CALIB[] = { + &TEMP_CALIB[0], // [] Temperature calibration data + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_ADC1_AVE_INITCODE_ATTEN0[] = { + &ADC1_AVE_INITCODE_ATTEN0[0], // [] ADC1 calibration data + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_ADC1_AVE_INITCODE_ATTEN1[] = { + &ADC1_AVE_INITCODE_ATTEN1[0], // [] ADC1 calibration data + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_ADC1_AVE_INITCODE_ATTEN2[] = { + &ADC1_AVE_INITCODE_ATTEN2[0], // [] ADC1 calibration data + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_ADC1_AVE_INITCODE_ATTEN3[] = { + &ADC1_AVE_INITCODE_ATTEN3[0], // [] ADC1 calibration data + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_ADC1_HI_DOUT_ATTEN0[] = { + &ADC1_HI_DOUT_ATTEN0[0], // [] ADC1 calibration data + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_ADC1_HI_DOUT_ATTEN1[] = { + &ADC1_HI_DOUT_ATTEN1[0], // [] ADC1 calibration data + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_ADC1_HI_DOUT_ATTEN2[] = { + &ADC1_HI_DOUT_ATTEN2[0], // [] ADC1 calibration data + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_ADC1_HI_DOUT_ATTEN3[] = { + &ADC1_HI_DOUT_ATTEN3[0], // [] ADC1 calibration data + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_ADC1_CH0_ATTEN0_INITCODE_DIFF[] = { + &ADC1_CH0_ATTEN0_INITCODE_DIFF[0], // [] ADC1 calibration data + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_ADC1_CH1_ATTEN0_INITCODE_DIFF[] = { + &ADC1_CH1_ATTEN0_INITCODE_DIFF[0], // [] ADC1 calibration data + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_ADC1_CH2_ATTEN0_INITCODE_DIFF[] = { + &ADC1_CH2_ATTEN0_INITCODE_DIFF[0], // [] ADC1 calibration data + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_ADC1_CH3_ATTEN0_INITCODE_DIFF[] = { + &ADC1_CH3_ATTEN0_INITCODE_DIFF[0], // [] ADC1 calibration data + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_ADC1_CH4_ATTEN0_INITCODE_DIFF[] = { + &ADC1_CH4_ATTEN0_INITCODE_DIFF[0], // [] ADC1 calibration data + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_USER_DATA[] = { + &USER_DATA[0], // [BLOCK_USR_DATA] User data + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_USER_DATA_MAC_CUSTOM[] = { + &USER_DATA_MAC_CUSTOM[0], // [MAC_CUSTOM CUSTOM_MAC] Custom MAC + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_KEY0[] = { + &KEY0[0], // [BLOCK_KEY0] Key0 or user data + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_KEY1[] = { + &KEY1[0], // [BLOCK_KEY1] Key1 or user data + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_KEY2[] = { + &KEY2[0], // [BLOCK_KEY2] Key2 or user data + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_KEY3[] = { + &KEY3[0], // [BLOCK_KEY3] Key3 or user data + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_KEY4[] = { + &KEY4[0], // [BLOCK_KEY4] Key4 or user data + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_KEY5[] = { + &KEY5[0], // [BLOCK_KEY5] Key5 or user data + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_SYS_DATA_PART2[] = { + &SYS_DATA_PART2[0], // [BLOCK_SYS_DATA2] System data part 2 (reserved) + NULL +}; diff --git a/components/efuse/esp32h21/esp_efuse_table.csv b/components/efuse/esp32h21/esp_efuse_table.csv new file mode 100644 index 00000000000..0f39ced2672 --- /dev/null +++ b/components/efuse/esp32h21/esp_efuse_table.csv @@ -0,0 +1,209 @@ + +# field_name, | efuse_block, | bit_start, | bit_count, |comment # +# | (EFUSE_BLK0 | (0..255) | (1-256) | # +# | EFUSE_BLK1 | | | # +# | ...) | | | # +########################################################################## +# !!!!!!!!!!! # +# After editing this file, run the command manually "idf.py efuse-common-table" +# this will generate new source files, next rebuild all the sources. +# !!!!!!!!!!! # + +# TODO: [ESP32H21] IDF-11556, file inherit from verify code, please check + +# This file was generated by regtools.py based on the efuses.yaml file with the version: ef562916e77cf77203c1a4c0cff35ac5 + +WR_DIS, EFUSE_BLK0, 0, 32, [] Disable programming of individual eFuses +WR_DIS.RD_DIS, EFUSE_BLK0, 0, 1, [] wr_dis of RD_DIS +WR_DIS.DIS_ICACHE, EFUSE_BLK0, 2, 1, [] wr_dis of DIS_ICACHE +WR_DIS.DIS_USB_JTAG, EFUSE_BLK0, 2, 1, [] wr_dis of DIS_USB_JTAG +WR_DIS.POWERGLITCH_EN, EFUSE_BLK0, 2, 1, [] wr_dis of POWERGLITCH_EN +WR_DIS.DIS_FORCE_DOWNLOAD, EFUSE_BLK0, 2, 1, [] wr_dis of DIS_FORCE_DOWNLOAD +WR_DIS.SPI_DOWNLOAD_MSPI_DIS, EFUSE_BLK0, 2, 1, [] wr_dis of SPI_DOWNLOAD_MSPI_DIS +WR_DIS.DIS_TWAI, EFUSE_BLK0, 2, 1, [WR_DIS.DIS_CAN] wr_dis of DIS_TWAI +WR_DIS.JTAG_SEL_ENABLE, EFUSE_BLK0, 2, 1, [] wr_dis of JTAG_SEL_ENABLE +WR_DIS.DIS_PAD_JTAG, EFUSE_BLK0, 2, 1, [] wr_dis of DIS_PAD_JTAG +WR_DIS.DIS_DOWNLOAD_MANUAL_ENCRYPT, EFUSE_BLK0, 2, 1, [] wr_dis of DIS_DOWNLOAD_MANUAL_ENCRYPT +WR_DIS.WDT_DELAY_SEL, EFUSE_BLK0, 3, 1, [] wr_dis of WDT_DELAY_SEL +WR_DIS.SPI_BOOT_CRYPT_CNT, EFUSE_BLK0, 4, 1, [] wr_dis of SPI_BOOT_CRYPT_CNT +WR_DIS.SECURE_BOOT_KEY_REVOKE0, EFUSE_BLK0, 5, 1, [] wr_dis of SECURE_BOOT_KEY_REVOKE0 +WR_DIS.SECURE_BOOT_KEY_REVOKE1, EFUSE_BLK0, 6, 1, [] wr_dis of SECURE_BOOT_KEY_REVOKE1 +WR_DIS.SECURE_BOOT_KEY_REVOKE2, EFUSE_BLK0, 7, 1, [] wr_dis of SECURE_BOOT_KEY_REVOKE2 +WR_DIS.KEY_PURPOSE_0, EFUSE_BLK0, 8, 1, [WR_DIS.KEY0_PURPOSE] wr_dis of KEY_PURPOSE_0 +WR_DIS.KEY_PURPOSE_1, EFUSE_BLK0, 9, 1, [WR_DIS.KEY1_PURPOSE] wr_dis of KEY_PURPOSE_1 +WR_DIS.KEY_PURPOSE_2, EFUSE_BLK0, 10, 1, [WR_DIS.KEY2_PURPOSE] wr_dis of KEY_PURPOSE_2 +WR_DIS.KEY_PURPOSE_3, EFUSE_BLK0, 11, 1, [WR_DIS.KEY3_PURPOSE] wr_dis of KEY_PURPOSE_3 +WR_DIS.KEY_PURPOSE_4, EFUSE_BLK0, 12, 1, [WR_DIS.KEY4_PURPOSE] wr_dis of KEY_PURPOSE_4 +WR_DIS.KEY_PURPOSE_5, EFUSE_BLK0, 13, 1, [WR_DIS.KEY5_PURPOSE] wr_dis of KEY_PURPOSE_5 +WR_DIS.SEC_DPA_LEVEL, EFUSE_BLK0, 14, 1, [] wr_dis of SEC_DPA_LEVEL +WR_DIS.CRYPT_DPA_ENABLE, EFUSE_BLK0, 14, 1, [] wr_dis of CRYPT_DPA_ENABLE +WR_DIS.SECURE_BOOT_EN, EFUSE_BLK0, 15, 1, [] wr_dis of SECURE_BOOT_EN +WR_DIS.SECURE_BOOT_AGGRESSIVE_REVOKE, EFUSE_BLK0, 16, 1, [] wr_dis of SECURE_BOOT_AGGRESSIVE_REVOKE +WR_DIS.ECDSA_FORCE_USE_HARDWARE_K, EFUSE_BLK0, 17, 1, [] wr_dis of ECDSA_FORCE_USE_HARDWARE_K +WR_DIS.FLASH_TPUW, EFUSE_BLK0, 18, 1, [] wr_dis of FLASH_TPUW +WR_DIS.DIS_DOWNLOAD_MODE, EFUSE_BLK0, 18, 1, [] wr_dis of DIS_DOWNLOAD_MODE +WR_DIS.DIS_DIRECT_BOOT, EFUSE_BLK0, 18, 1, [] wr_dis of DIS_DIRECT_BOOT +WR_DIS.DIS_USB_SERIAL_JTAG_ROM_PRINT, EFUSE_BLK0, 18, 1, [WR_DIS.DIS_USB_PRINT] wr_dis of DIS_USB_SERIAL_JTAG_ROM_PRINT +WR_DIS.DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE, EFUSE_BLK0, 18, 1, [] wr_dis of DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE +WR_DIS.ENABLE_SECURITY_DOWNLOAD, EFUSE_BLK0, 18, 1, [] wr_dis of ENABLE_SECURITY_DOWNLOAD +WR_DIS.UART_PRINT_CONTROL, EFUSE_BLK0, 18, 1, [] wr_dis of UART_PRINT_CONTROL +WR_DIS.FORCE_SEND_RESUME, EFUSE_BLK0, 18, 1, [] wr_dis of FORCE_SEND_RESUME +WR_DIS.SECURE_VERSION, EFUSE_BLK0, 18, 1, [] wr_dis of SECURE_VERSION +WR_DIS.SECURE_BOOT_DISABLE_FAST_WAKE, EFUSE_BLK0, 18, 1, [] wr_dis of SECURE_BOOT_DISABLE_FAST_WAKE +WR_DIS.HYS_EN_PAD0, EFUSE_BLK0, 19, 1, [] wr_dis of HYS_EN_PAD0 +WR_DIS.HYS_EN_PAD1, EFUSE_BLK0, 19, 1, [] wr_dis of HYS_EN_PAD1 +WR_DIS.BLK1, EFUSE_BLK0, 20, 1, [] wr_dis of BLOCK1 +WR_DIS.MAC, EFUSE_BLK0, 20, 1, [WR_DIS.MAC_FACTORY] wr_dis of MAC +WR_DIS.MAC_EXT, EFUSE_BLK0, 20, 1, [] wr_dis of MAC_EXT +WR_DIS.RXIQ_VERSION, EFUSE_BLK0, 20, 1, [] wr_dis of RXIQ_VERSION +WR_DIS.RXIQ_0, EFUSE_BLK0, 20, 1, [] wr_dis of RXIQ_0 +WR_DIS.RXIQ_1, EFUSE_BLK0, 20, 1, [] wr_dis of RXIQ_1 +WR_DIS.ACTIVE_HP_DBIAS, EFUSE_BLK0, 20, 1, [] wr_dis of ACTIVE_HP_DBIAS +WR_DIS.ACTIVE_LP_DBIAS, EFUSE_BLK0, 20, 1, [] wr_dis of ACTIVE_LP_DBIAS +WR_DIS.DSLP_DBIAS, EFUSE_BLK0, 20, 1, [] wr_dis of DSLP_DBIAS +WR_DIS.DBIAS_VOL_GAP, EFUSE_BLK0, 20, 1, [] wr_dis of DBIAS_VOL_GAP +WR_DIS.WAFER_VERSION_MINOR, EFUSE_BLK0, 20, 1, [] wr_dis of WAFER_VERSION_MINOR +WR_DIS.WAFER_VERSION_MAJOR, EFUSE_BLK0, 20, 1, [] wr_dis of WAFER_VERSION_MAJOR +WR_DIS.DISABLE_WAFER_VERSION_MAJOR, EFUSE_BLK0, 20, 1, [] wr_dis of DISABLE_WAFER_VERSION_MAJOR +WR_DIS.FLASH_CAP, EFUSE_BLK0, 20, 1, [] wr_dis of FLASH_CAP +WR_DIS.FLASH_TEMP, EFUSE_BLK0, 20, 1, [] wr_dis of FLASH_TEMP +WR_DIS.FLASH_VENDOR, EFUSE_BLK0, 20, 1, [] wr_dis of FLASH_VENDOR +WR_DIS.PKG_VERSION, EFUSE_BLK0, 20, 1, [] wr_dis of PKG_VERSION +WR_DIS.SYS_DATA_PART1, EFUSE_BLK0, 21, 1, [] wr_dis of BLOCK2 +WR_DIS.OPTIONAL_UNIQUE_ID, EFUSE_BLK0, 21, 1, [] wr_dis of OPTIONAL_UNIQUE_ID +WR_DIS.BLK_VERSION_MINOR, EFUSE_BLK0, 21, 1, [] wr_dis of BLK_VERSION_MINOR +WR_DIS.BLK_VERSION_MAJOR, EFUSE_BLK0, 21, 1, [] wr_dis of BLK_VERSION_MAJOR +WR_DIS.DISABLE_BLK_VERSION_MAJOR, EFUSE_BLK0, 21, 1, [] wr_dis of DISABLE_BLK_VERSION_MAJOR +WR_DIS.TEMP_CALIB, EFUSE_BLK0, 21, 1, [] wr_dis of TEMP_CALIB +WR_DIS.ADC1_AVE_INITCODE_ATTEN0, EFUSE_BLK0, 21, 1, [] wr_dis of ADC1_AVE_INITCODE_ATTEN0 +WR_DIS.ADC1_AVE_INITCODE_ATTEN1, EFUSE_BLK0, 21, 1, [] wr_dis of ADC1_AVE_INITCODE_ATTEN1 +WR_DIS.ADC1_AVE_INITCODE_ATTEN2, EFUSE_BLK0, 21, 1, [] wr_dis of ADC1_AVE_INITCODE_ATTEN2 +WR_DIS.ADC1_AVE_INITCODE_ATTEN3, EFUSE_BLK0, 21, 1, [] wr_dis of ADC1_AVE_INITCODE_ATTEN3 +WR_DIS.ADC1_HI_DOUT_ATTEN0, EFUSE_BLK0, 21, 1, [] wr_dis of ADC1_HI_DOUT_ATTEN0 +WR_DIS.ADC1_HI_DOUT_ATTEN1, EFUSE_BLK0, 21, 1, [] wr_dis of ADC1_HI_DOUT_ATTEN1 +WR_DIS.ADC1_HI_DOUT_ATTEN2, EFUSE_BLK0, 21, 1, [] wr_dis of ADC1_HI_DOUT_ATTEN2 +WR_DIS.ADC1_HI_DOUT_ATTEN3, EFUSE_BLK0, 21, 1, [] wr_dis of ADC1_HI_DOUT_ATTEN3 +WR_DIS.ADC1_CH0_ATTEN0_INITCODE_DIFF, EFUSE_BLK0, 21, 1, [] wr_dis of ADC1_CH0_ATTEN0_INITCODE_DIFF +WR_DIS.ADC1_CH1_ATTEN0_INITCODE_DIFF, EFUSE_BLK0, 21, 1, [] wr_dis of ADC1_CH1_ATTEN0_INITCODE_DIFF +WR_DIS.ADC1_CH2_ATTEN0_INITCODE_DIFF, EFUSE_BLK0, 21, 1, [] wr_dis of ADC1_CH2_ATTEN0_INITCODE_DIFF +WR_DIS.ADC1_CH3_ATTEN0_INITCODE_DIFF, EFUSE_BLK0, 21, 1, [] wr_dis of ADC1_CH3_ATTEN0_INITCODE_DIFF +WR_DIS.ADC1_CH4_ATTEN0_INITCODE_DIFF, EFUSE_BLK0, 21, 1, [] wr_dis of ADC1_CH4_ATTEN0_INITCODE_DIFF +WR_DIS.BLOCK_USR_DATA, EFUSE_BLK0, 22, 1, [WR_DIS.USER_DATA] wr_dis of BLOCK_USR_DATA +WR_DIS.CUSTOM_MAC, EFUSE_BLK0, 22, 1, [WR_DIS.MAC_CUSTOM WR_DIS.USER_DATA_MAC_CUSTOM] wr_dis of CUSTOM_MAC +WR_DIS.BLOCK_KEY0, EFUSE_BLK0, 23, 1, [WR_DIS.KEY0] wr_dis of BLOCK_KEY0 +WR_DIS.BLOCK_KEY1, EFUSE_BLK0, 24, 1, [WR_DIS.KEY1] wr_dis of BLOCK_KEY1 +WR_DIS.BLOCK_KEY2, EFUSE_BLK0, 25, 1, [WR_DIS.KEY2] wr_dis of BLOCK_KEY2 +WR_DIS.BLOCK_KEY3, EFUSE_BLK0, 26, 1, [WR_DIS.KEY3] wr_dis of BLOCK_KEY3 +WR_DIS.BLOCK_KEY4, EFUSE_BLK0, 27, 1, [WR_DIS.KEY4] wr_dis of BLOCK_KEY4 +WR_DIS.BLOCK_KEY5, EFUSE_BLK0, 28, 1, [WR_DIS.KEY5] wr_dis of BLOCK_KEY5 +WR_DIS.BLOCK_SYS_DATA2, EFUSE_BLK0, 29, 1, [WR_DIS.SYS_DATA_PART2] wr_dis of BLOCK_SYS_DATA2 +WR_DIS.USB_EXCHG_PINS, EFUSE_BLK0, 30, 1, [] wr_dis of USB_EXCHG_PINS +WR_DIS.VDD_SPI_AS_GPIO, EFUSE_BLK0, 30, 1, [] wr_dis of VDD_SPI_AS_GPIO +WR_DIS.SOFT_DIS_JTAG, EFUSE_BLK0, 31, 1, [] wr_dis of SOFT_DIS_JTAG +RD_DIS, EFUSE_BLK0, 32, 7, [] Disable reading from BlOCK4-10 +RD_DIS.BLOCK_KEY0, EFUSE_BLK0, 32, 1, [RD_DIS.KEY0] rd_dis of BLOCK_KEY0 +RD_DIS.BLOCK_KEY1, EFUSE_BLK0, 33, 1, [RD_DIS.KEY1] rd_dis of BLOCK_KEY1 +RD_DIS.BLOCK_KEY2, EFUSE_BLK0, 34, 1, [RD_DIS.KEY2] rd_dis of BLOCK_KEY2 +RD_DIS.BLOCK_KEY3, EFUSE_BLK0, 35, 1, [RD_DIS.KEY3] rd_dis of BLOCK_KEY3 +RD_DIS.BLOCK_KEY4, EFUSE_BLK0, 36, 1, [RD_DIS.KEY4] rd_dis of BLOCK_KEY4 +RD_DIS.BLOCK_KEY5, EFUSE_BLK0, 37, 1, [RD_DIS.KEY5] rd_dis of BLOCK_KEY5 +RD_DIS.BLOCK_SYS_DATA2, EFUSE_BLK0, 38, 1, [RD_DIS.SYS_DATA_PART2] rd_dis of BLOCK_SYS_DATA2 +PVT_GLITCH_EN, EFUSE_BLK0, 39, 1, [] Represents whether pvt glitch is enabled +DIS_ICACHE, EFUSE_BLK0, 40, 1, [] Represents whether icache is disabled +DIS_USB_JTAG, EFUSE_BLK0, 41, 1, [] Represents whether the function of usb switch to jtag is disabled or enabled. 1: disabled. 0: enabled +POWERGLITCH_EN, EFUSE_BLK0, 42, 1, [] Represents whether power glitch function is enabled. 1: enabled. 0: disabled +DIS_USJ, EFUSE_BLK0, 43, 1, [] Represents whether usb serial jtag is disabled +DIS_FORCE_DOWNLOAD, EFUSE_BLK0, 44, 1, [] Represents whether the function that forces chip into download mode is disabled or enabled. 1: disabled. 0: enabled +SPI_DOWNLOAD_MSPI_DIS, EFUSE_BLK0, 45, 1, [] Represents whether SPI0 controller during boot_mode_download is disabled or enabled. 1: disabled. 0: enabled +DIS_TWAI, EFUSE_BLK0, 46, 1, [DIS_CAN] Represents whether TWAI function is disabled or enabled. 1: disabled. 0: enabled +JTAG_SEL_ENABLE, EFUSE_BLK0, 47, 1, [] Set this bit to enable selection between usb_to_jtag and pad_to_jtag through strapping gpio25 when both EFUSE_DIS_PAD_JTAG and EFUSE_DIS_USB_JTAG are equal to 0 +SOFT_DIS_JTAG, EFUSE_BLK0, 48, 3, [] Represents whether JTAG is disabled in soft way. Odd number: disabled. Even number: enabled +DIS_PAD_JTAG, EFUSE_BLK0, 51, 1, [] Represents whether JTAG is disabled in the hard way(permanently). 1: disabled. 0: enabled +DIS_DOWNLOAD_MANUAL_ENCRYPT, EFUSE_BLK0, 52, 1, [] Represents whether flash encrypt function is disabled or enabled(except in SPI boot mode). 1: disabled. 0: enabled +USB_DREFH, EFUSE_BLK0, 53, 2, [] USB drefh +USB_DREFL, EFUSE_BLK0, 55, 2, [] USB drefl +USB_EXCHG_PINS, EFUSE_BLK0, 57, 1, [] Represents whether the D+ and D- pins is exchanged. 1: exchanged. 0: not exchanged +VDD_SPI_AS_GPIO, EFUSE_BLK0, 58, 1, [] Represents whether vdd spi pin is functioned as gpio. 1: functioned. 0: not functioned +ECDSA_CURVE_MODE, EFUSE_BLK0, 59, 2, [] ECDSA curve mode. 0: only P256. 1: only P192. 2: both P192 and P256. 3: only P256 +ECC_FORCE_CONST_TIME, EFUSE_BLK0, 61, 1, [] ECC force const time +XTS_DPA_PSEUDO_LEVEL, EFUSE_BLK0, 62, 2, [] XTS DPA pseudo level +IO_LDO_ADJUST, EFUSE_BLK0, 64, 8, [] Represents configuration of IO LDO mode and voltage. +VDD_SPI_LDO_ADJUST, EFUSE_BLK0, 72, 8, [] Represents configuration of FLASH LDO mode and voltage +WDT_DELAY_SEL, EFUSE_BLK0, 80, 2, [] Represents whether RTC watchdog timeout threshold is selected at startup. 1: selected. 0: not selected +SPI_BOOT_CRYPT_CNT, EFUSE_BLK0, 82, 3, [] Enables flash encryption when 1 or 3 bits are set and disables otherwise {0: "Disable"; 1: "Enable"; 3: "Disable"; 7: "Enable"} +SECURE_BOOT_KEY_REVOKE0, EFUSE_BLK0, 85, 1, [] Revoke 1st secure boot key +SECURE_BOOT_KEY_REVOKE1, EFUSE_BLK0, 86, 1, [] Revoke 2nd secure boot key +SECURE_BOOT_KEY_REVOKE2, EFUSE_BLK0, 87, 1, [] Revoke 3rd secure boot key +KEY_PURPOSE_0, EFUSE_BLK0, 88, 4, [KEY0_PURPOSE] Represents the purpose of Key0 +KEY_PURPOSE_1, EFUSE_BLK0, 92, 4, [KEY1_PURPOSE] Represents the purpose of Key1 +KEY_PURPOSE_2, EFUSE_BLK0, 96, 4, [KEY2_PURPOSE] Represents the purpose of Key2 +KEY_PURPOSE_3, EFUSE_BLK0, 100, 4, [KEY3_PURPOSE] Represents the purpose of Key3 +KEY_PURPOSE_4, EFUSE_BLK0, 104, 4, [KEY4_PURPOSE] Represents the purpose of Key4 +KEY_PURPOSE_5, EFUSE_BLK0, 108, 4, [KEY5_PURPOSE] Represents the purpose of Key5 +SEC_DPA_LEVEL, EFUSE_BLK0, 112, 2, [] Represents the spa secure level by configuring the clock random divide mode +IO_LDO_1P8, EFUSE_BLK0, 114, 1, [] Represents select IO LDO voltage to 1.8V or 3.3V.\\ 1: 1.8V\\ 0: 3.3V +CRYPT_DPA_ENABLE, EFUSE_BLK0, 115, 1, [] Represents whether anti-dpa attack is enabled. 1:enabled. 0: disabled +SECURE_BOOT_EN, EFUSE_BLK0, 116, 1, [] Represents whether secure boot is enabled or disabled. 1: enabled. 0: disabled +SECURE_BOOT_AGGRESSIVE_REVOKE, EFUSE_BLK0, 117, 1, [] Represents whether revoking aggressive secure boot is enabled or disabled. 1: enabled. 0: disabled +POWERGLITCH_EN1, EFUSE_BLK0, 118, 5, [] Represents whether to enable power glitch function when chip power on +FLASH_TPUW, EFUSE_BLK0, 124, 4, [] Represents the flash waiting time after power-up; in unit of ms. When the value less than 15; the waiting time is the programmed value. Otherwise; the waiting time is 2 times the programmed value +DIS_DOWNLOAD_MODE, EFUSE_BLK0, 128, 1, [] Represents whether Download mode is disabled or enabled. 1: disabled. 0: enabled +DIS_DIRECT_BOOT, EFUSE_BLK0, 129, 1, [] Represents whether direct boot mode is disabled or enabled. 1: disabled. 0: enabled +DIS_USB_SERIAL_JTAG_ROM_PRINT, EFUSE_BLK0, 130, 1, [DIS_USB_PRINT] Set this bit to disable USB-Serial-JTAG print during rom boot +DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE, EFUSE_BLK0, 132, 1, [] Represents whether the USB-Serial-JTAG download function is disabled or enabled. 1: disabled. 0: enabled +ENABLE_SECURITY_DOWNLOAD, EFUSE_BLK0, 133, 1, [] Represents whether security download is enabled or disabled. 1: enabled. 0: disabled +UART_PRINT_CONTROL, EFUSE_BLK0, 134, 2, [] Set the default UARTboot message output mode {0: "Enable"; 1: "Enable when GPIO8 is low at reset"; 2: "Enable when GPIO8 is high at reset"; 3: "Disable"} +FORCE_SEND_RESUME, EFUSE_BLK0, 136, 1, [] Represents whether ROM code is forced to send a resume command during SPI boot. 1: forced. 0:not forced +SECURE_VERSION, EFUSE_BLK0, 137, 16, [] Represents the version used by ESP-IDF anti-rollback feature +SECURE_BOOT_DISABLE_FAST_WAKE, EFUSE_BLK0, 153, 1, [] Represents whether FAST VERIFY ON WAKE is disabled or enabled when Secure Boot is enabled. 1: disabled. 0: enabled +HYS_EN_PAD0, EFUSE_BLK0, 154, 6, [] Set bits to enable hysteresis function of PAD0~5 +HYS_EN_PAD1, EFUSE_BLK0, 160, 22, [] Set bits to enable hysteresis function of PAD6~27 +MAC, EFUSE_BLK1, 40, 8, [MAC_FACTORY] MAC address +, EFUSE_BLK1, 32, 8, [MAC_FACTORY] MAC address +, EFUSE_BLK1, 24, 8, [MAC_FACTORY] MAC address +, EFUSE_BLK1, 16, 8, [MAC_FACTORY] MAC address +, EFUSE_BLK1, 8, 8, [MAC_FACTORY] MAC address +, EFUSE_BLK1, 0, 8, [MAC_FACTORY] MAC address +MAC_EXT, EFUSE_BLK1, 56, 8, [] Stores the extended bits of MAC address +, EFUSE_BLK1, 48, 8, [] Stores the extended bits of MAC address +RXIQ_VERSION, EFUSE_BLK1, 64, 3, [] Stores RF Calibration data. RXIQ version +RXIQ_0, EFUSE_BLK1, 67, 7, [] Stores RF Calibration data. RXIQ data 0 +RXIQ_1, EFUSE_BLK1, 74, 7, [] Stores RF Calibration data. RXIQ data 1 +ACTIVE_HP_DBIAS, EFUSE_BLK1, 81, 5, [] Stores the PMU active hp dbias +ACTIVE_LP_DBIAS, EFUSE_BLK1, 86, 5, [] Stores the PMU active lp dbias +DSLP_DBIAS, EFUSE_BLK1, 91, 4, [] Stores the PMU sleep dbias +DBIAS_VOL_GAP, EFUSE_BLK1, 95, 5, [] Stores the low 1 bit of dbias_vol_gap +WAFER_VERSION_MINOR, EFUSE_BLK1, 114, 3, [] Stores the wafer version minor +WAFER_VERSION_MAJOR, EFUSE_BLK1, 117, 2, [] Stores the wafer version major +DISABLE_WAFER_VERSION_MAJOR, EFUSE_BLK1, 119, 1, [] Disables check of wafer version major +FLASH_CAP, EFUSE_BLK1, 120, 3, [] Stores the flash cap +FLASH_TEMP, EFUSE_BLK1, 123, 2, [] Stores the flash temp +FLASH_VENDOR, EFUSE_BLK1, 125, 3, [] Stores the flash vendor +PKG_VERSION, EFUSE_BLK1, 128, 3, [] Package version +OPTIONAL_UNIQUE_ID, EFUSE_BLK2, 0, 128, [] Optional unique 128-bit ID +BLK_VERSION_MINOR, EFUSE_BLK2, 130, 3, [] BLK_VERSION_MINOR of BLOCK2. 1: RF Calibration data in BLOCK1 +BLK_VERSION_MAJOR, EFUSE_BLK2, 133, 2, [] BLK_VERSION_MAJOR of BLOCK2 +DISABLE_BLK_VERSION_MAJOR, EFUSE_BLK2, 135, 1, [] Disables check of blk version major +TEMP_CALIB, EFUSE_BLK2, 136, 9, [] Temperature calibration data +ADC1_AVE_INITCODE_ATTEN0, EFUSE_BLK2, 145, 10, [] ADC1 calibration data +ADC1_AVE_INITCODE_ATTEN1, EFUSE_BLK2, 155, 10, [] ADC1 calibration data +ADC1_AVE_INITCODE_ATTEN2, EFUSE_BLK2, 165, 10, [] ADC1 calibration data +ADC1_AVE_INITCODE_ATTEN3, EFUSE_BLK2, 175, 10, [] ADC1 calibration data +ADC1_HI_DOUT_ATTEN0, EFUSE_BLK2, 185, 10, [] ADC1 calibration data +ADC1_HI_DOUT_ATTEN1, EFUSE_BLK2, 195, 10, [] ADC1 calibration data +ADC1_HI_DOUT_ATTEN2, EFUSE_BLK2, 205, 10, [] ADC1 calibration data +ADC1_HI_DOUT_ATTEN3, EFUSE_BLK2, 215, 10, [] ADC1 calibration data +ADC1_CH0_ATTEN0_INITCODE_DIFF, EFUSE_BLK2, 225, 4, [] ADC1 calibration data +ADC1_CH1_ATTEN0_INITCODE_DIFF, EFUSE_BLK2, 229, 4, [] ADC1 calibration data +ADC1_CH2_ATTEN0_INITCODE_DIFF, EFUSE_BLK2, 233, 4, [] ADC1 calibration data +ADC1_CH3_ATTEN0_INITCODE_DIFF, EFUSE_BLK2, 237, 4, [] ADC1 calibration data +ADC1_CH4_ATTEN0_INITCODE_DIFF, EFUSE_BLK2, 241, 4, [] ADC1 calibration data +USER_DATA, EFUSE_BLK3, 0, 256, [BLOCK_USR_DATA] User data +USER_DATA.MAC_CUSTOM, EFUSE_BLK3, 200, 48, [MAC_CUSTOM CUSTOM_MAC] Custom MAC +KEY0, EFUSE_BLK4, 0, 256, [BLOCK_KEY0] Key0 or user data +KEY1, EFUSE_BLK5, 0, 256, [BLOCK_KEY1] Key1 or user data +KEY2, EFUSE_BLK6, 0, 256, [BLOCK_KEY2] Key2 or user data +KEY3, EFUSE_BLK7, 0, 256, [BLOCK_KEY3] Key3 or user data +KEY4, EFUSE_BLK8, 0, 256, [BLOCK_KEY4] Key4 or user data +KEY5, EFUSE_BLK9, 0, 256, [BLOCK_KEY5] Key5 or user data +SYS_DATA_PART2, EFUSE_BLK10, 0, 256, [BLOCK_SYS_DATA2] System data part 2 (reserved) diff --git a/components/efuse/esp32h21/esp_efuse_utility.c b/components/efuse/esp32h21/esp_efuse_utility.c new file mode 100644 index 00000000000..51dca0e22de --- /dev/null +++ b/components/efuse/esp32h21/esp_efuse_utility.c @@ -0,0 +1,208 @@ +/* + * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include "sdkconfig.h" +#include "esp_log.h" +#include "assert.h" +#include "esp_efuse_utility.h" +#include "soc/efuse_periph.h" +#include "hal/efuse_hal.h" + +static const char *TAG = "efuse"; + +#ifdef CONFIG_EFUSE_VIRTUAL +extern uint32_t virt_blocks[EFUSE_BLK_MAX][COUNT_EFUSE_REG_PER_BLOCK]; +#endif // CONFIG_EFUSE_VIRTUAL + +/*Range addresses to read blocks*/ +const esp_efuse_range_addr_t range_read_addr_blocks[] = { + {EFUSE_RD_WR_DIS_REG, EFUSE_RD_REPEAT_DATA4_REG}, // range address of EFUSE_BLK0 REPEAT + {EFUSE_RD_MAC_SYS_0_REG, EFUSE_RD_MAC_SYS_5_REG}, // range address of EFUSE_BLK1 MAC_8M + {EFUSE_RD_SYS_PART1_DATA0_REG, EFUSE_RD_SYS_PART1_DATA7_REG}, // range address of EFUSE_BLK2 SYS_DATA + {EFUSE_RD_USR_DATA0_REG, EFUSE_RD_USR_DATA7_REG}, // range address of EFUSE_BLK3 USR_DATA + {EFUSE_RD_KEY0_DATA0_REG, EFUSE_RD_KEY0_DATA7_REG}, // range address of EFUSE_BLK4 KEY0 + {EFUSE_RD_KEY1_DATA0_REG, EFUSE_RD_KEY1_DATA7_REG}, // range address of EFUSE_BLK5 KEY1 + {EFUSE_RD_KEY2_DATA0_REG, EFUSE_RD_KEY2_DATA7_REG}, // range address of EFUSE_BLK6 KEY2 + {EFUSE_RD_KEY3_DATA0_REG, EFUSE_RD_KEY3_DATA7_REG}, // range address of EFUSE_BLK7 KEY3 + {EFUSE_RD_KEY4_DATA0_REG, EFUSE_RD_KEY4_DATA7_REG}, // range address of EFUSE_BLK8 KEY4 + {EFUSE_RD_KEY5_DATA0_REG, EFUSE_RD_KEY5_DATA7_REG}, // range address of EFUSE_BLK9 KEY5 + {EFUSE_RD_SYS_PART2_DATA0_REG, EFUSE_RD_SYS_PART2_DATA7_REG} // range address of EFUSE_BLK10 KEY6 +}; + +static uint32_t write_mass_blocks[EFUSE_BLK_MAX][COUNT_EFUSE_REG_PER_BLOCK] = { 0 }; + +/*Range addresses to write blocks (it is not real regs, it is buffer) */ +const esp_efuse_range_addr_t range_write_addr_blocks[] = { + {(uint32_t) &write_mass_blocks[EFUSE_BLK0][0], (uint32_t) &write_mass_blocks[EFUSE_BLK0][5]}, + {(uint32_t) &write_mass_blocks[EFUSE_BLK1][0], (uint32_t) &write_mass_blocks[EFUSE_BLK1][5]}, + {(uint32_t) &write_mass_blocks[EFUSE_BLK2][0], (uint32_t) &write_mass_blocks[EFUSE_BLK2][7]}, + {(uint32_t) &write_mass_blocks[EFUSE_BLK3][0], (uint32_t) &write_mass_blocks[EFUSE_BLK3][7]}, + {(uint32_t) &write_mass_blocks[EFUSE_BLK4][0], (uint32_t) &write_mass_blocks[EFUSE_BLK4][7]}, + {(uint32_t) &write_mass_blocks[EFUSE_BLK5][0], (uint32_t) &write_mass_blocks[EFUSE_BLK5][7]}, + {(uint32_t) &write_mass_blocks[EFUSE_BLK6][0], (uint32_t) &write_mass_blocks[EFUSE_BLK6][7]}, + {(uint32_t) &write_mass_blocks[EFUSE_BLK7][0], (uint32_t) &write_mass_blocks[EFUSE_BLK7][7]}, + {(uint32_t) &write_mass_blocks[EFUSE_BLK8][0], (uint32_t) &write_mass_blocks[EFUSE_BLK8][7]}, + {(uint32_t) &write_mass_blocks[EFUSE_BLK9][0], (uint32_t) &write_mass_blocks[EFUSE_BLK9][7]}, + {(uint32_t) &write_mass_blocks[EFUSE_BLK10][0], (uint32_t) &write_mass_blocks[EFUSE_BLK10][7]}, +}; + +#ifndef CONFIG_EFUSE_VIRTUAL +// Update Efuse timing configuration +static esp_err_t esp_efuse_set_timing(void) +{ + // efuse clock is fixed. + // An argument (0) is for compatibility and will be ignored. + efuse_hal_set_timing(0); + return ESP_OK; +} +#endif // ifndef CONFIG_EFUSE_VIRTUAL + +// Efuse read operation: copies data from physical efuses to efuse read registers. +void esp_efuse_utility_clear_program_registers(void) +{ + efuse_hal_read(); + efuse_hal_clear_program_registers(); +} + +esp_err_t esp_efuse_utility_check_errors(void) +{ + return ESP_OK; +} + +// Burn values written to the efuse write registers +esp_err_t esp_efuse_utility_burn_chip(void) +{ + return esp_efuse_utility_burn_chip_opt(false, true); +} + +esp_err_t esp_efuse_utility_burn_chip_opt(bool ignore_coding_errors, bool verify_written_data) +{ + esp_err_t error = ESP_OK; +#ifdef CONFIG_EFUSE_VIRTUAL + (void) ignore_coding_errors; + (void) verify_written_data; + ESP_LOGW(TAG, "Virtual efuses enabled: Not really burning eFuses"); + for (int num_block = EFUSE_BLK_MAX - 1; num_block >= EFUSE_BLK0; num_block--) { + int subblock = 0; + for (uint32_t addr_wr_block = range_write_addr_blocks[num_block].start; addr_wr_block <= range_write_addr_blocks[num_block].end; addr_wr_block += 4) { + virt_blocks[num_block][subblock++] |= REG_READ(addr_wr_block); + } + } +#ifdef CONFIG_EFUSE_VIRTUAL_KEEP_IN_FLASH + esp_efuse_utility_write_efuses_to_flash(); +#endif +#else // CONFIG_EFUSE_VIRTUAL + if (esp_efuse_set_timing() != ESP_OK) { + ESP_LOGE(TAG, "Efuse fields are not burnt"); + } else { + // Permanently update values written to the efuse write registers + // It is necessary to process blocks in the order from MAX-> EFUSE_BLK0, because EFUSE_BLK0 has protection bits for other blocks. + for (int num_block = EFUSE_BLK_MAX - 1; num_block >= EFUSE_BLK0; num_block--) { + bool need_burn_block = false; + for (uint32_t addr_wr_block = range_write_addr_blocks[num_block].start; addr_wr_block <= range_write_addr_blocks[num_block].end; addr_wr_block += 4) { + if (REG_READ(addr_wr_block) != 0) { + need_burn_block = true; + break; + } + } + if (!need_burn_block) { + continue; + } + if (error) { + // It is done for a use case: BLOCK2 (Flash encryption key) could have an error (incorrect written data) + // in this case we can not burn any data into BLOCK0 because it might set read/write protections of BLOCK2. + ESP_LOGE(TAG, "BLOCK%d can not be burned because a previous block got an error, skipped.", num_block); + continue; + } + efuse_hal_clear_program_registers(); + if (esp_efuse_get_coding_scheme(num_block) == EFUSE_CODING_SCHEME_RS) { + uint8_t block_rs[12]; + efuse_hal_rs_calculate((void *)range_write_addr_blocks[num_block].start, block_rs); + hal_memcpy((void *)EFUSE_PGM_CHECK_VALUE0_REG, block_rs, sizeof(block_rs)); + } + unsigned r_data_len = (range_read_addr_blocks[num_block].end - range_read_addr_blocks[num_block].start) + sizeof(uint32_t); + unsigned data_len = (range_write_addr_blocks[num_block].end - range_write_addr_blocks[num_block].start) + sizeof(uint32_t); + memcpy((void *)EFUSE_PGM_DATA0_REG, (void *)range_write_addr_blocks[num_block].start, data_len); + + uint32_t backup_write_data[8 + 3]; // 8 words are data and 3 words are RS coding data + hal_memcpy(backup_write_data, (void *)EFUSE_PGM_DATA0_REG, sizeof(backup_write_data)); + int repeat_burn_op = 1; + bool correct_written_data; + bool coding_error_before = !ignore_coding_errors && efuse_hal_is_coding_error_in_block(num_block); + if (coding_error_before) { + ESP_LOGW(TAG, "BLOCK%d already has a coding error", num_block); + } + bool coding_error_occurred; + + do { + ESP_LOGI(TAG, "BURN BLOCK%d", num_block); + efuse_hal_program(num_block); // BURN a block + + bool coding_error_after; + for (unsigned i = 0; i < 5; i++) { + efuse_hal_read(); + coding_error_after = efuse_hal_is_coding_error_in_block(num_block); + if (coding_error_after == true) { + break; + } + } + coding_error_occurred = !ignore_coding_errors && (coding_error_before != coding_error_after) && !coding_error_before; + if (coding_error_occurred) { + ESP_LOGW(TAG, "BLOCK%d got a coding error", num_block); + } + + correct_written_data = (verify_written_data) ? esp_efuse_utility_is_correct_written_data(num_block, r_data_len) : true; + if (!correct_written_data || coding_error_occurred) { + ESP_LOGW(TAG, "BLOCK%d: next retry to fix an error [%d/3]...", num_block, repeat_burn_op); + hal_memcpy((void *)EFUSE_PGM_DATA0_REG, (void *)backup_write_data, sizeof(backup_write_data)); + } + + } while ((!correct_written_data || coding_error_occurred) && repeat_burn_op++ < 3); + + if (coding_error_occurred) { + ESP_LOGW(TAG, "Coding error was not fixed"); + if (num_block == 0) { + ESP_LOGE(TAG, "BLOCK0 got a coding error, which might be critical for security"); + error = ESP_FAIL; + } + } + if (!correct_written_data) { + ESP_LOGE(TAG, "Written data are incorrect"); + error = ESP_FAIL; + } + } + } +#endif // CONFIG_EFUSE_VIRTUAL + esp_efuse_utility_reset(); + return error; +} + +// After esp_efuse_write.. functions EFUSE_BLKx_WDATAx_REG were filled is not coded values. +// This function reads EFUSE_BLKx_WDATAx_REG registers, and checks possible to write these data with RS coding scheme. +// The RS coding scheme does not require data changes for the encoded data. esp32s2 has special registers for this. +// They will be filled during the burn operation. +esp_err_t esp_efuse_utility_apply_new_coding_scheme() +{ + // start with EFUSE_BLK1. EFUSE_BLK0 - always uses EFUSE_CODING_SCHEME_NONE. + for (int num_block = EFUSE_BLK1; num_block < EFUSE_BLK_MAX; num_block++) { + if (esp_efuse_get_coding_scheme(num_block) == EFUSE_CODING_SCHEME_RS) { + for (uint32_t addr_wr_block = range_write_addr_blocks[num_block].start; addr_wr_block <= range_write_addr_blocks[num_block].end; addr_wr_block += 4) { + if (REG_READ(addr_wr_block)) { + int num_reg = 0; + for (uint32_t addr_rd_block = range_read_addr_blocks[num_block].start; addr_rd_block <= range_read_addr_blocks[num_block].end; addr_rd_block += 4, ++num_reg) { + if (esp_efuse_utility_read_reg(num_block, num_reg)) { + ESP_LOGE(TAG, "Bits are not empty. Write operation is forbidden."); + return ESP_ERR_CODING; + } + } + break; + } + } + } + } + return ESP_OK; +} diff --git a/components/efuse/esp32h21/include/esp_efuse_chip.h b/components/efuse/esp32h21/include/esp_efuse_chip.h new file mode 100644 index 00000000000..d1d2add7ea1 --- /dev/null +++ b/components/efuse/esp32h21/include/esp_efuse_chip.h @@ -0,0 +1,82 @@ +/* + * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#pragma once + +#ifdef __cplusplus +extern "C" { +#endif + +// TODO: [ESP32H21] IDF-11556, file inherit from verify code, please check + +/** + * @brief Type of eFuse blocks ESP32H21 + */ +typedef enum { + EFUSE_BLK0 = 0, /**< Number of eFuse BLOCK0. REPEAT_DATA */ + + EFUSE_BLK1 = 1, /**< Number of eFuse BLOCK1. MAC_SPI_8M_SYS */ + + EFUSE_BLK2 = 2, /**< Number of eFuse BLOCK2. SYS_DATA_PART1 */ + EFUSE_BLK_SYS_DATA_PART1 = 2, /**< Number of eFuse BLOCK2. SYS_DATA_PART1 */ + + EFUSE_BLK3 = 3, /**< Number of eFuse BLOCK3. USER_DATA*/ + EFUSE_BLK_USER_DATA = 3, /**< Number of eFuse BLOCK3. USER_DATA*/ + + EFUSE_BLK4 = 4, /**< Number of eFuse BLOCK4. KEY0 */ + EFUSE_BLK_KEY0 = 4, /**< Number of eFuse BLOCK4. KEY0 */ + + EFUSE_BLK5 = 5, /**< Number of eFuse BLOCK5. KEY1 */ + EFUSE_BLK_KEY1 = 5, /**< Number of eFuse BLOCK5. KEY1 */ + + EFUSE_BLK6 = 6, /**< Number of eFuse BLOCK6. KEY2 */ + EFUSE_BLK_KEY2 = 6, /**< Number of eFuse BLOCK6. KEY2 */ + + EFUSE_BLK7 = 7, /**< Number of eFuse BLOCK7. KEY3 */ + EFUSE_BLK_KEY3 = 7, /**< Number of eFuse BLOCK7. KEY3 */ + + EFUSE_BLK8 = 8, /**< Number of eFuse BLOCK8. KEY4 */ + EFUSE_BLK_KEY4 = 8, /**< Number of eFuse BLOCK8. KEY4 */ + + EFUSE_BLK9 = 9, /**< Number of eFuse BLOCK9. KEY5 */ + EFUSE_BLK_KEY5 = 9, /**< Number of eFuse BLOCK9. KEY5 */ + EFUSE_BLK_KEY_MAX = 10, + + EFUSE_BLK10 = 10, /**< Number of eFuse BLOCK10. SYS_DATA_PART2 */ + EFUSE_BLK_SYS_DATA_PART2 = 10, /**< Number of eFuse BLOCK10. SYS_DATA_PART2 */ + + EFUSE_BLK_MAX +} esp_efuse_block_t; + +/** + * @brief Type of coding scheme + */ +typedef enum { + EFUSE_CODING_SCHEME_NONE = 0, /**< None */ + EFUSE_CODING_SCHEME_RS = 3, /**< Reed-Solomon coding */ +} esp_efuse_coding_scheme_t; + +/** + * @brief Type of key purpose + */ +typedef enum { + ESP_EFUSE_KEY_PURPOSE_USER = 0, /**< User purposes (software-only use) */ + ESP_EFUSE_KEY_PURPOSE_ECDSA_KEY = 1, /**< ECDSA private key (Expected in little endian order)*/ + ESP_EFUSE_KEY_PURPOSE_RESERVED = 2, /**< Reserved (Used as a place holder)*/ + ESP_EFUSE_KEY_PURPOSE_XTS_AES_128_KEY = 4, /**< XTS_AES_128_KEY (flash/PSRAM encryption) */ + ESP_EFUSE_KEY_PURPOSE_HMAC_DOWN_ALL = 5, /**< HMAC Downstream mode */ + ESP_EFUSE_KEY_PURPOSE_HMAC_DOWN_JTAG = 6, /**< JTAG soft enable key (uses HMAC Downstream mode) */ + ESP_EFUSE_KEY_PURPOSE_HMAC_DOWN_DIGITAL_SIGNATURE = 7, /**< Digital Signature peripheral key (uses HMAC Downstream mode) */ + ESP_EFUSE_KEY_PURPOSE_HMAC_UP = 8, /**< HMAC Upstream mode */ + ESP_EFUSE_KEY_PURPOSE_SECURE_BOOT_DIGEST0 = 9, /**< SECURE_BOOT_DIGEST0 (Secure Boot key digest) */ + ESP_EFUSE_KEY_PURPOSE_SECURE_BOOT_DIGEST1 = 10, /**< SECURE_BOOT_DIGEST1 (Secure Boot key digest) */ + ESP_EFUSE_KEY_PURPOSE_SECURE_BOOT_DIGEST2 = 11, /**< SECURE_BOOT_DIGEST2 (Secure Boot key digest) */ + ESP_EFUSE_KEY_PURPOSE_MAX, /**< MAX PURPOSE */ +} esp_efuse_purpose_t; + +#ifdef __cplusplus +} +#endif diff --git a/components/efuse/esp32h21/include/esp_efuse_rtc_calib.h b/components/efuse/esp32h21/include/esp_efuse_rtc_calib.h new file mode 100644 index 00000000000..de7995cdf26 --- /dev/null +++ b/components/efuse/esp32h21/include/esp_efuse_rtc_calib.h @@ -0,0 +1,75 @@ +/* + * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +// TODO: [ESP32H21] IDF-11590, file inherit from verify code, please check + +//This is the ADC calibration value version burnt in efuse +#define ESP_EFUSE_ADC_CALIB_VER1 1 +#define ESP_EFUSE_ADC_CALIB_VER_MIN ESP_EFUSE_ADC_CALIB_VER1 +#define ESP_EFUSE_ADC_CALIB_VER_MAX ESP_EFUSE_ADC_CALIB_VER1 +#define VER2IDX(ver) ((ver) - 1) // Version number to index number of the array + +/** + * @brief Get the RTC calibration efuse version + * + * @return Version of the stored efuse + */ +int esp_efuse_rtc_calib_get_ver(void); + +/** + * @brief Get the init code in the efuse, for the corresponding attenuation. + * + * @param version Version of the stored efuse + * @param adc_unit ADC unit. Not used, for compatibility. On esp32h21, for calibration v1, both ADC units use the same init code (calibrated by ADC1) + * @param atten Attenuation of the init code + * @return The init code stored in efuse + */ +uint32_t esp_efuse_rtc_calib_get_init_code(int version, uint32_t adc_unit, int atten); + +/** + * @brief Get the channel specific calibration compensation + * + * @param version Version of the stored efuse + * @param adc_unit ADC unit. Not used, for compatibility. ESP32H21 only supports one ADC unit + * @param atten Attenuation of the init code + * @return The channel calibration compensation value + */ +int esp_efuse_rtc_calib_get_chan_compens(int version, uint32_t adc_unit, uint32_t adc_channel, int atten); + +/** + * @brief Get the calibration digits stored in the efuse, and the corresponding voltage. + * + * @param version Version of the stored efuse + * @param adc_unit ADC unit (not used on ESP32H21, for compatibility) + * @param atten Attenuation to use + * @param out_digi Output buffer of the digits + * @param out_vol_mv Output of the voltage, in mV + * @return + * - ESP_ERR_INVALID_ARG: If efuse version or attenuation is invalid + * - ESP_OK: if success + */ +esp_err_t esp_efuse_rtc_calib_get_cal_voltage(int version, uint32_t adc_unit, int atten, uint32_t* out_digi, uint32_t* out_vol_mv); + +/** + * @brief Get the temperature sensor calibration number delta_T stored in the efuse. + * + * @param tsens_cal Pointer of the specification of temperature sensor calibration number in efuse. + * + * @return ESP_OK if get the calibration value successfully. + * ESP_ERR_INVALID_ARG if can't get the calibration value. + */ +esp_err_t esp_efuse_rtc_calib_get_tsens_val(float* tsens_cal); + +#ifdef __cplusplus +} +#endif diff --git a/components/efuse/esp32h21/include/esp_efuse_table.h b/components/efuse/esp32h21/include/esp_efuse_table.h new file mode 100644 index 00000000000..a836d6711a7 --- /dev/null +++ b/components/efuse/esp32h21/include/esp_efuse_table.h @@ -0,0 +1,256 @@ +/* + * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifdef __cplusplus +extern "C" { +#endif + +#include "esp_efuse.h" + +// md5_digest_table bedca3b10dd5d184f2e294291996a60e +// This file was generated from the file esp_efuse_table.csv. DO NOT CHANGE THIS FILE MANUALLY. +// If you want to change some fields, you need to change esp_efuse_table.csv file +// then run `efuse_common_table` or `efuse_custom_table` command it will generate this file. +// To show efuse_table run the command 'show_efuse_table'. + + +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_RD_DIS[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_ICACHE[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_USB_JTAG[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_POWERGLITCH_EN[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_FORCE_DOWNLOAD[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SPI_DOWNLOAD_MSPI_DIS[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_TWAI[]; +#define ESP_EFUSE_WR_DIS_DIS_CAN ESP_EFUSE_WR_DIS_DIS_TWAI +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_JTAG_SEL_ENABLE[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_PAD_JTAG[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_DOWNLOAD_MANUAL_ENCRYPT[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_WDT_DELAY_SEL[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SPI_BOOT_CRYPT_CNT[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SECURE_BOOT_KEY_REVOKE0[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SECURE_BOOT_KEY_REVOKE1[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SECURE_BOOT_KEY_REVOKE2[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY_PURPOSE_0[]; +#define ESP_EFUSE_WR_DIS_KEY0_PURPOSE ESP_EFUSE_WR_DIS_KEY_PURPOSE_0 +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY_PURPOSE_1[]; +#define ESP_EFUSE_WR_DIS_KEY1_PURPOSE ESP_EFUSE_WR_DIS_KEY_PURPOSE_1 +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY_PURPOSE_2[]; +#define ESP_EFUSE_WR_DIS_KEY2_PURPOSE ESP_EFUSE_WR_DIS_KEY_PURPOSE_2 +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY_PURPOSE_3[]; +#define ESP_EFUSE_WR_DIS_KEY3_PURPOSE ESP_EFUSE_WR_DIS_KEY_PURPOSE_3 +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY_PURPOSE_4[]; +#define ESP_EFUSE_WR_DIS_KEY4_PURPOSE ESP_EFUSE_WR_DIS_KEY_PURPOSE_4 +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY_PURPOSE_5[]; +#define ESP_EFUSE_WR_DIS_KEY5_PURPOSE ESP_EFUSE_WR_DIS_KEY_PURPOSE_5 +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SEC_DPA_LEVEL[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_CRYPT_DPA_ENABLE[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SECURE_BOOT_EN[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SECURE_BOOT_AGGRESSIVE_REVOKE[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ECDSA_FORCE_USE_HARDWARE_K[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_FLASH_TPUW[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_DOWNLOAD_MODE[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_DIRECT_BOOT[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_USB_SERIAL_JTAG_ROM_PRINT[]; +#define ESP_EFUSE_WR_DIS_DIS_USB_PRINT ESP_EFUSE_WR_DIS_DIS_USB_SERIAL_JTAG_ROM_PRINT +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ENABLE_SECURITY_DOWNLOAD[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_UART_PRINT_CONTROL[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_FORCE_SEND_RESUME[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SECURE_VERSION[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SECURE_BOOT_DISABLE_FAST_WAKE[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_HYS_EN_PAD0[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_HYS_EN_PAD1[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLK1[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_MAC[]; +#define ESP_EFUSE_WR_DIS_MAC_FACTORY ESP_EFUSE_WR_DIS_MAC +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_MAC_EXT[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_RXIQ_VERSION[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_RXIQ_0[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_RXIQ_1[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ACTIVE_HP_DBIAS[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ACTIVE_LP_DBIAS[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DSLP_DBIAS[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DBIAS_VOL_GAP[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_WAFER_VERSION_MINOR[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_WAFER_VERSION_MAJOR[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DISABLE_WAFER_VERSION_MAJOR[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_FLASH_CAP[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_FLASH_TEMP[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_FLASH_VENDOR[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_PKG_VERSION[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SYS_DATA_PART1[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_OPTIONAL_UNIQUE_ID[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLK_VERSION_MINOR[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLK_VERSION_MAJOR[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DISABLE_BLK_VERSION_MAJOR[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_TEMP_CALIB[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_AVE_INITCODE_ATTEN0[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_AVE_INITCODE_ATTEN1[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_AVE_INITCODE_ATTEN2[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_AVE_INITCODE_ATTEN3[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_HI_DOUT_ATTEN0[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_HI_DOUT_ATTEN1[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_HI_DOUT_ATTEN2[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_HI_DOUT_ATTEN3[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_CH0_ATTEN0_INITCODE_DIFF[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_CH1_ATTEN0_INITCODE_DIFF[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_CH2_ATTEN0_INITCODE_DIFF[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_CH3_ATTEN0_INITCODE_DIFF[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_CH4_ATTEN0_INITCODE_DIFF[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLOCK_USR_DATA[]; +#define ESP_EFUSE_WR_DIS_USER_DATA ESP_EFUSE_WR_DIS_BLOCK_USR_DATA +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_CUSTOM_MAC[]; +#define ESP_EFUSE_WR_DIS_MAC_CUSTOM ESP_EFUSE_WR_DIS_CUSTOM_MAC +#define ESP_EFUSE_WR_DIS_USER_DATA_MAC_CUSTOM ESP_EFUSE_WR_DIS_CUSTOM_MAC +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLOCK_KEY0[]; +#define ESP_EFUSE_WR_DIS_KEY0 ESP_EFUSE_WR_DIS_BLOCK_KEY0 +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLOCK_KEY1[]; +#define ESP_EFUSE_WR_DIS_KEY1 ESP_EFUSE_WR_DIS_BLOCK_KEY1 +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLOCK_KEY2[]; +#define ESP_EFUSE_WR_DIS_KEY2 ESP_EFUSE_WR_DIS_BLOCK_KEY2 +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLOCK_KEY3[]; +#define ESP_EFUSE_WR_DIS_KEY3 ESP_EFUSE_WR_DIS_BLOCK_KEY3 +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLOCK_KEY4[]; +#define ESP_EFUSE_WR_DIS_KEY4 ESP_EFUSE_WR_DIS_BLOCK_KEY4 +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLOCK_KEY5[]; +#define ESP_EFUSE_WR_DIS_KEY5 ESP_EFUSE_WR_DIS_BLOCK_KEY5 +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLOCK_SYS_DATA2[]; +#define ESP_EFUSE_WR_DIS_SYS_DATA_PART2 ESP_EFUSE_WR_DIS_BLOCK_SYS_DATA2 +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_USB_EXCHG_PINS[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_VDD_SPI_AS_GPIO[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SOFT_DIS_JTAG[]; +extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS[]; +extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_BLOCK_KEY0[]; +#define ESP_EFUSE_RD_DIS_KEY0 ESP_EFUSE_RD_DIS_BLOCK_KEY0 +extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_BLOCK_KEY1[]; +#define ESP_EFUSE_RD_DIS_KEY1 ESP_EFUSE_RD_DIS_BLOCK_KEY1 +extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_BLOCK_KEY2[]; +#define ESP_EFUSE_RD_DIS_KEY2 ESP_EFUSE_RD_DIS_BLOCK_KEY2 +extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_BLOCK_KEY3[]; +#define ESP_EFUSE_RD_DIS_KEY3 ESP_EFUSE_RD_DIS_BLOCK_KEY3 +extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_BLOCK_KEY4[]; +#define ESP_EFUSE_RD_DIS_KEY4 ESP_EFUSE_RD_DIS_BLOCK_KEY4 +extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_BLOCK_KEY5[]; +#define ESP_EFUSE_RD_DIS_KEY5 ESP_EFUSE_RD_DIS_BLOCK_KEY5 +extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_BLOCK_SYS_DATA2[]; +#define ESP_EFUSE_RD_DIS_SYS_DATA_PART2 ESP_EFUSE_RD_DIS_BLOCK_SYS_DATA2 +extern const esp_efuse_desc_t* ESP_EFUSE_PVT_GLITCH_EN[]; +extern const esp_efuse_desc_t* ESP_EFUSE_DIS_ICACHE[]; +extern const esp_efuse_desc_t* ESP_EFUSE_DIS_USB_JTAG[]; +extern const esp_efuse_desc_t* ESP_EFUSE_POWERGLITCH_EN[]; +extern const esp_efuse_desc_t* ESP_EFUSE_DIS_USJ[]; +extern const esp_efuse_desc_t* ESP_EFUSE_DIS_FORCE_DOWNLOAD[]; +extern const esp_efuse_desc_t* ESP_EFUSE_SPI_DOWNLOAD_MSPI_DIS[]; +extern const esp_efuse_desc_t* ESP_EFUSE_DIS_TWAI[]; +#define ESP_EFUSE_DIS_CAN ESP_EFUSE_DIS_TWAI +extern const esp_efuse_desc_t* ESP_EFUSE_JTAG_SEL_ENABLE[]; +extern const esp_efuse_desc_t* ESP_EFUSE_SOFT_DIS_JTAG[]; +extern const esp_efuse_desc_t* ESP_EFUSE_DIS_PAD_JTAG[]; +extern const esp_efuse_desc_t* ESP_EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT[]; +extern const esp_efuse_desc_t* ESP_EFUSE_USB_DREFH[]; +extern const esp_efuse_desc_t* ESP_EFUSE_USB_DREFL[]; +extern const esp_efuse_desc_t* ESP_EFUSE_USB_EXCHG_PINS[]; +extern const esp_efuse_desc_t* ESP_EFUSE_VDD_SPI_AS_GPIO[]; +extern const esp_efuse_desc_t* ESP_EFUSE_ECDSA_CURVE_MODE[]; +extern const esp_efuse_desc_t* ESP_EFUSE_ECC_FORCE_CONST_TIME[]; +extern const esp_efuse_desc_t* ESP_EFUSE_XTS_DPA_PSEUDO_LEVEL[]; +extern const esp_efuse_desc_t* ESP_EFUSE_IO_LDO_ADJUST[]; +extern const esp_efuse_desc_t* ESP_EFUSE_VDD_SPI_LDO_ADJUST[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WDT_DELAY_SEL[]; +extern const esp_efuse_desc_t* ESP_EFUSE_SPI_BOOT_CRYPT_CNT[]; +extern const esp_efuse_desc_t* ESP_EFUSE_SECURE_BOOT_KEY_REVOKE0[]; +extern const esp_efuse_desc_t* ESP_EFUSE_SECURE_BOOT_KEY_REVOKE1[]; +extern const esp_efuse_desc_t* ESP_EFUSE_SECURE_BOOT_KEY_REVOKE2[]; +extern const esp_efuse_desc_t* ESP_EFUSE_KEY_PURPOSE_0[]; +#define ESP_EFUSE_KEY0_PURPOSE ESP_EFUSE_KEY_PURPOSE_0 +extern const esp_efuse_desc_t* ESP_EFUSE_KEY_PURPOSE_1[]; +#define ESP_EFUSE_KEY1_PURPOSE ESP_EFUSE_KEY_PURPOSE_1 +extern const esp_efuse_desc_t* ESP_EFUSE_KEY_PURPOSE_2[]; +#define ESP_EFUSE_KEY2_PURPOSE ESP_EFUSE_KEY_PURPOSE_2 +extern const esp_efuse_desc_t* ESP_EFUSE_KEY_PURPOSE_3[]; +#define ESP_EFUSE_KEY3_PURPOSE ESP_EFUSE_KEY_PURPOSE_3 +extern const esp_efuse_desc_t* ESP_EFUSE_KEY_PURPOSE_4[]; +#define ESP_EFUSE_KEY4_PURPOSE ESP_EFUSE_KEY_PURPOSE_4 +extern const esp_efuse_desc_t* ESP_EFUSE_KEY_PURPOSE_5[]; +#define ESP_EFUSE_KEY5_PURPOSE ESP_EFUSE_KEY_PURPOSE_5 +extern const esp_efuse_desc_t* ESP_EFUSE_SEC_DPA_LEVEL[]; +extern const esp_efuse_desc_t* ESP_EFUSE_IO_LDO_1P8[]; +extern const esp_efuse_desc_t* ESP_EFUSE_CRYPT_DPA_ENABLE[]; +extern const esp_efuse_desc_t* ESP_EFUSE_SECURE_BOOT_EN[]; +extern const esp_efuse_desc_t* ESP_EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE[]; +extern const esp_efuse_desc_t* ESP_EFUSE_POWERGLITCH_EN1[]; +extern const esp_efuse_desc_t* ESP_EFUSE_FLASH_TPUW[]; +extern const esp_efuse_desc_t* ESP_EFUSE_DIS_DOWNLOAD_MODE[]; +extern const esp_efuse_desc_t* ESP_EFUSE_DIS_DIRECT_BOOT[]; +extern const esp_efuse_desc_t* ESP_EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT[]; +#define ESP_EFUSE_DIS_USB_PRINT ESP_EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT +extern const esp_efuse_desc_t* ESP_EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE[]; +extern const esp_efuse_desc_t* ESP_EFUSE_ENABLE_SECURITY_DOWNLOAD[]; +extern const esp_efuse_desc_t* ESP_EFUSE_UART_PRINT_CONTROL[]; +extern const esp_efuse_desc_t* ESP_EFUSE_FORCE_SEND_RESUME[]; +extern const esp_efuse_desc_t* ESP_EFUSE_SECURE_VERSION[]; +extern const esp_efuse_desc_t* ESP_EFUSE_SECURE_BOOT_DISABLE_FAST_WAKE[]; +extern const esp_efuse_desc_t* ESP_EFUSE_HYS_EN_PAD0[]; +extern const esp_efuse_desc_t* ESP_EFUSE_HYS_EN_PAD1[]; +extern const esp_efuse_desc_t* ESP_EFUSE_MAC[]; +#define ESP_EFUSE_MAC_FACTORY ESP_EFUSE_MAC +extern const esp_efuse_desc_t* ESP_EFUSE_MAC_EXT[]; +extern const esp_efuse_desc_t* ESP_EFUSE_RXIQ_VERSION[]; +extern const esp_efuse_desc_t* ESP_EFUSE_RXIQ_0[]; +extern const esp_efuse_desc_t* ESP_EFUSE_RXIQ_1[]; +extern const esp_efuse_desc_t* ESP_EFUSE_ACTIVE_HP_DBIAS[]; +extern const esp_efuse_desc_t* ESP_EFUSE_ACTIVE_LP_DBIAS[]; +extern const esp_efuse_desc_t* ESP_EFUSE_DSLP_DBIAS[]; +extern const esp_efuse_desc_t* ESP_EFUSE_DBIAS_VOL_GAP[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WAFER_VERSION_MINOR[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WAFER_VERSION_MAJOR[]; +extern const esp_efuse_desc_t* ESP_EFUSE_DISABLE_WAFER_VERSION_MAJOR[]; +extern const esp_efuse_desc_t* ESP_EFUSE_FLASH_CAP[]; +extern const esp_efuse_desc_t* ESP_EFUSE_FLASH_TEMP[]; +extern const esp_efuse_desc_t* ESP_EFUSE_FLASH_VENDOR[]; +extern const esp_efuse_desc_t* ESP_EFUSE_PKG_VERSION[]; +extern const esp_efuse_desc_t* ESP_EFUSE_OPTIONAL_UNIQUE_ID[]; +extern const esp_efuse_desc_t* ESP_EFUSE_BLK_VERSION_MINOR[]; +extern const esp_efuse_desc_t* ESP_EFUSE_BLK_VERSION_MAJOR[]; +extern const esp_efuse_desc_t* ESP_EFUSE_DISABLE_BLK_VERSION_MAJOR[]; +extern const esp_efuse_desc_t* ESP_EFUSE_TEMP_CALIB[]; +extern const esp_efuse_desc_t* ESP_EFUSE_ADC1_AVE_INITCODE_ATTEN0[]; +extern const esp_efuse_desc_t* ESP_EFUSE_ADC1_AVE_INITCODE_ATTEN1[]; +extern const esp_efuse_desc_t* ESP_EFUSE_ADC1_AVE_INITCODE_ATTEN2[]; +extern const esp_efuse_desc_t* ESP_EFUSE_ADC1_AVE_INITCODE_ATTEN3[]; +extern const esp_efuse_desc_t* ESP_EFUSE_ADC1_HI_DOUT_ATTEN0[]; +extern const esp_efuse_desc_t* ESP_EFUSE_ADC1_HI_DOUT_ATTEN1[]; +extern const esp_efuse_desc_t* ESP_EFUSE_ADC1_HI_DOUT_ATTEN2[]; +extern const esp_efuse_desc_t* ESP_EFUSE_ADC1_HI_DOUT_ATTEN3[]; +extern const esp_efuse_desc_t* ESP_EFUSE_ADC1_CH0_ATTEN0_INITCODE_DIFF[]; +extern const esp_efuse_desc_t* ESP_EFUSE_ADC1_CH1_ATTEN0_INITCODE_DIFF[]; +extern const esp_efuse_desc_t* ESP_EFUSE_ADC1_CH2_ATTEN0_INITCODE_DIFF[]; +extern const esp_efuse_desc_t* ESP_EFUSE_ADC1_CH3_ATTEN0_INITCODE_DIFF[]; +extern const esp_efuse_desc_t* ESP_EFUSE_ADC1_CH4_ATTEN0_INITCODE_DIFF[]; +extern const esp_efuse_desc_t* ESP_EFUSE_USER_DATA[]; +#define ESP_EFUSE_BLOCK_USR_DATA ESP_EFUSE_USER_DATA +extern const esp_efuse_desc_t* ESP_EFUSE_USER_DATA_MAC_CUSTOM[]; +#define ESP_EFUSE_MAC_CUSTOM ESP_EFUSE_USER_DATA_MAC_CUSTOM +#define ESP_EFUSE_CUSTOM_MAC ESP_EFUSE_USER_DATA_MAC_CUSTOM +extern const esp_efuse_desc_t* ESP_EFUSE_KEY0[]; +#define ESP_EFUSE_BLOCK_KEY0 ESP_EFUSE_KEY0 +extern const esp_efuse_desc_t* ESP_EFUSE_KEY1[]; +#define ESP_EFUSE_BLOCK_KEY1 ESP_EFUSE_KEY1 +extern const esp_efuse_desc_t* ESP_EFUSE_KEY2[]; +#define ESP_EFUSE_BLOCK_KEY2 ESP_EFUSE_KEY2 +extern const esp_efuse_desc_t* ESP_EFUSE_KEY3[]; +#define ESP_EFUSE_BLOCK_KEY3 ESP_EFUSE_KEY3 +extern const esp_efuse_desc_t* ESP_EFUSE_KEY4[]; +#define ESP_EFUSE_BLOCK_KEY4 ESP_EFUSE_KEY4 +extern const esp_efuse_desc_t* ESP_EFUSE_KEY5[]; +#define ESP_EFUSE_BLOCK_KEY5 ESP_EFUSE_KEY5 +extern const esp_efuse_desc_t* ESP_EFUSE_SYS_DATA_PART2[]; +#define ESP_EFUSE_BLOCK_SYS_DATA2 ESP_EFUSE_SYS_DATA_PART2 + +#ifdef __cplusplus +} +#endif diff --git a/components/efuse/esp32h21/private_include/esp_efuse_utility.h b/components/efuse/esp32h21/private_include/esp_efuse_utility.h new file mode 100644 index 00000000000..9752e679df9 --- /dev/null +++ b/components/efuse/esp32h21/private_include/esp_efuse_utility.h @@ -0,0 +1,21 @@ +/* + * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#pragma once + +#ifdef __cplusplus +extern "C" { +#endif + +#define COUNT_EFUSE_REG_PER_BLOCK 8 /* The number of registers per block. */ + +#define ESP_EFUSE_SECURE_VERSION_NUM_BLOCK EFUSE_BLK0 + +#define ESP_EFUSE_FIELD_CORRESPONDS_CODING_SCHEME(scheme, max_num_bit) + +#ifdef __cplusplus +} +#endif diff --git a/components/efuse/esp32h21/sources.cmake b/components/efuse/esp32h21/sources.cmake new file mode 100644 index 00000000000..9dffd72008d --- /dev/null +++ b/components/efuse/esp32h21/sources.cmake @@ -0,0 +1,4 @@ +set(EFUSE_SOC_SRCS "esp_efuse_table.c" + "esp_efuse_fields.c" + "esp_efuse_rtc_calib.c" + "esp_efuse_utility.c") From 11760387761c5b54900c2e3544e852ffb1f7e647 Mon Sep 17 00:00:00 2001 From: gaoxu Date: Tue, 17 Dec 2024 17:10:02 +0800 Subject: [PATCH 096/118] feat(esp32h21): add H21 esp_rom files (stage3) --- .../esp32h2/include/esp32h2/rom/gpio.h | 2 +- .../esp_rom/esp32h21/Kconfig.soc_caps.in | 88 +++ components/esp_rom/esp32h21/esp_rom_caps.h | 29 + .../esp32h21/include/esp32h21/rom/.gitkeep | 0 .../esp32h21/include/esp32h21/rom/cache.h | 610 ++++++++++++++++++ .../esp32h21/include/esp32h21/rom/ecdsa.h | 28 + .../esp32h21/include/esp32h21/rom/efuse.h | 283 ++++++++ .../esp32h21/include/esp32h21/rom/esp_flash.h | 46 ++ .../esp32h21/include/esp32h21/rom/ets_sys.h | 428 ++++++++++++ .../esp32h21/include/esp32h21/rom/gpio.h | 212 ++++++ .../esp32h21/include/esp32h21/rom/hmac.h | 54 ++ .../include/esp32h21/rom/libc_stubs.h | 94 +++ .../include/esp32h21/rom/rom_layout.h | 97 +++ .../esp32h21/include/esp32h21/rom/rsa_pss.h | 37 ++ .../esp32h21/include/esp32h21/rom/rtc.h | 249 +++++++ .../include/esp32h21/rom/secure_boot.h | 135 ++++ .../esp32h21/include/esp32h21/rom/sha.h | 52 ++ .../esp32h21/include/esp32h21/rom/spi_flash.h | 460 +++++++++++++ .../esp32h21/include/esp32h21/rom/uart.h | 349 ++++++++++ .../esp_rom/esp32h21/ld/esp32h21.rom.api.ld | 63 ++ .../esp_rom/esp32h21/ld/esp32h21.rom.heap.ld | 79 +++ .../esp_rom/esp32h21/ld/esp32h21.rom.ld | 381 +++++++++++ .../esp32h21/ld/esp32h21.rom.libgcc.ld | 112 ++++ .../esp32h21/ld/esp32h21.rom.newlib-nano.ld | 32 + .../esp32h21/ld/esp32h21.rom.newlib.ld | 99 +++ .../esp32h21/ld/esp32h21.rom.spiflash.ld | 166 +++++ .../esp32h21/ld/esp32h21.rom.systimer.ld | 27 + .../esp32h21/ld/esp32h21.rom.version.ld | 15 + .../esp_rom/esp32h21/ld/esp32h21.rom.wdt.ld | 27 + .../esp_rom/include/esp_rom_libc_stubs.h | 2 + components/esp_rom/patches/esp_rom_systimer.c | 2 +- 31 files changed, 4256 insertions(+), 2 deletions(-) create mode 100644 components/esp_rom/esp32h21/Kconfig.soc_caps.in create mode 100644 components/esp_rom/esp32h21/esp_rom_caps.h delete mode 100644 components/esp_rom/esp32h21/include/esp32h21/rom/.gitkeep create mode 100644 components/esp_rom/esp32h21/include/esp32h21/rom/cache.h create mode 100644 components/esp_rom/esp32h21/include/esp32h21/rom/ecdsa.h create mode 100644 components/esp_rom/esp32h21/include/esp32h21/rom/efuse.h create mode 100644 components/esp_rom/esp32h21/include/esp32h21/rom/esp_flash.h create mode 100644 components/esp_rom/esp32h21/include/esp32h21/rom/ets_sys.h create mode 100644 components/esp_rom/esp32h21/include/esp32h21/rom/gpio.h create mode 100644 components/esp_rom/esp32h21/include/esp32h21/rom/hmac.h create mode 100644 components/esp_rom/esp32h21/include/esp32h21/rom/libc_stubs.h create mode 100644 components/esp_rom/esp32h21/include/esp32h21/rom/rom_layout.h create mode 100644 components/esp_rom/esp32h21/include/esp32h21/rom/rsa_pss.h create mode 100644 components/esp_rom/esp32h21/include/esp32h21/rom/rtc.h create mode 100644 components/esp_rom/esp32h21/include/esp32h21/rom/secure_boot.h create mode 100644 components/esp_rom/esp32h21/include/esp32h21/rom/sha.h create mode 100644 components/esp_rom/esp32h21/include/esp32h21/rom/spi_flash.h create mode 100644 components/esp_rom/esp32h21/include/esp32h21/rom/uart.h create mode 100644 components/esp_rom/esp32h21/ld/esp32h21.rom.api.ld create mode 100644 components/esp_rom/esp32h21/ld/esp32h21.rom.heap.ld create mode 100644 components/esp_rom/esp32h21/ld/esp32h21.rom.ld create mode 100644 components/esp_rom/esp32h21/ld/esp32h21.rom.libgcc.ld create mode 100644 components/esp_rom/esp32h21/ld/esp32h21.rom.newlib-nano.ld create mode 100644 components/esp_rom/esp32h21/ld/esp32h21.rom.newlib.ld create mode 100644 components/esp_rom/esp32h21/ld/esp32h21.rom.spiflash.ld create mode 100644 components/esp_rom/esp32h21/ld/esp32h21.rom.systimer.ld create mode 100644 components/esp_rom/esp32h21/ld/esp32h21.rom.version.ld create mode 100644 components/esp_rom/esp32h21/ld/esp32h21.rom.wdt.ld diff --git a/components/esp_rom/esp32h2/include/esp32h2/rom/gpio.h b/components/esp_rom/esp32h2/include/esp32h2/rom/gpio.h index 5829765c607..acd5bac6ca3 100644 --- a/components/esp_rom/esp32h2/include/esp32h2/rom/gpio.h +++ b/components/esp_rom/esp32h2/include/esp32h2/rom/gpio.h @@ -84,7 +84,7 @@ uint32_t gpio_input_get(void); */ void gpio_pin_wakeup_enable(uint32_t i, GPIO_INT_TYPE intr_state); -/** +/**c * @brief disable GPIOs to wakeup the ESP32. * Please do not call this function in SDK. * diff --git a/components/esp_rom/esp32h21/Kconfig.soc_caps.in b/components/esp_rom/esp32h21/Kconfig.soc_caps.in new file mode 100644 index 00000000000..bd28ce6cab1 --- /dev/null +++ b/components/esp_rom/esp32h21/Kconfig.soc_caps.in @@ -0,0 +1,88 @@ +##################################################### +# This file is auto-generated from SoC caps +# using gen_soc_caps_kconfig.py, do not edit manually +##################################################### + +config ESP_ROM_HAS_CRC_LE + bool + default y + +config ESP_ROM_HAS_CRC_BE + bool + default y + +config ESP_ROM_UART_CLK_IS_XTAL + bool + default y + +config ESP_ROM_USB_SERIAL_DEVICE_NUM + int + default 3 + +config ESP_ROM_HAS_RETARGETABLE_LOCKING + bool + default y + +config ESP_ROM_GET_CLK_FREQ + bool + default y + +config ESP_ROM_HAS_HAL_WDT + bool + default y + +config ESP_ROM_HAS_HAL_SYSTIMER + bool + default y + +config ESP_ROM_HAS_HEAP_TLSF + bool + default y + +config ESP_ROM_HAS_LAYOUT_TABLE + bool + default y + +config ESP_ROM_HAS_SPI_FLASH + bool + default y + +config ESP_ROM_WITHOUT_REGI2C + bool + default y + +config ESP_ROM_HAS_NEWLIB + bool + default y + +config ESP_ROM_HAS_NEWLIB_NANO_FORMAT + bool + default y + +config ESP_ROM_WDT_INIT_PATCH + bool + default y + +config ESP_ROM_RAM_APP_NEEDS_MMU_INIT + bool + default y + +config ESP_ROM_HAS_SW_FLOAT + bool + default y + +config ESP_ROM_USB_OTG_NUM + int + default -1 + +config ESP_ROM_HAS_VERSION + bool + default y + +config ESP_ROM_SUPPORT_DEEP_SLEEP_WAKEUP_STUB + bool + default y + +config ESP_ROM_HAS_OUTPUT_PUTC_FUNC + bool + default y diff --git a/components/esp_rom/esp32h21/esp_rom_caps.h b/components/esp_rom/esp32h21/esp_rom_caps.h new file mode 100644 index 00000000000..936d777b1ff --- /dev/null +++ b/components/esp_rom/esp32h21/esp_rom_caps.h @@ -0,0 +1,29 @@ +/* + * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#pragma once + +#define ESP_ROM_HAS_CRC_LE (1) // ROM CRC library supports Little Endian +#define ESP_ROM_HAS_CRC_BE (1) // ROM CRC library supports Big Endian +#define ESP_ROM_UART_CLK_IS_XTAL (1) // UART clock source is selected to XTAL in ROM +#define ESP_ROM_USB_SERIAL_DEVICE_NUM (3) // UART uses USB_SERIAL_JTAG port in ROM. +#define ESP_ROM_HAS_RETARGETABLE_LOCKING (1) // ROM was built with retargetable locking +#define ESP_ROM_GET_CLK_FREQ (1) // Get clk frequency with rom function `ets_get_cpu_frequency` +#define ESP_ROM_HAS_HAL_WDT (1) // ROM has the implementation of Watchdog HAL driver +#define ESP_ROM_HAS_HAL_SYSTIMER (1) // ROM has the implementation of Systimer HAL driver +#define ESP_ROM_HAS_HEAP_TLSF (1) // ROM has the implementation of the tlsf and multi-heap library +#define ESP_ROM_HAS_LAYOUT_TABLE (1) // ROM has the layout table +#define ESP_ROM_HAS_SPI_FLASH (1) // ROM has the implementation of SPI Flash driver +#define ESP_ROM_WITHOUT_REGI2C (1) // ROM has no regi2c APIs +#define ESP_ROM_HAS_NEWLIB (1) // ROM has newlib (at least parts of it) functions included +#define ESP_ROM_HAS_NEWLIB_NANO_FORMAT (1) // ROM has the newlib nano versions of formatting functions +#define ESP_ROM_WDT_INIT_PATCH (1) // ROM version does not configure the clock +#define ESP_ROM_RAM_APP_NEEDS_MMU_INIT (1) // ROM doesn't init cache MMU when it's a RAM APP, needs MMU hal to init +#define ESP_ROM_HAS_SW_FLOAT (1) // ROM has libgcc software floating point emulation functions +#define ESP_ROM_USB_OTG_NUM (-1) // No USB_OTG CDC in the ROM, set -1 for Kconfig usage. +#define ESP_ROM_HAS_VERSION (1) // ROM has version/eco information +#define ESP_ROM_SUPPORT_DEEP_SLEEP_WAKEUP_STUB (1) // ROM supports the HP core to jump to the RTC memory to execute stub code after waking up from deepsleep. +#define ESP_ROM_HAS_OUTPUT_PUTC_FUNC (1) // ROM has esp_rom_output_putc (or ets_write_char_uart) diff --git a/components/esp_rom/esp32h21/include/esp32h21/rom/.gitkeep b/components/esp_rom/esp32h21/include/esp32h21/rom/.gitkeep deleted file mode 100644 index e69de29bb2d..00000000000 diff --git a/components/esp_rom/esp32h21/include/esp32h21/rom/cache.h b/components/esp_rom/esp32h21/include/esp32h21/rom/cache.h new file mode 100644 index 00000000000..eafc044bc49 --- /dev/null +++ b/components/esp_rom/esp32h21/include/esp32h21/rom/cache.h @@ -0,0 +1,610 @@ +/* + * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#pragma once + +#include +#include "esp_bit_defs.h" + +#ifdef __cplusplus +extern "C" { +#endif + +//TODO: [ESP32H21] IDF-11525 + +/** \defgroup cache_apis, cache operation related apis + * @brief cache apis + */ + +/** @addtogroup cache_apis + * @{ + */ +#define MIN_ICACHE_SIZE 16384 +#define MAX_ICACHE_SIZE 16384 +#define MIN_ICACHE_WAYS 2 +#define MAX_ICACHE_WAYS 2 +#define MAX_CACHE_WAYS 2 +#define MIN_CACHE_LINE_SIZE 32 +#define TAG_SIZE 4 +#define MIN_ICACHE_BANK_NUM 1 +#define MAX_ICACHE_BANK_NUM 1 +#define CACHE_MEMORY_BANK_NUM 1 +#define CACHE_MEMORY_IBANK_SIZE 0x4000 + +#define MAX_ITAG_BANK_ITEMS (MAX_ICACHE_SIZE / MAX_ICACHE_BANK_NUM / MIN_CACHE_LINE_SIZE) +#define MAX_ITAG_BLOCK_ITEMS (MAX_ICACHE_SIZE / MAX_ICACHE_BANK_NUM / MAX_ICACHE_WAYS / MIN_CACHE_LINE_SIZE) +#define MAX_ITAG_BANK_SIZE (MAX_ITAG_BANK_ITEMS * TAG_SIZE) +#define MAX_ITAG_BLOCK_SIZE (MAX_ITAG_BLOCK_ITEMS * TAG_SIZE) + +typedef enum { + CACHE_SIZE_HALF = 0, /*!< 8KB for icache and dcache */ + CACHE_SIZE_FULL = 1, /*!< 16KB for icache and dcache */ +} cache_size_t; + +typedef enum { + CACHE_4WAYS_ASSOC = 0, /*!< 4 way associated cache */ + CACHE_8WAYS_ASSOC = 1, /*!< 8 way associated cache */ +} cache_ways_t; + +typedef enum { + CACHE_LINE_SIZE_16B = 0, /*!< 16 Byte cache line size */ + CACHE_LINE_SIZE_32B = 1, /*!< 32 Byte cache line size */ + CACHE_LINE_SIZE_64B = 2, /*!< 64 Byte cache line size */ +} cache_line_size_t; + +typedef enum { + CACHE_AUTOLOAD_POSITIVE = 0, /*!< cache autoload step is positive */ + CACHE_AUTOLOAD_NEGATIVE = 1, /*!< cache autoload step is negative */ +} cache_autoload_order_t; + +#define CACHE_AUTOLOAD_STEP(i) ((i) - 1) + +typedef enum { + CACHE_AUTOLOAD_MISS_TRIGGER = 0, /*!< autoload only triggered by cache miss */ + CACHE_AUTOLOAD_HIT_TRIGGER = 1, /*!< autoload only triggered by cache hit */ + CACHE_AUTOLOAD_BOTH_TRIGGER = 2, /*!< autoload triggered both by cache miss and hit */ +} cache_autoload_trigger_t; + +typedef enum { + CACHE_FREEZE_ACK_BUSY = 0, /*!< in this mode, cache ack busy to CPU if a cache miss happens*/ + CACHE_FREEZE_ACK_ERROR = 1, /*!< in this mode, cache ack wrong data to CPU and trigger an error if a cache miss happens */ +} cache_freeze_mode_t; + +typedef enum { + MMU_PAGE_MODE_64KB = 0, + MMU_PAGE_MODE_32KB = 1, + MMU_PAGE_MODE_16KB = 2, + MMU_PAGE_MODE_8KB = 3, + MMU_PAGE_MODE_INVALID, +} mmu_page_mode_t; + +struct cache_mode { + uint32_t cache_size; /*!< cache size in byte */ + uint16_t cache_line_size; /*!< cache line size in byte */ + uint8_t cache_ways; /*!< cache ways, always 4 */ + uint8_t ibus; /*!< the cache index, 0 for dcache, 1 for icache */ +}; + +struct icache_tag_item { + uint32_t valid:1; /*!< the tag item is valid or not */ + uint32_t lock:1; /*!< the cache line is locked or not */ + uint32_t fifo_cnt:3; /*!< fifo cnt, 0 ~ 3 for 4 ways cache */ + uint32_t tag:13; /*!< the tag is the high part of the cache address, however is only 16MB (8MB Ibus + 8MB Dbus) range, and without low part */ + uint32_t reserved:14; +}; + +struct autoload_config { + uint8_t order; /*!< autoload step is positive or negative */ + uint8_t trigger; /*!< autoload trigger */ + uint8_t ena0; /*!< autoload region0 enable */ + uint8_t ena1; /*!< autoload region1 enable */ + uint32_t addr0; /*!< autoload region0 start address */ + uint32_t size0; /*!< autoload region0 size */ + uint32_t addr1; /*!< autoload region1 start address */ + uint32_t size1; /*!< autoload region1 size */ +}; + +struct tag_group_info { + struct cache_mode mode; /*!< cache and cache mode */ + uint32_t filter_addr; /*!< the address that used to generate the struct */ + uint32_t vaddr_offset; /*!< virtual address offset of the cache ways */ + uint32_t tag_addr[MAX_CACHE_WAYS]; /*!< tag memory address, only [0~mode.ways-1] is valid to use */ + uint32_t cache_memory_offset[MAX_CACHE_WAYS]; /*!< cache memory address, only [0~mode.ways-1] is valid to use */ +}; + +struct lock_config { + uint32_t addr; /*!< manual lock address*/ + uint16_t size; /*!< manual lock size*/ + uint16_t group; /*!< manual lock group, 0 or 1*/ +}; + +struct cache_internal_stub_table { + uint32_t (* icache_line_size)(void); + uint32_t (* icache_addr)(uint32_t addr); + uint32_t (* dcache_addr)(uint32_t addr); + void (* invalidate_icache_items)(uint32_t addr, uint32_t items); + void (* lock_icache_items)(uint32_t addr, uint32_t items); + void (* unlock_icache_items)(uint32_t addr, uint32_t items); + uint32_t (* suspend_icache_autoload)(void); + void (* resume_icache_autoload)(uint32_t autoload); + void (* freeze_icache_enable)(cache_freeze_mode_t mode); + void (* freeze_icache_disable)(void); + int (* op_addr)(uint32_t start_addr, uint32_t size, uint32_t cache_line_size, uint32_t max_sync_num, void(* cache_Iop)(uint32_t, uint32_t)); +}; + +/* Defined in the interface file, default value is rom_default_cache_internal_table */ +extern const struct cache_internal_stub_table* rom_cache_internal_table_ptr; + +typedef void (* cache_op_start)(void); +typedef void (* cache_op_end)(void); + +typedef struct { + cache_op_start start; + cache_op_end end; +} cache_op_cb_t; + +/* Defined in the interface file, default value is NULL */ +extern const cache_op_cb_t* rom_cache_op_cb; + +#define ESP_ROM_ERR_INVALID_ARG 1 +#define MMU_SET_ADDR_ALIGNED_ERROR 2 +#define MMU_SET_PASE_SIZE_ERROR 3 +#define MMU_SET_VADDR_OUT_RANGE 4 + +#define CACHE_OP_ICACHE_Y 1 +#define CACHE_OP_ICACHE_N 0 + +/** + * @brief Initialise cache mmu, mark all entries as invalid. + * Please do not call this function in your SDK application. + * + * @param None + * + * @return None + */ +void Cache_MMU_Init(void); + +/** + * @brief Init Cache for ROM boot, including resetting the Icache, initializing MMU, Enabling ICache, unmasking bus. + * + * @param None + * + * @return None + */ +void ROM_Boot_Cache_Init(void); + +/** + * @brief Set ICache mmu mapping. + * Please do not call this function in your SDK application. + * + * @param uint32_t senitive : Config this page should apply flash encryption or not + * + * @param uint32_t ext_ram : DPORT_MMU_ACCESS_FLASH for flash, DPORT_MMU_INVALID for invalid. In + * esp32h21, external memory is always flash + * + * @param uint32_t vaddr : virtual address in CPU address space. + * Can be Iram0,Iram1,Irom0,Drom0 and AHB buses address. + * Should be aligned by psize. + * + * @param uint32_t paddr : physical address in external memory. + * Should be aligned by psize. + * + * @param uint32_t psize : page size of ICache, in kilobytes. Should be 64 here. + * + * @param uint32_t num : pages to be set. + * + * @param uint32_t fixed : 0 for physical pages grow with virtual pages, other for virtual pages map to same physical page. + * + * @return uint32_t: error status + * 0 : mmu set success + * 2 : vaddr or paddr is not aligned + * 3 : psize error + * 4 : vaddr is out of range + */ +int Cache_MSPI_MMU_Set(uint32_t sensitive, uint32_t ext_ram, uint32_t vaddr, uint32_t paddr, uint32_t psize, uint32_t num, uint32_t fixed); + +/** + * @brief Set DCache mmu mapping. + * Please do not call this function in your SDK application. + * + * @param uint32_t ext_ram : DPORT_MMU_ACCESS_FLASH for flash, DPORT_MMU_INVALID for invalid. In + * esp32c3, external memory is always flash + * + * @param uint32_t vaddr : virtual address in CPU address space. + * Can be DRam0, DRam1, DRom0, DPort and AHB buses address. + * Should be aligned by psize. + * + * @param uint32_t paddr : physical address in external memory. + * Should be aligned by psize. + * + * @param uint32_t psize : page size of DCache, in kilobytes. Should be 64 here. + * + * @param uint32_t num : pages to be set. + + * @param uint32_t fixed : 0 for physical pages grow with virtual pages, other for virtual pages map to same physical page. + * + * @return uint32_t: error status + * 0 : mmu set success + * 2 : vaddr or paddr is not aligned + * 3 : psize error + * 4 : vaddr is out of range + */ +int Cache_Dbus_MMU_Set(uint32_t ext_ram, uint32_t vaddr, uint32_t paddr, uint32_t psize, uint32_t num, uint32_t fixed); + +/** + * @brief Get cache mode of ICache or DCache. + * Please do not call this function in your SDK application. + * + * @param struct cache_mode * mode : the pointer of cache mode struct, caller should set the icache field + * + * return none + */ +void Cache_Get_Mode(struct cache_mode * mode); + +/** + * @brief Set cache page mode. + * + * @param mmu_page_mode_t + * + * @return None + */ +void MMU_Set_Page_Mode(mmu_page_mode_t pg_mode); + +/** + * @brief Get cache page mode. + * + * @param None + * + * @return page mode + */ +mmu_page_mode_t MMU_Get_Page_Mode(void); + +/** + * @brief Invalidate the cache items for ICache. + * Operation will be done CACHE_LINE_SIZE aligned. + * If the region is not in ICache addr room, nothing will be done. + * Please do not call this function in your SDK application. + * + * @param uint32_t addr: start address to invalidate + * + * @param uint32_t items: cache lines to invalidate, items * cache_line_size should not exceed the bus address size(16MB/32MB/64MB) + * + * @return None + */ +void Cache_Invalidate_ICache_Items(uint32_t addr, uint32_t items); + +/** + * @brief Invalidate the Cache items in the region from ICache or DCache. + * If the region is not in Cache addr room, nothing will be done. + * Please do not call this function in your SDK application. + * + * @param uint32_t addr : invalidated region start address. + * + * @param uint32_t size : invalidated region size. + * + * @return 0 for success + * 1 for invalid argument + */ +int Cache_Invalidate_Addr(uint32_t addr, uint32_t size); + +/** + * @brief Invalidate all cache items in ICache. + * Please do not call this function in your SDK application. + * + * @param None + * + * @return None + */ +void Cache_Invalidate_ICache_All(void); + +/** + * @brief Mask all buses through ICache and DCache. + * Please do not call this function in your SDK application. + * + * @param None + * + * @return None + */ +void Cache_Mask_All(void); + +/** + * @brief Suspend ICache auto preload operation, then you can resume it after some ICache operations. + * Please do not call this function in your SDK application. + * + * @param None + * + * @return uint32_t : 0 for ICache not auto preload before suspend. + */ +uint32_t Cache_Suspend_ICache_Autoload(void); + +/** + * @brief Resume ICache auto preload operation after some ICache operations. + * Please do not call this function in your SDK application. + * + * @param uint32_t autoload : 0 for ICache not auto preload before suspend. + * + * @return None. + */ +void Cache_Resume_ICache_Autoload(uint32_t autoload); + +/** + * @brief Start an ICache manual preload, will suspend auto preload of ICache. + * Please do not call this function in your SDK application. + * + * @param uint32_t addr : start address of the preload region. + * + * @param uint32_t size : size of the preload region, should not exceed the size of ICache. + * + * @param uint32_t order : the preload order, 0 for positive, other for negative + * + * @return uint32_t : 0 for ICache not auto preload before manual preload. + */ +uint32_t Cache_Start_ICache_Preload(uint32_t addr, uint32_t size, uint32_t order); + +/** + * @brief Return if the ICache manual preload done. + * Please do not call this function in your SDK application. + * + * @param None + * + * @return uint32_t : 0 for ICache manual preload not done. + */ +uint32_t Cache_ICache_Preload_Done(void); + +/** + * @brief End the ICache manual preload to resume auto preload of ICache. + * Please do not call this function in your SDK application. + * + * @param uint32_t autoload : 0 for ICache not auto preload before manual preload. + * + * @return None + */ +void Cache_End_ICache_Preload(uint32_t autoload); + +/** + * @brief Config autoload parameters of ICache. + * Please do not call this function in your SDK application. + * + * @param struct autoload_config * config : autoload parameters. + * + * @return None + */ +void Cache_Config_ICache_Autoload(const struct autoload_config * config); + +/** + * @brief Enable auto preload for ICache. + * Please do not call this function in your SDK application. + * + * @param None + * + * @return None + */ +void Cache_Enable_ICache_Autoload(void); + +/** + * @brief Disable auto preload for ICache. + * Please do not call this function in your SDK application. + * + * @param None + * + * @return None + */ +void Cache_Disable_ICache_Autoload(void); + +/** + * @brief Config a group of prelock parameters of ICache. + * Please do not call this function in your SDK application. + * + * @param struct lock_config * config : a group of lock parameters. + * + * @return None + */ + +void Cache_Enable_ICache_PreLock(const struct lock_config *config); + +/** + * @brief Disable a group of prelock parameters for ICache. + * However, the locked data will not be released. + * Please do not call this function in your SDK application. + * + * @param uint16_t group : 0 for group0, 1 for group1. + * + * @return None + */ +void Cache_Disable_ICache_PreLock(uint16_t group); + +/** + * @brief Lock the cache items for ICache. + * Operation will be done CACHE_LINE_SIZE aligned. + * If the region is not in ICache addr room, nothing will be done. + * Please do not call this function in your SDK application. + * + * @param uint32_t addr: start address to lock + * + * @param uint32_t items: cache lines to lock, items * cache_line_size should not exceed the bus address size(16MB/32MB/64MB) + * + * @return None + */ +void Cache_Lock_ICache_Items(uint32_t addr, uint32_t items); + +/** + * @brief Unlock the cache items for ICache. + * Operation will be done CACHE_LINE_SIZE aligned. + * If the region is not in ICache addr room, nothing will be done. + * Please do not call this function in your SDK application. + * + * @param uint32_t addr: start address to unlock + * + * @param uint32_t items: cache lines to unlock, items * cache_line_size should not exceed the bus address size(16MB/32MB/64MB) + * + * @return None + */ +void Cache_Unlock_ICache_Items(uint32_t addr, uint32_t items); + +/** + * @brief Lock the cache items in tag memory for ICache or DCache. + * Please do not call this function in your SDK application. + * + * @param uint32_t addr : start address of lock region. + * + * @param uint32_t size : size of lock region. + * + * @return 0 for success + * 1 for invalid argument + */ +int Cache_Lock_Addr(uint32_t addr, uint32_t size); + +/** + * @brief Unlock the cache items in tag memory for ICache or DCache. + * Please do not call this function in your SDK application. + * + * @param uint32_t addr : start address of unlock region. + * + * @param uint32_t size : size of unlock region. + * + * @return 0 for success + * 1 for invalid argument + */ +int Cache_Unlock_Addr(uint32_t addr, uint32_t size); + +/** + * @brief Disable ICache access for the cpu. + * This operation will make all ICache tag memory invalid, CPU can't access ICache, ICache will keep idle. + * Please do not call this function in your SDK application. + * + * @return uint32_t : auto preload enabled before + */ +uint32_t Cache_Disable_ICache(void); + +/** + * @brief Enable ICache access for the cpu. + * Please do not call this function in your SDK application. + * + * @param uint32_t autoload : ICache will preload then. + * + * @return None + */ +void Cache_Enable_ICache(uint32_t autoload); + +/** + * @brief Suspend ICache access for the cpu. + * The ICache tag memory is still there, CPU can't access ICache, ICache will keep idle. + * Please do not change MMU, cache mode or tag memory(tag memory can be changed in some special case). + * Please do not call this function in your SDK application. + * + * @param None + * + * @return uint32_t : auto preload enabled before + */ +uint32_t Cache_Suspend_ICache(void); + +/** + * @brief Resume ICache access for the cpu. + * Please do not call this function in your SDK application. + * + * @param uint32_t autoload : ICache will preload then. + * + * @return None + */ +void Cache_Resume_ICache(uint32_t autoload); + +/** + * @brief Get ICache cache line size + * + * @param None + * + * @return uint32_t: 16, 32, 64 Byte + */ +uint32_t Cache_Get_ICache_Line_Size(void); + +/** + * @brief Enable freeze for ICache. + * Any miss request will be rejected, including cpu miss and preload/autoload miss. + * Please do not call this function in your SDK application. + * + * @param cache_freeze_mode_t mode : 0 for assert busy 1 for assert hit + * + * @return None + */ +void Cache_Freeze_ICache_Enable(cache_freeze_mode_t mode); + +/** + * @brief Disable freeze for ICache. + * Please do not call this function in your SDK application. + * + * @return None + */ +void Cache_Freeze_ICache_Disable(void); + +/** + * @brief Travel tag memory to run a call back function. + * ICache and DCache are suspend when doing this. + * The callback will get the parameter tag_group_info, which will include a group of tag memory addresses and cache memory addresses. + * Please do not call this function in your SDK application. + * + * @param struct cache_mode * mode : the cache to check and the cache mode. + * + * @param uint32_t filter_addr : only the cache lines which may include the filter_address will be returned to the call back function. + * 0 for do not filter, all cache lines will be returned. + * + * @param void (* process)(struct tag_group_info *) : call back function, which may be called many times, a group(the addresses in the group are in the same position in the cache ways) a time. + * + * @return None + */ +void Cache_Travel_Tag_Memory(struct cache_mode * mode, uint32_t filter_addr, void (* process)(struct tag_group_info *)); + +/** + * @brief Get the virtual address from cache mode, cache tag and the virtual address offset of cache ways. + * Please do not call this function in your SDK application. + * + * @param struct cache_mode * mode : the cache to calculate the virtual address and the cache mode. + * + * @param uint32_t tag : the tag part of a tag item, 12-14 bits. + * + * @param uint32_t addr_offset : the virtual address offset of the cache ways. + * + * @return uint32_t : the virtual address. + */ +uint32_t Cache_Get_Virtual_Addr(struct cache_mode *mode, uint32_t tag, uint32_t vaddr_offset); + +/** + * @} + */ + +/** + * @brief Get the cache MMU IROM end address. + * Please do not call this function in your SDK application. + * + * @param void + * + * @return uint32_t : the word value of the address. + */ +uint32_t Cache_Get_IROM_MMU_End(void); + +/** + * @brief Get the cache MMU DROM end address. + * Please do not call this function in your SDK application. + * + * @param void + * + * @return uint32_t : the word value of the address. + */ +uint32_t Cache_Get_DROM_MMU_End(void); + +/** + * @brief Configure cache MMU page size according to instruction and rodata size + * + * @param irom_size The instruction cache MMU page size + * @param drom_size The rodata data cache MMU page size + */ +void Cache_Set_IDROM_MMU_Size(uint32_t irom_size, uint32_t drom_size); + +#define Cache_Dbus_MMU_Set(ext_ram, vaddr, paddr, psize, num, fixed) \ + Cache_MSPI_MMU_Set(ets_efuse_cache_encryption_enabled() ? SOC_MMU_SENSITIVE : 0, ext_ram, vaddr, paddr, psize, num, fixed) + +#ifdef __cplusplus +} +#endif diff --git a/components/esp_rom/esp32h21/include/esp32h21/rom/ecdsa.h b/components/esp_rom/esp32h21/include/esp32h21/rom/ecdsa.h new file mode 100644 index 00000000000..f1c785d6f1a --- /dev/null +++ b/components/esp_rom/esp32h21/include/esp32h21/rom/ecdsa.h @@ -0,0 +1,28 @@ +/* + * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#pragma once + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +//TODO: [ESP32H21] IDF-11496 + +#define ETS_DIGEST_LEN 32 /* SHA-256, bytes */ + +typedef enum { + ECDSA_CURVE_P192 = 1, + ECDSA_CURVE_P256 = 2 +} ECDSA_CURVE; + +int ets_ecdsa_verify(const uint8_t *key, const uint8_t *sig, ECDSA_CURVE curve_id, const uint8_t *digest, uint8_t *verified_digest); + +#ifdef __cplusplus +} +#endif diff --git a/components/esp_rom/esp32h21/include/esp32h21/rom/efuse.h b/components/esp_rom/esp32h21/include/esp32h21/rom/efuse.h new file mode 100644 index 00000000000..b33df42b717 --- /dev/null +++ b/components/esp_rom/esp32h21/include/esp32h21/rom/efuse.h @@ -0,0 +1,283 @@ +/* + * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#pragma once + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include +#include + +//TODO: [ESP32H21] IDF-11556 + +/** \defgroup efuse_APIs efuse APIs + * @brief ESP32H21 efuse read/write APIs + * @attention + * + */ + +/** @addtogroup efuse_APIs + * @{ + */ + +typedef enum { + ETS_EFUSE_KEY_PURPOSE_USER = 0, + ETS_EFUSE_KEY_PURPOSE_ECDSA_KEY = 1, + ETS_EFUSE_KEY_PURPOSE_RESERVED = 2, + ETS_EFUSE_KEY_PURPOSE_XTS_AES_128_KEY = 4, + ETS_EFUSE_KEY_PURPOSE_HMAC_DOWN_ALL = 5, + ETS_EFUSE_KEY_PURPOSE_HMAC_DOWN_JTAG = 6, + ETS_EFUSE_KEY_PURPOSE_HMAC_DOWN_DIGITAL_SIGNATURE = 7, + ETS_EFUSE_KEY_PURPOSE_HMAC_UP = 8, + ETS_EFUSE_KEY_PURPOSE_SECURE_BOOT_DIGEST0 = 9, + ETS_EFUSE_KEY_PURPOSE_SECURE_BOOT_DIGEST1 = 10, + ETS_EFUSE_KEY_PURPOSE_SECURE_BOOT_DIGEST2 = 11, + ETS_EFUSE_KEY_PURPOSE_MAX, +} ets_efuse_purpose_t; + +typedef enum { + ETS_EFUSE_BLOCK0 = 0, + ETS_EFUSE_MAC_SPI_SYS_0 = 1, + ETS_EFUSE_BLOCK_SYS_DATA = 2, + ETS_EFUSE_BLOCK_USR_DATA = 3, + ETS_EFUSE_BLOCK_KEY0 = 4, + ETS_EFUSE_BLOCK_KEY1 = 5, + ETS_EFUSE_BLOCK_KEY2 = 6, + ETS_EFUSE_BLOCK_KEY3 = 7, + ETS_EFUSE_BLOCK_KEY4 = 8, + ETS_EFUSE_BLOCK_KEY5 = 9, + ETS_EFUSE_BLOCK_KEY6 = 10, + ETS_EFUSE_BLOCK_MAX, +} ets_efuse_block_t; + +/** + * @brief Efuse read operation: copies data from physical efuses to efuse read registers. + * + * @param null + * + * @return : 0 if success, others if apb clock is not accepted + */ +int ets_efuse_read(void); + +/** + * @brief Efuse write operation: Copies data from efuse write registers to efuse. Operates on a single block of efuses at a time. + * + * @note This function does not update read efuses, call ets_efuse_read() once all programming is complete. + * + * @return : 0 if success, others if apb clock is not accepted + */ +int ets_efuse_program(ets_efuse_block_t block); + +/** + * @brief Set all Efuse program registers to zero. + * + * Call this before writing new data to the program registers. + */ +void ets_efuse_clear_program_registers(void); + +/** + * @brief Program a block of key data to an efuse block + * + * @param key_block Block to read purpose for. Must be in range ETS_EFUSE_BLOCK_KEY0 to ETS_EFUSE_BLOCK_KEY6. Key block must be unused (@ref ets_efuse_key_block_unused). + * @param purpose Purpose to set for this key. Purpose must be already unset. + * @param data Pointer to data to write. + * @param data_len Length of data to write. + * + * @note This function also calls ets_efuse_program() for the specified block, and for block 0 (setting the purpose) + */ +int ets_efuse_write_key(ets_efuse_block_t key_block, ets_efuse_purpose_t purpose, const void *data, size_t data_len); + + +/* @brief Return the address of a particular efuse block's first read register + * + * @param block Index of efuse block to look up + * + * @return 0 if block is invalid, otherwise a numeric read register address + * of the first word in the block. + */ +uint32_t ets_efuse_get_read_register_address(ets_efuse_block_t block); + +/** + * @brief Return the current purpose set for an efuse key block + * + * @param key_block Block to read purpose for. Must be in range ETS_EFUSE_BLOCK_KEY0 to ETS_EFUSE_BLOCK_KEY6. + */ +ets_efuse_purpose_t ets_efuse_get_key_purpose(ets_efuse_block_t key_block); + +/** + * @brief Find a key block with the particular purpose set + * + * @param purpose Purpose to search for. + * @param[out] key_block Pointer which will be set to the key block if found. Can be NULL, if only need to test the key block exists. + * @return true if found, false if not found. If false, value at key_block pointer is unchanged. + */ +bool ets_efuse_find_purpose(ets_efuse_purpose_t purpose, ets_efuse_block_t *key_block); + +/** + * Return true if the key block is unused, false otherwise. + * + * An unused key block is all zero content, not read or write protected, + * and has purpose 0 (ETS_EFUSE_KEY_PURPOSE_USER) + * + * @param key_block key block to check. + * + * @return true if key block is unused, false if key block or used + * or the specified block index is not a key block. + */ +bool ets_efuse_key_block_unused(ets_efuse_block_t key_block); + + +/** + * @brief Search for an unused key block and return the first one found. + * + * See @ref ets_efuse_key_block_unused for a description of an unused key block. + * + * @return First unused key block, or ETS_EFUSE_BLOCK_MAX if no unused key block is found. + */ +ets_efuse_block_t ets_efuse_find_unused_key_block(void); + +/** + * @brief Return the number of unused efuse key blocks (0-6) + */ +unsigned ets_efuse_count_unused_key_blocks(void); + +/** + * @brief Calculate Reed-Solomon Encoding values for a block of efuse data. + * + * @param data Pointer to data buffer (length 32 bytes) + * @param rs_values Pointer to write encoded data to (length 12 bytes) + */ +void ets_efuse_rs_calculate(const void *data, void *rs_values); + +/** + * @brief Read if download mode disabled from Efuse + * + * @return + * - true for efuse disable download mode. + * - false for efuse doesn't disable download mode. + */ +bool ets_efuse_download_modes_disabled(void); + +/** + * @brief Read if uart print control value from Efuse + * + * @return + * - 0 for uart force print. + * - 1 for uart print when GPIO8 is low when digital reset. + * 2 for uart print when GPIO8 is high when digital reset. + * 3 for uart force silent + */ +uint32_t ets_efuse_get_uart_print_control(void); + +/** + * @brief Read if usb download mode disabled from Efuse + * + * (Also returns true if security download mode is enabled, as this mode + * disables USB download.) + * + * @return + * - true for efuse disable usb download mode. + * - false for efuse doesn't disable usb download mode. + */ +bool ets_efuse_usb_download_mode_disabled(void); + +/** + * @brief Read if security download modes enabled from Efuse + * + * @return + * - true for efuse enable security download mode. + * - false for efuse doesn't enable security download mode. + */ +bool ets_efuse_security_download_modes_enabled(void); + +/** + * @brief Return true if secure boot is enabled in EFuse + */ +bool ets_efuse_secure_boot_enabled(void); + +/** + * @brief Return true if secure boot aggressive revoke is enabled in EFuse + */ +bool ets_efuse_secure_boot_aggressive_revoke_enabled(void); + +/** + * @brief Return true if cache encryption (flash, etc) is enabled from boot via EFuse + */ +bool ets_efuse_cache_encryption_enabled(void); + +/** + * @brief Return true if EFuse indicates to send a flash resume command. + */ +bool ets_efuse_force_send_resume(void); + +/** + * @brief return the time in us ROM boot need wait flash to power on from Efuse + * + * @return + * - uint32_t the time in us. + */ +uint32_t ets_efuse_get_flash_delay_us(void); + +#define EFUSE_SPICONFIG_SPI_DEFAULTS 0 +#define EFUSE_SPICONFIG_HSPI_DEFAULTS 1 + +#define EFUSE_SPICONFIG_RET_SPICLK_MASK 0x3f +#define EFUSE_SPICONFIG_RET_SPICLK_SHIFT 0 +#define EFUSE_SPICONFIG_RET_SPICLK(ret) (((ret) >> EFUSE_SPICONFIG_RET_SPICLK_SHIFT) & EFUSE_SPICONFIG_RET_SPICLK_MASK) + +#define EFUSE_SPICONFIG_RET_SPIQ_MASK 0x3f +#define EFUSE_SPICONFIG_RET_SPIQ_SHIFT 6 +#define EFUSE_SPICONFIG_RET_SPIQ(ret) (((ret) >> EFUSE_SPICONFIG_RET_SPIQ_SHIFT) & EFUSE_SPICONFIG_RET_SPIQ_MASK) + +#define EFUSE_SPICONFIG_RET_SPID_MASK 0x3f +#define EFUSE_SPICONFIG_RET_SPID_SHIFT 12 +#define EFUSE_SPICONFIG_RET_SPID(ret) (((ret) >> EFUSE_SPICONFIG_RET_SPID_SHIFT) & EFUSE_SPICONFIG_RET_SPID_MASK) + +#define EFUSE_SPICONFIG_RET_SPICS0_MASK 0x3f +#define EFUSE_SPICONFIG_RET_SPICS0_SHIFT 18 +#define EFUSE_SPICONFIG_RET_SPICS0(ret) (((ret) >> EFUSE_SPICONFIG_RET_SPICS0_SHIFT) & EFUSE_SPICONFIG_RET_SPICS0_MASK) + + +#define EFUSE_SPICONFIG_RET_SPIHD_MASK 0x3f +#define EFUSE_SPICONFIG_RET_SPIHD_SHIFT 24 +#define EFUSE_SPICONFIG_RET_SPIHD(ret) (((ret) >> EFUSE_SPICONFIG_RET_SPIHD_SHIFT) & EFUSE_SPICONFIG_RET_SPIHD_MASK) + +/** + * @brief Enable JTAG temporarily by writing a JTAG HMAC "key" into + * the JTAG_CTRL registers. + * + * Works if JTAG has been "soft" disabled by burning the EFUSE_SOFT_DIS_JTAG efuse. + * + * Will enable the HMAC module to generate a "downstream" HMAC value from a key already saved in efuse, and then write the JTAG HMAC "key" which will enable JTAG if the two keys match. + * + * @param jtag_hmac_key Pointer to a 32 byte array containing a valid key. Supplied by user. + * @param key_block Index of a key block containing the source for this key. + * + * @return ETS_FAILED if HMAC operation fails or invalid parameter, ETS_OK otherwise. ETS_OK doesn't necessarily mean that JTAG was enabled. + */ +int ets_jtag_enable_temporarily(const uint8_t *jtag_hmac_key, ets_efuse_block_t key_block); + +/** + * @brief A crc8 algorithm used for MAC addresses in efuse + * + * @param unsigned char const *p : Pointer to original data. + * + * @param unsigned int len : Data length in byte. + * + * @return unsigned char: Crc value. + */ +unsigned char esp_crc8(unsigned char const *p, unsigned int len); + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif diff --git a/components/esp_rom/esp32h21/include/esp32h21/rom/esp_flash.h b/components/esp_rom/esp32h21/include/esp32h21/rom/esp_flash.h new file mode 100644 index 00000000000..6d48e4be2cc --- /dev/null +++ b/components/esp_rom/esp32h21/include/esp32h21/rom/esp_flash.h @@ -0,0 +1,46 @@ +/* + * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#pragma once + +#include "esp_err.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/* Note: Most of esp_flash APIs in ROM are compatible with headers in ESP-IDF, this function + just adds ROM-specific parts +*/ + +struct spi_flash_chip_t; +typedef struct esp_flash_t esp_flash_t; + +/* Structure to wrap "global" data used by esp_flash in ROM */ +typedef struct { + /* Default SPI flash chip, ie main chip attached to the MCU + This chip is used if the 'chip' argument passed to esp_flash_xxx API functions is ever NULL + */ + esp_flash_t *default_chip; + + /* Global API OS notification start/end/chip_check functions + + These are used by ROM if no other host functions are configured. + */ + struct { + esp_err_t (*start)(esp_flash_t *chip); + esp_err_t (*end)(esp_flash_t *chip, esp_err_t err); + esp_err_t (*chip_check)(esp_flash_t **inout_chip); + } api_funcs; +} esp_flash_rom_global_data_t; + +/** Access a pointer to the global data used by the ROM spi_flash driver + */ +esp_flash_rom_global_data_t *esp_flash_get_rom_global_data(void); + +#ifdef __cplusplus +} +#endif diff --git a/components/esp_rom/esp32h21/include/esp32h21/rom/ets_sys.h b/components/esp_rom/esp32h21/include/esp32h21/rom/ets_sys.h new file mode 100644 index 00000000000..4bb3a16fcfd --- /dev/null +++ b/components/esp_rom/esp32h21/include/esp32h21/rom/ets_sys.h @@ -0,0 +1,428 @@ +/* + * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#pragma once + +#include +#include + +//TODO: [ESP32H21] IDF-11555 + +#ifdef __cplusplus +extern "C" { +#endif + +/** \defgroup ets_sys_apis, ets system related apis + * @brief ets system apis + */ + +/** @addtogroup ets_sys_apis + * @{ + */ + +/************************************************************************ + * NOTE + * Many functions in this header files can't be run in FreeRTOS. + * Please see the comment of the Functions. + * There are also some functions that doesn't work on FreeRTOS + * without listed in the header, such as: + * xtos functions start with "_xtos_" in ld file. + * + *********************************************************************** + */ + +/** \defgroup ets_apis, Espressif Task Scheduler related apis + * @brief ets apis + */ + +/** @addtogroup ets_apis + * @{ + */ + +typedef enum { + ETS_OK = 0, /**< return successful in ets*/ + ETS_FAILED = 1, /**< return failed in ets*/ + ETS_PENDING = 2, + ETS_BUSY = 3, + ETS_CANCEL = 4, +} ETS_STATUS; + +typedef ETS_STATUS ets_status_t; + +typedef uint32_t ETSSignal; +typedef uint32_t ETSParam; + +typedef struct ETSEventTag ETSEvent; /**< Event transmit/receive in ets*/ + +struct ETSEventTag { + ETSSignal sig; /**< Event signal, in same task, different Event with different signal*/ + ETSParam par; /**< Event parameter, sometimes without usage, then will be set as 0*/ +}; + +typedef void (*ETSTask)(ETSEvent *e); /**< Type of the Task processor*/ +typedef void (* ets_idle_cb_t)(void *arg); /**< Type of the system idle callback*/ + + + + + +/** + * @} + */ + +/** \defgroup ets_boot_apis, Boot routing related apis + * @brief ets boot apis + */ + +/** @addtogroup ets_apis + * @{ + */ + +extern const char *const exc_cause_table[40]; ///**< exception cause that defined by the core.*/ + +/** + * @brief Set Pro cpu Entry code, code can be called in PRO CPU when booting is not completed. + * When Pro CPU booting is completed, Pro CPU will call the Entry code if not NULL. + * + * @param uint32_t start : the PRO Entry code address value in uint32_t + * + * @return None + */ +void ets_set_user_start(uint32_t start); + +/** + * @} + */ + +/** \defgroup ets_printf_apis, ets_printf related apis used in ets + * @brief ets printf apis + */ + +/** @addtogroup ets_printf_apis + * @{ + */ + +/** + * @brief Printf the strings to uart or other devices, similar with printf, simple than printf. + * Can not print float point data format, or longlong data format. + * So we maybe only use this in ROM. + * + * @param const char *fmt : See printf. + * + * @param ... : See printf. + * + * @return int : the length printed to the output device. + */ +int ets_printf(const char *fmt, ...); + +/** + * @brief Get the uart channel of ets_printf(uart_tx_one_char). + * + * @return uint8_t uart channel used by ets_printf(uart_tx_one_char). + */ +uint8_t ets_get_printf_channel(void); + +/** + * @brief Output a char to uart, which uart to output(which is in uart module in ROM) is not in scope of the function. + * Can not print float point data format, or longlong data format + * + * @param char c : char to output. + * + * @return None + */ +void ets_write_char_uart(char c); + +/** + * @brief Ets_printf have two output functions： putc1 and putc2, both of which will be called if need output. + * To install putc1, which is defaulted installed as ets_write_char_uart in none silent boot mode, as NULL in silent mode. + * + * @param void (*)(char) p: Output function to install. + * + * @return None + */ +void ets_install_putc1(void (*p)(char c)); + +/** + * @brief Ets_printf have two output functions： putc1 and putc2, both of which will be called if need output. + * To install putc2, which is defaulted installed as NULL. + * + * @param void (*)(char) p: Output function to install. + * + * @return None + */ +void ets_install_putc2(void (*p)(char c)); + +/** + * @brief Install putc1 as ets_write_char_uart. + * In silent boot mode(to void interfere the UART attached MCU), we can call this function, after booting ok. + * + * @param None + * + * @return None + */ +void ets_install_uart_printf(void); + +#define ETS_PRINTF(...) ets_printf(...) + +#define ETS_ASSERT(v) do { \ + if (!(v)) { \ + ets_printf("%s %u \n", __FILE__, __LINE__); \ + while (1) {}; \ + } \ +} while (0); + +/** + * @} + */ + +/** \defgroup ets_timer_apis, ets_timer related apis used in ets + * @brief ets timer apis + */ + +/** @addtogroup ets_timer_apis + * @{ + */ +typedef void ETSTimerFunc(void *timer_arg);/**< timer handler*/ + +typedef struct _ETSTIMER_ { + struct _ETSTIMER_ *timer_next; /**< timer linker*/ + uint32_t timer_expire; /**< abstract time when timer expire*/ + uint32_t timer_period; /**< timer period, 0 means timer is not periodic repeated*/ + ETSTimerFunc *timer_func; /**< timer handler*/ + void *timer_arg; /**< timer handler argument*/ +} ETSTimer; + +/** + * @brief Init ets timer, this timer range is 640 us to 429496 ms + * In FreeRTOS, please call FreeRTOS apis, never call this api. + * + * @param None + * + * @return None + */ +void ets_timer_init(void); + +/** + * @brief In FreeRTOS, please call FreeRTOS apis, never call this api. + * + * @param None + * + * @return None + */ +void ets_timer_deinit(void); + +/** + * @brief Arm an ets timer, this timer range is 640 us to 429496 ms. + * In FreeRTOS, please call FreeRTOS apis, never call this api. + * + * @param ETSTimer *timer : Timer struct pointer. + * + * @param uint32_t tmout : Timer value in ms, range is 1 to 429496. + * + * @param bool repeat : Timer is periodic repeated. + * + * @return None + */ +void ets_timer_arm(ETSTimer *timer, uint32_t tmout, bool repeat); + +/** + * @brief Arm an ets timer, this timer range is 640 us to 429496 ms. + * In FreeRTOS, please call FreeRTOS apis, never call this api. + * + * @param ETSTimer *timer : Timer struct pointer. + * + * @param uint32_t tmout : Timer value in us, range is 1 to 429496729. + * + * @param bool repeat : Timer is periodic repeated. + * + * @return None + */ +void ets_timer_arm_us(ETSTimer *ptimer, uint32_t us, bool repeat); + +/** + * @brief Disarm an ets timer. + * In FreeRTOS, please call FreeRTOS apis, never call this api. + * + * @param ETSTimer *timer : Timer struct pointer. + * + * @return None + */ +void ets_timer_disarm(ETSTimer *timer); + +/** + * @brief Set timer callback and argument. + * In FreeRTOS, please call FreeRTOS apis, never call this api. + * + * @param ETSTimer *timer : Timer struct pointer. + * + * @param ETSTimerFunc *pfunction : Timer callback. + * + * @param void *parg : Timer callback argument. + * + * @return None + */ +void ets_timer_setfn(ETSTimer *ptimer, ETSTimerFunc *pfunction, void *parg); + +/** + * @brief Unset timer callback and argument to NULL. + * In FreeRTOS, please call FreeRTOS apis, never call this api. + * + * @param ETSTimer *timer : Timer struct pointer. + * + * @return None + */ +void ets_timer_done(ETSTimer *ptimer); + +/** + * @brief CPU do while loop for some time. + * In FreeRTOS task, please call FreeRTOS apis. + * + * @param uint32_t us : Delay time in us. + * + * @return None + */ +void ets_delay_us(uint32_t us); + +/** + * @brief Set the real CPU ticks per us to the ets, so that ets_delay_us will be accurate. + * Call this function when CPU frequency is changed. + * + * @param uint32_t ticks_per_us : CPU ticks per us. + * + * @return None + */ +void ets_update_cpu_frequency(uint32_t ticks_per_us); + + + +/** + * @brief Get the real CPU ticks per us to the ets. + * This function do not return real CPU ticks per us, just the record in ets. It can be used to check with the real CPU frequency. + * + * @param None + * + * @return uint32_t : CPU ticks per us record in ets. + */ +uint32_t ets_get_cpu_frequency(void); + +/** + * @} + */ + +/** \defgroup ets_intr_apis, ets interrupt configure related apis + * @brief ets intr apis + */ + +/** @addtogroup ets_intr_apis + * @{ + */ + +typedef void (* ets_isr_t)(void *);/**< interrupt handler type*/ + +/** + * @brief Attach a interrupt handler to a CPU interrupt number. + * This function equals to _xtos_set_interrupt_handler_arg(i, func, arg). + * In FreeRTOS, please call FreeRTOS apis, never call this api. + * + * @param int i : CPU interrupt number. + * + * @param ets_isr_t func : Interrupt handler. + * + * @param void *arg : argument of the handler. + * + * @return None + */ +void ets_isr_attach(int i, ets_isr_t func, void *arg); + +/** + * @brief Mask the interrupts which show in mask bits. + * This function equals to _xtos_ints_off(mask). + * In FreeRTOS, please call FreeRTOS apis, never call this api. + * + * @param uint32_t mask : BIT(i) means mask CPU interrupt number i. + * + * @return None + */ +void ets_isr_mask(uint32_t mask); + +/** + * @brief Unmask the interrupts which show in mask bits. + * This function equals to _xtos_ints_on(mask). + * In FreeRTOS, please call FreeRTOS apis, never call this api. + * + * @param uint32_t mask : BIT(i) means mask CPU interrupt number i. + * + * @return None + */ +void ets_isr_unmask(uint32_t unmask); + +/** + * @brief Lock the interrupt to level 2. + * This function direct set the CPU registers. + * In FreeRTOS, please call FreeRTOS apis, never call this api. + * + * @param None + * + * @return None + */ +void ets_intr_lock(void); + +/** + * @brief Unlock the interrupt to level 0. + * This function direct set the CPU registers. + * In FreeRTOS, please call FreeRTOS apis, never call this api. + * + * @param None + * + * @return None + */ +void ets_intr_unlock(void); + +/** + * @brief Attach an CPU interrupt to a hardware source. + * We have 4 steps to use an interrupt: + * 1.Attach hardware interrupt source to CPU. intr_matrix_set(0, ETS_WIFI_MAC_INTR_SOURCE, ETS_WMAC_INUM); + * 2.Set interrupt handler. xt_set_interrupt_handler(ETS_WMAC_INUM, func, NULL); + * 3.Enable interrupt for CPU. xt_ints_on(1 << ETS_WMAC_INUM); + * 4.Enable interrupt in the module. + * + * @param int cpu_no : The CPU which the interrupt number belongs. + * + * @param uint32_t model_num : The interrupt hardware source number, please see the interrupt hardware source table. + * + * @param uint32_t intr_num : The interrupt number CPU, please see the interrupt cpu using table. + * + * @return None + */ +void intr_matrix_set(int cpu_no, uint32_t model_num, uint32_t intr_num); + +/** + * @} + */ + +#ifndef MAC2STR +#define MAC2STR(a) (a)[0], (a)[1], (a)[2], (a)[3], (a)[4], (a)[5] +#define MACSTR "%02x:%02x:%02x:%02x:%02x:%02x" +#endif + +#define ETS_MEM_BAR() asm volatile ( "" : : : "memory" ) + +//TODO: [ESP32H21] IDF-11555, need to check +typedef enum { + OK = 0, + FAIL, + PENDING, + BUSY, + CANCEL, +} STATUS; + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif diff --git a/components/esp_rom/esp32h21/include/esp32h21/rom/gpio.h b/components/esp_rom/esp32h21/include/esp32h21/rom/gpio.h new file mode 100644 index 00000000000..4fb5a201735 --- /dev/null +++ b/components/esp_rom/esp32h21/include/esp32h21/rom/gpio.h @@ -0,0 +1,212 @@ +/* + * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#pragma once + +#include +#include +#include "soc/gpio_reg.h" + +//TODO: [ESP32H21] IDF-11611 + +#ifdef __cplusplus +extern "C" { +#endif + +/** \defgroup gpio_apis, uart configuration and communication related apis + * @brief gpio apis + */ + +/** @addtogroup gpio_apis + * @{ + */ + +#define GPIO_REG_READ(reg) READ_PERI_REG(reg) +#define GPIO_REG_WRITE(reg, val) WRITE_PERI_REG(reg, val) +#define GPIO_ID_PIN0 0 +#define GPIO_ID_PIN(n) (GPIO_ID_PIN0+(n)) +#define GPIO_PIN_ADDR(i) (GPIO_PIN0_REG + i*4) + +//TODO: [ESP32H21] IDF-11611, need check +#define GPIO_FUNC_IN_HIGH 0x20 +#define GPIO_FUNC_IN_LOW 0x30 + +#define GPIO_ID_IS_PIN_REGISTER(reg_id) \ + ((reg_id >= GPIO_ID_PIN0) && (reg_id <= GPIO_ID_PIN(GPIO_PIN_COUNT-1))) + +#define GPIO_REGID_TO_PINIDX(reg_id) ((reg_id) - GPIO_ID_PIN0) + +typedef enum { + GPIO_PIN_INTR_DISABLE = 0, + GPIO_PIN_INTR_POSEDGE = 1, + GPIO_PIN_INTR_NEGEDGE = 2, + GPIO_PIN_INTR_ANYEDGE = 3, + GPIO_PIN_INTR_LOLEVEL = 4, + GPIO_PIN_INTR_HILEVEL = 5 +} GPIO_INT_TYPE; + + +/** + * @brief Change GPIO(0-27) pin output by setting, clearing, or disabling pins, GPIO0<->BIT(0). + * There is no particular ordering guaranteed; so if the order of writes is significant, + * calling code should divide a single call into multiple calls. + * + * @param uint32_t set_mask : the gpios that need high level. + * + * @param uint32_t clear_mask : the gpios that need low level. + * + * @param uint32_t enable_mask : the gpios that need be changed. + * + * @param uint32_t disable_mask : the gpios that need disable output. + * + * @return None + */ +void gpio_output_set(uint32_t set_mask, uint32_t clear_mask, uint32_t enable_mask, uint32_t disable_mask); + +/** + * @brief Sample the value of GPIO input pins(0-27) and returns a bitmask. + * + * @param None + * + * @return uint32_t : bitmask for GPIO input pins, BIT(0) for GPIO0. + */ +uint32_t gpio_input_get(void); + +/** + * @brief Set GPIO to wakeup the ESP32. + * Please do not call this function in SDK. + * + * @param uint32_t i: gpio number. + * + * @param GPIO_INT_TYPE intr_state : only GPIO_PIN_INTR_LOLEVEL\GPIO_PIN_INTR_HILEVEL can be used + * + * @return None + */ +void gpio_pin_wakeup_enable(uint32_t i, GPIO_INT_TYPE intr_state); + +/** + * @brief disable GPIOs to wakeup the ESP32. + * Please do not call this function in SDK. + * + * @param None + * + * @return None + */ +void gpio_pin_wakeup_disable(void); + +/** + * @brief set gpio input to a signal, one gpio can input to several signals. + * + * @param uint32_t gpio : gpio number, 0~27 + * gpio == 0x3C, input 0 to signal + * gpio == 0x3A, input nothing to signal + * gpio == 0x38, input 1 to signal + * + * @param uint32_t signal_idx : signal index. + * + * @param bool inv : the signal is inv or not + * + * @return None + */ +void gpio_matrix_in(uint32_t gpio, uint32_t signal_idx, bool inv); + +/** + * @brief set signal output to gpio, one signal can output to several gpios. + * + * @param uint32_t gpio : gpio number, 0~27 + * + * @param uint32_t signal_idx : signal index. + * signal_idx == 0x80, cancel output put to the gpio + * + * @param bool out_inv : the signal output is invert or not + * + * @param bool oen_inv : the signal output enable is invert or not + * + * @return None + */ +void gpio_matrix_out(uint32_t gpio, uint32_t signal_idx, bool out_inv, bool oen_inv); + +/** + * @brief Select pad as a gpio function from IOMUX. + * + * @param uint32_t gpio_num : gpio number, 0~27 + * + * @return None + */ +void gpio_pad_select_gpio(uint32_t gpio_num); + +/** + * @brief Set pad driver capability. + * + * @param uint32_t gpio_num : gpio number, 0~27 + * + * @param uint32_t drv : 0-3 + * + * @return None + */ +void gpio_pad_set_drv(uint32_t gpio_num, uint32_t drv); + +/** + * @brief Pull up the pad from gpio number. + * + * @param uint32_t gpio_num : gpio number, 0~27 + * + * @return None + */ +void gpio_pad_pullup(uint32_t gpio_num); + +/** + * @brief Pull down the pad from gpio number. + * + * @param uint32_t gpio_num : gpio number, 0~27 + * + * @return None + */ +void gpio_pad_pulldown(uint32_t gpio_num); + +/** + * @brief Unhold the pad from gpio number. + * + * @param uint32_t gpio_num : gpio number, 0~27 + * + * @return None + */ +void gpio_pad_unhold(uint32_t gpio_num); + +/** + * @brief Hold the pad from gpio number. + * + * @param uint32_t gpio_num : gpio number, 0~27 + * + * @return None + */ +void gpio_pad_hold(uint32_t gpio_num); + +/** + * @brief enable gpio pad input. + * + * @param uint32_t gpio_num : gpio number, 0~27 + * + * @return None + */ +void gpio_pad_input_enable(uint32_t gpio_num); + +/** + * @brief disable gpio pad input. + * + * @param uint32_t gpio_num : gpio number, 0~27 + * + * @return None + */ +void gpio_pad_input_disable(uint32_t gpio_num); + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif diff --git a/components/esp_rom/esp32h21/include/esp32h21/rom/hmac.h b/components/esp_rom/esp32h21/include/esp32h21/rom/hmac.h new file mode 100644 index 00000000000..a98c0119cae --- /dev/null +++ b/components/esp_rom/esp32h21/include/esp32h21/rom/hmac.h @@ -0,0 +1,54 @@ +/* + * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#pragma once + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include +#include "efuse.h" + +//TODO: [ESP32H21] IDF-11495 + +void ets_hmac_enable(void); + +void ets_hmac_disable(void); + +/* Use the "upstream" HMAC key (ETS_EFUSE_KEY_PURPOSE_HMAC_UP) + to digest a message. +*/ +int ets_hmac_calculate_message(ets_efuse_block_t key_block, const void *message, size_t message_len, uint8_t *hmac); + +/* Calculate a downstream HMAC message to temporarily enable JTAG, or + to generate a Digital Signature data decryption key. + + - purpose must be ETS_EFUSE_KEY_PURPOSE_HMAC_DOWN_DIGITAL_SIGNATURE + or ETS_EFUSE_KEY_PURPOSE_HMAC_DOWN_JTAG + + - key_block must be in range ETS_EFUSE_BLOCK_KEY0 toETS_EFUSE_BLOCK_KEY6. + This efuse block must have the corresponding purpose set in "purpose", or + ETS_EFUSE_KEY_PURPOSE_HMAC_DOWN_ALL. + + The result of this HMAC calculation is only made available "downstream" to the + corresponding hardware module, and cannot be accessed by software. +*/ +int ets_hmac_calculate_downstream(ets_efuse_block_t key_block, ets_efuse_purpose_t purpose); + +/* Invalidate a downstream HMAC value previously calculated by ets_hmac_calculate_downstream(). + * + * - purpose must match a previous call to ets_hmac_calculate_downstream(). + * + * After this function is called, the corresponding internal operation (JTAG or DS) will no longer + * have access to the generated key. + */ +int ets_hmac_invalidate_downstream(ets_efuse_purpose_t purpose); + +#ifdef __cplusplus +} +#endif diff --git a/components/esp_rom/esp32h21/include/esp32h21/rom/libc_stubs.h b/components/esp_rom/esp32h21/include/esp32h21/rom/libc_stubs.h new file mode 100644 index 00000000000..8b2b9ebd636 --- /dev/null +++ b/components/esp_rom/esp32h21/include/esp32h21/rom/libc_stubs.h @@ -0,0 +1,94 @@ +/* + * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#include +#include +#include +#include +#include +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/* +ESP32-H21 ROM code contains implementations of some of C library functions. +Whenever a function in ROM needs to use a syscall, it calls a pointer to the corresponding syscall +implementation defined in the following struct. + +The table itself, by default, is not allocated in RAM. A global pointer syscall_table_ptr is used to +set the address + +So, before using any of the C library functions (except for pure functions and memcpy/memset functions), +application must allocate syscall table structure for each CPU being used, and populate it with pointers +to actual implementations of corresponding syscalls. +*/ + +struct syscall_stub_table +{ + struct _reent* (*__getreent)(void); + void* (*_malloc_r)(struct _reent *r, size_t); + void (*_free_r)(struct _reent *r, void*); + void* (*_realloc_r)(struct _reent *r, void*, size_t); + void* (*_calloc_r)(struct _reent *r, size_t, size_t); + void (*_abort)(void); + int (*_system_r)(struct _reent *r, const char*); + int (*_rename_r)(struct _reent *r, const char*, const char*); + clock_t (*_times_r)(struct _reent *r, struct tms *); + int (*_gettimeofday_r) (struct _reent *r, struct timeval *, void *); + void (*_raise_r)(struct _reent *r); + int (*_unlink_r)(struct _reent *r, const char*); + int (*_link_r)(struct _reent *r, const char*, const char*); + int (*_stat_r)(struct _reent *r, const char*, struct stat *); + int (*_fstat_r)(struct _reent *r, int, struct stat *); + void* (*_sbrk_r)(struct _reent *r, ptrdiff_t); + int (*_getpid_r)(struct _reent *r); + int (*_kill_r)(struct _reent *r, int, int); + void (*_exit_r)(struct _reent *r, int); + int (*_close_r)(struct _reent *r, int); + int (*_open_r)(struct _reent *r, const char *, int, int); + int (*_write_r)(struct _reent *r, int, const void *, int); + int (*_lseek_r)(struct _reent *r, int, int, int); + int (*_read_r)(struct _reent *r, int, void *, int); +#ifdef _RETARGETABLE_LOCKING + void (*_retarget_lock_init)(_LOCK_T *lock); + void (*_retarget_lock_init_recursive)(_LOCK_T *lock); + void (*_retarget_lock_close)(_LOCK_T lock); + void (*_retarget_lock_close_recursive)(_LOCK_T lock); + void (*_retarget_lock_acquire)(_LOCK_T lock); + void (*_retarget_lock_acquire_recursive)(_LOCK_T lock); + int (*_retarget_lock_try_acquire)(_LOCK_T lock); + int (*_retarget_lock_try_acquire_recursive)(_LOCK_T lock); + void (*_retarget_lock_release)(_LOCK_T lock); + void (*_retarget_lock_release_recursive)(_LOCK_T lock); +#else + void (*_lock_init)(_lock_t *lock); + void (*_lock_init_recursive)(_lock_t *lock); + void (*_lock_close)(_lock_t *lock); + void (*_lock_close_recursive)(_lock_t *lock); + void (*_lock_acquire)(_lock_t *lock); + void (*_lock_acquire_recursive)(_lock_t *lock); + int (*_lock_try_acquire)(_lock_t *lock); + int (*_lock_try_acquire_recursive)(_lock_t *lock); + void (*_lock_release)(_lock_t *lock); + void (*_lock_release_recursive)(_lock_t *lock); +#endif + int (*_printf_float)(struct _reent *data, void *pdata, FILE * fp, int (*pfunc) (struct _reent *, FILE *, const char *, size_t len), va_list * ap); + int (*_scanf_float) (struct _reent *rptr, void *pdata, FILE *fp, va_list *ap); + void (*__assert_func) (const char *file, int line, const char * func, const char *failedexpr) __attribute__((noreturn)); + void (*__sinit) (struct _reent *r); + void (*_cleanup_r) (struct _reent* r); +}; + +extern struct syscall_stub_table *syscall_table_ptr; + +#ifdef __cplusplus +} // extern "C" +#endif diff --git a/components/esp_rom/esp32h21/include/esp32h21/rom/rom_layout.h b/components/esp_rom/esp32h21/include/esp32h21/rom/rom_layout.h new file mode 100644 index 00000000000..33355b8db82 --- /dev/null +++ b/components/esp_rom/esp32h21/include/esp32h21/rom/rom_layout.h @@ -0,0 +1,97 @@ +/* + * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#pragma once + +#include + +//TODO: [ESP32H21] IDF-11555 + +#ifdef __cplusplus +extern "C" { +#endif + +#define SUPPORT_BTDM 0 +#define SUPPORT_BTBB 0 +#define SUPPORT_WIFI 0 +#define SUPPORT_USB_DWCOTG 0 +#define SUPPORT_COEXIST 0 +#define SUPPORT_MBEDTLS 0 + +/* Structure and functions for returning ROM global layout + * + * This is for address symbols defined in the linker script, which may change during ECOs. + */ +typedef struct { + void *dram0_stack_shared_mem_start; + void *dram0_rtos_reserved_start; + void *stack_sentry; + void *stack; + +#if SUPPORT_BTDM + void *data_start_btdm; + void *data_end_btdm; + void *bss_start_btdm; + void *bss_end_btdm; + void *data_start_btdm_rom; + void *data_end_btdm_rom; + void *data_start_interface_btdm; + void *data_end_interface_btdm; + void *bss_start_interface_btdm; + void *bss_end_interface_btdm; +#endif + +#if SUPPORT_BTBB + void *dram_start_btbbrom; + void *dram_end_btbbrom; +#endif + + /* Other DRAM ranges */ +#if SUPPORT_BTDM || SUPPORT_WIFI + void *dram_start_phyrom; + void *dram_end_phyrom; +#endif +#if SUPPORT_WIFI + void *dram_start_coexist; + void *dram_end_coexist; + void *dram_start_net80211; + void *dram_end_net80211; + void *dram_start_pp; + void *dram_end_pp; + void *data_start_interface_coexist; + void *data_end_interface_coexist; + void *bss_start_interface_coexist; + void *bss_end_interface_coexist; + void *data_start_interface_net80211; + void *data_end_interface_net80211; + void *bss_start_interface_net80211; + void *bss_end_interface_net80211; + void *data_start_interface_pp; + void *data_end_interface_pp; + void *bss_start_interface_pp; + void *bss_end_interface_pp; +#endif + +#if SUPPORT_USB_DWCOTG + void *dram_start_usb_dwcotg_rom; + void *dram_end_usb_dwcotg_rom; +#else + //Two reserved members are defined here, so the structure will not be broken, + //please keep in mind that there is no memory can be released between + //dram_start_usb_reserved_rom ~ dram_end_usb_reserved_rom. + void *dram_start_usb_reserved_rom; + void *dram_end_usb_reserved_rom; +#endif + + void *dram_start_uart_rom; + void *dram_end_uart_rom; +} ets_rom_layout_t; + +extern const ets_rom_layout_t * const ets_rom_layout_p; + +#ifdef __cplusplus +} +#endif diff --git a/components/esp_rom/esp32h21/include/esp32h21/rom/rsa_pss.h b/components/esp_rom/esp32h21/include/esp32h21/rom/rsa_pss.h new file mode 100644 index 00000000000..c8fb830361e --- /dev/null +++ b/components/esp_rom/esp32h21/include/esp32h21/rom/rsa_pss.h @@ -0,0 +1,37 @@ +/* + * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#pragma once + +#include +#include +#include + +//TODO: [ESP32H21] IDF-11498 + +#ifdef __cplusplus +extern "C" { +#endif + +#define ETS_SIG_LEN 384 /* Bytes */ +#define ETS_DIGEST_LEN 32 /* SHA-256, bytes */ + +typedef struct { + uint8_t n[384]; /* Public key modulus */ + uint32_t e; /* Public key exponent */ + uint8_t rinv[384]; + uint32_t mdash; +} ets_rsa_pubkey_t; + +bool ets_rsa_pss_verify(const ets_rsa_pubkey_t *key, const uint8_t *sig, const uint8_t *digest, uint8_t *verified_digest); + +void ets_mgf1_sha256(const uint8_t *mgfSeed, size_t seedLen, size_t maskLen, uint8_t *mask); + +bool ets_emsa_pss_verify(const uint8_t *encoded_message, const uint8_t *mhash); + +#ifdef __cplusplus +} +#endif diff --git a/components/esp_rom/esp32h21/include/esp32h21/rom/rtc.h b/components/esp_rom/esp32h21/include/esp32h21/rom/rtc.h new file mode 100644 index 00000000000..4f72fa87e57 --- /dev/null +++ b/components/esp_rom/esp32h21/include/esp32h21/rom/rtc.h @@ -0,0 +1,249 @@ +/* + * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#pragma once + +#include +#include +#include +#include "soc/soc.h" +#include "soc/lp_aon_reg.h" +#include "soc/reset_reasons.h" +#include "esp_assert.h" + +//TODO: [ESP32H21] IDF-11548 + +#ifdef __cplusplus +extern "C" { +#endif + +/** \defgroup rtc_apis, rtc registers and memory related apis + * @brief rtc apis + */ + +/** @addtogroup rtc_apis + * @{ + */ + +/************************************************************************************** + * Note: * + * Some Rtc memory and registers are used, in ROM or in internal library. * + * Please do not use reserved or used rtc memory or registers. * + * * + ************************************************************************************* + * RTC Memory & Store Register usage + ************************************************************************************* + * rtc memory addr type size usage + * 0x50000000 Fast 0x4000 deep sleep entry code + * + ************************************************************************************* + * RTC store registers usage + * RTC_CNTL_STORE0_REG Reserved + * RTC_CNTL_STORE1_REG RTC_SLOW_CLK calibration value + * RTC_CNTL_STORE2_REG Boot time, low word + * RTC_CNTL_STORE3_REG Boot time, high word + * RTC_CNTL_STORE4_REG External XTAL frequency + * RTC_CNTL_STORE5_REG FAST_RTC_MEMORY_LENGTH + * RTC_CNTL_STORE6_REG FAST_RTC_MEMORY_ENTRY + * RTC_CNTL_STORE7_REG FAST_RTC_MEMORY_CRC + ************************************************************************************* + */ + +//TODO: [ESP32H21] IDF-1154, need to check from esp_rom +#define RTC_SLOW_CLK_CAL_REG LP_AON_STORE1_REG +#define RTC_BOOT_TIME_LOW_REG LP_AON_STORE2_REG +#define RTC_BOOT_TIME_HIGH_REG LP_AON_STORE3_REG +#define RTC_XTAL_FREQ_REG LP_AON_STORE4_REG +#define RTC_ENTRY_LENGTH_REG LP_AON_STORE5_REG +#define RTC_ENTRY_ADDR_REG LP_AON_STORE6_REG +#define RTC_MEMORY_CRC_REG LP_AON_STORE7_REG +#define ROM_LOG_CTRL_REG LP_AON_STORE4_REG + +#define RTC_DISABLE_ROM_LOG ((1 << 0) | (1 << 16)) //!< Disable logging from the ROM code. + +typedef enum { + AWAKE = 0, // +#include +#include "ets_sys.h" +#include "ecdsa.h" +#include "rsa_pss.h" +#include "esp_assert.h" + +//TODO: [ESP32H21] IDF-11500 + +#ifdef __cplusplus +extern "C" { +#endif + +#if CONFIG_SECURE_BOOT_V2_ENABLED || CONFIG_SECURE_SIGNED_APPS_NO_SECURE_BOOT + +typedef struct ets_secure_boot_sig_block ets_secure_boot_sig_block_t; +typedef struct ets_secure_boot_signature ets_secure_boot_signature_t; +typedef struct ets_secure_boot_key_digests ets_secure_boot_key_digests_t; + +/* Anti-FI measure: use full words for success/fail, instead of + 0/non-zero +*/ +typedef enum { + SB_SUCCESS = 0x3A5A5AA5, + SB_FAILED = 0x7533885E, +} ets_secure_boot_status_t; + +/* Verify bootloader image (reconfigures cache to map), + with key digests provided as parameters.) + + Can be used to verify secure boot status before enabling + secure boot permanently. + + If stage_load parameter is true, bootloader is copied into staging + buffer in RAM at the same time. + + If result is SB_SUCCESS, the "simple hash" of the bootloader is + copied into verified_hash. +*/ +ets_secure_boot_status_t ets_secure_boot_verify_bootloader_with_keys(uint8_t *verified_hash, const ets_secure_boot_key_digests_t *trusted_keys, bool stage_load); + +/* Read key digests from efuse. Any revoked/missing digests will be + marked as NULL +*/ +ETS_STATUS ets_secure_boot_read_key_digests(ets_secure_boot_key_digests_t *trusted_keys); + +/* Verify supplied signature against supplied digest, using + supplied trusted key digests. + + Doesn't reconfigure cache or any other hardware access except for RSA peripheral. + + If result is SB_SUCCESS, the image_digest value is copied into verified_digest. +*/ +ets_secure_boot_status_t ets_secure_boot_verify_signature(const ets_secure_boot_signature_t *sig, const uint8_t *image_digest, const ets_secure_boot_key_digests_t *trusted_keys, uint8_t *verified_digest); + +/* Revoke a public key digest in efuse. + @param index Digest to revoke. Must be 0, 1 or 2. + */ +void ets_secure_boot_revoke_public_key_digest(int index); + +#define CRC_SIGN_BLOCK_LEN 1196 +#define SIG_BLOCK_PADDING 4096 +#define ETS_SECURE_BOOT_V2_SIGNATURE_MAGIC 0xE7 + +/* Secure Boot V2 signature block + + (Up to 3 in a signature sector are appended to the image) + */ +#if CONFIG_SECURE_SIGNED_APPS_RSA_SCHEME + +struct ets_secure_boot_sig_block { + uint8_t magic_byte; + uint8_t version; + uint8_t _reserved1; + uint8_t _reserved2; + uint8_t image_digest[32]; + ets_rsa_pubkey_t key; + uint8_t signature[384]; + uint32_t block_crc; + uint8_t _padding[16]; +}; + +#elif CONFIG_SECURE_SIGNED_APPS_ECDSA_V2_SCHEME + +struct __attribute((packed)) ets_secure_boot_sig_block { + uint8_t magic_byte; + uint8_t version; + uint8_t _reserved1; + uint8_t _reserved2; + uint8_t image_digest[32]; + struct { + struct { + uint8_t curve_id; /* ETS_ECDSA_CURVE_P192 / ETS_ECDSA_CURVE_P256 */ + uint8_t point[64]; /* X followed by Y (both little-endian), plus zero bytes if P192 */ + } key; + uint8_t signature[64]; /* r followed by s (both little-endian) */ + uint8_t padding[1031]; + } ecdsa; + uint32_t block_crc; /* note: crc covers all bytes in the structure before it, regardless of version field */ + uint8_t _padding[16]; +}; +#endif + +ESP_STATIC_ASSERT(sizeof(ets_secure_boot_sig_block_t) == 1216, "invalid sig block size"); + +#define SECURE_BOOT_NUM_BLOCKS 3 + +/* V2 Secure boot signature sector (up to 3 blocks) */ +struct ets_secure_boot_signature { + ets_secure_boot_sig_block_t block[SECURE_BOOT_NUM_BLOCKS]; + uint8_t _padding[4096 - (sizeof(ets_secure_boot_sig_block_t) * SECURE_BOOT_NUM_BLOCKS)]; +}; + +ESP_STATIC_ASSERT(sizeof(ets_secure_boot_signature_t) == 4096, "invalid sig sector size"); + +#define MAX_KEY_DIGESTS 3 + +struct ets_secure_boot_key_digests { + const void *key_digests[MAX_KEY_DIGESTS]; + bool allow_key_revoke; +}; + +#endif /* CONFIG_SECURE_BOOT_V2_ENABLED || CONFIG_SECURE_SIGNED_APPS_NO_SECURE_BOOT */ + +#ifdef __cplusplus +} +#endif diff --git a/components/esp_rom/esp32h21/include/esp32h21/rom/sha.h b/components/esp_rom/esp32h21/include/esp32h21/rom/sha.h new file mode 100644 index 00000000000..3f074aeb76f --- /dev/null +++ b/components/esp_rom/esp32h21/include/esp32h21/rom/sha.h @@ -0,0 +1,52 @@ +/* + * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#include +#include "ets_sys.h" + +//TODO: [ESP32H21] IDF-11501 + +#ifdef __cplusplus +extern "C" { +#endif + +typedef enum { + SHA1 = 0, + SHA2_224, + SHA2_256, + SHA_TYPE_MAX +} SHA_TYPE; + +typedef struct SHAContext { + bool start; + bool in_hardware; // Is this context currently in peripheral? Needs to be manually cleared if multiple SHAs are interleaved + SHA_TYPE type; + uint32_t state[16]; // For SHA1/SHA224/SHA256, used 8, other used 16 + unsigned char buffer[128]; // For SHA1/SHA224/SHA256, used 64, other used 128 + uint32_t total_bits[4]; +} SHA_CTX; + +void ets_sha_enable(void); + +void ets_sha_disable(void); + +ets_status_t ets_sha_init(SHA_CTX *ctx, SHA_TYPE type); + +ets_status_t ets_sha_starts(SHA_CTX *ctx, uint16_t sha512_t); + +void ets_sha_get_state(SHA_CTX *ctx); + +void ets_sha_process(SHA_CTX *ctx, const unsigned char *input); + +void ets_sha_update(SHA_CTX *ctx, const unsigned char *input, uint32_t input_bytes, bool update_ctx); + +ets_status_t ets_sha_finish(SHA_CTX *ctx, unsigned char *output); + +#ifdef __cplusplus +} +#endif diff --git a/components/esp_rom/esp32h21/include/esp32h21/rom/spi_flash.h b/components/esp_rom/esp32h21/include/esp32h21/rom/spi_flash.h new file mode 100644 index 00000000000..6710d80a7ad --- /dev/null +++ b/components/esp_rom/esp32h21/include/esp32h21/rom/spi_flash.h @@ -0,0 +1,460 @@ +/* + * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#pragma once + +#include +#include +#include "esp_attr.h" +#include "esp_rom_spiflash.h" + +//TODO: [ESP32H21] IDF-11609 + +#ifdef __cplusplus +extern "C" { +#endif + +#define PERIPHS_SPI_FLASH_CMD SPI_MEM_CMD_REG(1) +#define PERIPHS_SPI_FLASH_ADDR SPI_MEM_ADDR_REG(1) +#define PERIPHS_SPI_FLASH_CTRL SPI_MEM_CTRL_REG(1) +#define PERIPHS_SPI_FLASH_CTRL1 SPI_MEM_CTRL1_REG(1) +#define PERIPHS_SPI_FLASH_STATUS SPI_MEM_RD_STATUS_REG(1) +#define PERIPHS_SPI_FLASH_USRREG SPI_MEM_USER_REG(1) +#define PERIPHS_SPI_FLASH_USRREG1 SPI_MEM_USER1_REG(1) +#define PERIPHS_SPI_FLASH_USRREG2 SPI_MEM_USER2_REG(1) +#define PERIPHS_SPI_FLASH_C0 SPI_MEM_W0_REG(1) +#define PERIPHS_SPI_FLASH_C1 SPI_MEM_W1_REG(1) +#define PERIPHS_SPI_FLASH_C2 SPI_MEM_W2_REG(1) +#define PERIPHS_SPI_FLASH_C3 SPI_MEM_W3_REG(1) +#define PERIPHS_SPI_FLASH_C4 SPI_MEM_W4_REG(1) +#define PERIPHS_SPI_FLASH_C5 SPI_MEM_W5_REG(1) +#define PERIPHS_SPI_FLASH_C6 SPI_MEM_W6_REG(1) +#define PERIPHS_SPI_FLASH_C7 SPI_MEM_W7_REG(1) +#define PERIPHS_SPI_FLASH_TX_CRC SPI_MEM_TX_CRC_REG(1) + +#define SPI0_R_QIO_DUMMY_CYCLELEN 5 +#define SPI0_R_QIO_ADDR_BITSLEN 23 +#define SPI0_R_FAST_DUMMY_CYCLELEN 7 +#define SPI0_R_DIO_DUMMY_CYCLELEN 3 +#define SPI0_R_FAST_ADDR_BITSLEN 23 +#define SPI0_R_SIO_ADDR_BITSLEN 23 + +#define SPI1_R_QIO_DUMMY_CYCLELEN 5 +#define SPI1_R_QIO_ADDR_BITSLEN 23 +#define SPI1_R_FAST_DUMMY_CYCLELEN 7 +#define SPI1_R_DIO_DUMMY_CYCLELEN 3 +#define SPI1_R_DIO_ADDR_BITSLEN 23 +#define SPI1_R_FAST_ADDR_BITSLEN 23 +#define SPI1_R_SIO_ADDR_BITSLEN 23 + +#define ESP_ROM_SPIFLASH_W_SIO_ADDR_BITSLEN 23 + +#define ESP_ROM_SPIFLASH_TWO_BYTE_STATUS_EN SPI_MEM_WRSR_2B + +//SPI address register +#define ESP_ROM_SPIFLASH_BYTES_LEN 24 +#define ESP_ROM_SPIFLASH_BUFF_BYTE_WRITE_NUM 32 +#define ESP_ROM_SPIFLASH_BUFF_BYTE_READ_NUM 16 +#define ESP_ROM_SPIFLASH_BUFF_BYTE_READ_BITS 0xf + +typedef void (* spi_flash_func_t)(void); +typedef esp_rom_spiflash_result_t (* spi_flash_op_t)(void); +typedef esp_rom_spiflash_result_t (* spi_flash_erase_t)(uint32_t); +typedef esp_rom_spiflash_result_t (* spi_flash_rd_t)(uint32_t, uint32_t*, int); +typedef esp_rom_spiflash_result_t (* spi_flash_wr_t)(uint32_t, const uint32_t*, int); +typedef esp_rom_spiflash_result_t (* spi_flash_ewr_t)(uint32_t, const void*, uint32_t); +typedef esp_rom_spiflash_result_t (* spi_flash_wren_t)(void*); +typedef esp_rom_spiflash_result_t (* spi_flash_erase_area_t)(uint32_t, uint32_t); + +typedef struct { + uint8_t pp_addr_bit_len; + uint8_t se_addr_bit_len; + uint8_t be_addr_bit_len; + uint8_t rd_addr_bit_len; + uint32_t read_sub_len; + uint32_t write_sub_len; + spi_flash_op_t unlock; + spi_flash_erase_t erase_sector; + spi_flash_erase_t erase_block; + spi_flash_rd_t read; + spi_flash_wr_t write; + spi_flash_ewr_t encrypt_write; + spi_flash_func_t check_sus; + spi_flash_wren_t wren; + spi_flash_op_t wait_idle; + spi_flash_erase_area_t erase_area; +} spiflash_legacy_funcs_t; + +typedef struct { + uint8_t data_length; + uint8_t read_cmd0; + uint8_t read_cmd1; + uint8_t write_cmd; + uint16_t data_mask; + uint16_t data; +} esp_rom_spiflash_common_cmd_t; + +/** + * @brief SPI Read Flash status register. We use CMD 0x05 (RDSR). + * Please do not call this function in SDK. + * + * @param esp_rom_spiflash_chip_t *spi : The information for Flash, which is exported from ld file. + * + * @param uint32_t *status : The pointer to which to return the Flash status value. + * + * @return ESP_ROM_SPIFLASH_RESULT_OK : read OK. + * ESP_ROM_SPIFLASH_RESULT_ERR : read error. + * ESP_ROM_SPIFLASH_RESULT_TIMEOUT : read timeout. + */ +esp_rom_spiflash_result_t esp_rom_spiflash_read_status(esp_rom_spiflash_chip_t *spi, uint32_t *status); + +/** + * @brief SPI Read Flash status register bits 8-15. We use CMD 0x35 (RDSR2). + * Please do not call this function in SDK. + * + * @param esp_rom_spiflash_chip_t *spi : The information for Flash, which is exported from ld file. + * + * @param uint32_t *status : The pointer to which to return the Flash status value. + * + * @return ESP_ROM_SPIFLASH_RESULT_OK : read OK. + * ESP_ROM_SPIFLASH_RESULT_ERR : read error. + * ESP_ROM_SPIFLASH_RESULT_TIMEOUT : read timeout. + */ +esp_rom_spiflash_result_t esp_rom_spiflash_read_statushigh(esp_rom_spiflash_chip_t *spi, uint32_t *status); + +/** + * @brief Write status to Flash status register. + * Please do not call this function in SDK. + * + * @param esp_rom_spiflash_chip_t *spi : The information for Flash, which is exported from ld file. + * + * @param uint32_t status_value : Value to . + * + * @return ESP_ROM_SPIFLASH_RESULT_OK : write OK. + * ESP_ROM_SPIFLASH_RESULT_ERR : write error. + * ESP_ROM_SPIFLASH_RESULT_TIMEOUT : write timeout. + */ +esp_rom_spiflash_result_t esp_rom_spiflash_write_status(esp_rom_spiflash_chip_t *spi, uint32_t status_value); + +/** + * @brief Use a command to Read Flash status register. + * Please do not call this function in SDK. + * + * @param esp_rom_spiflash_chip_t *spi : The information for Flash, which is exported from ld file. + * + * @param uint32_t*status : The pointer to which to return the Flash status value. + * + * @return ESP_ROM_SPIFLASH_RESULT_OK : read OK. + * ESP_ROM_SPIFLASH_RESULT_ERR : read error. + * ESP_ROM_SPIFLASH_RESULT_TIMEOUT : read timeout. + */ +esp_rom_spiflash_result_t esp_rom_spiflash_read_user_cmd(uint32_t *status, uint8_t cmd); + +/** + * @brief Config SPI Flash read mode when init. + * Please do not call this function in SDK. + * + * @param esp_rom_spiflash_read_mode_t mode : QIO/QOUT/DIO/DOUT/FastRD/SlowRD. + * + * This function does not try to set the QIO Enable bit in the status register, caller is responsible for this. + * + * @return ESP_ROM_SPIFLASH_RESULT_OK : config OK. + * ESP_ROM_SPIFLASH_RESULT_ERR : config error. + * ESP_ROM_SPIFLASH_RESULT_TIMEOUT : config timeout. + */ +esp_rom_spiflash_result_t esp_rom_spiflash_config_readmode(esp_rom_spiflash_read_mode_t mode); + +/** + * @brief Config SPI Flash clock divisor. + * Please do not call this function in SDK. + * + * @param uint8_t freqdiv: clock divisor. + * + * @param uint8_t spi: 0 for SPI0, 1 for SPI1. + * + * @return ESP_ROM_SPIFLASH_RESULT_OK : config OK. + * ESP_ROM_SPIFLASH_RESULT_ERR : config error. + * ESP_ROM_SPIFLASH_RESULT_TIMEOUT : config timeout. + */ +esp_rom_spiflash_result_t esp_rom_spiflash_config_clk(uint8_t freqdiv, uint8_t spi); + +/** + * @brief Clear all SR bits except QE bit. + * Please do not call this function in SDK. + * + * @param None. + * + * @return ESP_ROM_SPIFLASH_RESULT_OK : Unlock OK. + * ESP_ROM_SPIFLASH_RESULT_ERR : Unlock error. + * ESP_ROM_SPIFLASH_RESULT_TIMEOUT : Unlock timeout. + */ +esp_rom_spiflash_result_t esp_rom_spiflash_clear_bp(void); + +/** + * @brief Clear all SR bits except QE bit. + * Please do not call this function in SDK. + * + * @param None. + * + * @return ESP_ROM_SPIFLASH_RESULT_OK : Unlock OK. + * ESP_ROM_SPIFLASH_RESULT_ERR : Unlock error. + * ESP_ROM_SPIFLASH_RESULT_TIMEOUT : Unlock timeout. + */ +esp_rom_spiflash_result_t esp_rom_spiflash_unlock(void); + +/** + * @brief Update SPI Flash parameter. + * Please do not call this function in SDK. + * + * @param uint32_t deviceId : Device ID read from SPI, the low 32 bit. + * + * @param uint32_t chip_size : The Flash size. + * + * @param uint32_t block_size : The Flash block size. + * + * @param uint32_t sector_size : The Flash sector size. + * + * @param uint32_t page_size : The Flash page size. + * + * @param uint32_t status_mask : The Mask used when read status from Flash(use single CMD). + * + * @return ESP_ROM_SPIFLASH_RESULT_OK : Update OK. + * ESP_ROM_SPIFLASH_RESULT_ERR : Update error. + * ESP_ROM_SPIFLASH_RESULT_TIMEOUT : Update timeout. + */ +esp_rom_spiflash_result_t esp_rom_spiflash_config_param(uint32_t deviceId, uint32_t chip_size, uint32_t block_size, + uint32_t sector_size, uint32_t page_size, uint32_t status_mask); + +/** + * @brief Erase whole flash chip. + * Please do not call this function in SDK. + * + * @param None + * + * @return ESP_ROM_SPIFLASH_RESULT_OK : Erase OK. + * ESP_ROM_SPIFLASH_RESULT_ERR : Erase error. + * ESP_ROM_SPIFLASH_RESULT_TIMEOUT : Erase timeout. + */ +esp_rom_spiflash_result_t esp_rom_spiflash_erase_chip(void); + +/** + * @brief Erase a 64KB block of flash + * Uses SPI flash command D8H. + * Please do not call this function in SDK. + * + * @param uint32_t block_num : Which block to erase. + * + * @return ESP_ROM_SPIFLASH_RESULT_OK : Erase OK. + * ESP_ROM_SPIFLASH_RESULT_ERR : Erase error. + * ESP_ROM_SPIFLASH_RESULT_TIMEOUT : Erase timeout. + */ +esp_rom_spiflash_result_t esp_rom_spiflash_erase_block(uint32_t block_num); + +/** + * @brief Erase a sector of flash. + * Uses SPI flash command 20H. + * Please do not call this function in SDK. + * + * @param uint32_t sector_num : Which sector to erase. + * + * @return ESP_ROM_SPIFLASH_RESULT_OK : Erase OK. + * ESP_ROM_SPIFLASH_RESULT_ERR : Erase error. + * ESP_ROM_SPIFLASH_RESULT_TIMEOUT : Erase timeout. + */ +esp_rom_spiflash_result_t esp_rom_spiflash_erase_sector(uint32_t sector_num); + +/** + * @brief Erase some sectors. + * Please do not call this function in SDK. + * + * @param uint32_t start_addr : Start addr to erase, should be sector aligned. + * + * @param uint32_t area_len : Length to erase, should be sector aligned. + * + * @return ESP_ROM_SPIFLASH_RESULT_OK : Erase OK. + * ESP_ROM_SPIFLASH_RESULT_ERR : Erase error. + * ESP_ROM_SPIFLASH_RESULT_TIMEOUT : Erase timeout. + */ +esp_rom_spiflash_result_t esp_rom_spiflash_erase_area(uint32_t start_addr, uint32_t area_len); + +/** + * @brief Write Data to Flash, you should Erase it yourself if need. + * Please do not call this function in SDK. + * + * @param uint32_t dest_addr : Address to write, should be 4 bytes aligned. + * + * @param const uint32_t *src : The pointer to data which is to write. + * + * @param uint32_t len : Length to write, should be 4 bytes aligned. + * + * @return ESP_ROM_SPIFLASH_RESULT_OK : Write OK. + * ESP_ROM_SPIFLASH_RESULT_ERR : Write error. + * ESP_ROM_SPIFLASH_RESULT_TIMEOUT : Write timeout. + */ +esp_rom_spiflash_result_t esp_rom_spiflash_write(uint32_t dest_addr, const uint32_t *src, int32_t len); + +/** + * @brief Read Data from Flash, you should Erase it yourself if need. + * Please do not call this function in SDK. + * + * @param uint32_t src_addr : Address to read, should be 4 bytes aligned. + * + * @param uint32_t *dest : The buf to read the data. + * + * @param uint32_t len : Length to read, should be 4 bytes aligned. + * + * @return ESP_ROM_SPIFLASH_RESULT_OK : Read OK. + * ESP_ROM_SPIFLASH_RESULT_ERR : Read error. + * ESP_ROM_SPIFLASH_RESULT_TIMEOUT : Read timeout. + */ +esp_rom_spiflash_result_t esp_rom_spiflash_read(uint32_t src_addr, uint32_t *dest, int32_t len); + +/** + * @brief SPI1 go into encrypto mode. + * Please do not call this function in SDK. + * + * @param None + * + * @return None + */ +void esp_rom_spiflash_write_encrypted_enable(void); + +/** + * @brief SPI1 go out of encrypto mode. + * Please do not call this function in SDK. + * + * @param None + * + * @return None + */ +void esp_rom_spiflash_write_encrypted_disable(void); + +/** + * @brief Write data to flash with transparent encryption. + * @note Sectors to be written should already be erased. + * + * @note Please do not call this function in SDK. + * + * @param uint32_t flash_addr : Address to write, should be 32 byte aligned. + * + * @param uint32_t *data : The pointer to data to write. Note, this pointer must + * be 32 bit aligned and the content of the data will be + * modified by the encryption function. + * + * @param uint32_t len : Length to write, should be 32 bytes aligned. + * + * @return ESP_ROM_SPIFLASH_RESULT_OK : Data written successfully. + * ESP_ROM_SPIFLASH_RESULT_ERR : Encryption write error. + * ESP_ROM_SPIFLASH_RESULT_TIMEOUT : Encrypto write timeout. + */ +esp_rom_spiflash_result_t esp_rom_spiflash_write_encrypted(uint32_t flash_addr, uint32_t *data, uint32_t len); + + +/** @brief Wait until SPI flash write operation is complete + * + * @note Please do not call this function in SDK. + * + * Reads the Write In Progress bit of the SPI flash status register, + * repeats until this bit is zero (indicating write complete). + * + * @return ESP_ROM_SPIFLASH_RESULT_OK : Write is complete + * ESP_ROM_SPIFLASH_RESULT_ERR : Error while reading status. + */ +esp_rom_spiflash_result_t esp_rom_spiflash_wait_idle(esp_rom_spiflash_chip_t *spi); + + +/** @brief Enable Quad I/O pin functions + * + * @note Please do not call this function in SDK. + * + * Sets the HD & WP pin functions for Quad I/O modes, based on the + * efuse SPI pin configuration. + * + * @param wp_gpio_num - Number of the WP pin to reconfigure for quad I/O. + * + * @param spiconfig - Pin configuration, as returned from ets_efuse_get_spiconfig(). + * - If this parameter is 0, default SPI pins are used and wp_gpio_num parameter is ignored. + * - If this parameter is 1, default HSPI pins are used and wp_gpio_num parameter is ignored. + * - For other values, this parameter encodes the HD pin number and also the CLK pin number. CLK pin selection is used + * to determine if HSPI or SPI peripheral will be used (use HSPI if CLK pin is the HSPI clock pin, otherwise use SPI). + * Both HD & WP pins are configured via GPIO matrix to map to the selected peripheral. + */ +void esp_rom_spiflash_select_qio_pins(uint8_t wp_gpio_num, uint32_t spiconfig); + +/** + * @brief Clear WEL bit unconditionally. + * + * @return always ESP_ROM_SPIFLASH_RESULT_OK + */ +esp_rom_spiflash_result_t esp_rom_spiflash_write_disable(void); + +/** + * @brief Set WREN bit. + * + * @param esp_rom_spiflash_chip_t *spi : The information for Flash, which is exported from ld file. + * + * @return always ESP_ROM_SPIFLASH_RESULT_OK + */ +esp_rom_spiflash_result_t esp_rom_spiflash_write_enable(esp_rom_spiflash_chip_t *spi); + +/** + * @brief Fix the bug in SPI hardware communication with Flash/Ext-SRAM in High Speed. + * Please do not call this function in SDK. + * + * @param uint8_t spi: 0 for SPI0(Cache Access), 1 for SPI1(Flash read/write). + * + * @param uint8_t freqdiv: Pll is 80M, 4 for 20M, 3 for 26.7M, 2 for 40M, 1 for 80M. + * + * @return None + */ +void esp_rom_spiflash_fix_dummylen(uint8_t spi, uint8_t freqdiv); + +/** + * @brief Set SPI Flash pad drivers. + * Please do not call this function in SDK. + * + * @param uint8_t wp_gpio_num: WP gpio number. + * + * @param uint32_t ishspi: 0 for spi, 1 for hspi, flash pad decided by strapping + * else, bit[5:0] spiclk, bit[11:6] spiq, bit[17:12] spid, bit[23:18] spics0, bit[29:24] spihd + * + * @param uint8_t *drvs: drvs[0]-bit[3:0] for cpiclk, bit[7:4] for spiq, drvs[1]-bit[3:0] for spid, drvs[1]-bit[7:4] for spid + * drvs[2]-bit[3:0] for spihd, drvs[2]-bit[7:4] for spiwp. + * Values usually read from flash by rom code, function usually called by rom code. + * if value with bit(3) set, the value is valid, bit[2:0] is the real value. + * + * @return None + */ +void esp_rom_spiflash_set_drvs(uint8_t wp_gpio_num, uint32_t ishspi, uint8_t *drvs); + +/** + * @brief Select SPI Flash function for pads. + * Please do not call this function in SDK. + * + * @param uint32_t ishspi: 0 for spi, 1 for hspi, flash pad decided by strapping + * else, bit[5:0] spiclk, bit[11:6] spiq, bit[17:12] spid, bit[23:18] spics0, bit[29:24] spihd + * + * @return None + */ +void esp_rom_spiflash_select_padsfunc(uint32_t ishspi); + +/** + * @brief Send CommonCmd to Flash so that is can go into QIO mode, some Flash use different CMD. + * Please do not call this function in SDK. + * + * @param esp_rom_spiflash_common_cmd_t *cmd : A struct to show the action of a command. + * + * @return uint16_t 0 : do not send command any more. + * 1 : go to the next command. + * n > 1 : skip (n - 1) commands. + */ +uint16_t esp_rom_spiflash_common_cmd(esp_rom_spiflash_common_cmd_t *cmd); + +extern const spiflash_legacy_funcs_t *rom_spiflash_legacy_funcs; + +#ifdef __cplusplus +} +#endif diff --git a/components/esp_rom/esp32h21/include/esp32h21/rom/uart.h b/components/esp_rom/esp32h21/include/esp32h21/rom/uart.h new file mode 100644 index 00000000000..0d166cf8725 --- /dev/null +++ b/components/esp_rom/esp32h21/include/esp32h21/rom/uart.h @@ -0,0 +1,349 @@ +/* + * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#pragma once + +#include "esp_types.h" +#include "esp_attr.h" +#include "ets_sys.h" +#include "soc/soc.h" +#include "soc/uart_reg.h" + +#ifdef __cplusplus +extern "C" { +#endif + +//TODO: [ESP32H21] IDF-11618 + +/** \defgroup uart_apis, uart configuration and communication related apis + * @brief uart apis + */ + +/** @addtogroup uart_apis + * @{ + */ + +//uart int enable register ctrl bits +#define UART_RCV_INTEN BIT0 +#define UART_TRX_INTEN BIT1 +#define UART_LINE_STATUS_INTEN BIT2 + +//uart int identification ctrl bits +#define UART_INT_FLAG_MASK 0x0E + +//uart fifo ctrl bits +#define UART_CLR_RCV_FIFO BIT1 +#define UART_CLR_TRX_FIFO BIT2 +#define UART_RCVFIFO_TRG_LVL_BITS BIT6 + +//uart line control bits +#define UART_DIV_LATCH_ACCESS_BIT BIT7 + +//uart line status bits +#define UART_RCV_DATA_RDY_FLAG BIT0 +#define UART_RCV_OVER_FLOW_FLAG BIT1 +#define UART_RCV_PARITY_ERR_FLAG BIT2 +#define UART_RCV_FRAME_ERR_FLAG BIT3 +#define UART_BRK_INT_FLAG BIT4 +#define UART_TRX_FIFO_EMPTY_FLAG BIT5 +#define UART_TRX_ALL_EMPTY_FLAG BIT6 // include fifo and shift reg +#define UART_RCV_ERR_FLAG BIT7 + +//send and receive message frame head +#define FRAME_FLAG 0x7E + +typedef enum { + UART_LINE_STATUS_INT_FLAG = 0x06, + UART_RCV_FIFO_INT_FLAG = 0x04, + UART_RCV_TMOUT_INT_FLAG = 0x0C, + UART_TXBUFF_EMPTY_INT_FLAG = 0x02 +} UartIntType; //consider bit0 for int_flag + +typedef enum { + RCV_ONE_BYTE = 0x0, + RCV_FOUR_BYTE = 0x1, + RCV_EIGHT_BYTE = 0x2, + RCV_FOURTEEN_BYTE = 0x3 +} UartRcvFifoTrgLvl; + +typedef enum { + FIVE_BITS = 0x0, + SIX_BITS = 0x1, + SEVEN_BITS = 0x2, + EIGHT_BITS = 0x3 +} UartBitsNum4Char; + +typedef enum { + ONE_STOP_BIT = 1, + ONE_HALF_STOP_BIT = 2, + TWO_STOP_BIT = 3 +} UartStopBitsNum; + +typedef enum { + NONE_BITS = 0, + ODD_BITS = 2, + EVEN_BITS = 3 + +} UartParityMode; + +typedef enum { + STICK_PARITY_DIS = 0, + STICK_PARITY_EN = 2 +} UartExistParity; + +typedef enum { + BIT_RATE_9600 = 9600, + BIT_RATE_19200 = 19200, + BIT_RATE_38400 = 38400, + BIT_RATE_57600 = 57600, + BIT_RATE_115200 = 115200, + BIT_RATE_230400 = 230400, + BIT_RATE_460800 = 460800, + BIT_RATE_921600 = 921600 +} UartBautRate; + +typedef enum { + NONE_CTRL, + HARDWARE_CTRL, + XON_XOFF_CTRL +} UartFlowCtrl; + +typedef enum { + EMPTY, + UNDER_WRITE, + WRITE_OVER +} RcvMsgBuffState; + +typedef struct { + uint8_t *pRcvMsgBuff; + uint8_t *pWritePos; + uint8_t *pReadPos; + uint8_t TrigLvl; + RcvMsgBuffState BuffState; +} RcvMsgBuff; + +typedef struct { + uint32_t TrxBuffSize; + uint8_t *pTrxBuff; +} TrxMsgBuff; + +typedef enum { + BAUD_RATE_DET, + WAIT_SYNC_FRM, + SRCH_MSG_HEAD, + RCV_MSG_BODY, + RCV_ESC_CHAR, +} RcvMsgState; + +typedef struct { + UartBautRate baut_rate; + UartBitsNum4Char data_bits; + UartExistParity exist_parity; + UartParityMode parity; // chip size in byte + UartStopBitsNum stop_bits; + UartFlowCtrl flow_ctrl; + uint8_t buff_uart_no; //indicate which uart use tx/rx buffer + RcvMsgBuff rcv_buff; +// TrxMsgBuff trx_buff; + RcvMsgState rcv_state; + int received; +} UartDevice; + +/** + * @brief Init uart device struct value and reset uart0/uart1 rx. + * Please do not call this function in SDK. + * + * @param rxBuffer, must be a pointer to RX_BUFF_SIZE bytes or NULL + * + * @return None + */ +void uartAttach(void *rxBuffer); + +/** + * @brief Init uart0 or uart1 for UART download booting mode. + * Please do not call this function in SDK. + * + * @param uint8_t uart_no : 0 for UART0, else for UART1. + * + * @param uint32_t clock : clock used by uart module, to adjust baudrate. + * + * @return None + */ +void Uart_Init(uint8_t uart_no, uint32_t clock); + +/** + * @brief Modify uart baudrate. + * This function will reset RX/TX fifo for uart. + * + * @param uint8_t uart_no : 0 for UART0, 1 for UART1. + * + * @param uint32_t DivLatchValue : (clock << 4)/baudrate. + * + * @return None + */ +void uart_div_modify(uint8_t uart_no, uint32_t DivLatchValue); + +/** + * @brief Switch printf channel of uart_tx_one_char. + * Please do not call this function when printf. + * + * @param uint8_t uart_no : 0 for UART0, 1 for UART1. + * + * @return None + */ +void uart_tx_switch(uint8_t uart_no); + +/** + * @brief Output a char to printf channel, wait until fifo not full. + * + * @param None + * + * @return OK. + */ +ETS_STATUS uart_tx_one_char(uint8_t TxChar); + +/** + * @brief Output a char to message exchange channel, wait until fifo not full. + * Please do not call this function in SDK. + * + * @param None + * + * @return OK. + */ +ETS_STATUS uart_tx_one_char2(uint8_t TxChar); + +/** + * @brief Wait until uart tx full empty. + * + * @param uint8_t uart_no : 0 for UART0, 1 for UART1. + * + * @return None. + */ +void uart_tx_flush(uint8_t uart_no); + +/** + * @brief Wait until uart tx full empty and the last char send ok. + * + * @param uart_no : 0 for UART0, 1 for UART1 + * + * The function defined in ROM code has a bug, so we define the correct version + * here for compatibility. + */ +void uart_tx_wait_idle(uint8_t uart_no); + +/** + * @brief Get an input char from message channel. + * Please do not call this function in SDK. + * + * @param uint8_t *pRxChar : the pointer to store the char. + * + * @return OK for successful. + * FAIL for failed. + */ +ETS_STATUS uart_rx_one_char(uint8_t *pRxChar); + +/** + * @brief Get an input char from message channel, wait until successful. + * Please do not call this function in SDK. + * + * @param None + * + * @return char : input char value. + */ +char uart_rx_one_char_block(void); + +/** + * @brief Get an input string line from message channel. + * Please do not call this function in SDK. + * + * @param uint8_t *pString : the pointer to store the string. + * + * @param uint8_t MaxStrlen : the max string length, include '\0'. + * + * @return OK. + */ +ETS_STATUS UartRxString(uint8_t *pString, uint8_t MaxStrlen); + +/** + * @brief Process uart received information in the interrupt handler. + * Please do not call this function in SDK. + * + * @param void *para : the message receive buffer. + * + * @return None + */ +void uart_rx_intr_handler(void *para); + +/** + * @brief Get an char from receive buffer. + * Please do not call this function in SDK. + * + * @param RcvMsgBuff *pRxBuff : the pointer to the struct that include receive buffer. + * + * @param uint8_t *pRxByte : the pointer to store the char. + * + * @return OK for successful. + * FAIL for failed. + */ +ETS_STATUS uart_rx_readbuff( RcvMsgBuff *pRxBuff, uint8_t *pRxByte); + +/** + * @brief Get all chars from receive buffer. + * Please do not call this function in SDK. + * + * @param uint8_t *pCmdLn : the pointer to store the string. + * + * @return OK for successful. + * FAIL for failed. + */ +ETS_STATUS UartGetCmdLn(uint8_t *pCmdLn); + +/** + * @brief Get uart configuration struct. + * Please do not call this function in SDK. + * + * @param None + * + * @return UartDevice * : uart configuration struct pointer. + */ +UartDevice *GetUartDevice(void); + +/** + * @brief Send an packet to download tool, with SLIP escaping. + * Please do not call this function in SDK. + * + * @param uint8_t *p : the pointer to output string. + * + * @param int len : the string length. + * + * @return None. + */ +void send_packet(uint8_t *p, int len); + +/** + * @brief Receive an packet from download tool, with SLIP escaping. + * Please do not call this function in SDK. + * + * @param uint8_t *p : the pointer to input string. + * + * @param int len : If string length > len, the string will be truncated. + * + * @param uint8_t is_sync : 0, only one UART module; + * 1, two UART modules. + * + * @return int : the length of the string. + */ +int recv_packet(uint8_t *p, int len, uint8_t is_sync); + +extern UartDevice UartDev; + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif diff --git a/components/esp_rom/esp32h21/ld/esp32h21.rom.api.ld b/components/esp_rom/esp32h21/ld/esp32h21.rom.api.ld new file mode 100644 index 00000000000..31fced02bc2 --- /dev/null +++ b/components/esp_rom/esp32h21/ld/esp32h21.rom.api.ld @@ -0,0 +1,63 @@ +/* + * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +PROVIDE ( esp_rom_crc32_le = crc32_le ); +PROVIDE ( esp_rom_crc16_le = crc16_le ); +PROVIDE ( esp_rom_crc8_le = crc8_le ); +PROVIDE ( esp_rom_crc32_be = crc32_be ); +PROVIDE ( esp_rom_crc16_be = crc16_be ); +PROVIDE ( esp_rom_crc8_be = crc8_be ); + +PROVIDE ( esp_rom_gpio_pad_select_gpio = gpio_pad_select_gpio ); +PROVIDE ( esp_rom_gpio_pad_pullup_only = gpio_pad_pullup ); +PROVIDE ( esp_rom_gpio_pad_set_drv = gpio_pad_set_drv ); +PROVIDE ( esp_rom_gpio_pad_unhold = gpio_pad_unhold ); +PROVIDE ( esp_rom_gpio_connect_in_signal = gpio_matrix_in ); +PROVIDE ( esp_rom_gpio_connect_out_signal = gpio_matrix_out ); + +PROVIDE ( esp_rom_efuse_mac_address_crc8 = esp_crc8 ); +PROVIDE ( esp_rom_efuse_is_secure_boot_enabled = ets_efuse_secure_boot_enabled ); + +PROVIDE ( esp_rom_uart_flush_tx = uart_tx_flush ); +PROVIDE ( esp_rom_uart_tx_one_char = uart_tx_one_char2 ); +PROVIDE ( esp_rom_uart_tx_wait_idle = uart_tx_wait_idle ); +PROVIDE ( esp_rom_uart_rx_one_char = uart_rx_one_char ); +PROVIDE ( esp_rom_uart_rx_string = UartRxString ); +PROVIDE ( esp_rom_uart_set_as_console = uart_tx_switch ); +PROVIDE ( esp_rom_uart_putc = ets_write_char_uart ); + +PROVIDE ( esp_rom_output_flush_tx = uart_tx_flush ); +PROVIDE ( esp_rom_output_tx_one_char = uart_tx_one_char ); +PROVIDE ( esp_rom_output_tx_wait_idle = uart_tx_wait_idle ); +PROVIDE ( esp_rom_output_rx_one_char = uart_rx_one_char ); +PROVIDE ( esp_rom_output_rx_string = UartRxString ); +PROVIDE ( esp_rom_output_set_as_console = uart_tx_switch ); +PROVIDE ( esp_rom_output_putc = ets_write_char_uart ); + +PROVIDE ( esp_rom_md5_init = MD5Init ); +PROVIDE ( esp_rom_md5_update = MD5Update ); +PROVIDE ( esp_rom_md5_final = MD5Final ); + +PROVIDE ( esp_rom_software_reset_system = software_reset ); +PROVIDE ( esp_rom_software_reset_cpu = software_reset_cpu ); + +PROVIDE ( esp_rom_printf = ets_printf ); +PROVIDE ( esp_rom_install_uart_printf = ets_install_uart_printf ); +PROVIDE ( esp_rom_delay_us = ets_delay_us ); +PROVIDE ( esp_rom_get_reset_reason = rtc_get_reset_reason ); +PROVIDE ( esp_rom_route_intr_matrix = intr_matrix_set ); +PROVIDE ( esp_rom_get_cpu_ticks_per_us = ets_get_cpu_frequency ); +PROVIDE ( esp_rom_set_cpu_ticks_per_us = ets_update_cpu_frequency ); + +PROVIDE ( esp_rom_spiflash_attach = spi_flash_attach ); +PROVIDE ( esp_rom_spiflash_clear_bp = esp_rom_spiflash_unlock ); +PROVIDE ( esp_rom_spiflash_write_enable = SPI_write_enable ); +PROVIDE ( esp_rom_spiflash_erase_area = SPIEraseArea ); + +PROVIDE ( esp_rom_spiflash_fix_dummylen = spi_dummy_len_fix ); +PROVIDE ( esp_rom_spiflash_set_drvs = SetSpiDrvs); +PROVIDE ( esp_rom_spiflash_select_padsfunc = SelectSpiFunction ); +PROVIDE ( esp_rom_spiflash_common_cmd = SPI_Common_Command ); diff --git a/components/esp_rom/esp32h21/ld/esp32h21.rom.heap.ld b/components/esp_rom/esp32h21/ld/esp32h21.rom.heap.ld new file mode 100644 index 00000000000..57205290d97 --- /dev/null +++ b/components/esp_rom/esp32h21/ld/esp32h21.rom.heap.ld @@ -0,0 +1,79 @@ +/* + * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +/* ROM function interface esp32h21.rom.heap.ld for esp32h21 + * + * + * Generated from ./target/esp32h21/interface-esp32h21.yml md5sum dee73289acb146ae14dd9544143527f0 + * + * Compatible with ROM where ECO version equal or greater to 0. + * + * THIS FILE WAS AUTOMATICALLY GENERATED. DO NOT EDIT. + */ + +/*************************************** + Group heap + ***************************************/ + +/* Functions */ +tlsf_create = 0x400003f4; +tlsf_create_with_pool = 0x400003f8; +tlsf_get_pool = 0x400003fc; +tlsf_add_pool = 0x40000400; +tlsf_remove_pool = 0x40000404; +tlsf_malloc = 0x40000408; +tlsf_memalign = 0x4000040c; +tlsf_memalign_offs = 0x40000410; +tlsf_malloc_addr = 0x40000414; +tlsf_realloc = 0x40000418; +tlsf_free = 0x4000041c; +tlsf_block_size = 0x40000420; +tlsf_size = 0x40000424; +tlsf_pool_overhead = 0x40000428; +tlsf_alloc_overhead = 0x4000042c; +tlsf_walk_pool = 0x40000430; +tlsf_check = 0x40000434; +tlsf_check_pool = 0x40000438; +tlsf_poison_fill_pfunc_set = 0x4000043c; +tlsf_poison_check_pfunc_set = 0x40000440; +multi_heap_get_block_address_impl = 0x40000444; +multi_heap_get_allocated_size_impl = 0x40000448; +multi_heap_register_impl = 0x4000044c; +multi_heap_set_lock = 0x40000450; +multi_heap_os_funcs_init = 0x40000454; +multi_heap_internal_lock = 0x40000458; +multi_heap_internal_unlock = 0x4000045c; +multi_heap_get_first_block = 0x40000460; +multi_heap_get_next_block = 0x40000464; +multi_heap_is_free = 0x40000468; +multi_heap_malloc_impl = 0x4000046c; +multi_heap_free_impl = 0x40000470; +multi_heap_realloc_impl = 0x40000474; +multi_heap_aligned_alloc_impl_offs = 0x40000478; +multi_heap_aligned_alloc_impl = 0x4000047c; +multi_heap_check = 0x40000480; +multi_heap_dump = 0x40000484; +multi_heap_free_size_impl = 0x40000488; +multi_heap_minimum_free_size_impl = 0x4000048c; +multi_heap_get_info_impl = 0x40000490; +/* Data (.data, .bss, .rodata) */ +heap_tlsf_table_ptr = 0x4084ffd8; + +PROVIDE (multi_heap_malloc = multi_heap_malloc_impl); +PROVIDE (multi_heap_free = multi_heap_free_impl); +PROVIDE (multi_heap_realloc = multi_heap_realloc_impl); +PROVIDE (multi_heap_get_allocated_size = multi_heap_get_allocated_size_impl); +PROVIDE (multi_heap_register = multi_heap_register_impl); +PROVIDE (multi_heap_get_info = multi_heap_get_info_impl); +PROVIDE (multi_heap_free_size = multi_heap_free_size_impl); +PROVIDE (multi_heap_minimum_free_size = multi_heap_minimum_free_size_impl); +PROVIDE (multi_heap_get_block_address = multi_heap_get_block_address_impl); +PROVIDE (multi_heap_aligned_alloc = multi_heap_aligned_alloc_impl); +PROVIDE (multi_heap_aligned_free = multi_heap_aligned_free_impl); +PROVIDE (multi_heap_check = multi_heap_check); +PROVIDE (multi_heap_set_lock = multi_heap_set_lock); +PROVIDE (multi_heap_os_funcs_init = multi_heap_mutex_init); +PROVIDE (multi_heap_internal_lock = multi_heap_internal_lock); +PROVIDE (multi_heap_internal_unlock = multi_heap_internal_unlock); diff --git a/components/esp_rom/esp32h21/ld/esp32h21.rom.ld b/components/esp_rom/esp32h21/ld/esp32h21.rom.ld new file mode 100644 index 00000000000..78ef116c3d1 --- /dev/null +++ b/components/esp_rom/esp32h21/ld/esp32h21.rom.ld @@ -0,0 +1,381 @@ +/* + * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +/* ROM function interface esp32h21.rom.ld for esp32h21 + * + * + * Generated from ./target/esp32h21/interface-esp32h21.yml md5sum dee73289acb146ae14dd9544143527f0 + * + * Compatible with ROM where ECO version equal or greater to 0. + * + * THIS FILE WAS AUTOMATICALLY GENERATED. DO NOT EDIT. + */ + +/*************************************** + Group common + ***************************************/ + +/* Functions */ +rtc_get_reset_reason = 0x40000018; +analog_super_wdt_reset_happened = 0x4000001c; +rtc_get_wakeup_cause = 0x40000020; +rtc_unhold_all_pads = 0x40000024; +ets_printf = 0x40000028; +ets_install_putc1 = 0x4000002c; +ets_install_putc2 = 0x40000030; +ets_install_uart_printf = 0x40000034; +ets_install_usb_printf = 0x40000038; +ets_get_printf_channel = 0x4000003c; +ets_delay_us = 0x40000040; +ets_get_cpu_frequency = 0x40000044; +ets_update_cpu_frequency = 0x40000048; +ets_install_lock = 0x4000004c; +UartRxString = 0x40000050; +UartGetCmdLn = 0x40000054; +uart_tx_one_char = 0x40000058; +uart_tx_one_char2 = 0x4000005c; +uart_rx_one_char = 0x40000060; +uart_rx_one_char_block = 0x40000064; +uart_rx_intr_handler = 0x40000068; +uart_rx_readbuff = 0x4000006c; +uartAttach = 0x40000070; +uart_tx_flush = 0x40000074; +uart_tx_wait_idle = 0x40000078; +uart_div_modify = 0x4000007c; +ets_write_char_uart = 0x40000080; +uart_tx_switch = 0x40000084; +roundup2 = 0x40000088; +multofup = 0x4000008c; +software_reset = 0x40000090; +software_reset_cpu = 0x40000094; +ets_clk_assist_debug_clock_enable = 0x40000098; +clear_super_wdt_reset_flag = 0x4000009c; +disable_default_watchdog = 0x400000a0; +esp_rom_set_rtc_wake_addr = 0x400000a4; +esp_rom_get_rtc_wake_addr = 0x400000a8; +send_packet = 0x400000ac; +recv_packet = 0x400000b0; +GetUartDevice = 0x400000b4; +UartDwnLdProc = 0x400000b8; +GetSecurityInfoProc = 0x400000bc; +Uart_Init = 0x400000c0; +ets_set_user_start = 0x400000c4; +/* Data (.data, .bss, .rodata) */ +ets_rom_layout_p = 0x4001fffc; +ets_ops_table_ptr = 0x4084fff8; +g_saved_pc = 0x4084fffc; + + +/*************************************** + Group miniz + ***************************************/ + +/* Functions */ +mz_adler32 = 0x400000c8; +mz_free = 0x400000cc; +tdefl_compress = 0x400000d0; +tdefl_compress_buffer = 0x400000d4; +tdefl_compress_mem_to_heap = 0x400000d8; +tdefl_compress_mem_to_mem = 0x400000dc; +tdefl_compress_mem_to_output = 0x400000e0; +tdefl_get_adler32 = 0x400000e4; +tdefl_get_prev_return_status = 0x400000e8; +tdefl_init = 0x400000ec; +tdefl_write_image_to_png_file_in_memory = 0x400000f0; +tdefl_write_image_to_png_file_in_memory_ex = 0x400000f4; +tinfl_decompress = 0x400000f8; +tinfl_decompress_mem_to_callback = 0x400000fc; +tinfl_decompress_mem_to_heap = 0x40000100; +tinfl_decompress_mem_to_mem = 0x40000104; + + +/*************************************** + Group spiflash_legacy + ***************************************/ + +/* Functions */ +esp_rom_spiflash_wait_idle = 0x40000108; +esp_rom_spiflash_write_encrypted = 0x4000010c; +esp_rom_spiflash_write_encrypted_dest = 0x40000110; +esp_rom_spiflash_write_encrypted_enable = 0x40000114; +esp_rom_spiflash_write_encrypted_disable = 0x40000118; +esp_rom_spiflash_erase_chip = 0x4000011c; +_esp_rom_spiflash_erase_sector = 0x40000120; +_esp_rom_spiflash_erase_block = 0x40000124; +_esp_rom_spiflash_write = 0x40000128; +_esp_rom_spiflash_read = 0x4000012c; +_esp_rom_spiflash_unlock = 0x40000130; +_SPIEraseArea = 0x40000134; +_SPI_write_enable = 0x40000138; +esp_rom_spiflash_erase_sector = 0x4000013c; +esp_rom_spiflash_erase_block = 0x40000140; +esp_rom_spiflash_write = 0x40000144; +esp_rom_spiflash_read = 0x40000148; +esp_rom_spiflash_unlock = 0x4000014c; +SPIEraseArea = 0x40000150; +SPI_write_enable = 0x40000154; +esp_rom_spiflash_config_param = 0x40000158; +esp_rom_spiflash_read_user_cmd = 0x4000015c; +esp_rom_spiflash_select_qio_pins = 0x40000160; +esp_rom_spi_flash_auto_sus_res = 0x40000164; +esp_rom_spi_flash_send_resume = 0x40000168; +esp_rom_spi_flash_update_id = 0x4000016c; +esp_rom_spiflash_config_clk = 0x40000170; +esp_rom_spiflash_config_readmode = 0x40000174; +esp_rom_spiflash_read_status = 0x40000178; +esp_rom_spiflash_read_statushigh = 0x4000017c; +esp_rom_spiflash_write_status = 0x40000180; +spi_cache_mode_switch = 0x40000184; +spi_common_set_dummy_output = 0x40000188; +spi_common_set_flash_cs_timing = 0x4000018c; +esp_rom_spi_set_address_bit_len = 0x40000190; +SPILock = 0x40000194; +SPIMasterReadModeCnfig = 0x40000198; +SPI_Common_Command = 0x4000019c; +SPI_WakeUp = 0x400001a0; +SPI_block_erase = 0x400001a4; +SPI_chip_erase = 0x400001a8; +SPI_init = 0x400001ac; +SPI_page_program = 0x400001b0; +SPI_read_data = 0x400001b4; +SPI_sector_erase = 0x400001b8; +SelectSpiFunction = 0x400001bc; +SetSpiDrvs = 0x400001c0; +Wait_SPI_Idle = 0x400001c4; +spi_dummy_len_fix = 0x400001c8; +Disable_QMode = 0x400001cc; +Enable_QMode = 0x400001d0; +spi_flash_attach = 0x400001d4; +spi_flash_get_chip_size = 0x400001d8; +spi_flash_guard_set = 0x400001dc; +spi_flash_guard_get = 0x400001e0; +spi_flash_read_encrypted = 0x400001e4; +/* Data (.data, .bss, .rodata) */ +rom_spiflash_legacy_funcs = 0x4084fff0; +rom_spiflash_legacy_data = 0x4084ffec; +g_flash_guard_ops = 0x4084fff4; + + +/*************************************** + Group cache + ***************************************/ + +/* Functions */ +Cache_Get_ICache_Line_Size = 0x400005f4; +Cache_Get_Mode = 0x400005f8; +Cache_Address_Through_Cache = 0x400005fc; +ROM_Boot_Cache_Init = 0x40000600; +MMU_Set_Page_Mode = 0x40000604; +MMU_Get_Page_Mode = 0x40000608; +Cache_Invalidate_ICache_Items = 0x4000060c; +Cache_Op_Addr = 0x40000610; +Cache_Invalidate_Addr = 0x40000614; +Cache_Invalidate_ICache_All = 0x40000618; +Cache_Mask_All = 0x4000061c; +Cache_UnMask_Dram0 = 0x40000620; +Cache_Suspend_ICache_Autoload = 0x40000624; +Cache_Resume_ICache_Autoload = 0x40000628; +Cache_Start_ICache_Preload = 0x4000062c; +Cache_ICache_Preload_Done = 0x40000630; +Cache_End_ICache_Preload = 0x40000634; +Cache_Config_ICache_Autoload = 0x40000638; +Cache_Enable_ICache_Autoload = 0x4000063c; +Cache_Disable_ICache_Autoload = 0x40000640; +Cache_Enable_ICache_PreLock = 0x40000644; +Cache_Disable_ICache_PreLock = 0x40000648; +Cache_Lock_ICache_Items = 0x4000064c; +Cache_Unlock_ICache_Items = 0x40000650; +Cache_Lock_Addr = 0x40000654; +Cache_Unlock_Addr = 0x40000658; +Cache_Disable_ICache = 0x4000065c; +Cache_Enable_ICache = 0x40000660; +Cache_Suspend_ICache = 0x40000664; +Cache_Resume_ICache = 0x40000668; +Cache_Freeze_ICache_Enable = 0x4000066c; +Cache_Freeze_ICache_Disable = 0x40000670; +Cache_Set_IDROM_MMU_Size = 0x40000674; +Cache_Get_IROM_MMU_End = 0x40000678; +Cache_Get_DROM_MMU_End = 0x4000067c; +Cache_MMU_Init = 0x40000680; +Cache_MSPI_MMU_Set = 0x40000684; +Cache_Travel_Tag_Memory = 0x40000688; +Cache_Get_Virtual_Addr = 0x4000068c; +Cache_MSPI_MMU_Set_Secure = 0x40000690; +/* Data (.data, .bss, .rodata) */ +rom_cache_op_cb = 0x4084ffcc; +rom_cache_internal_table_ptr = 0x4084ffc8; + + +/*************************************** + Group clock + ***************************************/ + +/* Functions */ +ets_clk_get_xtal_freq = 0x40000694; +ets_clk_get_cpu_freq = 0x40000698; + + +/*************************************** + Group gpio + ***************************************/ + +/* Functions */ +gpio_input_get = 0x4000069c; +gpio_matrix_in = 0x400006a0; +gpio_matrix_out = 0x400006a4; + +//TODO: [ESP32H21] IDF-11621 +gpio_output_disable = 0x400006a8; +gpio_output_enable = 0x400006ac; + +gpio_output_set = 0x400006b0; +gpio_pad_hold = 0x400006b4; +gpio_pad_input_disable = 0x400006b8; +gpio_pad_input_enable = 0x400006bc; +gpio_pad_pulldown = 0x400006c0; +gpio_pad_pullup = 0x400006c4; +gpio_pad_select_gpio = 0x400006c8; +gpio_pad_set_drv = 0x400006cc; +gpio_pad_unhold = 0x400006d0; +gpio_pin_wakeup_disable = 0x400006d4; +gpio_pin_wakeup_enable = 0x400006d8; +gpio_bypass_matrix_in = 0x400006dc; + + +/*************************************** + Group interrupts + ***************************************/ + +/* Functions */ +esprv_intc_int_set_priority = 0x400006e0; +esprv_intc_int_set_threshold = 0x400006e4; +esprv_intc_int_enable = 0x400006e8; +esprv_intc_int_disable = 0x400006ec; +esprv_intc_int_set_type = 0x400006f0; +PROVIDE( intr_handler_set = 0x400006f4 ); +intr_matrix_set = 0x400006f8; +ets_intr_lock = 0x400006fc; +ets_intr_unlock = 0x40000700; +ets_isr_attach = 0x40000704; +ets_isr_mask = 0x40000708; +ets_isr_unmask = 0x4000070c; + + +/*************************************** + Group crypto + ***************************************/ + +/* Functions */ +md5_vector = 0x40000710; +MD5Init = 0x40000714; +MD5Update = 0x40000718; +MD5Final = 0x4000071c; +crc32_le = 0x40000720; +crc16_le = 0x40000724; +crc8_le = 0x40000728; +crc32_be = 0x4000072c; +crc16_be = 0x40000730; +crc8_be = 0x40000734; +esp_crc8 = 0x40000738; +ets_sha_enable = 0x4000073c; +ets_sha_disable = 0x40000740; +ets_sha_get_state = 0x40000744; +ets_sha_init = 0x40000748; +ets_sha_process = 0x4000074c; +ets_sha_starts = 0x40000750; +ets_sha_update = 0x40000754; +ets_sha_finish = 0x40000758; +ets_sha_clone = 0x4000075c; +ets_hmac_enable = 0x40000760; +ets_hmac_disable = 0x40000764; +ets_hmac_calculate_message = 0x40000768; +ets_hmac_calculate_downstream = 0x4000076c; +ets_hmac_invalidate_downstream = 0x40000770; +ets_jtag_enable_temporarily = 0x40000774; +ets_aes_enable = 0x40000778; +ets_aes_disable = 0x4000077c; +ets_aes_setkey = 0x40000780; +ets_aes_block = 0x40000784; +ets_aes_setkey_dec = 0x40000788; +ets_aes_setkey_enc = 0x4000078c; +ets_bigint_enable = 0x40000790; +ets_bigint_disable = 0x40000794; +ets_bigint_multiply = 0x40000798; +ets_bigint_modmult = 0x4000079c; +ets_bigint_modexp = 0x400007a0; +ets_bigint_wait_finish = 0x400007a4; +ets_bigint_getz = 0x400007a8; +ets_ds_enable = 0x400007ac; +ets_ds_disable = 0x400007b0; +ets_ds_start_sign = 0x400007b4; +ets_ds_is_busy = 0x400007b8; +ets_ds_finish_sign = 0x400007bc; +ets_ds_encrypt_params = 0x400007c0; +ets_mgf1_sha256 = 0x400007c4; +/* Data (.data, .bss, .rodata) */ +crc32_le_table_ptr = 0x4001fff8; +crc16_le_table_ptr = 0x4001fff4; +crc8_le_table_ptr = 0x4001fff0; +crc32_be_table_ptr = 0x4001ffec; +crc16_be_table_ptr = 0x4001ffe8; +crc8_be_table_ptr = 0x4001ffe4; + + +/*************************************** + Group efuse + ***************************************/ + +/* Functions */ +ets_efuse_read = 0x400007c8; +ets_efuse_program = 0x400007cc; +ets_efuse_clear_program_registers = 0x400007d0; +ets_efuse_write_key = 0x400007d4; +ets_efuse_get_read_register_address = 0x400007d8; +ets_efuse_get_key_purpose = 0x400007dc; +ets_efuse_key_block_unused = 0x400007e0; +ets_efuse_find_unused_key_block = 0x400007e4; +ets_efuse_rs_calculate = 0x400007e8; +ets_efuse_count_unused_key_blocks = 0x400007ec; +ets_efuse_secure_boot_enabled = 0x400007f0; +ets_efuse_secure_boot_aggressive_revoke_enabled = 0x400007f4; +ets_efuse_cache_encryption_enabled = 0x400007f8; +ets_efuse_download_modes_disabled = 0x400007fc; +ets_efuse_find_purpose = 0x40000800; +ets_efuse_force_send_resume = 0x40000804; +ets_efuse_get_flash_delay_us = 0x40000808; +ets_efuse_get_mac = 0x4000080c; +ets_efuse_get_uart_print_control = 0x40000810; +ets_efuse_direct_boot_mode_disabled = 0x40000814; +ets_efuse_security_download_modes_enabled = 0x40000818; +ets_efuse_jtag_disabled = 0x4000081c; +ets_efuse_usb_print_is_disabled = 0x40000820; +ets_efuse_usb_download_mode_disabled = 0x40000824; +ets_efuse_usb_device_disabled = 0x40000828; +ets_efuse_secure_boot_fast_wake_enabled = 0x4000082c; + + +/*************************************** + Group secureboot + ***************************************/ + +/* Functions */ +ets_emsa_pss_verify = 0x40000830; +ets_rsa_pss_verify = 0x40000834; +ets_ecdsa_verify = 0x40000838; +ets_secure_boot_verify_bootloader_with_keys = 0x4000083c; +ets_secure_boot_verify_signature = 0x40000840; +ets_secure_boot_read_key_digests = 0x40000844; +ets_secure_boot_revoke_public_key_digest = 0x40000848; + + +/*************************************** + Group usb_device_uart + ***************************************/ + +/* Functions */ +usb_serial_device_rx_one_char = 0x400009bc; +usb_serial_device_rx_one_char_block = 0x400009c0; +usb_serial_device_tx_flush = 0x400009c4; +usb_serial_device_tx_one_char = 0x400009c8; diff --git a/components/esp_rom/esp32h21/ld/esp32h21.rom.libgcc.ld b/components/esp_rom/esp32h21/ld/esp32h21.rom.libgcc.ld new file mode 100644 index 00000000000..af79c5322c1 --- /dev/null +++ b/components/esp_rom/esp32h21/ld/esp32h21.rom.libgcc.ld @@ -0,0 +1,112 @@ +/* + * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +/* ROM function interface esp32h21.rom.libgcc.ld for esp32h21 + * + * + * Generated from ./target/esp32h21/interface-esp32h21.yml md5sum dee73289acb146ae14dd9544143527f0 + * + * Compatible with ROM where ECO version equal or greater to 0. + * + * THIS FILE WAS AUTOMATICALLY GENERATED. DO NOT EDIT. + */ + +/*************************************** + Group libgcc + ***************************************/ + +/* Functions */ +__absvdi2 = 0x4000084c; +__absvsi2 = 0x40000850; +__adddf3 = 0x40000854; +__addsf3 = 0x40000858; +__addvdi3 = 0x4000085c; +__addvsi3 = 0x40000860; +__ashldi3 = 0x40000864; +__ashrdi3 = 0x40000868; +__bswapdi2 = 0x4000086c; +__bswapsi2 = 0x40000870; +__clear_cache = 0x40000874; +__clrsbdi2 = 0x40000878; +__clrsbsi2 = 0x4000087c; +__clzdi2 = 0x40000880; +__clzsi2 = 0x40000884; +__cmpdi2 = 0x40000888; +__ctzdi2 = 0x4000088c; +__ctzsi2 = 0x40000890; +__divdc3 = 0x40000894; +__divdf3 = 0x40000898; +__divdi3 = 0x4000089c; +__divsc3 = 0x400008a0; +__divsf3 = 0x400008a4; +__divsi3 = 0x400008a8; +__eqdf2 = 0x400008ac; +__eqsf2 = 0x400008b0; +__extendsfdf2 = 0x400008b4; +__ffsdi2 = 0x400008b8; +__ffssi2 = 0x400008bc; +__fixdfdi = 0x400008c0; +__fixdfsi = 0x400008c4; +__fixsfdi = 0x400008c8; +__fixsfsi = 0x400008cc; +__fixunsdfsi = 0x400008d0; +__fixunssfdi = 0x400008d4; +__fixunssfsi = 0x400008d8; +__floatdidf = 0x400008dc; +__floatdisf = 0x400008e0; +__floatsidf = 0x400008e4; +__floatsisf = 0x400008e8; +__floatundidf = 0x400008ec; +__floatundisf = 0x400008f0; +__floatunsidf = 0x400008f4; +__floatunsisf = 0x400008f8; +__gcc_bcmp = 0x400008fc; +__gedf2 = 0x40000900; +__gesf2 = 0x40000904; +__gtdf2 = 0x40000908; +__gtsf2 = 0x4000090c; +__ledf2 = 0x40000910; +__lesf2 = 0x40000914; +__lshrdi3 = 0x40000918; +__ltdf2 = 0x4000091c; +__ltsf2 = 0x40000920; +__moddi3 = 0x40000924; +__modsi3 = 0x40000928; +__muldc3 = 0x4000092c; +__muldf3 = 0x40000930; +__muldi3 = 0x40000934; +__mulsc3 = 0x40000938; +__mulsf3 = 0x4000093c; +__mulsi3 = 0x40000940; +__mulvdi3 = 0x40000944; +__mulvsi3 = 0x40000948; +__nedf2 = 0x4000094c; +__negdf2 = 0x40000950; +__negdi2 = 0x40000954; +__negsf2 = 0x40000958; +__negvdi2 = 0x4000095c; +__negvsi2 = 0x40000960; +__nesf2 = 0x40000964; +__paritysi2 = 0x40000968; +__popcountdi2 = 0x4000096c; +__popcountsi2 = 0x40000970; +__powidf2 = 0x40000974; +__powisf2 = 0x40000978; +__subdf3 = 0x4000097c; +__subsf3 = 0x40000980; +__subvdi3 = 0x40000984; +__subvsi3 = 0x40000988; +__truncdfsf2 = 0x4000098c; +__ucmpdi2 = 0x40000990; +__udivdi3 = 0x40000994; +__udivmoddi4 = 0x40000998; +__udivsi3 = 0x4000099c; +__udiv_w_sdiv = 0x400009a0; +__umoddi3 = 0x400009a4; +__umodsi3 = 0x400009a8; +__unorddf2 = 0x400009ac; +__unordsf2 = 0x400009b0; +__extenddftf2 = 0x400009b4; +__trunctfdf2 = 0x400009b8; diff --git a/components/esp_rom/esp32h21/ld/esp32h21.rom.newlib-nano.ld b/components/esp_rom/esp32h21/ld/esp32h21.rom.newlib-nano.ld new file mode 100644 index 00000000000..166c1ce2d79 --- /dev/null +++ b/components/esp_rom/esp32h21/ld/esp32h21.rom.newlib-nano.ld @@ -0,0 +1,32 @@ +/* + * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +/* ROM function interface esp32h21.rom.newlib-nano.ld for esp32h21 + * + * + * Generated from ./target/esp32h21/interface-esp32h21.yml md5sum dee73289acb146ae14dd9544143527f0 + * + * Compatible with ROM where ECO version equal or greater to 0. + * + * THIS FILE WAS AUTOMATICALLY GENERATED. DO NOT EDIT. + */ + +/*************************************** + Group newlib_nano_format + ***************************************/ + +/* Functions */ +__sprint_r = 0x400005c4; +_fiprintf_r = 0x400005c8; +_fprintf_r = 0x400005cc; +_printf_common = 0x400005d0; +_printf_i = 0x400005d4; +_vfiprintf_r = 0x400005d8; +_vfprintf_r = 0x400005dc; +fiprintf = 0x400005e0; +fprintf = 0x400005e4; +printf = 0x400005e8; +vfiprintf = 0x400005ec; +vfprintf = 0x400005f0; diff --git a/components/esp_rom/esp32h21/ld/esp32h21.rom.newlib.ld b/components/esp_rom/esp32h21/ld/esp32h21.rom.newlib.ld new file mode 100644 index 00000000000..a596f1709c9 --- /dev/null +++ b/components/esp_rom/esp32h21/ld/esp32h21.rom.newlib.ld @@ -0,0 +1,99 @@ +/* + * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +/* ROM function interface esp32h21.rom.newlib.ld for esp32h21 + * + * + * Generated from ./target/esp32h21/interface-esp32h21.yml md5sum dee73289acb146ae14dd9544143527f0 + * + * Compatible with ROM where ECO version equal or greater to 0. + * + * THIS FILE WAS AUTOMATICALLY GENERATED. DO NOT EDIT. + */ + +/*************************************** + Group newlib + ***************************************/ + +/* Functions */ +esp_rom_newlib_init_common_mutexes = 0x40000494; +memset = 0x40000498; +memcpy = 0x4000049c; +memmove = 0x400004a0; +memcmp = 0x400004a4; +strcpy = 0x400004a8; +strncpy = 0x400004ac; +strcmp = 0x400004b0; +strncmp = 0x400004b4; +strlen = 0x400004b8; +strstr = 0x400004bc; +bzero = 0x400004c0; +_isatty_r = 0x400004c4; +sbrk = 0x400004c8; +isalnum = 0x400004cc; +isalpha = 0x400004d0; +isascii = 0x400004d4; +isblank = 0x400004d8; +iscntrl = 0x400004dc; +isdigit = 0x400004e0; +islower = 0x400004e4; +isgraph = 0x400004e8; +isprint = 0x400004ec; +ispunct = 0x400004f0; +isspace = 0x400004f4; +isupper = 0x400004f8; +toupper = 0x400004fc; +tolower = 0x40000500; +toascii = 0x40000504; +memccpy = 0x40000508; +memchr = 0x4000050c; +memrchr = 0x40000510; +strcasecmp = 0x40000514; +strcasestr = 0x40000518; +strcat = 0x4000051c; +strdup = 0x40000520; +strchr = 0x40000524; +strcspn = 0x40000528; +strcoll = 0x4000052c; +strlcat = 0x40000530; +strlcpy = 0x40000534; +strlwr = 0x40000538; +strncasecmp = 0x4000053c; +strncat = 0x40000540; +strndup = 0x40000544; +strnlen = 0x40000548; +strrchr = 0x4000054c; +strsep = 0x40000550; +strspn = 0x40000554; +strtok_r = 0x40000558; +strupr = 0x4000055c; +longjmp = 0x40000560; +setjmp = 0x40000564; +abs = 0x40000568; +div = 0x4000056c; +labs = 0x40000570; +ldiv = 0x40000574; +qsort = 0x40000578; +rand_r = 0x4000057c; +rand = 0x40000580; +srand = 0x40000584; +utoa = 0x40000588; +itoa = 0x4000058c; +atoi = 0x40000590; +atol = 0x40000594; +strtol = 0x40000598; +strtoul = 0x4000059c; +fflush = 0x400005a0; +_fflush_r = 0x400005a4; +_fwalk = 0x400005a8; +_fwalk_reent = 0x400005ac; +__smakebuf_r = 0x400005b0; +__swhatbuf_r = 0x400005b4; +__swbuf_r = 0x400005b8; +__swbuf = 0x400005bc; +__swsetup_r = 0x400005c0; +/* Data (.data, .bss, .rodata) */ +syscall_table_ptr = 0x4084ffd4; +_global_impure_ptr = 0x4084ffd0; diff --git a/components/esp_rom/esp32h21/ld/esp32h21.rom.spiflash.ld b/components/esp_rom/esp32h21/ld/esp32h21.rom.spiflash.ld new file mode 100644 index 00000000000..98106e04050 --- /dev/null +++ b/components/esp_rom/esp32h21/ld/esp32h21.rom.spiflash.ld @@ -0,0 +1,166 @@ +/* + * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +/* ROM function interface esp32h21.rom.spiflash.ld for esp32h21 + * + * + * Generated from ./target/esp32h21/interface-esp32h21.yml md5sum dee73289acb146ae14dd9544143527f0 + * + * Compatible with ROM where ECO version equal or greater to 0. + * + * THIS FILE WAS AUTOMATICALLY GENERATED. DO NOT EDIT. + */ + +/*************************************** + Group spi_flash_cache + ***************************************/ + +/* Functions */ +spi_flash_disable_cache = 0x400001e8; +spi_flash_restore_cache = 0x400001ec; +spi_flash_cache_enabled = 0x400001f0; +spi_flash_enable_cache = 0x400001f4; +esp_enable_cache_flash_wrap = 0x400001f8; + + +/*************************************** + Group spi_flash_mmap + ***************************************/ + +/* Functions */ +spi_flash_mmap_os_func_set = 0x400001fc; +spi_flash_mmap_page_num_init = 0x40000200; +spi_flash_mmap = 0x40000204; +spi_flash_mmap_pages = 0x40000208; +spi_flash_munmap = 0x4000020c; +spi_flash_mmap_dump = 0x40000210; +spi_flash_check_and_flush_cache = 0x40000214; +spi_flash_mmap_get_free_pages = 0x40000218; +spi_flash_cache2phys = 0x4000021c; +spi_flash_phys2cache = 0x40000220; + + +/*************************************** + Group esp_flash + ***************************************/ + +/* Functions */ +esp_flash_chip_driver_initialized = 0x40000224; +esp_flash_read_id = 0x40000228; +esp_flash_get_size = 0x4000022c; +esp_flash_erase_chip = 0x40000230; +esp_flash_erase_region = 0x40000234; +esp_flash_get_chip_write_protect = 0x40000238; +esp_flash_set_chip_write_protect = 0x4000023c; +esp_flash_get_protectable_regions = 0x40000240; +esp_flash_get_protected_region = 0x40000244; +esp_flash_set_protected_region = 0x40000248; +esp_flash_read = 0x4000024c; +esp_flash_write = 0x40000250; +esp_flash_write_encrypted = 0x40000254; +esp_flash_read_encrypted = 0x40000258; +esp_flash_get_io_mode = 0x4000025c; +esp_flash_set_io_mode = 0x40000260; +spi_flash_boot_attach = 0x40000264; +esp_flash_read_chip_id = 0x40000268; +detect_spi_flash_chip = 0x4000026c; +esp_rom_spiflash_write_disable = 0x40000270; +esp_flash_suspend_cmd_init = 0x40000274; +/* Data (.data, .bss, .rodata) */ +esp_flash_default_chip = 0x4084ffe8; +esp_flash_api_funcs = 0x4084ffe4; + + +/*************************************** + Group spi_flash_chips + ***************************************/ + +/* Functions */ +spi_flash_chip_generic_probe = 0x40000278; +spi_flash_chip_generic_detect_size = 0x4000027c; +spi_flash_chip_generic_write = 0x40000280; +spi_flash_chip_generic_write_encrypted = 0x40000284; +spi_flash_chip_generic_set_write_protect = 0x40000288; +spi_flash_common_write_status_16b_wrsr = 0x4000028c; +spi_flash_chip_generic_reset = 0x40000290; +spi_flash_chip_generic_erase_chip = 0x40000294; +spi_flash_chip_generic_erase_sector = 0x40000298; +spi_flash_chip_generic_erase_block = 0x4000029c; +spi_flash_chip_generic_page_program = 0x400002a0; +spi_flash_chip_generic_get_write_protect = 0x400002a4; +spi_flash_common_read_status_16b_rdsr_rdsr2 = 0x400002a8; +spi_flash_chip_generic_read_reg = 0x400002ac; +spi_flash_chip_generic_yield = 0x400002b0; +spi_flash_generic_wait_host_idle = 0x400002b4; +spi_flash_chip_generic_wait_idle = 0x400002b8; +spi_flash_chip_generic_config_host_io_mode = 0x400002bc; +spi_flash_chip_generic_read = 0x400002c0; +spi_flash_common_read_status_8b_rdsr2 = 0x400002c4; +spi_flash_chip_generic_get_io_mode = 0x400002c8; +spi_flash_common_read_status_8b_rdsr = 0x400002cc; +spi_flash_common_write_status_8b_wrsr = 0x400002d0; +spi_flash_common_write_status_8b_wrsr2 = 0x400002d4; +spi_flash_common_set_io_mode = 0x400002d8; +spi_flash_chip_generic_set_io_mode = 0x400002dc; +spi_flash_chip_generic_read_unique_id = 0x400002e0; +spi_flash_chip_generic_get_caps = 0x400002e4; +spi_flash_chip_generic_suspend_cmd_conf = 0x400002e8; +spi_flash_chip_gd_get_io_mode = 0x400002ec; +spi_flash_chip_gd_probe = 0x400002f0; +spi_flash_chip_gd_set_io_mode = 0x400002f4; +/* Data (.data, .bss, .rodata) */ +spi_flash_chip_generic_config_data = 0x4084ffe0; +spi_flash_encryption = 0x4084ffdc; + + +/*************************************** + Group memspi_host + ***************************************/ + +/* Functions */ +memspi_host_read_id_hs = 0x400002f8; +memspi_host_read_status_hs = 0x400002fc; +memspi_host_flush_cache = 0x40000300; +memspi_host_erase_chip = 0x40000304; +memspi_host_erase_sector = 0x40000308; +memspi_host_erase_block = 0x4000030c; +memspi_host_program_page = 0x40000310; +memspi_host_read = 0x40000314; +memspi_host_set_write_protect = 0x40000318; +memspi_host_set_max_read_len = 0x4000031c; +memspi_host_read_data_slicer = 0x40000320; +memspi_host_write_data_slicer = 0x40000324; + + +/*************************************** + Group hal_spiflash + ***************************************/ + +/* Functions */ +spi_flash_hal_poll_cmd_done = 0x40000328; +spi_flash_hal_device_config = 0x4000032c; +spi_flash_hal_configure_host_io_mode = 0x40000330; +spi_flash_hal_common_command = 0x40000334; +spi_flash_hal_read = 0x40000338; +spi_flash_hal_erase_chip = 0x4000033c; +spi_flash_hal_erase_sector = 0x40000340; +spi_flash_hal_erase_block = 0x40000344; +spi_flash_hal_program_page = 0x40000348; +spi_flash_hal_set_write_protect = 0x4000034c; +spi_flash_hal_host_idle = 0x40000350; +spi_flash_hal_check_status = 0x40000354; +spi_flash_hal_setup_read_suspend = 0x40000358; +spi_flash_hal_setup_auto_suspend_mode = 0x4000035c; +spi_flash_hal_setup_auto_resume_mode = 0x40000360; +spi_flash_hal_disable_auto_suspend_mode = 0x40000364; +spi_flash_hal_disable_auto_resume_mode = 0x40000368; +spi_flash_hal_resume = 0x4000036c; +spi_flash_hal_suspend = 0x40000370; +spi_flash_encryption_hal_enable = 0x40000374; +spi_flash_encryption_hal_disable = 0x40000378; +spi_flash_encryption_hal_prepare = 0x4000037c; +spi_flash_encryption_hal_done = 0x40000380; +spi_flash_encryption_hal_destroy = 0x40000384; +spi_flash_encryption_hal_check = 0x40000388; diff --git a/components/esp_rom/esp32h21/ld/esp32h21.rom.systimer.ld b/components/esp_rom/esp32h21/ld/esp32h21.rom.systimer.ld new file mode 100644 index 00000000000..f2e82d522b9 --- /dev/null +++ b/components/esp_rom/esp32h21/ld/esp32h21.rom.systimer.ld @@ -0,0 +1,27 @@ +/* + * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/*************************************** + Group hal_systimer + ***************************************/ + +/* Functions */ +/* The following ROM functions are commented out because they're patched in the esp_rom_systimer.c */ +/* systimer_hal_init = 0x400003b8; */ +/* systimer_hal_deinit = 0x400003bc; */ +systimer_hal_set_tick_rate_ops = 0x400003c0; +systimer_hal_get_counter_value = 0x400003c4; +systimer_hal_get_time = 0x400003c8; +systimer_hal_set_alarm_target = 0x400003cc; +systimer_hal_set_alarm_period = 0x400003d0; +systimer_hal_get_alarm_value = 0x400003d4; +systimer_hal_enable_alarm_int = 0x400003d8; +systimer_hal_on_apb_freq_update = 0x400003dc; +systimer_hal_counter_value_advance = 0x400003e0; +systimer_hal_enable_counter = 0x400003e4; +systimer_hal_select_alarm_mode = 0x400003e8; +systimer_hal_connect_alarm_counter = 0x400003ec; +systimer_hal_counter_can_stall_by_cpu = 0x400003f0; diff --git a/components/esp_rom/esp32h21/ld/esp32h21.rom.version.ld b/components/esp_rom/esp32h21/ld/esp32h21.rom.version.ld new file mode 100644 index 00000000000..c91bb8f06c4 --- /dev/null +++ b/components/esp_rom/esp32h21/ld/esp32h21.rom.version.ld @@ -0,0 +1,15 @@ +/* + * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + + +/* ROM version variables for esp32h21 + * + * These addresses should be compatible with any ROM version for this chip. + * + * THIS FILE WAS AUTOMATICALLY GENERATED. DO NOT EDIT. + */ +_rom_chip_id = 0x40000010; +_rom_eco_version = 0x40000014; diff --git a/components/esp_rom/esp32h21/ld/esp32h21.rom.wdt.ld b/components/esp_rom/esp32h21/ld/esp32h21.rom.wdt.ld new file mode 100644 index 00000000000..6d139bdd041 --- /dev/null +++ b/components/esp_rom/esp32h21/ld/esp32h21.rom.wdt.ld @@ -0,0 +1,27 @@ +/* + * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/*************************************** + Group hal_wdt + ***************************************/ + +/* Functions */ + +/* Patch init function to set clock source +wdt_hal_init = 0x4000038c; +wdt_hal_deinit = 0x40000390; +*/ + +/* Functions */ +wdt_hal_config_stage = 0x40000394; +wdt_hal_write_protect_disable = 0x40000398; +wdt_hal_write_protect_enable = 0x4000039c; +wdt_hal_enable = 0x400003a0; +wdt_hal_disable = 0x400003a4; +wdt_hal_handle_intr = 0x400003a8; +wdt_hal_feed = 0x400003ac; +wdt_hal_set_flashboot_en = 0x400003b0; +wdt_hal_is_enabled = 0x400003b4; diff --git a/components/esp_rom/include/esp_rom_libc_stubs.h b/components/esp_rom/include/esp_rom_libc_stubs.h index 7db1a262818..734860864a7 100644 --- a/components/esp_rom/include/esp_rom_libc_stubs.h +++ b/components/esp_rom/include/esp_rom_libc_stubs.h @@ -25,6 +25,8 @@ #include "esp32c5/rom/libc_stubs.h" #elif CONFIG_IDF_TARGET_ESP32H2 #include "esp32h2/rom/libc_stubs.h" +#elif CONFIG_IDF_TARGET_ESP32H21 +#include "esp32h21/rom/libc_stubs.h" #elif CONFIG_IDF_TARGET_ESP32P4 #include "esp32p4/rom/libc_stubs.h" #endif diff --git a/components/esp_rom/patches/esp_rom_systimer.c b/components/esp_rom/patches/esp_rom_systimer.c index 7de32f09e6a..944d9f879e1 100644 --- a/components/esp_rom/patches/esp_rom_systimer.c +++ b/components/esp_rom/patches/esp_rom_systimer.c @@ -64,7 +64,7 @@ void systimer_hal_counter_value_advance(systimer_hal_context_t *hal, uint32_t co } #endif // CONFIG_IDF_TARGET_ESP32C2 && (CONFIG_ESP32C2_REV_MIN_FULL < 200) -#if CONFIG_IDF_TARGET_ESP32C6 || CONFIG_IDF_TARGET_ESP32H2 || CONFIG_IDF_TARGET_ESP32P4 || CONFIG_IDF_TARGET_ESP32C5 || CONFIG_IDF_TARGET_ESP32C61 +#if CONFIG_IDF_TARGET_ESP32C6 || CONFIG_IDF_TARGET_ESP32H2 || CONFIG_IDF_TARGET_ESP32P4 || CONFIG_IDF_TARGET_ESP32C5 || CONFIG_IDF_TARGET_ESP32C61 || CONFIG_IDF_TARGET_ESP32H21 void systimer_hal_init(systimer_hal_context_t *hal) { hal->dev = &SYSTIMER; From 92027a903953407a0e76ad43da9e54b5bb29fa33 Mon Sep 17 00:00:00 2001 From: "nilesh.kale" Date: Tue, 17 Dec 2024 17:14:27 +0530 Subject: [PATCH 097/118] fix(esp_http_client): updated API esp_http_client_get_url to get URL in correct format This commit updates the API to include the port number in the URL, which was previously missing. --- components/esp_http_client/esp_http_client.c | 2 +- .../test_apps/main/test_http_client.c | 24 +++++++++++++++++-- 2 files changed, 23 insertions(+), 3 deletions(-) diff --git a/components/esp_http_client/esp_http_client.c b/components/esp_http_client/esp_http_client.c index d54558ec161..4f365f98635 100644 --- a/components/esp_http_client/esp_http_client.c +++ b/components/esp_http_client/esp_http_client.c @@ -1864,7 +1864,7 @@ esp_err_t esp_http_client_get_url(esp_http_client_handle_t client, char *url, co return ESP_ERR_INVALID_ARG; } if (client->connection_info.host && client->connection_info.scheme && client->connection_info.path) { - snprintf(url, len, "%s://%s%s", client->connection_info.scheme, client->connection_info.host, client->connection_info.path); + snprintf(url, len, "%s://%s:%d%s", client->connection_info.scheme, client->connection_info.host, client->connection_info.port, client->connection_info.path); return ESP_OK; } else { ESP_LOGE(TAG, "Failed to get URL"); diff --git a/components/esp_http_client/test_apps/main/test_http_client.c b/components/esp_http_client/test_apps/main/test_http_client.c index f4b1e081f8d..f066c2d52bf 100644 --- a/components/esp_http_client/test_apps/main/test_http_client.c +++ b/components/esp_http_client/test_apps/main/test_http_client.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2018-2021 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2018-2024 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -99,7 +99,7 @@ TEST_CASE("Username is unmodified when we change to new path", "[ESP HTTP CLIENT * Explicit APIs esp_http_client_set_username and esp_http_client_set_password are used to change * the auth credentials **/ -TEST_CASE("Username and password will not reset if new absolute URL doesnot specify auth credentials.", "[ESP HTTP CLIENT]") +TEST_CASE("Username and password will not reset if new absolute URL does not specify auth credentials.", "[ESP HTTP CLIENT]") { esp_http_client_config_t config_with_auth = { .host = HOST, @@ -146,6 +146,26 @@ TEST_CASE("esp_http_client_init() should return NULL if configured with wrong ur esp_http_client_cleanup(client); } +/** + * Test case to verify that esp_http_client_get_url() returns the URL in the correct format. + **/ +TEST_CASE("esp_http_client_get_url() should return URL in the correct format", "[ESP HTTP CLIENT]") +{ + const char *url = "http://httpbin.org:8080/post"; + esp_http_client_config_t config = { + .url = url, + }; + + esp_http_client_handle_t client = esp_http_client_init(&config); + TEST_ASSERT_NOT_NULL(client); + + char client_url[32]; + esp_http_client_get_url(client, client_url, sizeof(client_url)); + esp_http_client_cleanup(client); + + TEST_ASSERT_EQUAL_STRING(url, client_url); +} + void app_main(void) { unity_run_menu(); From 7da66fb09864073c49d13b6461d446605dd129d4 Mon Sep 17 00:00:00 2001 From: Erhan Kurubas Date: Tue, 17 Dec 2024 11:33:42 +0300 Subject: [PATCH 098/118] change(coredump): make sure consistency with written data and calculated checksum --- components/espcoredump/src/core_dump_flash.c | 59 ++------------------ 1 file changed, 6 insertions(+), 53 deletions(-) diff --git a/components/espcoredump/src/core_dump_flash.c b/components/espcoredump/src/core_dump_flash.c index ece2af211ad..e72a23b4683 100644 --- a/components/espcoredump/src/core_dump_flash.c +++ b/components/espcoredump/src/core_dump_flash.c @@ -154,21 +154,15 @@ static esp_err_t esp_core_dump_flash_write_data(core_dump_write_data_t* wr_data, uint32_t written = 0; uint32_t wr_sz = 0; - /* Make sure that the partition is large enough to hold the data. */ - ESP_COREDUMP_ASSERT((wr_data->off + data_size) < s_core_flash_config.partition.size); + /* Make sure that the partition is large enough to store both the cached and new data. */ + ESP_COREDUMP_ASSERT((wr_data->off + wr_data->cached_bytes + data_size) < s_core_flash_config.partition.size); - if (wr_data->cached_bytes) { - /* Some bytes are in the cache, let's continue filling the cache - * with the data received as parameter. Let's calculate the maximum - * amount of bytes we can still fill the cache with. */ - if ((COREDUMP_CACHE_SIZE - wr_data->cached_bytes) > data_size) { - wr_sz = data_size; - } else { - wr_sz = COREDUMP_CACHE_SIZE - wr_data->cached_bytes; - } + while (data_size > 0) { + /* Calculate the maximum amount of bytes we can still fill the cache with. */ + wr_sz = MIN(data_size, COREDUMP_CACHE_SIZE - wr_data->cached_bytes); /* Append wr_sz bytes from data parameter to the cache. */ - memcpy(&wr_data->cached_data[wr_data->cached_bytes], data, wr_sz); + memcpy(&wr_data->cached_data[wr_data->cached_bytes], data + written, wr_sz); wr_data->cached_bytes += wr_sz; if (wr_data->cached_bytes == COREDUMP_CACHE_SIZE) { @@ -196,47 +190,6 @@ static esp_err_t esp_core_dump_flash_write_data(core_dump_write_data_t* wr_data, data_size -= wr_sz; } - /* Figure out how many bytes we can write onto the flash directly, without - * using the cache. In our case the cache size is a multiple of the flash's - * minimum writing block size, so we will use it for our calculation. - * For example, if COREDUMP_CACHE_SIZE equals 32, here are interesting - * values: - * +---------+-----------------------+ - * | | data_size | - * +---------+---+----+----+----+----+ - * | | 0 | 31 | 32 | 40 | 64 | - * +---------+---+----+----+----+----+ - * | (blocks | 0 | 0 | 1 | 1 | 2) | - * +---------+---+----+----+----+----+ - * | wr_sz | 0 | 0 | 32 | 32 | 64 | - * +---------+---+----+----+----+----+ - */ - wr_sz = (data_size / COREDUMP_CACHE_SIZE) * COREDUMP_CACHE_SIZE; - if (wr_sz) { - /* Write the contiguous amount of bytes to the flash, - * without using the cache */ - err = esp_core_dump_flash_custom_write(s_core_flash_config.partition.start + wr_data->off, data + written, wr_sz); - - if (err != ESP_OK) { - ESP_COREDUMP_LOGE("Failed to write data to flash (%d)!", err); - return err; - } - - /* Update the checksum with the newly written bytes */ - esp_core_dump_checksum_update(&wr_data->checksum_ctx, data + written, wr_sz); - wr_data->off += wr_sz; - written += wr_sz; - data_size -= wr_sz; - } - - if (data_size > 0) { - /* There still some bytes from the data parameter that need to be sent, - * append it to cache in order to write them later. (i.e. when there - * will be enough bytes to fill the cache) */ - memcpy(&wr_data->cached_data, data + written, data_size); - wr_data->cached_bytes = data_size; - } - return ESP_OK; } From 1456fec98c73a570f272acd79678e1968f4dd1c2 Mon Sep 17 00:00:00 2001 From: Erhan Kurubas Date: Tue, 17 Dec 2024 11:42:58 +0300 Subject: [PATCH 099/118] change(coredump): include coredump own stack into coredump file --- .../include_core_dump/esp_core_dump_common.h | 6 -- components/espcoredump/src/core_dump_common.c | 20 ----- components/espcoredump/src/core_dump_elf.c | 75 +------------------ 3 files changed, 1 insertion(+), 100 deletions(-) diff --git a/components/espcoredump/include_core_dump/esp_core_dump_common.h b/components/espcoredump/include_core_dump/esp_core_dump_common.h index 9e9efb2ef1c..1292e972460 100644 --- a/components/espcoredump/include_core_dump/esp_core_dump_common.h +++ b/components/espcoredump/include_core_dump/esp_core_dump_common.h @@ -136,12 +136,6 @@ esp_err_t esp_core_dump_write_data(core_dump_write_data_t *wr_data, void *data, */ esp_err_t esp_core_dump_write_end(core_dump_write_data_t *wr_data); -/** - * @brief Retrieve the stack information which will be used from the coredump module itself. - * It will show the whole stack boundaries in case the stack is shared with the crashed task. - */ -void esp_core_dump_get_own_stack_info(uint32_t *addr, uint32_t *size); - /** * @brief Stores the core dump in either binary or ELF format. */ diff --git a/components/espcoredump/src/core_dump_common.c b/components/espcoredump/src/core_dump_common.c index d455bc9d3b3..7442d856883 100644 --- a/components/espcoredump/src/core_dump_common.c +++ b/components/espcoredump/src/core_dump_common.c @@ -312,26 +312,6 @@ int esp_core_dump_get_user_ram_info(coredump_region_t region, uint32_t *start) return total_sz; } -#if CONFIG_ESP_COREDUMP_CAPTURE_DRAM -void esp_core_dump_get_own_stack_info(uint32_t *addr, uint32_t *size) -{ -#if CONFIG_ESP_COREDUMP_STACK_SIZE > 0 - /* Custom stack reserved for the coredump */ - *addr = (uint32_t)s_coredump_stack; - *size = sizeof(s_coredump_stack); -#else - /* Shared stack with the crashed task */ - core_dump_task_handle_t handle = esp_core_dump_get_current_task_handle(); - TaskSnapshot_t rtos_snapshot = { 0 }; - vTaskGetSnapshot(handle, &rtos_snapshot); - StaticTask_t *current = (StaticTask_t *)handle; - *addr = (uint32_t)current->pxDummy6; //pxStack - *size = (uint32_t)rtos_snapshot.pxTopOfStack - (uint32_t)current->pxDummy6; /* free */ -#endif -} - -#endif /* CONFIG_ESP_COREDUMP_CAPTURE_DRAM */ - inline bool esp_core_dump_tcb_addr_is_sane(uint32_t addr) { return esp_core_dump_mem_seg_is_sane(addr, esp_core_dump_get_tcb_len()); diff --git a/components/espcoredump/src/core_dump_elf.c b/components/espcoredump/src/core_dump_elf.c index cdd3420cc51..4b6852f3187 100644 --- a/components/espcoredump/src/core_dump_elf.c +++ b/components/espcoredump/src/core_dump_elf.c @@ -81,11 +81,6 @@ typedef struct _core_dump_elf_t { uint16_t segs_count; core_dump_write_data_t write_data; uint32_t note_data_size; /* can be used where static storage needed */ -#if CONFIG_ESP_COREDUMP_CAPTURE_DRAM - /* To avoid checksum failure, coredump stack region will be excluded while storing the sections. */ - uint32_t coredump_stack_start; - uint32_t coredump_stack_size; -#endif } core_dump_elf_t; typedef struct { @@ -524,61 +519,6 @@ static int elf_write_tasks_data(core_dump_elf_t *self) #if CONFIG_ESP_COREDUMP_CAPTURE_DRAM -/* Coredump stack will also be used by the checksum functions while saving sections. - * There is a potential for inconsistency when writing coredump stack to the flash and calculating checksum simultaneously. - * This is because, coredump stack will be modified during the process, leading to incorrect checksum calculations. - * To mitigate this issue, it's important to ensure that the coredump stack excluded from checksum calculation by - * filter out from the written regions. - * Typically, the coredump stack can be located in two different sections. - * 1. In the bss section; - * 1.a if `CONFIG_ESP_COREDUMP_STACK_SIZE` set to a nonzero value - * 1.b if the crashed task is created with a static task buffer using the xTaskCreateStatic() api - * 2. In the heap section, if custom stack is not defined and the crashed task buffer is allocated in the heap - * with the xTaskCreate() api - * - * esp_core_dump_store_section() will check if the coredump stack is located inside the section. - * If it is, this part will be skipped. - * |+++++++++| xxxxxxxxxxxxxx |++++++++| - * |+++++++++| coredump stack |++++++++| -*/ -static int esp_core_dump_store_section(core_dump_elf_t *self, uint32_t start, uint32_t data_len) -{ - uint32_t end = start + data_len; - int total_sz = 0; - int ret; - - if (self->coredump_stack_start > start && self->coredump_stack_start < end) { - /* write until the coredump stack. */ - data_len = self->coredump_stack_start - start; - ret = elf_add_segment(self, PT_LOAD, - start, - (void*)start, - data_len); - - if (ret <= 0) { - return ret; - } - total_sz += ret; - - /* Skip coredump stack and set offset for the rest of the section */ - start = self->coredump_stack_start + self->coredump_stack_size; - data_len = end - start; - } - - if (data_len > 0) { - ret = elf_add_segment(self, PT_LOAD, - (uint32_t)start, - (void*)start, - (uint32_t)data_len); - if (ret <= 0) { - return ret; - } - total_sz += ret; - } - - return total_sz; -} - typedef struct { core_dump_elf_t *self; int *total_sz; @@ -611,11 +551,6 @@ bool esp_core_dump_write_heap_blocks(walker_heap_into_t heap_info, walker_block_ return false; } - if (self->coredump_stack_start == (uint32_t)block_info.ptr) { - /* skip writing coredump stack block */ - return true; - } - *ret = elf_add_segment(self, PT_LOAD, (uint32_t)block_info.ptr, (void*)block_info.ptr, @@ -629,7 +564,7 @@ bool esp_core_dump_write_heap_blocks(walker_heap_into_t heap_info, walker_block_ return true; } -#else +#endif static int esp_core_dump_store_section(core_dump_elf_t *self, uint32_t start, uint32_t data_len) { @@ -639,8 +574,6 @@ static int esp_core_dump_store_section(core_dump_elf_t *self, uint32_t start, ui data_len); } -#endif - static int elf_write_core_dump_user_data(core_dump_elf_t *self) { int total_sz = 0; @@ -825,12 +758,6 @@ static esp_err_t esp_core_dump_write_elf(void) int tot_len = sizeof(dump_hdr); int write_len = sizeof(dump_hdr); -#if CONFIG_ESP_COREDUMP_CAPTURE_DRAM - esp_core_dump_get_own_stack_info(&self.coredump_stack_start, &self.coredump_stack_size); - ESP_COREDUMP_LOG_PROCESS("Core dump stack start=%p size = %d", - (void *)self.coredump_stack_start, self.coredump_stack_size); -#endif - esp_err_t err = esp_core_dump_write_init(); if (err != ESP_OK) { ESP_COREDUMP_LOGE("Elf write init failed!"); From b02eb0161925f25d0d7f08d3228a3c78125f964e Mon Sep 17 00:00:00 2001 From: laokaiyao Date: Thu, 12 Dec 2024 21:28:59 +0800 Subject: [PATCH 100/118] fix(i2s): fixed incorrect buf size calculation --- components/esp_driver_i2s/i2s_common.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/components/esp_driver_i2s/i2s_common.c b/components/esp_driver_i2s/i2s_common.c index 3e0ba8fa4a1..5d23e1ef129 100644 --- a/components/esp_driver_i2s/i2s_common.c +++ b/components/esp_driver_i2s/i2s_common.c @@ -417,7 +417,11 @@ esp_err_t i2s_channel_register_event_callback(i2s_chan_handle_t handle, const i2 uint32_t i2s_get_buf_size(i2s_chan_handle_t handle, uint32_t data_bit_width, uint32_t dma_frame_num) { uint32_t active_chan = handle->active_slot; +#if CONFIG_IDF_TARGET_ESP32 uint32_t bytes_per_sample = ((data_bit_width + 15) / 16) * 2; +#else + uint32_t bytes_per_sample = (data_bit_width + 7) / 8; +#endif // CONFIG_IDF_TARGET_ESP32 uint32_t bytes_per_frame = bytes_per_sample * active_chan; uint32_t bufsize = dma_frame_num * bytes_per_frame; #if SOC_CACHE_INTERNAL_MEM_VIA_L1CACHE From 6cc2c717a9043835d6d986c3d3f4b06198d3a9b2 Mon Sep 17 00:00:00 2001 From: laokaiyao Date: Tue, 17 Dec 2024 14:41:02 +0800 Subject: [PATCH 101/118] fix(i2s): return error when mclk_div is smaller than 2 --- components/esp_driver_i2s/i2s_pdm.c | 8 ++++---- components/esp_driver_i2s/i2s_std.c | 6 ++++-- components/esp_driver_i2s/i2s_tdm.c | 5 +++-- components/esp_driver_i2s/test_apps/i2s/main/test_i2s.c | 4 ++++ .../test_apps/i2s_multi_dev/main/test_i2s_multi_dev.c | 7 +++++++ 5 files changed, 22 insertions(+), 8 deletions(-) diff --git a/components/esp_driver_i2s/i2s_pdm.c b/components/esp_driver_i2s/i2s_pdm.c index f23e540f851..82cb7f29e9b 100644 --- a/components/esp_driver_i2s/i2s_pdm.c +++ b/components/esp_driver_i2s/i2s_pdm.c @@ -55,8 +55,8 @@ static esp_err_t i2s_pdm_tx_calculate_clock(i2s_chan_handle_t handle, const i2s_ clk_info->sclk = i2s_get_source_clk_freq(clk_cfg->clk_src, clk_info->mclk); clk_info->mclk_div = clk_info->sclk / clk_info->mclk; - /* Check if the configuration is correct */ - ESP_RETURN_ON_FALSE(clk_info->mclk_div, ESP_ERR_INVALID_ARG, TAG, "sample rate is too large"); + /* Check if the configuration is correct. Use float for check in case the mclk division might be carried up in the fine division calculation */ + ESP_RETURN_ON_FALSE(clk_info->sclk / (float)clk_info->mclk > 1.99, ESP_ERR_INVALID_ARG, TAG, "sample rate is too large"); ESP_RETURN_ON_FALSE(clk_info->mclk_div < 256, ESP_ERR_INVALID_ARG, TAG, "sample rate is too small"); #if SOC_I2S_SUPPORTS_PCM2PDM if (!handle->is_raw_pdm) { @@ -367,8 +367,8 @@ static esp_err_t i2s_pdm_rx_calculate_clock(i2s_chan_handle_t handle, const i2s_ clk_info->sclk = i2s_get_source_clk_freq(clk_cfg->clk_src, clk_info->mclk); clk_info->mclk_div = clk_info->sclk / clk_info->mclk; - /* Check if the configuration is correct */ - ESP_RETURN_ON_FALSE(clk_info->mclk_div, ESP_ERR_INVALID_ARG, TAG, "sample rate is too large"); + /* Check if the configuration is correct. Use float for check in case the mclk division might be carried up in the fine division calculation */ + ESP_RETURN_ON_FALSE(clk_info->sclk / (float)clk_info->mclk >= 0.99, ESP_ERR_INVALID_ARG, TAG, "sample rate is too large"); #if SOC_I2S_SUPPORTS_PDM2PCM if (!handle->is_raw_pdm) { /* Set down-sampling configuration */ diff --git a/components/esp_driver_i2s/i2s_std.c b/components/esp_driver_i2s/i2s_std.c index 564f2cd4f71..8c6ddc72bfa 100644 --- a/components/esp_driver_i2s/i2s_std.c +++ b/components/esp_driver_i2s/i2s_std.c @@ -51,13 +51,15 @@ static esp_err_t i2s_std_calculate_clock(i2s_chan_handle_t handle, const i2s_std #if SOC_I2S_HW_VERSION_2 clk_info->sclk = clk_cfg->clk_src == I2S_CLK_SRC_EXTERNAL ? clk_cfg->ext_clk_freq_hz : i2s_get_source_clk_freq(clk_cfg->clk_src, clk_info->mclk); + float min_mclk_div = clk_cfg->clk_src == I2S_CLK_SRC_EXTERNAL ? 0.99 : 1.99; #else clk_info->sclk = i2s_get_source_clk_freq(clk_cfg->clk_src, clk_info->mclk); + float min_mclk_div = 1.99; #endif clk_info->mclk_div = clk_info->sclk / clk_info->mclk; - /* Check if the configuration is correct */ - ESP_RETURN_ON_FALSE(clk_info->mclk_div, ESP_ERR_INVALID_ARG, TAG, "sample rate is too large for the current clock source"); + /* Check if the configuration is correct. Use float for check in case the mclk division might be carried up in the fine division calculation */ + ESP_RETURN_ON_FALSE(clk_info->sclk / (float)clk_info->mclk > min_mclk_div, ESP_ERR_INVALID_ARG, TAG, "sample rate or mclk_multiple is too large for the current clock source"); return ESP_OK; } diff --git a/components/esp_driver_i2s/i2s_tdm.c b/components/esp_driver_i2s/i2s_tdm.c index 01236591f48..8f48f91ea45 100644 --- a/components/esp_driver_i2s/i2s_tdm.c +++ b/components/esp_driver_i2s/i2s_tdm.c @@ -61,10 +61,11 @@ static esp_err_t i2s_tdm_calculate_clock(i2s_chan_handle_t handle, const i2s_tdm } clk_info->sclk = clk_cfg->clk_src == I2S_CLK_SRC_EXTERNAL ? clk_cfg->ext_clk_freq_hz : i2s_get_source_clk_freq(clk_cfg->clk_src, clk_info->mclk); + float min_mclk_div = clk_cfg->clk_src == I2S_CLK_SRC_EXTERNAL ? 0.99 : 1.99; clk_info->mclk_div = clk_info->sclk / clk_info->mclk; - /* Check if the configuration is correct */ - ESP_RETURN_ON_FALSE(clk_info->mclk_div, ESP_ERR_INVALID_ARG, TAG, "sample rate is too large for the current clock source"); + /* Check if the configuration is correct. Use float for check in case the mclk division might be carried up in the fine division calculation */ + ESP_RETURN_ON_FALSE(clk_info->sclk / (float)clk_info->mclk > min_mclk_div, ESP_ERR_INVALID_ARG, TAG, "sample rate or mclk_multiple is too large for the current clock source"); return ESP_OK; } diff --git a/components/esp_driver_i2s/test_apps/i2s/main/test_i2s.c b/components/esp_driver_i2s/test_apps/i2s/main/test_i2s.c index 43b2c705266..98908519fe5 100644 --- a/components/esp_driver_i2s/test_apps/i2s/main/test_i2s.c +++ b/components/esp_driver_i2s/test_apps/i2s/main/test_i2s.c @@ -879,7 +879,11 @@ TEST_CASE("I2S_package_lost_test", "[i2s]") TEST_ESP_OK(i2s_channel_register_event_callback(rx_handle, &cbs, &count)); uint32_t test_freq[] = {16000, 32000, 48000, 64000, 96000, 128000, 144000}; +#if CONFIG_IDF_TARGET_ESP32P4 + uint32_t test_num = 4; +#else uint32_t test_num = sizeof(test_freq) / sizeof(uint32_t); +#endif // CONFIG_IDF_TARGET_ESP32P4 uint8_t *data = (uint8_t *)calloc(TEST_RECV_BUF_LEN, sizeof(uint8_t)); size_t bytes_read = 0; int i; diff --git a/components/esp_driver_i2s/test_apps/i2s_multi_dev/main/test_i2s_multi_dev.c b/components/esp_driver_i2s/test_apps/i2s_multi_dev/main/test_i2s_multi_dev.c index b2d26c6e4b0..f39c4463516 100644 --- a/components/esp_driver_i2s/test_apps/i2s_multi_dev/main/test_i2s_multi_dev.c +++ b/components/esp_driver_i2s/test_apps/i2s_multi_dev/main/test_i2s_multi_dev.c @@ -339,6 +339,13 @@ static void test_i2s_external_clk_src(bool is_master, bool is_external) std_cfg.clk_cfg.clk_src = I2S_CLK_SRC_EXTERNAL; std_cfg.clk_cfg.ext_clk_freq_hz = 22579200; } +#if CONFIG_IDF_TARGET_ESP32P4 + else { + // Use APLL instead. + // Because the default clock source is not sufficient for 22.58M MCLK + std_cfg.clk_cfg.clk_src = I2S_CLK_SRC_APLL; + } +#endif TEST_ESP_OK(i2s_channel_init_std_mode(tx_handle, &std_cfg)); TEST_ESP_OK(i2s_channel_init_std_mode(rx_handle, &std_cfg)); From 74427172e18b49c70dc0770c73620b77ee6d8562 Mon Sep 17 00:00:00 2001 From: laokaiyao Date: Tue, 17 Dec 2024 19:05:50 +0800 Subject: [PATCH 102/118] fix(i2s): fixed i2s coverity issue --- components/esp_driver_i2s/i2s_common.c | 51 +++++++++++++++++--------- 1 file changed, 34 insertions(+), 17 deletions(-) diff --git a/components/esp_driver_i2s/i2s_common.c b/components/esp_driver_i2s/i2s_common.c index 5d23e1ef129..11487a80a22 100644 --- a/components/esp_driver_i2s/i2s_common.c +++ b/components/esp_driver_i2s/i2s_common.c @@ -749,8 +749,9 @@ static void IRAM_ATTR i2s_dma_tx_callback(void *arg) #pragma GCC diagnostic pop +#if SOC_GDMA_SUPPORTED /** - * @brief I2S DMA interrupt initialization + * @brief I2S DMA interrupt initialization (implemented by I2S dedicated DMA) * @note I2S will use GDMA if chip supports, and the interrupt is triggered by GDMA. * * @param handle I2S channel handle @@ -766,7 +767,6 @@ esp_err_t i2s_init_dma_intr(i2s_chan_handle_t handle, int intr_flag) esp_err_t ret = ESP_OK; i2s_port_t port_id = handle->controller->id; ESP_RETURN_ON_FALSE((port_id >= 0) && (port_id < SOC_I2S_NUM), ESP_ERR_INVALID_ARG, TAG, "invalid handle"); -#if SOC_GDMA_SUPPORTED /* Set GDMA trigger module */ gdma_trigger_t trig = {.periph = GDMA_TRIG_PERIPH_I2S}; @@ -808,31 +808,48 @@ esp_err_t i2s_init_dma_intr(i2s_chan_handle_t handle, int intr_flag) /* Set callback function for GDMA, the interrupt is triggered by GDMA, then the GDMA ISR will call the callback function */ ESP_GOTO_ON_ERROR(gdma_register_rx_event_callbacks(handle->dma.dma_chan, &cb, handle), err2, TAG, "Register rx callback failed"); } + return ret; +err2: + gdma_disconnect(handle->dma.dma_chan); +err1: + gdma_del_channel(handle->dma.dma_chan); + handle->dma.dma_chan = NULL; + return ret; +} #else +/** + * @brief I2S DMA interrupt initialization (implemented by I2S dedicated DMA) + * @note I2S will use GDMA if chip supports, and the interrupt is triggered by GDMA. + * + * @param handle I2S channel handle + * @param intr_flag Interrupt allocation flag + * @return + * - ESP_OK I2S DMA interrupt initialize success + * - ESP_ERR_NOT_FOUND GDMA channel not found + * - ESP_ERR_INVALID_ARG Invalid arguments + * - ESP_ERR_INVALID_STATE GDMA state error + */ +esp_err_t i2s_init_dma_intr(i2s_chan_handle_t handle, int intr_flag) +{ + esp_err_t ret = ESP_OK; + i2s_port_t port_id = handle->controller->id; + ESP_RETURN_ON_FALSE((port_id >= 0) && (port_id < SOC_I2S_NUM), ESP_ERR_INVALID_ARG, TAG, "invalid handle"); intr_flag |= handle->intr_prio_flags; /* Initialize I2S module interrupt */ if (handle->dir == I2S_DIR_TX) { - esp_intr_alloc_intrstatus(i2s_periph_signal[port_id].irq, intr_flag, - (uint32_t)i2s_ll_get_interrupt_status_reg(handle->controller->hal.dev), I2S_LL_TX_EVENT_MASK, - i2s_dma_tx_callback, handle, &handle->dma.dma_chan); + ESP_RETURN_ON_ERROR(esp_intr_alloc_intrstatus(i2s_periph_signal[port_id].irq, intr_flag, + (uint32_t)i2s_ll_get_interrupt_status_reg(handle->controller->hal.dev), I2S_LL_TX_EVENT_MASK, + i2s_dma_tx_callback, handle, &handle->dma.dma_chan), TAG, "Allocate tx dma channel failed"); } else { - esp_intr_alloc_intrstatus(i2s_periph_signal[port_id].irq, intr_flag, - (uint32_t)i2s_ll_get_interrupt_status_reg(handle->controller->hal.dev), I2S_LL_RX_EVENT_MASK, - i2s_dma_rx_callback, handle, &handle->dma.dma_chan); + ESP_RETURN_ON_ERROR(esp_intr_alloc_intrstatus(i2s_periph_signal[port_id].irq, intr_flag, + (uint32_t)i2s_ll_get_interrupt_status_reg(handle->controller->hal.dev), I2S_LL_RX_EVENT_MASK, + i2s_dma_rx_callback, handle, &handle->dma.dma_chan), TAG, "Allocate rx dma channel failed"); } /* Start DMA */ i2s_ll_enable_dma(handle->controller->hal.dev, true); -#endif // SOC_GDMA_SUPPORTED return ret; -#if SOC_GDMA_SUPPORTED -err2: - gdma_disconnect(handle->dma.dma_chan); -err1: - gdma_del_channel(handle->dma.dma_chan); - handle->dma.dma_chan = NULL; - return ret; -#endif } +#endif // SOC_GDMA_SUPPORTED static uint64_t s_i2s_get_pair_chan_gpio_mask(i2s_chan_handle_t handle) { From 0b809a1bc515cf6b784e0cd1ed4dda5e07d8caaf Mon Sep 17 00:00:00 2001 From: laokaiyao Date: Wed, 18 Dec 2024 11:27:11 +0800 Subject: [PATCH 103/118] docs(example): added troubleshooting for i2s_es8311 example Closes https://github.com/espressif/esp-idf/issues/15047 --- .../peripherals/i2s/i2s_codec/i2s_es8311/README.md | 10 ++++++++++ .../i2s_codec/i2s_es8311/main/Kconfig.projbuild | 7 +++++++ .../i2s/i2s_codec/i2s_es8311/main/example_config.h | 1 + .../i2s_codec/i2s_es8311/main/i2s_es8311_example.c | 14 +++++++++++++- 4 files changed, 31 insertions(+), 1 deletion(-) diff --git a/examples/peripherals/i2s/i2s_codec/i2s_es8311/README.md b/examples/peripherals/i2s/i2s_codec/i2s_es8311/README.md index 79aee879b64..936964f98fe 100644 --- a/examples/peripherals/i2s/i2s_codec/i2s_es8311/README.md +++ b/examples/peripherals/i2s/i2s_codec/i2s_es8311/README.md @@ -129,6 +129,11 @@ If you have a logic analyzer, you can use a logic analyzer to grab GPIO signal d | SDOUT |serial data out| GPIO_NUM_18/2 | | SDIN |serial data in | GPIO_NUM_19/3 | +Other pins like I2C please refer to `example_config.h`. + +Please note that the power amplifier on some development boards (like P4 EV board) are disabled by default, you might need to set the PA_CTRL pin to high to play the music via a speaker. +The PA_CTRL pin can be configured by `idf.py menuconfig`, please check if the PA_CTRL pin is correct on your board if the audio can only be played from the earphones but not the speaker. + ### Customize your own music The example have contained a piece of music in canon.pcm, if you want to play your own music, you can follow these steps: @@ -150,4 +155,9 @@ The example have contained a piece of music in canon.pcm, if you want to play yo * Hardware connection is not correct: run `idf.py -p PORT monitor`, and reboot your board to see if there are any output logs. * The baud rate for downloading is too high: lower your baud rate in the `menuconfig` menu, and try again. +* Failed to get audio from specker + + * The PA (Power Amplifier) on some dev-kits might be disabled by default, please check the schematic to see if PA_CTRL is connected to any GPIO or something. + * Pull-up the PA_CTRL pin either by setting that GPIO to high or by connecting it to 3.3V with a jump wire should help. + For any technical queries, please open an [issue](https://github.com/espressif/esp-idf/issues) on GitHub. We will get back to you soon. diff --git a/examples/peripherals/i2s/i2s_codec/i2s_es8311/main/Kconfig.projbuild b/examples/peripherals/i2s/i2s_codec/i2s_es8311/main/Kconfig.projbuild index 4595d6e1d8f..72ce831be62 100644 --- a/examples/peripherals/i2s/i2s_codec/i2s_es8311/main/Kconfig.projbuild +++ b/examples/peripherals/i2s/i2s_codec/i2s_es8311/main/Kconfig.projbuild @@ -56,6 +56,13 @@ menu "Example Configuration" help Set voice volume + config EXAMPLE_PA_CTRL_IO + int "Power Amplifier control IO" + default 53 if IDF_TARGET_ESP32P4 + default -1 + help + Set GPIO number for PA control. Set -1 to disable PA control. + config EXAMPLE_BSP bool "Enable Board Support Package (BSP) support" default n diff --git a/examples/peripherals/i2s/i2s_codec/i2s_es8311/main/example_config.h b/examples/peripherals/i2s/i2s_codec/i2s_es8311/main/example_config.h index 87f1cbfecd0..5c3181c4e2b 100644 --- a/examples/peripherals/i2s/i2s_codec/i2s_es8311/main/example_config.h +++ b/examples/peripherals/i2s/i2s_codec/i2s_es8311/main/example_config.h @@ -14,6 +14,7 @@ #define EXAMPLE_MCLK_MULTIPLE (384) // If not using 24-bit data width, 256 should be enough #define EXAMPLE_MCLK_FREQ_HZ (EXAMPLE_SAMPLE_RATE * EXAMPLE_MCLK_MULTIPLE) #define EXAMPLE_VOICE_VOLUME CONFIG_EXAMPLE_VOICE_VOLUME +#define EXAMPLE_PA_CTRL_IO CONFIG_EXAMPLE_PA_CTRL_IO #if CONFIG_EXAMPLE_MODE_ECHO #define EXAMPLE_MIC_GAIN CONFIG_EXAMPLE_MIC_GAIN #endif diff --git a/examples/peripherals/i2s/i2s_codec/i2s_es8311/main/i2s_es8311_example.c b/examples/peripherals/i2s/i2s_codec/i2s_es8311/main/i2s_es8311_example.c index 3abbb23efd7..d0fe16226a0 100644 --- a/examples/peripherals/i2s/i2s_codec/i2s_es8311/main/i2s_es8311_example.c +++ b/examples/peripherals/i2s/i2s_codec/i2s_es8311/main/i2s_es8311_example.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2021-2022 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2021-2024 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: CC0-1.0 */ @@ -10,6 +10,7 @@ #include "freertos/FreeRTOS.h" #include "freertos/task.h" #include "driver/i2s_std.h" +#include "driver/gpio.h" #include "esp_system.h" #include "esp_check.h" #include "es8311.h" @@ -198,6 +199,17 @@ void app_main(void) } else { ESP_LOGI(TAG, "es8311 codec init success"); } + +#if EXAMPLE_PA_CTRL_IO >= 0 + /* Enable PA by setting the PA_CTRL_IO to high, because the power amplifier on some dev-kits are disabled by default */ + gpio_config_t gpio_cfg = { + .pin_bit_mask = 1ULL << EXAMPLE_PA_CTRL_IO, + .mode = GPIO_MODE_OUTPUT, + }; + ESP_ERROR_CHECK(gpio_config(&gpio_cfg)); + ESP_ERROR_CHECK(gpio_set_level(EXAMPLE_PA_CTRL_IO, 1)); +#endif + #if CONFIG_EXAMPLE_MODE_MUSIC /* Play a piece of music in music mode */ xTaskCreate(i2s_music, "i2s_music", 4096, NULL, 5, NULL); From d04af97ae3f2e8a6412a8b5292450f508ea56c4b Mon Sep 17 00:00:00 2001 From: Armando Date: Wed, 11 Dec 2024 16:24:36 +0800 Subject: [PATCH 104/118] fix(spi_flash): fixed no_os flash API not consider cache states issue on h2/p4/c6/c5/c61 --- components/spi_flash/spi_flash_os_func_noos.c | 91 ++----------------- 1 file changed, 8 insertions(+), 83 deletions(-) diff --git a/components/spi_flash/spi_flash_os_func_noos.c b/components/spi_flash/spi_flash_os_func_noos.c index 78bdc4bc852..6843269e150 100644 --- a/components/spi_flash/spi_flash_os_func_noos.c +++ b/components/spi_flash/spi_flash_os_func_noos.c @@ -8,76 +8,21 @@ #include "sdkconfig.h" #include "esp_flash.h" #include "esp_attr.h" - #include "esp_rom_sys.h" -#if CONFIG_IDF_TARGET_ESP32 -#include "esp32/rom/cache.h" -#elif CONFIG_IDF_TARGET_ESP32S2 -#include "esp32s2/rom/cache.h" -#elif CONFIG_IDF_TARGET_ESP32S3 -#include "esp32s3/rom/ets_sys.h" -#include "esp32s3/rom/cache.h" -#elif CONFIG_IDF_TARGET_ESP32C3 -#include "esp32c3/rom/ets_sys.h" -#include "esp32c3/rom/cache.h" -#elif CONFIG_IDF_TARGET_ESP32C2 -#include "esp32c2/rom/ets_sys.h" -#include "esp32c2/rom/cache.h" -#elif CONFIG_IDF_TARGET_ESP32C6 -#include "esp32c6/rom/ets_sys.h" -#include "esp32c6/rom/cache.h" -#elif CONFIG_IDF_TARGET_ESP32C61 //TODO: IDF-9526, refactor this -#include "esp32c61/rom/ets_sys.h" -#include "esp32c61/rom/cache.h" -#elif CONFIG_IDF_TARGET_ESP32C5 -#include "esp32c5/rom/ets_sys.h" -#include "esp32c5/rom/cache.h" -#elif CONFIG_IDF_TARGET_ESP32H2 -#include "esp32h2/rom/ets_sys.h" -#include "esp32h2/rom/cache.h" -#elif CONFIG_IDF_TARGET_ESP32P4 -#include "esp32p4/rom/ets_sys.h" -#include "esp32p4/rom/cache.h" -#endif - -#include "esp_attr.h" - -#if CONFIG_IDF_TARGET_ESP32S2 || CONFIG_IDF_TARGET_ESP32S3 -typedef struct { - uint32_t icache_autoload; - uint32_t dcache_autoload; -} spi_noos_arg_t; - -static DRAM_ATTR spi_noos_arg_t spi_arg = { 0 }; -#elif CONFIG_IDF_TARGET_ESP32C3 || CONFIG_IDF_TARGET_ESP32C2 || CONFIG_IDF_TARGET_ESP32C6 || CONFIG_IDF_TARGET_ESP32H2 || CONFIG_IDF_TARGET_ESP32P4 || CONFIG_IDF_TARGET_ESP32C5 || CONFIG_IDF_TARGET_ESP32C61 -typedef struct { - uint32_t icache_autoload; -} spi_noos_arg_t; - -static DRAM_ATTR spi_noos_arg_t spi_arg = { 0 }; -#endif +#include "rom/cache.h" +#include "hal/cache_hal.h" +#include "hal/cache_ll.h" +#include "soc/soc_caps.h" static IRAM_ATTR esp_err_t start(void *arg) { #if CONFIG_IDF_TARGET_ESP32 Cache_Read_Disable(0); Cache_Read_Disable(1); -#elif CONFIG_IDF_TARGET_ESP32S2 || CONFIG_IDF_TARGET_ESP32S3 - spi_noos_arg_t *spi_arg = arg; - spi_arg->icache_autoload = Cache_Suspend_ICache(); - spi_arg->dcache_autoload = Cache_Suspend_DCache(); -#elif CONFIG_IDF_TARGET_ESP32C3 || CONFIG_IDF_TARGET_ESP32C2 || CONFIG_IDF_TARGET_ESP32C6 || CONFIG_IDF_TARGET_ESP32H2 - spi_noos_arg_t *spi_arg = arg; - spi_arg->icache_autoload = Cache_Suspend_ICache(); -#elif CONFIG_IDF_TARGET_ESP32C61 || CONFIG_IDF_TARGET_ESP32C5 - spi_noos_arg_t *spi_arg = arg; - spi_arg->icache_autoload = Cache_Suspend_Cache(); -#elif CONFIG_IDF_TARGET_ESP32P4 - spi_noos_arg_t *spi_arg = arg; - spi_arg->icache_autoload = Cache_Suspend_L2_Cache(); #else - abort(); + cache_hal_suspend(CACHE_LL_LEVEL_EXT_MEM, CACHE_TYPE_ALL); #endif + return ESP_OK; } @@ -86,26 +31,10 @@ static IRAM_ATTR esp_err_t end(void *arg) #if CONFIG_IDF_TARGET_ESP32 Cache_Read_Enable(0); Cache_Read_Enable(1); -#elif CONFIG_IDF_TARGET_ESP32S2 || CONFIG_IDF_TARGET_ESP32S3 - spi_noos_arg_t *spi_arg = arg; - Cache_Invalidate_ICache_All(); - Cache_Resume_ICache(spi_arg->icache_autoload); - Cache_Resume_DCache(spi_arg->dcache_autoload); -#elif CONFIG_IDF_TARGET_ESP32C3 || CONFIG_IDF_TARGET_ESP32C2 || CONFIG_IDF_TARGET_ESP32C6 || CONFIG_IDF_TARGET_ESP32H2 - spi_noos_arg_t *spi_arg = arg; - Cache_Invalidate_ICache_All(); - Cache_Resume_ICache(spi_arg->icache_autoload); -#elif CONFIG_IDF_TARGET_ESP32C61 || CONFIG_IDF_TARGET_ESP32C5 - spi_noos_arg_t *spi_arg = arg; - Cache_Invalidate_All(); - Cache_Resume_Cache(spi_arg->icache_autoload); -#elif CONFIG_IDF_TARGET_ESP32P4 - spi_noos_arg_t *spi_arg = arg; - Cache_Invalidate_All(CACHE_MAP_L2_CACHE); - Cache_Resume_L2_Cache(spi_arg->icache_autoload); #else - abort(); + cache_hal_resume(CACHE_LL_LEVEL_EXT_MEM, CACHE_TYPE_ALL); #endif + return ESP_OK; } @@ -137,9 +66,5 @@ esp_err_t IRAM_ATTR esp_flash_app_disable_os_functions(esp_flash_t* chip) { chip->os_func = &esp_flash_noos_functions; -#if !CONFIG_IDF_TARGET_ESP32 - chip->os_func_data = &spi_arg; -#endif - return ESP_OK; } From a3f70ef45b08d394f6a49aebc187bc240c05da17 Mon Sep 17 00:00:00 2001 From: Armando Date: Wed, 11 Dec 2024 16:26:59 +0800 Subject: [PATCH 105/118] fix(spi_flash): fixed no_os flash API not consider branch predictor on c5/c61 --- components/spi_flash/spi_flash_os_func_noos.c | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/components/spi_flash/spi_flash_os_func_noos.c b/components/spi_flash/spi_flash_os_func_noos.c index 6843269e150..a2f83f47cc2 100644 --- a/components/spi_flash/spi_flash_os_func_noos.c +++ b/components/spi_flash/spi_flash_os_func_noos.c @@ -9,6 +9,7 @@ #include "esp_flash.h" #include "esp_attr.h" #include "esp_rom_sys.h" +#include "esp_cpu.h" #include "rom/cache.h" #include "hal/cache_hal.h" #include "hal/cache_ll.h" @@ -16,6 +17,11 @@ static IRAM_ATTR esp_err_t start(void *arg) { +#if SOC_BRANCH_PREDICTOR_SUPPORTED + //branch predictor will start cache request as well + esp_cpu_branch_prediction_disable(); +#endif + #if CONFIG_IDF_TARGET_ESP32 Cache_Read_Disable(0); Cache_Read_Disable(1); @@ -35,6 +41,10 @@ static IRAM_ATTR esp_err_t end(void *arg) cache_hal_resume(CACHE_LL_LEVEL_EXT_MEM, CACHE_TYPE_ALL); #endif +#if SOC_BRANCH_PREDICTOR_SUPPORTED + esp_cpu_branch_prediction_enable(); +#endif + return ESP_OK; } From 63ea6113badc4f870a532f4b5690c90272fcb436 Mon Sep 17 00:00:00 2001 From: Armando Date: Mon, 16 Dec 2024 11:53:33 +0800 Subject: [PATCH 106/118] fix(cache): fixed cache hal ctx not initialised in app issue --- components/esp_system/port/cpu_start.c | 7 ++++++- components/hal/esp32/cache_hal_esp32.c | 7 ++++++- 2 files changed, 12 insertions(+), 2 deletions(-) diff --git a/components/esp_system/port/cpu_start.c b/components/esp_system/port/cpu_start.c index a65bb3a56bb..fa4ff6912ef 100644 --- a/components/esp_system/port/cpu_start.c +++ b/components/esp_system/port/cpu_start.c @@ -41,7 +41,6 @@ #include "soc/assist_debug_reg.h" #include "soc/system_reg.h" #include "esp32s3/rom/opi_flash.h" -#include "hal/cache_hal.h" #elif CONFIG_IDF_TARGET_ESP32C3 #include "esp32c3/rtc.h" #include "esp32c3/rom/cache.h" @@ -95,6 +94,7 @@ #include "esp_private/sleep_gpio.h" #include "hal/wdt_hal.h" #include "soc/rtc.h" +#include "hal/cache_hal.h" #include "hal/cache_ll.h" #include "hal/efuse_ll.h" #include "soc/periph_defs.h" @@ -463,6 +463,11 @@ void IRAM_ATTR call_start_cpu0(void) do_multicore_settings(); #endif +#if !CONFIG_APP_BUILD_TYPE_PURE_RAM_APP + //cache hal ctx needs to be initialised + cache_hal_init(); +#endif + // When the APP is loaded into ram for execution, some hardware initialization behaviors // in the bootloader are still necessary #if CONFIG_APP_BUILD_TYPE_RAM diff --git a/components/hal/esp32/cache_hal_esp32.c b/components/hal/esp32/cache_hal_esp32.c index 33a7b1fb265..b4f48fde260 100644 --- a/components/hal/esp32/cache_hal_esp32.c +++ b/components/hal/esp32/cache_hal_esp32.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2023-2024 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -8,6 +8,11 @@ static uint32_t s_cache_status[2]; +void cache_hal_init(void) +{ + //for compatibility +} + /** * On ESP32, The cache_hal_suspend()/cache_hal_resume() are replacements * for Cache_Read_Disable()/Cache_Read_Enable() in ROM. From 117aa74705456d69715fcf690a9b5dbc9bce0ce7 Mon Sep 17 00:00:00 2001 From: zhanghaipeng Date: Wed, 18 Dec 2024 17:07:22 +0800 Subject: [PATCH 107/118] fix(ble/bluedroid): Fixed BLE feature selection configuration --- components/bt/host/bluedroid/Kconfig.in | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/components/bt/host/bluedroid/Kconfig.in b/components/bt/host/bluedroid/Kconfig.in index 99d85eedcd0..6cacf29367a 100644 --- a/components/bt/host/bluedroid/Kconfig.in +++ b/components/bt/host/bluedroid/Kconfig.in @@ -1258,7 +1258,7 @@ config BT_BLE_50_FEATURES_SUPPORTED config BT_BLE_42_FEATURES_SUPPORTED bool "Enable BLE 4.2 features(please disable BLE 5.0 if enable BLE 4.2)" - depends on (BT_BLE_ENABLED && ((BT_CONTROLLER_ENABLED && SOC_BLE_SUPPORTED) || BT_CONTROLLER_DISABLED)) + depends on (BT_BLE_ENABLED && ((BT_CONTROLLER_ENABLED && SOC_BLE_50_SUPPORTED) || BT_CONTROLLER_DISABLED)) default n help This enables BLE 4.2 features. From 24be50e71d5bacab421d9b383f82bea11b15831e Mon Sep 17 00:00:00 2001 From: Espressif BOT Date: Sun, 24 Nov 2024 11:00:28 +0800 Subject: [PATCH 108/118] change(mbedtls/crt_bundle): Update esp_cmn_crt_bundle certificates --- components/mbedtls/esp_crt_bundle/cmn_crt_authorities.csv | 7 ++++--- docs/en/api-reference/protocols/esp_crt_bundle.rst | 2 +- docs/zh_CN/api-reference/protocols/esp_crt_bundle.rst | 2 +- 3 files changed, 6 insertions(+), 5 deletions(-) diff --git a/components/mbedtls/esp_crt_bundle/cmn_crt_authorities.csv b/components/mbedtls/esp_crt_bundle/cmn_crt_authorities.csv index 0e10c701395..eec9d2909d4 100644 --- a/components/mbedtls/esp_crt_bundle/cmn_crt_authorities.csv +++ b/components/mbedtls/esp_crt_bundle/cmn_crt_authorities.csv @@ -15,9 +15,9 @@ DigiCert,DigiCert High Assurance EV Root CA DigiCert,DigiCert TLS ECC P384 Root G5 DigiCert,DigiCert TLS RSA4096 Root G5 DigiCert,DigiCert Trusted Root G4 -GlobalSign nv-sa,GlobalSign Root CA - R3 -GlobalSign nv-sa,GlobalSign ECC Root CA - R5 GlobalSign nv-sa,GlobalSign Root CA - R6 +GlobalSign nv-sa,GlobalSign ECC Root CA - R5 +GlobalSign nv-sa,GlobalSign Root CA - R3 GlobalSign nv-sa,GlobalSign Root CA GlobalSign nv-sa,GlobalSign Root E46 GlobalSign nv-sa,GlobalSign Root R46 @@ -30,7 +30,6 @@ Google Trust Services LLC,GTS Root R1 Google Trust Services LLC,GTS Root R2 Google Trust Services LLC,GTS Root R3 Google Trust Services LLC,GTS Root R4 -"IdenTrust Services, LLC",DST Root CA X3 "IdenTrust Services, LLC",IdenTrust Commercial Root CA 1 "IdenTrust Services, LLC",IdenTrust Public Sector Root CA 1 Internet Security Research Group,ISRG Root X1 @@ -38,5 +37,7 @@ Internet Security Research Group,ISRG Root X2 Sectigo,COMODO Certification Authority Sectigo,COMODO ECC Certification Authority Sectigo,COMODO RSA Certification Authority +Sectigo,Sectigo Public Server Authentication Root E46 +Sectigo,Sectigo Public Server Authentication Root R46 Sectigo,USERTrust ECC Certification Authority Sectigo,USERTrust RSA Certification Authority diff --git a/docs/en/api-reference/protocols/esp_crt_bundle.rst b/docs/en/api-reference/protocols/esp_crt_bundle.rst index 528dcf440ff..5006b522fff 100644 --- a/docs/en/api-reference/protocols/esp_crt_bundle.rst +++ b/docs/en/api-reference/protocols/esp_crt_bundle.rst @@ -17,7 +17,7 @@ The bundle comes with the complete list of root certificates from Mozilla's NSS When generating the bundle you may choose between: * The full root certificate bundle from Mozilla, containing more than 130 certificates. The current bundle was updated Tue Nov 26 13:58:25 2024 GMT. - * A pre-selected filter list of the name of the most commonly used root certificates, reducing the amount of certificates to around 41 while still having around 90% absolute usage coverage and 99% market share coverage according to SSL certificate authorities statistics. + * A pre-selected filter list of the name of the most commonly used root certificates, reducing the amount of certificates to around 42 while still having around 93% absolute usage coverage and 99% market share coverage according to SSL certificate authorities statistics. In addition, it is possible to specify a path to a certificate file or a directory containing certificates which then will be added to the generated bundle. diff --git a/docs/zh_CN/api-reference/protocols/esp_crt_bundle.rst b/docs/zh_CN/api-reference/protocols/esp_crt_bundle.rst index 122cb1d8882..bdf445f5d16 100644 --- a/docs/zh_CN/api-reference/protocols/esp_crt_bundle.rst +++ b/docs/zh_CN/api-reference/protocols/esp_crt_bundle.rst @@ -17,7 +17,7 @@ ESP x509 证书包 API 提供了一种简便的方法，帮助你安装自定义 生成证书包时，你需选择： * 来自 Mozilla 的完整根证书包，包含超过 130 份证书。目前提供的证书包更新于 2024 年 11 月 26 日，星期一, 13:58:25 (GMT)。 -* 一组预先筛选的常用根证书。其中仅包含约 41 份证书，但根据 SSL 证书颁发机构统计数据，其绝对使用率约达到 90%，市场覆盖率约达 99%。 +* 一组预先筛选的常用根证书。其中仅包含约 42 份证书，但根据 SSL 证书颁发机构统计数据，其绝对使用率约达到 93%，市场覆盖率约达 99%。 此外，还可指定证书文件的路径或包含证书的目录，将其他证书添加到生成的证书包中。 From a69220b32deec872f9288ffae760d93b8c2f218d Mon Sep 17 00:00:00 2001 From: Roland Dobai Date: Wed, 18 Dec 2024 11:27:00 +0100 Subject: [PATCH 109/118] fix(idf_tools.py): Upgrade pip and setuptools separately This way the setuptools version dependency resolution will be done by the upgraded pip. --- tools/idf_tools.py | 10 ++++++++-- 1 file changed, 8 insertions(+), 2 deletions(-) diff --git a/tools/idf_tools.py b/tools/idf_tools.py index b818f5a7991..b5e4f024ec6 100755 --- a/tools/idf_tools.py +++ b/tools/idf_tools.py @@ -2660,8 +2660,14 @@ def action_install_python_env(args): # type: ignore constraint_file = get_constraints(idf_version) if use_constraints else None - info('Upgrading pip and setuptools...') - run_args = [virtualenv_python, '-m', 'pip', 'install', '--upgrade', 'pip', 'setuptools'] + info('Upgrading pip...') + run_args = [virtualenv_python, '-m', 'pip', 'install', '--upgrade', 'pip'] + if constraint_file: + run_args += ['--constraint', constraint_file] + subprocess.check_call(run_args, stdout=sys.stdout, stderr=sys.stderr, env=env_copy) + + info('Upgrading setuptools...') + run_args = [virtualenv_python, '-m', 'pip', 'install', '--upgrade', 'setuptools'] if constraint_file: run_args += ['--constraint', constraint_file] subprocess.check_call(run_args, stdout=sys.stdout, stderr=sys.stderr, env=env_copy) From fe48cbc3c00ca16bf6f24e6ce7508cbe66d4388f Mon Sep 17 00:00:00 2001 From: wanckl Date: Thu, 15 Aug 2024 19:22:13 +0800 Subject: [PATCH 110/118] feat(twai): c5 twaifd low level support and deprecate old types header --- .../test_apps/twai/main/test_twai_loop_back.c | 2 +- components/hal/esp32c3/include/hal/twai_ll.h | 2 +- .../hal/esp32c5/include/hal/twaifd_ll.h | 948 ++++++++++++++++++ components/hal/esp32s2/include/hal/twai_ll.h | 2 +- components/hal/esp32s3/include/hal/twai_ll.h | 2 +- components/hal/include/hal/twai_hal.h | 57 +- components/hal/include/hal/twai_types.h | 170 +--- .../hal/include/hal/twai_types_deprecated.h | 120 +++ .../esp32c5/include/soc/Kconfig.soc_caps.in | 36 + .../soc/esp32c5/include/soc/clk_tree_defs.h | 9 +- components/soc/esp32c5/include/soc/soc_caps.h | 14 +- .../soc/esp32c5/register/soc/pcr_struct.h | 99 +- .../soc/esp32c5/register/soc/twaifd_struct.h | 167 ++- components/soc/esp32c5/twai_periph.c | 31 + components/soc/include/soc/twai_periph.h | 3 + docs/doxygen/Doxyfile | 2 +- docs/en/api-reference/peripherals/twai.rst | 2 +- docs/zh_CN/api-reference/peripherals/twai.rst | 2 +- .../sg_rules/no_kconfig_in_hal_component.yml | 4 +- 19 files changed, 1365 insertions(+), 307 deletions(-) create mode 100644 components/hal/esp32c5/include/hal/twaifd_ll.h create mode 100644 components/hal/include/hal/twai_types_deprecated.h create mode 100644 components/soc/esp32c5/twai_periph.c diff --git a/components/driver/test_apps/twai/main/test_twai_loop_back.c b/components/driver/test_apps/twai/main/test_twai_loop_back.c index dccc9223054..324114b1f48 100644 --- a/components/driver/test_apps/twai/main/test_twai_loop_back.c +++ b/components/driver/test_apps/twai/main/test_twai_loop_back.c @@ -172,7 +172,7 @@ static void s_test_sleep_retention(bool allow_pd) // check if the sleep happened as expected TEST_ASSERT_EQUAL(0, sleep_ctx.sleep_request_result); -#if SOC_TWAI_SUPPORT_SLEEP_RETENTION +#if SOC_TWAI_SUPPORT_SLEEP_RETENTION && CONFIG_PM_POWER_DOWN_PERIPHERAL_IN_LIGHT_SLEEP // check if the power domain also is powered down TEST_ASSERT_EQUAL(allow_pd ? PMU_SLEEP_PD_TOP : 0, (sleep_ctx.sleep_flags) & PMU_SLEEP_PD_TOP); #endif diff --git a/components/hal/esp32c3/include/hal/twai_ll.h b/components/hal/esp32c3/include/hal/twai_ll.h index d2d713f206a..1c84232cffd 100644 --- a/components/hal/esp32c3/include/hal/twai_ll.h +++ b/components/hal/esp32c3/include/hal/twai_ll.h @@ -252,7 +252,7 @@ static inline void twai_ll_set_cmd_tx(twai_dev_t *hw) __attribute__((always_inline)) static inline void twai_ll_set_cmd_tx_single_shot(twai_dev_t *hw) { - hw->command_reg.val = 0x03; //Set command_reg.tr and command_reg.at simultaneously for single shot transmittion request + hw->command_reg.val = 0x03; //Set command_reg.tr and command_reg.at simultaneously for single shot transmission request } /** diff --git a/components/hal/esp32c5/include/hal/twaifd_ll.h b/components/hal/esp32c5/include/hal/twaifd_ll.h new file mode 100644 index 00000000000..6d8fab54c7f --- /dev/null +++ b/components/hal/esp32c5/include/hal/twaifd_ll.h @@ -0,0 +1,948 @@ +/* + * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/******************************************************************************* + * NOTICE + * The Lowlevel layer for TWAI is not public api, don't use in application code. + ******************************************************************************/ + +#pragma once + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include "soc/pcr_reg.h" +#include "soc/pcr_struct.h" +#include "soc/twaifd_reg.h" +#include "soc/twaifd_struct.h" +#include "hal/twai_types.h" +#include "hal/assert.h" +#include "hal/misc.h" + +#define TWAIFD_LL_GET_HW(num) (((num) == 0) ? (&TWAI0) : (&TWAI1)) + +#define TWAIFD_LL_ERR_BIT_ERR 0x0 // Bit Error +#define TWAIFD_LL_ERR_CRC_ERR 0x1 // CRC Error +#define TWAIFD_LL_ERR_FRM_ERR 0x2 // Form Error +#define TWAIFD_LL_ERR_ACK_ERR 0x3 // Acknowledge Error +#define TWAIFD_LL_ERR_STUF_ERR 0x4 // Stuff Error + +#define TWAIFD_LL_SSP_SRC_MEAS_OFFSET 0x0 // Using Measured Transmitter delay + SSP_OFFSET +#define TWAIFD_LL_SSP_SRC_NO_SSP 0x1 // SSP is disabled +#define TWAIFD_LL_SSP_SRC_OFFSET_ONLY 0x2 // Using SSP_OFFSET only + +#define TWAIFD_LL_TX_CMD_EMPTY TWAIFD_TXCE // Set tx buffer to "Empty" state +#define TWAIFD_LL_TX_CMD_READY TWAIFD_TXCR // Set tx buffer to "Ready" state +#define TWAIFD_LL_TX_CMD_ABORT TWAIFD_TXCA // Set tx buffer to "Aborted" state + +#define TWAIFD_LL_HW_CMD_RST_ERR_CNT TWAIFD_ERCRST // Error Counters Reset +#define TWAIFD_LL_HW_CMD_RST_RX_CNT TWAIFD_RXFCRST // Clear RX bus traffic counter +#define TWAIFD_LL_HW_CMD_RST_TX_CNT TWAIFD_TXFCRST // Clear TX bus traffic counter + +#define TWAIFD_LL_INTR_TX_DONE TWAIFD_TXI_INT_ST // Transmit Interrupt +#define TWAIFD_LL_INTR_RX_NOT_EMPTY TWAIFD_RBNEI_INT_ST // RX buffer not empty interrupt +#define TWAIFD_LL_INTR_RX_FULL TWAIFD_RXFI_INT_ST // RX buffer full interrupt +#define TWAIFD_LL_INTR_ERR_WARN TWAIFD_EWLI_INT_ST // Error Interrupt +#define TWAIFD_LL_INTR_BUS_ERR TWAIFD_BEI_INT_ST // Bus error interrupt +#define TWAIFD_LL_INTR_FSM_CHANGE TWAIFD_FCSI_INT_ST // Fault confinement state changed interrupt +#define TWAIFD_LL_INTR_ARBI_LOST TWAIFD_ALI_INT_ST // Arbitration Lost Interrupt +#define TWAIFD_LL_INTR_DATA_OVERRUN TWAIFD_DOI_INT_ST // Data Overrun Interrupt + +/** + * @brief Enable the bus clock and module clock for twai module + * + * @param twai_id Hardware ID + * @param enable true to enable, false to disable + */ +static inline void twaifd_ll_enable_bus_clock(uint8_t twai_id, bool enable) +{ + PCR.twai[twai_id].twai_conf.twai_clk_en = enable; +} + +/** + * @brief Reset the twai module + * + * @param twai_id Hardware ID + */ +static inline void twaifd_ll_reset_register(uint8_t twai_id) +{ + PCR.twai[twai_id].twai_conf.twai_rst_en = 1; + while (!PCR.twai[twai_id].twai_conf.twai_ready); +} + +/** + * @brief Set clock source for TWAI module + * + * @param twai_id Hardware ID + * @param clk_src Clock source + */ +static inline void twaifd_ll_set_clock_source(uint8_t twai_id, twai_clock_source_t clk_src) +{ + PCR.twai[twai_id].twai_func_clk_conf.twai_func_clk_sel = (clk_src == TWAI_CLK_SRC_RC_FAST) ? 1 : 0; +} + +/** + * @brief Enable TWAI module clock source + * + * @param twai_id Hardware ID + * @param enable true to enable, false to disable + */ +static inline void twaifd_ll_enable_clock(uint8_t twai_id, bool enable) +{ + PCR.twai[twai_id].twai_func_clk_conf.twai_func_clk_en = enable; +} + +/** + * @brief Waits for pending changes to take effect in the hardware. + * + * @param hw Pointer to the hardware structure. + */ +static inline void twaifd_ll_waiting_state_change(twaifd_dev_t *hw) +{ + while (!hw->int_stat.fcsi_int_st); // Wait until the change is applied +} + + +/* ---------------------------- Mode Register ------------------------------- */ +// WARNING!! Following 'mode_settings' should in same spin_lock` !!! + +/** + * @brief Reset hardware. + * + * @param hw Pointer to hardware structure. + */ +static inline void twaifd_ll_reset(twaifd_dev_t *hw) +{ + hw->mode_settings.rst = 1; +} + +/** + * @brief Enable or disable hardware. + * + * @param hw Pointer to hardware structure. + * @param enable Boolean flag to enable (true) or disable (false). + */ +static inline void twaifd_ll_enable_hw(twaifd_dev_t *hw, bool enable) +{ + hw->mode_settings.ena = enable; +} + +/** + * @brief Set operating mode of TWAI controller + * + * @param hw Start address of the TWAI registers + * @param modes Operating mode + */ +static inline void twaifd_ll_set_mode(twaifd_dev_t *hw, const twai_mode_t modes) +{ + //mode should be changed under disabled + HAL_ASSERT(hw->mode_settings.ena == 0); + + twaifd_mode_settings_reg_t opmode = {.val = hw->mode_settings.val}; + opmode.stm = (modes == TWAI_MODE_NO_ACK); + opmode.bmm = (modes == TWAI_MODE_LISTEN_ONLY); + + hw->mode_settings.val = opmode.val; +} + +/** + * @brief Set the TX retransmission limit. + * + * @param hw Pointer to the TWAI-FD device hardware. + * @param limit Retransmission limit (0-15, or negative for infinite). + */ +static inline void twaifd_ll_set_tx_retrans_limit(twaifd_dev_t *hw, int8_t limit) +{ + HAL_ASSERT(limit <= (int8_t)TWAIFD_RTRTH_V); // Check the limit is valid + hw->mode_settings.rtrle = (limit >= 0); // Enable/disable retransmissions + hw->mode_settings.rtrth = limit; // Set the limit +} + +/** + * set bit rate flexible between nominal field and data field + * when set this bit, all frame will be regarded as CANFD frame, even though nominal bit rate and data bit rate are the same + */ +static inline void twaifd_ll_enable_fd_mode(twaifd_dev_t *hw, bool ena) +{ + hw->mode_settings.fde = ena; +} + +/** + * @brief Enable or disable TX loopback + * + * @param hw Pointer to the TWAI-FD device hardware. + * @param ena Set to true to enable loopback, false to disable. + */ +static inline void twaifd_ll_enable_loopback(twaifd_dev_t *hw, bool ena) +{ + hw->mode_settings.ilbp = ena; +} + +/** + * @brief Enable or disable the RX fifo automatic increase when read to register + * + * @param hw Pointer to the TWAI-FD device hardware. + * @param ena Set to true to enable RX automatic mode, false to disable. + */ +static inline void twaifd_ll_enable_rxfifo_auto_incrase(twaifd_dev_t *hw, bool ena) +{ + hw->mode_settings.rxbam = ena; +} + +/** + * @brief Enable or disable the filter. + * + * @param hw Pointer to hardware structure. + * @param enable `true` to enable, `false` to disable. + */ +static inline void twaifd_ll_enable_filter_mode(twaifd_dev_t* hw, bool enable) +{ + // Must be called when hardware is disabled. + HAL_ASSERT(hw->mode_settings.ena == 0); + hw->mode_settings.afm = enable; +} + +/** + * @brief Set remote frame filtering behaviour. + * + * @param hw Pointer to hardware structure. + * @param en True to drop, false to Receive to next filter + */ +static inline void twaifd_ll_filter_drop_remote_frame(twaifd_dev_t* hw, bool en) +{ + hw->mode_settings.fdrf = en; +} + +/** + * @brief Get remote frame filtering behaviour. + * + * @param hw Pointer to hardware structure. + */ +static inline bool twaifd_ll_filter_is_drop_remote_frame(twaifd_dev_t* hw) +{ + return hw->mode_settings.fdrf; +} + +/** + * @brief Enable or disable the time-triggered transmission mode for the TWAI-FD peripheral. + * + * @param hw Pointer to the TWAI-FD device hardware. + * @param enable Set to true to enable time-triggered transmission mode, false to disable. + */ +static inline void twaifd_ll_enable_time_trig_trans_mode(twaifd_dev_t* hw, bool enable) +{ + hw->mode_settings.tttm = enable; +} + +/* --------------------------- Command Register ----------------------------- */ +/** + * @brief Set command to TWAIFD hardware + * + * @param hw Pointer to the TWAI-FD device hardware. + * @param commands command code refer to `TWAIFD_LL_HW_CMD_`. + */ +static inline void twaifd_ll_set_operate_cmd(twaifd_dev_t *hw, uint32_t commands) +{ + hw->command.val = commands; + while(hw->command.val & commands); +} + +/* -------------------------- Interrupt Register ---------------------------- */ + +/** + * @brief Set which interrupts are enabled + * + * @param hw Start address of the TWAI registers + * @param intr_mask mask of interrupts to enable + */ +static inline void twaifd_ll_enable_intr(twaifd_dev_t *hw, uint32_t intr_mask) +{ + hw->int_ena_set.val = intr_mask; + hw->int_ena_clr.val = ~intr_mask; +} + +/** + * @brief Get the interrupt status of the TWAI-FD peripheral. + * + * @param hw Pointer to the TWAI-FD device hardware. + * @return The current interrupt status as a 32-bit value, used with `TWAIFD_LL_INTR_`. + */ +static inline uint32_t twaifd_ll_get_intr_status(twaifd_dev_t *hw) +{ + return hw->int_stat.val; +} + +/** + * @brief Clear the specified interrupt status of the TWAI-FD peripheral. + * + * @param hw Pointer to the TWAI-FD device hardware. + * @param intr_mask The interrupt mask specifying which interrupts to clear. + */ +static inline void twaifd_ll_clr_intr_status(twaifd_dev_t *hw, uint32_t intr_mask) +{ + // this register is write to clear + hw->int_stat.val = intr_mask; +} + +/* ------------------------ Bus Timing Registers --------------------------- */ +/** + * @brief Set bus timing nominal bit rate + * + * @param hw Start address of the TWAI registers + * @param timing_param timing params + */ +static inline void twaifd_ll_set_nominal_bit_rate(twaifd_dev_t *hw, const twai_timing_config_t *timing_param) +{ + twaifd_btr_reg_t reg_w = {.val = 0}; + reg_w.brp = timing_param->brp; + reg_w.prop = timing_param->prop_seg; + reg_w.ph1 = timing_param->tseg_1; + reg_w.ph2 = timing_param->tseg_2; + reg_w.sjw = timing_param->sjw; + + hw->btr.val = reg_w.val; +} + +/** + * @brief Set bus timing for FD data section bit rate + * + * @param hw Start address of the TWAI registers + * @param timing_param_fd FD timing params + */ +static inline void twaifd_ll_set_fd_bit_rate(twaifd_dev_t *hw, const twai_timing_config_t *timing_param_fd) +{ + twaifd_btr_fd_reg_t reg_w = {.val = 0}; + reg_w.brp_fd = timing_param_fd->brp; + reg_w.prop_fd = timing_param_fd->prop_seg; + reg_w.ph1_fd = timing_param_fd->tseg_1; + reg_w.ph2_fd = timing_param_fd->tseg_2; + reg_w.sjw_fd = timing_param_fd->sjw; + + hw->btr_fd.val = reg_w.val; +} + +/** + * @brief Secondary Sample Point (SSP) config for data bitrate + * + * @param hw Start address of the TWAI registers + * @param ssp_src_code Secondary point mode config, see TWAIFD_LL_SSP_SRC_xxx. + * @param offset_val Secondary point offset based on Sync_Seg, in clock source freq. + */ +static inline void twaifd_ll_config_secondary_sample_point(twaifd_dev_t *hw, uint8_t ssp_src_code, uint8_t offset_val) +{ + hw->trv_delay_ssp_cfg.ssp_src = ssp_src_code; + HAL_FORCE_MODIFY_U32_REG_FIELD(hw->trv_delay_ssp_cfg, ssp_offset, offset_val); +} + +/* ----------------------------- ALC Register ------------------------------- */ + +/** + * @brief Get the arbitration lost field from the TWAI-FD peripheral. + * + * @param hw Pointer to the TWAI-FD device hardware. + * @return The arbitration lost ID field. + */ +static inline uint32_t twaifd_ll_get_arb_lost_field(twaifd_dev_t *hw) +{ + return hw->err_capt_retr_ctr_alc_ts_info.alc_id_field; +} + +/** + * @brief Get the bit where arbitration was lost from the TWAI-FD peripheral. + * + * @param hw Pointer to the TWAI-FD device hardware. + * @return The bit position where arbitration was lost. + */ +static inline uint32_t twaifd_ll_get_arb_lost_bit(twaifd_dev_t *hw) +{ + return hw->err_capt_retr_ctr_alc_ts_info.alc_bit; +} + +/** + * @brief Get the error code reason from the TWAI-FD peripheral. + * + * @param hw Pointer to the TWAI-FD device hardware. + * @return The error code, see `TWAIFD_LL_ERR_` + */ +static inline uint32_t twaifd_ll_get_err_reason_code(twaifd_dev_t *hw) +{ + return hw->err_capt_retr_ctr_alc_ts_info.err_type; +} + +/* ----------------------------- EWL Register ------------------------------- */ + +// this func can only use in TWAIFD_MODE_TEST, and 'mode_settings.ena' must be zero +static inline void twaifd_ll_set_err_warn_limit(twaifd_dev_t *hw, uint32_t ewl) +{ + HAL_ASSERT(hw->mode_settings.tstm); + HAL_FORCE_MODIFY_U32_REG_FIELD(hw->ewl_erp_fault_state, ew_limit, ewl); +} + +/** + * @brief Get Error Warning Limit + * + * @param hw Start address of the TWAI registers + * @return Error Warning Limit + */ +static inline uint32_t twaifd_ll_get_err_warn_limit(twaifd_dev_t *hw) +{ + return HAL_FORCE_READ_U32_REG_FIELD(hw->ewl_erp_fault_state, ew_limit); +} + +/** + * @brief Get the current fault state of the TWAI-FD peripheral. + * + * @param hw Pointer to the TWAI-FD device hardware. + * @return Fault state (bus-off, error passive, or active state). + */ +static inline twai_error_state_t twaifd_ll_get_fault_state(twaifd_dev_t *hw) +{ + if (hw->ewl_erp_fault_state.bof) { + return TWAI_ERROR_BUS_OFF; + } + if (hw->ewl_erp_fault_state.erp) { + return TWAI_ERROR_PASSIVE; + } + return TWAI_ERROR_ACTIVE; +} + +/** + * @brief Get the error count in normal mode for the TWAI-FD peripheral. + * + * @param hw Pointer to the TWAI-FD device hardware. + * @return Error count in normal mode. + */ +static inline uint32_t twaifd_ll_get_err_count_norm(twaifd_dev_t *hw) +{ + return HAL_FORCE_READ_U32_REG_FIELD(hw->err_norm_err_fd, err_norm_val); +} + +/** + * @brief Get the error count in FD mode for the TWAI-FD peripheral. + * + * @param hw Pointer to the TWAI-FD device hardware. + * @return Error count in FD mode. + */ +static inline uint32_t twaifd_ll_get_err_count_fd(twaifd_dev_t *hw) +{ + return HAL_FORCE_READ_U32_REG_FIELD(hw->err_norm_err_fd, err_fd_val); +} + +/* ------------------------ RX Error Count Register ------------------------- */ +/** + * @brief Get RX Error Counter + * + * @param hw Start address of the TWAI registers + * @return REC value + */ +static inline uint32_t twaifd_ll_get_rec(twaifd_dev_t *hw) +{ + return hw->rec_tec.rec_val; +} + +/* ------------------------ TX Error Count Register ------------------------- */ +/** + * @brief Get TX Error Counter + * + * @param hw Start address of the TWAI registers + * @return TEC value + */ +static inline uint32_t twaifd_ll_get_tec(twaifd_dev_t *hw) +{ + return hw->rec_tec.tec_val; +} + +/* ---------------------- Acceptance Filter Registers ----------------------- */ +/** + * @brief Enable or disable filter to receive basic frame with std id + * + * @param hw Pointer to the TWAI FD hardware instance + * @param filter_id The unique ID of the filter to configure + * @param en True to receive, False to drop + */ +static inline void twaifd_ll_filter_enable_basic_std(twaifd_dev_t* hw, uint8_t filter_id, bool en) +{ + HAL_ASSERT(filter_id < (SOC_TWAI_MASK_FILTER_NUM + SOC_TWAI_RANGE_FILTER_NUM)); + if (en) { + hw->filter_control_filter_status.val |= TWAIFD_FANB << (filter_id * TWAIFD_FBNB_S); + } else { + hw->filter_control_filter_status.val &= ~(TWAIFD_FANB << (filter_id * TWAIFD_FBNB_S)); + } +} + +/** + * @brief Enable or disable filter to receive basic frame with ext id + * + * @param hw Pointer to the TWAI FD hardware instance + * @param filter_id The unique ID of the filter to configure + * @param en True to receive, False to drop + */ +static inline void twaifd_ll_filter_enable_basic_ext(twaifd_dev_t* hw, uint8_t filter_id, bool en) +{ + HAL_ASSERT(filter_id < (SOC_TWAI_MASK_FILTER_NUM + SOC_TWAI_RANGE_FILTER_NUM)); + if (en) { + hw->filter_control_filter_status.val |= TWAIFD_FANE << (filter_id * TWAIFD_FBNB_S); + } else { + hw->filter_control_filter_status.val &= ~(TWAIFD_FANE << (filter_id * TWAIFD_FBNB_S)); + } +} + +/** + * @brief Enable or disable filter to receive fd frame with std id + * + * @param hw Pointer to the TWAI FD hardware instance + * @param filter_id The unique ID of the filter to configure + * @param en True to receive, False to drop + */ +static inline void twaifd_ll_filter_enable_fd_std(twaifd_dev_t* hw, uint8_t filter_id, bool en) +{ + HAL_ASSERT(filter_id < (SOC_TWAI_MASK_FILTER_NUM + SOC_TWAI_RANGE_FILTER_NUM)); + if (en) { + hw->filter_control_filter_status.val |= TWAIFD_FAFB << (filter_id * TWAIFD_FBNB_S); + } else { + hw->filter_control_filter_status.val &= ~(TWAIFD_FAFB << (filter_id * TWAIFD_FBNB_S)); + } +} + +/** + * @brief Enable or disable filter to receive fd frame with ext id + * + * @param hw Pointer to the TWAI FD hardware instance + * @param filter_id The unique ID of the filter to configure + * @param en True to receive, False to drop + */ +static inline void twaifd_ll_filter_enable_fd_ext(twaifd_dev_t* hw, uint8_t filter_id, bool en) +{ + HAL_ASSERT(filter_id < (SOC_TWAI_MASK_FILTER_NUM + SOC_TWAI_RANGE_FILTER_NUM)); + if (en) { + hw->filter_control_filter_status.val |= TWAIFD_FAFE << (filter_id * TWAIFD_FBNB_S); + } else { + hw->filter_control_filter_status.val &= ~(TWAIFD_FAFE << (filter_id * TWAIFD_FBNB_S)); + } +} + +/** + * @brief Set Bit Acceptance Filter + * @param hw Start address of the TWAI registers + * @param filter_id Filter number id + * @param code Acceptance Code + * @param mask Acceptance Mask + */ +static inline void twaifd_ll_filter_set_id_mask(twaifd_dev_t* hw, uint8_t filter_id, uint32_t code, uint32_t mask) +{ + hw->mask_filters[filter_id].filter_mask.bit_mask_val = mask; + hw->mask_filters[filter_id].filter_val.bit_val = code; +} + +/** + * @brief Set Range Acceptance Filter + * @param hw Start address of the TWAI registers + * @param filter_id Filter number id + * @param high The id range high limit + * @param low The id range low limit + */ +static inline void twaifd_ll_filter_set_range(twaifd_dev_t* hw, uint8_t filter_id, uint32_t high, uint32_t low) +{ + hw->range_filters[filter_id].ran_low.bit_ran_low_val = low; + hw->range_filters[filter_id].ran_high.bit_ran_high_val = high; +} + +/** + * @brief Enable or disable bit or range frame filtering for a specific filter. + * + * @param hw Pointer to the TWAI-FD device hardware. + * @param filter_id The ID of the filter to configure (0-2 for bit filter, 3 for range filter). + * @param enable True to enable the filter, false to disable. + */ +static inline void twaifd_ll_filter_enable(twaifd_dev_t* hw, uint8_t filter_id, bool enable) +{ + HAL_ASSERT(filter_id < (SOC_TWAI_MASK_FILTER_NUM + SOC_TWAI_RANGE_FILTER_NUM)); + twaifd_filter_control_filter_status_reg_t reg_val = {.val = hw->filter_control_filter_status.val}; + + // enable or disable filter selection + if (enable) { + reg_val.val |= BIT(filter_id + TWAIFD_SFA_S); + } else { + reg_val.val &= ~BIT(filter_id + TWAIFD_SFA_S); + } + hw->filter_control_filter_status.val = reg_val.val; +} +/* ------------------------- TX Buffer Registers ------------------------- */ + +/** + * @brief Get the number of TX buffers available. + * + * @param hw Pointer to the TWAI-FD device hardware. + * @return The number of TX buffers available. + */ +static inline uint32_t twaifd_ll_get_tx_buffer_quantity(twaifd_dev_t *hw) +{ + return hw->tx_command_txtb_info.txt_buffer_count; +} + +/** + * @brief Get the status of a specific TX buffer. + * + * @param hw Pointer to the TWAI-FD device hardware. + * @param buffer_idx Index of the TX buffer (0-7). + * @return The status of the selected TX buffer. + */ +static inline uint32_t twaifd_ll_get_tx_buffer_status(twaifd_dev_t *hw, uint8_t buffer_idx) +{ + HAL_ASSERT(buffer_idx < twaifd_ll_get_tx_buffer_quantity(hw)); // Ensure buffer index is valid + uint32_t reg_val = hw->tx_status.val; + return reg_val & (TWAIFD_TX2S_V << (TWAIFD_TX2S_S * buffer_idx)); // Get status for buffer +} + +/** + * @brief Set TX Buffer command + * + * Setting the TX command will cause the TWAI controller to attempt to transmit + * the frame stored in the TX buffer. The TX buffer will be occupied (i.e., + * locked) until TX completes. + * + * @param hw Start address of the TWAI registers + * @param buffer_idx + * @param cmd The command want to set, see `TWAIFD_LL_TX_CMD_` + */ +static inline void twaifd_ll_set_tx_cmd(twaifd_dev_t *hw, uint8_t buffer_idx, uint32_t cmd) +{ + hw->tx_command_txtb_info.val = (cmd | BIT(buffer_idx + TWAIFD_TXB1_S)); +} + +/** + * @brief Set the priority for a specific TX buffer. + * + * @param hw Pointer to the TWAI-FD device hardware. + * @param buffer_idx Index of the TX buffer (0-7). + * @param priority The priority level to set for the buffer. + */ +static inline void twaifd_ll_set_tx_buffer_priority(twaifd_dev_t *hw, uint8_t buffer_idx, uint32_t priority) +{ + HAL_ASSERT(buffer_idx < twaifd_ll_get_tx_buffer_quantity(hw)); // Ensure buffer index is valid + uint32_t reg_val = hw->tx_priority.val; + reg_val &= ~(TWAIFD_TXT1P_V << (TWAIFD_TXT2P_S * buffer_idx)); // Clear old priority + reg_val |= priority << (TWAIFD_TXT2P_S * buffer_idx); // Set new priority + hw->tx_priority.val = reg_val; +} + +/** + * @brief Copy a formatted TWAI frame into TX buffer for transmission + * + * @param hw Start address of the TWAI registers + * @param tx_frame Pointer to formatted frame + * @param buffer_idx The tx buffer index to copy in + * + * @note Call twaifd_ll_format_frame_header() and twaifd_ll_format_frame_data() to format a frame + */ +static inline void twaifd_ll_mount_tx_buffer(twaifd_dev_t *hw, twaifd_frame_buffer_t *tx_frame, uint8_t buffer_idx) +{ + //Copy formatted frame into TX buffer + for (int i = 0; i < sizeof(twaifd_frame_buffer_t) / sizeof(uint32_t); i++) { + hw->txt_mem_cell[buffer_idx].txt_buffer.words[i] = tx_frame->words[i]; + } +} + +/* ------------------------- RX Buffer Registers ------------------------- */ + +/** + * @brief Get the size of the RX buffer. + * + * @param hw Pointer to the TWAI-FD device hardware. + * @return Size of the RX buffer. + */ +static inline uint32_t twaifd_ll_get_rx_buffer_size(twaifd_dev_t *hw) +{ + return hw->rx_mem_info.rx_buff_size; +} + +/** + * @brief Get the number of frames in the RX buffer. + * + * @param hw Pointer to the TWAI-FD device hardware. + * @return Number of frames in the RX buffer. + */ +static inline uint32_t twaifd_ll_get_rx_frame_count(twaifd_dev_t *hw) +{ + return hw->rx_status_rx_settings.rxfrc; +} + +/** + * @brief Check if the RX FIFO is empty. + * + * @param hw Pointer to the TWAI-FD device hardware. + * @return 1 if RX FIFO is empty, 0 otherwise. + */ +static inline uint32_t twaifd_ll_is_rx_buffer_empty(twaifd_dev_t *hw) +{ + return hw->rx_status_rx_settings.rxe; +} + +/** + * @brief Copy a received frame from the RX buffer for parsing + * + * @param hw Start address of the TWAI registers + * @param rx_frame Pointer to store formatted frame + * + * @note Call twaifd_ll_parse_frame_header() and twaifd_ll_parse_frame_data() to parse the formatted frame + */ +static inline void twaifd_ll_get_rx_frame(twaifd_dev_t *hw, twaifd_frame_buffer_t *rx_frame) +{ + // If rx_automatic_mode enabled, hw->rx_data.rx_data should 32bit access + rx_frame->words[0] = hw->rx_data.rx_data; + for (uint8_t i = 1; i <= rx_frame->format.rwcnt; i++) { + rx_frame->words[i] = hw->rx_data.rx_data; + } + HAL_ASSERT(!hw->rx_status_rx_settings.rxmof); +} + +/* ------------------------- TWAIFD frame ------------------------- */ +/** + * @brief Format contents of a TWAI frame header into layout of TX Buffer + * + * This function encodes a message into a frame structure. The frame structure + * has an identical layout to the TX buffer, allowing the frame structure to be + * directly copied into hardware. + * + * @param[in] header Including DLC, ID, Format, etc. + * @param[in] final_dlc data length code of frame. + * @param[out] tx_frame Pointer to store formatted frame + */ +static inline void twaifd_ll_format_frame_header(const twai_frame_header_t *header, uint8_t final_dlc, twaifd_frame_buffer_t *tx_frame) +{ + HAL_ASSERT(final_dlc <= TWAIFD_FRAME_MAX_DLC); + + //Set frame information + tx_frame->format.ide = header->ide; + tx_frame->format.rtr = header->rtr; + tx_frame->format.fdf = header->fdf; + tx_frame->format.brs = header->brs; + tx_frame->format.dlc = final_dlc; + + tx_frame->timestamp_low = header->timestamp; + tx_frame->timestamp_high = header->timestamp >> 32; + + if (tx_frame->format.ide) { + tx_frame->identifier.val = (header->id & TWAI_EXT_ID_MASK); + } else { + tx_frame->identifier.identifier_base = (header->id & TWAI_STD_ID_MASK); + } +} + +/** + * @brief Format contents of a TWAI data into layout of TX Buffer + * + * This function encodes a message into a frame structure. The frame structure + * has an identical layout to the TX buffer, allowing the frame structure to be + * directly copied into hardware. + * + * @param[in] buffer Pointer to an 8 byte array containing data. + * @param[in] len data length of data buffer. + * @param[out] tx_frame Pointer to store formatted frame + */ +static inline void twaifd_ll_format_frame_data(const uint8_t *buffer, uint32_t len, twaifd_frame_buffer_t *tx_frame) +{ + HAL_ASSERT(len <= TWAIFD_FRAME_MAX_LEN); + memcpy(tx_frame->data, buffer, len); +} + +/** + * @brief Parse formatted TWAI frame header (RX Buffer Layout) into its constituent contents + * + * @param[in] rx_frame Pointer to formatted frame + * @param[out] p_frame_header Including DLC, ID, Format, etc. + */ +static inline void twaifd_ll_parse_frame_header(const twaifd_frame_buffer_t *rx_frame, twai_frame_header_t *p_frame_header) +{ + //Copy frame information + p_frame_header->ide = rx_frame->format.ide; + p_frame_header->rtr = rx_frame->format.rtr; + p_frame_header->fdf = rx_frame->format.fdf; + p_frame_header->brs = rx_frame->format.brs; + p_frame_header->esi = rx_frame->format.esi; + p_frame_header->dlc = rx_frame->format.dlc; + + p_frame_header->timestamp = rx_frame->timestamp_high; + p_frame_header->timestamp <<= 32; + p_frame_header->timestamp |= rx_frame->timestamp_low; + + if (p_frame_header->ide) { + p_frame_header->id = (rx_frame->identifier.val & TWAI_EXT_ID_MASK); + } else { + // No check with 'TWAI_STD_ID_MASK' again due to register `identifier_base` already 11 bits len + p_frame_header->id = rx_frame->identifier.identifier_base; + } +} + +/** + * @brief Parse formatted TWAI data (RX Buffer Layout) into data buffer + * + * @param[in] rx_frame Pointer to formatted frame + * @param[out] buffer Pointer to an 8 byte array to save data + * @param[in] buffer_len_limit The buffer length limit, If less then frame data length, over length data will dropped + */ +static inline void twaifd_ll_parse_frame_data(const twaifd_frame_buffer_t *rx_frame, uint8_t *buffer, int len_limit) +{ + memcpy(buffer, rx_frame->data, len_limit); +} + +/* ------------------------- Tx Rx traffic counters Register ------------------------- */ +/** + * @brief Get RX Message Counter + * + * @param hw Start address of the TWAI registers + * @return RX Message Counter + */ +static inline uint32_t twaifd_ll_get_rx_traffic_counter(twaifd_dev_t *hw) +{ + return hw->rx_fr_ctr.val; +} + +/** + * @brief Get TX Message Counter + * + * @param hw Start address of the TWAI registers + * @return TX Message Counter + */ +static inline uint32_t twaifd_ll_get_tx_traffic_counter(twaifd_dev_t *hw) +{ + return hw->tx_fr_ctr.val; +} + +/* ------------------------- Timestamp Register ------------------------- */ + +/** + * @brief Enable or disable the timer clock. + * + * @param hw Pointer to the TWAI-FD device hardware. + * @param enable True to enable, false to disable. + */ +static inline void twaifd_ll_timer_enable_clock(twaifd_dev_t *hw, bool enable) +{ + hw->timer_clk_en.clk_en = enable; +} + +/** + * @brief Enable or disable timer power. + * + * @param hw Pointer to the TWAI-FD device hardware. + * @param enable True to enable, false to disable. + */ +static inline void twaifd_ll_timer_enable(twaifd_dev_t *hw, bool enable) +{ + hw->timer_cfg.timer_ce = enable; +} + +/** + * @brief Set the timer step value. + * + * @param hw Pointer to the TWAI-FD device hardware. + * @param step Step value to set (actual step = step - 1). + */ +static inline void twaifd_ll_timer_set_step(twaifd_dev_t *hw, uint32_t step) +{ + HAL_FORCE_MODIFY_U32_REG_FIELD(hw->timer_cfg, timer_step, (step - 1)); +} + +/** + * @brief Set timer mode to up or down counter. + * + * @param hw Pointer to the TWAI-FD device hardware. + * @param up True for up counter, false for down counter. + */ +static inline void twaifd_ll_timer_set_direction(twaifd_dev_t *hw, bool up) +{ + hw->timer_cfg.timer_up_dn = up; +} + +/** + * @brief Clear or reset the timer count. + * + * @param hw Pointer to the TWAI-FD device hardware. + * @param clear True to clear count, false to set count. + */ +static inline void twaifd_ll_timer_clr_count(twaifd_dev_t *hw, bool clear) +{ + hw->timer_cfg.timer_clr = clear; +} + +/** + * @brief Set the timer preload value. + * + * @param hw Pointer to the TWAI-FD device hardware. + * @param load_value 64-bit load value. + */ +static inline void twaifd_ll_timer_set_preload_value(twaifd_dev_t *hw, uint64_t load_value) +{ + hw->timer_ld_val_h.val = (uint32_t) (load_value >> 32); + hw->timer_ld_val_l.val = (uint32_t) load_value; +} + +/** + * @brief Apply preload value + * + * @param hw Pointer to the TWAI-FD device hardware. + */ +static inline void twaifd_ll_timer_apply_preload_value(twaifd_dev_t *hw) +{ + hw->timer_cfg.timer_set = 1; +} + +/** + * @brief Set the timer alarm value. + * + * @param hw Pointer to the TWAI-FD device hardware. + * @param alarm_value 64-bit alarm value. + */ +static inline void twaifd_ll_timer_set_alarm_value(twaifd_dev_t *hw, uint64_t alarm_value) +{ + hw->timer_ct_val_h.val = (uint32_t) (alarm_value >> 32); + hw->timer_ct_val_l.val = (uint32_t) alarm_value; +} + +/** + * @brief Enable or disable timer interrupt by mask. + * + * @param hw Timer Group register base address + * @param mask Mask of interrupt events + * @param en True: enable interrupt + * False: disable interrupt + */ +static inline void twaifd_ll_timer_enable_intr(twaifd_dev_t *hw, uint32_t mask, bool en) +{ + if (en) { + hw->timer_int_ena.val |= mask; + } else { + hw->timer_int_ena.val &= ~mask; + } +} + +/** + * @brief Get the current timer interrupt status. + * + * @param hw Pointer to the TWAI-FD device hardware. + * @return Current interrupt status. + */ +static inline uint32_t twaifd_ll_timer_get_intr_status(twaifd_dev_t *hw, uint32_t mask) +{ + return hw->timer_int_st.val & mask; +} + +/** + * @brief Clear specific timer interrupts. + * + * @param hw Pointer to the TWAI-FD device hardware. + */ +static inline void twaifd_ll_timer_clr_intr_status(twaifd_dev_t *hw, uint32_t mask) +{ + hw->timer_int_clr.val = mask; +} + +#ifdef __cplusplus +} +#endif diff --git a/components/hal/esp32s2/include/hal/twai_ll.h b/components/hal/esp32s2/include/hal/twai_ll.h index 3d05c5b0bec..7068900840f 100644 --- a/components/hal/esp32s2/include/hal/twai_ll.h +++ b/components/hal/esp32s2/include/hal/twai_ll.h @@ -255,7 +255,7 @@ static inline void twai_ll_set_cmd_tx(twai_dev_t *hw) __attribute__((always_inline)) static inline void twai_ll_set_cmd_tx_single_shot(twai_dev_t *hw) { - hw->command_reg.val = 0x03; //Set command_reg.tr and command_reg.at simultaneously for single shot transmittion request + hw->command_reg.val = 0x03; //Set command_reg.tr and command_reg.at simultaneously for single shot transmission request } /** diff --git a/components/hal/esp32s3/include/hal/twai_ll.h b/components/hal/esp32s3/include/hal/twai_ll.h index 7f921438fa1..e11823397af 100644 --- a/components/hal/esp32s3/include/hal/twai_ll.h +++ b/components/hal/esp32s3/include/hal/twai_ll.h @@ -252,7 +252,7 @@ static inline void twai_ll_set_cmd_tx(twai_dev_t *hw) __attribute__((always_inline)) static inline void twai_ll_set_cmd_tx_single_shot(twai_dev_t *hw) { - hw->command_reg.val = 0x03; //Set command_reg.tr and command_reg.at simultaneously for single shot transmittion request + hw->command_reg.val = 0x03; //Set command_reg.tr and command_reg.at simultaneously for single shot transmission request } /** diff --git a/components/hal/include/hal/twai_hal.h b/components/hal/include/hal/twai_hal.h index 930b687cdc2..e50578ff808 100644 --- a/components/hal/include/hal/twai_hal.h +++ b/components/hal/include/hal/twai_hal.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2015-2022 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2015-2024 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -16,17 +16,23 @@ #include #include "sdkconfig.h" #include "soc/soc_caps.h" -#if SOC_TWAI_SUPPORTED #include "hal/twai_types.h" + +#if SOC_TWAI_SUPPORTED +#if SOC_TWAI_SUPPORT_FD +#include "hal/twaifd_ll.h" +typedef twaifd_dev_t* twai_soc_handle_t; +typedef twaifd_frame_buffer_t twai_hal_frame_t; +#else #include "hal/twai_ll.h" +typedef twai_dev_t* twai_soc_handle_t; +typedef twai_ll_frame_buffer_t twai_hal_frame_t; #endif #ifdef __cplusplus extern "C" { #endif -#if SOC_TWAI_SUPPORTED - /* ------------------------- Defines and Typedefs --------------------------- */ #define TWAI_HAL_SET_BITS(var, flag) ((var) |= (flag)) @@ -59,10 +65,8 @@ extern "C" { #define TWAI_HAL_EVENT_NEED_PERIPH_RESET (1 << 11) #endif -typedef twai_ll_frame_buffer_t twai_hal_frame_t; - typedef struct { - twai_dev_t *dev; + twai_soc_handle_t dev; // TWAI SOC layer handle (i.e. register base address) uint32_t state_flags; uint32_t clock_source_hz; #if defined(CONFIG_TWAI_ERRATA_FIX_RX_FRAME_INVALID) || defined(CONFIG_TWAI_ERRATA_FIX_RX_FIFO_CORRUPT) @@ -79,6 +83,34 @@ typedef struct { uint32_t clock_source_hz; } twai_hal_config_t; +/** + * @brief Translate TWAIFD format DLC code to bytes length + * @param[in] dlc The frame DLC code follow the FD spec + * @return The byte length of DLC stand for + */ +__attribute__((always_inline)) +static inline int twaifd_dlc2len(uint8_t dlc) { + HAL_ASSERT(dlc <= TWAIFD_FRAME_MAX_DLC); + return (dlc <= 8) ? dlc : + (dlc <= 12) ? (dlc - 8) * 4 + 8 : + (dlc <= 13) ? (dlc - 12) * 8 + 24 : + (dlc - 13) * 16 + 32; +} + +/** + * @brief Translate TWAIFD format bytes length to DLC code + * @param[in] byte_len The byte length of the message + * @return The FD adopted frame DLC code + */ +__attribute__((always_inline)) +static inline uint8_t twaifd_len2dlc(int byte_len) { + HAL_ASSERT((byte_len <= TWAIFD_FRAME_MAX_LEN) && (byte_len >= 0)); + return (byte_len <= 8) ? byte_len : + (byte_len <= 24) ? (byte_len - 8 + 3) / 4 + 8 : + (byte_len <= 32) ? (byte_len - 24 + 7) / 8 + 12 : + (byte_len - 32 + 15) / 16 + 13; +} + /** * @brief Initialize TWAI peripheral and HAL context * @@ -91,6 +123,7 @@ typedef struct { */ bool twai_hal_init(twai_hal_context_t *hal_ctx, const twai_hal_config_t *config); +#if !SOC_TWAI_SUPPORT_FD /** * @brief Deinitialize the TWAI peripheral and HAL context * @@ -300,7 +333,7 @@ static inline bool twai_hal_read_rx_buffer_and_clear(twai_hal_context_t *hal_ctx } #else if (twai_ll_get_status(hal_ctx->dev) & TWAI_LL_STATUS_DOS) { - //No need to release RX buffer as we'll be releaseing all RX frames in continuously later + //No need to release RX buffer as we'll be releasing all RX frames in continuously later return false; } #endif @@ -323,7 +356,7 @@ __attribute__((always_inline)) static inline uint32_t twai_hal_clear_rx_fifo_overrun(twai_hal_context_t *hal_ctx) { uint32_t msg_cnt = 0; - //Note: Need to keep polling th rx message counter incase another message arrives whilst clearing + //Note: Need to keep polling th rx message counter in case another message arrives whilst clearing while (twai_ll_get_rx_msg_count(hal_ctx->dev) > 0) { twai_ll_set_cmd_release_rx_buffer(hal_ctx->dev); msg_cnt++; @@ -347,7 +380,7 @@ static inline uint32_t twai_hal_clear_rx_fifo_overrun(twai_hal_context_t *hal_ct * - Checking if a reset will cancel a TX. If so, mark that we need to retry that message after the reset * - Save how many RX messages were lost due to this reset * - Enter reset mode to stop any the peripheral from receiving any bus activity - * - Store the regsiter state of the peripheral + * - Store the register state of the peripheral * * @param hal_ctx Context of the HAL layer */ @@ -381,9 +414,9 @@ static inline uint32_t twai_hal_get_reset_lost_rx_cnt(twai_hal_context_t *hal_ct return hal_ctx->rx_msg_cnt_save; } #endif //defined(CONFIG_TWAI_ERRATA_FIX_RX_FRAME_INVALID) || defined(CONFIG_TWAI_ERRATA_FIX_RX_FIFO_CORRUPT) - -#endif +#endif // !SOC_TWAI_SUPPORT_FD #ifdef __cplusplus } #endif +#endif // SOC_TWAI_SUPPORTED diff --git a/components/hal/include/hal/twai_types.h b/components/hal/include/hal/twai_types.h index d22c50d3ff1..978f4ec53d6 100644 --- a/components/hal/include/hal/twai_types.h +++ b/components/hal/include/hal/twai_types.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2015-2022 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -7,90 +7,35 @@ #pragma once #include -#include -#include "sdkconfig.h" #include "soc/soc_caps.h" #include "soc/clk_tree_defs.h" +#include "hal/twai_types_deprecated.h" //for backward competiblity, remove on 6.0 #ifdef __cplusplus extern "C" { #endif -/** - * @brief TWAI Constants - */ -#define TWAI_EXTD_ID_MASK 0x1FFFFFFF /**< Bit mask for 29 bit Extended Frame Format ID */ -#define TWAI_STD_ID_MASK 0x7FF /**< Bit mask for 11 bit Standard Frame Format ID */ -#define TWAI_FRAME_MAX_DLC 8 /**< Max data bytes allowed in TWAI */ -#define TWAI_FRAME_EXTD_ID_LEN_BYTES 4 /**< EFF ID requires 4 bytes (29bit) */ -#define TWAI_FRAME_STD_ID_LEN_BYTES 2 /**< SFF ID requires 2 bytes (11bit) */ -#define TWAI_ERR_PASS_THRESH 128 /**< Error counter threshold for error passive */ - -/** @cond */ //Doxy command to hide preprocessor definitions from docs - -/** - * @brief TWAI Message flags - * - * The message flags are used to indicate the type of message transmitted/received. - * Some flags also specify the type of transmission. - */ -#define TWAI_MSG_FLAG_NONE 0x00 /**< No message flags (Standard Frame Format) */ -#define TWAI_MSG_FLAG_EXTD 0x01 /**< Extended Frame Format (29bit ID) */ -#define TWAI_MSG_FLAG_RTR 0x02 /**< Message is a Remote Frame */ -#define TWAI_MSG_FLAG_SS 0x04 /**< Transmit as a Single Shot Transmission. Unused for received. */ -#define TWAI_MSG_FLAG_SELF 0x08 /**< Transmit as a Self Reception Request. Unused for received. */ -#define TWAI_MSG_FLAG_DLC_NON_COMP 0x10 /**< Message's Data length code is larger than 8. This will break compliance with TWAI */ - -#define TWAI_BRP_MAX SOC_TWAI_BRP_MAX /**< Maximum configurable BRP value */ -#define TWAI_BRP_MIN SOC_TWAI_BRP_MIN /**< Minimum configurable BRP value */ - +/* valid bits in TWAI ID for frame formats */ +#define TWAI_STD_ID_MASK 0x000007FFU /* Mask of the ID fields in a standard frame */ +#define TWAI_EXT_ID_MASK 0x1FFFFFFFU /* Mask of the ID fields in an extended frame */ -/** - * @brief Initializer macros for timing configuration structure - * - * The following initializer macros offer commonly found bit rates. These macros - * place the sample point at 80% or 67% of a bit time. - * - * @note The available bit rates are dependent on the chip target and ECO version. - */ -#if SOC_TWAI_BRP_MAX > 256 -#define TWAI_TIMING_CONFIG_1KBITS() {.clk_src = TWAI_CLK_SRC_DEFAULT, .quanta_resolution_hz = 20000, .brp = 0, .tseg_1 = 15, .tseg_2 = 4, .sjw = 3, .triple_sampling = false} -#define TWAI_TIMING_CONFIG_5KBITS() {.clk_src = TWAI_CLK_SRC_DEFAULT, .quanta_resolution_hz = 100000, .brp = 0, .tseg_1 = 15, .tseg_2 = 4, .sjw = 3, .triple_sampling = false} -#define TWAI_TIMING_CONFIG_10KBITS() {.clk_src = TWAI_CLK_SRC_DEFAULT, .quanta_resolution_hz = 200000, .brp = 0, .tseg_1 = 15, .tseg_2 = 4, .sjw = 3, .triple_sampling = false} -#endif // SOC_TWAI_BRP_MAX > 256 - -#if (SOC_TWAI_BRP_MAX > 128) || (CONFIG_ESP32_REV_MIN_FULL >= 200) -#define TWAI_TIMING_CONFIG_12_5KBITS() {.clk_src = TWAI_CLK_SRC_DEFAULT, .quanta_resolution_hz = 312500, .brp = 0, .tseg_1 = 16, .tseg_2 = 8, .sjw = 3, .triple_sampling = false} -#define TWAI_TIMING_CONFIG_16KBITS() {.clk_src = TWAI_CLK_SRC_DEFAULT, .quanta_resolution_hz = 400000, .brp = 0, .tseg_1 = 16, .tseg_2 = 8, .sjw = 3, .triple_sampling = false} -#define TWAI_TIMING_CONFIG_20KBITS() {.clk_src = TWAI_CLK_SRC_DEFAULT, .quanta_resolution_hz = 400000, .brp = 0, .tseg_1 = 15, .tseg_2 = 4, .sjw = 3, .triple_sampling = false} -#endif // (SOC_TWAI_BRP_MAX > 128) || (CONFIG_ESP32_REV_MIN_FULL >= 200) +/* TWAI payload length and DLC definitions */ +#define TWAI_FRAME_MAX_DLC 8 +#define TWAI_FRAME_MAX_LEN 8 -#if CONFIG_XTAL_FREQ == 32 // TWAI_CLK_SRC_XTAL = 32M -#define TWAI_TIMING_CONFIG_25KBITS() {.clk_src = TWAI_CLK_SRC_DEFAULT, .quanta_resolution_hz = 400000, .brp = 0, .tseg_1 = 11, .tseg_2 = 4, .sjw = 3, .triple_sampling = false} -#define TWAI_TIMING_CONFIG_50KBITS() {.clk_src = TWAI_CLK_SRC_DEFAULT, .quanta_resolution_hz = 1000000, .brp = 0, .tseg_1 = 15, .tseg_2 = 4, .sjw = 3, .triple_sampling = false} -#define TWAI_TIMING_CONFIG_100KBITS() {.clk_src = TWAI_CLK_SRC_DEFAULT, .quanta_resolution_hz = 2000000, .brp = 0, .tseg_1 = 15, .tseg_2 = 4, .sjw = 3, .triple_sampling = false} -#define TWAI_TIMING_CONFIG_125KBITS() {.clk_src = TWAI_CLK_SRC_DEFAULT, .quanta_resolution_hz = 4000000, .brp = 0, .tseg_1 = 23, .tseg_2 = 8, .sjw = 3, .triple_sampling = false} -#define TWAI_TIMING_CONFIG_250KBITS() {.clk_src = TWAI_CLK_SRC_DEFAULT, .quanta_resolution_hz = 4000000, .brp = 0, .tseg_1 = 11, .tseg_2 = 4, .sjw = 3, .triple_sampling = false} -#define TWAI_TIMING_CONFIG_500KBITS() {.clk_src = TWAI_CLK_SRC_DEFAULT, .quanta_resolution_hz = 8000000, .brp = 0, .tseg_1 = 11, .tseg_2 = 4, .sjw = 3, .triple_sampling = false} -#define TWAI_TIMING_CONFIG_800KBITS() {.clk_src = TWAI_CLK_SRC_DEFAULT, .quanta_resolution_hz = 16000000, .brp = 0, .tseg_1 = 15, .tseg_2 = 4, .sjw = 3, .triple_sampling = false} -#define TWAI_TIMING_CONFIG_1MBITS() {.clk_src = TWAI_CLK_SRC_DEFAULT, .quanta_resolution_hz = 16000000, .brp = 0, .tseg_1 = 11, .tseg_2 = 4, .sjw = 3, .triple_sampling = false} - -#elif CONFIG_XTAL_FREQ == 40 // TWAI_CLK_SRC_XTAL = 40M -#define TWAI_TIMING_CONFIG_25KBITS() {.clk_src = TWAI_CLK_SRC_DEFAULT, .quanta_resolution_hz = 625000, .brp = 0, .tseg_1 = 16, .tseg_2 = 8, .sjw = 3, .triple_sampling = false} -#define TWAI_TIMING_CONFIG_50KBITS() {.clk_src = TWAI_CLK_SRC_DEFAULT, .quanta_resolution_hz = 1000000, .brp = 0, .tseg_1 = 15, .tseg_2 = 4, .sjw = 3, .triple_sampling = false} -#define TWAI_TIMING_CONFIG_100KBITS() {.clk_src = TWAI_CLK_SRC_DEFAULT, .quanta_resolution_hz = 2000000, .brp = 0, .tseg_1 = 15, .tseg_2 = 4, .sjw = 3, .triple_sampling = false} -#define TWAI_TIMING_CONFIG_125KBITS() {.clk_src = TWAI_CLK_SRC_DEFAULT, .quanta_resolution_hz = 2500000, .brp = 0, .tseg_1 = 15, .tseg_2 = 4, .sjw = 3, .triple_sampling = false} -#define TWAI_TIMING_CONFIG_250KBITS() {.clk_src = TWAI_CLK_SRC_DEFAULT, .quanta_resolution_hz = 5000000, .brp = 0, .tseg_1 = 15, .tseg_2 = 4, .sjw = 3, .triple_sampling = false} -#define TWAI_TIMING_CONFIG_500KBITS() {.clk_src = TWAI_CLK_SRC_DEFAULT, .quanta_resolution_hz = 10000000, .brp = 0, .tseg_1 = 15, .tseg_2 = 4, .sjw = 3, .triple_sampling = false} -#define TWAI_TIMING_CONFIG_800KBITS() {.clk_src = TWAI_CLK_SRC_DEFAULT, .quanta_resolution_hz = 20000000, .brp = 0, .tseg_1 = 16, .tseg_2 = 8, .sjw = 3, .triple_sampling = false} -#define TWAI_TIMING_CONFIG_1MBITS() {.clk_src = TWAI_CLK_SRC_DEFAULT, .quanta_resolution_hz = 20000000, .brp = 0, .tseg_1 = 15, .tseg_2 = 4, .sjw = 3, .triple_sampling = false} -#endif //CONFIG_XTAL_FREQ +/* TWAI FD payload length and DLC definitions */ +#define TWAIFD_FRAME_MAX_DLC 15 +#define TWAIFD_FRAME_MAX_LEN 64 /** - * @brief Initializer macro for filter configuration to accept all IDs + * @brief TWAI error states */ -#define TWAI_FILTER_CONFIG_ACCEPT_ALL() {.acceptance_code = 0, .acceptance_mask = 0xFFFFFFFF, .single_filter = true} -/** @endcond */ +typedef enum { + TWAI_ERROR_ACTIVE, /**< Error active state: TEC/REC < 96 */ + TWAI_ERROR_WARNING, /**< Error warning state: TEC/REC >= 96 and < 128 */ + TWAI_ERROR_PASSIVE, /**< Error passive state: TEC/REC >= 128 and < 256 */ + TWAI_ERROR_BUS_OFF, /**< Bus-off state: TEC >= 256 (node disconnected from bus) */ +} twai_error_state_t; /** * @brief TWAI Controller operating modes @@ -102,31 +47,7 @@ typedef enum { } twai_mode_t; /** - * @brief Structure to store a TWAI message - * - * @note The flags member is deprecated - */ -typedef struct { - union { - struct { - //The order of these bits must match deprecated message flags for compatibility reasons - uint32_t extd: 1; /**< Extended Frame Format (29bit ID) */ - uint32_t rtr: 1; /**< Message is a Remote Frame */ - uint32_t ss: 1; /**< Transmit as a Single Shot Transmission. Unused for received. */ - uint32_t self: 1; /**< Transmit as a Self Reception Request. Unused for received. */ - uint32_t dlc_non_comp: 1; /**< Message's Data length code is larger than 8. This will break compliance with ISO 11898-1 */ - uint32_t reserved: 27; /**< Reserved bits */ - }; - //Todo: Deprecate flags - uint32_t flags; /**< Deprecated: Alternate way to set bits using message flags */ - }; - uint32_t identifier; /**< 11 or 29 bit identifier */ - uint8_t data_length_code; /**< Data length code */ - uint8_t data[TWAI_FRAME_MAX_DLC]; /**< Data bytes (not relevant in RTR frame) */ -} twai_message_t; - -/** - * @brief RMT group clock source + * @brief TWAI group clock source * @note User should select the clock source based on the power and resolution requirement */ #if SOC_TWAI_SUPPORTED @@ -136,32 +57,47 @@ typedef int twai_clock_source_t; #endif /** - * @brief Structure for bit timing configuration of the TWAI driver - * - * @note Macro initializers are available for this structure + * @brief TWAI baud rate timing config advanced mode + * @note Setting one of `quanta_resolution_hz` and `brp` is enough, otherwise, `brp` is not used. */ typedef struct { - twai_clock_source_t clk_src; /**< Clock source, set to 0 or TWAI_CLK_SRC_DEFAULT if you want a default clock source */ - uint32_t quanta_resolution_hz; /**< The resolution of one timing quanta, in Hz. - Note: the value of `brp` will reflected by this field if it's non-zero, otherwise, `brp` needs to be set manually */ - uint32_t brp; /**< Baudrate prescale (i.e., clock divider). Any even number from 2 to 128 for ESP32, 2 to 32768 for non-ESP32 chip. - Note: For ESP32 ECO 2 or later, multiples of 4 from 132 to 256 are also supported */ - uint8_t tseg_1; /**< Timing segment 1 (Number of time quanta, between 1 to 16) */ - uint8_t tseg_2; /**< Timing segment 2 (Number of time quanta, 1 to 8) */ - uint8_t sjw; /**< Synchronization Jump Width (Max time quanta jump for synchronize from 1 to 4) */ - bool triple_sampling; /**< Enables triple sampling when the TWAI controller samples a bit */ + twai_clock_source_t clk_src; /**< Optional, clock source, remain 0 to using TWAI_CLK_SRC_DEFAULT by default */ + uint32_t quanta_resolution_hz; /**< The resolution of one timing quanta, in Hz. If setting, brp will be ignored */ + uint32_t brp; /**< Bit rate pre-divider, clock_source_freq / brp = quanta_resolution_hz */ + uint8_t tseg_1; /**< Seg_1 length, in quanta time */ + uint8_t tseg_2; /**< Seg_2 length, in quanta time */ + uint8_t sjw; /**< Sync jump width, in quanta time */ + union { + bool en_multi_samp; /**< Multi-sampling for one bit to avoid noise and detect errors */ + bool triple_sampling; /**< Deprecate, using `en_multi_samp`, Enables triple sampling when the TWAI controller samples a bit, [deprecated("in favor of en_multi_samp")] */ + }; + uint8_t prop_seg; /**< Prop_seg length, in quanta time */ } twai_timing_config_t; /** - * @brief Structure for acceptance filter configuration of the TWAI driver (see documentation) - * - * @note Macro initializers are available for this structure + * @brief TWAI frame header/format struct type */ typedef struct { - uint32_t acceptance_code; /**< 32-bit acceptance code */ - uint32_t acceptance_mask; /**< 32-bit acceptance mask */ - bool single_filter; /**< Use Single Filter Mode (see documentation) */ -} twai_filter_config_t; + union { + struct { + uint32_t ide:1; /**< Extended Frame Format (29bit ID) */ + uint32_t rtr:1; /**< Message is a Remote Frame */ + uint32_t fdf:1; /**< TWAI 2.0: Reserved, FD: FD Frames. */ + uint32_t brs:1; /**< TWAI 2.0: Reserved, FD: Bit Rate Shift. */ + uint32_t esi:1; /**< Transmit side error indicator for received frame */ + uint32_t loopback:1; /**< Temporary transmit as loop back for this trans, if setting `TWAI_MODE_LOOP_BACK`, all transmit is loop back */ + int8_t retrans_count; /**< Re-trans count on transfer fail, -1: infinite, 0: no re-trans, others: re-trans times. */ + uint32_t reserved:18; /**< Reserved */ + }; + uint32_t format_val; /**< Frame format/type integrate value */ + }; + union { + uint64_t timestamp; /**< Timestamp for received message */ + uint64_t trigger_time; /**< Trigger time for transmitting message*/ + }; + uint32_t id; /**< message arbitration identification */ + uint8_t dlc; /**< message data length code */ +} twai_frame_header_t; #ifdef __cplusplus } diff --git a/components/hal/include/hal/twai_types_deprecated.h b/components/hal/include/hal/twai_types_deprecated.h new file mode 100644 index 00000000000..86c18022a0d --- /dev/null +++ b/components/hal/include/hal/twai_types_deprecated.h @@ -0,0 +1,120 @@ +/* + * SPDX-FileCopyrightText: 2015-2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#pragma once + +#include +#include +#include "sdkconfig.h" +#include "soc/soc_caps.h" +#include "soc/clk_tree_defs.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @brief TWAI Constants + */ +#define TWAI_EXTD_ID_MASK 0x1FFFFFFF /**< Bit mask for 29 bit Extended Frame Format ID */ +#define TWAI_FRAME_EXTD_ID_LEN_BYTES 4 /**< EFF ID requires 4 bytes (29bit) */ +#define TWAI_FRAME_STD_ID_LEN_BYTES 2 /**< SFF ID requires 2 bytes (11bit) */ +#define TWAI_ERR_PASS_THRESH 128 /**< Error counter threshold for error passive */ + +/** @cond */ //Doxy command to hide preprocessor definitions from docs + +/** + * @brief TWAI Message flags + * + * The message flags are used to indicate the type of message transmitted/received. + * Some flags also specify the type of transmission. + */ +#define TWAI_MSG_FLAG_NONE 0x00 /**< No message flags (Standard Frame Format) */ +#define TWAI_MSG_FLAG_EXTD 0x01 /**< Extended Frame Format (29bit ID) */ +#define TWAI_MSG_FLAG_RTR 0x02 /**< Message is a Remote Frame */ +#define TWAI_MSG_FLAG_SS 0x04 /**< Transmit as a Single Shot Transmission. Unused for received. */ +#define TWAI_MSG_FLAG_SELF 0x08 /**< Transmit as a Self Reception Request. Unused for received. */ +#define TWAI_MSG_FLAG_DLC_NON_COMP 0x10 /**< Message's Data length code is larger than 8. This will break compliance with TWAI */ + +#define TWAI_BRP_MAX SOC_TWAI_BRP_MAX /**< Maximum configurable BRP value */ +#define TWAI_BRP_MIN SOC_TWAI_BRP_MIN /**< Minimum configurable BRP value */ + +/** + * @brief Initializer macros for timing configuration structure + * + * The following initializer macros offer commonly found bit rates. These macros + * place the sample point at 80% or 67% of a bit time. + * + * @note The available bit rates are dependent on the chip target and ECO version. + */ +#if SOC_TWAI_BRP_MAX > 256 +#define TWAI_TIMING_CONFIG_1KBITS() {.clk_src = TWAI_CLK_SRC_DEFAULT, .quanta_resolution_hz = 20000, .brp = 0, .prop_seg = 0, .tseg_1 = 15, .tseg_2 = 4, .sjw = 3, .triple_sampling = false} +#define TWAI_TIMING_CONFIG_5KBITS() {.clk_src = TWAI_CLK_SRC_DEFAULT, .quanta_resolution_hz = 100000, .brp = 0, .prop_seg = 0, .tseg_1 = 15, .tseg_2 = 4, .sjw = 3, .triple_sampling = false} +#define TWAI_TIMING_CONFIG_10KBITS() {.clk_src = TWAI_CLK_SRC_DEFAULT, .quanta_resolution_hz = 200000, .brp = 0, .prop_seg = 0, .tseg_1 = 15, .tseg_2 = 4, .sjw = 3, .triple_sampling = false} +#endif // SOC_TWAI_BRP_MAX > 256 + +#if (SOC_TWAI_BRP_MAX > 128) || (CONFIG_ESP32_REV_MIN_FULL >= 200) +#define TWAI_TIMING_CONFIG_12_5KBITS() {.clk_src = TWAI_CLK_SRC_DEFAULT, .quanta_resolution_hz = 312500, .brp = 0, .prop_seg = 0, .tseg_1 = 16, .tseg_2 = 8, .sjw = 3, .triple_sampling = false} +#define TWAI_TIMING_CONFIG_16KBITS() {.clk_src = TWAI_CLK_SRC_DEFAULT, .quanta_resolution_hz = 400000, .brp = 0, .prop_seg = 0, .tseg_1 = 16, .tseg_2 = 8, .sjw = 3, .triple_sampling = false} +#define TWAI_TIMING_CONFIG_20KBITS() {.clk_src = TWAI_CLK_SRC_DEFAULT, .quanta_resolution_hz = 400000, .brp = 0, .prop_seg = 0, .tseg_1 = 15, .tseg_2 = 4, .sjw = 3, .triple_sampling = false} +#endif // (SOC_TWAI_BRP_MAX > 128) || (CONFIG_ESP32_REV_MIN_FULL >= 200) + +#if SOC_TWAI_CLK_SUPPORT_XTAL +#define TWAI_TIMING_CONFIG_25KBITS() {.clk_src = TWAI_CLK_SRC_DEFAULT, .quanta_resolution_hz = 500000, .brp = 0, .prop_seg = 0, .tseg_1 = 15, .tseg_2 = 4, .sjw = 3, .triple_sampling = false} +#else // APB +#define TWAI_TIMING_CONFIG_25KBITS() {.clk_src = TWAI_CLK_SRC_DEFAULT, .quanta_resolution_hz = 625000, .brp = 0, .prop_seg = 0, .tseg_1 = 16, .tseg_2 = 8, .sjw = 3, .triple_sampling = false} +#endif +#define TWAI_TIMING_CONFIG_50KBITS() {.clk_src = TWAI_CLK_SRC_DEFAULT, .quanta_resolution_hz = 1000000, .brp = 0, .prop_seg = 0, .tseg_1 = 15, .tseg_2 = 4, .sjw = 3, .triple_sampling = false} +#define TWAI_TIMING_CONFIG_100KBITS() {.clk_src = TWAI_CLK_SRC_DEFAULT, .quanta_resolution_hz = 2000000, .brp = 0, .prop_seg = 0, .tseg_1 = 15, .tseg_2 = 4, .sjw = 3, .triple_sampling = false} +#define TWAI_TIMING_CONFIG_250KBITS() {.clk_src = TWAI_CLK_SRC_DEFAULT, .quanta_resolution_hz = 4000000, .brp = 0, .prop_seg = 0, .tseg_1 = 11, .tseg_2 = 4, .sjw = 2, .triple_sampling = false} +#define TWAI_TIMING_CONFIG_500KBITS() {.clk_src = TWAI_CLK_SRC_DEFAULT, .quanta_resolution_hz = 8000000, .brp = 0, .prop_seg = 0, .tseg_1 = 11, .tseg_2 = 4, .sjw = 2, .triple_sampling = false} +#define TWAI_TIMING_CONFIG_800KBITS() {.clk_src = TWAI_CLK_SRC_DEFAULT, .quanta_resolution_hz = 8000000, .brp = 0, .prop_seg = 0, .tseg_1 = 6, .tseg_2 = 3, .sjw = 1, .triple_sampling = false} +#define TWAI_TIMING_CONFIG_1MBITS() {.clk_src = TWAI_CLK_SRC_DEFAULT, .quanta_resolution_hz = 8000000, .brp = 0, .prop_seg = 0, .tseg_1 = 5, .tseg_2 = 2, .sjw = 1, .triple_sampling = false} + +/** + * @brief Initializer macro for filter configuration to accept all IDs + */ +#define TWAI_FILTER_CONFIG_ACCEPT_ALL() {.acceptance_code = 0, .acceptance_mask = 0xFFFFFFFF, .single_filter = true} +/** @endcond */ + +/** + * @brief Structure to store a TWAI message + * + * @note The flags member is deprecated + */ +typedef struct { + union { + struct { + //The order of these bits must match deprecated message flags for compatibility reasons + uint32_t extd: 1; /**< Extended Frame Format (29bit ID) */ + uint32_t rtr: 1; /**< Message is a Remote Frame */ + uint32_t ss: 1; /**< Transmit as a Single Shot Transmission. Unused for received. */ + uint32_t self: 1; /**< Transmit as a Self Reception Request. Unused for received. */ + uint32_t dlc_non_comp: 1; /**< Message's Data length code is larger than 8. This will break compliance with ISO 11898-1 */ + uint32_t reserved: 27; /**< Reserved bits */ + }; + //Todo: Deprecate flags + uint32_t flags; /**< Deprecated: Alternate way to set bits using message flags */ + }; + uint32_t identifier; /**< 11 or 29 bit identifier */ + uint8_t data_length_code; /**< Data length code */ + uint8_t data[8]; /**< Data bytes (not relevant in RTR frame) */ +} twai_message_t; + +/** + * @brief Structure for acceptance filter configuration of the TWAI driver (see documentation) + * + * @note Macro initializers are available for this structure + */ +typedef struct { + uint32_t acceptance_code; /**< 32-bit acceptance code */ + uint32_t acceptance_mask; /**< 32-bit acceptance mask */ + bool single_filter; /**< Use Single Filter Mode (see documentation) */ +} twai_filter_config_t; + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32c5/include/soc/Kconfig.soc_caps.in b/components/soc/esp32c5/include/soc/Kconfig.soc_caps.in index bf586f05872..3c8459cdd76 100644 --- a/components/soc/esp32c5/include/soc/Kconfig.soc_caps.in +++ b/components/soc/esp32c5/include/soc/Kconfig.soc_caps.in @@ -1215,6 +1215,42 @@ config SOC_MWDT_SUPPORT_SLEEP_RETENTION bool default y +config SOC_TWAI_CONTROLLER_NUM + int + default 2 + +config SOC_TWAI_MASK_FILTER_NUM + int + default 3 + +config SOC_TWAI_RANGE_FILTER_NUM + int + default 1 + +config SOC_TWAI_BRP_MIN + int + default 1 + +config SOC_TWAI_BRP_MAX + int + default 255 + +config SOC_TWAI_CLK_SUPPORT_XTAL + bool + default y + +config SOC_TWAI_SUPPORTS_RX_STATUS + bool + default y + +config SOC_TWAI_SUPPORT_FD + bool + default y + +config SOC_TWAI_SUPPORT_TIMESTAMP + bool + default y + config SOC_EFUSE_ECDSA_KEY bool default y diff --git a/components/soc/esp32c5/include/soc/clk_tree_defs.h b/components/soc/esp32c5/include/soc/clk_tree_defs.h index 2f7d2e97176..94dbc59579b 100644 --- a/components/soc/esp32c5/include/soc/clk_tree_defs.h +++ b/components/soc/esp32c5/include/soc/clk_tree_defs.h @@ -407,14 +407,15 @@ typedef enum { /** * @brief Array initializer for all supported clock sources of TWAI */ -#define SOC_TWAI_CLKS {SOC_MOD_CLK_XTAL} +#define SOC_TWAI_CLKS {SOC_MOD_CLK_XTAL, SOC_MOD_CLK_RC_FAST} /** * @brief TWAI clock source */ -typedef enum { // TODO: [ESP32C5] IDF-8691, IDF-8692 (inherit from C6) - TWAI_CLK_SRC_XTAL = SOC_MOD_CLK_XTAL, /*!< Select XTAL as the source clock */ - TWAI_CLK_SRC_DEFAULT = SOC_MOD_CLK_XTAL, /*!< Select XTAL as the default clock choice */ +typedef enum { + TWAI_CLK_SRC_XTAL = SOC_MOD_CLK_XTAL, /*!< Select XTAL as the source clock */ + TWAI_CLK_SRC_RC_FAST = SOC_MOD_CLK_RC_FAST, /*!< Select RC_FAST as the source clock */ + TWAI_CLK_SRC_DEFAULT = SOC_MOD_CLK_XTAL, /*!< Select XTAL as the default clock choice */ } soc_periph_twai_clk_src_t; //////////////////////////////////////////////////ADC/////////////////////////////////////////////////////////////////// diff --git a/components/soc/esp32c5/include/soc/soc_caps.h b/components/soc/esp32c5/include/soc/soc_caps.h index d1323aff172..2fcf8fb1f85 100644 --- a/components/soc/esp32c5/include/soc/soc_caps.h +++ b/components/soc/esp32c5/include/soc/soc_caps.h @@ -494,11 +494,15 @@ #define SOC_MWDT_SUPPORT_SLEEP_RETENTION (1) /*-------------------------- TWAI CAPS ---------------------------------------*/ -// #define SOC_TWAI_CONTROLLER_NUM 2 -// #define SOC_TWAI_CLK_SUPPORT_XTAL 1 -// #define SOC_TWAI_BRP_MIN 2 -// #define SOC_TWAI_BRP_MAX 32768 -// #define SOC_TWAI_SUPPORTS_RX_STATUS 1 +#define SOC_TWAI_CONTROLLER_NUM 2 +#define SOC_TWAI_MASK_FILTER_NUM 3 +#define SOC_TWAI_RANGE_FILTER_NUM 1U +#define SOC_TWAI_BRP_MIN 1U +#define SOC_TWAI_BRP_MAX 255 +#define SOC_TWAI_CLK_SUPPORT_XTAL 1 +#define SOC_TWAI_SUPPORTS_RX_STATUS 1 +#define SOC_TWAI_SUPPORT_FD 1 +#define SOC_TWAI_SUPPORT_TIMESTAMP 1 /*-------------------------- eFuse CAPS----------------------------*/ // #define SOC_EFUSE_DIS_DOWNLOAD_ICACHE 1 diff --git a/components/soc/esp32c5/register/soc/pcr_struct.h b/components/soc/esp32c5/register/soc/pcr_struct.h index 15acd48aad6..299a2da15b1 100644 --- a/components/soc/esp32c5/register/soc/pcr_struct.h +++ b/components/soc/esp32c5/register/soc/pcr_struct.h @@ -267,93 +267,49 @@ typedef union { uint32_t val; } pcr_i2c_sclk_conf_reg_t; -/** Type of twai0_conf register - * TWAI0 configuration register +/** Type of twai_conf register + * TWAI configuration register */ typedef union { struct { - /** twai0_clk_en : R/W; bitpos: [0]; default: 0; - * Set 1 to enable twai0 apb clock + /** twai_clk_en : R/W; bitpos: [0]; default: 0; + * Set 1 to enable twai apb clock */ - uint32_t twai0_clk_en:1; - /** twai0_rst_en : R/W; bitpos: [1]; default: 0; - * Set 0 to reset twai0 module + uint32_t twai_clk_en:1; + /** twai_rst_en : R/W; bitpos: [1]; default: 0; + * Set 0 to reset twai module */ - uint32_t twai0_rst_en:1; - /** twai0_ready : RO; bitpos: [2]; default: 1; - * Query this field after reset twai0 module + uint32_t twai_rst_en:1; + /** twai_ready : RO; bitpos: [2]; default: 1; + * Query this field after reset twai module */ - uint32_t twai0_ready:1; + uint32_t twai_ready:1; uint32_t reserved_3:29; }; uint32_t val; -} pcr_twai0_conf_reg_t; +} pcr_twai_conf_reg_t; -/** Type of twai0_func_clk_conf register - * TWAI0_FUNC_CLK configuration register +/** Type of twai_func_clk_conf register + * TWAI_FUNC_CLK configuration register */ typedef union { struct { uint32_t reserved_0:20; - /** twai0_func_clk_sel : R/W; bitpos: [20]; default: 0; - * Configures the clock source of TWAI0.\\ + /** twai_func_clk_sel : R/W; bitpos: [20]; default: 0; + * Configures the clock source of TWAI.\\ * 0 (default): XTAL_CLK\\ * 1: RC_FAST_CLK\\ */ - uint32_t twai0_func_clk_sel:1; + uint32_t twai_func_clk_sel:1; uint32_t reserved_21:1; - /** twai0_func_clk_en : R/W; bitpos: [22]; default: 0; - * Set 1 to enable twai0 function clock + /** twai_func_clk_en : R/W; bitpos: [22]; default: 0; + * Set 1 to enable twai function clock */ - uint32_t twai0_func_clk_en:1; + uint32_t twai_func_clk_en:1; uint32_t reserved_23:9; }; uint32_t val; -} pcr_twai0_func_clk_conf_reg_t; - -/** Type of twai1_conf register - * TWAI1 configuration register - */ -typedef union { - struct { - /** twai1_clk_en : R/W; bitpos: [0]; default: 0; - * Set 1 to enable twai1 apb clock - */ - uint32_t twai1_clk_en:1; - /** twai1_rst_en : R/W; bitpos: [1]; default: 0; - * Set 0 to reset twai1 module - */ - uint32_t twai1_rst_en:1; - /** twai1_ready : RO; bitpos: [2]; default: 1; - * Query this field after reset twai1 module - */ - uint32_t twai1_ready:1; - uint32_t reserved_3:29; - }; - uint32_t val; -} pcr_twai1_conf_reg_t; - -/** Type of twai1_func_clk_conf register - * TWAI1_FUNC_CLK configuration register - */ -typedef union { - struct { - uint32_t reserved_0:20; - /** twai1_func_clk_sel : R/W; bitpos: [20]; default: 0; - * Configures the clock source of TWAI1.\\ - * 0 (default): XTAL_CLK\\ - * 1: RC_FAST_CLK\\ - */ - uint32_t twai1_func_clk_sel:1; - uint32_t reserved_21:1; - /** twai1_func_clk_en : R/W; bitpos: [22]; default: 0; - * Set 1 to enable twai1 function clock - */ - uint32_t twai1_func_clk_en:1; - uint32_t reserved_23:9; - }; - uint32_t val; -} pcr_twai1_func_clk_conf_reg_t; +} pcr_twai_func_clk_conf_reg_t; /** Type of uhci_conf register * UHCI configuration register @@ -2329,6 +2285,14 @@ typedef struct { pcr_i2c_sclk_conf_reg_t i2c_sclk_conf; } pcr_i2c_reg_t; +/** + * @brief The struct of TWAI configuration registers + */ +typedef struct { + pcr_twai_conf_reg_t twai_conf; + pcr_twai_func_clk_conf_reg_t twai_func_clk_conf; +} pcr_twai_reg_t; + typedef struct { volatile pcr_uart0_conf_reg_t uart0_conf; volatile pcr_uart0_sclk_conf_reg_t uart0_sclk_conf; @@ -2339,10 +2303,7 @@ typedef struct { volatile pcr_mspi_conf_reg_t mspi_conf; volatile pcr_mspi_clk_conf_reg_t mspi_clk_conf; volatile pcr_i2c_reg_t i2c[1]; - volatile pcr_twai0_conf_reg_t twai0_conf; - volatile pcr_twai0_func_clk_conf_reg_t twai0_func_clk_conf; - volatile pcr_twai1_conf_reg_t twai1_conf; - volatile pcr_twai1_func_clk_conf_reg_t twai1_func_clk_conf; + volatile pcr_twai_reg_t twai[2]; volatile pcr_uhci_conf_reg_t uhci_conf; volatile pcr_rmt_conf_reg_t rmt_conf; volatile pcr_rmt_sclk_conf_reg_t rmt_sclk_conf; diff --git a/components/soc/esp32c5/register/soc/twaifd_struct.h b/components/soc/esp32c5/register/soc/twaifd_struct.h index 1ab2d31c3bb..2da3e6e4472 100644 --- a/components/soc/esp32c5/register/soc/twaifd_struct.h +++ b/components/soc/esp32c5/register/soc/twaifd_struct.h @@ -1299,107 +1299,39 @@ typedef union { /** Group: filter register */ -/** Type of filter_a_mask register - * TWAI FD filter A mask value register +/** Type of filter_mask register + * TWAI FD filter mask value register */ typedef union { struct { - /** bit_mask_a_val : R/W; bitpos: [28:0]; default: 0; - * Filter A mask. The identifier format is the same as in IDENTIFIER_W of TXT buffer + /** bit_mask_val : R/W; bitpos: [28:0]; default: 0; + * Filter mask. The identifier format is the same as in IDENTIFIER_W of TXT buffer * or RX - * buffer. If filter A is not present, writes to this register have no effect and read + * buffer. If filter is not present, writes to this register have no effect and read * will return all zeroes. */ - uint32_t bit_mask_a_val:29; + uint32_t bit_mask_val:29; uint32_t reserved_29:3; }; uint32_t val; -} twaifd_filter_a_mask_reg_t; +} twaifd_filter_mask_reg_t; -/** Type of filter_a_val register - * TWAI FD filter A bit value register +/** Type of filter_val register + * TWAI FD filter bit value register */ typedef union { struct { - /** bit_val_a_val : R/W; bitpos: [28:0]; default: 0; - * Filter A value. The identifier format is the same as in IDENTIFIER_W of TXT buffer + /** bit_val : R/W; bitpos: [28:0]; default: 0; + * Filter value. The identifier format is the same as in IDENTIFIER_W of TXT buffer * or RX buffer. - * If filter A is not present, writes to this register have no effect and read will + * If filter is not present, writes to this register have no effect and read will * return all zeroes. */ - uint32_t bit_val_a_val:29; + uint32_t bit_val:29; uint32_t reserved_29:3; }; uint32_t val; -} twaifd_filter_a_val_reg_t; - -/** Type of filter_b_mask register - * TWAI FD filter B mask value register - */ -typedef union { - struct { - /** bit_mask_b_val : R/W; bitpos: [28:0]; default: 0; - * Filter B mask. The identifier format is the same as in IDENTIFIER_W of TXT buffer - * or RX - * buffer. If filter A is not present, writes to this register have no effect and read - * will return all zeroes. - */ - uint32_t bit_mask_b_val:29; - uint32_t reserved_29:3; - }; - uint32_t val; -} twaifd_filter_b_mask_reg_t; - -/** Type of filter_b_val register - * TWAI FD filter B bit value register - */ -typedef union { - struct { - /** bit_val_b_val : R/W; bitpos: [28:0]; default: 0; - * Filter B value. The identifier format is the same as in IDENTIFIER_W of TXT buffer - * or RX buffer. - * If filter A is not present, writes to this register have no effect and read will - * return all zeroes. - */ - uint32_t bit_val_b_val:29; - uint32_t reserved_29:3; - }; - uint32_t val; -} twaifd_filter_b_val_reg_t; - -/** Type of filter_c_mask register - * TWAI FD filter C mask value register - */ -typedef union { - struct { - /** bit_mask_c_val : R/W; bitpos: [28:0]; default: 0; - * Filter C mask. The identifier format is the same as in IDENTIFIER_W of TXT buffer - * or RX - * buffer. If filter A is not present, writes to this register have no effect and read - * will return all zeroes. - */ - uint32_t bit_mask_c_val:29; - uint32_t reserved_29:3; - }; - uint32_t val; -} twaifd_filter_c_mask_reg_t; - -/** Type of filter_c_val register - * TWAI FD filter C bit value register - */ -typedef union { - struct { - /** bit_val_c_val : R/W; bitpos: [28:0]; default: 0; - * Filter C value. The identifier format is the same as in IDENTIFIER_W of TXT buffer - * or RX buffer. - * If filter A is not present, writes to this register have no effect and read will - * return all zeroes. - */ - uint32_t bit_val_c_val:29; - uint32_t reserved_29:3; - }; - uint32_t val; -} twaifd_filter_c_val_reg_t; +} twaifd_filter_val_reg_t; /** Type of filter_ran_low register * TWAI FD filter range low value register @@ -1806,6 +1738,63 @@ typedef union { uint32_t val; } twaifd_date_ver_reg_t; +/** TWAI bits filter register + */ +typedef struct { + volatile twaifd_filter_mask_reg_t filter_mask; + volatile twaifd_filter_val_reg_t filter_val; +} twaifd_mask_filter_reg_t; + +/** TWAI range filter register + */ +typedef struct { + volatile twaifd_filter_ran_low_reg_t ran_low; + volatile twaifd_filter_ran_high_reg_t ran_high; +} twaifd_range_filter_reg_t; + +/** + * @brief TWAI frame buffer register types + */ +typedef union { + struct { + union { + struct { + uint32_t dlc: 4; // Data length code (0-15) + uint32_t reserved4: 1; // Reserved bit + uint32_t rtr: 1; // Remote transmission request + uint32_t ide: 1; // Identifier extension bit + uint32_t fdf: 1; // Flexible data-rate format bit + uint32_t reserved8: 1; // Reserved bit + uint32_t brs: 1; // Bit rate switch flag + uint32_t esi: 1; // Error state indicator + uint32_t rwcnt: 5; // Re-transmission counter + uint32_t reserved16: 16; // Reserved bits + }; + uint32_t val; // Complete 32-bit register value for format + } format; + + union { + struct { + uint32_t identifier_ext: 18; // Extended identifier (18 bits) + uint32_t identifier_base: 11; // Base identifier (11 bits) + uint32_t reserved29: 3; // Reserved bits + }; + uint32_t val; // Complete 32-bit register value for identifier + } identifier; + + uint32_t timestamp_low; // Lower 32 bits of timestamp + uint32_t timestamp_high; // Upper 32 bits of timestamp + uint32_t data[16]; // Data payload (16 words) + }; + uint32_t words[20]; // Raw 32-bit words for direct access +} twaifd_frame_buffer_t; + +/** TWAI frame txt buffer registers + */ +typedef struct { + volatile twaifd_frame_buffer_t txt_buffer; + uint32_t reserved_50[44]; +} twaifd_frame_mem_t; typedef struct { volatile twaifd_device_id_version_reg_t device_id_version; @@ -1823,14 +1812,8 @@ typedef struct { volatile twaifd_rec_tec_reg_t rec_tec; volatile twaifd_err_norm_err_fd_reg_t err_norm_err_fd; volatile twaifd_ctr_pres_reg_t ctr_pres; - volatile twaifd_filter_a_mask_reg_t filter_a_mask; - volatile twaifd_filter_a_val_reg_t filter_a_val; - volatile twaifd_filter_b_mask_reg_t filter_b_mask; - volatile twaifd_filter_b_val_reg_t filter_b_val; - volatile twaifd_filter_c_mask_reg_t filter_c_mask; - volatile twaifd_filter_c_val_reg_t filter_c_val; - volatile twaifd_filter_ran_low_reg_t filter_ran_low; - volatile twaifd_filter_ran_high_reg_t filter_ran_high; + volatile twaifd_mask_filter_reg_t mask_filters[3]; + volatile twaifd_range_filter_reg_t range_filters[1]; volatile twaifd_filter_control_filter_status_reg_t filter_control_filter_status; volatile twaifd_rx_mem_info_reg_t rx_mem_info; volatile twaifd_rx_pointers_reg_t rx_pointers; @@ -1847,7 +1830,9 @@ typedef struct { volatile twaifd_yolo_reg_t yolo; volatile twaifd_timestamp_low_reg_t timestamp_low; volatile twaifd_timestamp_high_reg_t timestamp_high; - uint32_t reserved_09c[974]; + uint32_t reserved_09c[25]; + volatile twaifd_frame_mem_t txt_mem_cell[8]; + uint32_t reserved_900[437]; volatile twaifd_timer_clk_en_reg_t timer_clk_en; volatile twaifd_timer_int_raw_reg_t timer_int_raw; volatile twaifd_timer_int_st_reg_t timer_int_st; diff --git a/components/soc/esp32c5/twai_periph.c b/components/soc/esp32c5/twai_periph.c new file mode 100644 index 00000000000..179116ddd28 --- /dev/null +++ b/components/soc/esp32c5/twai_periph.c @@ -0,0 +1,31 @@ +/* + * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include "soc/twai_periph.h" +#include "soc/gpio_sig_map.h" + +const twai_controller_signal_conn_t twai_controller_periph_signals = { + .controllers = { + [0] = { + .irq_id = ETS_TWAI0_INTR_SOURCE, + .timer_irq_id = ETS_TWAI0_TIMER_INTR_SOURCE, + .tx_sig = TWAI0_TX_IDX, + .rx_sig = TWAI0_RX_IDX, + .bus_off_sig = TWAI0_BUS_OFF_ON_IDX, + .clk_out_sig = TWAI0_CLKOUT_IDX, + .stand_by_sig = TWAI0_STANDBY_IDX, + }, + [1] = { + .irq_id = ETS_TWAI1_INTR_SOURCE, + .timer_irq_id = ETS_TWAI1_TIMER_INTR_SOURCE, + .tx_sig = TWAI1_TX_IDX, + .rx_sig = TWAI1_RX_IDX, + .bus_off_sig = TWAI1_BUS_OFF_ON_IDX, + .clk_out_sig = TWAI1_CLKOUT_IDX, + .stand_by_sig = TWAI1_STANDBY_IDX, + }, + } +}; diff --git a/components/soc/include/soc/twai_periph.h b/components/soc/include/soc/twai_periph.h index 89ca029f02c..8cb7682ebc7 100644 --- a/components/soc/include/soc/twai_periph.h +++ b/components/soc/include/soc/twai_periph.h @@ -24,6 +24,9 @@ typedef struct { struct { const periph_module_t module; // peripheral module const int irq_id; // interrupt source ID +#if SOC_TWAI_SUPPORT_TIMESTAMP + const int timer_irq_id; +#endif const int tx_sig; // TX signal ID in GPIO matrix const int rx_sig; // RX signal ID in GPIO matrix const int clk_out_sig; // CLK_OUT signal ID in GPIO matrix diff --git a/docs/doxygen/Doxyfile b/docs/doxygen/Doxyfile index 055c60d164c..467394d5f72 100644 --- a/docs/doxygen/Doxyfile +++ b/docs/doxygen/Doxyfile @@ -263,7 +263,7 @@ INPUT = \ $(PROJECT_PATH)/components/hal/include/hal/spi_types.h \ $(PROJECT_PATH)/components/hal/include/hal/temperature_sensor_types.h \ $(PROJECT_PATH)/components/hal/include/hal/timer_types.h \ - $(PROJECT_PATH)/components/hal/include/hal/twai_types.h \ + $(PROJECT_PATH)/components/hal/include/hal/twai_types_deprecated.h \ $(PROJECT_PATH)/components/hal/include/hal/uart_types.h \ $(PROJECT_PATH)/components/hal/include/hal/efuse_hal.h \ $(PROJECT_PATH)/components/hal/include/hal/eth_types.h \ diff --git a/docs/en/api-reference/peripherals/twai.rst b/docs/en/api-reference/peripherals/twai.rst index 310f9126c52..f93e1099e9e 100644 --- a/docs/en/api-reference/peripherals/twai.rst +++ b/docs/en/api-reference/peripherals/twai.rst @@ -613,5 +613,5 @@ Application Examples API Reference ------------- -.. include-build-file:: inc/twai_types.inc +.. include-build-file:: inc/twai_types_deprecated.inc .. include-build-file:: inc/twai.inc diff --git a/docs/zh_CN/api-reference/peripherals/twai.rst b/docs/zh_CN/api-reference/peripherals/twai.rst index 4bd78d2fe12..edf8def8142 100644 --- a/docs/zh_CN/api-reference/peripherals/twai.rst +++ b/docs/zh_CN/api-reference/peripherals/twai.rst @@ -613,5 +613,5 @@ TWAI 驱动程序通过 :cpp:type:`twai_message_t` 结构体的不同位字段 API 参考 ------------- -.. include-build-file:: inc/twai_types.inc +.. include-build-file:: inc/twai_types_deprecated.inc .. include-build-file:: inc/twai.inc diff --git a/tools/ci/sg_rules/no_kconfig_in_hal_component.yml b/tools/ci/sg_rules/no_kconfig_in_hal_component.yml index bc64f2535a3..46e8da761f5 100644 --- a/tools/ci/sg_rules/no_kconfig_in_hal_component.yml +++ b/tools/ci/sg_rules/no_kconfig_in_hal_component.yml @@ -41,7 +41,7 @@ ignores: - "components/hal/include/hal/pmu_types.h" - "components/hal/include/hal/sha_types.h" - "components/hal/include/hal/touch_sensor_legacy_types.h" - - "components/hal/include/hal/twai_types.h" + - "components/hal/include/hal/twai_types_deprecated.h" rule: any: - kind: argument_list @@ -95,7 +95,7 @@ ignores: - "components/hal/include/hal/sha_types.h" - "components/hal/include/hal/touch_sensor_legacy_types.h" - "components/hal/include/hal/twai_hal.h" - - "components/hal/include/hal/twai_types.h" + - "components/hal/include/hal/twai_types_deprecated.h" rule: kind: preproc_include has: From dd31a41303c17a31d8c9da4fce75a9f2f494ab96 Mon Sep 17 00:00:00 2001 From: Marek Fiala Date: Wed, 18 Dec 2024 13:24:15 +0100 Subject: [PATCH 111/118] fix(tools): Enable to use IDF_PATH with export.sh --- export.sh | 22 +++++++++++++++++++--- 1 file changed, 19 insertions(+), 3 deletions(-) diff --git a/export.sh b/export.sh index 2e136d3d2e0..b5adfd672ba 100644 --- a/export.sh +++ b/export.sh @@ -22,24 +22,40 @@ idf_path="." shell_type="detect" # shellcheck disable=SC2128,SC2169,SC2039,SC3054,SC3028 # ignore array expansion warning -if test -n "${BASH_SOURCE-}" +if [ -n "${BASH_SOURCE-}" ] then # shellcheck disable=SC3028,SC3054 # unreachable with 'dash' idf_path=$(dirname "${BASH_SOURCE[0]}") shell_type="bash" -elif test -n "${ZSH_VERSION-}" +elif [ -n "${ZSH_VERSION-}" ] then # shellcheck disable=SC2296 # ignore parameter starts with '{' because it's zsh idf_path=$(dirname "${(%):-%x}") shell_type="zsh" +elif [ -n "${IDF_PATH-}" ] +then + if [ -f "/.dockerenv" ] + then + echo "Using the IDF_PATH found in the environment as docker environment detected." + idf_path=$IDF_PATH + elif [ -n "${IDF_PATH_FORCE-}" ] + then + echo "Using the forced IDF_PATH found in the environment." + idf_path=$IDF_PATH + fi fi if [ ! -f "${idf_path}/tools/idf.py" ] || [ ! -f "${idf_path}/tools/idf_tools.py" ] || [ ! -f "${idf_path}/tools/activate.py" ] then - echo "Could not detect IDF_PATH. Please navigate to your ESP-IDF directory and run:" + echo "Could not automatically detect IDF_PATH from script location. Please navigate to your ESP-IDF directory and run:" echo ". ./export.sh" + if [ -n "${IDF_PATH-}" ] + then + echo + echo "To use the IDF_PATH set in the environment, you can enforce it by setting 'export IDF_PATH_FORCE=1'" + fi unset idf_path return 1 fi From 4d9d1645418277c045923c25696a2481c4dd281f Mon Sep 17 00:00:00 2001 From: Ihor Nehrutsa Date: Fri, 22 Nov 2024 23:55:21 +0200 Subject: [PATCH 112/118] feat(gpio): Add gpio_get_io_config() Signed-off-by: IhorNehrutsa --- .../esp_driver_gpio/include/driver/gpio.h | 22 +++++++++++++++++++ components/esp_driver_gpio/src/gpio.c | 11 +++++++++- 2 files changed, 32 insertions(+), 1 deletion(-) diff --git a/components/esp_driver_gpio/include/driver/gpio.h b/components/esp_driver_gpio/include/driver/gpio.h index 4d5d63b57c0..761d6145e96 100644 --- a/components/esp_driver_gpio/include/driver/gpio.h +++ b/components/esp_driver_gpio/include/driver/gpio.h @@ -590,6 +590,28 @@ esp_err_t gpio_deep_sleep_wakeup_disable(gpio_num_t gpio_num); */ esp_err_t gpio_dump_io_configuration(FILE *out_stream, uint64_t io_bit_mask); +/** + * @brief Get the configuration for an IO + * + * @param gpio_num GPIO number + * @param pu Pull-up enabled or not + * @param pd Pull-down enabled or not + * @param ie Input enabled or not + * @param oe Output enabled or not + * @param od Open-drain enabled or not + * @param drv Drive strength value + * @param fun_sel IOMUX function selection value + * @param sig_out Outputting peripheral signal index + * @param slp_sel Pin sleep mode enabled or not + * + * @return + * - ESP_OK Success + * - ESP_ERR_INVALID_ARG Parameter error + */ +esp_err_t gpio_get_io_config(uint32_t gpio_num, + bool *pu, bool *pd, bool *ie, bool *oe, bool *od, uint32_t *drv, + uint32_t *fun_sel, uint32_t *sig_out, bool *slp_sel); + #ifdef __cplusplus } #endif diff --git a/components/esp_driver_gpio/src/gpio.c b/components/esp_driver_gpio/src/gpio.c index a63ab11375a..5f7862aa99e 100644 --- a/components/esp_driver_gpio/src/gpio.c +++ b/components/esp_driver_gpio/src/gpio.c @@ -1055,7 +1055,16 @@ esp_err_t gpio_dump_io_configuration(FILE *out_stream, uint64_t io_bit_mask) fprintf(out_stream, " SleepSelEn: %d\n", slp_sel); fprintf(out_stream, "\n"); } - fprintf(out_stream, "=================IO DUMP End==================\n"); + fprintf(out_stream, "=================IO DUMP End=================\n"); + return ESP_OK; +} + +esp_err_t gpio_get_io_config(uint32_t gpio_num, + bool *pu, bool *pd, bool *ie, bool *oe, bool *od, uint32_t *drv, + uint32_t *fun_sel, uint32_t *sig_out, bool *slp_sel) +{ + GPIO_CHECK(GPIO_IS_VALID_GPIO(gpio_num), "GPIO number error", ESP_ERR_INVALID_ARG); + gpio_hal_get_io_config(gpio_context.gpio_hal, gpio_num, pu, pd, ie, oe, od, drv, fun_sel, sig_out, slp_sel); return ESP_OK; } From c749ec66f64527e09f2f1d50919914deca085e5c Mon Sep 17 00:00:00 2001 From: Song Ruo Jing Date: Fri, 13 Dec 2024 17:40:31 +0800 Subject: [PATCH 113/118] fix(gpio): fix pu, pd, drv value incorrect from gpio_dump_io_configuration on esp32 Closes https://github.com/espressif/esp-idf/issues/14931 --- .../esp_driver_gpio/include/driver/gpio.h | 20 ++--- components/esp_driver_gpio/src/gpio.c | 49 +++++++---- components/esp_hw_support/esp_gpio_reserve.c | 2 +- components/hal/esp32/include/hal/gpio_ll.h | 36 ++++++-- components/hal/esp32/include/hal/rtc_io_ll.h | 35 +++++++- components/hal/esp32c2/include/hal/gpio_ll.h | 36 ++++++-- components/hal/esp32c3/include/hal/gpio_ll.h | 82 +++++++++++------- components/hal/esp32c5/include/hal/gpio_ll.h | 37 +++++--- .../hal/esp32c5/include/hal/rtc_io_ll.h | 22 +++++ components/hal/esp32c6/include/hal/gpio_ll.h | 36 ++++++-- .../hal/esp32c6/include/hal/rtc_io_ll.h | 22 +++++ components/hal/esp32c61/include/hal/gpio_ll.h | 36 ++++++-- .../hal/esp32c61/include/hal/rtc_io_ll.h | 22 +++++ components/hal/esp32h2/include/hal/gpio_ll.h | 36 ++++++-- components/hal/esp32p4/include/hal/gpio_ll.h | 36 ++++++-- .../hal/esp32p4/include/hal/rtc_io_ll.h | 22 +++++ components/hal/esp32s2/include/hal/gpio_ll.h | 36 ++++++-- .../hal/esp32s2/include/hal/rtc_io_ll.h | 35 +++++++- components/hal/esp32s3/include/hal/gpio_ll.h | 84 +++++++++++-------- .../hal/esp32s3/include/hal/rtc_io_ll.h | 31 +++++++ components/hal/include/hal/rtc_io_hal.h | 16 ++++ 21 files changed, 564 insertions(+), 167 deletions(-) diff --git a/components/esp_driver_gpio/include/driver/gpio.h b/components/esp_driver_gpio/include/driver/gpio.h index 761d6145e96..b5822a55a09 100644 --- a/components/esp_driver_gpio/include/driver/gpio.h +++ b/components/esp_driver_gpio/include/driver/gpio.h @@ -594,21 +594,21 @@ esp_err_t gpio_dump_io_configuration(FILE *out_stream, uint64_t io_bit_mask); * @brief Get the configuration for an IO * * @param gpio_num GPIO number - * @param pu Pull-up enabled or not - * @param pd Pull-down enabled or not - * @param ie Input enabled or not - * @param oe Output enabled or not - * @param od Open-drain enabled or not - * @param drv Drive strength value - * @param fun_sel IOMUX function selection value - * @param sig_out Outputting peripheral signal index - * @param slp_sel Pin sleep mode enabled or not + * @param pu Pointer to accept the status of pull-up enabled or not, passing in NULL if this info is unwanted + * @param pd Pointer to accept the status of pull-down enabled or not, passing in NULL if this info is unwanted + * @param ie Pointer to accept the status of input enabled or not, passing in NULL if this info is unwanted + * @param oe Pointer to accept the status of output enabled or not, passing in NULL if this info is unwanted + * @param od Pointer to accept the status of open-drain enabled or not, passing in NULL if this info is unwanted + * @param drv Pointer to accept the value of drive strength, passing in NULL if this info is unwanted + * @param fun_sel Pointer to accept the value of IOMUX function selection, passing in NULL if this info is unwanted + * @param sig_out Pointer to accept the index of outputting peripheral signal, passing in NULL if this info is unwanted + * @param slp_sel Pointer to accept the status of pin sleep mode enabled or not, passing in NULL if this info is unwanted * * @return * - ESP_OK Success * - ESP_ERR_INVALID_ARG Parameter error */ -esp_err_t gpio_get_io_config(uint32_t gpio_num, +esp_err_t gpio_get_io_config(gpio_num_t gpio_num, bool *pu, bool *pd, bool *ie, bool *oe, bool *od, uint32_t *drv, uint32_t *fun_sel, uint32_t *sig_out, bool *slp_sel); diff --git a/components/esp_driver_gpio/src/gpio.c b/components/esp_driver_gpio/src/gpio.c index 5f7862aa99e..eb8bac60c86 100644 --- a/components/esp_driver_gpio/src/gpio.c +++ b/components/esp_driver_gpio/src/gpio.c @@ -75,7 +75,7 @@ static gpio_context_t gpio_context = { esp_err_t gpio_pullup_en(gpio_num_t gpio_num) { - GPIO_CHECK(GPIO_IS_VALID_GPIO(gpio_num), "GPIO number error", ESP_ERR_INVALID_ARG); + GPIO_CHECK(GPIO_IS_VALID_OUTPUT_GPIO(gpio_num), "GPIO number error", ESP_ERR_INVALID_ARG); if (!rtc_gpio_is_valid_gpio(gpio_num) || SOC_GPIO_SUPPORT_RTC_INDEPENDENT) { portENTER_CRITICAL(&gpio_context.gpio_spinlock); @@ -113,7 +113,7 @@ esp_err_t gpio_pullup_dis(gpio_num_t gpio_num) esp_err_t gpio_pulldown_en(gpio_num_t gpio_num) { - GPIO_CHECK(GPIO_IS_VALID_GPIO(gpio_num), "GPIO number error", ESP_ERR_INVALID_ARG); + GPIO_CHECK(GPIO_IS_VALID_OUTPUT_GPIO(gpio_num), "GPIO number error", ESP_ERR_INVALID_ARG); if (!rtc_gpio_is_valid_gpio(gpio_num) || SOC_GPIO_SUPPORT_RTC_INDEPENDENT) { portENTER_CRITICAL(&gpio_context.gpio_spinlock); @@ -1017,6 +1017,29 @@ esp_err_t gpio_deep_sleep_wakeup_disable(gpio_num_t gpio_num) } #endif // SOC_GPIO_SUPPORT_DEEPSLEEP_WAKEUP && SOC_DEEP_SLEEP_SUPPORTED +esp_err_t gpio_get_io_config(gpio_num_t gpio_num, + bool *pu, bool *pd, bool *ie, bool *oe, bool *od, uint32_t *drv, + uint32_t *fun_sel, uint32_t *sig_out, bool *slp_sel) +{ + GPIO_CHECK(GPIO_IS_VALID_GPIO(gpio_num), "GPIO number error", ESP_ERR_INVALID_ARG); + gpio_hal_get_io_config(gpio_context.gpio_hal, gpio_num, pu, pd, ie, oe, od, drv, fun_sel, sig_out, slp_sel); +#if !SOC_GPIO_SUPPORT_RTC_INDEPENDENT && SOC_RTCIO_PIN_COUNT > 0 + if (rtc_gpio_is_valid_gpio(gpio_num)) { + int rtcio_num = rtc_io_number_get(gpio_num); + if (pu) { + *pu = rtcio_hal_is_pullup_enabled(rtcio_num); + } + if (pd) { + *pd = rtcio_hal_is_pulldown_enabled(rtcio_num); + } + if (drv) { + *drv = rtcio_hal_get_drive_capability(rtcio_num); + } + } +#endif + return ESP_OK; +} + esp_err_t gpio_dump_io_configuration(FILE *out_stream, uint64_t io_bit_mask) { ESP_RETURN_ON_FALSE(out_stream, ESP_ERR_INVALID_ARG, GPIO_TAG, "out_stream error"); @@ -1027,9 +1050,16 @@ esp_err_t gpio_dump_io_configuration(FILE *out_stream, uint64_t io_bit_mask) uint32_t gpio_num = __builtin_ffsll(io_bit_mask) - 1; io_bit_mask &= ~(1ULL << gpio_num); - bool pu, pd, ie, oe, od, slp_sel; - uint32_t drv, fun_sel, sig_out; - gpio_hal_get_io_config(gpio_context.gpio_hal, gpio_num, &pu, &pd, &ie, &oe, &od, &drv, &fun_sel, &sig_out, &slp_sel); + bool pu = 0; + bool pd = 0; + bool ie = 0; + bool oe = 0; + bool od = 0; + bool slp_sel = 0; + uint32_t drv = 0; + uint32_t fun_sel = 0; + uint32_t sig_out = 0; + gpio_get_io_config(gpio_num, &pu, &pd, &ie, &oe, &od, &drv, &fun_sel, &sig_out, &slp_sel); fprintf(out_stream, "IO[%"PRIu32"]%s -\n", gpio_num, esp_gpio_is_reserved(BIT64(gpio_num)) ? " **RESERVED**" : ""); fprintf(out_stream, " Pullup: %d, Pulldown: %d, DriveCap: %"PRIu32"\n", pu, pd, drv); @@ -1059,15 +1089,6 @@ esp_err_t gpio_dump_io_configuration(FILE *out_stream, uint64_t io_bit_mask) return ESP_OK; } -esp_err_t gpio_get_io_config(uint32_t gpio_num, - bool *pu, bool *pd, bool *ie, bool *oe, bool *od, uint32_t *drv, - uint32_t *fun_sel, uint32_t *sig_out, bool *slp_sel) -{ - GPIO_CHECK(GPIO_IS_VALID_GPIO(gpio_num), "GPIO number error", ESP_ERR_INVALID_ARG); - gpio_hal_get_io_config(gpio_context.gpio_hal, gpio_num, pu, pd, ie, oe, od, drv, fun_sel, sig_out, slp_sel); - return ESP_OK; -} - esp_err_t gpio_func_sel(gpio_num_t gpio_num, uint32_t func) { GPIO_CHECK(GPIO_IS_VALID_GPIO(gpio_num), "GPIO number error", ESP_ERR_INVALID_ARG); diff --git a/components/esp_hw_support/esp_gpio_reserve.c b/components/esp_hw_support/esp_gpio_reserve.c index b7891c879d8..c2e5ec71c08 100644 --- a/components/esp_hw_support/esp_gpio_reserve.c +++ b/components/esp_hw_support/esp_gpio_reserve.c @@ -10,7 +10,7 @@ #include "esp_bit_defs.h" #include "esp_private/esp_gpio_reserve.h" -static _Atomic uint64_t s_reserved_pin_mask = ATOMIC_VAR_INIT(~(SOC_GPIO_VALID_OUTPUT_GPIO_MASK)); +static _Atomic uint64_t s_reserved_pin_mask = ATOMIC_VAR_INIT(~(SOC_GPIO_VALID_GPIO_MASK)); uint64_t esp_gpio_reserve(uint64_t gpio_mask) { diff --git a/components/hal/esp32/include/hal/gpio_ll.h b/components/hal/esp32/include/hal/gpio_ll.h index 3f5f64a4dba..dea152b34af 100644 --- a/components/hal/esp32/include/hal/gpio_ll.h +++ b/components/hal/esp32/include/hal/gpio_ll.h @@ -64,15 +64,33 @@ static inline void gpio_ll_get_io_config(gpio_dev_t *hw, uint32_t gpio_num, uint32_t bit_shift = (gpio_num < 32) ? gpio_num : (gpio_num - 32); uint32_t bit_mask = 1 << bit_shift; uint32_t iomux_reg_val = REG_READ(GPIO_PIN_MUX_REG[gpio_num]); - *pu = (iomux_reg_val & FUN_PU_M) >> FUN_PU_S; - *pd = (iomux_reg_val & FUN_PD_M) >> FUN_PD_S; - *ie = (iomux_reg_val & FUN_IE_M) >> FUN_IE_S; - *oe = (((gpio_num < 32) ? hw->enable : hw->enable1.val) & bit_mask) >> bit_shift; - *od = hw->pin[gpio_num].pad_driver; - *drv = (iomux_reg_val & FUN_DRV_M) >> FUN_DRV_S; - *fun_sel = (iomux_reg_val & MCU_SEL_M) >> MCU_SEL_S; - *sig_out = hw->func_out_sel_cfg[gpio_num].func_sel; - *slp_sel = (iomux_reg_val & SLP_SEL_M) >> SLP_SEL_S; + if (pu) { + *pu = (iomux_reg_val & FUN_PU_M) >> FUN_PU_S; + } + if (pd) { + *pd = (iomux_reg_val & FUN_PD_M) >> FUN_PD_S; + } + if (ie) { + *ie = (iomux_reg_val & FUN_IE_M) >> FUN_IE_S; + } + if (oe) { + *oe = (((gpio_num < 32) ? hw->enable : hw->enable1.val) & bit_mask) >> bit_shift; + } + if (od) { + *od = hw->pin[gpio_num].pad_driver; + } + if (drv) { + *drv = (iomux_reg_val & FUN_DRV_M) >> FUN_DRV_S; + } + if (fun_sel) { + *fun_sel = (iomux_reg_val & MCU_SEL_M) >> MCU_SEL_S; + } + if (sig_out) { + *sig_out = hw->func_out_sel_cfg[gpio_num].func_sel; + } + if (slp_sel) { + *slp_sel = (iomux_reg_val & SLP_SEL_M) >> SLP_SEL_S; + } } /** diff --git a/components/hal/esp32/include/hal/rtc_io_ll.h b/components/hal/esp32/include/hal/rtc_io_ll.h index 78a71c3d05f..b1cb5c65acc 100644 --- a/components/hal/esp32/include/hal/rtc_io_ll.h +++ b/components/hal/esp32/include/hal/rtc_io_ll.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2015-2023 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2015-2024 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -12,6 +12,7 @@ #pragma once +#include #include #include "soc/rtc_io_struct.h" #include "soc/rtc_io_reg.h" @@ -24,7 +25,7 @@ extern "C" { #endif typedef enum { - RTCIO_LL_FUNC_RTC = 0x0, /*!< The pin controled by RTC module. */ + RTCIO_LL_FUNC_RTC = 0x0, /*!< The pin controlled by RTC module. */ RTCIO_LL_FUNC_DIGITAL = 0x1, /*!< The pin controlled by DIGITAL module. */ } rtcio_ll_func_t; @@ -194,6 +195,21 @@ static inline void rtcio_ll_pullup_disable(int rtcio_num) } } +/** + * @brief Get RTC GPIO pad pullup status. + * + * @param rtcio_num The index of rtcio. 0 ~ MAX(rtcio). + * @return Whether the pullup of the pad is enabled or not. + */ +static inline bool rtcio_ll_is_pullup_enabled(int rtcio_num) +{ + if (rtc_io_desc[rtcio_num].pullup) { + return GET_PERI_REG_MASK(rtc_io_desc[rtcio_num].reg, rtc_io_desc[rtcio_num].pullup); + } else { + return false; + } +} + /** * RTC GPIO pulldown enable. * @@ -218,6 +234,21 @@ static inline void rtcio_ll_pulldown_disable(int rtcio_num) } } +/** + * @brief Get RTC GPIO pad pulldown status. + * + * @param rtcio_num The index of rtcio. 0 ~ MAX(rtcio). + * @return Whether the pulldown of the pad is enabled or not. + */ +static inline bool rtcio_ll_is_pulldown_enabled(int rtcio_num) +{ + if (rtc_io_desc[rtcio_num].pulldown) { + return GET_PERI_REG_MASK(rtc_io_desc[rtcio_num].reg, rtc_io_desc[rtcio_num].pulldown); + } else { + return false; + } +} + /** * Enable force hold function on an RTC IO pad. * diff --git a/components/hal/esp32c2/include/hal/gpio_ll.h b/components/hal/esp32c2/include/hal/gpio_ll.h index 80301ddf706..4fe51dfdc5a 100644 --- a/components/hal/esp32c2/include/hal/gpio_ll.h +++ b/components/hal/esp32c2/include/hal/gpio_ll.h @@ -53,15 +53,33 @@ static inline void gpio_ll_get_io_config(gpio_dev_t *hw, uint32_t gpio_num, { uint32_t bit_mask = 1 << gpio_num; uint32_t iomux_reg_val = REG_READ(GPIO_PIN_MUX_REG[gpio_num]); - *pu = (iomux_reg_val & FUN_PU_M) >> FUN_PU_S; - *pd = (iomux_reg_val & FUN_PD_M) >> FUN_PD_S; - *ie = (iomux_reg_val & FUN_IE_M) >> FUN_IE_S; - *oe = (hw->enable.val & bit_mask) >> gpio_num; - *od = hw->pin[gpio_num].pad_driver; - *drv = (iomux_reg_val & FUN_DRV_M) >> FUN_DRV_S; - *fun_sel = (iomux_reg_val & MCU_SEL_M) >> MCU_SEL_S; - *sig_out = hw->func_out_sel_cfg[gpio_num].func_sel; - *slp_sel = (iomux_reg_val & SLP_SEL_M) >> SLP_SEL_S; + if (pu) { + *pu = (iomux_reg_val & FUN_PU_M) >> FUN_PU_S; + } + if (pd) { + *pd = (iomux_reg_val & FUN_PD_M) >> FUN_PD_S; + } + if (ie) { + *ie = (iomux_reg_val & FUN_IE_M) >> FUN_IE_S; + } + if (oe) { + *oe = (hw->enable.val & bit_mask) >> gpio_num; + } + if (od) { + *od = hw->pin[gpio_num].pad_driver; + } + if (drv) { + *drv = (iomux_reg_val & FUN_DRV_M) >> FUN_DRV_S; + } + if (fun_sel) { + *fun_sel = (iomux_reg_val & MCU_SEL_M) >> MCU_SEL_S; + } + if (sig_out) { + *sig_out = hw->func_out_sel_cfg[gpio_num].func_sel; + } + if (slp_sel) { + *slp_sel = (iomux_reg_val & SLP_SEL_M) >> SLP_SEL_S; + } } /** diff --git a/components/hal/esp32c3/include/hal/gpio_ll.h b/components/hal/esp32c3/include/hal/gpio_ll.h index cd96a95d93b..f966d3b3c3e 100644 --- a/components/hal/esp32c3/include/hal/gpio_ll.h +++ b/components/hal/esp32c3/include/hal/gpio_ll.h @@ -34,38 +34,6 @@ extern "C" { #define GPIO_LL_PRO_CPU_INTR_ENA (BIT(0)) #define GPIO_LL_PRO_CPU_NMI_INTR_ENA (BIT(1)) -/** - * @brief Get the configuration for an IO - * - * @param hw Peripheral GPIO hardware instance address. - * @param gpio_num GPIO number - * @param pu Pull-up enabled or not - * @param pd Pull-down enabled or not - * @param ie Input enabled or not - * @param oe Output enabled or not - * @param od Open-drain enabled or not - * @param drv Drive strength value - * @param fun_sel IOMUX function selection value - * @param sig_out Outputting peripheral signal index - * @param slp_sel Pin sleep mode enabled or not - */ -static inline void gpio_ll_get_io_config(gpio_dev_t *hw, uint32_t gpio_num, - bool *pu, bool *pd, bool *ie, bool *oe, bool *od, uint32_t *drv, - uint32_t *fun_sel, uint32_t *sig_out, bool *slp_sel) -{ - uint32_t bit_mask = 1 << gpio_num; - uint32_t iomux_reg_val = REG_READ(GPIO_PIN_MUX_REG[gpio_num]); - *pu = (iomux_reg_val & FUN_PU_M) >> FUN_PU_S; - *pd = (iomux_reg_val & FUN_PD_M) >> FUN_PD_S; - *ie = (iomux_reg_val & FUN_IE_M) >> FUN_IE_S; - *oe = (hw->enable.val & bit_mask) >> gpio_num; - *od = hw->pin[gpio_num].pad_driver; - *drv = (iomux_reg_val & FUN_DRV_M) >> FUN_DRV_S; - *fun_sel = (iomux_reg_val & MCU_SEL_M) >> MCU_SEL_S; - *sig_out = hw->func_out_sel_cfg[gpio_num].func_sel; - *slp_sel = (iomux_reg_val & SLP_SEL_M) >> SLP_SEL_S; -} - /** * @brief Enable pull-up on GPIO. * @@ -760,6 +728,56 @@ static inline bool gpio_ll_deepsleep_wakeup_is_enabled(gpio_dev_t *hw, uint32_t return GET_PERI_REG_MASK(RTC_CNTL_GPIO_WAKEUP_REG, 1 << (RTC_CNTL_GPIO_PIN0_WAKEUP_ENABLE_S - gpio_num)); } +/** + * @brief Get the configuration for an IO + * + * @param hw Peripheral GPIO hardware instance address. + * @param gpio_num GPIO number + * @param pu Pull-up enabled or not + * @param pd Pull-down enabled or not + * @param ie Input enabled or not + * @param oe Output enabled or not + * @param od Open-drain enabled or not + * @param drv Drive strength value + * @param fun_sel IOMUX function selection value + * @param sig_out Outputting peripheral signal index + * @param slp_sel Pin sleep mode enabled or not + */ +static inline void gpio_ll_get_io_config(gpio_dev_t *hw, uint32_t gpio_num, + bool *pu, bool *pd, bool *ie, bool *oe, bool *od, uint32_t *drv, + uint32_t *fun_sel, uint32_t *sig_out, bool *slp_sel) +{ + uint32_t bit_mask = 1 << gpio_num; + uint32_t iomux_reg_val = REG_READ(GPIO_PIN_MUX_REG[gpio_num]); + if (pu) { + *pu = (iomux_reg_val & FUN_PU_M) >> FUN_PU_S; + } + if (pd) { + *pd = (iomux_reg_val & FUN_PD_M) >> FUN_PD_S; + } + if (ie) { + *ie = (iomux_reg_val & FUN_IE_M) >> FUN_IE_S; + } + if (oe) { + *oe = (hw->enable.val & bit_mask) >> gpio_num; + } + if (od) { + *od = hw->pin[gpio_num].pad_driver; + } + if (drv) { + gpio_ll_get_drive_capability(hw, gpio_num, (gpio_drive_cap_t *)drv); // specific workaround in the LL + } + if (fun_sel) { + *fun_sel = (iomux_reg_val & MCU_SEL_M) >> MCU_SEL_S; + } + if (sig_out) { + *sig_out = hw->func_out_sel_cfg[gpio_num].func_sel; + } + if (slp_sel) { + *slp_sel = (iomux_reg_val & SLP_SEL_M) >> SLP_SEL_S; + } +} + #ifdef __cplusplus } #endif diff --git a/components/hal/esp32c5/include/hal/gpio_ll.h b/components/hal/esp32c5/include/hal/gpio_ll.h index 31894abc028..68383838b9f 100644 --- a/components/hal/esp32c5/include/hal/gpio_ll.h +++ b/components/hal/esp32c5/include/hal/gpio_ll.h @@ -37,7 +37,6 @@ extern "C" { #define GPIO_LL_GET_HW(num) (((num) == 0) ? (&GPIO) : NULL) #define GPIO_LL_PRO_CPU_INTR_ENA (BIT(0)) -#define GPIO_LL_PRO_CPU_NMI_INTR_ENA (BIT(1)) /** * @brief Get the configuration for an IO @@ -58,15 +57,33 @@ static inline void gpio_ll_get_io_config(gpio_dev_t *hw, uint32_t gpio_num, bool *pu, bool *pd, bool *ie, bool *oe, bool *od, uint32_t *drv, uint32_t *fun_sel, uint32_t *sig_out, bool *slp_sel) { - *pu = IO_MUX.gpio[gpio_num].fun_wpu; - *pd = IO_MUX.gpio[gpio_num].fun_wpd; - *ie = IO_MUX.gpio[gpio_num].fun_ie; - *oe = (hw->enable.val & (1 << gpio_num)) >> gpio_num; - *od = hw->pin[gpio_num].pad_driver; - *drv = IO_MUX.gpio[gpio_num].fun_drv; - *fun_sel = IO_MUX.gpio[gpio_num].mcu_sel; - *sig_out = hw->func_out_sel_cfg[gpio_num].out_sel; - *slp_sel = IO_MUX.gpio[gpio_num].slp_sel; + if (pu) { + *pu = IO_MUX.gpio[gpio_num].fun_wpu; + } + if (pd) { + *pd = IO_MUX.gpio[gpio_num].fun_wpd; + } + if (ie) { + *ie = IO_MUX.gpio[gpio_num].fun_ie; + } + if (oe) { + *oe = (hw->enable.val & (1 << gpio_num)) >> gpio_num; + } + if (od) { + *od = hw->pin[gpio_num].pad_driver; + } + if (drv) { + *drv = IO_MUX.gpio[gpio_num].fun_drv; + } + if (fun_sel) { + *fun_sel = IO_MUX.gpio[gpio_num].mcu_sel; + } + if (sig_out) { + *sig_out = hw->func_out_sel_cfg[gpio_num].out_sel; + } + if (slp_sel) { + *slp_sel = IO_MUX.gpio[gpio_num].slp_sel; + } } /** diff --git a/components/hal/esp32c5/include/hal/rtc_io_ll.h b/components/hal/esp32c5/include/hal/rtc_io_ll.h index 7b3d10819cf..0fd5bec0cac 100644 --- a/components/hal/esp32c5/include/hal/rtc_io_ll.h +++ b/components/hal/esp32c5/include/hal/rtc_io_ll.h @@ -229,6 +229,17 @@ static inline void rtcio_ll_pullup_disable(int rtcio_num) LP_IO_MUX.gpion[rtcio_num].gpion_fun_wpu = 0; } +/** + * @brief Get RTC GPIO pad pullup status. + * + * @param rtcio_num The index of rtcio. 0 ~ MAX(rtcio). + * @return Whether the pullup of the pad is enabled or not. + */ +static inline bool rtcio_ll_is_pullup_enabled(int rtcio_num) +{ + return LP_IO_MUX.gpion[rtcio_num].gpion_fun_wpu; +} + /** * RTC GPIO pulldown enable. * @@ -251,6 +262,17 @@ static inline void rtcio_ll_pulldown_disable(int rtcio_num) LP_IO_MUX.gpion[rtcio_num].gpion_fun_wpd = 0; } +/** + * @brief Get RTC GPIO pad pulldown status. + * + * @param rtcio_num The index of rtcio. 0 ~ MAX(rtcio). + * @return Whether the pulldown of the pad is enabled or not. + */ +static inline bool rtcio_ll_is_pulldown_enabled(int rtcio_num) +{ + return LP_IO_MUX.gpion[rtcio_num].gpion_fun_wpd; +} + /** * Enable force hold function for an RTC IO pad. * diff --git a/components/hal/esp32c6/include/hal/gpio_ll.h b/components/hal/esp32c6/include/hal/gpio_ll.h index 2409c412e06..13451401701 100644 --- a/components/hal/esp32c6/include/hal/gpio_ll.h +++ b/components/hal/esp32c6/include/hal/gpio_ll.h @@ -59,15 +59,33 @@ static inline void gpio_ll_get_io_config(gpio_dev_t *hw, uint32_t gpio_num, { uint32_t bit_mask = 1 << gpio_num; uint32_t iomux_reg_val = REG_READ(IO_MUX_GPIO0_REG + (gpio_num * 4)); - *pu = (iomux_reg_val & FUN_PU_M) >> FUN_PU_S; - *pd = (iomux_reg_val & FUN_PD_M) >> FUN_PD_S; - *ie = (iomux_reg_val & FUN_IE_M) >> FUN_IE_S; - *oe = (hw->enable.val & bit_mask) >> gpio_num; - *od = hw->pin[gpio_num].pad_driver; - *drv = (iomux_reg_val & FUN_DRV_M) >> FUN_DRV_S; - *fun_sel = (iomux_reg_val & MCU_SEL_M) >> MCU_SEL_S; - *sig_out = hw->func_out_sel_cfg[gpio_num].out_sel; - *slp_sel = (iomux_reg_val & SLP_SEL_M) >> SLP_SEL_S; + if (pu) { + *pu = (iomux_reg_val & FUN_PU_M) >> FUN_PU_S; + } + if (pd) { + *pd = (iomux_reg_val & FUN_PD_M) >> FUN_PD_S; + } + if (ie) { + *ie = (iomux_reg_val & FUN_IE_M) >> FUN_IE_S; + } + if (oe) { + *oe = (hw->enable.val & bit_mask) >> gpio_num; + } + if (od) { + *od = hw->pin[gpio_num].pad_driver; + } + if (drv) { + *drv = (iomux_reg_val & FUN_DRV_M) >> FUN_DRV_S; + } + if (fun_sel) { + *fun_sel = (iomux_reg_val & MCU_SEL_M) >> MCU_SEL_S; + } + if (sig_out) { + *sig_out = hw->func_out_sel_cfg[gpio_num].out_sel; + } + if (slp_sel) { + *slp_sel = (iomux_reg_val & SLP_SEL_M) >> SLP_SEL_S; + } } /** diff --git a/components/hal/esp32c6/include/hal/rtc_io_ll.h b/components/hal/esp32c6/include/hal/rtc_io_ll.h index 6fcac4cd406..b805db38f7e 100644 --- a/components/hal/esp32c6/include/hal/rtc_io_ll.h +++ b/components/hal/esp32c6/include/hal/rtc_io_ll.h @@ -228,6 +228,17 @@ static inline void rtcio_ll_pullup_disable(int rtcio_num) LP_IO.gpio[rtcio_num].fun_wpu = 0; } +/** + * @brief Get RTC GPIO pad pullup status. + * + * @param rtcio_num The index of rtcio. 0 ~ MAX(rtcio). + * @return Whether the pullup of the pad is enabled or not. + */ +static inline bool rtcio_ll_is_pullup_enabled(int rtcio_num) +{ + return LP_IO.gpio[rtcio_num].fun_wpu; +} + /** * RTC GPIO pulldown enable. * @@ -250,6 +261,17 @@ static inline void rtcio_ll_pulldown_disable(int rtcio_num) LP_IO.gpio[rtcio_num].fun_wpd = 0; } +/** + * @brief Get RTC GPIO pad pulldown status. + * + * @param rtcio_num The index of rtcio. 0 ~ MAX(rtcio). + * @return Whether the pulldown of the pad is enabled or not. + */ +static inline bool rtcio_ll_is_pulldown_enabled(int rtcio_num) +{ + return LP_IO.gpio[rtcio_num].fun_wpd; +} + /** * Enable force hold function for an RTC IO pad. * diff --git a/components/hal/esp32c61/include/hal/gpio_ll.h b/components/hal/esp32c61/include/hal/gpio_ll.h index a04c6ce2e5c..9ca5b451afd 100644 --- a/components/hal/esp32c61/include/hal/gpio_ll.h +++ b/components/hal/esp32c61/include/hal/gpio_ll.h @@ -57,15 +57,33 @@ static inline void gpio_ll_get_io_config(gpio_dev_t *hw, uint32_t gpio_num, bool *pu, bool *pd, bool *ie, bool *oe, bool *od, uint32_t *drv, uint32_t *fun_sel, uint32_t *sig_out, bool *slp_sel) { - *pu = IO_MUX.gpion[gpio_num].gpion_fun_wpu; - *pd = IO_MUX.gpion[gpio_num].gpion_fun_wpd; - *ie = IO_MUX.gpion[gpio_num].gpion_fun_ie; - *oe = (hw->enable.val & (1 << gpio_num)) >> gpio_num; - *od = hw->pinn[gpio_num].pinn_pad_driver; - *drv = IO_MUX.gpion[gpio_num].gpion_fun_drv; - *fun_sel = IO_MUX.gpion[gpio_num].gpion_mcu_sel; - *sig_out = hw->funcn_out_sel_cfg[gpio_num].funcn_out_sel; - *slp_sel = IO_MUX.gpion[gpio_num].gpion_slp_sel; + if (pu) { + *pu = IO_MUX.gpion[gpio_num].gpion_fun_wpu; + } + if (pd) { + *pd = IO_MUX.gpion[gpio_num].gpion_fun_wpd; + } + if (ie) { + *ie = IO_MUX.gpion[gpio_num].gpion_fun_ie; + } + if (oe) { + *oe = (hw->enable.val & (1 << gpio_num)) >> gpio_num; + } + if (od) { + *od = hw->pinn[gpio_num].pinn_pad_driver; + } + if (drv) { + *drv = IO_MUX.gpion[gpio_num].gpion_fun_drv; + } + if (fun_sel) { + *fun_sel = IO_MUX.gpion[gpio_num].gpion_mcu_sel; + } + if (sig_out) { + *sig_out = hw->funcn_out_sel_cfg[gpio_num].funcn_out_sel; + } + if (slp_sel) { + *slp_sel = IO_MUX.gpion[gpio_num].gpion_slp_sel; + } } /** diff --git a/components/hal/esp32c61/include/hal/rtc_io_ll.h b/components/hal/esp32c61/include/hal/rtc_io_ll.h index 60bd5fd7d0d..442614024bf 100644 --- a/components/hal/esp32c61/include/hal/rtc_io_ll.h +++ b/components/hal/esp32c61/include/hal/rtc_io_ll.h @@ -229,6 +229,17 @@ static inline void rtcio_ll_pullup_disable(int rtcio_num) LP_IO_MUX.gpion[rtcio_num].gpion_fun_wpu = 0; } +/** + * @brief Get RTC GPIO pad pullup status. + * + * @param rtcio_num The index of rtcio. 0 ~ MAX(rtcio). + * @return Whether the pullup of the pad is enabled or not. + */ +static inline bool rtcio_ll_is_pullup_enabled(int rtcio_num) +{ + return LP_IO_MUX.gpion[rtcio_num].gpion_fun_wpu; +} + /** * RTC GPIO pulldown enable. * @@ -251,6 +262,17 @@ static inline void rtcio_ll_pulldown_disable(int rtcio_num) LP_IO_MUX.gpion[rtcio_num].gpion_fun_wpd = 0; } +/** + * @brief Get RTC GPIO pad pulldown status. + * + * @param rtcio_num The index of rtcio. 0 ~ MAX(rtcio). + * @return Whether the pulldown of the pad is enabled or not. + */ +static inline bool rtcio_ll_is_pulldown_enabled(int rtcio_num) +{ + return LP_IO_MUX.gpion[rtcio_num].gpion_fun_wpd; +} + /** * Enable force hold function for an RTC IO pad. * diff --git a/components/hal/esp32h2/include/hal/gpio_ll.h b/components/hal/esp32h2/include/hal/gpio_ll.h index 8a7cfd448bd..ac789777bfd 100644 --- a/components/hal/esp32h2/include/hal/gpio_ll.h +++ b/components/hal/esp32h2/include/hal/gpio_ll.h @@ -59,15 +59,33 @@ static inline void gpio_ll_get_io_config(gpio_dev_t *hw, uint32_t gpio_num, { uint32_t bit_mask = 1 << gpio_num; uint32_t iomux_reg_val = REG_READ(IO_MUX_GPIO0_REG + (gpio_num * 4)); - *pu = (iomux_reg_val & FUN_PU_M) >> FUN_PU_S; - *pd = (iomux_reg_val & FUN_PD_M) >> FUN_PD_S; - *ie = (iomux_reg_val & FUN_IE_M) >> FUN_IE_S; - *oe = (hw->enable.val & bit_mask) >> gpio_num; - *od = hw->pin[gpio_num].pad_driver; - *drv = (iomux_reg_val & FUN_DRV_M) >> FUN_DRV_S; - *fun_sel = (iomux_reg_val & MCU_SEL_M) >> MCU_SEL_S; - *sig_out = hw->func_out_sel_cfg[gpio_num].out_sel; - *slp_sel = (iomux_reg_val & SLP_SEL_M) >> SLP_SEL_S; + if (pu) { + *pu = (iomux_reg_val & FUN_PU_M) >> FUN_PU_S; + } + if (pd) { + *pd = (iomux_reg_val & FUN_PD_M) >> FUN_PD_S; + } + if (ie) { + *ie = (iomux_reg_val & FUN_IE_M) >> FUN_IE_S; + } + if (oe) { + *oe = (hw->enable.val & bit_mask) >> gpio_num; + } + if (od) { + *od = hw->pin[gpio_num].pad_driver; + } + if (drv) { + *drv = (iomux_reg_val & FUN_DRV_M) >> FUN_DRV_S; + } + if (fun_sel) { + *fun_sel = (iomux_reg_val & MCU_SEL_M) >> MCU_SEL_S; + } + if (sig_out) { + *sig_out = hw->func_out_sel_cfg[gpio_num].out_sel; + } + if (slp_sel) { + *slp_sel = (iomux_reg_val & SLP_SEL_M) >> SLP_SEL_S; + } } /** diff --git a/components/hal/esp32p4/include/hal/gpio_ll.h b/components/hal/esp32p4/include/hal/gpio_ll.h index 7fb9bec340d..4ecc70361cd 100644 --- a/components/hal/esp32p4/include/hal/gpio_ll.h +++ b/components/hal/esp32p4/include/hal/gpio_ll.h @@ -64,15 +64,33 @@ static inline void gpio_ll_get_io_config(gpio_dev_t *hw, uint32_t gpio_num, { uint32_t bit_shift = (gpio_num < 32) ? gpio_num : (gpio_num - 32); uint32_t bit_mask = 1 << bit_shift; - *pu = IO_MUX.gpio[gpio_num].fun_wpu; - *pd = IO_MUX.gpio[gpio_num].fun_wpd; - *ie = IO_MUX.gpio[gpio_num].fun_ie; - *oe = (((gpio_num < 32) ? hw->enable.val : hw->enable1.val) & bit_mask) >> bit_shift; - *od = hw->pin[gpio_num].pad_driver; - *drv = IO_MUX.gpio[gpio_num].fun_drv; - *fun_sel = IO_MUX.gpio[gpio_num].mcu_sel; - *sig_out = hw->func_out_sel_cfg[gpio_num].out_sel; - *slp_sel = IO_MUX.gpio[gpio_num].slp_sel; + if (pu) { + *pu = IO_MUX.gpio[gpio_num].fun_wpu; + } + if (pd) { + *pd = IO_MUX.gpio[gpio_num].fun_wpd; + } + if (ie) { + *ie = IO_MUX.gpio[gpio_num].fun_ie; + } + if (oe) { + *oe = (((gpio_num < 32) ? hw->enable.val : hw->enable1.val) & bit_mask) >> bit_shift; + } + if (od) { + *od = hw->pin[gpio_num].pad_driver; + } + if (drv) { + *drv = IO_MUX.gpio[gpio_num].fun_drv; + } + if (fun_sel) { + *fun_sel = IO_MUX.gpio[gpio_num].mcu_sel; + } + if (sig_out) { + *sig_out = hw->func_out_sel_cfg[gpio_num].out_sel; + } + if (slp_sel) { + *slp_sel = IO_MUX.gpio[gpio_num].slp_sel; + } } /** diff --git a/components/hal/esp32p4/include/hal/rtc_io_ll.h b/components/hal/esp32p4/include/hal/rtc_io_ll.h index 1bfe4659ffa..20f7f6ea73b 100644 --- a/components/hal/esp32p4/include/hal/rtc_io_ll.h +++ b/components/hal/esp32p4/include/hal/rtc_io_ll.h @@ -267,6 +267,17 @@ static inline void rtcio_ll_pullup_disable(int rtcio_num) LP_IOMUX.pad[rtcio_num].rue = 0; } +/** + * @brief Get RTC GPIO pad pullup status. + * + * @param rtcio_num The index of rtcio. 0 ~ MAX(rtcio). + * @return Whether the pullup of the pad is enabled or not. + */ +static inline bool rtcio_ll_is_pullup_enabled(int rtcio_num) +{ + return LP_IOMUX.pad[rtcio_num].rue; +} + /** * @brief RTC GPIO pulldown enable. * @@ -289,6 +300,17 @@ static inline void rtcio_ll_pulldown_disable(int rtcio_num) LP_IOMUX.pad[rtcio_num].rde = 0; } +/** + * @brief Get RTC GPIO pad pulldown status. + * + * @param rtcio_num The index of rtcio. 0 ~ MAX(rtcio). + * @return Whether the pulldown of the pad is enabled or not. + */ +static inline bool rtcio_ll_is_pulldown_enabled(int rtcio_num) +{ + return LP_IOMUX.pad[rtcio_num].rde; +} + /** * @brief Enable force hold function for an RTC IO pad. * diff --git a/components/hal/esp32s2/include/hal/gpio_ll.h b/components/hal/esp32s2/include/hal/gpio_ll.h index 233b86c3677..da967676caa 100644 --- a/components/hal/esp32s2/include/hal/gpio_ll.h +++ b/components/hal/esp32s2/include/hal/gpio_ll.h @@ -55,15 +55,33 @@ static inline void gpio_ll_get_io_config(gpio_dev_t *hw, uint32_t gpio_num, uint32_t bit_shift = (gpio_num < 32) ? gpio_num : (gpio_num - 32); uint32_t bit_mask = 1 << bit_shift; uint32_t iomux_reg_val = REG_READ(GPIO_PIN_MUX_REG[gpio_num]); - *pu = (iomux_reg_val & FUN_PU_M) >> FUN_PU_S; - *pd = (iomux_reg_val & FUN_PD_M) >> FUN_PD_S; - *ie = (iomux_reg_val & FUN_IE_M) >> FUN_IE_S; - *oe = (((gpio_num < 32) ? hw->enable : hw->enable1.val) & bit_mask) >> bit_shift; - *od = hw->pin[gpio_num].pad_driver; - *drv = (iomux_reg_val & FUN_DRV_M) >> FUN_DRV_S; - *fun_sel = (iomux_reg_val & MCU_SEL_M) >> MCU_SEL_S; - *sig_out = hw->func_out_sel_cfg[gpio_num].func_sel; - *slp_sel = (iomux_reg_val & SLP_SEL_M) >> SLP_SEL_S; + if (pu) { + *pu = (iomux_reg_val & FUN_PU_M) >> FUN_PU_S; + } + if (pd) { + *pd = (iomux_reg_val & FUN_PD_M) >> FUN_PD_S; + } + if (ie) { + *ie = (iomux_reg_val & FUN_IE_M) >> FUN_IE_S; + } + if (oe) { + *oe = (((gpio_num < 32) ? hw->enable : hw->enable1.val) & bit_mask) >> bit_shift; + } + if (od) { + *od = hw->pin[gpio_num].pad_driver; + } + if (drv) { + *drv = (iomux_reg_val & FUN_DRV_M) >> FUN_DRV_S; + } + if (fun_sel) { + *fun_sel = (iomux_reg_val & MCU_SEL_M) >> MCU_SEL_S; + } + if (sig_out) { + *sig_out = hw->func_out_sel_cfg[gpio_num].func_sel; + } + if (slp_sel) { + *slp_sel = (iomux_reg_val & SLP_SEL_M) >> SLP_SEL_S; + } } /** diff --git a/components/hal/esp32s2/include/hal/rtc_io_ll.h b/components/hal/esp32s2/include/hal/rtc_io_ll.h index 739d2722ddf..17eddbe01e8 100644 --- a/components/hal/esp32s2/include/hal/rtc_io_ll.h +++ b/components/hal/esp32s2/include/hal/rtc_io_ll.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2015-2023 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2015-2024 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -12,6 +12,7 @@ #pragma once +#include #include #include "soc/rtc_io_struct.h" #include "soc/rtc_io_reg.h" @@ -25,7 +26,7 @@ extern "C" { #endif typedef enum { - RTCIO_LL_FUNC_RTC = 0x0, /*!< The pin controled by RTC module. */ + RTCIO_LL_FUNC_RTC = 0x0, /*!< The pin controlled by RTC module. */ RTCIO_LL_FUNC_DIGITAL = 0x1, /*!< The pin controlled by DIGITAL module. */ } rtcio_ll_func_t; @@ -197,6 +198,21 @@ static inline void rtcio_ll_pullup_disable(int rtcio_num) } } +/** + * @brief Get RTC GPIO pad pullup status. + * + * @param rtcio_num The index of rtcio. 0 ~ MAX(rtcio). + * @return Whether the pullup of the pad is enabled or not. + */ +static inline bool rtcio_ll_is_pullup_enabled(int rtcio_num) +{ + if (rtc_io_desc[rtcio_num].pullup) { + return GET_PERI_REG_MASK(rtc_io_desc[rtcio_num].reg, rtc_io_desc[rtcio_num].pullup); + } else { + return false; + } +} + /** * RTC GPIO pulldown enable. * @@ -221,6 +237,21 @@ static inline void rtcio_ll_pulldown_disable(int rtcio_num) } } +/** + * @brief Get RTC GPIO pad pulldown status. + * + * @param rtcio_num The index of rtcio. 0 ~ MAX(rtcio). + * @return Whether the pulldown of the pad is enabled or not. + */ +static inline bool rtcio_ll_is_pulldown_enabled(int rtcio_num) +{ + if (rtc_io_desc[rtcio_num].pulldown) { + return GET_PERI_REG_MASK(rtc_io_desc[rtcio_num].reg, rtc_io_desc[rtcio_num].pulldown); + } else { + return false; + } +} + /** * Enable force hold function on an RTC IO pad. * diff --git a/components/hal/esp32s3/include/hal/gpio_ll.h b/components/hal/esp32s3/include/hal/gpio_ll.h index 3410e4f973b..a17ab088332 100644 --- a/components/hal/esp32s3/include/hal/gpio_ll.h +++ b/components/hal/esp32s3/include/hal/gpio_ll.h @@ -34,39 +34,6 @@ extern "C" { #define GPIO_LL_INTR_ENA (BIT(0)) #define GPIO_LL_NMI_INTR_ENA (BIT(1)) -/** - * @brief Get the configuration for an IO - * - * @param hw Peripheral GPIO hardware instance address. - * @param gpio_num GPIO number - * @param pu Pull-up enabled or not - * @param pd Pull-down enabled or not - * @param ie Input enabled or not - * @param oe Output enabled or not - * @param od Open-drain enabled or not - * @param drv Drive strength value - * @param fun_sel IOMUX function selection value - * @param sig_out Outputting peripheral signal index - * @param slp_sel Pin sleep mode enabled or not - */ -static inline void gpio_ll_get_io_config(gpio_dev_t *hw, uint32_t gpio_num, - bool *pu, bool *pd, bool *ie, bool *oe, bool *od, uint32_t *drv, - uint32_t *fun_sel, uint32_t *sig_out, bool *slp_sel) -{ - uint32_t bit_shift = (gpio_num < 32) ? gpio_num : (gpio_num - 32); - uint32_t bit_mask = 1 << bit_shift; - uint32_t iomux_reg_val = REG_READ(GPIO_PIN_MUX_REG[gpio_num]); - *pu = (iomux_reg_val & FUN_PU_M) >> FUN_PU_S; - *pd = (iomux_reg_val & FUN_PD_M) >> FUN_PD_S; - *ie = (iomux_reg_val & FUN_IE_M) >> FUN_IE_S; - *oe = (((gpio_num < 32) ? hw->enable : hw->enable1.val) & bit_mask) >> bit_shift; - *od = hw->pin[gpio_num].pad_driver; - *drv = (iomux_reg_val & FUN_DRV_M) >> FUN_DRV_S; - *fun_sel = (iomux_reg_val & MCU_SEL_M) >> MCU_SEL_S; - *sig_out = hw->func_out_sel_cfg[gpio_num].func_sel; - *slp_sel = (iomux_reg_val & SLP_SEL_M) >> SLP_SEL_S; -} - /** * @brief Enable pull-up on GPIO. * @@ -727,6 +694,57 @@ static inline void gpio_ll_sleep_output_enable(gpio_dev_t *hw, uint32_t gpio_num PIN_SLP_OUTPUT_ENABLE(GPIO_PIN_MUX_REG[gpio_num]); } +/** + * @brief Get the configuration for an IO + * + * @param hw Peripheral GPIO hardware instance address. + * @param gpio_num GPIO number + * @param pu Pull-up enabled or not + * @param pd Pull-down enabled or not + * @param ie Input enabled or not + * @param oe Output enabled or not + * @param od Open-drain enabled or not + * @param drv Drive strength value + * @param fun_sel IOMUX function selection value + * @param sig_out Outputting peripheral signal index + * @param slp_sel Pin sleep mode enabled or not + */ +static inline void gpio_ll_get_io_config(gpio_dev_t *hw, uint32_t gpio_num, + bool *pu, bool *pd, bool *ie, bool *oe, bool *od, uint32_t *drv, + uint32_t *fun_sel, uint32_t *sig_out, bool *slp_sel) +{ + uint32_t bit_shift = (gpio_num < 32) ? gpio_num : (gpio_num - 32); + uint32_t bit_mask = 1 << bit_shift; + uint32_t iomux_reg_val = REG_READ(GPIO_PIN_MUX_REG[gpio_num]); + if (pu) { + *pu = (iomux_reg_val & FUN_PU_M) >> FUN_PU_S; + } + if (pd) { + *pd = (iomux_reg_val & FUN_PD_M) >> FUN_PD_S; + } + if (ie) { + *ie = (iomux_reg_val & FUN_IE_M) >> FUN_IE_S; + } + if (oe) { + *oe = (((gpio_num < 32) ? hw->enable : hw->enable1.val) & bit_mask) >> bit_shift; + } + if (od) { + *od = hw->pin[gpio_num].pad_driver; + } + if (drv) { + gpio_ll_get_drive_capability(hw, gpio_num, (gpio_drive_cap_t *)drv); // specific workaround in the LL + } + if (fun_sel) { + *fun_sel = (iomux_reg_val & MCU_SEL_M) >> MCU_SEL_S; + } + if (sig_out) { + *sig_out = hw->func_out_sel_cfg[gpio_num].func_sel; + } + if (slp_sel) { + *slp_sel = (iomux_reg_val & SLP_SEL_M) >> SLP_SEL_S; + } +} + #ifdef __cplusplus } #endif diff --git a/components/hal/esp32s3/include/hal/rtc_io_ll.h b/components/hal/esp32s3/include/hal/rtc_io_ll.h index 86d483b217a..63ac998e4dd 100644 --- a/components/hal/esp32s3/include/hal/rtc_io_ll.h +++ b/components/hal/esp32s3/include/hal/rtc_io_ll.h @@ -12,6 +12,7 @@ #pragma once +#include #include #include "soc/rtc_io_struct.h" #include "soc/rtc_io_reg.h" @@ -224,6 +225,21 @@ static inline void rtcio_ll_pullup_disable(int rtcio_num) } } +/** + * @brief Get RTC GPIO pad pullup status. + * + * @param rtcio_num The index of rtcio. 0 ~ MAX(rtcio). + * @return Whether the pullup of the pad is enabled or not. + */ +static inline bool rtcio_ll_is_pullup_enabled(int rtcio_num) +{ + if (rtc_io_desc[rtcio_num].pullup) { + return GET_PERI_REG_MASK(rtc_io_desc[rtcio_num].reg, rtc_io_desc[rtcio_num].pullup); + } else { + return false; + } +} + /** * RTC GPIO pulldown enable. * @@ -248,6 +264,21 @@ static inline void rtcio_ll_pulldown_disable(int rtcio_num) } } +/** + * @brief Get RTC GPIO pad pulldown status. + * + * @param rtcio_num The index of rtcio. 0 ~ MAX(rtcio). + * @return Whether the pulldown of the pad is enabled or not. + */ +static inline bool rtcio_ll_is_pulldown_enabled(int rtcio_num) +{ + if (rtc_io_desc[rtcio_num].pulldown) { + return GET_PERI_REG_MASK(rtc_io_desc[rtcio_num].reg, rtc_io_desc[rtcio_num].pulldown); + } else { + return false; + } +} + /** * Enable force hold function on an RTC IO pad. * diff --git a/components/hal/include/hal/rtc_io_hal.h b/components/hal/include/hal/rtc_io_hal.h index e254ec76d5d..b55c45a6f03 100644 --- a/components/hal/include/hal/rtc_io_hal.h +++ b/components/hal/include/hal/rtc_io_hal.h @@ -160,6 +160,14 @@ void rtcio_hal_set_direction_in_sleep(int rtcio_num, rtc_gpio_mode_t mode); */ #define rtcio_hal_pullup_disable(rtcio_num) rtcio_ll_pullup_disable(rtcio_num) +/** + * @brief Get RTC GPIO pad pullup status. + * + * @param rtcio_num The index of rtcio. 0 ~ SOC_RTCIO_PIN_COUNT. + * @return Whether the pullup of the pad is enabled or not. + */ +#define rtcio_hal_is_pullup_enabled(rtcio_num) rtcio_ll_is_pullup_enabled(rtcio_num) + /** * RTC GPIO pulldown enable. * @@ -174,6 +182,14 @@ void rtcio_hal_set_direction_in_sleep(int rtcio_num, rtc_gpio_mode_t mode); */ #define rtcio_hal_pulldown_disable(rtcio_num) rtcio_ll_pulldown_disable(rtcio_num) +/** + * @brief Get RTC GPIO pad pulldown status. + * + * @param rtcio_num The index of rtcio. 0 ~ SOC_RTCIO_PIN_COUNT. + * @return Whether the pulldown of the pad is enabled or not. + */ +#define rtcio_hal_is_pulldown_enabled(rtcio_num) rtcio_ll_is_pulldown_enabled(rtcio_num) + /** * Select a RTC IOMUX function for the RTC IO * From c5ea3e6cf6307e730e6d457a12b114767f3f3834 Mon Sep 17 00:00:00 2001 From: Zhang Shuxian Date: Tue, 17 Dec 2024 16:15:27 +0800 Subject: [PATCH 114/118] docs: Update CN translation for dfu --- docs/en/api-guides/dfu.rst | 22 ++++++------- docs/zh_CN/api-guides/dfu.rst | 58 +++++++++++++++++++++-------------- 2 files changed, 46 insertions(+), 34 deletions(-) diff --git a/docs/en/api-guides/dfu.rst b/docs/en/api-guides/dfu.rst index e9322781c04..cf4bee30806 100644 --- a/docs/en/api-guides/dfu.rst +++ b/docs/en/api-guides/dfu.rst @@ -5,19 +5,19 @@ Device Firmware Upgrade via USB .. only:: not SOC_USB_SERIAL_JTAG_SUPPORTED - Typically, the firmware of the {IDF_TARGET_NAME} is flashed via the chip's serial port. However, flashing via the serial port requires a USB to serial converter chip (e.g., CP210x or FTDI) to be connected to the {IDF_TARGET_NAME} (see :doc:`Establish Serial Connection with {IDF_TARGET_NAME} <../get-started/establish-serial-connection>` for more details). The {IDF_TARGET_NAME} contains a USB OTG peripheral making it possible to connect the {IDF_TARGET_NAME} to the host directly via USB (thus not requiring a USB to serial converter chip). + Typically, the firmware of {IDF_TARGET_NAME} is flashed via the chip's serial port. However, flashing via the serial port requires a USB to serial converter chip (e.g., CP210x or FTDI) to be connected to {IDF_TARGET_NAME}. Please see :doc:`Establish Serial Connection with {IDF_TARGET_NAME} <../get-started/establish-serial-connection>` for more details. {IDF_TARGET_NAME} contains a USB OTG peripheral, making it possible to connect {IDF_TARGET_NAME} to the host directly via USB (thus not requiring a USB to serial converter chip). .. only:: SOC_USB_SERIAL_JTAG_SUPPORTED - Typically, the firmware of the {IDF_TARGET_NAME} is flashed via the chip's serial port or USB_SERIAL_JTAG (see :doc:`Establish Serial Connection with {IDF_TARGET_NAME} <../get-started/establish-serial-connection>` for more details). The {IDF_TARGET_NAME} also contains a USB OTG peripheral making it possible to connect the {IDF_TARGET_NAME} to the host directly via USB Device Firmware Upgrade. + Typically, the firmware of {IDF_TARGET_NAME} is flashed via the chip's serial port or USB_SERIAL_JTAG (see :doc:`Establish Serial Connection with {IDF_TARGET_NAME} <../get-started/establish-serial-connection>` for more details). {IDF_TARGET_NAME} also contains a USB OTG peripheral making it possible to connect {IDF_TARGET_NAME} to the host directly via USB Device Firmware Upgrade. .. only:: esp32s3 - By default, the :doc:`USB_SERIAL_JTAG ` module is connected to the {IDF_TARGET_NAME}'s internal USB PHY, while the USB OTG peripheral can be used only if an external USB PHY is connected. Since DFU is provided via the USB OTG peripheral, it cannot be used through the internal PHY in this configuration. + By default, the :doc:`USB_SERIAL_JTAG ` module is connected to {IDF_TARGET_NAME}'s internal USB PHY, while the USB OTG peripheral can be used only if an external USB PHY is connected. Since DFU is provided via the USB OTG peripheral, it cannot be used through the internal PHY in this configuration. - However, users can permanently switch the internal USB PHY to work with USB OTG peripheral instead of USB_SERIAL_JTAG by burning the ``USB_PHY_SEL`` eFuse. See *{IDF_TARGET_NAME} Technical Reference Manual* [`PDF <{IDF_TARGET_TRM_EN_URL}>`__] for more details about USB_SERIAL_JTAG and USB OTG. + However, you can permanently switch the internal USB PHY to work with USB OTG peripheral instead of USB_SERIAL_JTAG by burning the ``USB_PHY_SEL`` eFuse. See *{IDF_TARGET_NAME} Technical Reference Manual* [`PDF <{IDF_TARGET_TRM_EN_URL}>`__] for more details about USB_SERIAL_JTAG and USB OTG. -Device Firmware Upgrade (DFU) is a mechanism for upgrading the firmware of the {IDF_TARGET_NAME} directly via the Universal Serial Bus (USB). However, enabling Secure Boot or flash encryption disables the USB-OTG USB stack in the ROM, disallowing updates via the serial emulation or DFU on that port. +Device Firmware Upgrade (DFU) is a mechanism for upgrading the firmware of {IDF_TARGET_NAME} directly via the Universal Serial Bus (USB). However, enabling Secure Boot or flash encryption disables the USB-OTG USB stack in the ROM, disallowing updates via the serial emulation or DFU on that port. - :ref:`get-started-get-prerequisites` of the Getting Started Guide introduces the software requirements of DFU. - Section :ref:`api_guide_dfu_build` describes how to build firmware for DFU with ESP-IDF. @@ -29,11 +29,11 @@ USB Connection .. only:: esp32p4 - The {IDF_TARGET_NAME} routes the USB D+ and D- signals to their dedicated pins. For USB device functionality, these pins must be connected to the USB bus (e.g., via a Micro-B port, USB-C port, or directly to standard-A plug). + {IDF_TARGET_NAME} routes the USB D+ and D- signals to their dedicated pins. For USB device functionality, these pins must be connected to the USB bus (e.g., via a Micro-B port, USB-C port, or directly to standard-A plug). .. only:: esp32s2 or esp32s3 - The necessary connections for the {IDF_TARGET_NAME}'s internal USB PHY (transceiver) are shown in the following table: + The necessary connections for {IDF_TARGET_NAME}'s internal USB PHY (transceiver) are shown in the following table: .. list-table:: :header-rows: 1 @@ -60,7 +60,7 @@ USB Connection .. note:: - The {IDF_TARGET_NAME} chip needs to be in bootloader mode before it can be detected as a DFU device and flash. Please refer to `Boot Mode Selection `_ for more information about how to enter bootloader mode. + {IDF_TARGET_NAME} chip needs to be in bootloader mode before it can be detected as a DFU device and flash. Please refer to `Boot Mode Selection `_ for more information about how to enter bootloader mode. .. _api_guide_dfu_build: @@ -82,7 +82,7 @@ The command below will create a DFU image named ``dfu.bin`` that is placed in th Flashing the DFU Image ---------------------- -The command below will download the DFU image into the {IDF_TARGET_NAME}:: +The command below will download the DFU image into {IDF_TARGET_NAME}:: idf.py dfu-flash @@ -110,7 +110,7 @@ See :ref:`api_guide_dfu_flash_errors` and their solutions. Udev Rule (Linux Only) ---------------------- -Udev is a device manager for the Linux kernel. It allows us to run ``dfu-util`` (and ``idf.py dfu-flash``) without ``sudo`` for gaining access to the chip. +Udev is a device manager for the Linux kernel. It allows running ``dfu-util`` (and ``idf.py dfu-flash``) without ``sudo`` for gaining access to the chip. Create file ``/etc/udev/rules.d/40-dfuse.rules`` with the following content:: @@ -118,7 +118,7 @@ Create file ``/etc/udev/rules.d/40-dfuse.rules`` with the following content:: .. note:: - Please check the output of the command ``groups``. The user has to be a member of the `GROUP` specified above. You may use some other existing groups for this purpose (e.g., `uucp` on some systems instead of `plugdev`) or create a new group for this purpose. + Please check the output of the command ``groups``. You need to be a member of the `GROUP` specified above. You may use some other existing groups for this purpose (e.g., `uucp` on some systems instead of `plugdev`) or create a new group for this purpose. Restart your computer so the previous setting could take into affect or run ``sudo udevadm trigger`` to force manually udev to trigger your new rule. diff --git a/docs/zh_CN/api-guides/dfu.rst b/docs/zh_CN/api-guides/dfu.rst index cc0f476ef55..2a273588655 100644 --- a/docs/zh_CN/api-guides/dfu.rst +++ b/docs/zh_CN/api-guides/dfu.rst @@ -3,7 +3,19 @@ :link_to_translation:`en:[English]` -一般情况下，{IDF_TARGET_NAME} 的固件是通过芯片的串口烧录。但是，通过串口烧录 {IDF_TARGET_NAME} 需要连接 USB 转串口转换器（如 CP210x 或 FTDI），详细信息可参阅 :doc:`与 {IDF_TARGET_NAME} 创建串口连接<../get-started/establish-serial-connection>`。{IDF_TARGET_NAME} 包含一个 USB OTG 外设，使其可以通过 USB 将 {IDF_TARGET_NAME} 直接连接到主机，即不需要 USB 转串口转换器也可完成烧录。 +.. only:: not SOC_USB_SERIAL_JTAG_SUPPORTED + + 一般情况下，{IDF_TARGET_NAME} 的固件是通过芯片的串口烧录。但是，通过串口烧录 {IDF_TARGET_NAME} 需要连接 USB 转串口转换器（如 CP210x 或 FTDI），详细信息可参阅 :doc:`与 {IDF_TARGET_NAME} 创建串口连接 <../get-started/establish-serial-connection>`。{IDF_TARGET_NAME} 包含一个 USB OTG 外设，使其能够通过 USB 将 {IDF_TARGET_NAME} 直接连接到主机，即不需要 USB 转串口转换器也可完成烧录。 + +.. only:: SOC_USB_SERIAL_JTAG_SUPPORTED + + 一般情况下，{IDF_TARGET_NAME} 的固件是通过芯片的串口或 USB_SERIAL_JTAG 烧录，详细信息可参阅 :doc:`与 {IDF_TARGET_NAME} 创建串口连接 <../get-started/establish-serial-connection>`。{IDF_TARGET_NAME} 还包含一个 USB OTG 外设，使其能够通过 USB 设备固件升级直接连接到主机。 + +.. only:: esp32s3 + + 默认情况下，:doc:`USB_SERIAL_JTAG` 模块连接到 {IDF_TARGET_NAME} 的内部 USB PHY，而 USB OTG 外设只有在连接外部 USB PHY 时才能使用。由于 DFU 是通过 USB OTG 外设提供的，因此在默认的设置下，无法通过内部 USB PHY 使用 DFU。 + + 然而，你可以通过烧录 ``USB_PHY_SEL`` eFuse，将内部 USB PHY 永久切换为支持 USB OTG 外设的模式，不再用于 USB_SERIAL_JTAG。有关 USB_SERIAL_JTAG 和 USB OTG 的更多信息，请参阅 *{IDF_TARGET_NAME} 技术参考手册* [`PDF <{IDF_TARGET_TRM_CN_URL}>`__]。 设备固件升级 (DFU) 是一种通过通用串行总线 (USB) 升级设备固件的机制。但是，启用安全启动 (Secure Boot) 或 flash 加密会禁用 ROM 中的 USB-OTG USB 堆栈，则无法通过该端口上的模拟串口或 DFU 进行更新。 @@ -15,40 +27,40 @@ USB 连接 -------------- -{IDF_TARGET_NAME} 的内部 USB PHY（收发器）与 GPIO 的连接如下表所示： +.. only:: esp32p4 -.. list-table:: - :header-rows: 1 - :widths: 25 20 + {IDF_TARGET_NAME} 将 USB D+ 和 D- 信号连接到其专用引脚。为了实现 USB 设备功能，这些引脚必须连接到 USB 总线，如，通过 Micro-B 接口、USB-C 接口进行连接，或直接连接到标准 A 型插头。 - * - GPIO - - USB +.. only:: esp32s2 or esp32s3 - * - 20 - - D+（绿色） + {IDF_TARGET_NAME} 的内部 USB PHY（收发器）与 GPIO 的连接如下表所示： - * - 19 - - D-（白色） + .. list-table:: + :header-rows: 1 + :widths: 25 20 - * - GND - - GND（黑色） + * - GPIO + - USB - * - +5V - - +5V（红色） + * - 20 + - D+（绿色） -.. warning:: + * - 19 + - D-（白色） - 一些连接线采用非标准颜色连接，有时调换下 D+ 和 D- 的连接，驱动程序就能正常工作。如果无法检测到你的设备，请尝试下调换 D+ 和 D- 的连接线。 + * - GND + - GND（黑色） -.. only:: esp32s3 + * - +5V + - +5V（红色） - 默认情况下，{IDF_TARGET_NAME} 内部 USB PHY 与 :doc:`USB_SERIAL_JTAG` 模块连接，此时 USB OTG 外设只有在连接外部 USB PHY 时才能使用。DFU 是通过 USB OTG 外设提供，因此在默认的设置下，无法通过内部 USB PHY 使用 DFU。 +.. warning:: - 然而，用户可以烧录 ``USB_PHY_SEL`` eFuse 使得内部 USB PHY 与 USB OTG 连接，而不是连接 USB_SERIAL_JTAG。有关 USB_SERIAL_JTAG 和 USB OTG 的更多详细信息，请参阅 *{IDF_TARGET_NAME} 技术参考手册* [`PDF <{IDF_TARGET_TRM_CN_URL}>`__]。 + 一些连接线采用非标准颜色连接，且一些驱动程序能够在对调了 D+ 和 D- 连接的情况下正常工作。因此如果无法检测到设备，请尝试下调换 D+ 和 D- 的连接线。 .. note:: - {IDF_TARGET_NAME} 芯片需要处于引导加载程序模式才能被检测为 DFU 设备并烧录。可以通过下拉 GPIO0（例如按下 BOOT 按钮）、拉低 RESET 片刻并释放 GPIO0 来实现。 + {IDF_TARGET_NAME} 芯片需要处于引导加载程序模式才能被检测为 DFU 设备并烧录。有关如何进入引导加载程序模式的更多信息，请参阅 `Boot Mode Selection `_。 .. _api_guide_dfu_build: @@ -98,7 +110,7 @@ USB 连接 Udev 规则（仅限 Linux） -------------------------------- -Udev 是 Linux 内核的设备管理器，允许用户在没有 ``sudo`` 的情况下运行 ``dfu-util`` （和 ``idf.py dfu-flash``）从而访问芯片。 +Udev 是 Linux 内核的设备管理器，允许在没有 ``sudo`` 的情况下运行 ``dfu-util`` （和 ``idf.py dfu-flash``）从而访问芯片。 创建文件 ``/etc/udev/rules.d/40-dfuse.rules``，并在文件中添加如下内容:: @@ -106,7 +118,7 @@ Udev 是 Linux 内核的设备管理器，允许用户在没有 ``sudo`` 的情 .. note:: - 请检查 ``groups`` 命令的输出。用户必须是上面指定的 `GROUP` 的成员。你可以为此使用其他现有的组（例如，在某些系统上使用 `uucp` 而不是 `plugdev`）或为此创建一个新的组。 + 请检查 ``groups`` 命令的输出。加入上面指定的 `GROUP` 组获取访问权限。你可以为此使用其他现有的组（例如，在某些系统上使用 `uucp` 而不是 `plugdev`）或为此创建一个新的组。 你可以选择重启计算机使之前的设置生效，或者手动运行 ``sudo udevadm trigger``，强制 Udev 触发新规则。 From 849ce255aaec10e72c7678f1548ba32931bf66ba Mon Sep 17 00:00:00 2001 From: Mahavir Jain Date: Wed, 18 Dec 2024 09:41:47 +0530 Subject: [PATCH 115/118] fix(esp_crt_bundle): remove expired DST Root CA X3 from bundle --- .../mbedtls/esp_crt_bundle/cacrt_local.pem | 29 ---------- .../mbedtls/esp_crt_bundle/gen_crt_bundle.py | 6 +- .../test_gen_crt_bundle.py | 6 +- .../main/crts/correct_sig_crt_esp32_com.pem | 56 ++++++++++++++++++- .../main/crts/wrong_sig_crt_esp32_com.pem | 56 ++++++++++++++++++- 5 files changed, 114 insertions(+), 39 deletions(-) diff --git a/components/mbedtls/esp_crt_bundle/cacrt_local.pem b/components/mbedtls/esp_crt_bundle/cacrt_local.pem index 3633ed16193..5c5afaf293d 100644 --- a/components/mbedtls/esp_crt_bundle/cacrt_local.pem +++ b/components/mbedtls/esp_crt_bundle/cacrt_local.pem @@ -2,32 +2,3 @@ ## Local CA Root Certificates ## ## Local CA Root Certificates that gets appended to "cacrt_all.pem" - - -## letsencrypt has generated a cross signed certificate with DST ROOT CA X3 -## for compatibility after the expiry of the certificate. -## The new certificate has the ISSUER name as DST Root CA X3. -## Thus, the handshake fails if esp_crt_bundle does not find the -## respective name in the crt_bundle. -## Keeping this certificate for compatibility reasons. -## This will be removed once the cross-signed certificate expires in Sep 2024. - -DST Root CA X3 -============== ------BEGIN CERTIFICATE----- -MIIDSjCCAjKgAwIBAgIQRK+wgNajJ7qJMDmGLvhAazANBgkqhkiG9w0BAQUFADA/MSQwIgYDVQQK -ExtEaWdpdGFsIFNpZ25hdHVyZSBUcnVzdCBDby4xFzAVBgNVBAMTDkRTVCBSb290IENBIFgzMB4X -DTAwMDkzMDIxMTIxOVoXDTIxMDkzMDE0MDExNVowPzEkMCIGA1UEChMbRGlnaXRhbCBTaWduYXR1 -cmUgVHJ1c3QgQ28uMRcwFQYDVQQDEw5EU1QgUm9vdCBDQSBYMzCCASIwDQYJKoZIhvcNAQEBBQAD -ggEPADCCAQoCggEBAN+v6ZdQCINXtMxiZfaQguzH0yxrMMpb7NnDfcdAwRgUi+DoM3ZJKuM/IUmT -rE4Orz5Iy2Xu/NMhD2XSKtkyj4zl93ewEnu1lcCJo6m67XMuegwGMoOifooUMM0RoOEqOLl5CjH9 -UL2AZd+3UWODyOKIYepLYYHsUmu5ouJLGiifSKOeDNoJjj4XLh7dIN9bxiqKqy69cK3FCxolkHRy -xXtqqzTWMIn/5WgTe1QLyNau7Fqckh49ZLOMxt+/yUFw7BZy1SbsOFU5Q9D8/RhcQPGX69Wam40d -utolucbY38EVAjqr2m7xPi71XAicPNaDaeQQmxkqtilX4+U9m5/wAl0CAwEAAaNCMEAwDwYDVR0T -AQH/BAUwAwEB/zAOBgNVHQ8BAf8EBAMCAQYwHQYDVR0OBBYEFMSnsaR7LHH62+FLkHX/xBVghYkQ -MA0GCSqGSIb3DQEBBQUAA4IBAQCjGiybFwBcqR7uKGY3Or+Dxz9LwwmglSBd49lZRNI+DT69ikug -dB/OEIKcdBodfpga3csTS7MgROSR6cz8faXbauX+5v3gTt23ADq1cEmv8uXrAvHRAosZy5Q6XkjE -GB5YGV8eAlrwDPGxrancWYaLbumR9YbK+rlmM6pZW87ipxZzR8srzJmwN0jP41ZL9c8PDHIyh8bw -RLtTcm1D9SZImlJnt1ir/md2cXjbDaJWFBM5JDGFoqgCWjBH4d1QB7wCCZAA62RjYJsWvIjJEubS -fZGL+T0yjWW06XyxV3bqxbYoOb8VZRzI9neWagqNdwvYkQsEjgfbKbYK7p2CNTUQ ------END CERTIFICATE----- diff --git a/components/mbedtls/esp_crt_bundle/gen_crt_bundle.py b/components/mbedtls/esp_crt_bundle/gen_crt_bundle.py index 2e5bca544b1..c5380213002 100755 --- a/components/mbedtls/esp_crt_bundle/gen_crt_bundle.py +++ b/components/mbedtls/esp_crt_bundle/gen_crt_bundle.py @@ -103,9 +103,9 @@ def add_from_pem(self, crt_str): crt += strg if count == 0: - raise InputError('No certificate found') - - status('Successfully added %d certificates' % count) + status('No certificate found') + else: + status('Successfully added %d certificates' % count) def add_from_der(self, crt_str): self.certificates.append(x509.load_der_x509_certificate(crt_str, default_backend())) diff --git a/components/mbedtls/esp_crt_bundle/test_gen_crt_bundle/test_gen_crt_bundle.py b/components/mbedtls/esp_crt_bundle/test_gen_crt_bundle/test_gen_crt_bundle.py index 4ad3b72b97c..759aa656ca2 100755 --- a/components/mbedtls/esp_crt_bundle/test_gen_crt_bundle/test_gen_crt_bundle.py +++ b/components/mbedtls/esp_crt_bundle/test_gen_crt_bundle/test_gen_crt_bundle.py @@ -1,5 +1,4 @@ #!/usr/bin/env python - import os import sys import unittest @@ -70,8 +69,9 @@ def test_invalid_crt_input(self): with self.assertRaisesRegex(gen_crt_bundle.InputError, 'Invalid certificate'): bundle.add_from_file(test_crts_path + invalid_test_file) - with self.assertRaisesRegex(gen_crt_bundle.InputError, 'No certificate found'): - bundle.add_from_pem('') + bundle_prev_len = len(bundle.certificates) + bundle.add_from_pem('') + self.assertEqual(len(bundle.certificates), bundle_prev_len) def test_non_ascii_crt_input(self): bundle = gen_crt_bundle.CertificateBundle() diff --git a/components/mbedtls/test_apps/main/crts/correct_sig_crt_esp32_com.pem b/components/mbedtls/test_apps/main/crts/correct_sig_crt_esp32_com.pem index 2b7c6e2fa0f..eab49b1e2bb 100644 --- a/components/mbedtls/test_apps/main/crts/correct_sig_crt_esp32_com.pem +++ b/components/mbedtls/test_apps/main/crts/correct_sig_crt_esp32_com.pem @@ -1,6 +1,58 @@ -----BEGIN CERTIFICATE----- -MIIFXDCCBESgAwIBAgISA9EyvtMwECvtdhru9l2xnEOgMA0GCSqGSIb3DQEBCwUAMEoxCzAJBgNVBAYTAlVTMRYwFAYDVQQKEw1MZXQncyBFbmNyeXB0MSMwIQYDVQQDExpMZXQncyBFbmNyeXB0IEF1dGhvcml0eSBYMzAeFw0yMDEwMjMxODE2MDFaFw0yMTAxMjExODE2MDFaMBgxFjAUBgNVBAMTDXd3dy5lc3AzMi5jb20wggEiMA0GCSqGSIb3DQEBAQUAA4IBDwAwggEKAoIBAQDGvklnzfCVCwTwNFr9+W263qTDSOK8cS6azwirKQl+62Z4E/fvhxvvmp02xiuWoeDpmqsQQCoZMiR77ziqBEDnf80J1S9ZSX3PRWsAYuDGMajTwiywMa7ttvs4Cm3BmXhSQpYEDTIrT7EVgOljSfkGAStKWK5fbkxMJ11eIQdA5KCLKOOPEofq4I5pgwk/4PGGjPSDA51w/XJyNX85hIMLdwXIrWBukrW+B/GFe7a/gdWZCUY2QMBsFPqwGYKZ41S1xtM4VnpZyMu9bvVmS9fvoYIyYUQ6zlktkLawIo56PIEO7wGu4tSNm62dQW23g7jxRwfLCQ7vUSSxOy35LyplAgMBAAGjggJsMIICaDAOBgNVHQ8BAf8EBAMCBaAwHQYDVR0lBBYwFAYIKwYBBQUHAwEGCCsGAQUFBwMCMAwGA1UdEwEB/wQCMAAwHQYDVR0OBBYEFHiCm41V5UtbkbDidxwrRbN1Bn58MB8GA1UdIwQYMBaAFKhKamMEfd265tE5t6ZFZe/zqOyhMG8GCCsGAQUFBwEBBGMwYTAuBggrBgEFBQcwAYYiaHR0cDovL29jc3AuaW50LXgzLmxldHNlbmNyeXB0Lm9yZzAvBggrBgEFBQcwAoYjaHR0cDovL2NlcnQuaW50LXgzLmxldHNlbmNyeXB0Lm9yZy8wIwYDVR0RBBwwGoIJZXNwMzIuY29tgg13d3cuZXNwMzIuY29tMEwGA1UdIARFMEMwCAYGZ4EMAQIBMDcGCysGAQQBgt8TAQEBMCgwJgYIKwYBBQUHAgEWGmh0dHA6Ly9jcHMubGV0c2VuY3J5cHQub3JnMIIBAwYKKwYBBAHWeQIEAgSB9ASB8QDvAHUAXNxDkv7mq0VEsV6a1FbmEDf71fpH3KFzlLJe5vbHDsoAAAF1VuOmWgAABAMARjBEAiAn6M8aTEpBZ+jZgPV67cuNCzuBfa0cXSmntpONtT0ZXAIgYP2ZEZmwkNrkLmYYrhDsPlNlMikj/Y+sObK31z8k30QAdgB9PvL4j/+IVWgkwsDKnlKJeSvFDngJfy5ql2iZfiLw1wAAAXVW46acAAAEAwBHMEUCIF9duaNUkko6siaTN1qY0Jqep7KQ5l/c9bhxkXLvwOLPAiEAlf6Zn/EaXCVCubM1ouKBaYXggKhWWDVRlfPclyDqmHgwDQYJKoZIhvcNAQELBQADggEBAFjhZtXgJTgDc8x19LWE3LVlPsQBNmO1WIuFaTSOShmXHocIy1pR80TWBa905EB0gdVqw7Ez7e84DkIJlczH+1fPUZs8K1TUtte7iR/NfpExrbFXDiGM7kkq9FzVU2xDzLIvlYPFkIfcY1fiaYcnlsS3F3p+vfVidVel61mtBQ7mM2Mf0Vg3emGcw7uuNq5Q1QWs6ILM+JRePDnOD9JQBbK3XZ8imIXr4ewW2VG85NHTyRXRCEP9PwEsMmpqmsYk8vonNz9GeFEPusQ5BWvLvlpC/lprhgpFdxyPQ8iTqBjG5m36J+6TaQdyFi2kpTdnHzV6uvBgyTEUz/Zw3rjlxT8= +MIIE8jCCA9qgAwIBAgISBEkOpd5XXwkXRsF+YCP7+zDBMA0GCSqGSIb3DQEBCwUA +MDMxCzAJBgNVBAYTAlVTMRYwFAYDVQQKEw1MZXQncyBFbmNyeXB0MQwwCgYDVQQD +EwNSMTAwHhcNMjQxMTE5MTgxODE5WhcNMjUwMjE3MTgxODE4WjAUMRIwEAYDVQQD +Ewllc3AzMi5jb20wggEiMA0GCSqGSIb3DQEBAQUAA4IBDwAwggEKAoIBAQDvyscS +8KoMMkKRloLau2glrZcQAudqCtXLSN1M1GIV1/iVIwQZ50U6veJl4AElP89owy1A +Z7vMYyr6+chns7nx6WO67P63RkZliO0j1i00cy50ONW2VT4Es/Qs+3vS0MlEjloj +QlI6ZM62/gwFlYapD1QDhyHq5j1q5jlwmNerf1U58FZ+uSXBjDbl8p7E+kNeBYF3 +Dk3gp09+64ZHtNz3zzxUd3FBt0pbEmJZDiT0mH0DsmqaYh4pckU3qBzUx3PSce8j +/UJsymJChg9d1NmzsgJMmCEPb7G2Q9X5BlXSHjz1KwO0TaDN6GFiQTiVMEO0ltl/ +HsBcpQ+C5w+7upg7AgMBAAGjggIdMIICGTAOBgNVHQ8BAf8EBAMCBaAwHQYDVR0l +BBYwFAYIKwYBBQUHAwEGCCsGAQUFBwMCMAwGA1UdEwEB/wQCMAAwHQYDVR0OBBYE +FGCFENPyhsWmQfXsvtO35u9jlFSSMB8GA1UdIwQYMBaAFLu8w0el5LypxsOkcgwQ +jaI14cjoMFcGCCsGAQUFBwEBBEswSTAiBggrBgEFBQcwAYYWaHR0cDovL3IxMC5v +LmxlbmNyLm9yZzAjBggrBgEFBQcwAoYXaHR0cDovL3IxMC5pLmxlbmNyLm9yZy8w +IwYDVR0RBBwwGoIJZXNwMzIuY29tgg13d3cuZXNwMzIuY29tMBMGA1UdIAQMMAow +CAYGZ4EMAQIBMIIBBQYKKwYBBAHWeQIEAgSB9gSB8wDxAHYAE0rfGrWYQgl4DG/v +THqRpBa3I0nOWFdq367ap8Kr4CIAAAGTRdsjWgAABAMARzBFAiEA7hUzakbnOXOt +tnDgNY5060a1SAR9yb0BfeGIKHGP4w0CIHll4tHmq7DhLYlysoMeP5qjezlkMRRr +1prMsqjTwZytAHcAouMK5EXvva2bfjjtR2d3U9eCW4SU1yteGyzEuVCkR+cAAAGT +RdsqcAAABAMASDBGAiEA9y7+a2OJjfXGIvjyG84IL8MSM1XFvHtwETFMssWXJDAC +IQC8SWpI/kpX09zRqD5n1ySdNrgypxJo3PUGAzCHjir5NTANBgkqhkiG9w0BAQsF +AAOCAQEALFIaefXlonTt88v4CwbJpPUEwapoNxlE5nefwZPzmB/g09HhZw0GLFcE +wxUBNTmy9zfANFTiDj7vCx44U+KnvJ6SmJg2EMHfst/6gnTtOjO+tgg3dt26XMN7 +p9BmsXlRY0wB09D2X4rAczNW6Wl2/Hi38k3cPwm4RcNLe7LsNGBkUV4BZZwazW5K +PNQKZAP+3ApTnVDVQqVK/7sXqHni5j8yEjg715nD5fBMBX0CHaUe+hRnMJo3x700 +RKaI0zAr8jxJKYFqBN6l7tzcqcnDfP7k8FicKw4PtN1mfG6n/JyvQQZk6bJlSviK +BLhDw+BZRfvbT1x4igGDX+tQUy1e4g== -----END CERTIFICATE----- -----BEGIN CERTIFICATE----- -MIIEkjCCA3qgAwIBAgIQCgFBQgAAAVOFc2oLheynCDANBgkqhkiG9w0BAQsFADA/MSQwIgYDVQQKExtEaWdpdGFsIFNpZ25hdHVyZSBUcnVzdCBDby4xFzAVBgNVBAMTDkRTVCBSb290IENBIFgzMB4XDTE2MDMxNzE2NDA0NloXDTIxMDMxNzE2NDA0NlowSjELMAkGA1UEBhMCVVMxFjAUBgNVBAoTDUxldCdzIEVuY3J5cHQxIzAhBgNVBAMTGkxldCdzIEVuY3J5cHQgQXV0aG9yaXR5IFgzMIIBIjANBgkqhkiG9w0BAQEFAAOCAQ8AMIIBCgKCAQEAnNMM8FrlLke3cl03g7NoYzDq1zUmGSXhvb418XCSL7e4S0EFq6meNQhY7LEqxGiHC6PjdeTm86dicbp5gWAf15Gan/PQeGdxyGkOlZHP/uaZ6WA8SMx+yk13EiSdRxta67nsHjcAHJyse6cF6s5K671B5TaYucv9bTyWaN8jKkKQDIZ0Z8h/pZq4UmEUEz9l6YKHy9v6Dlb2honzhT+Xhq+w3Brvaw2VFn3EK6BlspkENnWAa6xK8xuQSXgvopZPKiAlKQTGdMDQMc2PMTiVFrqoM7hD8bEfwzB/onkxEz0tNvjj/PIzark5McWvxI0NHWQWM6r6hCm21AvA2H3DkwIDAQABo4IBfTCCAXkwEgYDVR0TAQH/BAgwBgEB/wIBADAOBgNVHQ8BAf8EBAMCAYYwfwYIKwYBBQUHAQEEczBxMDIGCCsGAQUFBzABhiZodHRwOi8vaXNyZy50cnVzdGlkLm9jc3AuaWRlbnRydXN0LmNvbTA7BggrBgEFBQcwAoYvaHR0cDovL2FwcHMuaWRlbnRydXN0LmNvbS9yb290cy9kc3Ryb290Y2F4My5wN2MwHwYDVR0jBBgwFoAUxKexpHsscfrb4UuQdf/EFWCFiRAwVAYDVR0gBE0wSzAIBgZngQwBAgEwPwYLKwYBBAGC3xMBAQEwMDAuBggrBgEFBQcCARYiaHR0cDovL2Nwcy5yb290LXgxLmxldHNlbmNyeXB0Lm9yZzA8BgNVHR8ENTAzMDGgL6AthitodHRwOi8vY3JsLmlkZW50cnVzdC5jb20vRFNUUk9PVENBWDNDUkwuY3JsMB0GA1UdDgQWBBSoSmpjBH3duubRObemRWXv86jsoTANBgkqhkiG9w0BAQsFAAOCAQEA3TPXEfNjWDjdGBX7CVW+dla5cEilaUcne8IkCJLxWh9KEik3JHRRHGJouM2VcGfl96S8TihRzZvoroed6ti6WqEBmtzw3Wodatg+VyOeph4EYpr/1wXKtx8/wApIvJSwtmVi4MFU5aMqrSDE6ea73Mj2tcMyo5jMd6jmeWUHK8so/joWUoHOUgwuX4Po1QYz+3dszkDqMp4fklxBwXRsW10KXzPMTZ+sOPAveyxindmjkW8lGy+QsRlGPfZ+G6Z6h7mjem0Y+iWlkYcV4PIWL1iwBi8saCbGS5jN2p8M+X+Q7UNKEkROb3N6KOqkqm57TH2H3eDJAkSnh6/DNFu0Qg== +MIIFBTCCAu2gAwIBAgIQS6hSk/eaL6JzBkuoBI110DANBgkqhkiG9w0BAQsFADBP +MQswCQYDVQQGEwJVUzEpMCcGA1UEChMgSW50ZXJuZXQgU2VjdXJpdHkgUmVzZWFy +Y2ggR3JvdXAxFTATBgNVBAMTDElTUkcgUm9vdCBYMTAeFw0yNDAzMTMwMDAwMDBa +Fw0yNzAzMTIyMzU5NTlaMDMxCzAJBgNVBAYTAlVTMRYwFAYDVQQKEw1MZXQncyBF +bmNyeXB0MQwwCgYDVQQDEwNSMTAwggEiMA0GCSqGSIb3DQEBAQUAA4IBDwAwggEK +AoIBAQDPV+XmxFQS7bRH/sknWHZGUCiMHT6I3wWd1bUYKb3dtVq/+vbOo76vACFL +YlpaPAEvxVgD9on/jhFD68G14BQHlo9vH9fnuoE5CXVlt8KvGFs3Jijno/QHK20a +/6tYvJWuQP/py1fEtVt/eA0YYbwX51TGu0mRzW4Y0YCF7qZlNrx06rxQTOr8IfM4 +FpOUurDTazgGzRYSespSdcitdrLCnF2YRVxvYXvGLe48E1KGAdlX5jgc3421H5KR +mudKHMxFqHJV8LDmowfs/acbZp4/SItxhHFYyTr6717yW0QrPHTnj7JHwQdqzZq3 +DZb3EoEmUVQK7GH29/Xi8orIlQ2NAgMBAAGjgfgwgfUwDgYDVR0PAQH/BAQDAgGG +MB0GA1UdJQQWMBQGCCsGAQUFBwMCBggrBgEFBQcDATASBgNVHRMBAf8ECDAGAQH/ +AgEAMB0GA1UdDgQWBBS7vMNHpeS8qcbDpHIMEI2iNeHI6DAfBgNVHSMEGDAWgBR5 +tFnme7bl5AFzgAiIyBpY9umbbjAyBggrBgEFBQcBAQQmMCQwIgYIKwYBBQUHMAKG +Fmh0dHA6Ly94MS5pLmxlbmNyLm9yZy8wEwYDVR0gBAwwCjAIBgZngQwBAgEwJwYD +VR0fBCAwHjAcoBqgGIYWaHR0cDovL3gxLmMubGVuY3Iub3JnLzANBgkqhkiG9w0B +AQsFAAOCAgEAkrHnQTfreZ2B5s3iJeE6IOmQRJWjgVzPw139vaBw1bGWKCIL0vIo +zwzn1OZDjCQiHcFCktEJr59L9MhwTyAWsVrdAfYf+B9haxQnsHKNY67u4s5Lzzfd +u6PUzeetUK29v+PsPmI2cJkxp+iN3epi4hKu9ZzUPSwMqtCceb7qPVxEbpYxY1p9 +1n5PJKBLBX9eb9LU6l8zSxPWV7bK3lG4XaMJgnT9x3ies7msFtpKK5bDtotij/l0 +GaKeA97pb5uwD9KgWvaFXMIEt8jVTjLEvwRdvCn294GPDF08U8lAkIv7tghluaQh +1QnlE4SEN4LOECj8dsIGJXpGUk3aU3KkJz9icKy+aUgA+2cP21uh6NcDIS3XyfaZ +QjmDQ993ChII8SXWupQZVBiIpcWO4RqZk3lr7Bz5MUCwzDIA359e57SSq5CCkY0N +4B6Vulk7LktfwrdGNVI5BsC9qqxSwSKgRJeZ9wygIaehbHFHFhcBaMDKpiZlBHyz +rsnnlFXCb5s8HKn5LsUgGvB24L7sGNZP2CX7dhHov+YhD+jozLW2p9W4959Bz2Ei +RmqDtmiXLnzqTpXbI+suyCsohKRg6Un0RC47+cpiVwHiXZAW+cn8eiNIjqbVgXLx +KPpdzvvtTnOPlC7SQZSYmdunr3Bf9b77AiC/ZidstK36dRILKz7OA54= -----END CERTIFICATE----- diff --git a/components/mbedtls/test_apps/main/crts/wrong_sig_crt_esp32_com.pem b/components/mbedtls/test_apps/main/crts/wrong_sig_crt_esp32_com.pem index 0d6b8b7208a..0fbdf0d0124 100644 --- a/components/mbedtls/test_apps/main/crts/wrong_sig_crt_esp32_com.pem +++ b/components/mbedtls/test_apps/main/crts/wrong_sig_crt_esp32_com.pem @@ -1,6 +1,58 @@ -----BEGIN CERTIFICATE----- -MIIFXDCCBESgAwIBAgISA9EyvtMwECvtdhru9l2xnEOgMA0GCSqGSIb3DQEBCwUAMEoxCzAJBgNVBAYTAlVTMRYwFAYDVQQKEw1MZXQncyBFbmNyeXB0MSMwIQYDVQQDExpMZXQncyBFbmNyeXB0IEF1dGhvcml0eSBYMzAeFw0yMDEwMjMxODE2MDFaFw0yMTAxMjExODE2MDFaMBgxFjAUBgNVBAMTDXd3dy5lc3AzMi5jb20wggEiMA0GCSqGSIb3DQEBAQUAA4IBDwAwggEKAoIBAQDGvklnzfCVCwTwNFr9+W263qTDSOK8cS6azwirKQl+62Z4E/fvhxvvmp02xiuWoeDpmqsQQCoZMiR77ziqBEDnf80J1S9ZSX3PRWsAYuDGMajTwiywMa7ttvs4Cm3BmXhSQpYEDTIrT7EVgOljSfkGAStKWK5fbkxMJ11eIQdA5KCLKOOPEofq4I5pgwk/4PGGjPSDA51w/XJyNX85hIMLdwXIrWBukrW+B/GFe7a/gdWZCUY2QMBsFPqwGYKZ41S1xtM4VnpZyMu9bvVmS9fvoYIyYUQ6zlktkLawIo56PIEO7wGu4tSNm62dQW23g7jxRwfLCQ7vUSSxOy35LyplAgMBAAGjggJsMIICaDAOBgNVHQ8BAf8EBAMCBaAwHQYDVR0lBBYwFAYIKwYBBQUHAwEGCCsGAQUFBwMCMAwGA1UdEwEB/wQCMAAwHQYDVR0OBBYEFHiCm41V5UtbkbDidxwrRbN1Bn58MB8GA1UdIwQYMBaAFKhKamMEfd265tE5t6ZFZe/zqOyhMG8GCCsGAQUFBwEBBGMwYTAuBggrBgEFBQcwAYYiaHR0cDovL29jc3AuaW50LXgzLmxldHNlbmNyeXB0Lm9yZzAvBggrBgEFBQcwAoYjaHR0cDovL2NlcnQuaW50LXgzLmxldHNlbmNyeXB0Lm9yZy8wIwYDVR0RBBwwGoIJZXNwMzIuY29tgg13d3cuZXNwMzIuY29tMEwGA1UdIARFMEMwCAYGZ4EMAQIBMDcGCysGAQQBgt8TAQEBMCgwJgYIKwYBBQUHAgEWGmh0dHA6Ly9jcHMubGV0c2VuY3J5cHQub3JnMIIBAwYKKwYBBAHWeQIEAgSB9ASB8QDvAHUAXNxDkv7mq0VEsV6a1FbmEDf71fpH3KFzlLJe5vbHDsoAAAF1VuOmWgAABAMARjBEAiAn6M8aTEpBZ+jZgPV67cuNCzuBfa0cXSmntpONtT0ZXAIgYP2ZEZmwkNrkLmYYrhDsPlNlMikj/Y+sObK31z8k30QAdgB9PvL4j/+IVWgkwsDKnlKJeSvFDngJfy5ql2iZfiLw1wAAAXVW46acAAAEAwBHMEUCIF9duaNUkko6siaTN1qY0Jqep7KQ5l/c9bhxkXLvwOLPAiEAlf6Zn/EaXCVCubM1ouKBaYXggKhWWDVRlfPclyDqmHgwDQYJKoZIhvcNAQELBQADggEBAFjhZtXgJTgDc8x19LWE3LVlPsQBNmO1WIuFaTSOShmXHocIy1pR80TWBa905EB0gdVqw7Ez7e84DkIJlczH+1fPUZs8K1TUtte7iR/NfpExrbFXDiGM7kkq9FzVU2xDzLIvlYPFkIfcY1fiaYcnlsS3F3p+vfVidVel61mtBQ7mM2Mf0Vg3emGcw7uuNq5Q1QWs6ILM+JRePDnOD9JQBbK3XZ8imIXr4ewW2VG85NHTyRXRCEP9PwEsMmpqmsYk8vonNz9GeFEPusQ5BWvLvlpC/lprhgpFdxyPQ8iTqBjG5m36J+6TaQdyFi2kpTdnHzV6uvBgyTEUz/Zw3rjlxT8= +MIIE8jCCA9qgAwIBAgISBEkOpd5XXwkXRsF+YCP7+zDBMA0GCSqGSIb3DQEBCwUA +MDMxCzAJBgNVBAYTAlVTMRYwFAYDVQQKEw1MZXQncyBFbmNyeXB0MQwwCgYDVQQD +EwNSMTAwHhcNMjQxMTE5MTgxODE5WhcNMjUwMjE3MTgxODE4WjAUMRIwEAYDVQQD +Ewllc3AzMi5jb20wggEiMA0GCSqGSIb3DQEBAQUAA4IBDwAwggEKAoIBAQDvyscS +8KoMMkKRloLau2glrZcQAudqCtXLSN1M1GIV1/iVIwQZ50U6veJl4AElP89owy1A +Z7vMYyr6+chns7nx6WO67P63RkZliO0j1i00cy50ONW2VT4Es/Qs+3vS0MlEjloj +QlI6ZM62/gwFlYapD1QDhyHq5j1q5jlwmNerf1U58FZ+uSXBjDbl8p7E+kNeBYF3 +Dk3gp09+64ZHtNz3zzxUd3FBt0pbEmJZDiT0mH0DsmqaYh4pckU3qBzUx3PSce8j +/UJsymJChg9d1NmzsgJMmCEPb7G2Q9X5BlXSHjz1KwO0TaDN6GFiQTiVMEO0ltl/ +HsBcpQ+C5w+7upg7AgMBAAGjggIdMIICGTAOBgNVHQ8BAf8EBAMCBaAwHQYDVR0l +BBYwFAYIKwYBBQUHAwEGCCsGAQUFBwMCMAwGA1UdEwEB/wQCMAAwHQYDVR0OBBYE +FGCFENPyhsWmQfXsvtO35u9jlFSSMB8GA1UdIwQYMBaAFLu8w0el5LypxsOkcgwQ +jaI14cjoMFcGCCsGAQUFBwEBBEswSTAiBggrBgEFBQcwAYYWaHR0cDovL3IxMC5v +LmxlbmNyLm9yZzAjBggrBgEFBQcwAoYXaHR0cDovL3IxMC5pLmxlbmNyLm9yZy8w +IwYDVR0RBBwwGoIJZXNwMzIuY29tgg13d3cuZXNwMzIuY29tMBMGA1UdIAQMMAow +CAYGZ4EMAQIBMIIBBQYKKwYBBAHWeQIEAgSB9gSB8wDxAHYAE0rfGrWYQgl4DG/v +THqRpBa3I0nOWFdq367ap8Kr4CIAAAGTRdsjWgAABAMARzBFAiEA7hUzakbnOXOt +tnDgNY5060a1SAR9yb0BfeGIKHGP4w0CIHll4tHmq7DhLYlysoMeP5qjezlkMRRr +1prMsqjTwZytAHcAouMK5EXvva2bfjjtR2d3U9eCW4SU1yteGyzEuVCkR+cAAAGT +RdsqcAAABAMASDBGAiEA9y7+a2OJjfXGIvjyG84IL8MSM1XFvHtwETFMssWXJDAC +IQC8SWpI/kpX09zRqD5n1ySdNrgypxJo3PUGAzCHjir5NTANBgkqhkiG9w0BAQsF +AAOCAQEALFIaefXlonTt88v4CwbJpPUEwapoNxlE5nefwZPzmB/g09HhZw0GLFcE +wxUBNTmy9zfANFTiDj7vCx44U+KnvJ6SmJg2EMHfst/6gnTtOjO+tgg3dt26XMN7 +p9BmsXlRY0wB09D2X4rAczNW6Wl2/Hi38k3cPwm4RcNLe7LsNGBkUV4BZZwazW5K +PNQKZAP+3ApTnVDVQqVK/7sXqHni5j8yEjg715nD5fBMBX0CHaUe+hRnMJo3x700 +RKaI0zAr8jxJKYFqBN6l7tzcqcnDfP7k8FicKw4PtN1mfG6n/JyvQQZk6bJlSviK +BLhDw+BZRfvbT1x4igGDX+tQUy1e4g== -----END CERTIFICATE----- -----BEGIN CERTIFICATE----- -MIIEkjCCA3qgAwIBAgIQCgFBQgAAAVOFc2oLheynCDANBgkqhkiG9w0BAQsFADA/MSQwIgYDVQQKExtEaWdpdGFsIFNpZ25hdHVyZSBUcnVzdCBDby4xFzAVBgNVBAMTDkRTVCBSb290IENBIFgzMB4XDTE2MDMxNzE2NDA0NloXDTIxMDMxNzE2NDA0NlowSjELMAkGA1UEBhMCVVMxFjAUBgNVBAoTDUxldCdzIEVuY3J5cHQxIzAhBgNVBAMTGkxldCdzIEVuY3J5cHQgQXV0aG9yaXR5IFgzMIIBIjANBgkqhkiG9w0BAQEFAAOCAQ8AMIIBCgKCAQEAnNMM8FrlLke3cl03g7NoYzDq1zUmGSXhvb418XCSL7e4S0EFq6meNQhY7LEqxGiHC6PjdeTm86dicbp5gWAf15Gan/PQeGdxyGkOlZHP/uaZ6WA8SMx+yk13EiSdRxta67nsHjcAHJyse6cF6s5K671B5TaYucv9bTyWaN8jKkKQDIZ0Z8h/pZq4UmEUEz9l6YKHy9v6Dlb2honzhT+Xhq+w3Brvaw2VFn3EK6BlspkENnWAa6xK8xuQSXgvopZPKiAlKQTGdMDQMc2PMTiVFrqoM7hD8bEfwzB/onkxEz0tNvjj/PIzark5McWvxI0NHWQWM6r6hCm21AvA2H3DkwIDAQABo4IBfTCCAXkwEgYDVR0TAQH/BAgwBgEB/wIBADAOBgNVHQ8BAf8EBAMCAYYwfwYIKwYBBQUHAQEEczBxMDIGCCsGAQUFBzABhiZodHRwOi8vaXNyZy50cnVzdGlkLm9jc3AuaWRlbnRydXN0LmNvbTA7BggrBgEFBQcwAoYvaHR0cDovL2FwcHMuaWRlbnRydXN0LmNvbS9yb290cy9kc3Ryb290Y2F4My5wN2MwHwYDVR0jBBgwFoAUxKexpHsscfrb4UuQdf/EFWCFiRAwVAYDVR0gBE0wSzAIBgZngQwBAgEwPwYLKwYBBAGC3xMBAQEwMDAuBggrBgEFBQcCARYiaHR0cDovL2Nwcy5yb290LXgxLmxldHNlbmNyeXB0Lm9yZzA8BgNVHR8ENTAzMDGgL6AthitodHRwOi8vY3JsLmlkZW50cnVzdC5jb20vRFNUUk9PVENBWDNDUkwuY3JsMB0GA1UdDgQWBBSoSmpjBH3duubRObemRWXv86jsoTANBgkqhkiG9w0BAQsFAAOCAQEA3TPXEfNjWDjdGBX7CVW+dla5cEilaUcne8IkCJLxWh9KEik3JHRRHGJouM2VcGfl96S8TihRzZvoroed6ti6WqEBmtzw3Wodatg+VyOeph4EYpr/1wXKtx8/wApIvJSwtmVi4MFU5aMqrSDE6ea73Mj2tcMyo5jMd6jmeWUHK8so/joWUoHOUgwuX4Po1QYz+3dszkDqMp4fklxBwXRsW10KXzPMTZ+sOPAveyxindmjkW8lGy+QsRlGPfZ+G6Z6h7mjem0Y+iWlkYcV4PIWL1iwBi8saCbGS5jN2p8M+X+Q7UNKEkROb3N6KOqkqm57TH2H3eDJAkSnh6/DNFu1Qg== +MIIFBTCCAu2gAwIBAgIQS6hSk/eaL6JzBkuoBI110DANBgkqhkiG9w0BAQsFADBP +MQswCQYDVQQGEwJVUzEpMCcGA1UEChMgSW50ZXJuZXQgU2VjdXJpdHkgUmVzZWFy +Y2ggR3JvdXAxFTATBgNVBAMTDElTUkcgUm9vdCBYMTAeFw0yNDAzMTMwMDAwMDBa +Fw0yNzAzMTIyMzU5NTlaMDMxCzAJBgNVBAYTAlVTMRYwFAYDVQQKEw1MZXQncyBF +bmNyeXB0MQwwCgYDVQQDEwNSMTAwggEiMA0GCSqGSIb3DQEBAQUAA4IBDwAwggEK +AoIBAQDPV+XmxFQS7bRH/sknWHZGUCiMHT6I3wWd1bUYKb3dtVq/+vbOo76vACFL +YlpaPAEvxVgD9on/jhFD68G14BQHlo9vH9fnuoE5CXVlt8KvGFs3Jijno/QHK20a +/6tYvJWuQP/py1fEtVt/eA0YYbwX51TGu0mRzW4Y0YCF7qZlNrx06rxQTOr8IfM4 +FpOUurDTazgGzRYSespSdcitdrLCnF2YRVxvYXvGLe48E1KGAdlX5jgc3421H5KR +mudKHMxFqHJV8LDmowfs/acbZp4/SItxhHFYyTr6717yW0QrPHTnj7JHwQdqzZq3 +DZb3EoEmUVQK7GH29/Xi8orIlQ2NAgMBAAGjgfgwgfUwDgYDVR0PAQH/BAQDAgGG +MB0GA1UdJQQWMBQGCCsGAQUFBwMCBggrBgEFBQcDATASBgNVHRMBAf8ECDAGAQH/ +AgEAMB0GA1UdDgQWBBS7vMNHpeS8qcbDpHIMEI2iNeHI6DAfBgNVHSMEGDAWgBR5 +tFnme7bl5AFzgAiIyBpY9umbbjAyBggrBgEFBQcBAQQmMCQwIgYIKwYBBQUHMAKG +Fmh0dHA6Ly94MS5pLmxlbmNyLm9yZy8wEwYDVR0gBAwwCjAIBgZngQwBAgEwJwYD +VR0fBCAwHjAcoBqgGIYWaHR0cDovL3gxLmMubGVuY3Iub3JnLzANBgkqhkiG9w0B +AQsFAAOCAgEAkrHnQTfreZ2B5s3iJeE6IOmQRJWjgVzPw139vaBw1bGWKCIL0vIo +zwzn1OZDjCQiHcFCktEJr59L9MhwTyAWsVrdAfYf+B9haxQnsHKNY67u4s5Lzzfd +u6PUzeetUK29v+PsPmI2cJkxp+iN3epi4hKu9ZzUPSwMqtCceb7qPVxEbpYxY1p9 +1n5PJKBLBX9eb9LU6l8zSxPWV7bK3lG4XaMJgnT9x3ies7msFtpKK5bDtotij/l0 +GaKeA97pb5uwD9KgWvaFXMIEt8jVTjLEvwRdvCn294GPDF08U8lAkIv7tghluaQh +1QnlE4SEN4LOECj8dsIGJXpGUk3aU3KkJz9icKy+aUgA+2cP21uh6NcDIS3XyfaZ +QjmDQ993ChII8SXWupQZVBiIpcWO4RqZk3lr7Bz5MUCwzDIA359e57SSq5CCkY0N +4B6Vulk7LktfwrdGNVI5BsC9qqxSwSKgRJeZ9wygIaehbHFHFhcBaMDKpiZlBHyz +rsnnlFXCb5s8HKn5LsUgGvB24L7sGNZP2CX7dhHov+YhD+jozLW2p9W4959Bz2Ei +RmqDtmiXLnzqTpXbI+suyCsohKRg6Un0RC47+cpiVwHiXZAW+cn8eiNIjqbVgXLx +KPpdzvvtTnOPlC7SQZSYmdunr3Bf9b77AiC/ZidstK36dRILKz71A54= -----END CERTIFICATE----- From c9cdf51b059abb42f621242efb40234ee536f2ad Mon Sep 17 00:00:00 2001 From: zhanghaipeng Date: Wed, 18 Dec 2024 11:49:53 +0800 Subject: [PATCH 116/118] docs(ble/bluedroid): Added BLE log when bond info was deleted --- components/bt/host/bluedroid/bta/dm/bta_dm_act.c | 4 +++- components/bt/host/bluedroid/btc/core/btc_dm.c | 3 +++ 2 files changed, 6 insertions(+), 1 deletion(-) diff --git a/components/bt/host/bluedroid/bta/dm/bta_dm_act.c b/components/bt/host/bluedroid/bta/dm/bta_dm_act.c index 3940dc308bf..d33696e3196 100644 --- a/components/bt/host/bluedroid/bta/dm/bta_dm_act.c +++ b/components/bt/host/bluedroid/bta/dm/bta_dm_act.c @@ -4972,7 +4972,9 @@ static UINT8 bta_dm_ble_smp_cback (tBTM_LE_EVT event, BD_ADDR bda, tBTM_LE_EVT_D if (p_data->complt.reason != 0) { sec_event.auth_cmpl.fail_reason = BTA_DM_AUTH_CONVERT_SMP_CODE(((UINT8)p_data->complt.reason)); /* delete this device entry from Sec Dev DB */ - bta_dm_remove_sec_dev_entry (bda); + APPL_TRACE_WARNING("%s remove bond,rsn %d, BDA:0x%02X%02X%02X%02X%02X%02X", __func__, sec_event.auth_cmpl.fail_reason, + bda[0], bda[1], bda[2], bda[3], bda[4], bda[5]); + bta_dm_remove_sec_dev_entry(bda); } else { sec_event.auth_cmpl.success = TRUE; if (!p_data->complt.smp_over_br) { diff --git a/components/bt/host/bluedroid/btc/core/btc_dm.c b/components/bt/host/bluedroid/btc/core/btc_dm.c index c50d8884744..deca600c773 100644 --- a/components/bt/host/bluedroid/btc/core/btc_dm.c +++ b/components/bt/host/bluedroid/btc/core/btc_dm.c @@ -293,6 +293,9 @@ static void btc_dm_ble_auth_cmpl_evt (tBTA_DM_AUTH_CMPL *p_auth_cmpl) status = BT_STATUS_AUTH_REJECTED; break; default: + BTC_TRACE_WARNING ("%s, remove bond in flash bd_addr: %08x%04x", __func__, + (p_auth_cmpl->bd_addr[0] << 24) + (p_auth_cmpl->bd_addr[1] << 16) + (p_auth_cmpl->bd_addr[2] << 8) + p_auth_cmpl->bd_addr[3], + (p_auth_cmpl->bd_addr[4] << 8) + p_auth_cmpl->bd_addr[5]); btc_dm_remove_ble_bonding_keys(); status = BT_STATUS_FAIL; break; From 0140c6fb78bb68853a66aedb91004aa5b78c7aa2 Mon Sep 17 00:00:00 2001 From: Marius Vikhammer Date: Wed, 11 Dec 2024 11:43:53 +0800 Subject: [PATCH 117/118] feat(docs): Replace PDF download link with HTML zip download link PDF build would randomly fail after S3 docs grew to a certain size. At 3k+ pages PDF is not very usable anyways. For offline use an HTML archive makes more sense. --- .gitlab/ci/docs.yml | 16 ---------------- docs/conf_common.py | 1 + docs/en/conf.py | 4 +++- docs/zh_CN/conf.py | 4 +++- 4 files changed, 7 insertions(+), 18 deletions(-) diff --git a/.gitlab/ci/docs.yml b/.gitlab/ci/docs.yml index f66eae3d591..3f7dd1c6086 100644 --- a/.gitlab/ci/docs.yml +++ b/.gitlab/ci/docs.yml @@ -139,19 +139,6 @@ build_docs_html_partial: - DOCLANG: "zh_CN" DOCTGT: "esp32p4" -build_docs_pdf: - extends: - - .build_docs_template - - .doc-rules:build:docs-full - artifacts: - when: always - paths: - - docs/_build/*/*/latex/* - expire_in: 4 days - allow_failure: true # TODO IDFCI-2216 - variables: - DOC_BUILDERS: "latex" - .deploy_docs_template: image: $ESP_IDF_DOC_ENV_IMAGE variables: @@ -180,8 +167,6 @@ deploy_docs_preview: optional: true - job: build_docs_html_full optional: true - - job: build_docs_pdf - optional: true variables: TYPE: "preview" # older branches use DOCS_DEPLOY_KEY, DOCS_SERVER, DOCS_SERVER_USER, DOCS_PATH for preview server so we keep these names for 'preview' @@ -202,7 +187,6 @@ deploy_docs_production: dependencies: # set dependencies to null to avoid missing artifacts issue needs: # ensure runs after push_to_github succeeded - build_docs_html_full - - build_docs_pdf - job: push_to_github artifacts: false variables: diff --git a/docs/conf_common.py b/docs/conf_common.py index 7892e2c07bd..357585ab70b 100644 --- a/docs/conf_common.py +++ b/docs/conf_common.py @@ -331,6 +331,7 @@ 'esp_docs.idf_extensions.kconfig_reference', 'esp_docs.idf_extensions.gen_idf_tools_links', 'esp_docs.esp_extensions.run_doxygen', + 'esp_docs.esp_extensions.add_html_zip', 'linuxdoc.rstFlatTable', # https://return42.github.io/linuxdoc/linuxdoc-howto/table-markup.html#flat-table ] diff --git a/docs/en/conf.py b/docs/en/conf.py index c69e51b6427..dbb6edf2911 100644 --- a/docs/en/conf.py +++ b/docs/en/conf.py @@ -1,9 +1,9 @@ +# type: ignore # -*- coding: utf-8 -*- # # English Language RTD & Sphinx config file # # Uses ../conf_common.py for most non-language-specific settings. - # Importing conf_common adds all the non-language-specific # parts to this conf module try: @@ -25,3 +25,5 @@ # The language for content autogenerated by Sphinx. Refer to documentation # for a list of supported languages. language = 'en' + +html_zip = f'esp-idf-{language}-{release}' # noqa: F405 diff --git a/docs/zh_CN/conf.py b/docs/zh_CN/conf.py index cc6fbc27121..cf62a26e929 100644 --- a/docs/zh_CN/conf.py +++ b/docs/zh_CN/conf.py @@ -1,9 +1,9 @@ +# type: ignore # -*- coding: utf-8 -*- # # English Language RTD & Sphinx config file # # Uses ../conf_common.py for most non-language-specific settings. - # Importing conf_common adds all the non-language-specific # parts to this conf module try: @@ -25,3 +25,5 @@ # The language for content autogenerated by Sphinx. Refer to documentation # for a list of supported languages. language = 'zh_CN' + +html_zip = f'esp-idf-{language}-{release}' # noqa: F405 From 36e65097cd705080d6f921d84a09e397ee2aa411 Mon Sep 17 00:00:00 2001 From: Alexey Lapshin Date: Fri, 4 Oct 2024 16:21:09 +0700 Subject: [PATCH 118/118] feat(gdbstub): add riscv xesppie extension support --- .../esp_gdbstub/src/port/riscv/rv_decode.c | 25 +- .../rv_decode/test_rv_decode.cpp | 377 +++++++++++++++++- .../test_gdbstub_host/rv_decode/xesppie.S | 369 +++++++++++++++++ .../gdbstub_runtime/main/CMakeLists.txt | 7 +- .../gdbstub_runtime/main/test_app_main.c | 8 +- .../gdbstub_runtime/main/xesppie_loops.S | 50 +++ ...t_runtime.py => pytest_gdbstub_runtime.py} | 155 +++---- 7 files changed, 920 insertions(+), 71 deletions(-) create mode 100644 components/esp_gdbstub/test_gdbstub_host/rv_decode/xesppie.S create mode 100644 tools/test_apps/system/gdbstub_runtime/main/xesppie_loops.S rename tools/test_apps/system/gdbstub_runtime/{pytest_runtime.py => pytest_gdbstub_runtime.py} (64%) diff --git a/components/esp_gdbstub/src/port/riscv/rv_decode.c b/components/esp_gdbstub/src/port/riscv/rv_decode.c index b5556210864..defe48aa460 100644 --- a/components/esp_gdbstub/src/port/riscv/rv_decode.c +++ b/components/esp_gdbstub/src/port/riscv/rv_decode.c @@ -1,10 +1,12 @@ /* - * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2023-2024 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ #include "rv_decode.h" +#include "riscv/csr_hwlp.h" +#include "soc/soc_caps.h" static inline uint32_t rv_inst_len(uint32_t inst) { @@ -154,5 +156,26 @@ uintptr_t rv_compute_next_pc(esp_gdbstub_frame_t *frame, uintptr_t inst_addr) } } #endif /* __riscv_c */ +#if SOC_CPU_HAS_HWLOOP + /* This block of code could be done with a loop, but the RV_READ_CSR macro + * is not designed to pass values as variables. + */ + /* Check if LOOP0 is executing */ + const uintptr_t loop0_end_addr = RV_READ_CSR(CSR_LOOP0_END_ADDR); + if (loop0_end_addr == inst_addr) { + const uint32_t loop0_count = RV_READ_CSR(CSR_LOOP0_COUNT); + if (loop0_count > 1) { + return RV_READ_CSR(CSR_LOOP0_START_ADDR); + } + } + /* Check if LOOP1 is executing */ + const uintptr_t loop1_end_addr = RV_READ_CSR(CSR_LOOP1_END_ADDR); + if (loop1_end_addr == inst_addr) { + const uint32_t loop1_count = RV_READ_CSR(CSR_LOOP1_COUNT); + if (loop1_count > 1) { + return RV_READ_CSR(CSR_LOOP1_START_ADDR); + } + } +#endif // SOC_CPU_HAS_HWLOOP return inst_addr + inst_len; } diff --git a/components/esp_gdbstub/test_gdbstub_host/rv_decode/test_rv_decode.cpp b/components/esp_gdbstub/test_gdbstub_host/rv_decode/test_rv_decode.cpp index 1f624eac4de..50c9ccc3860 100644 --- a/components/esp_gdbstub/test_gdbstub_host/rv_decode/test_rv_decode.cpp +++ b/components/esp_gdbstub/test_gdbstub_host/rv_decode/test_rv_decode.cpp @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2023-2024 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -103,6 +103,368 @@ struct inst_list_s rv32c_nojump[] = { {0x9459, "c.srai"}, {0x8481, "c.srai64"}}; +struct inst_list_s xesppie_nojump[] = { + {0x0287805f, "esp.vcmulas.s16.qacc.h"}, + {0x03c0633b, "esp.vcmulas.s16.qacc.h.ld.ip"}, + {0x0300207f, "esp.vcmulas.s16.qacc.h.ld.xp"}, + {0x0283805f, "esp.vcmulas.s16.qacc.l"}, + {0x01c0633b, "esp.vcmulas.s16.qacc.l.ld.ip"}, + {0x0100207f, "esp.vcmulas.s16.qacc.l.ld.xp"}, + {0x0285805f, "esp.vcmulas.s8.qacc.h"}, + {0x02c0633b, "esp.vcmulas.s8.qacc.h.ld.ip"}, + {0x0200207f, "esp.vcmulas.s8.qacc.h.ld.xp"}, + {0x0281805f, "esp.vcmulas.s8.qacc.l"}, + {0x00c0633b, "esp.vcmulas.s8.qacc.l.ld.ip"}, + {0x0000207f, "esp.vcmulas.s8.qacc.l.ld.xp"}, + {0x02c7005f, "esp.vmulas.s16.qacc"}, + {0x02e060bb, "esp.vmulas.s16.qacc.ld.ip"}, + {0x020822ff, "esp.vmulas.s16.qacc.ld.xp"}, + {0x03e060bb, "esp.vmulas.s16.qacc.st.ip"}, + {0x030822ff, "esp.vmulas.s16.qacc.st.xp"}, + {0x02c3005f, "esp.vmulas.s16.xacc"}, + {0x00e060bb, "esp.vmulas.s16.xacc.ld.ip"}, + {0x000822ff, "esp.vmulas.s16.xacc.ld.xp"}, + {0x01e060bb, "esp.vmulas.s16.xacc.st.ip"}, + {0x010822ff, "esp.vmulas.s16.xacc.st.xp"}, + {0x02c5005f, "esp.vmulas.s8.qacc"}, + {0x026060bb, "esp.vmulas.s8.qacc.ld.ip"}, + {0x020022ff, "esp.vmulas.s8.qacc.ld.xp"}, + {0x036060bb, "esp.vmulas.s8.qacc.st.ip"}, + {0x030022ff, "esp.vmulas.s8.qacc.st.xp"}, + {0x02c1005f, "esp.vmulas.s8.xacc"}, + {0x006060bb, "esp.vmulas.s8.xacc.ld.ip"}, + {0x000022ff, "esp.vmulas.s8.xacc.ld.xp"}, + {0x016060bb, "esp.vmulas.s8.xacc.st.ip"}, + {0x010022ff, "esp.vmulas.s8.xacc.st.xp"}, + {0x02c6005f, "esp.vmulas.u16.qacc"}, + {0x02a060bb, "esp.vmulas.u16.qacc.ld.ip"}, + {0x020820ff, "esp.vmulas.u16.qacc.ld.xp"}, + {0x03a060bb, "esp.vmulas.u16.qacc.st.ip"}, + {0x030820ff, "esp.vmulas.u16.qacc.st.xp"}, + {0x02c2005f, "esp.vmulas.u16.xacc"}, + {0x00a060bb, "esp.vmulas.u16.xacc.ld.ip"}, + {0x000820ff, "esp.vmulas.u16.xacc.ld.xp"}, + {0x01a060bb, "esp.vmulas.u16.xacc.st.ip"}, + {0x010820ff, "esp.vmulas.u16.xacc.st.xp"}, + {0x02c4005f, "esp.vmulas.u8.qacc"}, + {0x022060bb, "esp.vmulas.u8.qacc.ld.ip"}, + {0x020020ff, "esp.vmulas.u8.qacc.ld.xp"}, + {0x032060bb, "esp.vmulas.u8.qacc.st.ip"}, + {0x030020ff, "esp.vmulas.u8.qacc.st.xp"}, + {0x02c0005f, "esp.vmulas.u8.xacc"}, + {0x002060bb, "esp.vmulas.u8.xacc.ld.ip"}, + {0x000020ff, "esp.vmulas.u8.xacc.ld.xp"}, + {0x012060bb, "esp.vmulas.u8.xacc.st.ip"}, + {0x010020ff, "esp.vmulas.u8.xacc.st.xp"}, + {0x006061bb, "esp.vmulas.s16.qacc.ldbc.incp"}, + {0x002061bb, "esp.vmulas.s8.qacc.ldbc.incp"}, + {0x004061bb, "esp.vmulas.u16.qacc.ldbc.incp"}, + {0x000061bb, "esp.vmulas.u8.qacc.ldbc.incp"}, + {0x02f0005f, "esp.vsmulas.s16.qacc"}, + {0x038063bb, "esp.vsmulas.s16.qacc.ld.incp"}, + {0x02b0005f, "esp.vsmulas.s8.qacc"}, + {0x018063bb, "esp.vsmulas.s8.qacc.ld.incp"}, + {0x02d0005f, "esp.vsmulas.u16.qacc"}, + {0x028063bb, "esp.vsmulas.u16.qacc.ld.incp"}, + {0x0290005f, "esp.vsmulas.u8.qacc"}, + {0x008063bb, "esp.vsmulas.u8.qacc.ld.incp"}, + {0x0006245f, "esp.cmul.s16"}, + {0x00c0403f, "esp.cmul.s16.ld.incp"}, + {0x02c0403f, "esp.cmul.s16.st.incp"}, + {0x0002245f, "esp.cmul.s8"}, + {0x0040403f, "esp.cmul.s8.ld.incp"}, + {0x0240403f, "esp.cmul.s8.st.incp"}, + {0x0004245f, "esp.cmul.u16"}, + {0x0080403f, "esp.cmul.u16.ld.incp"}, + {0x0280403f, "esp.cmul.u16.st.incp"}, + {0x0000245f, "esp.cmul.u8"}, + {0x0000403f, "esp.cmul.u8.ld.incp"}, + {0x0200403f, "esp.cmul.u8.st.incp"}, + {0x90c0505b, "esp.max.s16.a"}, + {0x90a0505b, "esp.max.s32.a"}, + {0x9040505b, "esp.max.s8.a"}, + {0x9080505b, "esp.max.u16.a"}, + {0x9020505b, "esp.max.u32.a"}, + {0x9000505b, "esp.max.u8.a"}, + {0x90d0505b, "esp.min.s16.a"}, + {0x90b0505b, "esp.min.s32.a"}, + {0x9050505b, "esp.min.s8.a"}, + {0x9090505b, "esp.min.u16.a"}, + {0x9030505b, "esp.min.u32.a"}, + {0x9010505b, "esp.min.u8.a"}, + {0x8000105b, "esp.vabs.16"}, + {0x8000085b, "esp.vabs.32"}, + {0x8000005b, "esp.vabs.8"}, + {0x0284065f, "esp.vadd.s16"}, + {0x0108603b, "esp.vadd.s16.ld.incp"}, + {0x0308603b, "esp.vadd.s16.st.incp"}, + {0x0284055f, "esp.vadd.s32"}, + {0x0100613b, "esp.vadd.s32.ld.incp"}, + {0x0300613b, "esp.vadd.s32.st.incp"}, + {0x0280065f, "esp.vadd.s8"}, + {0x0008603b, "esp.vadd.s8.ld.incp"}, + {0x0208603b, "esp.vadd.s8.st.incp"}, + {0x0284045f, "esp.vadd.u16"}, + {0x0100603b, "esp.vadd.u16.ld.incp"}, + {0x0300603b, "esp.vadd.u16.st.incp"}, + {0x0280055f, "esp.vadd.u32"}, + {0x0000613b, "esp.vadd.u32.ld.incp"}, + {0x0200613b, "esp.vadd.u32.st.incp"}, + {0x0280045f, "esp.vadd.u8"}, + {0x0000603b, "esp.vadd.u8.ld.incp"}, + {0x0200603b, "esp.vadd.u8.st.incp"}, + {0x0000505b, "esp.vclamp.s16"}, + {0x0006ac5f, "esp.vmax.s16"}, + {0x0068403f, "esp.vmax.s16.ld.incp"}, + {0x00e8403f, "esp.vmax.s16.st.incp"}, + {0x0005ac5f, "esp.vmax.s32"}, + {0x0058403f, "esp.vmax.s32.ld.incp"}, + {0x00d8403f, "esp.vmax.s32.st.incp"}, + {0x0002ac5f, "esp.vmax.s8"}, + {0x0028403f, "esp.vmax.s8.ld.incp"}, + {0x00a8403f, "esp.vmax.s8.st.incp"}, + {0x0004ac5f, "esp.vmax.u16"}, + {0x0048403f, "esp.vmax.u16.ld.incp"}, + {0x00c8403f, "esp.vmax.u16.st.incp"}, + {0x0001ac5f, "esp.vmax.u32"}, + {0x0018403f, "esp.vmax.u32.ld.incp"}, + {0x0098403f, "esp.vmax.u32.st.incp"}, + {0x0000ac5f, "esp.vmax.u8"}, + {0x0008403f, "esp.vmax.u8.ld.incp"}, + {0x0088403f, "esp.vmax.u8.st.incp"}, + {0x00063c5f, "esp.vmin.s16"}, + {0x0168403f, "esp.vmin.s16.ld.incp"}, + {0x01e8403f, "esp.vmin.s16.st.incp"}, + {0x00053c5f, "esp.vmin.s32"}, + {0x0158403f, "esp.vmin.s32.ld.incp"}, + {0x01d8403f, "esp.vmin.s32.st.incp"}, + {0x00023c5f, "esp.vmin.s8"}, + {0x0128403f, "esp.vmin.s8.ld.incp"}, + {0x01a8403f, "esp.vmin.s8.st.incp"}, + {0x00043c5f, "esp.vmin.u16"}, + {0x0148403f, "esp.vmin.u16.ld.incp"}, + {0x01c8403f, "esp.vmin.u16.st.incp"}, + {0x00013c5f, "esp.vmin.u32"}, + {0x0118403f, "esp.vmin.u32.ld.incp"}, + {0x0198403f, "esp.vmin.u32.st.incp"}, + {0x00003c5f, "esp.vmin.u8"}, + {0x0108403f, "esp.vmin.u8.ld.incp"}, + {0x0188403f, "esp.vmin.u8.st.incp"}, + {0x0006bc5f, "esp.vmul.s16"}, + {0x0368403f, "esp.vmul.s16.ld.incp"}, + {0x0283045f, "esp.vmul.s16.s8xs8"}, + {0x03e8403f, "esp.vmul.s16.st.incp"}, + {0x0287045f, "esp.vmul.s32.s16xs16"}, + {0x0002bc5f, "esp.vmul.s8"}, + {0x0328403f, "esp.vmul.s8.ld.incp"}, + {0x03a8403f, "esp.vmul.s8.st.incp"}, + {0x0004bc5f, "esp.vmul.u16"}, + {0x0348403f, "esp.vmul.u16.ld.incp"}, + {0x03c8403f, "esp.vmul.u16.st.incp"}, + {0x0000bc5f, "esp.vmul.u8"}, + {0x0308403f, "esp.vmul.u8.ld.incp"}, + {0x0388403f, "esp.vmul.u8.st.incp"}, + {0x02a0605f, "esp.vprelu.s16"}, + {0x0220605f, "esp.vprelu.s8"}, + {0x82005c5b, "esp.vrelu.s16"}, + {0x8200585b, "esp.vrelu.s8"}, + {0x1a80025f, "esp.vsadds.s16"}, + {0x0a80025f, "esp.vsadds.s8"}, + {0x1280025f, "esp.vsadds.u16"}, + {0x0280025f, "esp.vsadds.u8"}, + {0x1800583b, "esp.vsat.s16"}, + {0x1800543b, "esp.vsat.s32"}, + {0x1800483b, "esp.vsat.s8"}, + {0x1800503b, "esp.vsat.u16"}, + {0x1800443b, "esp.vsat.u32"}, + {0x1800403b, "esp.vsat.u8"}, + {0x1e80025f, "esp.vssubs.s16"}, + {0x0e80025f, "esp.vssubs.s8"}, + {0x1680025f, "esp.vssubs.u16"}, + {0x0680025f, "esp.vssubs.u8"}, + {0x028406df, "esp.vsub.s16"}, + {0x0188613b, "esp.vsub.s16.ld.incp"}, + {0x0388613b, "esp.vsub.s16.st.incp"}, + {0x028405df, "esp.vsub.s32"}, + {0x0100633b, "esp.vsub.s32.ld.incp"}, + {0x0300633b, "esp.vsub.s32.st.incp"}, + {0x028006df, "esp.vsub.s8"}, + {0x0088613b, "esp.vsub.s8.ld.incp"}, + {0x0288613b, "esp.vsub.s8.st.incp"}, + {0x028404df, "esp.vsub.u16"}, + {0x0180613b, "esp.vsub.u16.ld.incp"}, + {0x0380613b, "esp.vsub.u16.st.incp"}, + {0x028005df, "esp.vsub.u32"}, + {0x0000633b, "esp.vsub.u32.ld.incp"}, + {0x0200633b, "esp.vsub.u32.st.incp"}, + {0x028004df, "esp.vsub.u8"}, + {0x0080613b, "esp.vsub.u8.ld.incp"}, + {0x0280613b, "esp.vsub.u8.st.incp"}, + {0x04840433, "esp.addx2"}, + {0x08840433, "esp.addx4"}, + {0x40842433, "esp.sat"}, + {0x44840433, "esp.subx2"}, + {0x48840433, "esp.subx4"}, + {0x0004205f, "esp.andq"}, + {0x0006205f, "esp.notq"}, + {0x0000205f, "esp.orq"}, + {0x0002205f, "esp.xorq"}, + {0x0001b45f, "esp.vcmp.eq.s16"}, + {0x00012c5f, "esp.vcmp.eq.s32"}, + {0x0000b45f, "esp.vcmp.eq.s8"}, + {0x0001345f, "esp.vcmp.eq.u16"}, + {0x00002c5f, "esp.vcmp.eq.u32"}, + {0x0000345f, "esp.vcmp.eq.u8"}, + {0x0005b45f, "esp.vcmp.gt.s16"}, + {0x00052c5f, "esp.vcmp.gt.s32"}, + {0x0004b45f, "esp.vcmp.gt.s8"}, + {0x0005345f, "esp.vcmp.gt.u16"}, + {0x00042c5f, "esp.vcmp.gt.u32"}, + {0x0004345f, "esp.vcmp.gt.u8"}, + {0x0003b45f, "esp.vcmp.lt.s16"}, + {0x00032c5f, "esp.vcmp.lt.s32"}, + {0x0002b45f, "esp.vcmp.lt.s8"}, + {0x0003345f, "esp.vcmp.lt.u16"}, + {0x00022c5f, "esp.vcmp.lt.u32"}, + {0x0002345f, "esp.vcmp.lt.u8"}, + {0x1060005b, "esp.mov.s16.qacc"}, + {0x1020005b, "esp.mov.s8.qacc"}, + {0x1040005b, "esp.mov.u16.qacc"}, + {0x1000005b, "esp.mov.u8.qacc"}, + {0x00c0005f, "esp.movi.16.a"}, + {0x80e0005f, "esp.movi.16.q"}, + {0x8080005f, "esp.movi.32.a"}, + {0x8090005f, "esp.movi.32.q"}, + {0x0080005f, "esp.movi.8.a"}, + {0x80a0005f, "esp.movi.8.q"}, + {0x80d0005f, "esp.movx.r.cfg"}, + {0x84d0005f, "esp.movx.r.fft.bit.width"}, + {0x8cd0005f, "esp.movx.r.perf"}, + {0x80b0005f, "esp.movx.r.sar"}, + {0x88b0005f, "esp.movx.r.sar.bytes"}, + {0x8cb0005f, "esp.movx.r.xacc.h"}, + {0x84b0005f, "esp.movx.r.xacc.l"}, + {0x90d0005f, "esp.movx.w.cfg"}, + {0x94d0005f, "esp.movx.w.fft.bit.width"}, + {0x9cd0005f, "esp.movx.w.perf"}, + {0x90b0005f, "esp.movx.w.sar"}, + {0x98b0005f, "esp.movx.w.sar.bytes"}, + {0x9cb0005f, "esp.movx.w.xacc.h"}, + {0x94b0005f, "esp.movx.w.xacc.l"}, + {0x1800585b, "esp.vext.s16"}, + {0x0800585b, "esp.vext.s8"}, + {0x1000585b, "esp.vext.u16"}, + {0x0000585b, "esp.vext.u8"}, + {0x0286005f, "esp.vunzip.16"}, + {0x0284805f, "esp.vunzip.32"}, + {0x0284005f, "esp.vunzip.8"}, + {0x00c04c5b, "esp.vunzipt.16"}, + {0x00804c5b, "esp.vunzipt.8"}, + {0x0282005f, "esp.vzip.16"}, + {0x0280805f, "esp.vzip.32"}, + {0x0280005f, "esp.vzip.8"}, + {0x00404c5b, "esp.vzipt.16"}, + {0x00004c5b, "esp.vzipt.8"}, + {0x0040005b, "esp.zero.q"}, + {0x0000025b, "esp.zero.qacc"}, + {0x0000005b, "esp.zero.xacc"}, + {0x0000007b, "esp.fft.ams.s16.ld.incp"}, + {0x0000207b, "esp.fft.ams.s16.ld.incp.uaup"}, + {0x0000607b, "esp.fft.ams.s16.ld.r32.decp"}, + {0x0000203f, "esp.fft.ams.s16.st.incp"}, + {0x1000025b, "esp.fft.bitrev"}, + {0x0000003f, "esp.fft.cmul.s16.ld.xp"}, + {0x0000007f, "esp.fft.cmul.s16.st.xp"}, + {0x0281045f, "esp.fft.r2bf.s16"}, + {0x0200605f, "esp.fft.r2bf.s16.st.incp"}, + {0x0000203b, "esp.fft.vst.r32.decp"}, + {0x8800203b, "esp.ld.128.usar.ip"}, + {0x8000405f, "esp.ld.128.usar.xp"}, + {0xa000433b, "esp.ld.xacc.ip"}, + {0xe08040bb, "esp.ldqa.s16.128.ip"}, + {0x1300535b, "esp.ldqa.s16.128.xp"}, + {0x608040bb, "esp.ldqa.s8.128.ip"}, + {0x1300515b, "esp.ldqa.s8.128.xp"}, + {0xa08040bb, "esp.ldqa.u16.128.ip"}, + {0x1300525b, "esp.ldqa.u16.128.xp"}, + {0x208040bb, "esp.ldqa.u8.128.ip"}, + {0x1300505b, "esp.ldqa.u8.128.xp"}, + {0xc600203b, "esp.vldbc.16.ip"}, + {0x9600405f, "esp.vldbc.16.xp"}, + {0x8e00203b, "esp.vldbc.32.ip"}, + {0x8e00405f, "esp.vldbc.32.xp"}, + {0x4600203b, "esp.vldbc.8.ip"}, + {0x8600405f, "esp.vldbc.8.xp"}, + {0xc880403b, "esp.vldext.s16.ip"}, + {0xf000605f, "esp.vldext.s16.xp"}, + {0x4880403b, "esp.vldext.s8.ip"}, + {0x7000605f, "esp.vldext.s8.xp"}, + {0x8880403b, "esp.vldext.u16.ip"}, + {0xb000605f, "esp.vldext.u16.xp"}, + {0x0880403b, "esp.vldext.u8.ip"}, + {0x3000605f, "esp.vldext.u8.xp"}, + {0x2800403b, "esp.vldhbc.16.incp"}, + {0x4080403b, "esp.ld.qacc.h.h.128.ip"}, + {0x6080403b, "esp.ld.qacc.h.l.128.ip"}, + {0x0080403b, "esp.ld.qacc.l.h.128.ip"}, + {0x2080403b, "esp.ld.qacc.l.l.128.ip"}, + {0x6000413b, "esp.ld.ua.state.ip"}, + {0x0080205f, "esp.ldxq.32"}, + {0xc080403b, "esp.st.qacc.h.h.128.ip"}, + {0xe080403b, "esp.st.qacc.h.l.128.ip"}, + {0x8080403b, "esp.st.qacc.l.h.128.ip"}, + {0xa080403b, "esp.st.qacc.l.l.128.ip"}, + {0xe000413b, "esp.st.ua.state.ip"}, + {0x8080205f, "esp.stxq.32"}, + {0x4200203b, "esp.vld.128.ip"}, + {0x8200405f, "esp.vld.128.xp"}, + {0x6400203b, "esp.vld.h.64.ip"}, + {0x8c00405f, "esp.vld.h.64.xp"}, + {0x2400203b, "esp.vld.l.64.ip"}, + {0x8400405f, "esp.vld.l.64.xp"}, + {0xc200203b, "esp.vst.128.ip"}, + {0x9200405f, "esp.vst.128.xp"}, + {0xe400203b, "esp.vst.h.64.ip"}, + {0x9c00405f, "esp.vst.h.64.xp"}, + {0xa400203b, "esp.vst.l.64.ip"}, + {0x9400405f, "esp.vst.l.64.xp"}, + {0x0000485b, "esp.slci.2q"}, + {0x0000405f, "esp.slcxxp.2q"}, + {0x8024005b, "esp.src.q"}, + {0x8000213b, "esp.src.q.ld.ip"}, + {0x0000003b, "esp.src.q.ld.xp"}, + {0x8024105b, "esp.src.q.qup"}, + {0x0080485b, "esp.srci.2q"}, + {0x9864005b, "esp.srcmb.s16.q.qacc"}, + {0xd800203b, "esp.srcmb.s16.qacc"}, + {0x8864005b, "esp.srcmb.s8.q.qacc"}, + {0x5800203b, "esp.srcmb.s8.qacc"}, + {0x9064005b, "esp.srcmb.u16.q.qacc"}, + {0x9800203b, "esp.srcmb.u16.qacc"}, + {0x8064005b, "esp.srcmb.u8.q.qacc"}, + {0x1800203b, "esp.srcmb.u8.qacc"}, + {0x0000405b, "esp.srcq.128.st.incp"}, + {0x0000445f, "esp.srcxxp.2q"}, + {0x94f0005f, "esp.srs.s.xacc"}, + {0x84f0005f, "esp.srs.u.xacc"}, + {0x8004005b, "esp.vsl.32"}, + {0x0020005f, "esp.vsld.16"}, + {0x0010005f, "esp.vsld.32"}, + {0x0000005f, "esp.vsld.8"}, + {0x8004035b, "esp.vsr.s32"}, + {0x8004015b, "esp.vsr.u32"}, + {0x0060005f, "esp.vsrd.16"}, + {0x0050005f, "esp.vsrd.32"}, + {0x0040005f, "esp.vsrd.8"}, + {0xe00041bb, "esp.st.s.xacc.ip"}, + {0x600041bb, "esp.st.u.xacc.ip"}, + {0x0000502b, "esp.lp.setupi"}, + {0x0004402b, "esp.lp.setup"}, + {0x0000002b, "esp.lp.starti"}, + {0x0000102b, "esp.lp.endi"}, + {0x0000302b, "esp.lp.counti"}, + {0x0004202b, "esp.lp.count"}}; + TEST_CASE("decode rv32i instructions") { @@ -336,3 +698,16 @@ TEST_CASE("decode rv32m instructions") CHECK(rv_compute_next_pc(temp_regs_frame, inst_addr) == inst_addr + 4); } } + +TEST_CASE("decode xesppie instructions") +{ + uintptr_t pc; + uint32_t inst; + uintptr_t inst_addr = (uintptr_t)&inst; + + for (size_t i = 0; i < sizeof(xesppie_nojump)/sizeof(xesppie_nojump[0]); i++) { + inst = xesppie_nojump[i].inst; + DEBUG_PRINTF("testing instruction %s\n", xesppie_nojump[i].name); + CHECK(rv_compute_next_pc(temp_regs_frame, inst_addr) == inst_addr + 4); + } +} diff --git a/components/esp_gdbstub/test_gdbstub_host/rv_decode/xesppie.S b/components/esp_gdbstub/test_gdbstub_host/rv_decode/xesppie.S new file mode 100644 index 00000000000..8f662369d43 --- /dev/null +++ b/components/esp_gdbstub/test_gdbstub_host/rv_decode/xesppie.S @@ -0,0 +1,369 @@ +/* + * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +// This file is used to generate "xesppie_nojump" array. +// It's manually passed to gcc + objdump: +// riscv32-esp-elf-gcc -march=rv32ixesppie -c rv_decode/xesppie.S +// riscv32-esp-elf-objdump -D -j .text xesppie.o | tail -n +8 | sed -E 's/^\s+[0-9a-f]+:\s+([0-9a-f]+)\s+([a-zA-Z0-9_.]+).*/{0x\1, "\2"},/' +esp.vcmulas.s16.qacc.h q0,q0 +esp.vcmulas.s16.qacc.h.ld.ip q0,x8,-128,q0,q0 +esp.vcmulas.s16.qacc.h.ld.xp q0,x8,x8,q0,q0 +esp.vcmulas.s16.qacc.l q0,q0 +esp.vcmulas.s16.qacc.l.ld.ip q0,x8,-128,q0,q0 +esp.vcmulas.s16.qacc.l.ld.xp q0,x8,x8,q0,q0 +esp.vcmulas.s8.qacc.h q0,q0 +esp.vcmulas.s8.qacc.h.ld.ip q0,x8,-128,q0,q0 +esp.vcmulas.s8.qacc.h.ld.xp q0,x8,x8,q0,q0 +esp.vcmulas.s8.qacc.l q0,q0 +esp.vcmulas.s8.qacc.l.ld.ip q0,x8,-128,q0,q0 +esp.vcmulas.s8.qacc.l.ld.xp q0,x8,x8,q0,q0 +esp.vmulas.s16.qacc q0,q0 +esp.vmulas.s16.qacc.ld.ip q0,x8,-128,q0,q0 +esp.vmulas.s16.qacc.ld.xp q0,x8,x8,q0,q0 +esp.vmulas.s16.qacc.st.ip q0,x8,-128,q0,q0 +esp.vmulas.s16.qacc.st.xp q0,x8,x8,q0,q0 +esp.vmulas.s16.xacc q0,q0 +esp.vmulas.s16.xacc.ld.ip q0,x8,-128,q0,q0 +esp.vmulas.s16.xacc.ld.xp q0,x8,x8,q0,q0 +esp.vmulas.s16.xacc.st.ip q0,x8,-128,q0,q0 +esp.vmulas.s16.xacc.st.xp q0,x8,x8,q0,q0 +esp.vmulas.s8.qacc q0,q0 +esp.vmulas.s8.qacc.ld.ip q0,x8,-128,q0,q0 +esp.vmulas.s8.qacc.ld.xp q0,x8,x8,q0,q0 +esp.vmulas.s8.qacc.st.ip q0,x8,-128,q0,q0 +esp.vmulas.s8.qacc.st.xp q0,x8,x8,q0,q0 +esp.vmulas.s8.xacc q0,q0 +esp.vmulas.s8.xacc.ld.ip q0,x8,-128,q0,q0 +esp.vmulas.s8.xacc.ld.xp q0,x8,x8,q0,q0 +esp.vmulas.s8.xacc.st.ip q0,x8,-128,q0,q0 +esp.vmulas.s8.xacc.st.xp q0,x8,x8,q0,q0 +esp.vmulas.u16.qacc q0,q0 +esp.vmulas.u16.qacc.ld.ip q0,x8,-128,q0,q0 +esp.vmulas.u16.qacc.ld.xp q0,x8,x8,q0,q0 +esp.vmulas.u16.qacc.st.ip q0,x8,-128,q0,q0 +esp.vmulas.u16.qacc.st.xp q0,x8,x8,q0,q0 +esp.vmulas.u16.xacc q0,q0 +esp.vmulas.u16.xacc.ld.ip q0,x8,-128,q0,q0 +esp.vmulas.u16.xacc.ld.xp q0,x8,x8,q0,q0 +esp.vmulas.u16.xacc.st.ip q0,x8,-128,q0,q0 +esp.vmulas.u16.xacc.st.xp q0,x8,x8,q0,q0 +esp.vmulas.u8.qacc q0,q0 +esp.vmulas.u8.qacc.ld.ip q0,x8,-128,q0,q0 +esp.vmulas.u8.qacc.ld.xp q0,x8,x8,q0,q0 +esp.vmulas.u8.qacc.st.ip q0,x8,-128,q0,q0 +esp.vmulas.u8.qacc.st.xp q0,x8,x8,q0,q0 +esp.vmulas.u8.xacc q0,q0 +esp.vmulas.u8.xacc.ld.ip q0,x8,-128,q0,q0 +esp.vmulas.u8.xacc.ld.xp q0,x8,x8,q0,q0 +esp.vmulas.u8.xacc.st.ip q0,x8,-128,q0,q0 +esp.vmulas.u8.xacc.st.xp q0,x8,x8,q0,q0 +esp.vmulas.s16.qacc.ldbc.incp q0,x8,q0,q0 +esp.vmulas.s8.qacc.ldbc.incp q0,x8,q0,q0 +esp.vmulas.u16.qacc.ldbc.incp q0,x8,q0,q0 +esp.vmulas.u8.qacc.ldbc.incp q0,x8,q0,q0 +esp.vsmulas.s16.qacc q0,q0,0 +esp.vsmulas.s16.qacc.ld.incp q0,x8,q0,q0,0 +esp.vsmulas.s8.qacc q0,q0,0 +esp.vsmulas.s8.qacc.ld.incp q0,x8,q0,q0,0 +esp.vsmulas.u16.qacc q0,q0,0 +esp.vsmulas.u16.qacc.ld.incp q0,x8,q0,q0,0 +esp.vsmulas.u8.qacc q0,q0,0 +esp.vsmulas.u8.qacc.ld.incp q0,x8,q0,q0,0 +esp.cmul.s16 q0,q0,q0,0 +esp.cmul.s16.ld.incp q0,x8,q0,q0,q0,0 +esp.cmul.s16.st.incp q0,x8,q0,q0,q0,0 +esp.cmul.s8 q0,q0,q0,0 +esp.cmul.s8.ld.incp q0,x8,q0,q0,q0,0 +esp.cmul.s8.st.incp q0,x8,q0,q0,q0,0 +esp.cmul.u16 q0,q0,q0,0 +esp.cmul.u16.ld.incp q0,x8,q0,q0,q0,0 +esp.cmul.u16.st.incp q0,x8,q0,q0,q0,0 +esp.cmul.u8 q0,q0,q0,0 +esp.cmul.u8.ld.incp q0,x8,q0,q0,q0,0 +esp.cmul.u8.st.incp q0,x8,q0,q0,q0,0 +esp.max.s16.a q0,x8 +esp.max.s32.a q0,x8 +esp.max.s8.a q0,x8 +esp.max.u16.a q0,x8 +esp.max.u32.a q0,x8 +esp.max.u8.a q0,x8 +esp.min.s16.a q0,x8 +esp.min.s32.a q0,x8 +esp.min.s8.a q0,x8 +esp.min.u16.a q0,x8 +esp.min.u32.a q0,x8 +esp.min.u8.a q0,x8 +esp.vabs.16 q0,q0 +esp.vabs.32 q0,q0 +esp.vabs.8 q0,q0 +esp.vadd.s16 q0,q0,q0 +esp.vadd.s16.ld.incp q0,x8,q0,q0,q0 +esp.vadd.s16.st.incp q0,x8,q0,q0,q0 +esp.vadd.s32 q0,q0,q0 +esp.vadd.s32.ld.incp q0,x8,q0,q0,q0 +esp.vadd.s32.st.incp q0,x8,q0,q0,q0 +esp.vadd.s8 q0,q0,q0 +esp.vadd.s8.ld.incp q0,x8,q0,q0,q0 +esp.vadd.s8.st.incp q0,x8,q0,q0,q0 +esp.vadd.u16 q0,q0,q0 +esp.vadd.u16.ld.incp q0,x8,q0,q0,q0 +esp.vadd.u16.st.incp q0,x8,q0,q0,q0 +esp.vadd.u32 q0,q0,q0 +esp.vadd.u32.ld.incp q0,x8,q0,q0,q0 +esp.vadd.u32.st.incp q0,x8,q0,q0,q0 +esp.vadd.u8 q0,q0,q0 +esp.vadd.u8.ld.incp q0,x8,q0,q0,q0 +esp.vadd.u8.st.incp q0,x8,q0,q0,q0 +esp.vclamp.s16 q0,q0,0 +esp.vmax.s16 q0,q0,q0 +esp.vmax.s16.ld.incp q0,x8,q0,q0,q0 +esp.vmax.s16.st.incp q0,x8,q0,q0,q0 +esp.vmax.s32 q0,q0,q0 +esp.vmax.s32.ld.incp q0,x8,q0,q0,q0 +esp.vmax.s32.st.incp q0,x8,q0,q0,q0 +esp.vmax.s8 q0,q0,q0 +esp.vmax.s8.ld.incp q0,x8,q0,q0,q0 +esp.vmax.s8.st.incp q0,x8,q0,q0,q0 +esp.vmax.u16 q0,q0,q0 +esp.vmax.u16.ld.incp q0,x8,q0,q0,q0 +esp.vmax.u16.st.incp q0,x8,q0,q0,q0 +esp.vmax.u32 q0,q0,q0 +esp.vmax.u32.ld.incp q0,x8,q0,q0,q0 +esp.vmax.u32.st.incp q0,x8,q0,q0,q0 +esp.vmax.u8 q0,q0,q0 +esp.vmax.u8.ld.incp q0,x8,q0,q0,q0 +esp.vmax.u8.st.incp q0,x8,q0,q0,q0 +esp.vmin.s16 q0,q0,q0 +esp.vmin.s16.ld.incp q0,x8,q0,q0,q0 +esp.vmin.s16.st.incp q0,x8,q0,q0,q0 +esp.vmin.s32 q0,q0,q0 +esp.vmin.s32.ld.incp q0,x8,q0,q0,q0 +esp.vmin.s32.st.incp q0,x8,q0,q0,q0 +esp.vmin.s8 q0,q0,q0 +esp.vmin.s8.ld.incp q0,x8,q0,q0,q0 +esp.vmin.s8.st.incp q0,x8,q0,q0,q0 +esp.vmin.u16 q0,q0,q0 +esp.vmin.u16.ld.incp q0,x8,q0,q0,q0 +esp.vmin.u16.st.incp q0,x8,q0,q0,q0 +esp.vmin.u32 q0,q0,q0 +esp.vmin.u32.ld.incp q0,x8,q0,q0,q0 +esp.vmin.u32.st.incp q0,x8,q0,q0,q0 +esp.vmin.u8 q0,q0,q0 +esp.vmin.u8.ld.incp q0,x8,q0,q0,q0 +esp.vmin.u8.st.incp q0,x8,q0,q0,q0 +esp.vmul.s16 q0,q0,q0 +esp.vmul.s16.ld.incp q0,x8,q0,q0,q0 +esp.vmul.s16.s8xs8 q0,q0,q0,q0 +esp.vmul.s16.st.incp q0,x8,q0,q0,q0 +esp.vmul.s32.s16xs16 q0,q0,q0,q0 +esp.vmul.s8 q0,q0,q0 +esp.vmul.s8.ld.incp q0,x8,q0,q0,q0 +esp.vmul.s8.st.incp q0,x8,q0,q0,q0 +esp.vmul.u16 q0,q0,q0 +esp.vmul.u16.ld.incp q0,x8,q0,q0,q0 +esp.vmul.u16.st.incp q0,x8,q0,q0,q0 +esp.vmul.u8 q0,q0,q0 +esp.vmul.u8.ld.incp q0,x8,q0,q0,q0 +esp.vmul.u8.st.incp q0,x8,q0,q0,q0 +esp.vprelu.s16 q0,q0,q0,x8 +esp.vprelu.s8 q0,q0,q0,x8 +esp.vrelu.s16 q0,x8,x8 +esp.vrelu.s8 q0,x8,x8 +esp.vsadds.s16 q0,q0,x8 +esp.vsadds.s8 q0,q0,x8 +esp.vsadds.u16 q0,q0,x8 +esp.vsadds.u8 q0,q0,x8 +esp.vsat.s16 q0,q0,x8,x8 +esp.vsat.s32 q0,q0,x8,x8 +esp.vsat.s8 q0,q0,x8,x8 +esp.vsat.u16 q0,q0,x8,x8 +esp.vsat.u32 q0,q0,x8,x8 +esp.vsat.u8 q0,q0,x8,x8 +esp.vssubs.s16 q0,q0,x8 +esp.vssubs.s8 q0,q0,x8 +esp.vssubs.u16 q0,q0,x8 +esp.vssubs.u8 q0,q0,x8 +esp.vsub.s16 q0,q0,q0 +esp.vsub.s16.ld.incp q0,x8,q0,q0,q0 +esp.vsub.s16.st.incp q0,x8,q0,q0,q0 +esp.vsub.s32 q0,q0,q0 +esp.vsub.s32.ld.incp q0,x8,q0,q0,q0 +esp.vsub.s32.st.incp q0,x8,q0,q0,q0 +esp.vsub.s8 q0,q0,q0 +esp.vsub.s8.ld.incp q0,x8,q0,q0,q0 +esp.vsub.s8.st.incp q0,x8,q0,q0,q0 +esp.vsub.u16 q0,q0,q0 +esp.vsub.u16.ld.incp q0,x8,q0,q0,q0 +esp.vsub.u16.st.incp q0,x8,q0,q0,q0 +esp.vsub.u32 q0,q0,q0 +esp.vsub.u32.ld.incp q0,x8,q0,q0,q0 +esp.vsub.u32.st.incp q0,x8,q0,q0,q0 +esp.vsub.u8 q0,q0,q0 +esp.vsub.u8.ld.incp q0,x8,q0,q0,q0 +esp.vsub.u8.st.incp q0,x8,q0,q0,q0 +esp.addx2 x8,x8,x8 +esp.addx4 x8,x8,x8 +esp.sat x8,x8,x8 +esp.subx2 x8,x8,x8 +esp.subx4 x8,x8,x8 +esp.andq q0,q0,q0 +esp.notq q0,q0 +esp.orq q0,q0,q0 +esp.xorq q0,q0,q0 +esp.vcmp.eq.s16 q0,q0,q0 +esp.vcmp.eq.s32 q0,q0,q0 +esp.vcmp.eq.s8 q0,q0,q0 +esp.vcmp.eq.u16 q0,q0,q0 +esp.vcmp.eq.u32 q0,q0,q0 +esp.vcmp.eq.u8 q0,q0,q0 +esp.vcmp.gt.s16 q0,q0,q0 +esp.vcmp.gt.s32 q0,q0,q0 +esp.vcmp.gt.s8 q0,q0,q0 +esp.vcmp.gt.u16 q0,q0,q0 +esp.vcmp.gt.u32 q0,q0,q0 +esp.vcmp.gt.u8 q0,q0,q0 +esp.vcmp.lt.s16 q0,q0,q0 +esp.vcmp.lt.s32 q0,q0,q0 +esp.vcmp.lt.s8 q0,q0,q0 +esp.vcmp.lt.u16 q0,q0,q0 +esp.vcmp.lt.u32 q0,q0,q0 +esp.vcmp.lt.u8 q0,q0,q0 +esp.mov.s16.qacc q0 +esp.mov.s8.qacc q0 +esp.mov.u16.qacc q0 +esp.mov.u8.qacc q0 +esp.movi.16.a q0,x8,0 +esp.movi.16.q q0,x8,0 +esp.movi.32.a q0,x8,0 +esp.movi.32.q q0,x8,0 +esp.movi.8.a q0,x8,0 +esp.movi.8.q q0,x8,0 +esp.movx.r.cfg x8 +esp.movx.r.fft.bit.width x8 +esp.movx.r.perf x8,x8 +esp.movx.r.sar x8 +esp.movx.r.sar.bytes x8 +esp.movx.r.xacc.h x8 +esp.movx.r.xacc.l x8 +esp.movx.w.cfg x8 +esp.movx.w.fft.bit.width x8 +esp.movx.w.perf x8 +esp.movx.w.sar x8 +esp.movx.w.sar.bytes x8 +esp.movx.w.xacc.h x8 +esp.movx.w.xacc.l x8 +esp.vext.s16 q0,q0,q0 +esp.vext.s8 q0,q0,q0 +esp.vext.u16 q0,q0,q0 +esp.vext.u8 q0,q0,q0 +esp.vunzip.16 q0,q0 +esp.vunzip.32 q0,q0 +esp.vunzip.8 q0,q0 +esp.vunzipt.16 q0,q0,q0 +esp.vunzipt.8 q0,q0,q0 +esp.vzip.16 q0,q0 +esp.vzip.32 q0,q0 +esp.vzip.8 q0,q0 +esp.vzipt.16 q0,q0,q0 +esp.vzipt.8 q0,q0,q0 +esp.zero.q q0 +esp.zero.qacc +esp.zero.xacc +esp.fft.ams.s16.ld.incp q0,x8,q0,q0,q0,q0,q0,0 +esp.fft.ams.s16.ld.incp.uaup q0,x8,q0,q0,q0,q0,q0,0 +esp.fft.ams.s16.ld.r32.decp q0,x8,q0,q0,q0,q0,q0,0 +esp.fft.ams.s16.st.incp q0,q0,x8,x8,q0,q0,q0,0 +esp.fft.bitrev q0,x8 +esp.fft.cmul.s16.ld.xp q0,x8,x8,q0,q0,q0,0 +esp.fft.cmul.s16.st.xp q0,q0,q0,x8,x8,0,0,0 +esp.fft.r2bf.s16 q0,q0,q0,q0,0 +esp.fft.r2bf.s16.st.incp q0,q0,q0,x8,0 +esp.fft.vst.r32.decp q0,x8,0 +esp.ld.128.usar.ip q0,x8,-2048 +esp.ld.128.usar.xp q0,x8,x8 +esp.ld.xacc.ip x8,-1024 +esp.ldqa.s16.128.ip x8,-2048 +esp.ldqa.s16.128.xp x8,x8 +esp.ldqa.s8.128.ip x8,-2048 +esp.ldqa.s8.128.xp x8,x8 +esp.ldqa.u16.128.ip x8,-2048 +esp.ldqa.u16.128.xp x8,x8 +esp.ldqa.u8.128.ip x8,-2048 +esp.ldqa.u8.128.xp x8,x8 +esp.vldbc.16.ip q0,x8,-512 +esp.vldbc.16.xp q0,x8,x8 +esp.vldbc.32.ip q0,x8,-512 +esp.vldbc.32.xp q0,x8,x8 +esp.vldbc.8.ip q0,x8,-512 +esp.vldbc.8.xp q0,x8,x8 +esp.vldext.s16.ip q0,q0,x8,-128 +esp.vldext.s16.xp q0,q0,x8,x8 +esp.vldext.s8.ip q0,q0,x8,-128 +esp.vldext.s8.xp q0,q0,x8,x8 +esp.vldext.u16.ip q0,q0,x8,-128 +esp.vldext.u16.xp q0,q0,x8,x8 +esp.vldext.u8.ip q0,q0,x8,-128 +esp.vldext.u8.xp q0,q0,x8,x8 +esp.vldhbc.16.incp q0,q0,x8 +esp.ld.qacc.h.h.128.ip x8,-2048 +esp.ld.qacc.h.l.128.ip x8,-2048 +esp.ld.qacc.l.h.128.ip x8,-2048 +esp.ld.qacc.l.l.128.ip x8,-2048 +esp.ld.ua.state.ip x8,-2048 +esp.ldxq.32 q0,q0,x8,0,0 +esp.st.qacc.h.h.128.ip x8,-2048 +esp.st.qacc.h.l.128.ip x8,-2048 +esp.st.qacc.l.h.128.ip x8,-2048 +esp.st.qacc.l.l.128.ip x8,-2048 +esp.st.ua.state.ip x8,-2048 +esp.stxq.32 q0,q0,x8,0,0 +esp.vld.128.ip q0,x8,-2048 +esp.vld.128.xp q0,x8,x8 +esp.vld.h.64.ip q0,x8,-1024 +esp.vld.h.64.xp q0,x8,x8 +esp.vld.l.64.ip q0,x8,-1024 +esp.vld.l.64.xp q0,x8,x8 +esp.vst.128.ip q0,x8,-2048 +esp.vst.128.xp q0,x8,x8 +esp.vst.h.64.ip q0,x8,-1024 +esp.vst.h.64.xp q0,x8,x8 +esp.vst.l.64.ip q0,x8,-1024 +esp.vst.l.64.xp q0,x8,x8 +esp.slci.2q q0,q0,0 +esp.slcxxp.2q q0,q0,x8,x8 +esp.src.q q0,q0,q0 +esp.src.q.ld.ip q0,x8,-2048,q0,q0 +esp.src.q.ld.xp q0,x8,x8,q0,q0 +esp.src.q.qup q0,q0,q0 +esp.srci.2q q0,q0,0 +esp.srcmb.s16.q.qacc q0,q0,0 +esp.srcmb.s16.qacc q0,x8,0 +esp.srcmb.s8.q.qacc q0,q0,0 +esp.srcmb.s8.qacc q0,x8,0 +esp.srcmb.u16.q.qacc q0,q0,0 +esp.srcmb.u16.qacc q0,x8,0 +esp.srcmb.u8.q.qacc q0,q0,0 +esp.srcmb.u8.qacc q0,x8,0 +esp.srcq.128.st.incp q0,q0,x8 +esp.srcxxp.2q q0,q0,x8,x8 +esp.srs.s.xacc x8,x8 +esp.srs.u.xacc x8,x8 +esp.vsl.32 q0,q0 +esp.vsld.16 q0,q0,q0 +esp.vsld.32 q0,q0,q0 +esp.vsld.8 q0,q0,q0 +esp.vsr.s32 q0,q0 +esp.vsr.u32 q0,q0 +esp.vsrd.16 q0,q0,q0 +esp.vsrd.32 q0,q0,q0 +esp.vsrd.8 q0,q0,q0 +esp.st.s.xacc.ip x8,-1024 +esp.st.u.xacc.ip x8,-1024 +esp.lp.setupi 0,0,0 +esp.lp.setup 0,x8,0 +esp.lp.starti 0,0 +esp.lp.endi 0,0 +esp.lp.counti 0,0 +esp.lp.count 0,x8 diff --git a/tools/test_apps/system/gdbstub_runtime/main/CMakeLists.txt b/tools/test_apps/system/gdbstub_runtime/main/CMakeLists.txt index 9d9aaefa8f5..efe217bc94b 100644 --- a/tools/test_apps/system/gdbstub_runtime/main/CMakeLists.txt +++ b/tools/test_apps/system/gdbstub_runtime/main/CMakeLists.txt @@ -1,4 +1,9 @@ -idf_component_register(SRCS "test_app_main.c" +set(srcs "test_app_main.c") +if(CONFIG_IDF_TARGET_ARCH_RISCV AND CONFIG_SOC_CPU_HAS_HWLOOP) + list(APPEND srcs "xesppie_loops.S") +endif() + +idf_component_register(SRCS ${srcs} INCLUDE_DIRS "" REQUIRES esp_gdbstub) diff --git a/tools/test_apps/system/gdbstub_runtime/main/test_app_main.c b/tools/test_apps/system/gdbstub_runtime/main/test_app_main.c index 7f3980e3a9c..554d6fc09c1 100644 --- a/tools/test_apps/system/gdbstub_runtime/main/test_app_main.c +++ b/tools/test_apps/system/gdbstub_runtime/main/test_app_main.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2023-2024 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -7,6 +7,7 @@ #include #include "freertos/FreeRTOS.h" #include "freertos/task.h" +#include "sdkconfig.h" int var_1; int var_2; @@ -19,12 +20,17 @@ void foo(void) var_2--; } +void test_xesppie_loops(void); void app_main(void) { printf("tested app is running.\n"); vTaskDelay(5000 / portTICK_PERIOD_MS); +#if SOC_CPU_HAS_HWLOOP + test_xesppie_loops(); +#endif + while(1) { var_1++; if (var_1 % 10 == 0) { diff --git a/tools/test_apps/system/gdbstub_runtime/main/xesppie_loops.S b/tools/test_apps/system/gdbstub_runtime/main/xesppie_loops.S new file mode 100644 index 00000000000..dfb1a8a9680 --- /dev/null +++ b/tools/test_apps/system/gdbstub_runtime/main/xesppie_loops.S @@ -0,0 +1,50 @@ +/* + * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Unlicense OR CC0-1.0 + */ + +#define DEBUG_OUTPUT 0 +#define LOOP_COUNT 3 + +#if DEBUG_OUTPUT +.section .data +loop_counter_str: .string "loop counter is %d\n" +#endif + +.section .text +.type test_xesppie_loops, @function +.global test_xesppie_loops + +/* This workaround is intended to help the MI2 interpreter find labels in + * assembly code. */ +.globl test_loop_start +.type test_loop_start, @function + +test_xesppie_loops: + addi sp, sp, -16 + sw ra, 12(sp) +#if DEBUG_OUTPUT + sw s0, 8(sp) + + la s0, loop_counter_str +#endif + li t0, LOOP_COUNT + +test_loop_start: + esp.lp.setup 0, t0, test_loop_end + csrr a1, 0x7C8 +#if DEBUG_OUTPUT + mv a0, s0 + call ets_printf +#endif +test_loop_end: + nop + +#if DEBUG_OUTPUT + lw s0, 8(sp) +#endif + lw ra, 12(sp) + addi sp, sp, 16 + ret +.size test_xesppie_loops, .-test_xesppie_loops diff --git a/tools/test_apps/system/gdbstub_runtime/pytest_runtime.py b/tools/test_apps/system/gdbstub_runtime/pytest_gdbstub_runtime.py similarity index 64% rename from tools/test_apps/system/gdbstub_runtime/pytest_runtime.py rename to tools/test_apps/system/gdbstub_runtime/pytest_gdbstub_runtime.py index f2c3fa2c08a..dc51c3681af 100644 --- a/tools/test_apps/system/gdbstub_runtime/pytest_runtime.py +++ b/tools/test_apps/system/gdbstub_runtime/pytest_gdbstub_runtime.py @@ -3,6 +3,7 @@ import os import os.path as path import sys +from typing import Any import pytest @@ -19,25 +20,93 @@ def get_line_number(lookup: str, offset: int = 0) -> int: return -1 -@pytest.mark.supported_targets -@pytest.mark.generic -def test_gdbstub_runtime(dut: PanicTestDut) -> None: +def start_gdb(dut: PanicTestDut) -> None: dut.expect_exact('tested app is running.') dut.write(b'\x03') # send Ctrl-C dut.start_gdb_for_gdbstub() - # Test breakpoint - cmd = '-break-insert --source test_app_main.c --function app_main --label label_1' - response = dut.find_gdb_response('done', 'result', dut.gdb_write(cmd)) - assert response is not None - cmd = '-exec-continue' + +def run_and_break(dut: PanicTestDut, cmd: str) -> dict[Any, Any]: responses = dut.gdb_write(cmd) assert dut.find_gdb_response('running', 'result', responses) is not None - if not dut.find_gdb_response('stopped', 'notify', responses): - # have not stopped on breakpoint yet + if not dut.find_gdb_response('stopped', 'notify', responses): # have not stopped on breakpoint yet responses = dut.gdbmi.get_gdb_response(timeout_sec=3) assert dut.find_gdb_response('stopped', 'notify', responses) is not None payload = dut.find_gdb_response('stopped', 'notify', responses)['payload'] + assert isinstance(payload, dict) + return payload + + +@pytest.mark.esp32p4 +@pytest.mark.generic +def test_hwloop_jump(dut: PanicTestDut) -> None: + start_gdb(dut) + + cmd = '-break-insert --source xesppie_loops.S --function test_loop_start' + response = dut.find_gdb_response('done', 'result', dut.gdb_write(cmd)) + assert response is not None + + # go to the beginning of the loop + cmd = '-exec-continue' + payload = run_and_break(dut, cmd) + assert payload['reason'] == 'breakpoint-hit' + assert payload['bkptno'] == '1' + assert payload['frame']['func'] == 'test_xesppie_loops' + assert payload['stopped-threads'] == 'all' + + cmd = '-break-delete 1' + responses = dut.gdb_write(cmd) + assert dut.find_gdb_response('done', 'result', responses) is not None + + # go through the loop + loop_count = 3 + while loop_count: + inst_count = 2 + while inst_count: + cmd = '-exec-step' + payload = run_and_break(dut, cmd) + assert payload['reason'] == 'end-stepping-range' + assert payload['frame']['func'] == 'test_xesppie_loops' + assert payload['stopped-threads'] == 'all' + inst_count -= 1 + cmd = '-data-list-register-values d 11' + responses = dut.gdb_write(cmd) + response = dut.find_gdb_response('done', 'result', responses) + assert response is not None + payload = response['payload'] + assert payload['register-values'][0]['number'] == '11' + assert payload['register-values'][0]['value'] == f'{loop_count}' + loop_count -= 1 + + # go through the func prologue + remaining_instructions = 3 + while remaining_instructions: + cmd = '-exec-step' + payload = run_and_break(dut, cmd) + assert payload['reason'] == 'end-stepping-range' + assert payload['frame']['func'] == 'test_xesppie_loops' + assert payload['stopped-threads'] == 'all' + remaining_instructions -= 1 + + # Now we stepping back to app_main + cmd = '-exec-step' + payload = run_and_break(dut, cmd) + assert payload['reason'] == 'end-stepping-range' + assert payload['frame']['func'] == 'app_main' + assert payload['stopped-threads'] == 'all' + + +@pytest.mark.supported_targets +@pytest.mark.generic +def test_gdbstub_runtime(dut: PanicTestDut) -> None: + start_gdb(dut) + + # Test breakpoint + cmd = '-break-insert --source test_app_main.c --function app_main --label label_1' + response = dut.find_gdb_response('done', 'result', dut.gdb_write(cmd)) + assert response is not None + cmd = '-exec-continue' + payload = run_and_break(dut, cmd) assert payload['reason'] == 'breakpoint-hit' assert payload['bkptno'] == '1' assert payload['frame']['func'] == 'app_main' @@ -46,13 +115,7 @@ def test_gdbstub_runtime(dut: PanicTestDut) -> None: # Test step command cmd = '-exec-step' - responses = dut.gdb_write(cmd) - assert dut.find_gdb_response('running', 'result', responses) is not None - if not dut.find_gdb_response('stopped', 'notify', responses): - # have not stopped on breakpoint yet - responses = dut.gdbmi.get_gdb_response(timeout_sec=3) - assert dut.find_gdb_response('stopped', 'notify', responses) is not None - payload = dut.find_gdb_response('stopped', 'notify', responses)['payload'] + payload = run_and_break(dut, cmd) assert payload['reason'] == 'end-stepping-range' assert payload['frame']['func'] == 'foo' assert payload['frame']['line'] == str(get_line_number('var_2+=2;')) @@ -60,13 +123,7 @@ def test_gdbstub_runtime(dut: PanicTestDut) -> None: # Test finish command cmd = '-exec-finish' - responses = dut.gdb_write(cmd) - assert dut.find_gdb_response('running', 'result', responses) is not None - if not dut.find_gdb_response('stopped', 'notify', responses): - # have not stopped on breakpoint yet - responses = dut.gdbmi.get_gdb_response(timeout_sec=3) - assert dut.find_gdb_response('stopped', 'notify', responses) is not None - payload = dut.find_gdb_response('stopped', 'notify', responses)['payload'] + payload = run_and_break(dut, cmd) assert payload['reason'] == 'function-finished' # On riscv we may have situation when returned from a function but stay on exactly the same line # foo(); @@ -84,13 +141,7 @@ def test_gdbstub_runtime(dut: PanicTestDut) -> None: # Test next command cmd = '-exec-next' - responses = dut.gdb_write(cmd) - assert dut.find_gdb_response('running', 'result', responses) is not None - if not dut.find_gdb_response('stopped', 'notify', responses): - # have not stopped on breakpoint yet - responses = dut.gdbmi.get_gdb_response(timeout_sec=3) - assert dut.find_gdb_response('stopped', 'notify', responses) is not None - payload = dut.find_gdb_response('stopped', 'notify', responses)['payload'] + payload = run_and_break(dut, cmd) assert payload['reason'] == 'end-stepping-range' assert payload['frame']['line'] == str(get_line_number('label_3:', 1)) assert payload['frame']['func'] == 'app_main' @@ -117,12 +168,7 @@ def test_gdbstub_runtime(dut: PanicTestDut) -> None: responses = dut.gdb_write(cmd) assert dut.find_gdb_response('done', 'result', responses) is not None cmd = '-exec-continue' - responses = dut.gdb_write(cmd) - assert dut.find_gdb_response('running', 'result', responses) is not None - if not dut.find_gdb_response('stopped', 'notify', responses): - # have not stopped on breakpoint yet - responses = dut.gdbmi.get_gdb_response(timeout_sec=3) - payload = dut.find_gdb_response('stopped', 'notify', responses)['payload'] + payload = run_and_break(dut, cmd) assert payload['reason'] == 'signal-received' assert payload['frame']['func'] == 'foo' assert payload['stopped-threads'] == 'all' @@ -143,12 +189,7 @@ def test_gdbstub_runtime(dut: PanicTestDut) -> None: # test panic handling cmd = '-exec-continue' - responses = dut.gdb_write(cmd) - assert dut.find_gdb_response('running', 'result', responses) is not None - if not dut.find_gdb_response('stopped', 'notify', responses): - # have not stopped on breakpoint yet - responses = dut.gdbmi.get_gdb_response(timeout_sec=3) - payload = dut.find_gdb_response('stopped', 'notify', responses)['payload'] + payload = run_and_break(dut, cmd) assert payload['reason'] == 'signal-received' assert payload['signal-name'] == 'SIGSEGV' assert payload['frame']['func'] == 'app_main' @@ -162,22 +203,14 @@ def test_gdbstub_runtime(dut: PanicTestDut) -> None: @pytest.mark.generic @pytest.mark.temp_skip_ci(targets=['esp32', 'esp32s2', 'esp32s3'], reason='fix IDF-7927') def test_gdbstub_runtime_xtensa_stepping_bug(dut: PanicTestDut) -> None: - dut.expect_exact('tested app is running.') - dut.write(b'\x03') # send Ctrl-C - dut.start_gdb_for_gdbstub() + start_gdb(dut) # Test breakpoint cmd = '-break-insert --source test_app_main.c --function app_main --label label_1' response = dut.find_gdb_response('done', 'result', dut.gdb_write(cmd)) assert response is not None cmd = '-exec-continue' - responses = dut.gdb_write(cmd) - assert dut.find_gdb_response('running', 'result', responses) is not None - if not dut.find_gdb_response('stopped', 'notify', responses): - # have not stopped on breakpoint yet - responses = dut.gdbmi.get_gdb_response(timeout_sec=3) - assert dut.find_gdb_response('stopped', 'notify', responses) is not None - payload = dut.find_gdb_response('stopped', 'notify', responses)['payload'] + payload = run_and_break(dut, cmd) assert payload['reason'] == 'breakpoint-hit' assert payload['bkptno'] == '1' assert payload['frame']['func'] == 'app_main' @@ -186,13 +219,7 @@ def test_gdbstub_runtime_xtensa_stepping_bug(dut: PanicTestDut) -> None: # Test step command cmd = '-exec-step' - responses = dut.gdb_write(cmd) - assert dut.find_gdb_response('running', 'result', responses) is not None - if not dut.find_gdb_response('stopped', 'notify', responses): - # have not stopped on breakpoint yet - responses = dut.gdbmi.get_gdb_response(timeout_sec=3) - assert dut.find_gdb_response('stopped', 'notify', responses) is not None - payload = dut.find_gdb_response('stopped', 'notify', responses)['payload'] + payload = run_and_break(dut, cmd) assert payload['reason'] == 'end-stepping-range' assert payload['frame']['func'] == 'foo' assert payload['frame']['line'] == str(get_line_number('var_2+=2;')) @@ -200,13 +227,7 @@ def test_gdbstub_runtime_xtensa_stepping_bug(dut: PanicTestDut) -> None: # Test next command cmd = '-exec-next' - responses = dut.gdb_write(cmd) - assert dut.find_gdb_response('running', 'result', responses) is not None - if not dut.find_gdb_response('stopped', 'notify', responses): - # have not stopped on breakpoint yet - responses = dut.gdbmi.get_gdb_response(timeout_sec=3) - assert dut.find_gdb_response('stopped', 'notify', responses) is not None - payload = dut.find_gdb_response('stopped', 'notify', responses)['payload'] + payload = run_and_break(dut, cmd) assert payload['reason'] == 'end-stepping-range' assert payload['frame']['line'] == str(get_line_number('var_2--;', 0)) assert payload['frame']['func'] == 'foo'