Simulation results are inconsistent

[FSY369]

Hello, recently I encountered a problem that gave me a lot of headaches when using iverilog for project development. Here's how it works, I have an RTL design file called rtl.v that I synthesize using two different tools (vivado and yosys). Following the normal process, I thought I would get a similar result, but it wasn't.

After synthesis, I used IverLog to perform simulation tests to verify the correctness of the design. However, during this step, I noticed an anomaly: the combined results of Vivado and Yosys were inconsistent in the simulation. This inconsistency is mainly reflected in the presence of the letter "z" in the analog output, which confuses me a lot.

Here, I'd like to ask, does iverilog need additional clarification or handling of the special state of "z"? After all, in my current project, there are cases where I use the same tools and get inconsistent results.

[caryr]

I'm not sure how we can help given all you have provided is what looks like screen shots of diagnostic output. We have no idea what the RTL is that is generating the logs or what the diagnostic output corresponds to. It is very likely that the RTL is different between the two runs and that it is this difference, not a bug in iverilog, that is causing the difference.

It feels like this is part of a class and if so it would be best if you discussed any failures in your simulations with a teaching assistant or instructor before filing bug reports against the tools you are using. In general you should not need to file a report and your instructor/teaching assistant should do this after reducing the example to the minimum that reproduces the issue

Once you start to learn to code RTL one of the first adjacent skills you need to learn is how to debug the RTL and how to create a reduced example of the failure. There are occasionally issues that are because of global interactions, but these are rare. For this example it looks like you have an 8-bit wide wire that is not driven by any logic. Find the statement that is generating the output and determine what wire/wires are showing z? Next look in the design and find if the signal is actually driven in both cases. If it's not then why are the synthesis tools giving different results? It is much more likely that this is a synthesis issue and not an issue in iverilog.

Lastly if this is part of a class could you have your instructor contact us because we have seen reports like this before and we are not adjunct teaching assistants. They should be making it clear that the students do not currently have the skills necessary to file bug reports.