Skip to content
New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Assertion lwid == ivl_signal_width(lsig)' failed #1183

Open
Noah-S-E opened this issue Nov 12, 2024 · 3 comments
Open

Assertion lwid == ivl_signal_width(lsig)' failed #1183

Noah-S-E opened this issue Nov 12, 2024 · 3 comments

Comments

@Noah-S-E
Copy link

I have minimized the design and encountered an assertion error when using a task to assign values to array elements.

The error is as follows (I have upgraded to the latest version of Icarus Verilog Icarus Verilog version 13.0 (devel) (s20221226-565-g6c8ed62a5)):

iverilog -g2005-sv t.v
ivl: stmt_assign.c:480: store_vec4_to_lval: Assertion `lwid == ivl_signal_width(lsig)' failed.

module array();
  logic clk;
  logic [1:0] a[2];  

  task task1(output logic [1:0] a);
    begin
      a[0] = 00;  
      a[1] = 01;
    end
  endtask
  
  always @(posedge clk) begin
    task1(a);  
    $display("buff = %h", a); 
  end

endmodule
@caryr
Copy link
Collaborator

caryr commented Nov 12, 2024

This is caused by an error in your code that the compiler is not catching.

The error is that the function is declared to take a two bit packed vector, yet you are passing a two element array of two packed bits. It is this mismatch that is causing the assertion. Unfortunately tasks do not currently support unpacked arguments so you would need to pass them individually.

The other error that is actually in the runtime is %h is specified to only print packed elements, but you are passing an unpacked array.

It's also worth noting that the assignments inside the task are assigning signed decimal values and not binary which I am assuming was your intention.

I will leave this open since we should report the task call type does not match the task declaration type.

@caryr
Copy link
Collaborator

caryr commented Nov 12, 2024

We should also report that passing an unpacked array to %h, etc. is invalid and not just currently unsupported.

The integer format specifiers, %h, %x, %d, %o, %b, %c, %u, and %z (uppercase or lowercase), may be used with any of the SystemVerilog integral data types, including enumerated types and packed aggregate data types. These format specifiers can also be used with user-defined types that have been defined (using typedef) to be represented using one of these basic types. They shall not be used with any unpacked aggregate type.

@Noah-S-E
Copy link
Author

Thank you very much for clarifying my doubts.

Sign up for free to join this conversation on GitHub. Already have an account? Sign in to comment
Projects
None yet
Development

No branches or pull requests

2 participants