Failed assertion when creating an incorrect table

[luizademelo]

When running iverilog on the following program:

primitive id_0(output id_2, input id_1);
  table
    ? 1 ? 0 0 0 : 0;
  endtable
endprimitive 

Icarus Verilog outputs the following message:

ivl: pform.cc:1822: void process_udp_table(PUdp*, std::__cxx11::list<std::__cxx11::basic_string<char> >*, const vlltype&): Assertion `tmp.find(':') == (udp->ports.size() - 1)' failed.
Aborted

I'm using this Icarus Verilog version:
Icarus Verilog version 13.0 (devel) (s20221226-526-g5cbdff202)