Pullup/pull down are only a single connection

[caryr]

I am trying to cleanup ivtest so it works better in sv-tests (https://github.com/SymbiFlow/sv-tests) and one thing I noticed is they have flagged pullup/pulldown with multiple terminals as an error and sure enough that appears to be invalid in all version of Verilog/SystemVerilog. Is this something we should fix? As a minimum I think this needs to be move to the Icarus specific test file and we should likely generate some kind of portability warning.

[caryr]

FYI VCS does support this functionality so that alone is probably enough justification to keep things the way they are.

[steveicarus]

An example of what you think is wrong/not wrong, actual code instead of a description or external link, would be helpful. Perhaps we can generate a warning for these cases if it turns out to be an unwritten rule.

[caryr]

The standard say the following is valid:

pulldown (a);
pulldown (b);

but

pulldown(a, b);

is invalid. We along with at least VCS support the latter.

I'm all for a warning (e.g. maybe -Wportability or -Wstrict), but should it be part of -Wall?

specify
  (a, b => y) = (tr, tf);
endspecify

also does not match the standard where the input and output side of the => (full connection) are supposed to be exactly the same size. The comments in the elaboration code say NC-Verilog supports this in the case of all signals being a single bit. VCS also supports this.

[steveicarus]

This is also explicitly allowed by the standard: pulldown p1(a), p2(b); I would say that -Wportability, but not part of -Wall. It seems like such an obvious thing to do and since VCS supports it, there is that.

…

On Sat, Dec 19, 2020 at 7:48 PM Cary R. ***@***.***> wrote: The standard say the following is valid: pulldown (a); pulldown (b); but pulldown(a, b); is invalid. We along with at least VCS support the latter. I'm all for a warning (e.g. maybe -Wportability or -Wstrict), but should it be part of -Wall? specify (a, b => y) = (tr, tf); endspecify also does not match the standard where the input and output side of the => (full connection) are supposed to be exactly the same size. The comments in the elaboration code say NC-Verilog supports this in the case of all signals being a single bit. VCS also supports this. — You are receiving this because you commented. Reply to this email directly, view it on GitHub <#432 (comment)>, or unsubscribe <https://github.com/notifications/unsubscribe-auth/AAACKMRIJ5M7ZWQ66PRTCFDSVVXXDANCNFSM4VCSCQBQ> .

-- Steve Williams "The woods are lovely, dark and deep. [email protected] <[email protected]> But I have promises to keep, http://www.icarus.com and lines to code before I sleep, http://www.picturel.com And lines to code before I sleep."

[caryr]

Just to be clear, what you wrote is two instances each with a single terminal. What I wrote is a single instance with two terminals. Effectively the same from a simulation standpoint, but semantically different.

[steveicarus]

I know. Three cases: pulldown (a); pulldown (b); pulldown p1(a), p2(b); pulldown (a, b); // <-- This should generate a -Wportability warning.

…

On Sat, Dec 19, 2020 at 8:32 PM Cary R. ***@***.***> wrote: Just to be clear, what you wrote is two instances each with a single terminal. What I wrote is a single instance with two terminals. Effectively the same from a simulation standpoint, but semantically different. — You are receiving this because you commented. Reply to this email directly, view it on GitHub, or unsubscribe.

-- Steve Williams "The woods are lovely, dark and deep. [email protected] But I have promises to keep, http://www.icarus.com and lines to code before I sleep, http://www.picturel.com And lines to code before I sleep."

[martinwhitaker]

This feature was added at your request Cary:

https://sourceforge.net/p/iverilog/bugs/297/

It was supported on NC-Verilog too, so no doubt is a Verilog-XL feature that all the major simulators support for compatibility.