Replies: 5 comments 6 replies
-
I don't know what you mean by "It seems VVP tool is no longer available as a library to be linked with a bigger project simulation.". AFAIK that was never supported in the past, but was enabled by PR #1068 which was merged a couple of months ago. And yes, the person who worked on that PR certainly tried it :-) |
Beta Was this translation helpful? Give feedback.
-
@martinwhitaker sorry for the confusion, I was looking at https://steveicarus.github.io/iverilog/usage/vvp_library.html and because this option was not available (v12-branch) I thought it was removed. I looked the comments and PR and now I have doubts if that's what I need - can you help please? Suppose I compile my FPGA design with: Thanks, |
Beta Was this translation helpful? Give feedback.
-
Hello Marcio, If I had seen this discussion before today, I would have commented sooner: PR #1068 was from me, based on some earlier work. If you are interested in how I use libvvp, there is some code here. There I have been using a test harness to discover how to compile interface components with MSVC, on a machine without Iverilog installed. The aim is to use Iverilog to implement digital components inside the mixed-signal (but mostly analogue) simulator, Ngspice. The code linked is almost that same as that used with Ngspice and running for some months. I would be interested to know more about how you are using libvvp, particularly how you are handling the problem of keeping two (or more!) simulators synchronised. Giles |
Beta Was this translation helpful? Give feedback.
-
The code to use libvvp inside Ngspice is now in the development branch for the next NGspice release, probably due around December. |
Beta Was this translation helpful? Give feedback.
-
An update: iverilog support using libvvp is included in Ngspice-44, released two days ago. |
Beta Was this translation helpful? Give feedback.
-
Hi All,
It seems VVP tool is no longer available as a library to be linked with a bigger project simulation.
However I see it is possible to compile the VVP and include it in a project. Has anyone tried that? If I integrate the VVP into my simulation project, does the source code of this tool include all PLI API to exercise the HDL design?
My idea is to design a FPGA that will work with a microprocessor to interface with SRAM and some peripherals, simply speaking. I have everything constructed in an emulator, but I would want to replace C code with a PLI interface to exercise the FPGA as part of the design verification.
Thanks,
Marcio.
Beta Was this translation helpful? Give feedback.
All reactions