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caryrcaryr
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Fix the trigger for user functions with no args
1 parent c6fe010 commit f229dfc

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5 files changed

+106
-37
lines changed

5 files changed

+106
-37
lines changed

‎ivtest/ivltests/br_gh979.v

+73
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,73 @@
1+
module top;
2+
reg passed;
3+
wire wconst, wfconst, wfconstarg;
4+
wire wdconst = 1'b0;
5+
wire wdfconst = cfunc();
6+
wire wdfconstarg = func(1'b0);
7+
real rfconst;
8+
9+
function automatic reg cfunc();
10+
cfunc = 1'b0;
11+
endfunction
12+
13+
function automatic reg func(input reg val);
14+
func = val;
15+
endfunction
16+
17+
function automatic real crfunc();
18+
crfunc = 2.0;
19+
endfunction
20+
21+
assign wconst = 1'b1;
22+
assign wfconst = cfunc();
23+
assign wfconstarg = func(1'b1);
24+
assign rfconst = crfunc();
25+
26+
initial begin
27+
passed = 1'b1;
28+
#1;
29+
30+
if (wconst !== 1'b1) begin
31+
$display("Expected wire constant value to be 1'b1, actual is %b", wconst);
32+
passed = 1'b0;
33+
end
34+
35+
if (wdconst !== 1'b0) begin
36+
$display("Expected wire decl constant value to be 1'b0, actual is %b", wdconst);
37+
passed = 1'b0;
38+
end
39+
40+
if (wfconst !== 1'b0) begin
41+
$display("Expected wire constant function value to be 1'b0, actual is %b", wfconst);
42+
passed = 1'b0;
43+
end
44+
45+
if (wdfconst !== 1'b0) begin
46+
$display("Expected wire decl constant function value to be 1'b0, actual is %b", wdfconst);
47+
passed = 1'b0;
48+
end
49+
50+
if (rfconst != 2.0) begin
51+
$display("Expected real constant function value to be 2.0, actual is %f", rfconst);
52+
passed = 1'b0;
53+
end
54+
55+
if (wfconstarg !== 1'b1) begin
56+
$display("Expected wire constant arg function value to be 1'b1, actual is %b", wfconstarg);
57+
passed = 1'b0;
58+
end
59+
60+
if (wdfconstarg !== 1'b0) begin
61+
$display("Expected wire decl constant arg function value to be 1'b0, actual is %b", wdfconstarg);
62+
passed = 1'b0;
63+
end
64+
65+
if (cfunc() !== 1'b0) begin
66+
$display("Expected constant function value to be 1'b0, actual is %b", cfunc());
67+
passed = 1'b0;
68+
end
69+
70+
if (passed) $display("PASSED");
71+
end
72+
73+
endmodule

‎ivtest/ivltests/sv_argumentless_func.v

+12-12
Original file line numberDiff line numberDiff line change
@@ -10,10 +10,10 @@ parameter test_parameter = test_func();
1010
logic [7:0] test_alwayscomb;
1111
always_comb test_alwayscomb = test_func();
1212

13-
// logic [7:0] test_assign;
14-
// assign test_assign = test_func();
13+
logic [7:0] test_assign;
14+
assign test_assign = test_func();
1515

16-
// wire [7:0] test_wire = test_func();
16+
wire [7:0] test_wire = test_func();
1717

1818
logic [7:0] test_alwaysff;
1919
logic clk;
@@ -37,15 +37,15 @@ initial begin
3737
$finish;
3838
end
3939

40-
// if (test_assign !== test_func()) begin
41-
// $display("FAILED -- test_assign=%h, expect %h", test_assign, test_func());
42-
// $finish;
43-
// end
40+
if (test_assign !== test_func()) begin
41+
$display("FAILED -- test_assign=%h, expect %h", test_assign, test_func());
42+
$finish;
43+
end
4444

45-
// if (test_wire !== test_func()) begin
46-
// $display("FAILED -- test_wire=%h, expect %h", test_wire, test_func());
47-
// $finish;
48-
// end
45+
if (test_wire !== test_func()) begin
46+
$display("FAILED -- test_wire=%h, expect %h", test_wire, test_func());
47+
$finish;
48+
end
4949

5050
clk = 0;
5151
#1;
@@ -57,7 +57,7 @@ initial begin
5757
end
5858

5959
$display("PASSED");
60-
$finish;
60+
$finish(0);
6161
end
6262

6363
endmodule

‎ivtest/regress-sv.list

+1
Original file line numberDiff line numberDiff line change
@@ -994,6 +994,7 @@ br_gh823a CE,-g2012 ivltests
994994
br_gh823b CE,-g2012 ivltests
995995
br_gh840a CE,-g2012 ivltests
996996
br_gh840b CE,-g2012 ivltests
997+
br_gh979 normal,-g2012 ivltests
997998
bitsel_real_idx CE,-g2012 ivltests gold=bitsel_real_idx.gold
998999
partsel_real_idx CE,-g2012 ivltests gold=partsel_real_idx.gold
9991000
ipsdownsel_real_idx CE,-g2012 ivltests gold=ipsdownsel_real_idx.gold

‎tgt-vvp/vvp_scope.c

+15-15
Original file line numberDiff line numberDiff line change
@@ -1,5 +1,5 @@
11
/*
2-
* Copyright (c) 2001-2022 Stephen Williams ([email protected])
2+
* Copyright (c) 2001-2023 Stephen Williams ([email protected])
33
*
44
* This source code is free software; you can redistribute it
55
* and/or modify it in source code form under the terms of the GNU
@@ -2072,22 +2072,20 @@ static void draw_lpm_ufunc(ivl_lpm_t net)
20722072
for (idx = 0 ; idx < ninp ; idx += 1)
20732073
input_strings[idx] = draw_net_input(ivl_lpm_data(net, idx));
20742074

2075-
if (ivl_lpm_trigger(net))
2076-
fprintf(vvp_out, "L_%p%s .ufunc/e TD_%s, %u, E_%p", net, dly,
2077-
vvp_mangle_id(ivl_scope_name(def)),
2078-
ivl_lpm_width(net), ivl_lpm_trigger(net));
2079-
else
2080-
fprintf(vvp_out, "L_%p%s .ufunc%s TD_%s, %u", net, dly, type_string,
2081-
vvp_mangle_id(ivl_scope_name(def)),
2082-
ivl_lpm_width(net));
2083-
fprintf(vvp_out, ", ");
2075+
if (ivl_lpm_trigger(net)) {
2076+
assert(ninp > 0);
2077+
fprintf(vvp_out, "L_%p%s .ufunc/e TD_%s, %u, E_%p", net, dly,
2078+
vvp_mangle_id(ivl_scope_name(def)),
2079+
ivl_lpm_width(net), ivl_lpm_trigger(net));
2080+
} else
2081+
fprintf(vvp_out, "L_%p%s .ufunc%s TD_%s, %u", net, dly, type_string,
2082+
vvp_mangle_id(ivl_scope_name(def)),
2083+
ivl_lpm_width(net));
20842084

20852085
/* Print all the net signals that connect to the input of the
20862086
function. */
20872087
for (idx = 0 ; idx < ninp ; idx += 1) {
2088-
fprintf(vvp_out, "%s", input_strings[idx]);
2089-
if (idx != ninp-1)
2090-
fprintf(vvp_out, ", ");
2088+
fprintf(vvp_out, ", %s", input_strings[idx]);
20912089
}
20922090
free(input_strings);
20932091

@@ -2107,8 +2105,10 @@ static void draw_lpm_ufunc(ivl_lpm_t net)
21072105
fprintf(vvp_out, "v%p_0", psig);
21082106
}
21092107

2110-
if (ninp > 0)
2111-
fprintf(vvp_out, ")");
2108+
if (ninp == 0)
2109+
fprintf(vvp_out, ",");
2110+
else
2111+
fprintf(vvp_out, ")");
21122112
#if 0
21132113
/* Now print the reference to the signal from which the
21142114
result is collected. */

‎vvp/parse.y

+5-10
Original file line numberDiff line numberDiff line change
@@ -1,7 +1,7 @@
11

22
%{
33
/*
4-
* Copyright (c) 2001-2022 Stephen Williams ([email protected])
4+
* Copyright (c) 2001-2023 Stephen Williams ([email protected])
55
*
66
* This source code is free software; you can redistribute it
77
* and/or modify it in source code form under the terms of the GNU
@@ -258,24 +258,19 @@ statement
258258
other thread code that is automatically invoked if any of the
259259
bits in the symbols list change. */
260260

261+
| T_LABEL K_UFUNC_REAL T_SYMBOL ',' T_NUMBER ',' T_SYMBOL ';'
262+
{ compile_ufunc_real($1, $3, $5, 0, 0, 0, 0, $7, strdup("E_0x0")); }
261263
| T_LABEL K_UFUNC_REAL T_SYMBOL ',' T_NUMBER ',' symbols '(' symbols ')' T_SYMBOL ';'
262264
{ compile_ufunc_real($1, $3, $5, $7.cnt, $7.vect, $9.cnt, $9.vect, $11, 0); }
263265

264-
| T_LABEL K_UFUNC_REAL T_SYMBOL ',' T_NUMBER ',' T_SYMBOL ';'
265-
{ compile_ufunc_real($1, $3, $5, 0, 0, 0, 0, $7, 0); }
266-
266+
| T_LABEL K_UFUNC_VEC4 T_SYMBOL ',' T_NUMBER ',' T_SYMBOL ';'
267+
{ compile_ufunc_vec4($1, $3, $5, 0, 0, 0, 0, $7, strdup("E_0x0")); }
267268
| T_LABEL K_UFUNC_VEC4 T_SYMBOL ',' T_NUMBER ',' symbols '(' symbols ')' T_SYMBOL ';'
268269
{ compile_ufunc_vec4($1, $3, $5, $7.cnt, $7.vect, $9.cnt, $9.vect, $11, 0); }
269270

270-
| T_LABEL K_UFUNC_VEC4 T_SYMBOL ',' T_NUMBER ',' T_SYMBOL ';'
271-
{ compile_ufunc_vec4($1, $3, $5, 0, 0, 0, 0, $7, 0); }
272-
273271
| T_LABEL K_UFUNC_E T_SYMBOL ',' T_NUMBER ',' T_SYMBOL ',' symbols '(' symbols ')' T_SYMBOL ';'
274272
{ compile_ufunc_vec4($1, $3, $5, $9.cnt, $9.vect, $11.cnt, $11.vect, $13, $7); }
275273

276-
| T_LABEL K_UFUNC_E T_SYMBOL ',' T_NUMBER ',' T_SYMBOL ',' T_SYMBOL ';'
277-
{ compile_ufunc_vec4($1, $3, $5, 0, 0, 0, 0, $7, 0); }
278-
279274
/* Resolver statements are very much like functors. They are
280275
compiled to functors of a different mode. */
281276

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