add config for sram capacity

Author: yaqiz01

src/core/SpadeConfig.scala

@@ -25,6 +25,7 @@ object SpadeConfig extends prism.GlobalConfig {
   /* ------------------ Architecture parameters ---------------- */
   register[Int]("word", default=32, info="Word width")
   register[Int]("vec", default=16, info="Vector width of SIMD lanes and vector network")
+  register[Int]("pmu-sram-size", default=64*1024, info="SRAM capacity in PMU in word.")
   register[String]("net", default="static", info="Network type [dynamic, static, asic, p2p]")
   register[String]("topo", default="mesh", info="Network topology [mesh, torus, cmesh]")
   register[Int]("row", default=2, info="number of rows in network")

src/param/DesignParam.scala

@@ -11,5 +11,5 @@ case class DesignParam(
 ) extends Parameter {
   def burstSizeWord = burstSize / wordWidth
   def burstSizeByte = burstSize / 8 
-  def bytePerWord = designParam.wordWidth / 8
+  def bytePerWord = wordWidth / 8
 }

src/param/routable/CUParams.scala

@@ -69,7 +69,7 @@ case class PMUParam (
   controlFifoParam:FIFOParam=FIFOParam(size=option("fifo-depth")),
   scalarFifoParam:FIFOParam=FIFOParam(size=option("fifo-depth")),
   vectorFifoParam:FIFOParam=FIFOParam(size=option("fifo-depth")),
-  sramParam:SRAMParam=SRAMParam(size=256 * 1024 / 4,4), // 256 kB
+  sramParam:SRAMParam=SRAMParam(size=option("pmu-sram-size"),4), // 256 kB
   numCtrs:Int=6,
   simdParam:Option[SIMDParam]=Some(DefaultSIMDParam(
     numStages=4,