Update LiteX soc

Author: mole99

fpga/ulx3s_soc/csr.csv

@@ -1,35 +1,31 @@
 #--------------------------------------------------------------------------------
-# Auto-generated by LiteX (a977adf5) on 2022-07-05 15:47:10
+# Auto-generated by LiteX (a977adf5) on 2022-07-18 10:34:45
 #--------------------------------------------------------------------------------
-csr_base,sim_trace,0x82000000,,
-csr_base,sim_marker,0x82000800,,
-csr_base,sim_finish,0x82001000,,
-csr_base,ctrl,0x82001800,,
-csr_base,identifier_mem,0x82002000,,
-csr_base,timer0,0x82002800,,
-csr_base,uart,0x82003000,,
-csr_register,sim_trace_enable,0x82000000,1,rw
-csr_register,sim_marker_marker,0x82000800,1,rw
-csr_register,sim_finish_finish,0x82001000,1,rw
-csr_register,ctrl_reset,0x82001800,1,rw
-csr_register,ctrl_scratch,0x82001804,1,rw
-csr_register,ctrl_bus_errors,0x82001808,1,ro
-csr_register,timer0_load,0x82002800,1,rw
-csr_register,timer0_reload,0x82002804,1,rw
-csr_register,timer0_en,0x82002808,1,rw
-csr_register,timer0_update_value,0x8200280c,1,rw
-csr_register,timer0_value,0x82002810,1,ro
-csr_register,timer0_ev_status,0x82002814,1,ro
-csr_register,timer0_ev_pending,0x82002818,1,rw
-csr_register,timer0_ev_enable,0x8200281c,1,rw
-csr_register,uart_rxtx,0x82003000,1,rw
-csr_register,uart_txfull,0x82003004,1,ro
-csr_register,uart_rxempty,0x82003008,1,ro
-csr_register,uart_ev_status,0x8200300c,1,ro
-csr_register,uart_ev_pending,0x82003010,1,rw
-csr_register,uart_ev_enable,0x82003014,1,rw
-csr_register,uart_txempty,0x82003018,1,ro
-csr_register,uart_rxfull,0x8200301c,1,ro
+csr_base,ctrl,0x82000000,,
+csr_base,identifier_mem,0x82000800,,
+csr_base,leds,0x82001000,,
+csr_base,timer0,0x82001800,,
+csr_base,uart,0x82002000,,
+csr_register,ctrl_reset,0x82000000,1,rw
+csr_register,ctrl_scratch,0x82000004,1,rw
+csr_register,ctrl_bus_errors,0x82000008,1,ro
+csr_register,leds_out,0x82001000,1,rw
+csr_register,timer0_load,0x82001800,1,rw
+csr_register,timer0_reload,0x82001804,1,rw
+csr_register,timer0_en,0x82001808,1,rw
+csr_register,timer0_update_value,0x8200180c,1,rw
+csr_register,timer0_value,0x82001810,1,ro
+csr_register,timer0_ev_status,0x82001814,1,ro
+csr_register,timer0_ev_pending,0x82001818,1,rw
+csr_register,timer0_ev_enable,0x8200181c,1,rw
+csr_register,uart_rxtx,0x82002000,1,rw
+csr_register,uart_txfull,0x82002004,1,ro
+csr_register,uart_rxempty,0x82002008,1,ro
+csr_register,uart_ev_status,0x8200200c,1,ro
+csr_register,uart_ev_pending,0x82002010,1,rw
+csr_register,uart_ev_enable,0x82002014,1,rw
+csr_register,uart_txempty,0x82002018,1,ro
+csr_register,uart_rxfull,0x8200201c,1,ro
 constant,config_clock_frequency,50000000,,
 constant,config_cpu_reset_addr,0,,
 constant,config_cpu_type_femtorv,None,,

fpga/ulx3s_soc/firmware/firmware_build.bin

@@ -53,37 +53,44 @@ void wfg_init(void)
 {
     //*(volatile int*)(WFG_BASE) = 0xDEADBEEF;
 
-    int sync_count = 16;
-    int subcycle_count = 16;
+    int core_sync_count = 16;
+    int core_subcycle_count = 16;
+    
+    int subcore_sync_count = 32;
+    int subcore_subcycle_count = 16;
 
     // Core
-    wfg_set_register(0x1, 0x4, (sync_count << 0) | (subcycle_count << 8));
+    wfg_set_register(0x1, 0x4, (core_sync_count << 0) | (core_subcycle_count << 8));
     wfg_set_register(0x1, 0x0, 1); // Enable
 
-    // Interconnect
-    wfg_set_register(0x2, 0x4, 0); // Driver0
-    wfg_set_register(0x2, 0x8, 1); // Driver1
+    // Subcore
+    wfg_set_register(0x2, 0x4, (subcore_sync_count << 0) | (subcore_subcycle_count << 8));
     wfg_set_register(0x2, 0x0, 1); // Enable
 
-    // Sine
+    // Interconnect
+    wfg_set_register(0x3, 0x4, 0); // Driver0
+    wfg_set_register(0x3, 0x8, 1); // Driver1
     wfg_set_register(0x3, 0x0, 1); // Enable
 
-    // Mem
-    wfg_set_register(0x4, 0x4, 0x4); // Start
-    wfg_set_register(0x4, 0x8, 0xF); // End
-    wfg_set_register(0x4, 0xC, 0x2); // Increment
+    // Sine
     wfg_set_register(0x4, 0x0, 1); // Enable
+    
+    // Mem
+    wfg_set_register(0x5, 0x4, 0x4); // Start
+    wfg_set_register(0x5, 0x8, 0xF); // End
+    wfg_set_register(0x5, 0xC, 0x2); // Increment
+    wfg_set_register(0x5, 0x0, 1); // Enable
 
     // SPI
-    wfg_set_register(0x5, 0x8, cnt); // Clock divider
-    wfg_set_register(0x5, 0x4, (cpol<<0) | (lsbfirst<<1) | (dff<<2) | (sspol<<4));
-    wfg_set_register(0x5, 0x0, 1); // Enable SPI
+    wfg_set_register(0x6, 0x8, cnt); // Clock divider
+    wfg_set_register(0x6, 0x4, (cpol<<0) | (lsbfirst<<1) | (dff<<2) | (sspol<<4));
+    wfg_set_register(0x6, 0x0, 1); // Enable SPI
 
     // Pattern
-    wfg_set_register(0x6, 0x4, (0) | (8<<8) ); // Start:End
-    wfg_set_register(0x6, 0x8, 0xFFFFFFFF); // Low bit
-    wfg_set_register(0x6, 0xC, 0xFFFFFFFF); // High bit
-    wfg_set_register(0x6, 0x0, 0xFFFFFFFF); // Enable all bits
+    wfg_set_register(0x7, 0x4, (0) | (8<<8) ); // Start:End
+    wfg_set_register(0x7, 0x8, 0xFFFFFFFF); // Low bit
+    wfg_set_register(0x7, 0xC, 0xFFFFFFFF); // High bit
+    wfg_set_register(0x7, 0x0, 0xFFFFFFFF); // Enable all bits
 }
 
 #endif

fpga/ulx3s_soc/firmware/firmware_build.elf

@@ -164,13 +164,14 @@ def __init__(self,
                 spi_cs      = oled_ctl.csn
                 spi_sdo     = oled_spi.mosi
 
-            platform.add_source("../../../design/wfg_top/rtl/wfg_top.sv")
-            platform.add_source("../../../design/wfg_core/rtl/*.sv")
-            platform.add_source("../../../design/wfg_interconnect/rtl/*.sv")
-            platform.add_source("../../../design/wfg_stim_sine/rtl/*.sv")
-            platform.add_source("../../../design/wfg_stim_mem/rtl/*.sv")
-            platform.add_source("../../../design/wfg_drive_spi/rtl/*.sv")
-            platform.add_source("../../../design/wfg_drive_pat/rtl/*.sv")
+            platform.add_source("../../design/wfg_top/rtl/wfg_top.sv")
+            platform.add_source("../../design/wfg_core/rtl/*.sv")
+            platform.add_source("../../design/wfg_subcore/rtl/*.sv")
+            platform.add_source("../../design/wfg_interconnect/rtl/*.sv")
+            platform.add_source("../../design/wfg_stim_sine/rtl/*.sv")
+            platform.add_source("../../design/wfg_stim_mem/rtl/*.sv")
+            platform.add_source("../../design/wfg_drive_spi/rtl/*.sv")
+            platform.add_source("../../design/wfg_drive_pat/rtl/*.sv")
 
             self.specials += Instance("wfg_top",
                 i_io_wbs_clk      = self.crg.cd_sys.clk,