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Steven Derrien
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Merge pull request #4 from sderrien/dev
Dev
2 parents 485f098 + c9d3b61 commit 1117b4d

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11 files changed

+69
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Makefile

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -49,7 +49,7 @@ rsync:
4949

5050

5151
rdebug: rgdb
52-
ssh sderrien@ubuntu18vm $(REMOTE_PATH)/bin/gdb-server-uart
52+
ssh sderrien@ubuntu18vm $(REMOTE_PATH)/bin/gdb-server-uart $(DEVICE)
5353
riscv32-unknown-elf-gdb ../riscv-programs/example.elf --ex='target $(REMOTE_HOST):1234'
5454

5555
debug:

readme.md

Lines changed: 21 additions & 12 deletions
Original file line numberDiff line numberDiff line change
@@ -32,40 +32,49 @@ Installation
3232

3333
Get the sources from the repo
3434

35-
git clone
35+
git clone https://github.com/sderrien/riscv-hls.git
3636

3737
Update `PATH` with local folders
3838

39-
export PATH=$PATH:#$install_dir/bin
39+
cd riscv-hls
40+
export PATH=$PATH:`pwd`/bin
4041

41-
Synthesize RTL for the CPU ISS with Vivado HLS
42+
Installation
43+
------------
44+
4245

43-
make -C ./riscv-core hls_ip
46+
Synthesize RTL for the CPU ISS with Vivado HLS
47+
48+
make hls
4449

4550
Perform logic sythesis, place & route and geenrate bitstream
4651

47-
make -C ./vivado bistream
52+
make bistream
53+
54+
Program the Nexys4-DDR board through Digilent USB bridge
4855

49-
Program the Nexys4-DDR board (assume /dev/ttyUSB1)
56+
make program
5057

51-
make -C ./vivado program
58+
Compiling gdb servers for the RISCV
5259

53-
Compiling RISCV programs
60+
make gdb
61+
62+
Compiling RISCV example programs
5463

55-
make -C ./riscv-programs
64+
make elf
5665

5766

5867
Usage (from command line)
5968
-------------------------
6069

61-
Debugging a progam using the ISS model running on the host CPU
70+
To debug a program running on the ISS model running on the host CPU
6271

6372
gdb-server-iss
6473
riscv32-unknown-elf-gdb -ex "target remote :1234" ../riscv-programs/example.elf
6574

66-
Debugging a program running on the RISCV core on the FPGA
75+
To debug a program running on the FPGA using the RISCV hardware IP synthesized from the ISS model
6776

68-
gdb-server-uart
77+
gdb-server-uart
6978
riscv32-unknown-elf-gdb -ex "target remote 1234" ../riscv-programs/example.elf
7079

7180

riscv-core/.cproject

Lines changed: 4 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -10,11 +10,13 @@
1010
</cconfiguration>
1111
</storageModule>
1212
<storageModule moduleId="scannerConfiguration"/>
13+
<storageModule moduleId="org.eclipse.cdt.core.LanguageSettingsProviders"/>
14+
<storageModule moduleId="org.eclipse.cdt.make.core.buildtargets"/>
1315
<storageModule moduleId="org.eclipse.cdt.core.pathentry">
1416
<pathentry include="/Applications/Xcode.app/Contents/Developer/Platforms/MacOSX.platform/Developer/SDKs/MacOSX.sdk/usr/include/" kind="inc" path="" system="true"/>
17+
<pathentry base-path="riscv-gdbserver" include="" kind="inc" path="" system="true"/>
1518
<pathentry kind="src" path=""/>
1619
<pathentry kind="out" path="build"/>
1720
</storageModule>
18-
<storageModule moduleId="org.eclipse.cdt.core.LanguageSettingsProviders"/>
19-
<storageModule moduleId="org.eclipse.cdt.make.core.buildtargets"/>
21+
<storageModule moduleId="org.eclipse.cdt.internal.ui.text.commentOwnerProjectMappings"/>
2022
</cproject>

riscv-core/hls/Makefile

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1,3 +1,4 @@
11
hls:
2+
-rm -rf uart_master
23
vivado_hls -f hls.tcl
34

riscv-core/hls/hls.tcl

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -6,8 +6,8 @@
66
open_project uart_master
77
set_top uart_master
88
add_files ../src/asm.cpp
9-
add_files ../src/miniriscv.cpp
10-
add_files -cflags -I../../riscv-gdbserver ../src/uart_server.cpp
9+
add_files -cflags "-I../../riscv-gdbserver -I../src" ../src/riscv-iss.cpp
10+
add_files -cflags "-I../../riscv-gdbserver -I../src" ../src/uart_server.cpp
1111
open_solution "solution1"
1212
set_part {xc7a100tcsg324-1}
1313
create_clock -period 10 -name default

riscv-core/src/asm.cpp

Lines changed: 2 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -38,7 +38,8 @@ struct decode_info decode(unsigned int ir) {
3838
}
3939
}
4040

41-
#ifndef SYNTHESIS
41+
#ifndef __SYNTHESIS__
42+
4243
char buffer[256];
4344

4445
char *regnames[32] = { "zero", "ra", "sp", "gp", "tp", "t0", "t1", "t2",

riscv-core/src/riscv-iss.cpp

Lines changed: 5 additions & 66 deletions
Original file line numberDiff line numberDiff line change
@@ -104,13 +104,18 @@ int cpu_load(uint32_t addr) {
104104
}
105105

106106
void cpu_store(uint32_t addr,uint8_t data) {
107+
if (addr < (MEMSIZE)) {
108+
107109
memw[addr]=data;
108110
switch (addr%4) {
109111
case 0: mem0[addr32(addr)]= data; break;
110112
case 1: mem1[addr32(addr)]= data; break;
111113
case 2: mem2[addr32(addr)]= data; break;
112114
case 3: mem3[addr32(addr)]= data; break;
113115
}
116+
} else {
117+
PRINTF("Out of bound [%08X]\n",addr);
118+
}
114119
// PRINTF("[%08X]=%02X ; {%02X,%02X,%02X,%02X}\n",addr,data,
115120
// mem0[addr32(addr)],
116121
// mem1[addr32(addr)],
@@ -184,21 +189,6 @@ int remove_hw_bkpt(uint32_t addr) {
184189
return 0;
185190
}
186191

187-
//int read_csr(uint16_t addr) {
188-
// switch (addr) {
189-
// case RISCV_CSR_MTVEC:
190-
// return mtvec;
191-
// break;
192-
// default:
193-
// break;
194-
// }
195-
//}
196-
//
197-
//csr[RISCV_CSR_MEPC] = pc;
198-
// next_pc = csr[RISCV_CSR_MTVEC];
199-
//int write_csr(uint16_t addr,uint32_t data) {
200-
//}
201-
202192
uint32_t cpu_step(bool irq) {
203193

204194
char shcpt = -1;
@@ -698,20 +688,6 @@ int cpu_info(uint8_t id) {
698688
return 0xDEADBEEF;
699689
}
700690

701-
//int cpu_run() {
702-
// uint32_t pc;
703-
// u_int32_t cpt = 0;
704-
// bool irq = false;
705-
// do {
706-
// pc = cpu_step(irq);
707-
// if (match_hbkpt(pc)) {
708-
// return pc;
709-
// }
710-
// if (halted) {
711-
// return pc;
712-
// }
713-
// } while (1);
714-
//}
715691

716692
#pragma toplevel
717693
int riscv(volatile unsigned int *leds, volatile unsigned int *dbg_pc,
@@ -739,41 +715,4 @@ int riscv(volatile unsigned int *leds, volatile unsigned int *dbg_pc,
739715

740716
}
741717

742-
#ifndef __SYNTHESIS__
743-
int loadbinary(char *filename) {
744-
int i;
745-
FILE *f;
746-
char buffer[16];
747-
f = fopen(filename, "r");
748-
i = 0;
749-
if (f != NULL) {
750-
while (!feof(f) && i < (MEMSIZE)) {
751-
fread(buffer, 4, 1, f);
752-
mem0[i / 4] = buffer[0];
753-
mem1[i / 4] = buffer[1];
754-
mem2[i / 4] = buffer[2];
755-
mem3[i / 4] = buffer[3];
756-
i += 4;
757-
}
758-
fclose(f);
759-
return i;
760-
} else {
761-
fprintf(stderr, "Could not open %s\n", filename);
762-
return -1;
763-
}
764-
}
765-
#endif
766718

767-
#ifdef MAIN
768-
int main(int argc, char **argv) {
769-
unsigned int leds;
770-
unsigned int pc;
771-
unsigned int ir;
772-
773-
#ifndef __SYNTHESIS__
774-
loadbinary(argv[1]);
775-
#endif
776-
riscv(&leds, &pc,&ir,iomap);
777-
return 0;
778-
}
779-
#endif

riscv-core/src/uart_server.cpp

Lines changed: 10 additions & 51 deletions
Original file line numberDiff line numberDiff line change
@@ -14,16 +14,13 @@
1414
#include <unistd.h>
1515
#endif
1616

17-
#include <gdb-target.h>
18-
#include "rvi32.h"
19-
2017

2118
#ifdef __SYNTHESIS__
2219

23-
#define FFLUSH(...) 0
24-
#define PRINTF(...) 0
25-
#define FPRINTF(...) 0
26-
#define EXIT(a) 0
20+
#define FFLUSH(...)
21+
#define PRINTF(...)
22+
#define FPRINTF(...)
23+
#define EXIT(a)
2724

2825
#else
2926

@@ -34,6 +31,10 @@
3431

3532
#endif
3633

34+
35+
#include <gdb-target.h>
36+
#include <rvi32.h>
37+
3738
#ifndef __SYNTHESIS__
3839

3940
FILE *in_trace , *out_trace = NULL;
@@ -101,15 +102,12 @@ int read_byte(volatile unsigned int *uart) {
101102
#endif
102103
}
103104

104-
105+
#define TX_FULL_MASK 0x8
105106

106107
void write_byte(volatile unsigned int *uart, unsigned char data) {
107108
#ifdef __SYNTHESIS__
108109
int x;
109-
for (int k=0;k<0x1000;k++) {
110-
x= uart[2];
111-
}
112-
while ((uart[2] & 0x2)!=0);
110+
while ((uart[2] & TX_FULL_MASK)!=0);
113111
uart[1] = data;
114112
return;
115113
#else
@@ -207,7 +205,6 @@ uint32_t cpu_step(bool irq);
207205
int cpu_load(uint32_t addr);
208206
void cpu_store(uint32_t addr,uint8_t data);
209207
int cpu_reset();
210-
int loadbinary(char *filename);
211208

212209
extern bool halted ;
213210
int cmd_count = 0xAB000000;
@@ -381,10 +378,6 @@ int uart_master(volatile bool *debug, volatile bool *step,
381378
write_string(uart, "Helloworld from hls-riscv on nexys4-DDR\r\n");
382379
while (1) {
383380

384-
//
385-
// if (!halted) {
386-
// cpu_step(false);
387-
// }
388381
if (*step ) {
389382
*dbg_ir = 0xABBADEDE;
390383
}
@@ -398,38 +391,4 @@ int uart_master(volatile bool *debug, volatile bool *step,
398391
}
399392
}
400393

401-
int main(int argc, char** argv) {
402-
unsigned int io[1024];
403-
unsigned int pc, ir;
404-
bool dbg, step;
405-
406-
#ifndef __SYNTHESIS__
407-
// Open FIFO for write only
408-
mkfifo("/tmp/c2s",0666);
409-
io[0] = open("/tmp/c2s", O_RDONLY|O_NONBLOCK);
410-
if (io[0]<0) {
411-
FPRINTF(stderr,"error c2s\n");FFLUSH(stderr);
412-
return -1;
413-
}
414-
415-
mkfifo("/tmp/s2c",0666);
416-
io[1] = open("/tmp/s2c", O_WRONLY);
417-
if (io[1]<0) {
418-
FPRINTF(stderr,"error s2c\n");FFLUSH(stderr);
419-
return -1;
420-
}
421-
422-
if (argc==2) {
423-
FPRINTF(stdout,"loading program %s\n",argv[1]); FFLUSH(stdout);
424-
loadbinary(argv[1]);
425-
}
426-
427-
FPRINTF(stdout,"opened pipes\n"); FFLUSH(stdout);
428-
#endif
429-
430-
uart_master(&dbg, &step, &pc, &ir, io);
431-
#ifndef __SYNTHESIS__
432-
system("/bin/stty -raw");
433-
#endif
434-
}
435394

riscv-gdbserver/gdb-target-uart.cpp

Lines changed: 6 additions & 11 deletions
Original file line numberDiff line numberDiff line change
@@ -77,30 +77,25 @@ bool init_device(char *device) {
7777
}
7878

7979

80-
unsigned int hasbyte = 0;
81-
82-
83-
8480
bool has_byte() {
8581
int bytes;
8682
ioctl(tty, FIONREAD, &bytes);
8783
return bytes>1;
8884
}
8985

90-
int cpt = 1;
91-
92-
// int bytes;
93-
// ioctl(fd, FIONREAD, &bytes);
94-
9586
int read_byte() {
9687
unsigned char c;
9788
do {
98-
hasbyte = (read(tty, &c, sizeof(char))==1) ;
89+
int hasbyte = (read(tty, &c, sizeof(char))==1) ;
90+
if (hasbyte<0) {
91+
fprintf(stderr,"Error tty\n");
92+
exit(-1);
93+
}
9994
trace_in(c);
10095
if ((c&0x80)==0) {
10196
return c;
10297
} else {
103-
printf("%c",c);
98+
printf("stdout: %c",c);
10499
}
105100
} while(1);
106101
}

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