fix docs

Author: wissygh

.gitignore

@@ -123,9 +123,8 @@ temp
 
 # jar
 # *.jar
-main.py
 
 # docs
 _site/
-errors/
+testfordocs/
 *.lock

docs/AboutPyHCL/AboutPyHCL.md

@@ -0,0 +1,33 @@
+---
+sort: 1
+---
+# FAQ
+## What is the overhead of PyHCL generated RTL compared to human written Verilog?
+PyHCL is a hardware construct language like [Chisel](https://github.com/freechipsproject/chisel3) but more lightweight and more relaxed to use.
+
+## What if PyHCL becomes unsupported in the future?
+This question has two sides:
+
+1. PyHCL generates Verilog files, which means that PyHCL will be supported by all EDA tools for many decades.
+
+2. If there is a bug in PyHCL and there is no longer support to fix it, it’s not a deadly situation, because the PyHCL compiler is fully open source. For simple issues, you may be able to fix the issue yourself in few hours. Remember how much time it takes to EDA companies to fix issues or to add new features in their closed tools.
+
+## Does PyHCL keep comments in generated verilog?
+No, it doesn’t. Generated files should be considered as a netlist.
+## Could PyHCL scale up to big projects?
+PyHCL is powered by [FIRRTL](https://github.com/freechipsproject/firrtl), an intermediate representation for digital circuit design.
+
+PyHCL-generated circuits can be compiled to the widely-used HDL Verilog.
+
+Attention: The back end of the compilation is highly experimental.
+## How PyHCL came to be?
+The dominant hardware design languages in industry are **Verilog** and **VHDL**, however this procedural language, which has been around for decades, can no longer meet the needs of today's increasingly large and complex integrated circuit chip development.
+
+**Chisel**, the pioneer of combining hardware design with high-level programming languages, has proposed the possibility of agile design for hardware by embedding hardware design into the high-level programming language Scala. Embedding a hardware design framework into an object-oriented programming language allows hardware design to enjoy the advantages of object-oriented language ontologies.
+
+However, since Chisel is based on Scala, this language has a small audience, is difficult to learn, and has a low community activity, making it difficult to get started and the learning time period is long, which is not conducive to its promotion. Therefore, our team uses the Python language to design and develop PyHCL to provide a more easy-to-use and concise hardware design framework.
+
+## Why develop a new language when there is VHDL/Verilog/SystemVerilog?
+The goal of PyHCL is providing a complete design and verification tool flow for heterogeneous computing systems flexibly using the same design methodology.
+## How to use an unreleased version of PyHCL (but committed on git)?
+

docs/AboutPyHCL/FAQ.md

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+---
+sort: 2
+---
+# Support
+[![Build Status](https://travis-ci.com/scutdig/py-hcl.svg?branch=master)](https://travis-ci.com/scutdig/py-hcl)
+[![codecov](https://codecov.io/gh/scutdig/py-hcl/branch/master/graph/badge.svg)](https://codecov.io/gh/scutdig/py-hcl)
+[![PyPI](https://img.shields.io/pypi/v/py-hcl.svg)](https://pypi.python.org/pypi)
+## Communication channels
+For bug reporting and feature requests, do not hesitate to create github issues:\
+<https://github.com/scutdig/PyChip-py-hcl/issues>  \
+
+## Commercial support

docs/AboutPyHCL/Support.md

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+---
+sort: 3
+---
+# Users
+## Companies
+## Repositories
+

docs/AboutPyHCL/Users.md

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+---
+sort: 9
+---
+# AFix
+
+## Description
+## Declaration
+## Operations

docs/Datatypes/AFix.md

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+---
+sort: 2
+---
+# Bits
+
+## Description
+## Declaration
+## Operations

docs/Datatypes/Bits.md

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+---
+sort: 1
+---
+# Bool
+
+## Description
+The Bool type corresponds to `U.w(1)`.
+## Declaration
+The syntax to declare a boolean value is as follows:
+
+|        Syntax        |                             Description                              |     Return    |
+|:--------------------:|:--------------------------------------------------------------------:|:-------------:|
+|         Bool         |                            Create a Bool                             |     U.w(1)    |
+| Bool(value: Boolean) | Create a Bool <br/>assigned with a Python Boolean<br/> (true, false) | U.w(1)(value) |
+
+```python
+myBool_1 = Bool         # Create a Bool
+myBool_1 = Bool(True)
+myBOol_2 = Bool(3>5)    # same as Bool(False)
+io.cout @= myBool_1     # @= is the assignment operator
+```
+## Operators
+All operators available for the Bool type is same as `U.w(1)`

docs/Datatypes/Bool.md

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+---
+sort: 5
+---
+# Bundle！
+## Description
+The Bundle is a composite type that defines a group of named signals (of any PyHCL basic type) under a single name. It is similar to Chisel Bundle. Actually, in PyHCL's core library, IO is actually a Bundle and translate to FIRRTL later on. As a beginner of PyHCL, you could simply treat Bundle as the struct data structure of C/C++.
+## Declaration
+The way we define a Bundle is similar to IO:
+```python
+bun = Bundle(
+  x=U.w(16),
+  y=S.w(16),
+  z=Bool
+)
+```
+`x`, `y`, and `z` are the subfield of Bundle. `Bundle` is a datatype, so it must used in a circuit element:
+```python
+breg = Reg(Bundle(
+  x=U.w(16),
+  y=S.w(16),
+  z=Bool
+))
+```
+We use `.` operator to access the subfield of the `Bundle`, similar to IO:
+```python
+breg.x <<= U(12)
+breg.y <<= S(4)
+breg.z <<= Bool(False)
+io.out <<= breg.x
+```
+> Bundle is still an experimental feature of PyHCL, we suggest that you only include basic types in Bundle.
+
+### Conditional signals
+
+## Operators
+### Comparison
+### Type cast
+### Convert Bits back to Bundle
+## IO Element direction