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vedge_FixPt.vhd
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-- -------------------------------------------------------------
--
-- File Name: G:\AI\IIT BHU\codegen\vedge\hdlsrc\vedge_FixPt.vhd
-- Created: 2016-05-25 12:40:40
--
-- Generated by MATLAB 8.1, MATLAB Coder 2.4 and HDL Coder 3.2
--
--
--
-- -------------------------------------------------------------
-- Rate and Clocking Details
-- -------------------------------------------------------------
-- Design base rate: 1
--
--
-- Clock Enable Sample Time
-- -------------------------------------------------------------
-- ce_out 1
-- -------------------------------------------------------------
--
--
-- Output Signal Clock Enable Sample Time
-- -------------------------------------------------------------
-- p1_out ce_out 1
-- p2_out ce_out 1
-- -------------------------------------------------------------
--
-- -------------------------------------------------------------
-- -------------------------------------------------------------
--
-- Module: vedge_FixPt
-- Source Path: vedge_FixPt
-- Hierarchy Level: 0
--
-- -------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.numeric_std.ALL;
USE work.vedge_FixPt_pkg.ALL;
ENTITY vedge_FixPt IS
PORT( clk : IN std_logic;
reset : IN std_logic;
clk_enable : IN std_logic;
b1_in : IN std_logic_vector(7 DOWNTO 0); -- ufix8
b2_in : IN std_logic_vector(7 DOWNTO 0); -- ufix8
ce_out : OUT std_logic;
p1_out : OUT std_logic_vector(8 DOWNTO 0); -- sfix9
p2_out : OUT std_logic_vector(7 DOWNTO 0) -- ufix8
);
END vedge_FixPt;
ARCHITECTURE rtl OF vedge_FixPt IS
-- Constants
CONSTANT nc : vector_of_signed3(0 TO 1) := ( to_signed(-1, 3), to_signed(1, 3) ); -- sfix3 [2]
-- Signals
SIGNAL enb : std_logic;
SIGNAL b1_in_unsigned : unsigned(7 DOWNTO 0); -- ufix8
SIGNAL b2_in_unsigned : unsigned(7 DOWNTO 0); -- ufix8
SIGNAL p1_out_tmp : signed(8 DOWNTO 0); -- sfix9
SIGNAL p2_out_tmp : unsigned(7 DOWNTO 0); -- ufix8
BEGIN
b1_in_unsigned <= unsigned(b1_in);
b2_in_unsigned <= unsigned(b2_in);
enb <= clk_enable;
vedge_FixPt_1_output : PROCESS (b1_in_unsigned, b2_in_unsigned)
VARIABLE BSI : vector_of_unsigned8(0 TO 1);
VARIABLE c : vector_of_signed11(0 TO 3);
VARIABLE OrigImg_1 : vector_of_signed9(0 TO 3);
VARIABLE add_cast : vector_of_signed64(0 TO 1);
VARIABLE add_cast_0 : vector_of_signed64(0 TO 1);
VARIABLE cast : vector_of_signed9(0 TO 1);
VARIABLE mul_temp : vector_of_signed12(0 TO 1);
VARIABLE add_cast_1 : vector_of_signed11(0 TO 1);
BEGIN
--spssa
--%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
-- %
-- Generated by MATLAB 8.1, MATLAB Coder 2.4 and HDL Coder 3.2 %
-- %
--%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
BSI(0) := b1_in_unsigned;
BSI(1) := b2_in_unsigned;
c := (OTHERS => to_signed(0, 11));
FOR l IN 0 TO 1 LOOP
FOR m IN 0 TO 1 LOOP
add_cast(m) := resize(to_signed(m, 32) & '0', 64);
add_cast_0(m) := resize(to_signed(m, 32) & '0', 64);
cast(m) := signed(resize(BSI(m), 9));
mul_temp(m) := nc(l) * cast(m);
add_cast_1(m) := mul_temp(m)(10 DOWNTO 0);
c(to_integer(to_signed(l, 32) + resize(add_cast(m), 32))) := c(to_integer(to_signed(l, 32) + resize(add_cast_0(m), 32))) + add_cast_1(m);
END LOOP;
END LOOP;
FOR t_0 IN 0 TO 3 LOOP
OrigImg_1(t_0) := c(t_0)(8 DOWNTO 0);
END LOOP;
--PD=abs((b1_in)-(b2_in));
p1_out_tmp <= OrigImg_1(0);
p2_out_tmp <= unsigned(OrigImg_1(3)(7 DOWNTO 0));
END PROCESS vedge_FixPt_1_output;
p1_out <= std_logic_vector(p1_out_tmp);
p2_out <= std_logic_vector(p2_out_tmp);
ce_out <= clk_enable;
END rtl;