Add the keylocker intrinsics

Author: sayantn

crates/core_arch/missing-x86.md

@@ -137,27 +137,6 @@
 </p></details>
 
 
-<details><summary>["KEYLOCKER"]</summary><p>
-
-  * [ ] [`_mm_aesdec128kl_u8`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_aesdec128kl_u8)
-  * [ ] [`_mm_aesdec256kl_u8`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_aesdec256kl_u8)
-  * [ ] [`_mm_aesenc128kl_u8`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_aesenc128kl_u8)
-  * [ ] [`_mm_aesenc256kl_u8`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_aesenc256kl_u8)
-  * [ ] [`_mm_encodekey128_u32`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_encodekey128_u32)
-  * [ ] [`_mm_encodekey256_u32`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_encodekey256_u32)
-  * [ ] [`_mm_loadiwkey`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_loadiwkey)
-</p></details>
-
-
-<details><summary>["KEYLOCKER_WIDE"]</summary><p>
-
-  * [ ] [`_mm_aesdecwide128kl_u8`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_aesdecwide128kl_u8)
-  * [ ] [`_mm_aesdecwide256kl_u8`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_aesdecwide256kl_u8)
-  * [ ] [`_mm_aesencwide128kl_u8`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_aesencwide128kl_u8)
-  * [ ] [`_mm_aesencwide256kl_u8`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_aesencwide256kl_u8)
-</p></details>
-
-
 <details><summary>["MONITOR"]</summary><p>
 
   * [ ] [`_mm_monitor`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_monitor)

crates/core_arch/src/lib.rs

@@ -38,7 +38,8 @@
     asm_experimental_arch,
     sha512_sm_x86,
     x86_amx_intrinsics,
-    f16
+    f16,
+    keylocker_x86
 )]
 #![cfg_attr(test, feature(test, abi_vectorcall, stdarch_internal))]
 #![deny(clippy::missing_inline_in_public_items)]

crates/core_arch/src/x86/kl.rs

@@ -750,3 +750,7 @@ pub use self::avxneconvert::*;
 mod avx512fp16;
 #[unstable(feature = "stdarch_x86_avx512_f16", issue = "127213")]
 pub use self::avx512fp16::*;
+
+mod kl;
+#[unstable(feature = "keylocker_x86", issue = "134813")]
+pub use self::kl::*;

crates/core_arch/src/x86/mod.rs

@@ -185,7 +185,12 @@ fn parse(output: &str) -> HashSet<Function> {
                     _ => {}
                 };
             }
+
             instructions.push(parts.join(" "));
+            if matches!(&**instructions.last().unwrap(), "ret" | "retq") {
+                cached_header = None;
+                break;
+            }
         }
         let function = Function {
             name: symbol,

crates/stdarch-test/src/disassembly.rs

@@ -119,6 +119,9 @@ pub fn assert(shim_addr: usize, fnname: &str, expected: &str) {
                 // it from the slightly more restrictive 22 instructions below.
                 "cpuid" => 30,
 
+                // These require 8 loads and stores, so it _just_ overflows the limit
+                "aesencwide128kl" | "aesencwide256kl" | "aesdecwide128kl" | "aesdecwide256kl" => 24,
+
                 // Apparently, on Windows, LLVM generates a bunch of
                 // saves/restores of xmm registers around these instructions,
                 // which exceeds the limit of 20 below. As it seems dictated by

crates/stdarch-test/src/lib.rs

@@ -201,6 +201,7 @@ fn verify_all_signatures() {
                 "_xrstors",
                 "_xsaves64",
                 "_xrstors64",
+                "_mm_loadiwkey",
                 // RDRAND
                 "_rdrand16_step",
                 "_rdrand32_step",
@@ -448,6 +449,8 @@ fn check_target_features(rust: &Function, intel: &Intrinsic) -> Result<(), Strin
             // it "avx512ifma".
             "avx512ifma52" => String::from("avx512ifma"),
             "xss" => String::from("xsaves"),
+            "keylocker" => String::from("kl"),
+            "keylockerwide" => String::from("widekl"),
             _ => cpuid,
         };