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Title: Introducing the feature target for the Intel avx512 instruction set
Type: technical
Summary
MCP#778 proposes to add a target feature to support only the 256-bit instructions of the new Intel avx512 instruction set.
From the MCP: LLVM uses the evex512 feature flag to differentiate between avx512-avx10.N-512 and avx10.N-256. Due to rust#121088, the avx512 target features auto-enable evex512, making it impossible for Rust to use avx10.N-256.
The proponent of the MCP suggest two ways to proceed:
evex512 approach: just designates the target feature a single target feature (evex512) for 512-bit vectors - if a function uses 512-bit vectors, it must have this target feature enabled. Mirrors LLVM's solution so preserves LLVM parity features and introduces just 1 new target feature
avx256 approach: add 14 (possibly more) target features for each corresponding avx512* target feature. Only allows operations on vectors of up to 256-bits and none of the avx512f. Creates a de facto parallel ISA system to the existing AVX512 system, but for 256-bit system. This is completely backward-compatible, and preserves the association of CPU features and Rust features.
The meeting should evaluate pro and cons of both solution and decide
which approach we prefer. Given the impacyt of this change, should also
decide if an RFC is needed (RFC is drafted on that HackMD document).
This issue corresponds to a meeting proposal for the compiler team steering meeting. It corresponds to a possible topic of
discussion. You can read more about the steering meeting procedure
here.
Comment policy
These issues are meant to be used as an "announcements channel"
regarding the proposal, and not as a place to discuss the technical
details. Feel free to subscribe to updates. We'll post comments when
reviewing the proposal in meetings or making a scheduling decision.
In the meantime, if you have questions or ideas, ping the proposers
on Zulip (or elsewhere).
The text was updated successfully, but these errors were encountered:
Meeting proposal info
Summary
MCP#778 proposes to add a target feature to support only the 256-bit instructions of the new Intel avx512 instruction set.
From the MCP: LLVM uses the
evex512
feature flag to differentiate betweenavx512-avx10.N-512
andavx10.N-256
. Due to rust#121088, the avx512 target features auto-enableevex512
, making it impossible for Rust to useavx10.N-256
.The proponent of the MCP suggest two ways to proceed:
evex512
approach: just designates the target feature a single target feature (evex512
) for 512-bit vectors - if a function uses 512-bit vectors, it must have this target feature enabled. Mirrors LLVM's solution so preserves LLVM parity features and introduces just 1 new target featureavx256
approach: add 14 (possibly more) target features for each correspondingavx512*
target feature. Only allows operations on vectors of up to 256-bits and none of theavx512f
. Creates a de facto parallel ISA system to the existing AVX512 system, but for 256-bit system. This is completely backward-compatible, and preserves the association of CPU features and Rust features.More at the HackMD authored by the MCP author.
About this issue
The meeting should evaluate pro and cons of both solution and decide
which approach we prefer. Given the impacyt of this change, should also
decide if an RFC is needed (RFC is drafted on that HackMD document).
This issue corresponds to a meeting proposal for the compiler team
steering meeting. It corresponds to a possible topic of
discussion. You can read more about the steering meeting procedure
here.
Comment policy
These issues are meant to be used as an "announcements channel"
regarding the proposal, and not as a place to discuss the technical
details. Feel free to subscribe to updates. We'll post comments when
reviewing the proposal in meetings or making a scheduling decision.
In the meantime, if you have questions or ideas, ping the proposers
on Zulip (or elsewhere).
The text was updated successfully, but these errors were encountered: