ari_asm_mips64.d: translate comments, convert to /**/

Author: rurban

src/ari_asm_mips64.d

@@ -1,22 +1,23 @@
-# Externe Routinen zu ARILEV1.D
-# Prozessor: MIPS 64-bit
-# Endianness: irrelevant
-# Compiler: GNU-C oder ...
-# Parameter passing conventions:
-#   Arguments:
-#     in registers $4,$5,$6,$7,$8,$9,$10,$11, and on the stack
-#   Return value register:
-#     $2
-#   Call-used registers (do not have to be preserved across function calls):
-#     $2..$15, $24
-# Settings: intCsize=32, intDsize=32.
-# Particularities:
-#   After every load instruction a wait cycle is necessary, before the
-#   fetched values may be used.
-#   After branches and jumps, there is a delay slot. The assembler fills
-#   it by pulling some instruction from before the jump (unless we use
-#   the pseudo-op '.set noreorder' to disable this instruction reordering).
-
+/* -*- asm -*-
+ * External routines for arilev1.d
+ * Prozessor: MIPS 64-bit
+ * Endianness: irrelevant
+ * Compiler: GNU-C oder ...
+ * Parameter passing conventions:
+ *   Arguments:
+ *     in registers $4,$5,$6,$7,$8,$9,$10,$11, and on the stack
+ *   Return value register:
+ *     $2
+ *   Call-used registers (do not have to be preserved across function calls):
+ *     $2..$15, $24
+ * Settings: intCsize=32, intDsize=32.
+ * Particularities:
+ *   After every load instruction a wait cycle is necessary, before the
+ *   fetched values may be used.
+ *   After branches and jumps, there is a delay slot. The assembler fills
+ *   it by pulling some instruction from before the jump (unless we use
+ *   the pseudo-op '.set noreorder' to disable this instruction reordering).
+ */
 #ifdef INCLUDED_FROM_C
 
   #define COPY_LOOPS