RTIC on RISC-V - roadmap / tasks

[mchodzikiewicz]

Hi everyone!

I think it would be great to port RTIC to RISC-V, especially that core is already separated from cortex-m code and RISC-V is going more and more mainstream.

Each and everyday RISC-V gets more adoption on the silicon market. Notably, Espressif have launched its ESP32-C3 chip that is RISC-V based, which is an easy enabler for Rust embedded WiFi applications. It might also expose huge ESP32 maker community to Rust.

Main obstacle for wide Rust adoption on ESP32 was lack of support in upstream LLVM for xtensa-lx arch which is not the case with RISC-V.

I guess everything else is more or less in place, like embedded-hal implementation and experimental WiFi library (see esp-rs) It needs further investingation but I expect peripherals to be very similar as in xtensa-lx version of the chip.

I would love to contribute along the way there but I am not at the position where I'd be able to make it entirely on my own since I have very limited skill set beside couple of years of general embedded dev experience and small RTIC experience from end user perspective.

I think plenty of users are very eager to make this happen, so perhaps spending an effort on providing a roadmap along with set of tasks small enough to play with it as small side projects would make this happen.

[AfoHT]

There has been some prior work done but I haven't investigated thoroughly:

https://github.com/japaric/hifive1/tree/master/rtfm

https://github.com/riscv-rust/riscv-rtfm/tree/633d6427f2b91ab687095f5e2d0aedd6ff289fa4

With these as a potential starting point to study how the hardware interface differs from cortex-m-rtfm (maybe easier if comparing with the contemporary RTFM available back then)

In the past 2 years since these saw any updates RTFM/RTIC has changed a bit, so I would imagine taking current day cortex-m-rtic and modifying it to become riscv-rtic seems a preferable approach.

I agree with you that RTIC on RISC-V would be very nice, hopefully we can make that happen!