makefile.common

OBJ     =$(SRC:.c=.o) # replaces the .c from SRC with .o
DEPS    =$(SRC:.c=.d) # replaces the .c from SRC with .d

%.o: %.c         # combined w/ next line will compile recently changed .c files
	$(ECHO) Compiling $(notdir $<) ...
	$(DEBUG)$(CC) $(CFLAGS) -o $@ -c $<

.PHONY : all     # .PHONY ignores files named all
all: $(SUBDIRS) $(EXE)$ $(LIB)   # all is dependent on $(EXE) to be complete

.PHONY : $(SUBDIRS)
$(SUBDIRS):
	$(MAKE) -C $@ $(TARGET)

$(LIB): $(OBJ)
	$(ECHO) Archiving $@ ...
	$(DEBUG)$(AR) $@ $(OBJ)
	$(ECHO) Done

$(EXE): $(OBJ)   # $(EXE) is dependent on all of the files in $(OBJ) to exist
	$(ECHO) Linking $@ ...
	$(DEBUG)$(CC) $(OBJ) $(LDFLAGS) $(addprefix -l,$(LIBS)) -o $@
	$(ECHO) Done

.PHONY : clean   # .PHONY ignores files named clean

clean:	TARGET := clean
clean:	$(SUBDIRS)
	$(ECHO) Deleting $(OBJ) $(DEPS) $(LIB) $(EXE) ...
	$(DEBUG)-$(RM) $(OBJ) $(DEPS) $(LIB) $(EXE)

.PHONY: force
.compiler_flags: force
	@echo '$(CDEFS)' | cmp -s - $@ || echo '$(CDEFS)' > $@

$(OBJ): .compiler_flags

-include $(DEPS)