From 1a9ac88d8e6ed34a733a663523a327a2f94ef55b Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Rom=C3=A1n=20C=C3=A1rdenas?= Date: Tue, 31 Oct 2023 17:00:54 +0100 Subject: [PATCH] force-amo --- .github/workflows/ci.yaml | 4 ++-- .vscode/settings.json | 4 ---- CHANGELOG.md | 5 ++++- Cargo.toml | 6 +++--- README.md | 2 +- 5 files changed, 10 insertions(+), 11 deletions(-) diff --git a/.github/workflows/ci.yaml b/.github/workflows/ci.yaml index 432c595..ce4ca01 100644 --- a/.github/workflows/ci.yaml +++ b/.github/workflows/ci.yaml @@ -11,8 +11,8 @@ jobs: continue-on-error: ${{ matrix.experimental || false }} strategy: matrix: - # All generated code should be running on stable now, MRSV is 1.60.0 - rust: [nightly, stable, 1.60.0] + # All generated code should be running on stable now, MRSV is 1.72.0 + rust: [nightly, stable, 1.72.0] include: # Nightly is only for reference and allowed to fail diff --git a/.vscode/settings.json b/.vscode/settings.json index 2781fab..a742e3e 100644 --- a/.vscode/settings.json +++ b/.vscode/settings.json @@ -1,8 +1,4 @@ { - "[rust]": { - "editor.defaultFormatter": "rust-lang.rust-analyzer", - "editor.formatOnSave": true - }, "rust-analyzer.cargo.features": [ "g002", "virq", diff --git a/CHANGELOG.md b/CHANGELOG.md index aa47fb6..2e86866 100644 --- a/CHANGELOG.md +++ b/CHANGELOG.md @@ -7,7 +7,10 @@ and this project adheres to [Semantic Versioning](http://semver.org/). ## [Unreleased] -- Use `portable-atomic` to allow builds on `riscv32imc-unknown-none-elf`` targets when needed. +### Changed +- Use `portable-atomic` to allow builds on `riscv32imc-unknown-none-elf` targets when needed. +- Use `force-amo` on `portable-atomic` to use AMO instructions even when compiling for `riscv32imc-unknown-none-elf`. +- Bump MSRV to 1.72 due to `force-amo` on `portable-atomic`. ## [v0.10.0] - 2023-03-28 diff --git a/Cargo.toml b/Cargo.toml index ca7141c..58e53b0 100644 --- a/Cargo.toml +++ b/Cargo.toml @@ -7,8 +7,8 @@ categories = ["embedded", "hardware-support", "no-std"] description = "HAL for the E310x family of microcontrollers." keywords = ["riscv", "e310", "hal"] license = "ISC" -edition = "2018" -rust-version = "1.59" +edition = "2021" +rust-version = "1.72" [dependencies] embedded-hal = { version = "0.2.6", features = ["unproven"] } @@ -17,7 +17,7 @@ riscv = { version = "0.10.1", features = ["critical-section-single-hart"] } e310x = { version = "0.11.0", features = ["rt", "critical-section"] } [target.'cfg(not(target_has_atomic = "32"))'.dependencies] -portable-atomic = { version = "1.4", default-features = false, features = ["unsafe-assume-single-core"] } +portable-atomic = { version = "1.5", default-features = false, features = ["unsafe-assume-single-core", "force-amo"] } [features] g002 = ["e310x/g002"] diff --git a/README.md b/README.md index fe081e8..a3f65bb 100644 --- a/README.md +++ b/README.md @@ -12,7 +12,7 @@ This project is developed and maintained by the [RISC-V team][team]. ## Minimum Supported Rust Version (MSRV) -This crate is guaranteed to compile on stable Rust 1.60.0 and up. It *might* +This crate is guaranteed to compile on stable Rust 1.72.0 and up. It *might* compile with older versions but that may change in any new patch release. ## License