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Hi,
I am running make clean simulate verify postverify XLEN=32 RISCV_DEVICE=Vb with riscv-toolchains-rvv-0.9.x and hitting following error:
make clean simulate verify postverify XLEN=32 RISCV_DEVICE=Vb
make[1]: *** [Makefile:5: /home/*/*/imperas-riscv-tests/work/rv32i_m/Vb/VSETIVLI-SEW16_LMUL2.elf] Error 1 src/VSETIVLI-SEW16_LMUL4.S: Assembler messages: src/VSETIVLI-SEW16_LMUL4.S:83: Error: unrecognized opcode `vsetivli x1,23,e16,m4' src/VSETIVLI-SEW16_LMUL4.S:211: Error: unrecognized opcode `vsetivli x2,16,e16,m4' src/VSETIVLI-SEW16_LMUL4.S:339: Error: unrecognized opcode `vsetivli x3,10,e16,m4'
Do I need to set a different toolchain to fix this error?
The text was updated successfully, but these errors were encountered:
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Hi,
I am running
make clean simulate verify postverify XLEN=32 RISCV_DEVICE=Vb
with riscv-toolchains-rvv-0.9.x and hitting following error:Do I need to set a different toolchain to fix this error?
The text was updated successfully, but these errors were encountered: