RV32I Base Integer Instruction Set, Version 2.1
This directory contains information on an Imperas test suite. The focus of these tests is to check the device under test complies with the RISC-V specifications.
If the test directory has -RVI in its name, then these test are from the RISC-V International compliance working group and Imperas have included them in these suites to make use of the ease-of-use of the Imperas make/bash test framework.
If the test directory does not have -RVI in its name, then the tests have been generated by the Imperas directed test generator. At the top of each test source file is listed the specification version and configuration options used.
The signature files have been created by the Imperas golden reference RISC-V envelope model.
test_suite_details.txt provides instruction counts.
test_suite_sizes.txt has information about each test in the suite.
basic.coverage.txt shows functional coverage data.
extended.coverage.txt includes extended functional coverage detail.
The coverage data is collected and reported by functionality included in riscvOVPsim.
Depending where you are viewing this file you might see some other directories/files: The src and reference directories are the test suites and their reference. The 'src' directory contains all the .S assembler files of the tests. The 'reference' directory contains the reference signatures for the tests.
On github you will find only the RV32I tests. All the other open source freely available suites are can be found on OVPworld. To obtain the download package for those configured testsuites, get the download package from: www.OVPworld.org.
If you need vector tests and your device is a different configuration of vector engine, please contact Imperas ([email protected]) to obtain a test suite configured for your specific device.
If the suite is only commercially available (for example for the Vector instructions and PMP privilege ISA tests) please contact Imperas.