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target/riscv: set appropriate memory access result codes #1224

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merged 1 commit into from
Feb 26, 2025

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@fk-sc fk-sc commented Feb 7, 2025

Set appropriate memory access result codes

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fk-sc commented Feb 7, 2025

This PR contains 3 commits because it requires #1194 and #1218 to be merged. After merge I'll leave only last commit here

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fk-sc commented Feb 7, 2025

@JanMatCodasip, @MarekVCodasip, can you please take a look after #1194 and #1218 merge?

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MarekVCodasip previously approved these changes Feb 17, 2025
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LGTM

en-sc
en-sc previously approved these changes Feb 21, 2025
@fk-sc fk-sc dismissed en-sc’s stale review February 21, 2025 10:42

The merge-base changed after approval.

Set appropriate memory access result codes

Checkpatch-ignore: MACRO_ARG_PRECEDENCE, MULTISTATEMENT_MACRO_USE_DO_WHILE
Checkpatch-ignore: TRAILING_SEMICOLON
Change-Id: Ib73b5a041e5f15aef150b80fdd45f107de19d3a6
Signed-off-by: Farid Khaydari <[email protected]>
@en-sc en-sc merged commit 7335759 into riscv-collab:riscv Feb 26, 2025
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3 participants