From fbb102e5190eea300951e5de2f9842b2092808e0 Mon Sep 17 00:00:00 2001 From: Jan Matyas Date: Tue, 7 Jan 2025 15:10:04 +0100 Subject: [PATCH] Semihosting 2 of 3: Cosmetic improvements Cosmetic, non-functional improvements in `riscv_semihosting_detect_magic_sequence()`. Change-Id: I935d3847749a02e4f579900a0971c30a5cc826b7 Signed-off-by: Jan Matyas --- src/target/riscv/riscv_semihosting.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/src/target/riscv/riscv_semihosting.c b/src/target/riscv/riscv_semihosting.c index 656ba7ea3..5bb3c618c 100644 --- a/src/target/riscv/riscv_semihosting.c +++ b/src/target/riscv/riscv_semihosting.c @@ -53,12 +53,13 @@ static int riscv_semihosting_detect_magic_sequence(struct target *target, /* Read three uncompressed instructions: * The previous, the current one (pointed to by PC) and the next one. */ + const target_addr_t sequence_start_address = pc - 4; for (int i = 0; i < 3; i++) { uint8_t buf[4]; /* Instruction memories may not support arbitrary read size. * Use any size that will work. */ - const target_addr_t address = (pc - 4) + 4 * i; + const target_addr_t address = sequence_start_address + (4 * i); int result = riscv_read_by_any_size(target, address, 4, buf); if (result != ERROR_OK) { *sequence_found = false; @@ -67,7 +68,7 @@ static int riscv_semihosting_detect_magic_sequence(struct target *target, const uint32_t value = target_buffer_get_u32(target, buf); - LOG_TARGET_DEBUG(target, "compare 0x%08x from 0x%" PRIx64 " against 0x%08x", + LOG_TARGET_DEBUG(target, "compare 0x%08" PRIx32 " from 0x%" PRIx64 " against 0x%08" PRIx32, value, address, magic[i]); if (value != magic[i]) { LOG_TARGET_DEBUG(target, "Not a RISC-V semihosting sequence");