From 94d739ac9a85b8fc13e11510d98615dbfee11b42 Mon Sep 17 00:00:00 2001 From: Samuel Obuch Date: Mon, 27 Jan 2025 17:52:08 +0100 Subject: [PATCH] target/riscv: dont set mcause and mstatus as cachable With CLIC extension (smclic), mcause and mstatus CSRs share mirrored fields for mpp and mpie. Therefore, neither can be assumed cachable. Signed-off-by: Samuel Obuch --- src/target/riscv/riscv_reg_impl.h | 2 -- 1 file changed, 2 deletions(-) diff --git a/src/target/riscv/riscv_reg_impl.h b/src/target/riscv/riscv_reg_impl.h index 7a483adc2..a86020252 100644 --- a/src/target/riscv/riscv_reg_impl.h +++ b/src/target/riscv/riscv_reg_impl.h @@ -204,9 +204,7 @@ static inline bool riscv_reg_impl_gdb_regno_cacheable(enum gdb_regno regno, case GDB_REGNO_MISA: case GDB_REGNO_DCSR: case GDB_REGNO_DSCRATCH0: - case GDB_REGNO_MSTATUS: case GDB_REGNO_MEPC: - case GDB_REGNO_MCAUSE: case GDB_REGNO_SATP: /* * WARL registers might not contain the value we just wrote, but