34-bit memory read/write support？

[KotorinMinami]

The current Sail-RISCV model uses the Sail model from currency_interface in the Sail lib. interface), which only supports 32-bit and 64-bit memory reads and writes.

However, it is mentioned in the RISCV spec that in RV32, the physical memory has 34 bits, so is it possible to include support for 34-bit memory reads and writes?

[Alasdair]

We actually support arbitrary PA types, the requirement is you have to be able to map those types into either 64 or 32 bits. When you instantiate the memory events you provide a pa_bits function that takes whatever physical address type the model has, and converts it to either 64 or 32 bits. For 34 bits, you can just zero-extend up to 64.

I think right now the pa_bits function in the sail-riscv model is just the identity function, but if you change that it should work.