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Cheri.thy
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chapter \<open>Generated by Lem from \<open>cheri.lem\<close>.\<close>
theory "Cheri"
imports
Main
"LEM.Lem_pervasives_extra"
"Sail.Sail2_instr_kinds"
"Sail.Sail2_values"
"Sail.Sail2_string"
"Sail.Sail2_operators_mwords"
"Sail.Sail2_prompt_monad"
"Sail.Sail2_prompt"
"Cheri_types"
"Mips_extras"
begin
(*Generated by Sail from cheri.*)
(*open import Pervasives_extra*)
(*open import Sail2_instr_kinds*)
(*open import Sail2_values*)
(*open import Sail2_string*)
(*open import Sail2_operators_mwords*)
(*open import Sail2_prompt_monad*)
(*open import Sail2_prompt*)
(*open import Cheri_types*)
(*open import Mips_extras*)
definition cap_size :: " int " where
" cap_size = ( (( 32 :: int)::ii))"
(*val eq_unit : unit -> unit -> bool*)
definition eq_unit :: " unit \<Rightarrow> unit \<Rightarrow> bool " where
" eq_unit g__20 g__21 = ( True )"
(*val neq_bool : bool -> bool -> bool*)
definition neq_bool :: " bool \<Rightarrow> bool \<Rightarrow> bool " where
" neq_bool x y = ( \<not> (((x = y))))"
(*val undefined_option : forall 'a. 'a -> M (maybe 'a)*)
definition undefined_option :: " 'a \<Rightarrow>((register_value),('a option),(exception))monad " where
" undefined_option typ_a = (
undefined_unit () \<bind> (\<lambda> (u_0 :: unit) .
(let u_1 = typ_a in
internal_pick [Some u_1,None])))"
(*val is_none : forall 'a. maybe 'a -> bool*)
fun is_none :: " 'a option \<Rightarrow> bool " where
" is_none (Some (_)) = ( False )"
|" is_none None = ( True )"
(*val is_some : forall 'a. maybe 'a -> bool*)
fun is_some :: " 'a option \<Rightarrow> bool " where
" is_some (Some (_)) = ( True )"
|" is_some None = ( False )"
(*val sail_mask : forall 'len 'v . Size 'len, Size 'v => itself 'len -> mword 'v -> mword 'len*)
definition sail_mask :: "('len::len)itself \<Rightarrow>('v::len)Word.word \<Rightarrow>('len::len)Word.word " where
" sail_mask len v = (
(let len = (size_itself_int len) in
if ((len \<le> ((int (size v))))) then (vector_truncate v len :: ( 'len::len)Word.word)
else (zero_extend v len :: ( 'len::len)Word.word)))"
(*val cast_unit_vec : bitU -> mword ty1*)
fun cast_unit_vec0 :: " bitU \<Rightarrow>(1)Word.word " where
" cast_unit_vec0 B0 = ( (vec_of_bits [B0] :: 1 Word.word))"
|" cast_unit_vec0 _ = ( (vec_of_bits [B1] :: 1 Word.word))"
(*val __MIPS_write : forall 'p8_times_n_ . Size 'p8_times_n_ => mword ty64 -> integer -> mword 'p8_times_n_ -> M unit*)
definition MIPS_write :: "(64)Word.word \<Rightarrow> int \<Rightarrow>('p8_times_n_::len)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where
" MIPS_write addr width data = (
write_ram instance_Sail2_values_Bitvector_Machine_word_mword_dict instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 64 :: int)::ii) width
(vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
B0,B0,B0,B0,B0,B0,B0,B0,B0,B0]
:: 64 Word.word) addr data \<then>
return () )"
(*val __MIPS_read : forall 'p8_times_n_ . Size 'p8_times_n_ => mword ty64 -> integer -> M (mword 'p8_times_n_)*)
definition MIPS_read :: "(64)Word.word \<Rightarrow> int \<Rightarrow>((register_value),(('p8_times_n_::len)Word.word),(exception))monad " where
" MIPS_read addr width = (
(read_ram instance_Sail2_values_Bitvector_Machine_word_mword_dict instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 64 :: int)::ii) width
(vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
B0,B0,B0,B0,B0,B0,B0,B0,B0,B0]
:: 64 Word.word) addr
:: (( 'p8_times_n_::len)Word.word) M))"
(*val undefined_exception : unit -> M exception*)
definition undefined_exception :: " unit \<Rightarrow>((register_value),(exception),(exception))monad " where
" undefined_exception _ = (
undefined_string () \<bind> (\<lambda> (u_0 :: string) .
undefined_unit () \<bind> (\<lambda> (u_1 :: unit) .
internal_pick
[ISAException u_1,Error_not_implemented u_0,Error_misaligned_access u_1,Error_EBREAK u_1,Error_internal_error u_1])))"
(*val mips_sign_extend : forall 'n 'm . Size 'm, Size 'n => integer -> mword 'n -> mword 'm*)
(*val mips_zero_extend : forall 'n 'm . Size 'm, Size 'n => integer -> mword 'n -> mword 'm*)
definition mips_sign_extend :: " int \<Rightarrow>('n::len)Word.word \<Rightarrow>('m::len)Word.word " where
" mips_sign_extend (m__tv :: int) v = ( (sign_extend v m__tv :: ( 'm::len)Word.word))"
definition mips_zero_extend :: " int \<Rightarrow>('n::len)Word.word \<Rightarrow>('m::len)Word.word " where
" mips_zero_extend (m__tv :: int) v = ( (zero_extend v m__tv :: ( 'm::len)Word.word))"
(*val zeros : forall 'n . Size 'n => integer -> unit -> mword 'n*)
definition zeros0 :: " int \<Rightarrow> unit \<Rightarrow>('n::len)Word.word " where
" zeros0 (n__tv :: int) _ = ( (replicate_bits (vec_of_bits [B0] :: 1 Word.word) n__tv :: ( 'n::len)Word.word))"
(*val ones : forall 'n . Size 'n => integer -> unit -> mword 'n*)
definition ones :: " int \<Rightarrow> unit \<Rightarrow>('n::len)Word.word " where
" ones (n__tv :: int) _ = ( (replicate_bits (vec_of_bits [B1] :: 1 Word.word) n__tv :: ( 'n::len)Word.word))"
(*val zopz0zI_s : forall 'n . Size 'n => mword 'n -> mword 'n -> bool*)
(*val zopz0zKzJ_s : forall 'n . Size 'n => mword 'n -> mword 'n -> bool*)
(*val zopz0zI_u : forall 'n . Size 'n => mword 'n -> mword 'n -> bool*)
(*val zopz0zKzJ_u : forall 'n . Size 'n => mword 'n -> mword 'n -> bool*)
definition zopz0zI_s :: "('n::len)Word.word \<Rightarrow>('n::len)Word.word \<Rightarrow> bool " where
" zopz0zI_s x y = ( ((Word.sint x)) < ((Word.sint y)))"
definition zopz0zKzJ_s :: "('n::len)Word.word \<Rightarrow>('n::len)Word.word \<Rightarrow> bool " where
" zopz0zKzJ_s x y = ( ((Word.sint x)) \<ge> ((Word.sint y)))"
definition zopz0zI_u :: "('n::len)Word.word \<Rightarrow>('n::len)Word.word \<Rightarrow> bool " where
" zopz0zI_u x y = ( ((Word.uint x)) < ((Word.uint y)))"
definition zopz0zKzJ_u :: "('n::len)Word.word \<Rightarrow>('n::len)Word.word \<Rightarrow> bool " where
" zopz0zKzJ_u x y = ( ((Word.uint x)) \<ge> ((Word.uint y)))"
(*val bool_to_bits : bool -> mword ty1*)
definition bool_to_bits :: " bool \<Rightarrow>(1)Word.word " where
" bool_to_bits x = ( if x then (vec_of_bits [B1] :: 1 Word.word) else (vec_of_bits [B0] :: 1 Word.word))"
(*val bit_to_bool : bitU -> bool*)
fun bit_to_bool :: " bitU \<Rightarrow> bool " where
" bit_to_bool B1 = ( True )"
|" bit_to_bool _ = ( False )"
(*val bits_to_bool : mword ty1 -> bool*)
definition bits_to_bool :: "(1)Word.word \<Rightarrow> bool " where
" bits_to_bool x = ( bit_to_bool ((access_vec_dec x (( 0 :: int)::ii))))"
(*
function{to_bits} converts an integer to a bit vector of given length. If the integer is negative a twos-complement representation is used. If the integer is too large (or too negative) to fit in the requested length then it is truncated to the least significant bits.
*)
(*val to_bits : forall 'l . Size 'l => itself 'l -> ii -> mword 'l*)
definition to_bits :: "('l::len)itself \<Rightarrow> int \<Rightarrow>('l::len)Word.word " where
" to_bits l n = (
(let l = (size_itself_int l) in
(get_slice_int0 instance_Sail2_values_Bitvector_Machine_word_mword_dict l n (( 0 :: int)::ii) :: ( 'l::len)Word.word)))"
(*val mask : forall 'm 'n . Size 'm, Size 'n => integer -> mword 'm -> mword 'n*)
definition mask0 :: " int \<Rightarrow>('m::len)Word.word \<Rightarrow>('n::len)Word.word " where
" mask0 (n__tv :: int) bs = (
(subrange_vec_dec bs ((n__tv - (( 1 :: int)::ii))) (( 0 :: int)::ii) :: ( 'n::len)Word.word))"
(*val undefined_CauseReg : unit -> M CauseReg*)
definition undefined_CauseReg :: " unit \<Rightarrow>((register_value),(CauseReg),(exception))monad " where
" undefined_CauseReg _ = (
(undefined_bitvector
instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 32 :: int)::ii) :: ( 32 Word.word) M) \<bind> (\<lambda> (w__0 :: 32 Word.word) .
return ((| CauseReg_CauseReg_chunk_0 = w__0 |))))"
(*val Mk_CauseReg : mword ty32 -> CauseReg*)
definition Mk_CauseReg :: "(32)Word.word \<Rightarrow> CauseReg " where
" Mk_CauseReg v = (
(| CauseReg_CauseReg_chunk_0 = ((subrange_vec_dec v (( 31 :: int)::ii) (( 0 :: int)::ii) :: 32 Word.word)) |) )"
(*val _get_CauseReg_bits : CauseReg -> mword ty32*)
definition get_CauseReg_bits :: " CauseReg \<Rightarrow>(32)Word.word " where
" get_CauseReg_bits v = (
(subrange_vec_dec(CauseReg_CauseReg_chunk_0 v) (( 31 :: int)::ii) (( 0 :: int)::ii) :: 32 Word.word))"
(*val _set_CauseReg_bits : register_ref regstate register_value CauseReg -> mword ty32 -> M unit*)
definition set_CauseReg_bits :: "((regstate),(register_value),(CauseReg))register_ref \<Rightarrow>(32)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where
" set_CauseReg_bits r_ref v = (
reg_deref r_ref \<bind> (\<lambda> r .
(let r =
((r (|
CauseReg_CauseReg_chunk_0 :=
((update_subrange_vec_dec(CauseReg_CauseReg_chunk_0 r) (( 31 :: int)::ii) (( 0 :: int)::ii)
((subrange_vec_dec v (( 31 :: int)::ii) (( 0 :: int)::ii) :: 32 Word.word))
:: 32 Word.word))|))) in
write_reg r_ref r)))"
(*val _update_CauseReg_bits : CauseReg -> mword ty32 -> CauseReg*)
definition update_CauseReg_bits :: " CauseReg \<Rightarrow>(32)Word.word \<Rightarrow> CauseReg " where
" update_CauseReg_bits v x = (
(v (|
CauseReg_CauseReg_chunk_0 :=
((update_subrange_vec_dec(CauseReg_CauseReg_chunk_0 v) (( 31 :: int)::ii) (( 0 :: int)::ii)
((subrange_vec_dec x (( 31 :: int)::ii) (( 0 :: int)::ii) :: 32 Word.word))
:: 32 Word.word))|)))"
(*val _update_CapCauseReg_bits : CapCauseReg -> mword ty16 -> CapCauseReg*)
(*val _get_CapCauseReg_bits : CapCauseReg -> mword ty16*)
(*val _set_CapCauseReg_bits : register_ref regstate register_value CapCauseReg -> mword ty16 -> M unit*)
(*val _get_CauseReg_BD : CauseReg -> mword ty1*)
definition get_CauseReg_BD :: " CauseReg \<Rightarrow>(1)Word.word " where
" get_CauseReg_BD v = ( (subrange_vec_dec(CauseReg_CauseReg_chunk_0 v) (( 31 :: int)::ii) (( 31 :: int)::ii) :: 1 Word.word))"
(*val _set_CauseReg_BD : register_ref regstate register_value CauseReg -> mword ty1 -> M unit*)
definition set_CauseReg_BD :: "((regstate),(register_value),(CauseReg))register_ref \<Rightarrow>(1)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where
" set_CauseReg_BD r_ref v = (
reg_deref r_ref \<bind> (\<lambda> r .
(let r =
((r (|
CauseReg_CauseReg_chunk_0 :=
((update_subrange_vec_dec(CauseReg_CauseReg_chunk_0 r) (( 31 :: int)::ii) (( 31 :: int)::ii)
((subrange_vec_dec v (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word))
:: 32 Word.word))|))) in
write_reg r_ref r)))"
(*val _update_CauseReg_BD : CauseReg -> mword ty1 -> CauseReg*)
definition update_CauseReg_BD :: " CauseReg \<Rightarrow>(1)Word.word \<Rightarrow> CauseReg " where
" update_CauseReg_BD v x = (
(v (|
CauseReg_CauseReg_chunk_0 :=
((update_subrange_vec_dec(CauseReg_CauseReg_chunk_0 v) (( 31 :: int)::ii) (( 31 :: int)::ii)
((subrange_vec_dec x (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word))
:: 32 Word.word))|)))"
(*val _get_CauseReg_CE : CauseReg -> mword ty2*)
definition get_CauseReg_CE :: " CauseReg \<Rightarrow>(2)Word.word " where
" get_CauseReg_CE v = ( (subrange_vec_dec(CauseReg_CauseReg_chunk_0 v) (( 29 :: int)::ii) (( 28 :: int)::ii) :: 2 Word.word))"
(*val _set_CauseReg_CE : register_ref regstate register_value CauseReg -> mword ty2 -> M unit*)
definition set_CauseReg_CE :: "((regstate),(register_value),(CauseReg))register_ref \<Rightarrow>(2)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where
" set_CauseReg_CE r_ref v = (
reg_deref r_ref \<bind> (\<lambda> r .
(let r =
((r (|
CauseReg_CauseReg_chunk_0 :=
((update_subrange_vec_dec(CauseReg_CauseReg_chunk_0 r) (( 29 :: int)::ii) (( 28 :: int)::ii)
((subrange_vec_dec v (( 1 :: int)::ii) (( 0 :: int)::ii) :: 2 Word.word))
:: 32 Word.word))|))) in
write_reg r_ref r)))"
(*val _update_CauseReg_CE : CauseReg -> mword ty2 -> CauseReg*)
definition update_CauseReg_CE :: " CauseReg \<Rightarrow>(2)Word.word \<Rightarrow> CauseReg " where
" update_CauseReg_CE v x = (
(v (|
CauseReg_CauseReg_chunk_0 :=
((update_subrange_vec_dec(CauseReg_CauseReg_chunk_0 v) (( 29 :: int)::ii) (( 28 :: int)::ii)
((subrange_vec_dec x (( 1 :: int)::ii) (( 0 :: int)::ii) :: 2 Word.word))
:: 32 Word.word))|)))"
(*val _get_CauseReg_IV : CauseReg -> mword ty1*)
definition get_CauseReg_IV :: " CauseReg \<Rightarrow>(1)Word.word " where
" get_CauseReg_IV v = ( (subrange_vec_dec(CauseReg_CauseReg_chunk_0 v) (( 23 :: int)::ii) (( 23 :: int)::ii) :: 1 Word.word))"
(*val _set_CauseReg_IV : register_ref regstate register_value CauseReg -> mword ty1 -> M unit*)
definition set_CauseReg_IV :: "((regstate),(register_value),(CauseReg))register_ref \<Rightarrow>(1)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where
" set_CauseReg_IV r_ref v = (
reg_deref r_ref \<bind> (\<lambda> r .
(let r =
((r (|
CauseReg_CauseReg_chunk_0 :=
((update_subrange_vec_dec(CauseReg_CauseReg_chunk_0 r) (( 23 :: int)::ii) (( 23 :: int)::ii)
((subrange_vec_dec v (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word))
:: 32 Word.word))|))) in
write_reg r_ref r)))"
(*val _update_CauseReg_IV : CauseReg -> mword ty1 -> CauseReg*)
definition update_CauseReg_IV :: " CauseReg \<Rightarrow>(1)Word.word \<Rightarrow> CauseReg " where
" update_CauseReg_IV v x = (
(v (|
CauseReg_CauseReg_chunk_0 :=
((update_subrange_vec_dec(CauseReg_CauseReg_chunk_0 v) (( 23 :: int)::ii) (( 23 :: int)::ii)
((subrange_vec_dec x (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word))
:: 32 Word.word))|)))"
(*val _get_CauseReg_WP : CauseReg -> mword ty1*)
definition get_CauseReg_WP :: " CauseReg \<Rightarrow>(1)Word.word " where
" get_CauseReg_WP v = ( (subrange_vec_dec(CauseReg_CauseReg_chunk_0 v) (( 22 :: int)::ii) (( 22 :: int)::ii) :: 1 Word.word))"
(*val _set_CauseReg_WP : register_ref regstate register_value CauseReg -> mword ty1 -> M unit*)
definition set_CauseReg_WP :: "((regstate),(register_value),(CauseReg))register_ref \<Rightarrow>(1)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where
" set_CauseReg_WP r_ref v = (
reg_deref r_ref \<bind> (\<lambda> r .
(let r =
((r (|
CauseReg_CauseReg_chunk_0 :=
((update_subrange_vec_dec(CauseReg_CauseReg_chunk_0 r) (( 22 :: int)::ii) (( 22 :: int)::ii)
((subrange_vec_dec v (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word))
:: 32 Word.word))|))) in
write_reg r_ref r)))"
(*val _update_CauseReg_WP : CauseReg -> mword ty1 -> CauseReg*)
definition update_CauseReg_WP :: " CauseReg \<Rightarrow>(1)Word.word \<Rightarrow> CauseReg " where
" update_CauseReg_WP v x = (
(v (|
CauseReg_CauseReg_chunk_0 :=
((update_subrange_vec_dec(CauseReg_CauseReg_chunk_0 v) (( 22 :: int)::ii) (( 22 :: int)::ii)
((subrange_vec_dec x (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word))
:: 32 Word.word))|)))"
(*val _get_CauseReg_IP : CauseReg -> mword ty8*)
definition get_CauseReg_IP :: " CauseReg \<Rightarrow>(8)Word.word " where
" get_CauseReg_IP v = ( (subrange_vec_dec(CauseReg_CauseReg_chunk_0 v) (( 15 :: int)::ii) (( 8 :: int)::ii) :: 8 Word.word))"
(*val _set_CauseReg_IP : register_ref regstate register_value CauseReg -> mword ty8 -> M unit*)
definition set_CauseReg_IP :: "((regstate),(register_value),(CauseReg))register_ref \<Rightarrow>(8)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where
" set_CauseReg_IP r_ref v = (
reg_deref r_ref \<bind> (\<lambda> r .
(let r =
((r (|
CauseReg_CauseReg_chunk_0 :=
((update_subrange_vec_dec(CauseReg_CauseReg_chunk_0 r) (( 15 :: int)::ii) (( 8 :: int)::ii)
((subrange_vec_dec v (( 7 :: int)::ii) (( 0 :: int)::ii) :: 8 Word.word))
:: 32 Word.word))|))) in
write_reg r_ref r)))"
(*val _update_CauseReg_IP : CauseReg -> mword ty8 -> CauseReg*)
definition update_CauseReg_IP :: " CauseReg \<Rightarrow>(8)Word.word \<Rightarrow> CauseReg " where
" update_CauseReg_IP v x = (
(v (|
CauseReg_CauseReg_chunk_0 :=
((update_subrange_vec_dec(CauseReg_CauseReg_chunk_0 v) (( 15 :: int)::ii) (( 8 :: int)::ii)
((subrange_vec_dec x (( 7 :: int)::ii) (( 0 :: int)::ii) :: 8 Word.word))
:: 32 Word.word))|)))"
(*val _get_CauseReg_ExcCode : CauseReg -> mword ty5*)
definition get_CauseReg_ExcCode :: " CauseReg \<Rightarrow>(5)Word.word " where
" get_CauseReg_ExcCode v = (
(subrange_vec_dec(CauseReg_CauseReg_chunk_0 v) (( 6 :: int)::ii) (( 2 :: int)::ii) :: 5 Word.word))"
(*val _set_CauseReg_ExcCode : register_ref regstate register_value CauseReg -> mword ty5 -> M unit*)
definition set_CauseReg_ExcCode :: "((regstate),(register_value),(CauseReg))register_ref \<Rightarrow>(5)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where
" set_CauseReg_ExcCode r_ref v = (
reg_deref r_ref \<bind> (\<lambda> r .
(let r =
((r (|
CauseReg_CauseReg_chunk_0 :=
((update_subrange_vec_dec(CauseReg_CauseReg_chunk_0 r) (( 6 :: int)::ii) (( 2 :: int)::ii)
((subrange_vec_dec v (( 4 :: int)::ii) (( 0 :: int)::ii) :: 5 Word.word))
:: 32 Word.word))|))) in
write_reg r_ref r)))"
(*val _update_CauseReg_ExcCode : CauseReg -> mword ty5 -> CauseReg*)
definition update_CauseReg_ExcCode :: " CauseReg \<Rightarrow>(5)Word.word \<Rightarrow> CauseReg " where
" update_CauseReg_ExcCode v x = (
(v (|
CauseReg_CauseReg_chunk_0 :=
((update_subrange_vec_dec(CauseReg_CauseReg_chunk_0 v) (( 6 :: int)::ii) (( 2 :: int)::ii)
((subrange_vec_dec x (( 4 :: int)::ii) (( 0 :: int)::ii) :: 5 Word.word))
:: 32 Word.word))|)))"
(*val _update_CapCauseReg_ExcCode : CapCauseReg -> mword ty8 -> CapCauseReg*)
(*val _get_CapCauseReg_ExcCode : CapCauseReg -> mword ty8*)
(*val _set_CapCauseReg_ExcCode : register_ref regstate register_value CapCauseReg -> mword ty8 -> M unit*)
(*val undefined_TLBEntryLoReg : unit -> M TLBEntryLoReg*)
definition undefined_TLBEntryLoReg :: " unit \<Rightarrow>((register_value),(TLBEntryLoReg),(exception))monad " where
" undefined_TLBEntryLoReg _ = (
(undefined_bitvector
instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 64 :: int)::ii) :: ( 64 Word.word) M) \<bind> (\<lambda> (w__0 :: 64 Word.word) .
return ((| TLBEntryLoReg_TLBEntryLoReg_chunk_0 = w__0 |))))"
(*val Mk_TLBEntryLoReg : mword ty64 -> TLBEntryLoReg*)
definition Mk_TLBEntryLoReg :: "(64)Word.word \<Rightarrow> TLBEntryLoReg " where
" Mk_TLBEntryLoReg v = (
(| TLBEntryLoReg_TLBEntryLoReg_chunk_0 = ((subrange_vec_dec v (( 63 :: int)::ii) (( 0 :: int)::ii) :: 64 Word.word)) |) )"
(*val _get_TLBEntryLoReg_bits : TLBEntryLoReg -> mword ty64*)
definition get_TLBEntryLoReg_bits :: " TLBEntryLoReg \<Rightarrow>(64)Word.word " where
" get_TLBEntryLoReg_bits v = (
(subrange_vec_dec(TLBEntryLoReg_TLBEntryLoReg_chunk_0 v) (( 63 :: int)::ii) (( 0 :: int)::ii) :: 64 Word.word))"
(*val _set_TLBEntryLoReg_bits : register_ref regstate register_value TLBEntryLoReg -> mword ty64 -> M unit*)
definition set_TLBEntryLoReg_bits :: "((regstate),(register_value),(TLBEntryLoReg))register_ref \<Rightarrow>(64)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where
" set_TLBEntryLoReg_bits r_ref v = (
reg_deref r_ref \<bind> (\<lambda> r .
(let r =
((r (|
TLBEntryLoReg_TLBEntryLoReg_chunk_0 :=
((update_subrange_vec_dec(TLBEntryLoReg_TLBEntryLoReg_chunk_0 r) (( 63 :: int)::ii) (( 0 :: int)::ii)
((subrange_vec_dec v (( 63 :: int)::ii) (( 0 :: int)::ii) :: 64 Word.word))
:: 64 Word.word))|))) in
write_reg r_ref r)))"
(*val _update_TLBEntryLoReg_bits : TLBEntryLoReg -> mword ty64 -> TLBEntryLoReg*)
definition update_TLBEntryLoReg_bits :: " TLBEntryLoReg \<Rightarrow>(64)Word.word \<Rightarrow> TLBEntryLoReg " where
" update_TLBEntryLoReg_bits v x = (
(v (|
TLBEntryLoReg_TLBEntryLoReg_chunk_0 :=
((update_subrange_vec_dec(TLBEntryLoReg_TLBEntryLoReg_chunk_0 v) (( 63 :: int)::ii) (( 0 :: int)::ii)
((subrange_vec_dec x (( 63 :: int)::ii) (( 0 :: int)::ii) :: 64 Word.word))
:: 64 Word.word))|)))"
(*val _get_TLBEntryLoReg_CapS : TLBEntryLoReg -> mword ty1*)
definition get_TLBEntryLoReg_CapS :: " TLBEntryLoReg \<Rightarrow>(1)Word.word " where
" get_TLBEntryLoReg_CapS v = (
(subrange_vec_dec(TLBEntryLoReg_TLBEntryLoReg_chunk_0 v) (( 63 :: int)::ii) (( 63 :: int)::ii) :: 1 Word.word))"
(*val _set_TLBEntryLoReg_CapS : register_ref regstate register_value TLBEntryLoReg -> mword ty1 -> M unit*)
definition set_TLBEntryLoReg_CapS :: "((regstate),(register_value),(TLBEntryLoReg))register_ref \<Rightarrow>(1)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where
" set_TLBEntryLoReg_CapS r_ref v = (
reg_deref r_ref \<bind> (\<lambda> r .
(let r =
((r (|
TLBEntryLoReg_TLBEntryLoReg_chunk_0 :=
((update_subrange_vec_dec(TLBEntryLoReg_TLBEntryLoReg_chunk_0 r) (( 63 :: int)::ii) (( 63 :: int)::ii)
((subrange_vec_dec v (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word))
:: 64 Word.word))|))) in
write_reg r_ref r)))"
(*val _update_TLBEntryLoReg_CapS : TLBEntryLoReg -> mword ty1 -> TLBEntryLoReg*)
definition update_TLBEntryLoReg_CapS :: " TLBEntryLoReg \<Rightarrow>(1)Word.word \<Rightarrow> TLBEntryLoReg " where
" update_TLBEntryLoReg_CapS v x = (
(v (|
TLBEntryLoReg_TLBEntryLoReg_chunk_0 :=
((update_subrange_vec_dec(TLBEntryLoReg_TLBEntryLoReg_chunk_0 v) (( 63 :: int)::ii) (( 63 :: int)::ii)
((subrange_vec_dec x (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word))
:: 64 Word.word))|)))"
(*val _get_TLBEntryLoReg_CapL : TLBEntryLoReg -> mword ty1*)
definition get_TLBEntryLoReg_CapL :: " TLBEntryLoReg \<Rightarrow>(1)Word.word " where
" get_TLBEntryLoReg_CapL v = (
(subrange_vec_dec(TLBEntryLoReg_TLBEntryLoReg_chunk_0 v) (( 62 :: int)::ii) (( 62 :: int)::ii) :: 1 Word.word))"
(*val _set_TLBEntryLoReg_CapL : register_ref regstate register_value TLBEntryLoReg -> mword ty1 -> M unit*)
definition set_TLBEntryLoReg_CapL :: "((regstate),(register_value),(TLBEntryLoReg))register_ref \<Rightarrow>(1)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where
" set_TLBEntryLoReg_CapL r_ref v = (
reg_deref r_ref \<bind> (\<lambda> r .
(let r =
((r (|
TLBEntryLoReg_TLBEntryLoReg_chunk_0 :=
((update_subrange_vec_dec(TLBEntryLoReg_TLBEntryLoReg_chunk_0 r) (( 62 :: int)::ii) (( 62 :: int)::ii)
((subrange_vec_dec v (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word))
:: 64 Word.word))|))) in
write_reg r_ref r)))"
(*val _update_TLBEntryLoReg_CapL : TLBEntryLoReg -> mword ty1 -> TLBEntryLoReg*)
definition update_TLBEntryLoReg_CapL :: " TLBEntryLoReg \<Rightarrow>(1)Word.word \<Rightarrow> TLBEntryLoReg " where
" update_TLBEntryLoReg_CapL v x = (
(v (|
TLBEntryLoReg_TLBEntryLoReg_chunk_0 :=
((update_subrange_vec_dec(TLBEntryLoReg_TLBEntryLoReg_chunk_0 v) (( 62 :: int)::ii) (( 62 :: int)::ii)
((subrange_vec_dec x (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word))
:: 64 Word.word))|)))"
(*val _get_TLBEntryLoReg_PFN : TLBEntryLoReg -> mword ty24*)
definition get_TLBEntryLoReg_PFN :: " TLBEntryLoReg \<Rightarrow>(24)Word.word " where
" get_TLBEntryLoReg_PFN v = (
(subrange_vec_dec(TLBEntryLoReg_TLBEntryLoReg_chunk_0 v) (( 29 :: int)::ii) (( 6 :: int)::ii) :: 24 Word.word))"
(*val _set_TLBEntryLoReg_PFN : register_ref regstate register_value TLBEntryLoReg -> mword ty24 -> M unit*)
definition set_TLBEntryLoReg_PFN :: "((regstate),(register_value),(TLBEntryLoReg))register_ref \<Rightarrow>(24)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where
" set_TLBEntryLoReg_PFN r_ref v = (
reg_deref r_ref \<bind> (\<lambda> r .
(let r =
((r (|
TLBEntryLoReg_TLBEntryLoReg_chunk_0 :=
((update_subrange_vec_dec(TLBEntryLoReg_TLBEntryLoReg_chunk_0 r) (( 29 :: int)::ii) (( 6 :: int)::ii)
((subrange_vec_dec v (( 23 :: int)::ii) (( 0 :: int)::ii) :: 24 Word.word))
:: 64 Word.word))|))) in
write_reg r_ref r)))"
(*val _update_TLBEntryLoReg_PFN : TLBEntryLoReg -> mword ty24 -> TLBEntryLoReg*)
definition update_TLBEntryLoReg_PFN :: " TLBEntryLoReg \<Rightarrow>(24)Word.word \<Rightarrow> TLBEntryLoReg " where
" update_TLBEntryLoReg_PFN v x = (
(v (|
TLBEntryLoReg_TLBEntryLoReg_chunk_0 :=
((update_subrange_vec_dec(TLBEntryLoReg_TLBEntryLoReg_chunk_0 v) (( 29 :: int)::ii) (( 6 :: int)::ii)
((subrange_vec_dec x (( 23 :: int)::ii) (( 0 :: int)::ii) :: 24 Word.word))
:: 64 Word.word))|)))"
(*val _get_TLBEntryLoReg_C : TLBEntryLoReg -> mword ty3*)
definition get_TLBEntryLoReg_C :: " TLBEntryLoReg \<Rightarrow>(3)Word.word " where
" get_TLBEntryLoReg_C v = (
(subrange_vec_dec(TLBEntryLoReg_TLBEntryLoReg_chunk_0 v) (( 5 :: int)::ii) (( 3 :: int)::ii) :: 3 Word.word))"
(*val _set_TLBEntryLoReg_C : register_ref regstate register_value TLBEntryLoReg -> mword ty3 -> M unit*)
definition set_TLBEntryLoReg_C :: "((regstate),(register_value),(TLBEntryLoReg))register_ref \<Rightarrow>(3)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where
" set_TLBEntryLoReg_C r_ref v = (
reg_deref r_ref \<bind> (\<lambda> r .
(let r =
((r (|
TLBEntryLoReg_TLBEntryLoReg_chunk_0 :=
((update_subrange_vec_dec(TLBEntryLoReg_TLBEntryLoReg_chunk_0 r) (( 5 :: int)::ii) (( 3 :: int)::ii)
((subrange_vec_dec v (( 2 :: int)::ii) (( 0 :: int)::ii) :: 3 Word.word))
:: 64 Word.word))|))) in
write_reg r_ref r)))"
(*val _update_TLBEntryLoReg_C : TLBEntryLoReg -> mword ty3 -> TLBEntryLoReg*)
definition update_TLBEntryLoReg_C :: " TLBEntryLoReg \<Rightarrow>(3)Word.word \<Rightarrow> TLBEntryLoReg " where
" update_TLBEntryLoReg_C v x = (
(v (|
TLBEntryLoReg_TLBEntryLoReg_chunk_0 :=
((update_subrange_vec_dec(TLBEntryLoReg_TLBEntryLoReg_chunk_0 v) (( 5 :: int)::ii) (( 3 :: int)::ii)
((subrange_vec_dec x (( 2 :: int)::ii) (( 0 :: int)::ii) :: 3 Word.word))
:: 64 Word.word))|)))"
(*val _get_TLBEntryLoReg_D : TLBEntryLoReg -> mword ty1*)
definition get_TLBEntryLoReg_D :: " TLBEntryLoReg \<Rightarrow>(1)Word.word " where
" get_TLBEntryLoReg_D v = (
(subrange_vec_dec(TLBEntryLoReg_TLBEntryLoReg_chunk_0 v) (( 2 :: int)::ii) (( 2 :: int)::ii) :: 1 Word.word))"
(*val _set_TLBEntryLoReg_D : register_ref regstate register_value TLBEntryLoReg -> mword ty1 -> M unit*)
definition set_TLBEntryLoReg_D :: "((regstate),(register_value),(TLBEntryLoReg))register_ref \<Rightarrow>(1)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where
" set_TLBEntryLoReg_D r_ref v = (
reg_deref r_ref \<bind> (\<lambda> r .
(let r =
((r (|
TLBEntryLoReg_TLBEntryLoReg_chunk_0 :=
((update_subrange_vec_dec(TLBEntryLoReg_TLBEntryLoReg_chunk_0 r) (( 2 :: int)::ii) (( 2 :: int)::ii)
((subrange_vec_dec v (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word))
:: 64 Word.word))|))) in
write_reg r_ref r)))"
(*val _update_TLBEntryLoReg_D : TLBEntryLoReg -> mword ty1 -> TLBEntryLoReg*)
definition update_TLBEntryLoReg_D :: " TLBEntryLoReg \<Rightarrow>(1)Word.word \<Rightarrow> TLBEntryLoReg " where
" update_TLBEntryLoReg_D v x = (
(v (|
TLBEntryLoReg_TLBEntryLoReg_chunk_0 :=
((update_subrange_vec_dec(TLBEntryLoReg_TLBEntryLoReg_chunk_0 v) (( 2 :: int)::ii) (( 2 :: int)::ii)
((subrange_vec_dec x (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word))
:: 64 Word.word))|)))"
(*val _get_TLBEntryLoReg_V : TLBEntryLoReg -> mword ty1*)
definition get_TLBEntryLoReg_V :: " TLBEntryLoReg \<Rightarrow>(1)Word.word " where
" get_TLBEntryLoReg_V v = (
(subrange_vec_dec(TLBEntryLoReg_TLBEntryLoReg_chunk_0 v) (( 1 :: int)::ii) (( 1 :: int)::ii) :: 1 Word.word))"
(*val _set_TLBEntryLoReg_V : register_ref regstate register_value TLBEntryLoReg -> mword ty1 -> M unit*)
definition set_TLBEntryLoReg_V :: "((regstate),(register_value),(TLBEntryLoReg))register_ref \<Rightarrow>(1)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where
" set_TLBEntryLoReg_V r_ref v = (
reg_deref r_ref \<bind> (\<lambda> r .
(let r =
((r (|
TLBEntryLoReg_TLBEntryLoReg_chunk_0 :=
((update_subrange_vec_dec(TLBEntryLoReg_TLBEntryLoReg_chunk_0 r) (( 1 :: int)::ii) (( 1 :: int)::ii)
((subrange_vec_dec v (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word))
:: 64 Word.word))|))) in
write_reg r_ref r)))"
(*val _update_TLBEntryLoReg_V : TLBEntryLoReg -> mword ty1 -> TLBEntryLoReg*)
definition update_TLBEntryLoReg_V :: " TLBEntryLoReg \<Rightarrow>(1)Word.word \<Rightarrow> TLBEntryLoReg " where
" update_TLBEntryLoReg_V v x = (
(v (|
TLBEntryLoReg_TLBEntryLoReg_chunk_0 :=
((update_subrange_vec_dec(TLBEntryLoReg_TLBEntryLoReg_chunk_0 v) (( 1 :: int)::ii) (( 1 :: int)::ii)
((subrange_vec_dec x (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word))
:: 64 Word.word))|)))"
(*val _get_TLBEntryLoReg_G : TLBEntryLoReg -> mword ty1*)
definition get_TLBEntryLoReg_G :: " TLBEntryLoReg \<Rightarrow>(1)Word.word " where
" get_TLBEntryLoReg_G v = (
(subrange_vec_dec(TLBEntryLoReg_TLBEntryLoReg_chunk_0 v) (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word))"
(*val _set_TLBEntryLoReg_G : register_ref regstate register_value TLBEntryLoReg -> mword ty1 -> M unit*)
definition set_TLBEntryLoReg_G :: "((regstate),(register_value),(TLBEntryLoReg))register_ref \<Rightarrow>(1)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where
" set_TLBEntryLoReg_G r_ref v = (
reg_deref r_ref \<bind> (\<lambda> r .
(let r =
((r (|
TLBEntryLoReg_TLBEntryLoReg_chunk_0 :=
((update_subrange_vec_dec(TLBEntryLoReg_TLBEntryLoReg_chunk_0 r) (( 0 :: int)::ii) (( 0 :: int)::ii)
((subrange_vec_dec v (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word))
:: 64 Word.word))|))) in
write_reg r_ref r)))"
(*val _update_TLBEntryLoReg_G : TLBEntryLoReg -> mword ty1 -> TLBEntryLoReg*)
definition update_TLBEntryLoReg_G :: " TLBEntryLoReg \<Rightarrow>(1)Word.word \<Rightarrow> TLBEntryLoReg " where
" update_TLBEntryLoReg_G v x = (
(v (|
TLBEntryLoReg_TLBEntryLoReg_chunk_0 :=
((update_subrange_vec_dec(TLBEntryLoReg_TLBEntryLoReg_chunk_0 v) (( 0 :: int)::ii) (( 0 :: int)::ii)
((subrange_vec_dec x (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word))
:: 64 Word.word))|)))"
(*val undefined_TLBEntryHiReg : unit -> M TLBEntryHiReg*)
definition undefined_TLBEntryHiReg :: " unit \<Rightarrow>((register_value),(TLBEntryHiReg),(exception))monad " where
" undefined_TLBEntryHiReg _ = (
(undefined_bitvector
instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 64 :: int)::ii) :: ( 64 Word.word) M) \<bind> (\<lambda> (w__0 :: 64 Word.word) .
return ((| TLBEntryHiReg_TLBEntryHiReg_chunk_0 = w__0 |))))"
(*val Mk_TLBEntryHiReg : mword ty64 -> TLBEntryHiReg*)
definition Mk_TLBEntryHiReg :: "(64)Word.word \<Rightarrow> TLBEntryHiReg " where
" Mk_TLBEntryHiReg v = (
(| TLBEntryHiReg_TLBEntryHiReg_chunk_0 = ((subrange_vec_dec v (( 63 :: int)::ii) (( 0 :: int)::ii) :: 64 Word.word)) |) )"
(*val _get_TLBEntryHiReg_bits : TLBEntryHiReg -> mword ty64*)
definition get_TLBEntryHiReg_bits :: " TLBEntryHiReg \<Rightarrow>(64)Word.word " where
" get_TLBEntryHiReg_bits v = (
(subrange_vec_dec(TLBEntryHiReg_TLBEntryHiReg_chunk_0 v) (( 63 :: int)::ii) (( 0 :: int)::ii) :: 64 Word.word))"
(*val _set_TLBEntryHiReg_bits : register_ref regstate register_value TLBEntryHiReg -> mword ty64 -> M unit*)
definition set_TLBEntryHiReg_bits :: "((regstate),(register_value),(TLBEntryHiReg))register_ref \<Rightarrow>(64)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where
" set_TLBEntryHiReg_bits r_ref v = (
reg_deref r_ref \<bind> (\<lambda> r .
(let r =
((r (|
TLBEntryHiReg_TLBEntryHiReg_chunk_0 :=
((update_subrange_vec_dec(TLBEntryHiReg_TLBEntryHiReg_chunk_0 r) (( 63 :: int)::ii) (( 0 :: int)::ii)
((subrange_vec_dec v (( 63 :: int)::ii) (( 0 :: int)::ii) :: 64 Word.word))
:: 64 Word.word))|))) in
write_reg r_ref r)))"
(*val _update_TLBEntryHiReg_bits : TLBEntryHiReg -> mword ty64 -> TLBEntryHiReg*)
definition update_TLBEntryHiReg_bits :: " TLBEntryHiReg \<Rightarrow>(64)Word.word \<Rightarrow> TLBEntryHiReg " where
" update_TLBEntryHiReg_bits v x = (
(v (|
TLBEntryHiReg_TLBEntryHiReg_chunk_0 :=
((update_subrange_vec_dec(TLBEntryHiReg_TLBEntryHiReg_chunk_0 v) (( 63 :: int)::ii) (( 0 :: int)::ii)
((subrange_vec_dec x (( 63 :: int)::ii) (( 0 :: int)::ii) :: 64 Word.word))
:: 64 Word.word))|)))"
(*val _get_TLBEntryHiReg_R : TLBEntryHiReg -> mword ty2*)
definition get_TLBEntryHiReg_R :: " TLBEntryHiReg \<Rightarrow>(2)Word.word " where
" get_TLBEntryHiReg_R v = (
(subrange_vec_dec(TLBEntryHiReg_TLBEntryHiReg_chunk_0 v) (( 63 :: int)::ii) (( 62 :: int)::ii) :: 2 Word.word))"
(*val _set_TLBEntryHiReg_R : register_ref regstate register_value TLBEntryHiReg -> mword ty2 -> M unit*)
definition set_TLBEntryHiReg_R :: "((regstate),(register_value),(TLBEntryHiReg))register_ref \<Rightarrow>(2)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where
" set_TLBEntryHiReg_R r_ref v = (
reg_deref r_ref \<bind> (\<lambda> r .
(let r =
((r (|
TLBEntryHiReg_TLBEntryHiReg_chunk_0 :=
((update_subrange_vec_dec(TLBEntryHiReg_TLBEntryHiReg_chunk_0 r) (( 63 :: int)::ii) (( 62 :: int)::ii)
((subrange_vec_dec v (( 1 :: int)::ii) (( 0 :: int)::ii) :: 2 Word.word))
:: 64 Word.word))|))) in
write_reg r_ref r)))"
(*val _update_TLBEntryHiReg_R : TLBEntryHiReg -> mword ty2 -> TLBEntryHiReg*)
definition update_TLBEntryHiReg_R :: " TLBEntryHiReg \<Rightarrow>(2)Word.word \<Rightarrow> TLBEntryHiReg " where
" update_TLBEntryHiReg_R v x = (
(v (|
TLBEntryHiReg_TLBEntryHiReg_chunk_0 :=
((update_subrange_vec_dec(TLBEntryHiReg_TLBEntryHiReg_chunk_0 v) (( 63 :: int)::ii) (( 62 :: int)::ii)
((subrange_vec_dec x (( 1 :: int)::ii) (( 0 :: int)::ii) :: 2 Word.word))
:: 64 Word.word))|)))"
(*val _get_TLBEntryHiReg_VPN2 : TLBEntryHiReg -> mword ty27*)
definition get_TLBEntryHiReg_VPN2 :: " TLBEntryHiReg \<Rightarrow>(27)Word.word " where
" get_TLBEntryHiReg_VPN2 v = (
(subrange_vec_dec(TLBEntryHiReg_TLBEntryHiReg_chunk_0 v) (( 39 :: int)::ii) (( 13 :: int)::ii) :: 27 Word.word))"
(*val _set_TLBEntryHiReg_VPN2 : register_ref regstate register_value TLBEntryHiReg -> mword ty27 -> M unit*)
definition set_TLBEntryHiReg_VPN2 :: "((regstate),(register_value),(TLBEntryHiReg))register_ref \<Rightarrow>(27)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where
" set_TLBEntryHiReg_VPN2 r_ref v = (
reg_deref r_ref \<bind> (\<lambda> r .
(let r =
((r (|
TLBEntryHiReg_TLBEntryHiReg_chunk_0 :=
((update_subrange_vec_dec(TLBEntryHiReg_TLBEntryHiReg_chunk_0 r) (( 39 :: int)::ii) (( 13 :: int)::ii)
((subrange_vec_dec v (( 26 :: int)::ii) (( 0 :: int)::ii) :: 27 Word.word))
:: 64 Word.word))|))) in
write_reg r_ref r)))"
(*val _update_TLBEntryHiReg_VPN2 : TLBEntryHiReg -> mword ty27 -> TLBEntryHiReg*)
definition update_TLBEntryHiReg_VPN2 :: " TLBEntryHiReg \<Rightarrow>(27)Word.word \<Rightarrow> TLBEntryHiReg " where
" update_TLBEntryHiReg_VPN2 v x = (
(v (|
TLBEntryHiReg_TLBEntryHiReg_chunk_0 :=
((update_subrange_vec_dec(TLBEntryHiReg_TLBEntryHiReg_chunk_0 v) (( 39 :: int)::ii) (( 13 :: int)::ii)
((subrange_vec_dec x (( 26 :: int)::ii) (( 0 :: int)::ii) :: 27 Word.word))
:: 64 Word.word))|)))"
(*val _get_TLBEntryHiReg_ASID : TLBEntryHiReg -> mword ty8*)
definition get_TLBEntryHiReg_ASID :: " TLBEntryHiReg \<Rightarrow>(8)Word.word " where
" get_TLBEntryHiReg_ASID v = (
(subrange_vec_dec(TLBEntryHiReg_TLBEntryHiReg_chunk_0 v) (( 7 :: int)::ii) (( 0 :: int)::ii) :: 8 Word.word))"
(*val _set_TLBEntryHiReg_ASID : register_ref regstate register_value TLBEntryHiReg -> mword ty8 -> M unit*)
definition set_TLBEntryHiReg_ASID :: "((regstate),(register_value),(TLBEntryHiReg))register_ref \<Rightarrow>(8)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where
" set_TLBEntryHiReg_ASID r_ref v = (
reg_deref r_ref \<bind> (\<lambda> r .
(let r =
((r (|
TLBEntryHiReg_TLBEntryHiReg_chunk_0 :=
((update_subrange_vec_dec(TLBEntryHiReg_TLBEntryHiReg_chunk_0 r) (( 7 :: int)::ii) (( 0 :: int)::ii)
((subrange_vec_dec v (( 7 :: int)::ii) (( 0 :: int)::ii) :: 8 Word.word))
:: 64 Word.word))|))) in
write_reg r_ref r)))"
(*val _update_TLBEntryHiReg_ASID : TLBEntryHiReg -> mword ty8 -> TLBEntryHiReg*)
definition update_TLBEntryHiReg_ASID :: " TLBEntryHiReg \<Rightarrow>(8)Word.word \<Rightarrow> TLBEntryHiReg " where
" update_TLBEntryHiReg_ASID v x = (
(v (|
TLBEntryHiReg_TLBEntryHiReg_chunk_0 :=
((update_subrange_vec_dec(TLBEntryHiReg_TLBEntryHiReg_chunk_0 v) (( 7 :: int)::ii) (( 0 :: int)::ii)
((subrange_vec_dec x (( 7 :: int)::ii) (( 0 :: int)::ii) :: 8 Word.word))
:: 64 Word.word))|)))"
(*val undefined_ContextReg : unit -> M ContextReg*)
definition undefined_ContextReg :: " unit \<Rightarrow>((register_value),(ContextReg),(exception))monad " where
" undefined_ContextReg _ = (
(undefined_bitvector
instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 64 :: int)::ii) :: ( 64 Word.word) M) \<bind> (\<lambda> (w__0 :: 64 Word.word) .
return ((| ContextReg_ContextReg_chunk_0 = w__0 |))))"
(*val Mk_ContextReg : mword ty64 -> ContextReg*)
definition Mk_ContextReg :: "(64)Word.word \<Rightarrow> ContextReg " where
" Mk_ContextReg v = (
(| ContextReg_ContextReg_chunk_0 = ((subrange_vec_dec v (( 63 :: int)::ii) (( 0 :: int)::ii) :: 64 Word.word)) |) )"
(*val _get_ContextReg_bits : ContextReg -> mword ty64*)
definition get_ContextReg_bits :: " ContextReg \<Rightarrow>(64)Word.word " where
" get_ContextReg_bits v = (
(subrange_vec_dec(ContextReg_ContextReg_chunk_0 v) (( 63 :: int)::ii) (( 0 :: int)::ii) :: 64 Word.word))"
(*val _set_ContextReg_bits : register_ref regstate register_value ContextReg -> mword ty64 -> M unit*)
definition set_ContextReg_bits :: "((regstate),(register_value),(ContextReg))register_ref \<Rightarrow>(64)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where
" set_ContextReg_bits r_ref v = (
reg_deref r_ref \<bind> (\<lambda> r .
(let r =
((r (|
ContextReg_ContextReg_chunk_0 :=
((update_subrange_vec_dec(ContextReg_ContextReg_chunk_0 r) (( 63 :: int)::ii) (( 0 :: int)::ii)
((subrange_vec_dec v (( 63 :: int)::ii) (( 0 :: int)::ii) :: 64 Word.word))
:: 64 Word.word))|))) in
write_reg r_ref r)))"
(*val _update_ContextReg_bits : ContextReg -> mword ty64 -> ContextReg*)
definition update_ContextReg_bits :: " ContextReg \<Rightarrow>(64)Word.word \<Rightarrow> ContextReg " where
" update_ContextReg_bits v x = (
(v (|
ContextReg_ContextReg_chunk_0 :=
((update_subrange_vec_dec(ContextReg_ContextReg_chunk_0 v) (( 63 :: int)::ii) (( 0 :: int)::ii)
((subrange_vec_dec x (( 63 :: int)::ii) (( 0 :: int)::ii) :: 64 Word.word))
:: 64 Word.word))|)))"
(*val _get_ContextReg_PTEBase : ContextReg -> mword ty41*)
definition get_ContextReg_PTEBase :: " ContextReg \<Rightarrow>(41)Word.word " where
" get_ContextReg_PTEBase v = (
(subrange_vec_dec(ContextReg_ContextReg_chunk_0 v) (( 63 :: int)::ii) (( 23 :: int)::ii) :: 41 Word.word))"
(*val _set_ContextReg_PTEBase : register_ref regstate register_value ContextReg -> mword ty41 -> M unit*)
definition set_ContextReg_PTEBase :: "((regstate),(register_value),(ContextReg))register_ref \<Rightarrow>(41)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where
" set_ContextReg_PTEBase r_ref v = (
reg_deref r_ref \<bind> (\<lambda> r .
(let r =
((r (|
ContextReg_ContextReg_chunk_0 :=
((update_subrange_vec_dec(ContextReg_ContextReg_chunk_0 r) (( 63 :: int)::ii) (( 23 :: int)::ii)
((subrange_vec_dec v (( 40 :: int)::ii) (( 0 :: int)::ii) :: 41 Word.word))
:: 64 Word.word))|))) in
write_reg r_ref r)))"
(*val _update_ContextReg_PTEBase : ContextReg -> mword ty41 -> ContextReg*)
definition update_ContextReg_PTEBase :: " ContextReg \<Rightarrow>(41)Word.word \<Rightarrow> ContextReg " where
" update_ContextReg_PTEBase v x = (
(v (|
ContextReg_ContextReg_chunk_0 :=
((update_subrange_vec_dec(ContextReg_ContextReg_chunk_0 v) (( 63 :: int)::ii) (( 23 :: int)::ii)
((subrange_vec_dec x (( 40 :: int)::ii) (( 0 :: int)::ii) :: 41 Word.word))
:: 64 Word.word))|)))"
(*val _get_ContextReg_BadVPN2 : ContextReg -> mword ty19*)
definition get_ContextReg_BadVPN2 :: " ContextReg \<Rightarrow>(19)Word.word " where
" get_ContextReg_BadVPN2 v = (
(subrange_vec_dec(ContextReg_ContextReg_chunk_0 v) (( 22 :: int)::ii) (( 4 :: int)::ii) :: 19 Word.word))"
(*val _set_ContextReg_BadVPN2 : register_ref regstate register_value ContextReg -> mword ty19 -> M unit*)
definition set_ContextReg_BadVPN2 :: "((regstate),(register_value),(ContextReg))register_ref \<Rightarrow>(19)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where
" set_ContextReg_BadVPN2 r_ref v = (
reg_deref r_ref \<bind> (\<lambda> r .
(let r =
((r (|
ContextReg_ContextReg_chunk_0 :=
((update_subrange_vec_dec(ContextReg_ContextReg_chunk_0 r) (( 22 :: int)::ii) (( 4 :: int)::ii)
((subrange_vec_dec v (( 18 :: int)::ii) (( 0 :: int)::ii) :: 19 Word.word))
:: 64 Word.word))|))) in
write_reg r_ref r)))"
(*val _update_ContextReg_BadVPN2 : ContextReg -> mword ty19 -> ContextReg*)
definition update_ContextReg_BadVPN2 :: " ContextReg \<Rightarrow>(19)Word.word \<Rightarrow> ContextReg " where
" update_ContextReg_BadVPN2 v x = (
(v (|
ContextReg_ContextReg_chunk_0 :=
((update_subrange_vec_dec(ContextReg_ContextReg_chunk_0 v) (( 22 :: int)::ii) (( 4 :: int)::ii)
((subrange_vec_dec x (( 18 :: int)::ii) (( 0 :: int)::ii) :: 19 Word.word))
:: 64 Word.word))|)))"
(*val undefined_XContextReg : unit -> M XContextReg*)
definition undefined_XContextReg :: " unit \<Rightarrow>((register_value),(XContextReg),(exception))monad " where
" undefined_XContextReg _ = (
(undefined_bitvector
instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 64 :: int)::ii) :: ( 64 Word.word) M) \<bind> (\<lambda> (w__0 :: 64 Word.word) .
return ((| XContextReg_XContextReg_chunk_0 = w__0 |))))"
(*val Mk_XContextReg : mword ty64 -> XContextReg*)