bump rvm version.

Author: gjz010

kernel/Cargo.lock

@@ -77,7 +77,7 @@ virtio-drivers = { git = "https://github.com/rcore-riscv-hypervisor-dev/virtio-d
 volatile = "0.2"
 woke = "0.0.2"
 xmas-elf = "0.7"
-rvm = { git = "https://github.com/rcore-riscv-hypervisor-dev/RVM", rev = "5cde71c", optional = true }
+rvm = { git = "https://github.com/rcore-riscv-hypervisor-dev/RVM", rev = "5ccac8b", optional = true }
 
 [target.'cfg(target_arch = "x86_64")'.dependencies]
 apic = { git = "https://github.com/rcore-os/apic-rs", rev = "fb86bd7" }

kernel/Cargo.toml

@@ -26,10 +26,15 @@ const RVM_VCPU_READ_STATE: u32 = RVM_IO + 0x13;
 const RVM_VCPU_WRITE_STATE: u32 = RVM_IO + 0x14;
 const RVM_VCPU_INTERRUPT: u32 = RVM_IO + 0x15;
 
-const RVM_RISCV_SET_SSIP: u32 = 0;
-const RVM_RISCV_CLEAR_SSIP: u32 = 1;
-const RVM_RISCV_SET_SEIP: u32 = 2;
-const RVM_RISCV_CLEAR_SEIP: u32 = 3;
+#[cfg(any(target_arch = "riscv64", target_arch = "riscv32"))]
+mod riscv_intr_constants {
+    pub const RVM_RISCV_SET_SSIP: u32 = 0;
+    pub const RVM_RISCV_CLEAR_SSIP: u32 = 1;
+    pub const RVM_RISCV_SET_SEIP: u32 = 2;
+    pub const RVM_RISCV_CLEAR_SEIP: u32 = 3;
+}
+#[cfg(any(target_arch = "riscv64", target_arch = "riscv32"))]
+use riscv_intr_constants::*;
 
 pub struct RvmINode {
     guests: RwLock<BTreeMap<usize, Guest>>,

kernel/src/rvm/inode.rs

@@ -55,12 +55,16 @@ mod rvm_extern_fn {
     }
 
     #[cfg(target_arch = "x86_64")]
-    #[rvm::extern_fn(x86_all_traps_handler_addr)]
-    unsafe fn rvm_x86_all_traps_handler_addr() -> usize {
-        extern "C" {
-            fn __alltraps();
-        }
-        __alltraps as usize
+    #[rvm::extern_fn(is_host_timer_interrupt)]
+    fn rvm_x86_is_host_timer_interrupt(_vec: u8) -> bool {
+        // TODO: fill in the blanks.
+        false
+    }
+    #[cfg(target_arch = "x86_64")]
+    #[rvm::extern_fn(is_host_serial_interrupt)]
+    fn rvm_x86_is_host_serial_interrupt(_vec: u8) -> bool {
+        // TODO: fill in the blanks.
+        false
     }
 
     #[cfg(any(target_arch = "riscv64", target_arch = "riscv32"))]