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BCM2712 PCIEx1 tweaks #6180

Merged
merged 2 commits into from
May 21, 2024
Merged

BCM2712 PCIEx1 tweaks #6180

merged 2 commits into from
May 21, 2024

Commits on May 20, 2024

  1. DTS: bcm2712: don't assume L1 sub-state support at chip level 

    L1 sub-states require the connection of the CLKREQ# auxiliary signal
which is a PCB-level decision, and also depends on the vagrancies of
adapters/interposers/slots that may exist between the chip and the
endpoint.

If this parameter is present, and the RC driver sees an L1 substate
capability in the endpoint, then the result is a broken link if CLKREQ#
isn't end-to-end connected - regardless of the state of the L1.x enable
bits in the RC.

Board-specific methods (HAT+ overlay, board DTB) should define this
property if required.

Signed-off-by: Jonathan Bell <[email protected]>
    @P33M
    P33M committed May 20, 2024
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  2. DTS: overlays: add pciex1-compat-pi5 

    Interop testing with the M.2 HAT has revealed that there are many quirky
endpoint devices out there, so users should have a way of rapidly
iterating to find which quirk is causing reliability issues.

Signed-off-by: Jonathan Bell <[email protected]>
    @P33M
    P33M committed May 20, 2024
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