DTS: overlays: add pciex1-compat-pi5

Interop testing with the M.2 HAT has revealed that there are many quirky endpoint devices out there, so users should have a way of rapidly iterating to find which quirk is causing reliability issues. Signed-off-by: Jonathan Bell <[email protected]>
raspberrypi · May 20, 2024 · df555f1 · df555f1
1 parent 1ae0ff6
commit df555f1
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diff --git a/arch/arm/boot/dts/overlays/Makefile b/arch/arm/boot/dts/overlays/Makefile
@@ -189,6 +189,7 @@ dtbo-$(CONFIG_ARCH_BCM2835) += \
 	pcf857x.dtbo \
 	pcie-32bit-dma.dtbo \
 	pcie-32bit-dma-pi5.dtbo \
+	pciex1-compat-pi5.dtbo \
 	pibell.dtbo \
 	pifacedigital.dtbo \
 	pifi-40.dtbo \

diff --git a/arch/arm/boot/dts/overlays/README b/arch/arm/boot/dts/overlays/README
@@ -3540,6 +3540,18 @@ Info:   Force PCIe config to support 32bit DMA addresses at the expense of
 Load:   dtoverlay=pcie-32bit-dma-pi5
 Params: <None>
 
+
+Name:   pciex1-compat-pi5
+Info:   Compatibility features for pciex1 on Pi 5.
+Load:   dtoverlay=pciex1-compat-pi5,<param>=<val>
+Params: l1ss                    Enable ASPM L1 sub-state support
+        no-l0s                  Disable ASPM L0s
+        no-mip                  Revert to the MSI target in the RC, instead of
+                                the MSI-MIP peripheral. Use if a) more than 8
+                                interrupt vectors are required or b) the EP
+                                requires DMA and MSI addresses to be 32bit.
+
+
 [ The pcf2127-rtc overlay has been deleted. See i2c-rtc. ]
 
 

diff --git a/arch/arm/boot/dts/overlays/overlay_map.dts b/arch/arm/boot/dts/overlays/overlay_map.dts
@@ -196,6 +196,10 @@
 		bcm2712;
 	};
 
+	pcie-compat-pi5 {
+		bcm2712;
+	};
+
 	pi3-act-led {
 		renamed = "act-led";
 	};

diff --git a/arch/arm/boot/dts/overlays/pciex1-compat-pi5-overlay.dts b/arch/arm/boot/dts/overlays/pciex1-compat-pi5-overlay.dts
@@ -0,0 +1,40 @@
+/*
+ * Various feature switches for the 1-lane PCIe controller on Pi 5
+ */
+
+/dts-v1/;
+/plugin/;
+
+/ {
+	compatible = "brcm,bcm2712";
+
+	/* Enable L1 sub-state support */
+	fragment@0 {
+		target = <&pciex1>;
+		__dormant__ {
+			brcm,enable-l1ss;
+		};
+	};
+
+	/* Disable ASPM L0s */
+	fragment@1 {
+		target = <&pciex1>;
+		__dormant__ {
+			aspm-no-l0s;
+		};
+	};
+
+	/* Use RC MSI target instead of MIP MSIx target */
+	fragment@2 {
+		target = <&pciex1>;
+		__dormant__ {
+			msi-parent = <&pciex1>;
+		};
+	};
+
+	__overrides__ {
+		l1ss = <0>, "+0";
+		no-l0s = <0>, "+1";
+		no-mip = <0>, "+2";
+	};
+};