We read every piece of feedback, and take your input very seriously.
To see all available qualifiers, see our documentation.
There was an error while loading. Please reload this page.
1 parent 23182a3 commit a9cae21Copy full SHA for a9cae21
CHANGELOG.md
@@ -4,10 +4,10 @@ All notable changes to this project will be documented in this file.
4
The format is based on [Keep a Changelog](http://keepachangelog.com/en/1.0.0/)
5
and this project adheres to [Semantic Versioning](http://semver.org/spec/v2.0.0.html).
6
7
-## Unreleased
+## 0.2.11 - 2022-12-12
8
### Added
9
- `tc_clk_or2`: A new generic tech cell for balanced clock OR-gates.
10
-- Added warning about misusing `tc_clk_mux2` cells.
+- `tc_clk_mux2`: Added warning about misusing `tc_clk_mux2` cells.
11
12
## 0.2.10 - 2022-11-20
13
0 commit comments