Fix bender, add xilinx pads (#16)

* Add override targets to Bender.yml

* Patch Bender file for fpga target.

Looks like `not(synthesys)` automatically overrides the `fpga` target.
To have the xilinx-specific cells linked by Bender to Vivado, we need
to modify `synthesis` into `asic`.
Fixed typo in sram cells.

* Fix bender fpga files, add pad_functional_xilinx

* remove unneeded files

Co-authored-by: Manuel Eggimann <[email protected]>
Co-authored-by: Luca Valente <[email protected]>

Author: 3 people

Bender.yml

@@ -6,38 +6,40 @@ dependencies:
   common_verification: { git: "https://github.com/pulp-platform/common_verification.git", version: 0.2.0 }
 
 sources:
-  # These simply wrap tc_* cells and are fine to use in any case
-  - src/deprecated/cluster_clk_cells.sv
-  - src/deprecated/pulp_clk_cells.sv
-
-  - target: all(rtl, not(synthesis))
+  - target: all(any(all(not(asic), not(fpga)), tech_cells_generic_include_tc_sram), not(tech_cells_generic_exclude_tc_sram))
     files:
-      # level 0
+      # Level 0
       - src/rtl/tc_sram.sv
 
-  - target: all(all(fpga, xilinx), not(synthesis))
-    files:
-      - src/deprecated/cluster_clk_cells_xilinx.sv
-      - src/deprecated/pulp_clk_cells_xilinx.sv
-      - src/fpga/tc_clk_xilinx.sv
-      - src/fpga/tc_sram_xilinx.sv
-
-  - target: all(not(all(fpga, xilinx)), not(synthesis))
+  - target: all(any(all(not(asic), not(fpga)), tech_cells_generic_include_tc_clk), not(tech_cells_generic_exclude_tc_clk))
     files:
       # Level 0
       - src/rtl/tc_clk.sv
 
-  - target: not(synthesis)
+  - target: all(any(fpga, tech_cells_generic_include_xilinx_xpm), not(tech_cells_generic_exclude_xilinx_xpm))
+    files:
+      - src/fpga/pad_functional_xilinx.sv
+      - src/fpga/tc_clk_xilinx.sv
+      - src/fpga/tc_sram_xilinx.sv
+
+  - target: all(any(not(synthesis), tech_cells_generic_include_deprecated), not(tech_cells_generic_exclude_deprecated))
     files:
       - src/deprecated/cluster_pwr_cells.sv
       - src/deprecated/generic_memory.sv
       - src/deprecated/generic_rom.sv
       - src/deprecated/pad_functional.sv
       - src/deprecated/pulp_buffer.sv
       - src/deprecated/pulp_pwr_cells.sv
+      
+  - target: all(any(not(synthesis), tech_cells_generic_include_pwr_cells), not(tech_cells_generic_exclude_pwr_cells))
+    files:
       - src/tc_pwr.sv
 
-  - target: test
+  - target: all(any(test, tech_cells_generic_include_tb_cells), not(tech_cells_generic_exclude_tb_cells))
     files:
       - test/tb_tc_sram.sv
   - src/deprecated/pulp_clock_gating_async.sv
+
+  # These simply wrap tc_* cells and are fine to use in any case
+  - src/deprecated/cluster_clk_cells.sv
+  - src/deprecated/pulp_clk_cells.sv

src/deprecated/cluster_clk_cells_xilinx.sv

@@ -0,0 +1,48 @@
+// Copyright 2018 ETH Zurich and University of Bologna.
+// Copyright and related rights are licensed under the Solderpad Hardware
+// License, Version 0.51 (the "License"); you may not use this file except in
+// compliance with the License.  You may obtain a copy of the License at
+// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law
+// or agreed to in writing, software, hardware and materials distributed under
+// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR
+// CONDITIONS OF ANY KIND, either express or implied. See the License for the
+// specific language governing permissions and limitations under the License.
+
+
+module pad_functional_pd
+(
+   input  logic             OEN,
+   input  logic             I,
+   output logic             O,
+   input  logic             PEN,
+   inout  logic             PAD
+);
+
+  (* PULLDOWN = "YES" *)
+  IOBUF iobuf_i (
+    .T ( OEN ),
+    .I ( I    ),
+    .O ( O    ),
+    .IO( PAD  )
+  );
+
+endmodule
+
+module pad_functional_pu
+(
+   input  logic             OEN,
+   input  logic             I,
+   output logic             O,
+   input  logic             PEN,
+   inout  logic             PAD
+);
+
+  (* PULLUP = "YES" *)
+  IOBUF iobuf_i (
+    .T ( OEN ),
+    .I ( I    ),
+    .O ( O    ),
+    .IO( PAD  )
+  );
+
+endmodule

src/deprecated/pulp_clk_cells_xilinx.sv

@@ -168,7 +168,7 @@ module tc_sram #(
 // Validate parameters.
 // pragma translate_off
 `ifndef VERILATOR
-`ifndef TARGET_SYNTHESYS
+`ifndef TARGET_SYNTHESIS
   initial begin: p_assertions
     assert (SimInit == "zeros") else $fatal(1, "The Xilinx `tc_sram` has fixed SimInit: zeros");
     assert ($bits(addr_i)  == NumPorts * AddrWidth) else $fatal(1, "AddrWidth problem on `addr_i`");

src/fpga/pad_functional_xilinx.sv

@@ -167,7 +167,7 @@ module tc_sram #(
 // Validate parameters.
 // pragma translate_off
 `ifndef VERILATOR
-`ifndef TARGET_SYNTHESYS
+`ifndef TARGET_SYNTHESIS
   initial begin: p_assertions
     assert ($bits(addr_i)  == NumPorts * AddrWidth) else $fatal(1, "AddrWidth problem on `addr_i`");
     assert ($bits(wdata_i) == NumPorts * DataWidth) else $fatal(1, "DataWidth problem on `wdata_i`");