test: Verilator compile fixes (#255)

Author: solomatnikov

test/cdc_2phase_clearable_tb.sv

@@ -368,10 +368,16 @@ module cdc_2phase_clearable_tb_delay_injector #(
     .a_rst_ni  ( src_rst_ni  ),
     .a_clear_i ( src_clear_i ),
     .a_clear_o ( s_src_clear ),
+    .a_clear_ack_i  ( '0     ),
+    .a_isolate_o    (        ),
+    .a_isolate_ack_i( '0     ),
     .b_clk_i   ( dst_clk_i   ),
     .b_rst_ni  ( dst_rst_ni  ),
     .b_clear_i ( dst_clear_i ),
-    .b_clear_o ( s_dst_clear )
+    .b_clear_o ( s_dst_clear ),
+    .b_clear_ack_i  ( '0     ),
+    .b_isolate_o    (        ),
+    .b_isolate_ack_i( '0     )
   );
 
   assign src_clear_pending_o = s_src_clear;

test/clk_int_div_static_tb.sv

@@ -35,6 +35,8 @@ module clk_int_div_static_tb;
     .rst_no ( rstn )
   );
 
+// https://github.com/verilator/verilator/issues/5979
+`ifndef VERILATOR
   property T_clk(real clk_period);
     realtime               current_time;
     realtime               actual_period;
@@ -43,7 +45,7 @@ module clk_int_div_static_tb;
                            ('1, actual_period = $realtime - current_time) |->
                            (($realtime - current_time >= clk_period - t_delta) && ($realtime - current_time < clk_period + t_delta));
   endproperty
-
+`endif
 
   for (genvar i = 1; i < MaxClkDiv; i++) begin :gen_clk_divs
     clk_int_div_static #(
@@ -57,8 +59,10 @@ module clk_int_div_static_tb;
       .clk_o          ( clk_out[i]   )
     );
 
+`ifndef VERILATOR
     assert_period_period: assert property (@(posedge clk_out[i]) T_clk(TClkIn*i)) else
       $error("Output period of div %d clock is incorrect. Should be in range %d to %d.", i, TClkIn*i-t_delta, TClkIn*i+t_delta);
+`endif
 
   end
 

test/fifo_tb.sv

@@ -147,12 +147,15 @@ module fifo_inst_tb #(
         end
     end
 
+// https://github.com/verilator/verilator/issues/5981
+`ifndef VERILATOR
     if (FALL_THROUGH) begin
         // In fall through mode, assert that the output data is equal to the input data when pushing
         // to an empty FIFO.
         assert property (@(posedge clk_i) ((empty & ~push) ##1 push) |-> rdata == wdata)
             else $error("Input did not fall through");
     end
+`endif
 
 endmodule