Address final TODOs

Author: colluca

src/axi_mcast_demux_mapped.sv

@@ -378,6 +378,10 @@ module axi_mcast_demux_mapped #(
   // Assertions
   // -----------------
 
+// pragma translate_off
+`ifndef VERILATOR
+`ifndef XSIM
+
   // Check that multicast address map rules expressed in interval form can be converted to
   // mask form, see https://arxiv.org/pdf/2502.19215
   for (genvar i = 0; i < NoMulticastRules; i++) begin : gen_multicast_rule_assertion
@@ -404,6 +408,36 @@ module axi_mcast_demux_mapped #(
         default_mst_port_i.start_addr, size))
   end
 
+  // Check that addrmap and default slave do not change while there is an unserved Ax
+  `ASSERT(default_mst_port_en_aw_stable,
+    (slv_req_cut.aw_valid && !slv_resp_cut.aw_ready) |=> $stable(en_default_mst_port_i),
+    clk_i, !rst_ni,
+    "It is not allowed to change the default mst port enable when there is an unserved Aw beat.")
+  `ASSERT(default_mst_port_aw_stable,
+    (slv_req_cut.aw_valid && !slv_resp_cut.aw_ready) |=> $stable(default_mst_port_i),
+    clk_i, !rst_ni,
+    "It is not allowed to change the default mst port when there is an unserved Aw beat.")
+  `ASSERT(addrmap_aw_stable,
+    (slv_req_cut.aw_valid && !slv_resp_cut.aw_ready) |=> $stable(addr_map_i),
+    clk_i, !rst_ni,
+    "It is not allowed to change the address map when there is an unserved Aw beat.")
+  `ASSERT(default_mst_port_en_ar_stable,
+    (slv_req_cut.ar_valid && !slv_resp_cut.ar_ready) |=> $stable(en_default_mst_port_i),
+    clk_i, !rst_ni,
+    "It is not allowed to change the default mst port enable when there is an unserved Ar beat.")
+  `ASSERT(default_mst_port_ar_stable,
+    (slv_req_cut.ar_valid && !slv_resp_cut.ar_ready) |=> $stable(default_mst_port_i),
+    clk_i, !rst_ni,
+    "It is not allowed to change the default mst port when there is an unserved Ar beat.")
+  `ASSERT(addrmap_ar_stable,
+    (slv_req_cut.ar_valid && !slv_resp_cut.ar_ready) |=> $stable(addr_map_i),
+    clk_i, !rst_ni,
+    "It is not allowed to change the address map when there is an unserved Ar beat.")
+
+`endif
+`endif
+// pragma translate_on
+
 endmodule
 
 // interface wrapper

src/axi_mcast_mux.sv

@@ -67,10 +67,6 @@ module axi_mcast_mux #(
   input  mst_resp_t                  mst_resp_i
 );
 
-  // TODO colluca: can this be merged with MstIdxBits?
-  localparam int unsigned SlvPortIdxBits = cf_math_pkg::idx_width(NoSlvPorts);
-  typedef logic [SlvPortIdxBits-1:0] mst_idx_t;
-
   localparam int unsigned MstIdxBits    = $clog2(NoSlvPorts);
   localparam int unsigned MstAxiIDWidth = SlvAxiIDWidth + MstIdxBits;
 
@@ -182,7 +178,7 @@ module axi_mcast_mux #(
     logic                  ucast_aw_valid, ucast_aw_ready;
     logic                  mcast_aw_valid, mcast_aw_ready, mcast_aw_commit;
     logic                  mcast_not_aw_valid;
-    mst_idx_t              mcast_sel_q, mcast_sel_d;
+    logic [MstIdxBits-1:0] mcast_sel_q, mcast_sel_d;
     logic [NoSlvPorts-1:0] mcast_sel_mask;
     logic [NoSlvPorts-1:0] ucast_aw_readies, mcast_aw_readies;
 
@@ -299,7 +295,6 @@ module axi_mcast_mux #(
     );
 
     // Arbitrate multicast requests in priority encoder fashion
-    // TODO colluca: extend lzc to return mask form instead of cnt?
     lzc #(
       .WIDTH ( NoSlvPorts ),
       .MODE  ( 1'b0       ) // Trailing zero mode
@@ -314,8 +309,7 @@ module axi_mcast_mux #(
     assign mcast_aw_commit = |slv_aw_commit_i;
     assign mcast_aw_readies = {NoSlvPorts{mcast_aw_ready}} & mcast_sel_mask;
 
-    // TODO colluca: change all FFxARN to FFx
-    `FFLARN(mcast_sel_q, mcast_sel_d, mcast_aw_valid && mcast_aw_ready, '0, clk_i, rst_ni)
+    `FFL(mcast_sel_q, mcast_sel_d, mcast_aw_valid && mcast_aw_ready, '0, clk_i, rst_ni)
 
     // Arbitrate "winners" of unicast and multicast arbitrations
     // giving priority to multicast
@@ -546,7 +540,6 @@ module axi_mcast_mux #(
 // pragma translate_on
 endmodule
 
-// TODO colluca: adapt this
 // interface wrap
 `include "axi/assign.svh"
 `include "axi/typedef.svh"

src/axi_mcast_xbar_unmuxed.sv

@@ -91,37 +91,6 @@ import cf_math_pkg::idx_width;
 
   for (genvar i = 0; i < Cfg.NoSlvPorts; i++) begin : gen_slv_port_demux
 
-    // make sure that the default slave does not get changed, if there is an unserved Ax
-    // pragma translate_off
-    // TODO(colluca): is this still the right place for these? and are they still correct after
-    //                moving the address decoders past the spill registers
-    `ifndef VERILATOR
-    `ifndef XSIM
-    default disable iff (~rst_ni);
-    default_aw_mst_port_en: assert property(
-      @(posedge clk_i) (slv_ports_req_i[i].aw_valid && !slv_ports_resp_o[i].aw_ready)
-          |=> $stable(en_default_mst_port_i[i]))
-        else $fatal (1, $sformatf("It is not allowed to change the default mst port\
-                                   enable, when there is an unserved Aw beat. Slave Port: %0d", i));
-    default_aw_mst_port: assert property(
-      @(posedge clk_i) (slv_ports_req_i[i].aw_valid && !slv_ports_resp_o[i].aw_ready)
-          |=> $stable(default_mst_port_i[i]))
-        else $fatal (1, $sformatf("It is not allowed to change the default mst port\
-                                   when there is an unserved Aw beat. Slave Port: %0d", i));
-    default_ar_mst_port_en: assert property(
-      @(posedge clk_i) (slv_ports_req_i[i].ar_valid && !slv_ports_resp_o[i].ar_ready)
-          |=> $stable(en_default_mst_port_i[i]))
-        else $fatal (1, $sformatf("It is not allowed to change the enable, when\
-                                   there is an unserved Ar beat. Slave Port: %0d", i));
-    default_ar_mst_port: assert property(
-      @(posedge clk_i) (slv_ports_req_i[i].ar_valid && !slv_ports_resp_o[i].ar_ready)
-          |=> $stable(default_mst_port_i[i]))
-        else $fatal (1, $sformatf("It is not allowed to change the default mst port\
-                                   when there is an unserved Ar beat. Slave Port: %0d", i));
-    `endif
-    `endif
-    // pragma translate_on
-
     axi_mcast_demux_mapped #(
       .AxiIdWidth            ( Cfg.AxiIdWidthSlvPorts   ),  // ID Width
       .AxiAddrWidth          ( Cfg.AxiAddrWidth         ),

src/axi_test.sv

@@ -906,7 +906,6 @@ package axi_test;
       // Determine memory type.
       ax_beat.ax_cache = is_read ? axi_pkg::get_arcache(mem_region.mem_type) : axi_pkg::get_awcache(mem_region.mem_type);
       // Randomize beat size.
-      // TODO colluca: how do we handle traffic shaping w/ multicast?
       if (TRAFFIC_SHAPING) begin
         rand_success = std::randomize(cprob) with {
           cprob >= 0; cprob < max_cprob;