diff --git a/.github/workflows/lint.yml b/.github/workflows/lint.yml index 7db655b5..022f7027 100644 --- a/.github/workflows/lint.yml +++ b/.github/workflows/lint.yml @@ -27,9 +27,12 @@ jobs: # Exclude generated headers (no license checker support for optional lines) exclude_paths: | sw/include/regs/*.h + sw/include/tasi.h + sw/tests/bare-metal/hostd/tasi_* .dir-locals.el utils/* scripts/* + hw/padframe/* lint-sv: runs-on: ubuntu-latest @@ -42,7 +45,7 @@ jobs: uses: chipsalliance/verible-linter-action@main with: paths: hw - exclude_paths: hw/configs + exclude_paths: hw/configs hw/padframe extra_args: "--waiver_files .github/verible.waiver" github_token: ${{ secrets.GITHUB_TOKEN }} fail_on_error: true diff --git a/Bender.local b/Bender.local index fde9c3ac..af31e73e 100644 --- a/Bender.local +++ b/Bender.local @@ -7,7 +7,7 @@ overrides: axi_riscv_atomics: { git: https://github.com/pulp-platform/axi_riscv_atomics.git , rev: 46d567cad5a614a82778702d48b3a789aed7711b } # branch: astral apb: { git: "https://github.com/pulp-platform/apb.git" , version: 0.2.3 } redundancy_cells: { git: "https://github.com/pulp-platform/redundancy_cells.git" , rev: "9e31f7c6c24877eaf58279903e7a162b16c9a721" } # branch: astral-v0 - hci: { git: "https://github.com/pulp-platform/hci.git" , version: 2.1.1 } + hci: { git: "https://github.com/pulp-platform/hci.git" , rev: "38fc2a7eea7978df52434e66ee04a40788fd86b7" } # branch: lg/ecc_rebase_v2.1.1 tech_cells_generic: { git: "https://github.com/pulp-platform/tech_cells_generic.git" , version: =0.2.13 } riscv-dbg: { git: "https://github.com/pulp-platform/riscv-dbg.git" , version: =0.8.0 } idma: { git: "https://github.com/pulp-platform/idma.git" , version: 0.6.2 } diff --git a/Bender.lock b/Bender.lock index 0cff3477..2dda0b61 100644 --- a/Bender.lock +++ b/Bender.lock @@ -1,4 +1,11 @@ packages: + ace: + revision: ea2fc9ced5be964b47cfcbcd6eb6518771a9e85d + version: null + source: + Git: https://github.com/pulp-platform/ace.git + dependencies: + - axi apb: revision: 77ddf073f194d44b9119949d2421be59789e69ae version: 0.2.4 @@ -22,8 +29,8 @@ packages: - apb - register_interface axi: - revision: 9402c8a9ce0a7b5253c3c29e788612d771e8b5d6 - version: 0.39.3 + revision: 587355b77b8ce94dcd600efbd5d5bd118ff913a7 + version: 0.39.4 source: Git: https://github.com/pulp-platform/axi.git dependencies: @@ -46,7 +53,7 @@ packages: dependencies: - axi_slice axi_llc: - revision: 62079f9cc13e64d1ef131377aee6801eeef52642 + revision: 2f23e6fc40ac7256f177a44c1f106c70c05c6cca version: null source: Git: https://github.com/pulp-platform/axi_llc @@ -114,11 +121,12 @@ packages: Git: https://github.com/AlSaqr-platform/can_bus.git dependencies: [] cheshire: - revision: ac8b56958ca89e7ce5ebece004ea19844dd4b8ef + revision: c96614848899df428aef29888747799609ff96fd version: null source: Git: https://github.com/pulp-platform/cheshire.git dependencies: + - ace - apb_uart - axi - axi_llc @@ -205,11 +213,12 @@ packages: - fpnew - tech_cells_generic cva6: - revision: 8ccc3ff4d5dd51278d4af2b1e587b760a8e52b0d + revision: 125c68eeb1a64c20db652be15491c19e03730b70 version: null source: Git: https://github.com/pulp-platform/cva6.git dependencies: + - ace - axi - common_cells - fpnew @@ -251,14 +260,17 @@ packages: dependencies: - common_cells hci: - revision: afe0220f9a2f132dc8655c48da05aae5121a570b - version: 2.1.1 + revision: 38fc2a7eea7978df52434e66ee04a40788fd86b7 + version: null source: Git: https://github.com/pulp-platform/hci.git dependencies: - cluster_interconnect + - common_cells - hwpe-stream - l2_tcdm_hybrid_interco + - redundancy_cells + - register_interface hier-icache: revision: 2886cb2a46cea3e2bd2d979b505d88fadfbe150c version: null @@ -352,25 +364,26 @@ packages: dependencies: - common_cells neureka: - revision: b6141132d915b3fa5c1db712b730ac463a949a34 - version: 1.0.0 + revision: f23d22a2d630cf8e4d524c919bfd943ab9e4998d + version: null source: Git: https://github.com/pulp-platform/neureka.git dependencies: - hci - hwpe-ctrl - hwpe-stream + - register_interface - zeroriscy obi: - revision: c2141a653c755461ff44f61d12aeb5d99fc8e760 - version: 0.1.3 + revision: 5321106817e177d6c16ecc4daa922b96b1bc946b + version: 0.1.5 source: Git: https://github.com/pulp-platform/obi.git dependencies: - common_cells - common_verification opentitan: - revision: 1466a339775f62ebec9fababe2859462bf9198b3 + revision: cb163f0d8eefd896ceed8b83d2987e7feccf830e version: null source: Git: https://github.com/pulp-platform/opentitan.git @@ -408,7 +421,7 @@ packages: - idma - register_interface pulp_cluster: - revision: 2cd26c4923570ae81297c06078a0cfcded1e761c + revision: 069d77e162a4b2be4132d429135656b54d5150ba version: null source: Git: https://github.com/pulp-platform/pulp_cluster.git @@ -438,7 +451,7 @@ packages: - tech_cells_generic - timer_unit redmule: - revision: 60ba008c339ec70b5ffa7120bec2cbf5a8f53c99 + revision: 9223ccc932e21d0667e9c2d30831db41eec9299e version: null source: Git: https://github.com/pulp-platform/redmule.git @@ -449,6 +462,7 @@ packages: - hci - hwpe-ctrl - hwpe-stream + - register_interface - tech_cells_generic redundancy_cells: revision: 9e31f7c6c24877eaf58279903e7a162b16c9a721 @@ -544,6 +558,12 @@ packages: - hwpe-ctrl - hwpe-stream - ibex + spacewire: + revision: null + version: null + source: + Path: /usr/scratch2/lagrev5/mciani/astral-project/spacewire + dependencies: [] spatz: revision: 98de97f24fe42675c9b4a8cc08354a03af57400a version: null @@ -558,6 +578,12 @@ packages: - register_interface - riscv-dbg - tech_cells_generic + streamer: + revision: null + version: null + source: + Path: /usr/scratch2/lagrev5/mciani/astral-project/streamer + dependencies: [] tagger: revision: b288376b65b6bbd5feea196bb3c220f783d96e29 version: null diff --git a/Bender.yml b/Bender.yml index 7b0da95a..e3165879 100644 --- a/Bender.yml +++ b/Bender.yml @@ -13,21 +13,23 @@ package: dependencies: register_interface: { git: https://github.com/pulp-platform/register_interface.git, version: 0.4.3 } axi: { git: https://github.com/pulp-platform/axi.git, version: 0.39.1 } - cheshire: { git: https://github.com/pulp-platform/cheshire.git, rev: ac8b56958ca89e7ce5ebece004ea19844dd4b8ef } # branch: astral-v0 + cheshire: { git: https://github.com/pulp-platform/cheshire.git, rev: c96614848899df428aef29888747799609ff96fd } # branch: rt/astral-culsans-complete/align hyperbus: { git: https://github.com/pulp-platform/hyperbus.git, rev: f039e601c8b6590181734e6d26ff8b77aa380412 } # branch: chi/add_fsm_with_Tcsh dyn_mem: { git: https://github.com/pulp-platform/dyn_spm.git, rev: 480590062742230dc9bd4050358a15b4747bdf34 } # branch: main safety_island: { git: https://github.com/pulp-platform/safety_island.git, rev: aaef55c798ab53560faaf451a86668fa1e6d0f3b } # branch: carfield - pulp_cluster: { git: https://github.com/pulp-platform/pulp_cluster.git, rev: 2cd26c4923570ae81297c06078a0cfcded1e761c } # branch: astral - opentitan: { git: https://github.com/pulp-platform/opentitan.git, rev: 1466a339775f62ebec9fababe2859462bf9198b3 } # branch: mc/astral + pulp_cluster: { git: https://github.com/pulp-platform/pulp_cluster.git, rev: 069d77e162a4b2be4132d429135656b54d5150ba } # branch: astral + opentitan: { git: https://github.com/pulp-platform/opentitan.git, rev: cb163f0d8eefd896ceed8b83d2987e7feccf830e } # branch: mc/astral mailbox_unit: { git: https://github.com/pulp-platform/mailbox_unit.git, version: 1.1.0 } apb: { git: https://github.com/pulp-platform/apb.git, version: 0.2.3 } timer_unit: { git: https://github.com/pulp-platform/timer_unit.git, version: 1.0.2 } apb_adv_timer: { git: https://github.com/pulp-platform/apb_adv_timer.git, version: 1.0.4 } can_bus: { git: https://github.com/AlSaqr-platform/can_bus.git, rev: 0ec0bf8b7dab6d5e4b3f7ec58338a8efee066379 } # branch: pulp spatz: { git: https://github.com/pulp-platform/spatz.git, rev: 98de97f24fe42675c9b4a8cc08354a03af57400a } # branch: yt/astral - common_cells: { git: https://github.com/pulp-platform/common_cells.git, version: 1.37.0 } # branch: master + common_cells: { git: https://github.com/pulp-platform/common_cells.git, version: 1.37.0 } # branch: master pulp-ethernet: { git: https://github.com/pulp-platform/pulp-ethernet.git, rev: 1f8f1776ec494773f8e6c48e16685eb35d5f445e } # branch: handshake riscv-dbg: { git: https://github.com/pulp-platform/riscv-dbg.git, version: =0.8.0 } + streamer: { path: /usr/scratch2/lagrev5/mciani/astral-project/streamer } + spacewire: { path: /usr/scratch2/lagrev5/mciani/astral-project/spacewire } workspace: package_links: @@ -44,6 +46,10 @@ sources: files: - hw/configs/carfield_l2dual_secure_pulp_periph_can.sv + - target: carfield_l2dual_secure_pulp_periph_can_ethernet_streamer_spw + files: + - hw/configs/carfield_l2dual_secure_pulp_periph_can_ethernet_streamer_spw.sv + - target: carfield_l2dual_safe_secure_pulp_spatz_periph_can files: - hw/configs/carfield_l2dual_safe_secure_pulp_spatz_periph_can.sv @@ -85,8 +91,18 @@ sources: # levels 1 and 0, etc. Files within a level are ordered alphabetically. # Level 0 - hw/carfield_pkg.sv + - hw/carfield_chip_pkg.sv - hw/regs/carfield_reg_pkg.sv - hw/regs/carfield_reg_top.sv + - hw/padframe/astral_padframe/src/pkg_astral_padframe.sv + - hw/padframe/astral_padframe/src/pkg_internal_astral_padframe_periph.sv + - hw/padframe/astral_padframe/src/astral_padframe_periph_config_reg_pkg.sv + - hw/padframe/astral_padframe/src/astral_padframe_periph_config_reg_top.sv + - hw/padframe/astral_padframe/src/astral_padframe_periph_pads.sv + - hw/padframe/astral_padframe/src/astral_padframe_periph_muxer.sv + - hw/padframe/astral_padframe/src/astral_padframe_periph.sv + - hw/padframe/astral_padframe/src/astral_padframe.sv + - hw/padframe/pad_behav.sv # Level 1 - hw/cheshire_wrap.sv - hw/hyperbus_wrap.sv @@ -95,6 +111,7 @@ sources: - hw/carfield_rstgen.sv # Level 2 - hw/carfield.sv + - hw/astral_wrap.sv - target: spatz files: @@ -104,8 +121,8 @@ sources: files: - target/sim/src/hyp_vip/s27ks0641.v - target/sim/src/vip_carfield_soc.sv - - target/sim/src/carfield_fix.sv - - target/sim/src/carfield_tb.sv + - target/sim/src/astral_fix.sv + - target/sim/src/astral_tb.sv - target: spyglass files: @@ -115,11 +132,13 @@ sources: files: - tech/sourcecode/tc_clk.sv - tech/sourcecode/tc_sram.sv + - tech/sourcecode/ptme_ram.sv - tech/sourcecode/configurable_delay.sv - - target/synth/src/carfield_synth_wrap.sv + - tech/sourcecode/gf12_fll_wrap.sv - target: tech_sim files: + # TODO: add technology dependent memory cells - tech/sourcecode/macros/rf_sp_uhse_rvt_mvt_128x40m2b1w0.v - tech/sourcecode/macros/rf_sp_uhse_rvt_mvt_256x32m2b1w1.v - tech/sourcecode/macros/rf_sp_uhse_rvt_mvt_256x39m4b1w0.v @@ -127,6 +146,7 @@ sources: - tech/sourcecode/macros/rf_sp_uhse_rvt_mvt_256x46m2b1w1.v - tech/sourcecode/macros/rf_sp_uhse_rvt_mvt_256x64m2b1w1.v - tech/sourcecode/macros/rf_sp_uhse_rvt_mvt_256x128m2b1w1.v + - tech/sourcecode/macros/rf_sp_uhse_rvt_mvt_1024x39m4b1w0.v - tech/sourcecode/macros/rf_sp_uhse_rvt_mvt_512x39m4b1w0.v - tech/sourcecode/macros/rf_sp_uhse_rvt_mvt_1024x64m4b1w1.v - tech/sourcecode/macros/rf_sp_uhse_rvt_mvt_128x264m1b1w0.v @@ -134,7 +154,33 @@ sources: - tech/sourcecode/macros/sram_dp_hse_rvt_mvt_16384x8m16b8w1.v - tech/sourcecode/macros/sram_sp_hse_rvt_mvt_2560x76m4b4w0.v - tech/sourcecode/macros/sram_sp_hse_rvt_mvt_4096x76m4b4w0.v + - tech/sourcecode/macros/sram_sp_hse_rvt_mvt_16384x39m8b8w0.v - tech/sourcecode/tc_sram.sv + # FLL Model + - tech/sourcecode/fll/rtl/FLL_digital/FLLPkg.vhd + - tech/sourcecode/fll/rtl/FLL_digital/FLL_clk_divider.vhd + - tech/sourcecode/fll/rtl/FLL_digital/FLL_clk_period_quantizer.vhd + - tech/sourcecode/fll/rtl/FLL_digital/FLL_clock_gated.gf12.vhd + - tech/sourcecode/fll/rtl/FLL_digital/FLL_clock_gated.rtl.vhd + - tech/sourcecode/fll/rtl/FLL_digital/FLL_dither_pattern_gen.vhd + - tech/sourcecode/fll/rtl/FLL_digital/FLL_glitchfree_clkdiv.vhd + - tech/sourcecode/fll/rtl/FLL_digital/FLL_glitchfree_clkmux.vhd + - tech/sourcecode/fll/rtl/FLL_digital/FLL_loop_filter.vhd + - tech/sourcecode/fll/rtl/FLL_digital/FLL_mux.gf12.vhd + - tech/sourcecode/fll/rtl/FLL_digital/FLL_mux.rtl.vhd + - tech/sourcecode/fll/rtl/FLL_digital/FLL_reg.vhd + - tech/sourcecode/fll/rtl/FLL_digital/FLL_settling_monitor.vhd + - tech/sourcecode/fll/rtl/FLL_digital/FLL_synchroedge.vhd + - tech/sourcecode/fll/rtl/FLL_digital/FLL_zerodelta.vhd + - tech/sourcecode/fll/rtl/FLL_digital/FLL_digital.vhd + - tech/sourcecode/fll/rtl/behavioral/gf12_FLL_DCO_model.tc.vhd + #- tech/sourcecode/fll/rtl/behavioral/gf12_FLL_DCO_model.vhd + - tech/sourcecode/fll/rtl/behavioral/gf12_FLL_model.vhd + - tech/sourcecode/fll/rtl/behavioral/gf12_FLL.v + - tech/sourcecode/gf12_fll_wrap.sv + # PAD Model + - tech/sourcecode/pad/io_gppr_12lpplus_t18_mv08_mv18_fs18_rvt_dr.v + - tech/sourcecode/ptme_ram.sv - target: all(xilinx, fpga, xilinx_vanilla) files: diff --git a/README.md b/README.md index 9717848e..01b22b56 100644 --- a/README.md +++ b/README.md @@ -32,20 +32,24 @@ floating-point and integer workloads. [Targets](https://pulp-platform.github.io/carfield/tg). * For detailed information on Carfield's inner workings, consult the [User Manual](https://pulp-platform.github.io/carfield/um/). + If you are impatient and have all needed [dependencies](https://pulp-platform.github.io/carfield/gs/#dependencies), type: ``` -make car-all +source env/env-iis.sh +bender update +make car-all PYTHON=python3 +make tech-init ``` and then run a [simulation](https://pulp-platform.github.io/carfield/tg/sim) with Questasim by typing: ```tcl -make car-vsim-sim-build -make car-vsim-sim-run CHS_BINARY=./sw/tests/bare-metal/hostd/helloworld.car.l2.elf +make car-vsim-sim-build DEBUG=1 TECH_SIM=1 +make car-vsim-sim-run CHS_BINARY=./sw/tests/bare-metal/hostd/helloworld.car.l2.elf DEBUG=1 TECH_SIM=1 ``` --- diff --git a/bender-common.mk b/bender-common.mk index 0f12d785..8f6e6bf9 100644 --- a/bender-common.mk +++ b/bender-common.mk @@ -6,7 +6,7 @@ # Author: Matteo Perotti # Runtime-selectable Carfield configuration -CARFIELD_CONFIG ?= carfield_l2dual_secure_pulp_periph_can +CARFIELD_CONFIG ?= carfield_l2dual_secure_pulp_periph_can_ethernet_streamer_spw # bender targets common_targs += -t cva6 @@ -14,7 +14,7 @@ common_targs += -t mchan common_targs += -t integer_cluster common_targs += -t cv32e40p_use_ff_regfile common_targs += -t scm_use_fpga_scm -common_targs += -t cv64a6_imafdcsclic_sv39 +common_targs += -t cv64a6_imafdch_sv39_wb # cv64a6_imafdcsclic_sv39 common_targs += -t rtl # The `snitch_cluster` target is needed for iDMA backend generation common_targs += -t snitch_cluster diff --git a/bender-sim.mk b/bender-sim.mk index 87c8f067..cb8594e2 100644 --- a/bender-sim.mk +++ b/bender-sim.mk @@ -13,4 +13,5 @@ ifeq ($(TECH_SIM), 1) sim_targs += -t tech_sim sim_defs += -D INITIALIZE_MEMORY sim_defs += -D INITIALIZE_OUTPUT + sim_defs += -D GF12_FLL endif diff --git a/bender-synth.mk b/bender-synth.mk index b4036462..e6a3ad2a 100644 --- a/bender-synth.mk +++ b/bender-synth.mk @@ -17,3 +17,4 @@ synth_defs += -D SYNTHESIS synth_defs += -D EXCLUDE_PADFRAME synth_defs += -D TARGET_INTEL16_SIMPLE_DPM_RF synth_defs += -D NO_SYNOPSYS_FF +synth_defs += -D GF12_FLL diff --git a/carfield.mk b/carfield.mk index fe88d4c0..556b78b4 100644 --- a/carfield.mk +++ b/carfield.mk @@ -20,7 +20,7 @@ CAR_ROOT ?= $(shell $(BENDER) path carfield) CAR_HW_DIR := $(CAR_ROOT)/hw CAR_SW_DIR := $(CAR_ROOT)/sw -CAR_TGT_DIR := $(CAR_ROOT)/target/ +CAR_TGT_DIR := $(CAR_ROOT)/target CAR_XIL_DIR := $(CAR_TGT_DIR)/xilinx CAR_SIM_DIR := $(CAR_TGT_DIR)/sim SECD_ROOT ?= $(shell $(BENDER) path opentitan) @@ -36,6 +36,8 @@ BENDER_PATH ?= $(shell which $(BENDER)) PYTHON ?= python3 +PADRICK ?= $(CAR_HW_DIR)/padframe/padrick + # Include mandatory bender targets and defines for multiple targets (sim, fpga, synth) include $(CAR_ROOT)/bender-common.mk include $(CAR_ROOT)/bender-sim.mk @@ -100,6 +102,15 @@ SPATZD_MAKEDIR := $(SPATZD_ROOT)/hw/system/spatz_cluster SPATZD_BINARY ?= SPATZD_BOOTMODE ?= 0 # default jtag bootmode +# Streamer, implementing telecommand and telemetry protocols +STREAMER_ROOT ?= $(shell $(BENDER) path streamer) + +# SpaceWire IP +SPACEWIRE_ROOT ?= $(shell $(BENDER) path spacewire) + +# PLL/FLL bypass +BYPASS_PLL ?= 0 + ########################### # System HW configuration # ########################### @@ -167,7 +178,7 @@ SAFED_SW_BUILD := safed-sw-build SAFED_SW_INIT := safed-sw-init endif -ifeq ($(shell echo $(SAFED_PRESENT)), 1) +ifeq ($(shell echo $(SPATZD_PRESENT)), 1) SPATZD_HW_INIT := spatzd-hw-init endif @@ -246,6 +257,30 @@ secd-hw-init: ## not forget to check in the generated RTL. In addition, dedicated documentation is autogenerated. regenerate_soc_regs: $(CAR_ROOT)/hw/regs/carfield_reg_pkg.sv $(CAR_ROOT)/hw/regs/carfield_reg_top.sv $(CAR_SW_DIR)/include/regs/soc_ctrl.h $(CAR_HW_DIR)/regs/pcr.md +.PHONY: $(CAR_ROOT)/hw/regs/carfield_regs.hjson +$(CAR_ROOT)/hw/regs/carfield_regs.hjson: hw/regs/carfield_regs.csv | venv + $(VENV)/$(PYTHON) ./scripts/csv_to_json.py --input $< --output $@ + +.PHONY: $(CAR_ROOT)/hw/regs/carfield_reg_pkg.sv hw/regs/carfield_reg_top.sv +$(CAR_ROOT)/hw/regs/carfield_reg_pkg.sv $(CAR_ROOT)/hw/regs/carfield_reg_top.sv: $(CAR_ROOT)/hw/regs/carfield_regs.hjson | venv + $(VENV)/$(PYTHON) utils/reggen/regtool.py -r $< --outdir $(dir $@) + +.PHONY: $(CAR_SW_DIR)/include/regs/soc_ctrl.h +$(CAR_SW_DIR)/include/regs/soc_ctrl.h: $(CAR_ROOT)/hw/regs/carfield_regs.hjson | venv + $(VENV)/$(PYTHON) utils/reggen/regtool.py -D $< > $@ + +.PHONY: $(CAR_SW_DIR)/hw/regs/pcr.md +$(CAR_HW_DIR)/regs/pcr.md: $(CAR_ROOT)/hw/regs/carfield_regs.hjson | venv + $(VENV)/$(PYTHON) utils/reggen/regtool.py -d $< > $@ + +## @section Carfield padframe generation +.PHONY: regenerate_padframe +regenerate_padframe: $(CAR_HW_DIR)/padframe/astral_padframe + +$(CAR_HW_DIR)/padframe/astral_padframe: $(CAR_HW_DIR)/padframe/astral_padframe.yml + $(PADRICK) generate rtl $< -o $@ + sed -i.original '/i_pad_vss_core_v_2/d' $@/src/astral_padframe_periph_pads.sv + .PHONY: $(CAR_ROOT)/hw/regs/carfield_regs.hjson $(CAR_ROOT)/hw/regs/carfield_regs.hjson: hw/regs/carfield_regs.csv | venv $(VENV)/$(PYTHON) ./scripts/csv_to_json.py --input $< --output $@ @@ -387,7 +422,7 @@ car-check-litmus-tests: $(LITMUS_WORK_DIR)/litmus.log ############## tech-repo := git@iis-git.ee.ethz.ch:Astral/gf12.git # no commit by default, change during development -tech-commit := 26f9f03b6fcd9af8ace79bf5b4c6ea3a61c681a0 # branch: main +tech-commit := 9fe2a2bcb7a636c93bceada37e23bfc08902b6b3 # branch: yt/thales tech-clone: git clone $(tech-repo) tech diff --git a/hw/astral_wrap.sv b/hw/astral_wrap.sv new file mode 100644 index 00000000..082c2922 --- /dev/null +++ b/hw/astral_wrap.sv @@ -0,0 +1,722 @@ +// Copyright 2023 ETH Zurich and University of Bologna. +// Solderpad Hardware License, Version 0.51, see LICENSE for details. +// SPDX-License-Identifier: SHL-0.51 +// +// Victor Isachi + +`include "cheshire/typedef.svh" +`include "axi/typedef.svh" +`include "apb/typedef.svh" + +module astral_wrap + import carfield_pkg::*; + import carfield_chip_pkg::*; + import carfield_reg_pkg::*; + import cheshire_pkg::*; + import pkg_astral_padframe::*; +#( + parameter cheshire_cfg_t Cfg = carfield_pkg::CarfieldCfgDefault, + parameter int unsigned HypNumPhys = 1, + parameter int unsigned HypNumChips = 1, + parameter type reg_req_t = logic, + parameter type reg_rsp_t = logic +) ( + inout wire logic pad_periph_ref_clk_pad, + inout wire logic pad_periph_fll_host_pad, + inout wire logic pad_periph_fll_periph_pad, + inout wire logic pad_periph_fll_alt_pad, + inout wire logic pad_periph_fll_rt_pad, + inout wire logic pad_periph_fll_bypass_pad, + inout wire logic pad_periph_pwr_on_rst_n_pad, + inout wire logic pad_periph_test_mode_pad, + inout wire logic pad_periph_boot_mode_0_pad, + inout wire logic pad_periph_boot_mode_1_pad, + input wire logic pad_periph_ot_boot_mode_pad, + inout wire logic pad_periph_secure_boot_pad, + inout wire logic pad_periph_jtag_tclk_pad, + inout wire logic pad_periph_jtag_trst_n_pad, + inout wire logic pad_periph_jtag_tms_pad, + inout wire logic pad_periph_jtag_tdi_pad, + inout wire logic pad_periph_jtag_tdo_pad, + inout wire logic pad_periph_jtag_ot_tclk_pad, + inout wire logic pad_periph_jtag_ot_trst_ni_pad, + inout wire logic pad_periph_jtag_ot_tms_pad, + inout wire logic pad_periph_jtag_ot_tdi_pad, + inout wire logic pad_periph_jtag_ot_tdo_pad, + inout wire logic pad_periph_hyper_cs_0_n_pad, + inout wire logic pad_periph_hyper_cs_1_n_pad, + inout wire logic pad_periph_hyper_ck_pad, + inout wire logic pad_periph_hyper_ck_n_pad, + inout wire logic pad_periph_hyper_rwds_pad, + inout wire logic pad_periph_hyper_dq_0_pad, + inout wire logic pad_periph_hyper_dq_1_pad, + inout wire logic pad_periph_hyper_dq_2_pad, + inout wire logic pad_periph_hyper_dq_3_pad, + inout wire logic pad_periph_hyper_dq_4_pad, + inout wire logic pad_periph_hyper_dq_5_pad, + inout wire logic pad_periph_hyper_dq_6_pad, + inout wire logic pad_periph_hyper_dq_7_pad, + inout wire logic pad_periph_hyper_reset_n_pad, + inout wire logic pad_periph_spw_data_in_pad, + inout wire logic pad_periph_spw_strb_in_pad, + inout wire logic pad_periph_spw_data_out_pad, + inout wire logic pad_periph_spw_strb_out_pad, + inout wire logic pad_periph_uart_tx_out_pad, + inout wire logic pad_periph_uart_rx_in_pad, + inout wire logic pad_periph_muxed_v_00_pad, + inout wire logic pad_periph_muxed_v_01_pad, + inout wire logic pad_periph_muxed_v_02_pad, + inout wire logic pad_periph_muxed_v_03_pad, + inout wire logic pad_periph_muxed_v_04_pad, + inout wire logic pad_periph_muxed_v_05_pad, + inout wire logic pad_periph_muxed_v_06_pad, + inout wire logic pad_periph_muxed_v_07_pad, + inout wire logic pad_periph_muxed_v_08_pad, + inout wire logic pad_periph_muxed_v_09_pad, + inout wire logic pad_periph_muxed_v_10_pad, + inout wire logic pad_periph_muxed_v_11_pad, + inout wire logic pad_periph_muxed_v_12_pad, + inout wire logic pad_periph_muxed_v_13_pad, + inout wire logic pad_periph_muxed_v_14_pad, + inout wire logic pad_periph_muxed_v_15_pad, + inout wire logic pad_periph_muxed_v_16_pad, + inout wire logic pad_periph_muxed_v_17_pad, + inout wire logic pad_periph_muxed_h_00_pad, + inout wire logic pad_periph_muxed_h_01_pad, + inout wire logic pad_periph_muxed_h_02_pad, + inout wire logic pad_periph_muxed_h_03_pad +); + + //////////////////////////// + // Carfield configuration // + //////////////////////////// + + localparam cheshire_cfg_t CarfieldCfg = carfield_pkg::CarfieldCfgDefault; + `CHESHIRE_TYPEDEF_ALL(carfield_, CarfieldCfg) + + + //////////////////////// + // Connection Signals // + //////////////////////// + + // POR + logic pwr_on_rst_n; + logic ref_clk_pwr_on_rst_n; + + // clock signals + logic ref_clk; + // generated clocks + logic host_clk, periph_clk, alt_clk, rt_clk; + + // secure boot mode signal + logic secure_boot; + + ////////////// + // Padframe // + ////////////// + + // register interface + // to padframe: ref clock domain + carfield_reg_req_t padframe_refclk_cfg_reg_req; + carfield_reg_rsp_t padframe_refclk_cfg_reg_rsp; + + // signal to pad + static_connection_signals_pad2soc_t st_pad2soc_signals; + static_connection_signals_soc2pad_t st_soc2pad_signals; + port_signals_pad2soc_t pad2soc_port_signals; + port_signals_soc2pad_t soc2pad_port_signals; + + // pad2soc + + // is secure boot enabled + assign secure_boot = st_pad2soc_signals.periph.secure_boot_i; + // safed bootmodes - no sefety island + logic [1:0] bootmode_safe_isln_s; + assign bootmode_safe_isln_s[0] = 1'b0; + assign bootmode_safe_isln_s[1] = 1'b0; + // secd bootmodes + logic [1:0] bootmode_sec_isln_s; + assign bootmode_sec_isln_s[0] = st_pad2soc_signals.periph.ot_boot_mode_i; + assign bootmode_sec_isln_s[1] = 1'b0; + // hostd bootmodes + logic [1:0] bootmode_host_s; + assign bootmode_host_s[0] = st_pad2soc_signals.periph.boot_mode_0_i; + assign bootmode_host_s[1] = st_pad2soc_signals.periph.boot_mode_1_i; + // serial link + logic [SlinkNumChan-1:0][SlinkNumLanes-1:0] serial_link_data_in_s; + assign serial_link_data_in_s[0][0] = pad2soc_port_signals.periph.serial_link.slink_0_i; + assign serial_link_data_in_s[0][1] = pad2soc_port_signals.periph.serial_link.slink_1_i; + assign serial_link_data_in_s[0][2] = pad2soc_port_signals.periph.serial_link.slink_2_i; + assign serial_link_data_in_s[0][3] = pad2soc_port_signals.periph.serial_link.slink_3_i; + assign serial_link_data_in_s[0][4] = pad2soc_port_signals.periph.serial_link.slink_4_i; + assign serial_link_data_in_s[0][5] = pad2soc_port_signals.periph.serial_link.slink_5_i; + assign serial_link_data_in_s[0][6] = pad2soc_port_signals.periph.serial_link.slink_6_i; + assign serial_link_data_in_s[0][7] = pad2soc_port_signals.periph.serial_link.slink_7_i; + // hyperbus signals + logic [HypNumPhys-1:0] hyperbus_rwds_in_s; + logic [HypNumPhys-1:0][7:0] hyperbus_data_in_s; + // hyperbus 0 + assign hyperbus_data_in_s[0][0] = st_pad2soc_signals.periph.hyper_dq_0_i; + assign hyperbus_data_in_s[0][1] = st_pad2soc_signals.periph.hyper_dq_1_i; + assign hyperbus_data_in_s[0][2] = st_pad2soc_signals.periph.hyper_dq_2_i; + assign hyperbus_data_in_s[0][3] = st_pad2soc_signals.periph.hyper_dq_3_i; + assign hyperbus_data_in_s[0][4] = st_pad2soc_signals.periph.hyper_dq_4_i; + assign hyperbus_data_in_s[0][5] = st_pad2soc_signals.periph.hyper_dq_5_i; + assign hyperbus_data_in_s[0][6] = st_pad2soc_signals.periph.hyper_dq_6_i; + assign hyperbus_data_in_s[0][7] = st_pad2soc_signals.periph.hyper_dq_7_i; + assign hyperbus_rwds_in_s[0] = st_pad2soc_signals.periph.hyper_rwds_i; + + // soc2pad + + // serial link + logic [SlinkNumChan-1:0][SlinkNumLanes-1:0] serial_link_data_out_s; + assign soc2pad_port_signals.periph.serial_link.slink_v_0_o = serial_link_data_out_s[0][0]; + assign soc2pad_port_signals.periph.serial_link.slink_v_1_o = serial_link_data_out_s[0][1]; + assign soc2pad_port_signals.periph.serial_link.slink_v_2_o = serial_link_data_out_s[0][2]; + assign soc2pad_port_signals.periph.serial_link.slink_v_3_o = serial_link_data_out_s[0][3]; + assign soc2pad_port_signals.periph.serial_link.slink_h_0_o = serial_link_data_out_s[0][4]; + assign soc2pad_port_signals.periph.serial_link.slink_h_1_o = serial_link_data_out_s[0][5]; + assign soc2pad_port_signals.periph.serial_link.slink_h_2_o = serial_link_data_out_s[0][6]; + assign soc2pad_port_signals.periph.serial_link.slink_h_3_o = serial_link_data_out_s[0][7]; + //hyperbus + logic [HypNumPhys-1:0] hyperbus_rwds_out_s; + logic [HypNumPhys-1:0] hyperbus_rwds_oe_s; + logic [HypNumPhys-1:0] hyperbus_clk_o_s; + logic [HypNumPhys-1:0] hyperbus_clk_no_s; + logic [HypNumPhys-1:0] hyperbus_rst_no_s; + logic [HypNumPhys-1:0][HypNumChips-1:0] hyperbus_cs_no_s; + logic [HypNumPhys-1:0][7:0] hyperbus_data_out_s; + logic [HypNumPhys-1:0] hyperbus_data_oe_s; + // hyper bus 0 + assign st_soc2pad_signals.periph.hyper_ck_no = hyperbus_clk_no_s[0]; + assign st_soc2pad_signals.periph.hyper_ck_o = hyperbus_clk_o_s[0]; + assign st_soc2pad_signals.periph.hyper_cs_0_no = hyperbus_cs_no_s[0][0]; + assign st_soc2pad_signals.periph.hyper_cs_1_no = hyperbus_cs_no_s[0][1]; + assign st_soc2pad_signals.periph.hyper_dq_0_o = hyperbus_data_out_s[0][0]; + assign st_soc2pad_signals.periph.hyper_dq_1_o = hyperbus_data_out_s[0][1]; + assign st_soc2pad_signals.periph.hyper_dq_2_o = hyperbus_data_out_s[0][2]; + assign st_soc2pad_signals.periph.hyper_dq_3_o = hyperbus_data_out_s[0][3]; + assign st_soc2pad_signals.periph.hyper_dq_4_o = hyperbus_data_out_s[0][4]; + assign st_soc2pad_signals.periph.hyper_dq_5_o = hyperbus_data_out_s[0][5]; + assign st_soc2pad_signals.periph.hyper_dq_6_o = hyperbus_data_out_s[0][6]; + assign st_soc2pad_signals.periph.hyper_dq_7_o = hyperbus_data_out_s[0][7]; + assign st_soc2pad_signals.periph.hyper_dq_oen_i = hyperbus_data_oe_s[0]; + assign st_soc2pad_signals.periph.hyper_reset_no = hyperbus_rst_no_s[0]; + assign st_soc2pad_signals.periph.hyper_rwds_o = hyperbus_rwds_out_s[0]; + assign st_soc2pad_signals.periph.hyper_rwds_oen_i = hyperbus_rwds_oe_s[0]; + // TMTC + logic [2:0] hpc_addr_out_s; + assign soc2pad_port_signals.periph.hpc.hpc_addr_0_o = hpc_addr_out_s[0]; + assign soc2pad_port_signals.periph.hpc.hpc_addr_1_o = hpc_addr_out_s[1]; + assign soc2pad_port_signals.periph.hpc.hpc_addr_2_o = hpc_addr_out_s[2]; + logic [1:0] llc_line_out_s; + assign soc2pad_port_signals.periph.llc.llc_line_0_o = llc_line_out_s[0]; + assign soc2pad_port_signals.periph.llc.llc_line_1_o = llc_line_out_s[1]; + + // peripherals + + // pad2soc + // spih + logic [ 3:0] spih_sd_i_s; + assign spih_sd_i_s[0] = pad2soc_port_signals.periph.spi.spih_sd_0_i; + assign spih_sd_i_s[1] = pad2soc_port_signals.periph.spi.spih_sd_1_i; + assign spih_sd_i_s[2] = pad2soc_port_signals.periph.spi.spih_sd_2_i; + assign spih_sd_i_s[3] = pad2soc_port_signals.periph.spi.spih_sd_3_i; + // spih_ot + logic [ 3:0] spih_ot_sd_i_s; + assign spih_ot_sd_i_s[0] = pad2soc_port_signals.periph.spi_ot.spih_ot_sd_0_i; + assign spih_ot_sd_i_s[1] = pad2soc_port_signals.periph.spi_ot.spih_ot_sd_1_i; + assign spih_ot_sd_i_s[2] = pad2soc_port_signals.periph.spi_ot.spih_ot_sd_2_i; + assign spih_ot_sd_i_s[3] = pad2soc_port_signals.periph.spi_ot.spih_ot_sd_3_i; + // ethernet + logic [3:0] eth_rxd_i_s; + assign eth_rxd_i_s[0] = pad2soc_port_signals.periph.ethernet.eth_rxd_0_i; + assign eth_rxd_i_s[1] = pad2soc_port_signals.periph.ethernet.eth_rxd_1_i; + assign eth_rxd_i_s[2] = pad2soc_port_signals.periph.ethernet.eth_rxd_2_i; + assign eth_rxd_i_s[3] = pad2soc_port_signals.periph.ethernet.eth_rxd_3_i; + + // gpio + logic [31:0] gpio_out_s; + logic [31:0] gpio_tx_en_s; + logic [31:0] gpio_in_s; + assign soc2pad_port_signals.periph.gpio.gpio_v_0_o = gpio_out_s[0]; + assign soc2pad_port_signals.periph.gpio.gpio_v_1_o = gpio_out_s[1]; + assign soc2pad_port_signals.periph.gpio.gpio_v_2_o = gpio_out_s[2]; + assign soc2pad_port_signals.periph.gpio.gpio_v_3_o = gpio_out_s[3]; + assign soc2pad_port_signals.periph.gpio.gpio_v_4_o = gpio_out_s[4]; + assign soc2pad_port_signals.periph.gpio.gpio_v_5_o = gpio_out_s[5]; + assign soc2pad_port_signals.periph.gpio.gpio_v_6_o = gpio_out_s[6]; + assign soc2pad_port_signals.periph.gpio.gpio_v_7_o = gpio_out_s[7]; + assign soc2pad_port_signals.periph.gpio.gpio_v_8_o = gpio_out_s[8]; + assign soc2pad_port_signals.periph.gpio.gpio_v_9_o = gpio_out_s[9]; + assign soc2pad_port_signals.periph.gpio.gpio_v_10_o = gpio_out_s[10]; + assign soc2pad_port_signals.periph.gpio.gpio_v_11_o = gpio_out_s[11]; + assign soc2pad_port_signals.periph.gpio.gpio_v_12_o = gpio_out_s[12]; + assign soc2pad_port_signals.periph.gpio.gpio_v_13_o = gpio_out_s[13]; + assign soc2pad_port_signals.periph.gpio.gpio_v_14_o = gpio_out_s[14]; + assign soc2pad_port_signals.periph.gpio.gpio_v_15_o = gpio_out_s[15]; + assign soc2pad_port_signals.periph.gpio.gpio_v_16_o = gpio_out_s[16]; + assign soc2pad_port_signals.periph.gpio.gpio_v_17_o = gpio_out_s[17]; + assign soc2pad_port_signals.periph.gpio.gpio_h_0_o = gpio_out_s[18]; + assign soc2pad_port_signals.periph.gpio.gpio_h_1_o = gpio_out_s[19]; + assign soc2pad_port_signals.periph.gpio.gpio_h_2_o = gpio_out_s[20]; + assign soc2pad_port_signals.periph.gpio.gpio_h_3_o = gpio_out_s[21]; + // GPIO 22-31 remain unconnected + assign soc2pad_port_signals.periph.gpio.gpio_v_0_oen_i = gpio_tx_en_s[0]; + assign soc2pad_port_signals.periph.gpio.gpio_v_1_oen_i = gpio_tx_en_s[1]; + assign soc2pad_port_signals.periph.gpio.gpio_v_2_oen_i = gpio_tx_en_s[2]; + assign soc2pad_port_signals.periph.gpio.gpio_v_3_oen_i = gpio_tx_en_s[3]; + assign soc2pad_port_signals.periph.gpio.gpio_v_4_oen_i = gpio_tx_en_s[4]; + assign soc2pad_port_signals.periph.gpio.gpio_v_5_oen_i = gpio_tx_en_s[5]; + assign soc2pad_port_signals.periph.gpio.gpio_v_6_oen_i = gpio_tx_en_s[6]; + assign soc2pad_port_signals.periph.gpio.gpio_v_7_oen_i = gpio_tx_en_s[7]; + assign soc2pad_port_signals.periph.gpio.gpio_v_8_oen_i = gpio_tx_en_s[8]; + assign soc2pad_port_signals.periph.gpio.gpio_v_9_oen_i = gpio_tx_en_s[9]; + assign soc2pad_port_signals.periph.gpio.gpio_v_10_oen_i = gpio_tx_en_s[10]; + assign soc2pad_port_signals.periph.gpio.gpio_v_11_oen_i = gpio_tx_en_s[11]; + assign soc2pad_port_signals.periph.gpio.gpio_v_12_oen_i = gpio_tx_en_s[12]; + assign soc2pad_port_signals.periph.gpio.gpio_v_13_oen_i = gpio_tx_en_s[13]; + assign soc2pad_port_signals.periph.gpio.gpio_v_14_oen_i = gpio_tx_en_s[14]; + assign soc2pad_port_signals.periph.gpio.gpio_v_15_oen_i = gpio_tx_en_s[15]; + assign soc2pad_port_signals.periph.gpio.gpio_v_16_oen_i = gpio_tx_en_s[16]; + assign soc2pad_port_signals.periph.gpio.gpio_v_17_oen_i = gpio_tx_en_s[17]; + assign soc2pad_port_signals.periph.gpio.gpio_h_0_oen_i = gpio_tx_en_s[18]; + assign soc2pad_port_signals.periph.gpio.gpio_h_1_oen_i = gpio_tx_en_s[19]; + assign soc2pad_port_signals.periph.gpio.gpio_h_2_oen_i = gpio_tx_en_s[20]; + assign soc2pad_port_signals.periph.gpio.gpio_h_3_oen_i = gpio_tx_en_s[21]; + // GPIO 22-31 remain unconnected + assign gpio_in_s[0] = pad2soc_port_signals.periph.gpio.gpio_v_0_i; + assign gpio_in_s[1] = pad2soc_port_signals.periph.gpio.gpio_v_1_i; + assign gpio_in_s[2] = pad2soc_port_signals.periph.gpio.gpio_v_2_i; + assign gpio_in_s[3] = pad2soc_port_signals.periph.gpio.gpio_v_3_i; + assign gpio_in_s[4] = pad2soc_port_signals.periph.gpio.gpio_v_4_i; + assign gpio_in_s[5] = pad2soc_port_signals.periph.gpio.gpio_v_5_i; + assign gpio_in_s[6] = pad2soc_port_signals.periph.gpio.gpio_v_6_i; + assign gpio_in_s[7] = pad2soc_port_signals.periph.gpio.gpio_v_7_i; + assign gpio_in_s[8] = pad2soc_port_signals.periph.gpio.gpio_v_8_i; + assign gpio_in_s[9] = pad2soc_port_signals.periph.gpio.gpio_v_9_i; + assign gpio_in_s[10] = pad2soc_port_signals.periph.gpio.gpio_v_10_i; + assign gpio_in_s[11] = pad2soc_port_signals.periph.gpio.gpio_v_11_i; + assign gpio_in_s[12] = pad2soc_port_signals.periph.gpio.gpio_v_12_i; + assign gpio_in_s[13] = pad2soc_port_signals.periph.gpio.gpio_v_13_i; + assign gpio_in_s[14] = pad2soc_port_signals.periph.gpio.gpio_v_14_i; + assign gpio_in_s[15] = pad2soc_port_signals.periph.gpio.gpio_v_15_i; + assign gpio_in_s[16] = pad2soc_port_signals.periph.gpio.gpio_v_16_i; + assign gpio_in_s[17] = pad2soc_port_signals.periph.gpio.gpio_v_17_i; + assign gpio_in_s[18] = pad2soc_port_signals.periph.gpio.gpio_h_0_i; + assign gpio_in_s[19] = pad2soc_port_signals.periph.gpio.gpio_h_1_i; + assign gpio_in_s[20] = pad2soc_port_signals.periph.gpio.gpio_h_2_i; + assign gpio_in_s[21] = pad2soc_port_signals.periph.gpio.gpio_h_3_i; + // GPI0 22-31 remain unconnected + assign gpio_in_s[31:22] = '0; + + // soc2pad + // clocks + assign st_soc2pad_signals.periph.fll_host_clk_o = host_clk; + assign st_soc2pad_signals.periph.fll_periph_clk_o = periph_clk; + assign st_soc2pad_signals.periph.fll_alt_clk_o = alt_clk; + assign st_soc2pad_signals.periph.fll_rt_clk_o = rt_clk; + + + // soc2pad + // uart-- carfield itf + // spi + logic spih_sck_o_s; + logic [ 1:0] spih_csb_o_s; + logic [ 3:0] spih_sd_o_s; + logic [ 3:0] spih_sd_en_o_s; + // TODO: CHECK POLARITY OF THE SIGNAL (SPI CS) + assign soc2pad_port_signals.periph.spi.spih_csb_0_o = spih_csb_o_s[0]; + assign soc2pad_port_signals.periph.spi.spih_csb_1_o = spih_csb_o_s[1]; + assign soc2pad_port_signals.periph.spi.spih_sck_o = spih_sck_o_s; + assign soc2pad_port_signals.periph.spi.spih_sd_0_o = spih_sd_o_s[0]; + assign soc2pad_port_signals.periph.spi.spih_sd_0_oen_i = spih_sd_en_o_s[0]; + assign soc2pad_port_signals.periph.spi.spih_sd_1_o = spih_sd_o_s[1]; + assign soc2pad_port_signals.periph.spi.spih_sd_1_oen_i = spih_sd_en_o_s[1]; + assign soc2pad_port_signals.periph.spi.spih_sd_2_o = spih_sd_o_s[2]; + assign soc2pad_port_signals.periph.spi.spih_sd_2_oen_i = spih_sd_en_o_s[2]; + assign soc2pad_port_signals.periph.spi.spih_sd_3_o = spih_sd_o_s[3]; + assign soc2pad_port_signals.periph.spi.spih_sd_3_oen_i = spih_sd_en_o_s[3]; + // i2c -- carfield itf + // spi_ot + logic spih_ot_sck_o_s; + logic spih_ot_csb_o_s; + logic [ 3:0] spih_ot_sd_o_s; + logic [ 3:0] spih_ot_sd_en_o_s; + // TODO: CHECK POLARITY OF THE SIGNAL (SPI CS) + assign soc2pad_port_signals.periph.spi_ot.spih_ot_csb_o = spih_ot_csb_o_s; + assign soc2pad_port_signals.periph.spi_ot.spih_ot_sck_o = spih_ot_sck_o_s; + assign soc2pad_port_signals.periph.spi_ot.spih_ot_sd_0_o = spih_ot_sd_o_s[0]; + assign soc2pad_port_signals.periph.spi_ot.spih_ot_sd_0_oen_i = spih_ot_sd_en_o_s[0]; + assign soc2pad_port_signals.periph.spi_ot.spih_ot_sd_1_o = spih_ot_sd_o_s[1]; + assign soc2pad_port_signals.periph.spi_ot.spih_ot_sd_1_oen_i = spih_ot_sd_en_o_s[1]; + assign soc2pad_port_signals.periph.spi_ot.spih_ot_sd_2_o = spih_ot_sd_o_s[2]; + assign soc2pad_port_signals.periph.spi_ot.spih_ot_sd_2_oen_i = spih_ot_sd_en_o_s[2]; + assign soc2pad_port_signals.periph.spi_ot.spih_ot_sd_3_o = spih_ot_sd_o_s[3]; + assign soc2pad_port_signals.periph.spi_ot.spih_ot_sd_3_oen_i = spih_ot_sd_en_o_s[3]; + // can0 -- carfield itf + // ethernet + logic [ 3:0] eth_txd_o_s; + assign soc2pad_port_signals.periph.ethernet.eth_txd_0_o = eth_txd_o_s[0]; + assign soc2pad_port_signals.periph.ethernet.eth_txd_1_o = eth_txd_o_s[1]; + assign soc2pad_port_signals.periph.ethernet.eth_txd_2_o = eth_txd_o_s[2]; + assign soc2pad_port_signals.periph.ethernet.eth_txd_3_o = eth_txd_o_s[3]; + + // External async register interface + logic[1:0] ext_reg_async_slv_req_src_out; + logic[1:0] ext_reg_async_slv_ack_src_in; + carfield_reg_req_t[1:0] ext_reg_async_slv_data_src_out; + logic[1:0] ext_reg_async_slv_req_src_in; + logic[1:0] ext_reg_async_slv_ack_src_out; + carfield_reg_rsp_t[1:0] ext_reg_async_slv_data_src_in; + + ////////////////////// + // Clock generation // + ////////////////////// + + logic[carfield_pkg::NumFll-1:0] clk_fll_out; + logic[carfield_pkg::NumFll-1:0] clk_fll_e; + logic[carfield_pkg::NumFll-1:0] fll_lock; + logic[carfield_pkg::NumFll-1:0] fll_pwd; + logic[carfield_pkg::NumFll-1:0] fll_test_mode; + logic[carfield_pkg::NumFll-1:0] fll_scan_e; + logic[carfield_pkg::NumFll-1:0] fll_scan_in; + logic[carfield_pkg::NumFll-1:0] fll_scan_out; + logic[carfield_pkg::NumFll-1:0] fll_scan_jtag_in; + logic[carfield_pkg::NumFll-1:0] fll_scan_jtag_out; + + // ref_clk + assign ref_clk = st_pad2soc_signals.periph.ref_clk_i; + // power on reset + assign pwr_on_rst_n = st_pad2soc_signals.periph.pwr_on_rst_ni; + + assign host_clk = clk_fll_out[0]; + assign periph_clk = clk_fll_out[1]; + assign alt_clk = clk_fll_out[2]; + assign secd_clk = clk_fll_out[3]; + assign clk_fll_e = '{default: 1'b1}; + + clk_int_div_static #( + .DIV_VALUE ( 100 ), + .ENABLE_CLOCK_IN_RESET( 1'b1 ) + ) i_rt_clk_div ( + .clk_i ( clk_fll_out[4] ), + .rst_ni ( pwr_on_rst_n ), + .en_i ( 1'b1 ), + .test_mode_en_i ( 1'b0 ), + .clk_o ( rt_clk ) + ); + + assign fll_pwd = '{default: 1'b0}; + assign fll_test_mode = '{default: 1'b0}; + assign fll_scan_e = '{default: 1'b0}; + assign fll_scan_in = '{default: 1'b0}; + assign fll_scan_jtag_in = '{default: 1'b0}; + + // synchronize power-on rst with ref clock (required by padframe) + rstgen i_ref_clk_rstgen ( + .clk_i (ref_clk), + .rst_ni (pwr_on_rst_n), + .test_mode_i ( '0 ), + .rst_no (ref_clk_pwr_on_rst_n), + .init_no () + ); + +`ifdef GF12_FLL + gf12_fll_wrap #( + .NUM_FLL ( carfield_pkg::NumFll ), + // Addresses are double-word aligned (0x2002_0000, 0x2002_0008, ...) + .FLL_REG_OFFSET ( 3 ), + .reg_req_t ( carfield_reg_req_t ), + .reg_rsp_t ( carfield_reg_rsp_t ) + ) i_fll_wrap ( + .clk_ref_i ( ref_clk ), + .rst_n_i ( ref_clk_pwr_on_rst_n ), + .clk_bypass_i ( st_pad2soc_signals.periph.ref_clk_i ), + .bypass_i ( st_pad2soc_signals.periph.fll_bypass_i ), + .async_req_i ( ext_reg_async_slv_req_src_out[0] ), + .async_ack_o ( ext_reg_async_slv_ack_src_in[0] ), + .async_data_i ( ext_reg_async_slv_data_src_out[0] ), + .async_req_o ( ext_reg_async_slv_req_src_in[0] ), + .async_ack_i ( ext_reg_async_slv_ack_src_out[0] ), + .async_data_o ( ext_reg_async_slv_data_src_in[0] ), + .clk_fll_out_o ( clk_fll_out ), + .clk_fll_e_i ( clk_fll_e ), + .fll_lock_o ( fll_lock ), + .fll_pwd_i ( fll_pwd ), + .fll_test_mode_i ( fll_test_mode ), + .fll_scan_e_i ( fll_scan_e ), + .fll_scan_in_i ( fll_scan_in ), + .fll_scan_out_o ( fll_scan_out ), + .fll_scan_jtag_in_i ( fll_scan_jtag_in ), + .fll_scan_jtag_out_o ( fll_scan_jtag_out ) + ); +`else + logic dummy_rst; + logic dummy_clk; + carfield_reg_rsp_t dummy_rsp; + + clk_rst_gen #( + .ClkPeriod ( 20ns ), + .RstClkCycles ( 33 ) + ) i_dummy_fll ( + .clk_o ( dummy_clk ), + .rst_no ( dummy_rst ) + ); + assign clk_fll_out = '{default: dummy_clk & dummy_rst}; + assign fll_lock = '{default: dummy_rst}; + + reg_cdc_dst #( + .CDC_KIND ( "cdc_4phase" ), + .req_t ( carfield_reg_req_t ), + .rsp_t ( carfield_reg_rsp_t ) + ) i_fake_cdc ( + .dst_clk_i ( dummy_clk ), + .dst_rst_ni ( dummy_rst ), + .dst_req_o ( ), + .dst_rsp_i ( dummy_rsp ), + + .async_req_i ( ext_reg_async_slv_req_src_out[0] ), + .async_ack_o ( ext_reg_async_slv_ack_src_in[0] ), + .async_data_i ( ext_reg_async_slv_data_src_out[0] ), + + .async_req_o ( ext_reg_async_slv_req_src_in[0] ), + .async_ack_i ( ext_reg_async_slv_ack_src_out[0] ), + .async_data_o ( ext_reg_async_slv_data_src_in[0] ) + ); + assign dummy_rsp.ready = 1'b1; + assign dummy_rsp.error = 1'b0; + assign dummy_rsp.rdata = 'hCACABABE; +`endif + + ////////////////// + // Carfield SoC // + ////////////////// + + carfield #( + .Cfg ( Cfg ), + .HypNumPhys ( HypNumPhys ), + .HypNumChips ( HypNumChips ), + .reg_req_t ( carfield_reg_req_t ), + .reg_rsp_t ( carfield_reg_rsp_t ) + ) i_dut ( + .host_clk_i ( host_clk ), + .periph_clk_i ( periph_clk ), + .alt_clk_i ( alt_clk ), + .secd_clk_i ( secd_clk ), + .rt_clk_i ( rt_clk ), + .pwr_on_rst_ni ( pwr_on_rst_n ), + .test_mode_i ( '0 ), + .boot_mode_i ( bootmode_host_s[1:0] ), + .jtag_tck_i ( st_pad2soc_signals.periph.jtag_tclk_i ), + .jtag_trst_ni ( st_pad2soc_signals.periph.jtag_trst_ni ), + .jtag_tms_i ( st_pad2soc_signals.periph.jtag_tms_i ), + .jtag_tdi_i ( st_pad2soc_signals.periph.jtag_tdi_i ), + .jtag_tdo_o ( st_soc2pad_signals.periph.jtag_tdo_o ), + .jtag_tdo_oe_o ( ), + .jtag_ot_tck_i ( st_pad2soc_signals.periph.jtag_ot_tclk_i ), + .jtag_ot_trst_ni ( st_pad2soc_signals.periph.jtag_ot_trst_ni ), + .jtag_ot_tms_i ( st_pad2soc_signals.periph.jtag_ot_tms_i ), + .jtag_ot_tdi_i ( st_pad2soc_signals.periph.jtag_ot_tdi_i ), + .jtag_ot_tdo_o ( st_soc2pad_signals.periph.jtag_ot_tdo_o ), + .jtag_ot_tdo_oe_o ( ), + .bootmode_ot_i ( bootmode_sec_isln_s ), + .jtag_safety_island_tck_i ( '0 ), + .jtag_safety_island_trst_ni ( '0 ), + .jtag_safety_island_tms_i ( '0 ), + .jtag_safety_island_tdi_i ( '0 ), + .jtag_safety_island_tdo_o ( ), + .bootmode_safe_isln_i ( bootmode_safe_isln_s ), + .secure_boot_i ( secure_boot ), + .uart_tx_o ( st_soc2pad_signals.periph.uart_tx_o ), + .uart_rx_i ( st_pad2soc_signals.periph.uart_rx_i ), + .uart_ot_tx_o ( ), + .uart_ot_rx_i ( '0 ), + .i2c_sda_o ( soc2pad_port_signals.periph.i2c.i2c_sda_o ), + .i2c_sda_i ( pad2soc_port_signals.periph.i2c.i2c_sda_i ), + .i2c_sda_en_o ( soc2pad_port_signals.periph.i2c.i2c_sda_oen_i ), + .i2c_scl_o ( soc2pad_port_signals.periph.i2c.i2c_scl_o ), + .i2c_scl_i ( pad2soc_port_signals.periph.i2c.i2c_scl_i ), + .i2c_scl_en_o ( soc2pad_port_signals.periph.i2c.i2c_scl_oen_i ), + .spih_sck_o ( spih_sck_o_s ), + .spih_sck_en_o ( ), + .spih_csb_o ( spih_csb_o_s ), + .spih_csb_en_o ( ), + .spih_sd_o ( spih_sd_o_s ), + .spih_sd_en_o ( spih_sd_en_o_s ), + .spih_sd_i ( spih_sd_i_s ), + // spi secd + .spih_ot_sck_o ( spih_ot_sck_o_s ), + .spih_ot_sck_en_o ( ), + .spih_ot_csb_o ( spih_ot_csb_o_s ), + .spih_ot_csb_en_o ( ), + .spih_ot_sd_o ( spih_ot_sd_o_s ), + .spih_ot_sd_en_o ( spih_ot_sd_en_o_s ), + .spih_ot_sd_i ( spih_ot_sd_i_s ), + // ethernet + .eth_rxck_i ( pad2soc_port_signals.periph.ethernet.eth_rxck_i ), + .eth_rxctl_i ( pad2soc_port_signals.periph.ethernet.eth_rxctl_i ), + .eth_rxd_i ( eth_rxd_i_s ), + .eth_md_i ( pad2soc_port_signals.periph.ethernet.eth_md_i ), + .eth_txck_o ( soc2pad_port_signals.periph.ethernet.eth_txck_o ), + .eth_txctl_o ( soc2pad_port_signals.periph.ethernet.eth_txctl_o ), + .eth_txd_o ( eth_txd_o_s ), + .eth_md_o ( soc2pad_port_signals.periph.ethernet.eth_md_o ), + .eth_md_oe ( soc2pad_port_signals.periph.ethernet.eth_md_oen_i ), + .eth_mdc_o ( soc2pad_port_signals.periph.ethernet.eth_mdc_o ), + .eth_rst_n_o ( soc2pad_port_signals.periph.ethernet.eth_rst_no ), + // can bus + .can_rx_i ( pad2soc_port_signals.periph.can.can_rx_i ), + .can_tx_o ( soc2pad_port_signals.periph.can.can_tx_o ), + // gpios + .gpio_i ( gpio_in_s ), + .gpio_o ( gpio_out_s ), + .gpio_en_o ( gpio_tx_en_s ), + // serial link + .slink_rcv_clk_i ( pad2soc_port_signals.periph.serial_link.slink_rcv_clk_i ), + .slink_rcv_clk_o ( soc2pad_port_signals.periph.serial_link.slink_rcv_clk_o ), + .slink_i ( serial_link_data_in_s ), + .slink_o ( serial_link_data_out_s ), + // hyperbus + .hyper_cs_no ( hyperbus_cs_no_s ), + .hyper_ck_o ( hyperbus_clk_o_s ), + .hyper_ck_no ( hyperbus_clk_no_s ), + .hyper_rwds_o ( hyperbus_rwds_out_s ), + .hyper_rwds_i ( hyperbus_rwds_in_s ), + .hyper_rwds_oe_o ( hyperbus_rwds_oe_s ), + .hyper_dq_i ( hyperbus_data_in_s ), + .hyper_dq_o ( hyperbus_data_out_s ), + .hyper_dq_oe_o ( hyperbus_data_oe_s ), + .hyper_reset_no ( hyperbus_rst_no_s ), + .tc_active_i ( pad2soc_port_signals.periph.tc.tc_active_i ), + .tc_clock_i ( pad2soc_port_signals.periph.tc.tc_clk_i ), + .tc_data_i ( pad2soc_port_signals.periph.tc.tc_data_i ), + .ptme_clk_o ( soc2pad_port_signals.periph.ptme.ptme_clk_o ), + .ptme_enc_o ( soc2pad_port_signals.periph.ptme.ptme_enc_o ), + .ptme_sync_o ( soc2pad_port_signals.periph.ptme.ptme_sync_o ), + .ptme_ext_clk_i ( pad2soc_port_signals.periph.ptme.ptme_ext_clk_i ), + .hpc_addr_o ( hpc_addr_out_s ), + .hpc_cmd_en_o ( soc2pad_port_signals.periph.hpc.hpc_cmd_en_o ), + .hpc_sample_o ( soc2pad_port_signals.periph.hpc.hpc_sample_o ), + .llc_line_o ( llc_line_out_s ), + .obt_ext_clk_i ( pad2soc_port_signals.periph.obt.obt_ext_clk_i ), + .obt_pps_in_i ( '0 ), + .obt_sync_out_o ( /* Not connected */ ), + .spw_data_i ( st_pad2soc_signals.periph.spw_data_i ), + .spw_strb_i ( st_pad2soc_signals.periph.spw_strb_i ), + .spw_data_o ( st_soc2pad_signals.periph.spw_data_o ), + .spw_strb_o ( st_soc2pad_signals.periph.spw_strb_o ), + .ext_reg_async_slv_req_o ( ext_reg_async_slv_req_src_out ), + .ext_reg_async_slv_ack_i ( ext_reg_async_slv_ack_src_in ), + .ext_reg_async_slv_data_o ( ext_reg_async_slv_data_src_out ), + .ext_reg_async_slv_req_i ( ext_reg_async_slv_req_src_in ), + .ext_reg_async_slv_ack_o ( ext_reg_async_slv_ack_src_out ), + .ext_reg_async_slv_data_i ( ext_reg_async_slv_data_src_in ), + // Debug Signals + .debug_signals_o ( ) + ); + + ////////////// + // Padframe // + ////////////// + + reg_cdc_dst #( + .CDC_KIND ( "cdc_4phase" ), + .req_t ( carfield_reg_req_t ), + .rsp_t ( carfield_reg_rsp_t ) + ) i_reg_cdc_dst_padframe ( + .dst_clk_i ( ref_clk ), + .dst_rst_ni ( ref_clk_pwr_on_rst_n ), + .dst_req_o ( padframe_refclk_cfg_reg_req ), + .dst_rsp_i ( padframe_refclk_cfg_reg_rsp ), + + .async_req_i ( ext_reg_async_slv_req_src_out[1] ), + .async_ack_o ( ext_reg_async_slv_ack_src_in[1] ), + .async_data_i( ext_reg_async_slv_data_src_out[1] ), + + .async_req_o ( ext_reg_async_slv_req_src_in[1] ), + .async_ack_i ( ext_reg_async_slv_ack_src_out[1] ), + .async_data_o( ext_reg_async_slv_data_src_in[1] ) + ); + + astral_padframe #( + .req_t ( carfield_reg_req_t ), + .resp_t ( carfield_reg_rsp_t ) + ) i_astral_padframe ( + .clk_i ( ref_clk ), + .rst_ni ( ref_clk_pwr_on_rst_n ), + .static_connection_signals_pad2soc ( st_pad2soc_signals ), + .static_connection_signals_soc2pad ( st_soc2pad_signals ), + .port_signals_pad2soc ( pad2soc_port_signals ), + .port_signals_soc2pad ( soc2pad_port_signals ), + // Landing Pads + .pad_periph_ref_clk_pad, + .pad_periph_fll_host_pad, + .pad_periph_fll_periph_pad, + .pad_periph_fll_alt_pad, + .pad_periph_fll_rt_pad, + .pad_periph_fll_bypass_pad, + .pad_periph_pwr_on_rst_n_pad, + .pad_periph_test_mode_pad, + .pad_periph_boot_mode_0_pad, + .pad_periph_boot_mode_1_pad, + .pad_periph_ot_boot_mode_pad, + .pad_periph_secure_boot_pad, + .pad_periph_jtag_tclk_pad, + .pad_periph_jtag_trst_n_pad, + .pad_periph_jtag_tms_pad, + .pad_periph_jtag_tdi_pad, + .pad_periph_jtag_tdo_pad, + .pad_periph_jtag_ot_tclk_pad, + .pad_periph_jtag_ot_trst_ni_pad, + .pad_periph_jtag_ot_tms_pad, + .pad_periph_jtag_ot_tdi_pad, + .pad_periph_jtag_ot_tdo_pad, + .pad_periph_hyper_cs_0_n_pad, + .pad_periph_hyper_cs_1_n_pad, + .pad_periph_hyper_ck_pad, + .pad_periph_hyper_ck_n_pad, + .pad_periph_hyper_rwds_pad, + .pad_periph_hyper_dq_0_pad, + .pad_periph_hyper_dq_1_pad, + .pad_periph_hyper_dq_2_pad, + .pad_periph_hyper_dq_3_pad, + .pad_periph_hyper_dq_4_pad, + .pad_periph_hyper_dq_5_pad, + .pad_periph_hyper_dq_6_pad, + .pad_periph_hyper_dq_7_pad, + .pad_periph_hyper_reset_n_pad, + .pad_periph_spw_data_in_pad, + .pad_periph_spw_strb_in_pad, + .pad_periph_spw_data_out_pad, + .pad_periph_spw_strb_out_pad, + .pad_periph_uart_tx_out_pad, + .pad_periph_uart_rx_in_pad, + .pad_periph_muxed_v_00_pad, + .pad_periph_muxed_v_01_pad, + .pad_periph_muxed_v_02_pad, + .pad_periph_muxed_v_03_pad, + .pad_periph_muxed_v_04_pad, + .pad_periph_muxed_v_05_pad, + .pad_periph_muxed_v_06_pad, + .pad_periph_muxed_v_07_pad, + .pad_periph_muxed_v_08_pad, + .pad_periph_muxed_v_09_pad, + .pad_periph_muxed_v_10_pad, + .pad_periph_muxed_v_11_pad, + .pad_periph_muxed_v_12_pad, + .pad_periph_muxed_v_13_pad, + .pad_periph_muxed_v_14_pad, + .pad_periph_muxed_v_15_pad, + .pad_periph_muxed_v_16_pad, + .pad_periph_muxed_v_17_pad, + .pad_periph_muxed_h_00_pad, + .pad_periph_muxed_h_01_pad, + .pad_periph_muxed_h_02_pad, + .pad_periph_muxed_h_03_pad, + // Config Interface + .config_req_i ( padframe_refclk_cfg_reg_req ), + .config_rsp_o ( padframe_refclk_cfg_reg_rsp ) + ); + +endmodule: astral_wrap diff --git a/hw/carfield.sv b/hw/carfield.sv index f6aba4f8..7d08bad9 100644 --- a/hw/carfield.sv +++ b/hw/carfield.sv @@ -43,6 +43,8 @@ module carfield input logic periph_clk_i, // accelerator and island clock input logic alt_clk_i, + // secure domain clock + input logic secd_clk_i, // external reference clock for timers (CLINT, islands) input logic rt_clk_i, @@ -142,6 +144,26 @@ module carfield output logic [HypNumPhys-1:0][7:0] hyper_dq_o, output logic [HypNumPhys-1:0] hyper_dq_oe_o, output logic [HypNumPhys-1:0] hyper_reset_no, + // TCTM Interface + input logic tc_active_i, + input logic tc_clock_i, + input logic tc_data_i, + output logic ptme_clk_o, + output logic ptme_enc_o, + output logic ptme_sync_o, + input logic ptme_ext_clk_i, + output logic [2:0] hpc_addr_o, + output logic hpc_cmd_en_o, + output logic hpc_sample_o, + output logic [1:0] llc_line_o, + input logic obt_ext_clk_i, + input logic obt_pps_in_i, + output logic obt_sync_out_o, + // SpW Interface + input logic spw_data_i, + input logic spw_strb_i, + output logic spw_data_o, + output logic spw_strb_o, `ifdef GEN_NO_HYPERBUS // LLC interface output logic [LlcArWidth-1:0] llc_ar_data, @@ -501,11 +523,13 @@ end // Clock Multiplexing for each sub block localparam int unsigned DomainClkDivValueWidth = 24; +// One FLL is for the RT clock which does not go through the MUX. +localparam int unsigned ClkMuxNumInputs = carfield_pkg::NumFll-1; typedef logic [DomainClkDivValueWidth-1:0] domain_clk_div_value_t; logic [NumDomains-1:0] domain_clk; logic [NumDomains-1:0] domain_clk_en; logic [NumDomains-1:0] domain_clk_gated; -logic [NumDomains-1:0][1:0] domain_clk_sel; +logic [NumDomains-1:0][$clog2(ClkMuxNumInputs)-1:0] domain_clk_sel; logic [NumDomains-1:0] domain_clk_div_changed; logic [NumDomains-1:0] domain_clk_div_decoupled_valid, domain_clk_div_decoupled_ready; @@ -533,14 +557,14 @@ logic [NumDomains-1:0] rsts_n; for (genvar i = 0; i < NumDomains; i++) begin : gen_domain_clock_mux clk_mux_glitch_free #( - .NUM_INPUTS(3) + .NUM_INPUTS(carfield_pkg::NumFll-1) ) i_clk_mux ( - .clks_i ( {periph_clk_i, alt_clk_i, host_clk_i} ), - .test_clk_i ( 1'b0 ), - .test_en_i ( 1'b0 ), - .async_rstn_i ( host_pwr_on_rst_n ), - .async_sel_i ( domain_clk_sel[i] ), - .clk_o ( domain_clk[i] ) + .clks_i ( {secd_clk_i, periph_clk_i, alt_clk_i, host_clk_i} ), + .test_clk_i ( 1'b0 ), + .test_en_i ( 1'b0 ), + .async_rstn_i ( host_pwr_on_rst_n ), + .async_sel_i ( domain_clk_sel[i] ), + .clk_o ( domain_clk[i] ) ); // The register file does not support back pressure directly. I.e the hardware side cannot tell @@ -1356,7 +1380,7 @@ localparam pulp_cluster_package::pulp_cluster_cfg_t PulpClusterCfg = '{ DmaNumOutstandingBursts: 8, DmaBurstLength: 256, NumMstPeriphs: 1, - NumSlvPeriphs: 11, + NumSlvPeriphs: 12, ClusterAlias: 1, ClusterAliasBase: 'h0, NumSyncStages: 3, @@ -1656,10 +1680,14 @@ if (CarfieldIslandsCfg.spatz.enable) begin : gen_spatz_cluster assign spatzcl_mbox_intr = hostd_spatzcl_mbox_intr_ored | safed_spatzcl_mbox_intr; // verilog_lint: waive-stop line-length end else begin : gen_no_spatz_cluster + assign spatzcl_mbox_intr = '0; + assign spatzcl_timer_intr = '0; assign car_regs_hw2reg.spatz_cluster_isolate_status.d = 1'b0; assign car_regs_hw2reg.spatz_cluster_isolate_status.de = 1'b0; assign car_regs_hw2reg.spatz_cluster_busy.d = '0; assign car_regs_hw2reg.spatz_cluster_busy.de = 1'b0; + assign safed_spatzcl_mbox_intr = '0; + assign hostd_spatzcl_mbox_intr = '0; assign spatzcl_hostd_mbox_intr = '0; assign spatzcl_safed_mbox_intr = '0; assign spatz_rst_n = '0; @@ -1939,11 +1967,11 @@ mailbox_unit #( ); // Carfield peripherals +logic eth_clk; if (CarfieldIslandsCfg.ethernet.enable) begin : gen_ethernet localparam int unsigned EthAsyncIdx = CarfieldRegBusSlvIdx.ethernet-NumSyncRegSlv; localparam int unsigned EthDivWidth = 20; localparam int unsigned DefaultEthClkDivValue = 1; - logic eth_clk; logic eth_clk_decoupled_valid, eth_clk_decoupled_ready; assign ethernet_isolate_req = car_regs_reg2hw.periph_isolate.q; @@ -1960,6 +1988,17 @@ if (CarfieldIslandsCfg.ethernet.enable) begin : gen_ethernet .data_o ( ), .busy_o ( ) ); + // The Ethernet RGMII interfaces mandates a clock of 125MHz (in 1GBit mode) for both TX and RX + // clocks. We generate a 125MHz clock starting from the `periph_clk`. The (integer) division value + // is SW-programmable. + localparam int unsigned EthRgmiiPhyClkDivWidth = 20; + // We assume a peripheral clock of 250MHz to get the 125MHz clock for the RGMII interface. Hence, + // the default division value after PoR is 250/125. + localparam int unsigned EthRgmiiPhyClkDivDefaultValue = 2; + logic [EthRgmiiPhyClkDivWidth-1:0] eth_rgmii_phy_clk_div_value; + logic eth_rgmii_phy_clk_div_value_valid; + logic eth_rgmii_phy_clk_div_value_ready; + logic eth_rgmii_phy_clk0; clk_int_div #( .DIV_VALUE_WIDTH ( EthDivWidth ), @@ -2050,6 +2089,7 @@ if (CarfieldIslandsCfg.ethernet.enable) begin : gen_ethernet .eth_rx_irq_o ( car_eth_rx_intr ) ); end else begin : gen_no_ethernet + assign eth_clk = '0; assign ethernet_isolate_req = '0; assign car_eth_rx_intr = '0; assign eth_md_o = '0; @@ -2455,6 +2495,308 @@ if (CarfieldIslandsCfg.periph.enable) begin: gen_periph // Handle with care... assign can_tx_o = '0; assign apb_mst_rsp[CanIdx] = '0; end + + // Telemetry and Telecomand IP (Streamer) + if (carfield_configuration::StreamerEnable) begin: gen_streamer + localparam int unsigned ZeroBits = Cfg.AddrWidth - AxiNarrowAddrWidth; + localparam int unsigned StreamerDivisionValueWidth = 6; // Divide up to 63 + localparam int unsigned NrStreamerApbSlaves = 2; // 0: APB2Reg; 1: APB + logic [Cfg.AddrWidth-1:0] mask_address; + logic streamer_clk; + logic streamer_clk_decoupled_valid, streamer_clk_decoupled_ready; + logic streamer_apb_demux_sel; + logic [StreamerDivisionValueWidth-1:0] streamer_clk_div_value; + + carfield_apb_req_t apb_async_req; + carfield_apb_rsp_t apb_async_rsp; + + carfield_apb_req_t [NrStreamerApbSlaves-1:0] apb_streamer_req; + carfield_apb_rsp_t [NrStreamerApbSlaves-1:0] apb_streamer_rsp; + + lossy_valid_to_stream #( + .T ( logic[StreamerDivisionValueWidth-1:0] ) + ) i_streamer_decouple ( + .clk_i ( periph_clk ), + .rst_ni ( periph_pwr_on_rst_n ), + .valid_i ( car_regs_reg2hw.streamer_clk_div_value.qe ), + .data_i ( car_regs_reg2hw.streamer_clk_div_value.q ), + .valid_o ( streamer_clk_decoupled_valid ), + .ready_i ( streamer_clk_decoupled_ready ), + .data_o ( streamer_clk_div_value ), + .busy_o ( ) + ); + + clk_int_div #( + .DIV_VALUE_WIDTH(StreamerDivisionValueWidth), + .DEFAULT_DIV_VALUE(1), + .ENABLE_CLOCK_IN_RESET(1) + ) i_streamer_clk_div ( + .clk_i ( periph_clk ), + .rst_ni ( periph_pwr_on_rst_n ), + .en_i ( car_regs_reg2hw.streamer_clk_div_enable.q ), + .test_mode_en_i ( test_mode_i ), + .div_i ( streamer_clk_div_value ), + .div_valid_i ( streamer_clk_decoupled_valid ), + .div_ready_o ( streamer_clk_decoupled_ready ), + .clk_o ( streamer_clk ), + .cycl_count_o ( ) + ); + + REG_BUS #( + .ADDR_WIDTH ( AxiNarrowAddrWidth ), + .DATA_WIDTH ( AxiNarrowDataWidth ) + ) reg_bus_streamer ( streamer_clk ); + + (* no_ungroup *) + (* no_boundary_optimization *) + apb_cdc #( + .LogDepth ( LogDepth ), + .req_t ( carfield_apb_req_t ), + .resp_t ( carfield_apb_rsp_t ), + .addr_t ( car_nar_addrw_t ), + .data_t ( car_nar_dataw_t ), + .strb_t ( car_nar_strb_t ) + ) i_streamer_apb_cdc ( + .src_pclk_i ( periph_clk ), + .src_preset_ni ( periph_pwr_on_rst_n ), + .src_req_i ( apb_mst_req[StreamerIdx] ), + .src_resp_o ( apb_mst_rsp[StreamerIdx] ), + .dst_pclk_i ( streamer_clk ), + .dst_preset_ni ( periph_pwr_on_rst_n ), + .dst_req_o ( apb_async_req ), + .dst_resp_i ( apb_async_rsp ) + ); + + assign streamer_apb_demux_sel = + (apb_async_req.paddr < carfield_configuration::StreamerApbBase) ? 'h0 : 'h1; + + apb_demux #( + .NoMstPorts ( NrStreamerApbSlaves ), + .req_t ( carfield_apb_req_t ), + .resp_t ( carfield_apb_rsp_t ) + ) i_streamer_apb_demux ( + .slv_req_i ( apb_async_req ), + .slv_resp_o ( apb_async_rsp ), + .mst_req_o ( apb_streamer_req ), + .mst_resp_i ( apb_streamer_rsp ), + .select_i ( streamer_apb_demux_sel ) + ); + + apb_to_reg i_streamer_apb_to_reg ( + .clk_i ( streamer_clk ), + .rst_ni ( periph_pwr_on_rst_n ), + .penable_i ( apb_streamer_req[0].penable ), + .pwrite_i ( apb_streamer_req[0].pwrite ), + .paddr_i ( apb_streamer_req[0].paddr ), + .psel_i ( apb_streamer_req[0].psel ), + .pwdata_i ( apb_streamer_req[0].pwdata ), + .prdata_o ( apb_streamer_rsp[0].prdata ), + .pready_o ( apb_streamer_rsp[0].pready ), + .pslverr_o ( apb_streamer_rsp[0].pslverr ), + .reg_o ( reg_bus_streamer ) + ); + + assign reg_bus_streamer.error = '0; + assign mask_address = {{ZeroBits{1'b0}}, reg_bus_streamer.addr}; + + TASI_top i_tctm_streamer ( + .SYS_CLK (streamer_clk), + .ASYNC_RST_N (periph_rst_n), + .APB_PADD (apb_streamer_req[1].paddr), // : in + .APB_PENABLE (apb_streamer_req[1].penable), // : in + .APB_PPROT (3'b0), // : in + .APB_PSEL (apb_streamer_req[1].psel), // : in + .APB_PSTROBE (4'b1111), // : in + .APB_PWDATA (apb_streamer_req[1].pwdata), // : in + .APB_PWRITE (apb_streamer_req[1].pwrite), // : in + .APB_PRDATA (apb_streamer_rsp[1].prdata), // : out + .APB_PREADY (apb_streamer_rsp[1].pready), // : out + .APB_PSLVERR (apb_streamer_rsp[1].pslverr), // : out + .REG_ADDR (mask_address), // : in + .REG_M_ID (3'b001), // : in + .REG_VALID (reg_bus_streamer.valid), // : in + .REG_WDATA (reg_bus_streamer.wdata), // : in + .REG_WRITE (reg_bus_streamer.write), // : in + .REG_RDATA (reg_bus_streamer.rdata), // : out + .REG_READY (reg_bus_streamer.ready), // : out + .AUEND_SDU (1'b0), // : in + .AUR_SDU (1'b0), // : in + .BIT_LOCKn (3'b0), // : in + .CLCW_C_B (1'b0), // : in + .CLCW_S_B (1'b0), // : in + .CONF_REG_ACC_ACK (1'b1), // : in + .CPDU_INPROGRESS (1'b0), // : in + .EXT_OBT_CLK (obt_ext_clk_i), // : in + .INT_PPS_IN (obt_pps_in_i), // : in + .RFAVN (1'b0), // : in + .SDU_WRONG_LENGTH (1'b0), // : in + .SYNC_RST_N (1'b1), // : in + .TC_ACTIVE (tc_active_i), // : in + .TC_CLOCK (tc_clock_i), // : in + .TC_DATA (tc_data_i), // : in + .TME_CLCW_FSR_DAT_FROM_REM_PDEC_SEC (1'b0), // : in + .TME_ENCR_UNENC_CLK (1'b0), // : in + .TME_ENCR_UNENC_OUT (1'b0), // : in + .TME_ENCR_UNENC_SYNC (1'b0), // : in + .TME_EXT_CLK (ptme_ext_clk_i), // : in + .TME_FSR_DAT_FROM_LOC_SEC (1'b0), // : in + .ANACOND_LLC_RESET (/* Not Connected */), // : out + .AUTH_SEL (/* Not Connected */), // : out + .BUSY (/* Not Connected */), // : out + + .CADUFrameMark (/* Not Connected */), // : out + .CLCWD_B (/* Not Connected */), // : out + .CONF_REG_ACC_REQ (/* Not Connected */), // : out + + .CONF_REG_ADDR_OFFSET (/* Not Connected */), // : out + + .CONF_REG_GROUP_ADDR (/* Not Connected */), // : out + + .CONF_REG_WDATA (/* Not Connected */), // : out + + .CROSSED_LCL_RESET (/* Not Connected */), // : out + .CROSSED_POWER_REARM_OUT (llc_line_o[1]), // : out + .CROSSED_RESET_OUT (/* Not Connected */), // : out + .FPEMO (/* Not Connected */), // : out + .FPRELM (/* Not Connected */), // : out + .GENERAL_INTERRUPT (car_regs_hw2reg.streamer_general_irq.d), // : out + .HPC_ADDR (hpc_addr_o), // : out + .HPC_CMD_EN (hpc_cmd_en_o), // : out + .HPC_INTERRUPT_SOURCES (/* Not Connected */), // : out + .HPC_PROTECTIONn (/* Not Connected */), // : out + .HPC_SMP (hpc_sample_o), // : out + .INH_MMA (/* Not Connected */), // : out + .LLC_INTERRUPT_SOURCES (/* Not Connected */), // : out + .LLC_IRQ_FORCE_REGISTER (/* Not Connected */), // : out + .LOC_AOCS_LCL_PRI_BUS_ON_OFFn (/* Not Connected */), // : out + .LOC_AOCS_ON_OFFn (/* Not Connected */), // : out + .LOC_HK_ON_OFFn (/* Not Connected */), // : out + .LOC_IO_ON_OFFn (/* Not Connected */), // : out + .LOC_MCPM_ON_OFFn (/* Not Connected */), // : out + .LOC_MCPM_RESET (llc_line_o[0]), // : out + .LVDS_IF_TME_ENC_IOUT (/* Not Connected */), // : out + .LVDS_IF_TME_ENC_IQCLK (/* Not Connected */), // : out + .LVDS_IF_TME_ENC_QOUT (/* Not Connected */), // : out + .PP0Busy_N (/* Not Connected */), // : out + //.PP1Busy_N (/* Not Connected */), // : out + .PP2Busy_N (/* Not Connected */), // : out + .PP3Busy_N (/* Not Connected */), // : out + .PP4Busy_N (/* Not Connected */), // : out + .PP5Busy_N (/* Not Connected */), // : out + .PP6Busy_N (/* Not Connected */), // : out + .PPS_OUT (/* Not Connected */), // : out + .REM_AOCS_LCL_PRI_BUS_ON_OFFn (/* Not Connected */), // : out + .REM_AOCS_ON_OFFn (/* Not Connected */), // : out + .REM_HK_ON_OFFn (/* Not Connected */), // : out + .REM_IO_ON_OFFn (/* Not Connected */), // : out + .REM_MCPM_ON_OFFn (/* Not Connected */), // : out + .RM_RECOVERY_RESET (/* Not Connected */), // : out + .RM_RESET (/* Not Connected */), // : out + .RS422_IF_TME_ENC_CLK (ptme_clk_o), // : out + .RS422_IF_TME_ENC_OUT (ptme_enc_o), // : out + .RS422_IF_TME_ENC_SYNC (ptme_sync_o), // : out + .SYNC_TO_EXT_IF (obt_sync_out_o), // : out + .TC_ONDOING (/* Not Connected */), // : out + .TC_STANDARD (/* Not Connected */), // : out + .TME_CLR_UNENC_CLK (/* Not Connected */), // : out + .TME_CLR_UNENC_EODF_TO_ADAM (/* Not Connected */), // : out + .TME_CLR_UNENC_EODF_TO_EXT (/* Not Connected */), // : out + .TME_CLR_UNENC_OUT (/* Not Connected */), // : out + .TME_CLR_UNENC_SYNC (/* Not Connected */), // : out + .TME_Cn_S (/* Not Connected */), // : out + .TME_REM_CLCWn_FSR_SEL (/* Not Connected */), // : out + .TME_TIME_STROBE_TO_REM_OBT (/* Not Connected */), // : out + .TME_UNENC_SYNC (/* Not Connected */) // : out + ); + + assign car_regs_hw2reg.streamer_general_irq.de = '1; + end else begin: gen_no_streamer + assign car_regs_hw2reg.streamer_general_irq.de = '0; + assign car_regs_hw2reg.streamer_general_irq.d = '0; + end + + // SpaceWire IP + if (carfield_configuration::SpaceWireEnable) begin: gen_spw + + localparam int unsigned SpWZeroBits = Cfg.AddrWidth - AxiNarrowAddrWidth; + localparam int unsigned NrSpaceWireApbSlaves = 2; // 0: APB2Reg; 1: APB + logic spw_apb_demux_sel; + logic [Cfg.AddrWidth-1:0] spw_address; + + carfield_apb_req_t [NrSpaceWireApbSlaves-1:0] apb_spw_req; + carfield_apb_rsp_t [NrSpaceWireApbSlaves-1:0] apb_spw_rsp; + + REG_BUS #( + .ADDR_WIDTH ( AxiNarrowAddrWidth ), + .DATA_WIDTH ( AxiNarrowDataWidth ) + ) reg_bus_spw ( periph_clk ); + + assign spw_apb_demux_sel = + (apb_mst_req[SpaceWireIdx].paddr < carfield_configuration::SpaceWireApbBase) ? 'h0 : 'h1; + + apb_demux #( + .NoMstPorts ( NrSpaceWireApbSlaves ), + .req_t ( carfield_apb_req_t ), + .resp_t ( carfield_apb_rsp_t ) + ) i_spw_apb_demux ( + .slv_req_i ( apb_mst_req[SpaceWireIdx] ), + .slv_resp_o ( apb_mst_rsp[SpaceWireIdx] ), + .mst_req_o ( apb_spw_req ), + .mst_resp_i ( apb_spw_rsp ), + .select_i ( spw_apb_demux_sel ) + ); + + apb_to_reg i_spw_apb_to_reg ( + .clk_i ( periph_clk ), + .rst_ni ( periph_rst_n ), + .penable_i ( apb_spw_req[0].penable ), + .pwrite_i ( apb_spw_req[0].pwrite ), + .paddr_i ( apb_spw_req[0].paddr ), + .psel_i ( apb_spw_req[0].psel ), + .pwdata_i ( apb_spw_req[0].pwdata ), + .prdata_o ( apb_spw_rsp[0].prdata ), + .pready_o ( apb_spw_rsp[0].pready ), + .pslverr_o ( apb_spw_rsp[0].pslverr ), + .reg_o ( reg_bus_spw ) + ); + + assign reg_bus_spw.error = '0; + + assign spw_address = {{SpWZeroBits{1'b0}}, reg_bus_spw.addr}; + + spw_astr_top i_spacewire ( + .ASYNC_RSTN (periph_rst_n), + .SYNC_RSTN (periph_rst_n), + .SYS_CLK (periph_clk), + .SPW_DATA_IN (spw_data_i), + .SPW_STROBE_IN (spw_strb_i), + .SPW_DATA_OUT (spw_data_o), + .SPW_STROBE_OUT (spw_strb_o), + .REG_ADDR_i (spw_address), + .REG_VALID_i (reg_bus_spw.valid), + .REG_WDATA_i (reg_bus_spw.wdata), + .REG_WRITE_i (reg_bus_spw.write), + .REG_RDATA_o (reg_bus_spw.rdata), + .REG_READY_o (reg_bus_spw.ready), + .APB_PADD (apb_spw_req[1].paddr), + .APB_PSEL (apb_spw_req[1].psel), + .APB_PENABLE (apb_spw_req[1].penable), + .APB_PWDATA (apb_spw_req[1].pwdata), + .APB_PWRITE (apb_spw_req[1].pwrite), + .APB_PRDATA (apb_spw_rsp[1].prdata), + .APB_PREADY (apb_spw_rsp[1].pready), + .APB_PSLVERR (apb_spw_rsp[1].pslverr), + .GENERAL_INTERRUPT_o (car_regs_hw2reg.spw_general_irq.d) + ); + assign car_regs_hw2reg.spw_general_irq.de = '1; + + end else begin: gen_no_spw + assign spw_data_o = '0; + assign spw_strb_o = '0; + assign car_regs_hw2reg.spw_general_irq.d = '0; + assign car_regs_hw2reg.spw_general_irq.de = '0; + end + end else begin: gen_no_periph assign car_regs_hw2reg.periph_isolate_status.d = '0; assign car_regs_hw2reg.periph_isolate_status.de = '0; diff --git a/hw/carfield_chip_pkg.sv b/hw/carfield_chip_pkg.sv new file mode 100644 index 00000000..fe5cac2f --- /dev/null +++ b/hw/carfield_chip_pkg.sv @@ -0,0 +1,35 @@ +// Copyright 2023 ETH Zurich and University of Bologna. +// Solderpad Hardware License, Version 0.51, see LICENSE for details. +// SPDX-License-Identifier: SHL-0.51 +// +// Alessandro Ottaviano + +`include "cheshire/typedef.svh" + +/// Carfield chip specific parameters +package carfield_chip_pkg; + +// import pll_digital_pkg::*; + +// localparam int unsigned NumPlls = pll_digital_pkg::NPLLs; + +typedef enum int { + HostDomainClkIdx = 'd0, + PeriphDomainClkIdx = 'd1, + AltDomainClkIdx = 'd2, + SecureDomainClkIdx = 'd3 +} carfield_clocks_e; + +// PULP Platform manufacturer and default Carfield Pll part number +// JTAG ID code: +// LSB [0]: 1'h1 +// PULP Platform Manufacturer [11:1]: 11'h6d9 +// Part Number [27:12]: 16'habc0 --> TBD! +// Version [31:28]: 4'h1 +localparam int unsigned CarfieldPllJtagIdCode = 32'h1_abc0_db3; + +// Padframe configuration +parameter int unsigned PAD_CFG_ADDR = 32'h2100_0000; +parameter int unsigned PAD_CFG_LEN = 32'h1000; + +endpackage diff --git a/hw/carfield_pkg.sv b/hw/carfield_pkg.sv index c9f792dc..19614d03 100644 --- a/hw/carfield_pkg.sv +++ b/hw/carfield_pkg.sv @@ -212,8 +212,8 @@ typedef struct packed { byte_bt pcrs; byte_bt pll; byte_bt padframe; - byte_bt l2ecc; byte_bt ethernet; + byte_bt l2ecc; } carfield_regbus_slave_idx_t; // Generate the number of AXI slave devices to be connected to the @@ -322,6 +322,17 @@ function automatic int unsigned gen_carfield_domains(islands_cfg_t island_cfg); return ret; endfunction +// Generate number of clock sources +function automatic int unsigned gen_carfield_clock_srcs(islands_cfg_t island_cfg); + int unsigned ret = 2; // Number of clock sources starts from 2 (Host + rt clock) + if (island_cfg.safed.enable ) begin ret++; end + if (island_cfg.periph.enable ) begin ret++; end + if (island_cfg.spatz.enable ) begin ret++; end + if (island_cfg.pulp.enable ) begin ret++; end + if (island_cfg.secured.enable ) begin ret++; end + return ret; +endfunction + localparam islands_cfg_t CarfieldIslandsCfg = '{ l2_port0: '{L2Port0Enable, L2Port0Base, L2Port0Size}, l2_port1: '{L2Port1Enable, L2Port1Base, L2Port1Size}, @@ -352,6 +363,8 @@ localparam regbus_struct_t CarfieldRegBusMap = carfield_gen_regbus_map(NumTotalR localparam int unsigned CarfieldNumDomains = gen_carfield_domains(CarfieldIslandsCfg); +localparam int unsigned NumFll = gen_carfield_clock_srcs(CarfieldIslandsCfg); + typedef struct { int unsigned clock_div_value[CarfieldNumDomains]; } carfield_clk_div_values_t; @@ -373,6 +386,7 @@ typedef struct packed { byte_bt secured; byte_bt safed; byte_bt periph; + byte_bt ethernet; } carfield_domain_idx_t; function automatic carfield_domain_idx_t gen_domain_idx(islands_cfg_t island_cfg); @@ -520,12 +534,14 @@ localparam dm::hartinfo_t [MaxHartId:0] SafetyIslandExtHartinfo = default: '0 }; localparam int unsigned SafetyIslandIrqs = SafetyIslandCfg.NumInterrupts; + localparam safety_island_pkg::bootmode_e SafetyIslandPreloaded = safety_island_pkg::Preloaded; `else localparam int unsigned SafetyIslandCfg = '0; localparam bit [31:0] SafedDebugOffs = 0; localparam int unsigned SafetyIslandMemOffset = 0; localparam int unsigned SafetyIslandPerOffset = 0; localparam int unsigned SafetyIslandIrqs = 1; + localparam int unsigned SafetyIslandPreloaded = 0; `endif // Compute the number of atomic MSBs depending on the configuration @@ -588,6 +604,7 @@ localparam cheshire_cfg_t CarfieldCfgDefault = '{ AxiUserErrLsb : 4, RegMaxReadTxns : 8, RegMaxWriteTxns : 8, + CorePostCut : 1, RegAmoNumCuts : 1, RegAmoPostCut : 1, RegAdaptMemCut : 1, @@ -754,14 +771,16 @@ typedef logic [ AxiNarrowDataWidth-1:0] car_nar_dataw_t; typedef logic [ AxiNarrowStrobe-1:0] car_nar_strb_t; // APB Mapping -localparam int unsigned NumApbMst = 5; +localparam int unsigned NumApbMst = 7; typedef enum int { SystemTimerIdx = 'd0, AdvancedTimerIdx = 'd1, SystemWdtIdx = 'd2, CanIdx = 'd3, - HyperBusIdx = 'd4 + HyperBusIdx = 'd4, + StreamerIdx = 'd5, + SpaceWireIdx = 'd6 } carfield_peripherals_e; // Address map of peripheral system @@ -772,7 +791,7 @@ typedef struct packed { } carfield_addr_map_rule_t; localparam carfield_addr_map_rule_t [NumApbMst-1:0] PeriphApbAddrMapRule = '{ - // 0: System Timer + // 0: System Timer '{ idx: SystemTimerIdx, start_addr: SystemTimerBase, end_addr: SystemTimerBase + SystemTimerSize }, // 1: Advanced Timer @@ -786,7 +805,13 @@ localparam carfield_addr_map_rule_t [NumApbMst-1:0] PeriphApbAddrMapRule = '{ end_addr: CanBase + CanSize }, // 4: Hyperbus '{ idx: HyperBusIdx, start_addr: HyperBusBase, - end_addr: HyperBusBase + HyperBusSize } + end_addr: HyperBusBase + HyperBusSize }, + // 5: Streamer + '{ idx: StreamerIdx, start_addr: StreamerCfgBase, + end_addr: StreamerApbBase + StreamerApbSize }, + // 6: SpW + '{ idx: SpaceWireIdx, start_addr: SpaceWireRegBase, + end_addr: SpaceWireApbBase + SpaceWireApbSize } }; // Narrow reg types diff --git a/hw/configs/carfield_l2dual_periph.sv b/hw/configs/carfield_l2dual_periph.sv index 57244739..978aa3b3 100644 --- a/hw/configs/carfield_l2dual_periph.sv +++ b/hw/configs/carfield_l2dual_periph.sv @@ -62,6 +62,18 @@ localparam doub_bt SystemWatchdogSize = 'h00001000; // Hyperbus Config localparam doub_bt HyperBusBase = 'h20009000; localparam doub_bt HyperBusSize = 'h00001000; +// Streamer +localparam bit StreamerEnable = 0; +localparam doub_bt StreamerCfgBase = 'h20009000; +localparam doub_bt StreamerCfgSize = 'h00008000; +localparam doub_bt StreamerApbBase = StreamerCfgBase + StreamerCfgSize; +localparam doub_bt StreamerApbSize = 'h00008000; +// SpaceWire +localparam bit SpaceWireEnable = 0; +localparam doub_bt SpaceWireRegBase = 'h20019000; +localparam doub_bt SpaceWireRegSize = 'h00000100; +localparam doub_bt SpaceWireApbBase = SpaceWireRegBase + SpaceWireRegSize; +localparam doub_bt SpaceWireApbSize = 'h00000F00; /************************ * RegBus Configuration * ***********************/ diff --git a/hw/configs/carfield_l2dual_pulp_periph.sv b/hw/configs/carfield_l2dual_pulp_periph.sv index de8683e3..9a5b157d 100644 --- a/hw/configs/carfield_l2dual_pulp_periph.sv +++ b/hw/configs/carfield_l2dual_pulp_periph.sv @@ -62,6 +62,18 @@ localparam doub_bt SystemWatchdogSize = 'h00001000; // Hyperbus Config localparam doub_bt HyperBusBase = 'h20009000; localparam doub_bt HyperBusSize = 'h00001000; +// Streamer +localparam bit StreamerEnable = 0; +localparam doub_bt StreamerCfgBase = 'h20009000; +localparam doub_bt StreamerCfgSize = 'h00008000; +localparam doub_bt StreamerApbBase = StreamerCfgBase + StreamerCfgSize; +localparam doub_bt StreamerApbSize = 'h00008000; +// SpaceWire +localparam bit SpaceWireEnable = 0; +localparam doub_bt SpaceWireRegBase = 'h20019000; +localparam doub_bt SpaceWireRegSize = 'h00000100; +localparam doub_bt SpaceWireApbBase = SpaceWireRegBase + SpaceWireRegSize; +localparam doub_bt SpaceWireApbSize = 'h00000F00; /************************ * RegBus Configuration * ***********************/ diff --git a/hw/configs/carfield_l2dual_safe_periph.sv b/hw/configs/carfield_l2dual_safe_periph.sv index 814f2ada..89500364 100644 --- a/hw/configs/carfield_l2dual_safe_periph.sv +++ b/hw/configs/carfield_l2dual_safe_periph.sv @@ -62,6 +62,18 @@ localparam doub_bt SystemWatchdogSize = 'h00001000; // Hyperbus Config localparam doub_bt HyperBusBase = 'h20009000; localparam doub_bt HyperBusSize = 'h00001000; +// Streamer +localparam bit StreamerEnable = 0; +localparam doub_bt StreamerCfgBase = 'h20009000; +localparam doub_bt StreamerCfgSize = 'h00008000; +localparam doub_bt StreamerApbBase = StreamerCfgBase + StreamerCfgSize; +localparam doub_bt StreamerApbSize = 'h00008000; +// SpaceWire +localparam bit SpaceWireEnable = 0; +localparam doub_bt SpaceWireRegBase = 'h20019000; +localparam doub_bt SpaceWireRegSize = 'h00000100; +localparam doub_bt SpaceWireApbBase = SpaceWireRegBase + SpaceWireRegSize; +localparam doub_bt SpaceWireApbSize = 'h00000F00; /************************ * RegBus Configuration * ***********************/ diff --git a/hw/configs/carfield_l2dual_safe_pulp_periph.sv b/hw/configs/carfield_l2dual_safe_pulp_periph.sv index c46fac5d..5029464a 100644 --- a/hw/configs/carfield_l2dual_safe_pulp_periph.sv +++ b/hw/configs/carfield_l2dual_safe_pulp_periph.sv @@ -62,6 +62,18 @@ localparam doub_bt SystemWatchdogSize = 'h00001000; // Hyperbus Config localparam doub_bt HyperBusBase = 'h20009000; localparam doub_bt HyperBusSize = 'h00001000; +// Streamer +localparam bit StreamerEnable = 0; +localparam doub_bt StreamerCfgBase = 'h20009000; +localparam doub_bt StreamerCfgSize = 'h00008000; +localparam doub_bt StreamerApbBase = StreamerCfgBase + StreamerCfgSize; +localparam doub_bt StreamerApbSize = 'h00008000; +// SpaceWire +localparam bit SpaceWireEnable = 0; +localparam doub_bt SpaceWireRegBase = 'h20019000; +localparam doub_bt SpaceWireRegSize = 'h00000100; +localparam doub_bt SpaceWireApbBase = SpaceWireRegBase + SpaceWireRegSize; +localparam doub_bt SpaceWireApbSize = 'h00000F00; /************************ * RegBus Configuration * ***********************/ diff --git a/hw/configs/carfield_l2dual_safe_pulp_spatz_periph.sv b/hw/configs/carfield_l2dual_safe_pulp_spatz_periph.sv index ba8e2f44..74da29a9 100644 --- a/hw/configs/carfield_l2dual_safe_pulp_spatz_periph.sv +++ b/hw/configs/carfield_l2dual_safe_pulp_spatz_periph.sv @@ -62,6 +62,18 @@ localparam doub_bt SystemWatchdogSize = 'h00001000; // Hyperbus Config localparam doub_bt HyperBusBase = 'h20009000; localparam doub_bt HyperBusSize = 'h00001000; +// Streamer +localparam bit StreamerEnable = 0; +localparam doub_bt StreamerCfgBase = 'h20009000; +localparam doub_bt StreamerCfgSize = 'h00008000; +localparam doub_bt StreamerApbBase = StreamerCfgBase + StreamerCfgSize; +localparam doub_bt StreamerApbSize = 'h00008000; +// SpaceWire +localparam bit SpaceWireEnable = 0; +localparam doub_bt SpaceWireRegBase = 'h20019000; +localparam doub_bt SpaceWireRegSize = 'h00000100; +localparam doub_bt SpaceWireApbBase = SpaceWireRegBase + SpaceWireRegSize; +localparam doub_bt SpaceWireApbSize = 'h00000F00; /************************ * RegBus Configuration * ***********************/ diff --git a/hw/configs/carfield_l2dual_safe_secure_pulp_spatz_periph_can.sv b/hw/configs/carfield_l2dual_safe_secure_pulp_spatz_periph_can.sv index 99e0628c..59b6e194 100644 --- a/hw/configs/carfield_l2dual_safe_secure_pulp_spatz_periph_can.sv +++ b/hw/configs/carfield_l2dual_safe_secure_pulp_spatz_periph_can.sv @@ -11,15 +11,15 @@ import cheshire_pkg::*; * AXI Configuration * ********************/ //L2, port 0 -localparam bit L2Port0Enable = 1; +localparam bit L2Port0Enable = 0; localparam doub_bt L2Port0Base = 'h78000000; localparam doub_bt L2Port0Size = 'h00200000; // L2, port 1 -localparam bit L2Port1Enable = 1; +localparam bit L2Port1Enable = 0; localparam doub_bt L2Port1Base = L2Port0Base + L2Port0Size; localparam doub_bt L2Port1Size = L2Port0Size; // Safety Island -localparam bit SafetyIslandEnable = 1; +localparam bit SafetyIslandEnable = 0; localparam doub_bt SafetyIslandBase = 'h60000000; localparam doub_bt SafetyIslandSize = 'h00800000; // Ethernet @@ -31,15 +31,15 @@ localparam bit PeriphEnable = 1; localparam doub_bt PeriphBase = 'h20001000; localparam doub_bt PeriphSize = 'h00009000; // Spatz cluster -localparam bit SpatzClusterEnable = 1; +localparam bit SpatzClusterEnable = 0; localparam doub_bt SpatzClusterBase = 'h51000000; localparam doub_bt SpatzClusterSize = 'h00800000; // PULP cluster -localparam bit PulpClusterEnable = 1; +localparam bit PulpClusterEnable = 0; localparam doub_bt PulpClusterBase = 'h50000000; localparam doub_bt PulpClusterSize = 'h00800000; // Security Island -localparam bit SecurityIslandEnable = 1; +localparam bit SecurityIslandEnable = 0; localparam doub_bt SecurityIslandBase = 'h0; localparam doub_bt SecurityIslandSize = 'h0; // Mailbox @@ -65,6 +65,18 @@ localparam doub_bt SystemWatchdogSize = 'h00001000; // Hyperbus Config localparam doub_bt HyperBusBase = 'h20009000; localparam doub_bt HyperBusSize = 'h00001000; +// Streamer +localparam bit StreamerEnable = 0; +localparam doub_bt StreamerCfgBase = 'h20009000; +localparam doub_bt StreamerCfgSize = 'h00008000; +localparam doub_bt StreamerApbBase = StreamerCfgBase + StreamerCfgSize; +localparam doub_bt StreamerApbSize = 'h00008000; +// SpaceWire +localparam bit SpaceWireEnable = 0; +localparam doub_bt SpaceWireRegBase = 'h20019000; +localparam doub_bt SpaceWireRegSize = 'h00000100; +localparam doub_bt SpaceWireApbBase = SpaceWireRegBase + SpaceWireRegSize; +localparam doub_bt SpaceWireApbSize = 'h00000F00; /************************ * RegBus Configuration * ***********************/ @@ -89,4 +101,4 @@ localparam doub_bt L2EccCfgSize = 'h00001000; localparam doub_bt NumHypPhys = 1; localparam doub_bt NumHypChips = 2; -endpackage \ No newline at end of file +endpackage diff --git a/hw/configs/carfield_l2dual_secure_periph.sv b/hw/configs/carfield_l2dual_secure_periph.sv index 44211918..7744ee59 100644 --- a/hw/configs/carfield_l2dual_secure_periph.sv +++ b/hw/configs/carfield_l2dual_secure_periph.sv @@ -62,6 +62,18 @@ localparam doub_bt SystemWatchdogSize = 'h00001000; // Hyperbus Config localparam doub_bt HyperBusBase = 'h20009000; localparam doub_bt HyperBusSize = 'h00001000; +// Streamer +localparam bit StreamerEnable = 0; +localparam doub_bt StreamerCfgBase = 'h20009000; +localparam doub_bt StreamerCfgSize = 'h00008000; +localparam doub_bt StreamerApbBase = StreamerCfgBase + StreamerCfgSize; +localparam doub_bt StreamerApbSize = 'h00008000; +// SpaceWire +localparam bit SpaceWireEnable = 0; +localparam doub_bt SpaceWireRegBase = 'h20019000; +localparam doub_bt SpaceWireRegSize = 'h00000100; +localparam doub_bt SpaceWireApbBase = SpaceWireRegBase + SpaceWireRegSize; +localparam doub_bt SpaceWireApbSize = 'h00000F00; /************************ * RegBus Configuration * ***********************/ diff --git a/hw/configs/carfield_l2dual_secure_pulp_periph_can.sv b/hw/configs/carfield_l2dual_secure_pulp_periph_can.sv index 13212e51..5c90b5b6 100644 --- a/hw/configs/carfield_l2dual_secure_pulp_periph_can.sv +++ b/hw/configs/carfield_l2dual_secure_pulp_periph_can.sv @@ -65,6 +65,18 @@ localparam doub_bt SystemWatchdogSize = 'h00001000; // Hyperbus Config localparam doub_bt HyperBusBase = 'h20008000; localparam doub_bt HyperBusSize = 'h00001000; +// Streamer +localparam bit StreamerEnable = 0; +localparam doub_bt StreamerCfgBase = 'h20009000; +localparam doub_bt StreamerCfgSize = 'h00008000; +localparam doub_bt StreamerApbBase = StreamerCfgBase + StreamerCfgSize; +localparam doub_bt StreamerApbSize = 'h00008000; +// SpaceWire +localparam bit SpaceWireEnable = 0; +localparam doub_bt SpaceWireRegBase = 'h20019000; +localparam doub_bt SpaceWireRegSize = 'h00000100; +localparam doub_bt SpaceWireApbBase = SpaceWireRegBase + SpaceWireRegSize; +localparam doub_bt SpaceWireApbSize = 'h00000F00; /************************ * RegBus Configuration * ***********************/ diff --git a/hw/configs/carfield_l2dual_secure_pulp_periph_can_ethernet_streamer_spw.sv b/hw/configs/carfield_l2dual_secure_pulp_periph_can_ethernet_streamer_spw.sv new file mode 100644 index 00000000..1754e609 --- /dev/null +++ b/hw/configs/carfield_l2dual_secure_pulp_periph_can_ethernet_streamer_spw.sv @@ -0,0 +1,104 @@ +// Copyright 2022 ETH Zurich and University of Bologna. +// Solderpad Hardware License, Version 0.51, see LICENSE for details. +// SPDX-License-Identifier: SHL-0.51 +// +// Yvan Tortorella + +package carfield_configuration; + +import cheshire_pkg::*; +/********************* + * AXI Configuration * + ********************/ +//L2, port 0 +localparam bit L2Port0Enable = 1; +localparam doub_bt L2Port0Base = 'h78000000; +localparam doub_bt L2Port0Size = 'h00020000; +// L2, port 1 +localparam bit L2Port1Enable = 1; +localparam doub_bt L2Port1Base = L2Port0Base + L2Port0Size; +localparam doub_bt L2Port1Size = L2Port0Size; +// Safety Island +localparam bit SafetyIslandEnable = 0; +localparam doub_bt SafetyIslandBase = 'h60000000; +localparam doub_bt SafetyIslandSize = 'h00800000; +// Ethernet +localparam bit EthernetEnable = 1; +localparam doub_bt EthernetBase = 'h20000000; +localparam doub_bt EthernetSize = 'h00001000; +// Peripherals +localparam bit PeriphEnable = 1; +localparam doub_bt PeriphBase = 'h20001000; +localparam doub_bt PeriphSize = 'h00FFF000; +// Spatz cluster +localparam bit SpatzClusterEnable = 0; +localparam doub_bt SpatzClusterBase = 'h51000000; +localparam doub_bt SpatzClusterSize = 'h00800000; +// PULP cluster +localparam bit PulpClusterEnable = 1; +localparam doub_bt PulpClusterBase = 'h50000000; +localparam doub_bt PulpClusterSize = 'h00800000; +// Security Island +localparam bit SecurityIslandEnable = 1; +localparam doub_bt SecurityIslandBase = 'h0; +localparam doub_bt SecurityIslandSize = 'h0; +// Mailbox +localparam bit MailboxEnable = 1; +localparam doub_bt MailboxBase = 'h40000000; +localparam doub_bt MailboxSize = 'h00003000; +/********************* + * APB Configuration * + ********************/ +// Can +localparam bit CanEnable = 1; +localparam doub_bt CanBase = 'h20001000; +localparam doub_bt CanSize = 'h00001000; +// System Timer +localparam doub_bt SystemTimerBase = 'h20004000; +localparam doub_bt SystemTimerSize = 'h00001000; +// System Advanced Timer +localparam doub_bt SystemAdvancedTimerBase = 'h20005000; +localparam doub_bt SystemAdvancedTimerSize = 'h00001000; +// System Watchdog +localparam doub_bt SystemWatchdogBase = 'h20007000; +localparam doub_bt SystemWatchdogSize = 'h00001000; +// Hyperbus Config +localparam doub_bt HyperBusBase = 'h20008000; +localparam doub_bt HyperBusSize = 'h00001000; +// Streamer +localparam bit StreamerEnable = 1; +localparam doub_bt StreamerCfgBase = 'h20009000; +localparam doub_bt StreamerCfgSize = 'h00008000; +localparam doub_bt StreamerApbBase = StreamerCfgBase + StreamerCfgSize; +localparam doub_bt StreamerApbSize = 'h00008000; +// SpaceWire +localparam bit SpaceWireEnable = 1; +localparam doub_bt SpaceWireRegBase = 'h20019000; +localparam doub_bt SpaceWireRegSize = 'h00000100; +localparam doub_bt SpaceWireApbBase = SpaceWireRegBase + SpaceWireRegSize; +localparam doub_bt SpaceWireApbSize = 'h00000F00; +/************************ + * RegBus Configuration * + ***********************/ +// Padframe +localparam bit PadframeCfgEnable = 1; +localparam doub_bt PadframeCfgBase = 'h21000000; +localparam doub_bt PadframeCfgSize = 'h00001000; +// L2 ECC +localparam bit L2EccCfgEnable = 1; +localparam doub_bt L2EccCfgBase = 'h21001000; +localparam doub_bt L2EccCfgSize = 'h00001000; +// Platform control registers +localparam doub_bt PcrsBase = 'h21002000; +localparam doub_bt PcrsSize = 'h00001000; +// PLL +localparam bit PllCfgEnable = 1; +localparam doub_bt PllCfgBase = 'h21003000; +localparam doub_bt PllCfgSize = 'h00001000; +/************************** + * HyperBus Configuration * + **************************/ +localparam doub_bt NumHypPhys = 1; +localparam doub_bt NumHypChips = 2; + +endpackage diff --git a/hw/configs/carfield_l2dual_spatz_periph.sv b/hw/configs/carfield_l2dual_spatz_periph.sv index a5d7135a..a371a4f6 100644 --- a/hw/configs/carfield_l2dual_spatz_periph.sv +++ b/hw/configs/carfield_l2dual_spatz_periph.sv @@ -62,6 +62,18 @@ localparam doub_bt SystemWatchdogSize = 'h00001000; // Hyperbus Config localparam doub_bt HyperBusBase = 'h20009000; localparam doub_bt HyperBusSize = 'h00001000; +// Streamer +localparam bit StreamerEnable = 0; +localparam doub_bt StreamerCfgBase = 'h20009000; +localparam doub_bt StreamerCfgSize = 'h00008000; +localparam doub_bt StreamerApbBase = StreamerCfgBase + StreamerCfgSize; +localparam doub_bt StreamerApbSize = 'h00008000; +// SpaceWire +localparam bit SpaceWireEnable = 0; +localparam doub_bt SpaceWireRegBase = 'h20019000; +localparam doub_bt SpaceWireRegSize = 'h00000100; +localparam doub_bt SpaceWireApbBase = SpaceWireRegBase + SpaceWireRegSize; +localparam doub_bt SpaceWireApbSize = 'h00000F00; /************************ * RegBus Configuration * ***********************/ diff --git a/hw/padframe/astral_padframe.yml b/hw/padframe/astral_padframe.yml new file mode 100644 index 00000000..5d691e81 --- /dev/null +++ b/hw/padframe/astral_padframe.yml @@ -0,0 +1,1301 @@ +# Astral Padframe +# authors: Victor Isachi + +name: astral_padframe +manifest_version: 3 +pad_domains: + - name: periph + pad_types: + - name: PDVDDTIE_18_18_NT_DR_V + description: "gf12 pad, horizontal orientation, I/O power control tie" + template: | + wire io_pads_rto; + wire io_pads_sns; + + PDVDDTIE_18_18_NT_DR_V ${instance_name} ( + .SNS( io_pads_sns ), + .RTO( io_pads_rto ) + ); + - name: PVDD_08_08_NT_DR_H + description: "gf12 pad, horizontal orientation, core power domain VDD" + template: | + PVDD_08_08_NT_DR_H ${instance_name} ( .SNS( io_pads_sns ), .RTO( io_pads_rto ) ); + - name: PVDD_08_08_NT_DR_V + description: "gf12 pad, vertical orientation, core power domain VDD" + template: | + PVDD_08_08_NT_DR_V ${instance_name} ( .SNS( io_pads_sns ), .RTO( io_pads_rto ) ); + - name: PVSS_08_08_NT_DR_H + description: "gf12 pad, horizontal orientation, core power domain VSS" + template: | + PVSS_08_08_NT_DR_H ${instance_name} ( .SNS( io_pads_sns ), .RTO( io_pads_rto ) ); + - name: PVSS_08_08_NT_DR_V + description: "gf12 pad, vertical orientation, core power domain VSS" + template: | + PVSS_08_08_NT_DR_V ${instance_name} ( .SNS( io_pads_sns ), .RTO( io_pads_rto ) ); + - name: PDVDD_18_18_NT_DR_H + description: "gf12 pad, horizontal orientation, pad power domain VDD" + template: | + PDVDD_18_18_NT_DR_H ${instance_name} ( .SNS( io_pads_sns ), .RTO( io_pads_rto ) ); + - name: PDVDD_18_18_NT_DR_V + description: "gf12 pad, vertical orientation, pad power domain VDD" + template: | + PDVDD_18_18_NT_DR_V ${instance_name} ( .SNS( io_pads_sns ), .RTO( io_pads_rto ) ); + - name: PDVSS_18_18_NT_DR_H + description: "gf12 pad, horizontal orientation, pad power domain VSS" + template: | + PDVSS_18_18_NT_DR_H ${instance_name} ( .SNS( io_pads_sns ), .RTO( io_pads_rto ) ); + - name: PDVSS_18_18_NT_DR_V + description: "gf12 pad, vertical orientation, pad power domain VSS" + template: | + PDVSS_18_18_NT_DR_V ${instance_name} ( .SNS( io_pads_sns ), .RTO( io_pads_rto ) ); + - name: PCORNER_18_18_NT_DR + description: "gf12 pad, corner" + template: | + PCORNER_18_18_NT_DR ${instance_name} ( .SNS( io_pads_sns ), .RTO( io_pads_rto ) ); + - name: POSCP_18_18_NT_DR_H + description: "gf12 pad, horizontal orientation, oscillator 1-4MHz" + template: | + (* dont_touch *) + POSCP_18_18_NT_DR_H ${instance_name} ( + .CK ( ${conn["pad2core_clk"]} ), + .CK_IOV ( ${conn["pad2io_clk"]} ), + .PO ( ), + .PADO ( ${conn["pad_o"]} ), + .E0 ( ${conn["crystal_en"]} ), + .PADI ( ${conn["pad_i"]} ), + .POE ( 1'b0 ), + .RTO ( io_pads_rto ), + .SF0 ( 1'b0 ), + .SF1 ( 1'b0 ), + .SNS ( io_pads_sns ), + .SP ( 1'b0 ), + .TE ( ${conn["test_en"]} ) + ); + pad_signals: &gf12_pad_oscillator_signals + - name: pad_i + description: "Oscillator input (differential pair)" + size: 1 + kind: pad + - name: pad_o + description: "Oscillator output (differential pair)" + size: 1 + kind: pad + - name: pad2core_clk + description: "Core power doman output pin from oscillator" + size: 1 + kind: output + conn_type: dynamic + - name: pad2io_clk + description: "I/O power doman output pin from oscillator" + size: 1 + kind: output + conn_type: dynamic + - name: crystal_en + description: "Oscillator enable signal, active high" + size: 1 + kind: input + conn_type: dynamic + default_reset_value: 1 + default_static_value: 1'b1 + - name: test_en + description: "Test enable signal, active high" + size: 1 + kind: input + conn_type: dynamic + default_reset_value: 0 + default_static_value: 1'b0 + + - name: PBIDIR_18_18_NT_DR_H + description: "gf12 pad, horizontal orientation, digital input/output" + template: | + (* dont_touch *) + PBIDIR_18_18_NT_DR_H ${instance_name} ( + .PO ( ), + .Y ( ${conn["pad2chip"]} ), + .PAD ( ${conn["pad"]} ), + .A ( ${conn["chip2pad"]} ), + .DS0 ( 1'b0 ), + .DS1 ( 1'b0 ), + .IE ( ${conn["input_en"]} ), + .IS ( 1'b0 ), + .OE ( ${conn["output_en"]} ), + .PE ( ${conn["pull_en"]} ), + .POE ( 1'b0 ), + .PS ( ${conn["pull_sel"]} ), + .RTO ( io_pads_rto ), + .SNS ( io_pads_sns ), + .SR ( 1'b0 ) + ); + pad_signals: &gf12_pad_bidir_signals + - name: pad + description: "Data external input/output" + size: 1 + kind: pad + - name: chip2pad + description: "Data input pin from chip to padframe" + size: 1 + kind: input + conn_type: dynamic + default_reset_value: 0 + default_static_value: 1'b0 + - name: pad2chip + description: "Data output pin from padframe to chip" + size: 1 + kind: output + conn_type: dynamic + - name: input_en + description: "Input enable signal, active high" + size: 1 + kind: input + conn_type: dynamic + default_reset_value: 0 + default_static_value: 1'b0 + - name: output_en + description: "Output enable signal, active high" + size: 1 + kind: input + conn_type: dynamic + default_reset_value: 0 + default_static_value: 1'b0 + - name: pull_en + description: "Pull-up/-down enable signal, active high" + size: 1 + kind: input + conn_type: dynamic + default_reset_value: 0 + default_static_value: 1'b0 + - name: pull_sel + description: "Pull-up/-down select signal, high: pull-up, low: pull-down" + size: 1 + kind: input + conn_type: dynamic + default_reset_value: 0 + default_static_value: 1'b0 + + - name: PBIDIR_18_18_NT_DR_V + description: "gf12 pad, vertical orientation, digital input/output" + template: | + (* dont_touch *) + PBIDIR_18_18_NT_DR_V ${instance_name} ( + .PO ( ), + .Y ( ${conn["pad2chip"]} ), + .PAD ( ${conn["pad"]} ), + .A ( ${conn["chip2pad"]} ), + .DS0 ( 1'b0 ), + .DS1 ( 1'b0 ), + .IE ( ${conn["input_en"]} ), + .IS ( 1'b0 ), + .OE ( ${conn["output_en"]} ), + .PE ( ${conn["pull_en"]} ), + .POE ( 1'b0 ), + .PS ( ${conn["pull_sel"]} ), + .RTO ( io_pads_rto ), + .SNS ( io_pads_sns ), + .SR ( 1'b0 ) + ); + pad_signals: *gf12_pad_bidir_signals + +# END PAD DEFINITIONS +################################################################### +################################################################### + +# PAD INSTANCES + pad_list: + +######################################## +# POWER MANAGEMENT +######################################## + + - name: pad_tie_io + description: "I/O power control tie pad" + pad_type: PDVDDTIE_18_18_NT_DR_V + is_static: true + +######################################## +# I/O POWER +######################################## + + - name: pad_dvdd_io_h_{i} + multiple: 2 + description: "I/O power domain horizontal VDD pad" + pad_type: PDVDD_18_18_NT_DR_H + is_static: true + + - name: pad_dvdd_io_v_{i} + multiple: 6 + description: "I/O power domain vertical VDD pad" + pad_type: PDVDD_18_18_NT_DR_V + is_static: true + + - name: pad_dvss_io_h_{i} + multiple: 2 + description: "I/O power domain horizontal VSS pad" + pad_type: PDVSS_18_18_NT_DR_H + is_static: true + + - name: pad_dvss_io_v_{i} + multiple: 6 + description: "I/O power domain vertical VSS pad" + pad_type: PDVSS_18_18_NT_DR_V + is_static: true + +######################################## +# CORE POWER +######################################## + + - name: pad_vdd_core_h_{i} + multiple: 4 + description: "Core power domain horizontal VDD pad" + pad_type: PVDD_08_08_NT_DR_H + is_static: true + + - name: pad_vdd_core_v_{i} + multiple: 6 + description: "Core power domain vertical VDD pad" + pad_type: PVDD_08_08_NT_DR_V + is_static: true + + - name: pad_vss_core_h_{i} + multiple: 4 + description: "Core power domain horizontal VSS pad" + pad_type: PVSS_08_08_NT_DR_H + is_static: true + + - name: pad_vss_core_v_{i} + multiple: 6 + description: "Core power domain vertical VSS pad" + pad_type: PVSS_08_08_NT_DR_V + is_static: true + +######################################## +# CORNER PADS +######################################## + + - name: pad_corner_{i} + multiple: 4 + description: "Corner pad" + pad_type: PCORNER_18_18_NT_DR + is_static: true + +######################################## +# CLOCKS +######################################## + + - name: ref_clk + description: "Reference clock in" + pad_type: PBIDIR_18_18_NT_DR_H + is_static: true + connections: + chip2pad: 1'b0 + pad2chip: ref_clk_i + input_en: 1'b1 + output_en: 1'b0 + pull_en: 1'b0 + pull_sel: 1'b0 + + - name: fll_host + description: "host clock generated by the FLL" + pad_type: PBIDIR_18_18_NT_DR_H + is_static: true + connections: + chip2pad: fll_host_clk_o + #pad2chip + input_en: 1'b0 + output_en: 1'b1 + pull_en: 1'b0 + pull_sel: 1'b0 + + - name: fll_periph + description: "periph clock generated by the FLL" + pad_type: PBIDIR_18_18_NT_DR_H + is_static: true + connections: + chip2pad: fll_periph_clk_o + #pad2chip + input_en: 1'b0 + output_en: 1'b1 + pull_en: 1'b0 + pull_sel: 1'b0 + + - name: fll_alt + description: "alt clock generated by the FLL" + pad_type: PBIDIR_18_18_NT_DR_H + is_static: true + connections: + chip2pad: fll_alt_clk_o + #pad2chip + input_en: 1'b0 + output_en: 1'b1 + pull_en: 1'b0 + pull_sel: 1'b0 + + - name: fll_rt + description: "rt clock generated by the FLL" + pad_type: PBIDIR_18_18_NT_DR_H + is_static: true + connections: + chip2pad: fll_rt_clk_o + #pad2chip + input_en: 1'b0 + output_en: 1'b1 + pull_en: 1'b0 + pull_sel: 1'b0 + + - name: fll_bypass + description: "FLL bypass in, when active bypasses FLL clock with ref_clk" + pad_type: PBIDIR_18_18_NT_DR_H + is_static: true + connections: + chip2pad: 1'b0 + pad2chip: fll_bypass_i + input_en: 1'b1 + output_en: 1'b0 + pull_en: 1'b0 + pull_sel: 1'b0 + +######################################## +# POWER ON AND RESET +######################################## + + - name: pwr_on_rst_n + description: "Power on and reset in, active-low" + pad_type: PBIDIR_18_18_NT_DR_H + is_static: true + connections: + chip2pad: 1'b0 + pad2chip: pwr_on_rst_ni + input_en: 1'b1 + output_en: 1'b0 + pull_en: 1'b0 + pull_sel: 1'b0 + +######################################## +# SECURE BOOT +######################################## + + - name: secure_boot + description: "Secure boot in" + pad_type: PBIDIR_18_18_NT_DR_H + is_static: true + connections: + chip2pad: 1'b0 + pad2chip: secure_boot_i + input_en: 1'b1 + output_en: 1'b0 + pull_en: 1'b0 + pull_sel: 1'b0 + +######################################## +# JTAG +######################################## + + - name: jtag_tclk + description: "JTAG tclk in" + pad_type: PBIDIR_18_18_NT_DR_H + is_static: true + connections: + chip2pad: 1'b0 + pad2chip: jtag_tclk_i + input_en: 1'b1 + output_en: 1'b0 + pull_en: 1'b0 + pull_sel: 1'b0 + + - name: jtag_trst_n + description: "JTAG trst in, active-low" + pad_type: PBIDIR_18_18_NT_DR_H + is_static: true + connections: + chip2pad: 1'b0 + pad2chip: jtag_trst_ni + input_en: 1'b1 + output_en: 1'b0 + pull_en: 1'b0 + pull_sel: 1'b0 + + - name: jtag_tms + description: "JTAG tms in" + pad_type: PBIDIR_18_18_NT_DR_H + is_static: true + connections: + chip2pad: 1'b0 + pad2chip: jtag_tms_i + input_en: 1'b1 + output_en: 1'b0 + pull_en: 1'b0 + pull_sel: 1'b0 + + - name: jtag_tdi + description: "JTAG tdi in" + pad_type: PBIDIR_18_18_NT_DR_H + is_static: true + connections: + chip2pad: 1'b0 + pad2chip: jtag_tdi_i + input_en: 1'b1 + output_en: 1'b0 + pull_en: 1'b0 + pull_sel: 1'b0 + + - name: jtag_tdo + description: "JTAG tdo out" + pad_type: PBIDIR_18_18_NT_DR_H + is_static: true + connections: + chip2pad: jtag_tdo_o + #pad2chip + input_en: 1'b0 + output_en: 1'b1 + pull_en: 1'b0 + pull_sel: 1'b0 + +######################################## +# TEST MODE +######################################## + + - name: test_mode + description: "Test mode in" + pad_type: PBIDIR_18_18_NT_DR_H + is_static: true + connections: + chip2pad: 1'b0 + pad2chip: test_mode_i + input_en: 1'b1 + output_en: 1'b0 + pull_en: 1'b0 + pull_sel: 1'b0 + +######################################## +# CHESHIRE BOOT MODE +######################################## + + - name: boot_mode_{i} + multiple: 2 + description: "Boot mode in" + pad_type: PBIDIR_18_18_NT_DR_H + is_static: true + connections: + chip2pad: 1'b0 + pad2chip: boot_mode_{i}_i + input_en: 1'b1 + output_en: 1'b0 + pull_en: 1'b0 + pull_sel: 1'b0 + +######################################## +# OPENTITAN BOOT MODE +######################################## + + - name: ot_boot_mode + description: "Opentitan boot mode in" + pad_type: PBIDIR_18_18_NT_DR_H + is_static: true + connections: + chip2pad: 1'b0 + pad2chip: ot_boot_mode_i + input_en: 1'b1 + output_en: 1'b0 + pull_en: 1'b0 + pull_sel: 1'b0 + +######################################## +# JTAG OT +######################################## + + - name: jtag_ot_tclk + description: "JTAG OT tclk in" + pad_type: PBIDIR_18_18_NT_DR_H + is_static: true + connections: + chip2pad: 1'b0 + pad2chip: jtag_ot_tclk_i + input_en: 1'b1 + output_en: 1'b0 + pull_en: 1'b0 + pull_sel: 1'b0 + + - name: jtag_ot_trst_ni + description: "JTAG OT trst in, active-low" + pad_type: PBIDIR_18_18_NT_DR_H + is_static: true + connections: + chip2pad: 1'b0 + pad2chip: jtag_ot_trst_ni + input_en: 1'b1 + output_en: 1'b0 + pull_en: 1'b0 + pull_sel: 1'b0 + + - name: jtag_ot_tms + description: "JTAG OT tms in" + pad_type: PBIDIR_18_18_NT_DR_H + is_static: true + connections: + chip2pad: 1'b0 + pad2chip: jtag_ot_tms_i + input_en: 1'b1 + output_en: 1'b0 + pull_en: 1'b0 + pull_sel: 1'b0 + + - name: jtag_ot_tdi + description: "JTAG OT tdi in" + pad_type: PBIDIR_18_18_NT_DR_H + is_static: true + connections: + chip2pad: 1'b0 + pad2chip: jtag_ot_tdi_i + input_en: 1'b1 + output_en: 1'b0 + pull_en: 1'b0 + pull_sel: 1'b0 + + - name: jtag_ot_tdo + description: "JTAG OT tdo out" + pad_type: PBIDIR_18_18_NT_DR_H + is_static: true + connections: + chip2pad: jtag_ot_tdo_o + #pad2chip + input_en: 1'b0 + output_en: 1'b1 + pull_en: 1'b0 + pull_sel: 1'b0 + +######################################## +# HYPERBUS +######################################## + + - name: hyper_cs_{i}_n + multiple: 2 + description: "Hyperbus cs out, active-low" + pad_type: PBIDIR_18_18_NT_DR_V + is_static: true + connections: + chip2pad: hyper_cs_{i}_no + #pad2chip + input_en: 1'b0 + output_en: 1'b1 + pull_en: 1'b0 + pull_sel: 1'b0 + + - name: hyper_ck + description: "Hyperbus ck out" + pad_type: PBIDIR_18_18_NT_DR_V + is_static: true + connections: + chip2pad: hyper_ck_o + #pad2chip + input_en: 1'b0 + output_en: 1'b1 + pull_en: 1'b0 + pull_sel: 1'b0 + + - name: hyper_ck_n + description: "Hyperbus ck out, active-low" + pad_type: PBIDIR_18_18_NT_DR_V + is_static: true + connections: + chip2pad: hyper_ck_no + #pad2chip + input_en: 1'b0 + output_en: 1'b1 + pull_en: 1'b0 + pull_sel: 1'b0 + + - name: hyper_rwds + description: "Hyperbus rwds in/out" + pad_type: PBIDIR_18_18_NT_DR_V + is_static: true + connections: + chip2pad: hyper_rwds_o + pad2chip: hyper_rwds_i + input_en: ~hyper_rwds_oen_i + output_en: hyper_rwds_oen_i + pull_en: 1'b0 + pull_sel: 1'b0 + + - name: hyper_dq_{i} + multiple: 8 + description: "Hyperbus dq in/out" + pad_type: PBIDIR_18_18_NT_DR_V + is_static: true + connections: + chip2pad: hyper_dq_{i}_o + pad2chip: hyper_dq_{i}_i + input_en: ~hyper_dq_oen_i + output_en: hyper_dq_oen_i + pull_en: 1'b0 + pull_sel: 1'b0 + + - name: hyper_reset_n + description: "Hyperbus reset out, active-low" + pad_type: PBIDIR_18_18_NT_DR_V + is_static: true + connections: + chip2pad: hyper_reset_no + #pad2chip + input_en: 1'b0 + output_en: 1'b1 + pull_en: 1'b0 + pull_sel: 1'b0 + +######################################## +# SPW +######################################## + + - name: spw_data_in + description: "SPW data in" + pad_type: PBIDIR_18_18_NT_DR_H + is_static: true + connections: + chip2pad: 1'b0 + pad2chip: spw_data_i + input_en: 1'b1 + output_en: 1'b0 + pull_en: 1'b0 + pull_sel: 1'b0 + + - name: spw_strb_in + description: "SPW strb in" + pad_type: PBIDIR_18_18_NT_DR_H + is_static: true + connections: + chip2pad: 1'b0 + pad2chip: spw_strb_i + input_en: 1'b1 + output_en: 1'b0 + pull_en: 1'b0 + pull_sel: 1'b0 + + - name: spw_data_out + description: "SPW data out" + pad_type: PBIDIR_18_18_NT_DR_H + is_static: true + connections: + chip2pad: spw_data_o + #pad2chip + input_en: 1'b0 + output_en: 1'b1 + pull_en: 1'b0 + pull_sel: 1'b0 + + - name: spw_strb_out + description: "SPW strb out" + pad_type: PBIDIR_18_18_NT_DR_H + is_static: true + connections: + chip2pad: spw_strb_o + #pad2chip + input_en: 1'b0 + output_en: 1'b1 + pull_en: 1'b0 + pull_sel: 1'b0 + +######################################## +# UART +######################################## + + - name: uart_tx_out + description: "UART tx out" + pad_type: PBIDIR_18_18_NT_DR_H + is_static: true + connections: + chip2pad: uart_tx_o + #pad2chip + input_en: 1'b0 + output_en: 1'b1 + pull_en: 1'b0 + pull_sel: 1'b0 + + - name: uart_rx_in + description: "UART rx in" + pad_type: PBIDIR_18_18_NT_DR_H + is_static: true + connections: + chip2pad: 1'b0 + pad2chip: uart_rx_i + input_en: 1'b1 + output_en: 1'b0 + pull_en: 1'b0 + pull_sel: 1'b0 + +######################################## +# MUXED PADS +######################################## + + - name: muxed_v_{i:2d} + multiple: 18 + mux_groups: [self] + description: "Vertical digital input/output pads that are muxed" + pad_type: PBIDIR_18_18_NT_DR_V + is_static: false + default_port: + muxed_v_00: can.rx + muxed_v_01: can.tx + muxed_v_02: gpio.io_v_2 + muxed_v_03: gpio.io_v_3 + muxed_v_04: serial_link.rcv_clk_i + muxed_v_05: serial_link.i_0 + muxed_v_06: serial_link.i_1 + muxed_v_07: serial_link.i_2 + muxed_v_08: serial_link.i_3 + muxed_v_09: serial_link.i_4 + muxed_v_10: serial_link.i_5 + muxed_v_11: serial_link.i_6 + muxed_v_12: serial_link.i_7 + muxed_v_13: serial_link.rcv_clk_o + # Serial Link data out from 0 to 3 + muxed_v_14: serial_link.o_v_0 + muxed_v_15: serial_link.o_v_1 + muxed_v_16: serial_link.o_v_2 + muxed_v_17: serial_link.o_v_3 + # muxed_v_18: serial_link.o_4 + # muxed_v_19: serial_link.o_5 + # muxed_v_20: serial_link.o_6 + # muxed_v_21: serial_link.o_7 + + - name: muxed_h_{i:2d} + multiple: 4 + mux_groups: [self] + description: "Horizontal digital input/output pads that are muxed" + pad_type: PBIDIR_18_18_NT_DR_H + is_static: false + default_port: + # Serial Link data out from 4 to 7 + muxed_h_00: serial_link.o_h_0 + muxed_h_01: serial_link.o_h_1 + muxed_h_02: serial_link.o_h_2 + muxed_h_03: serial_link.o_h_3 + + # muxed_v_00: spi.sck + # muxed_v_01: spi.csb_0 + # muxed_v_02: spi.csb_1 + # muxed_v_03: spi.sd_0 + # muxed_v_04: spi.sd_1 + # muxed_v_05: spi.sd_2 + # muxed_v_06: spi.sd_3 + # muxed_v_07: ethernet.rxck + # muxed_v_08: ethernet.rxctl + # muxed_v_09: ethernet.rxd_0 + # muxed_v_10: ethernet.rxd_1 + # muxed_v_11: ethernet.rxd_2 + # muxed_v_12: ethernet.rxd_3 + # muxed_v_13: ethernet.txck + # muxed_v_14: ethernet.txctl + # muxed_v_15: ethernet.txd_0 + # muxed_v_16: ethernet.txd_1 + # muxed_v_17: ethernet.txd_2 + # muxed_v_18: ethernet.txd_3 + # muxed_v_19: ethernet.md + # muxed_v_20: ethernet.mdc + # muxed_v_21: ethernet.rst_n + +# END PAD INSTANCES +################################################################### +################################################################### + +# PORT INSTANCES + port_groups: + +######################################## +# MUX 0 +######################################## + + - name: spi + description: "SPI" + output_defaults: 1'b0 + ports: + - name: sck + mux_groups: [muxed_v_00] + description: "SPI sck out" + connections: + chip2pad: spih_sck_o + #pad2chip + input_en: 1'b0 + output_en: 1'b1 + #pull_en: spih_sck_pen_i + #pull_sel: spih_sck_psel_i + - name: csb_{i} + multiple: 2 + mux_groups: ["muxed_v_{i+1:2d}"] + description: "SPI cs out, active-low" + connections: + chip2pad: spih_csb_{i}_o + #pad2chip + input_en: 1'b0 + output_en: 1'b1 + #pull_en: spih_csb_{i}_pen_i + #pull_sel: spih_csb_{i}_psel_i + - name: sd_{i} + multiple: 4 + mux_groups: ["muxed_v_{i+3:2d}"] + description: "SPI sd in/out" + connections: + chip2pad: spih_sd_{i}_o + spih_sd_{i}_i: pad2chip + input_en: ~spih_sd_{i}_oen_i + output_en: spih_sd_{i}_oen_i + #pull_en: spih_sd_{i}_pen_i + #pull_sel: spih_sd_{i}_psel_i + + - name: ethernet + description: "Ethernet" + output_defaults: 1'b0 + ports: + - name: rxck + mux_groups: [muxed_v_07] + description: "Ethernet rxck in" + connections: + #chip2pad + eth_rxck_i: pad2chip + input_en: 1'b1 + output_en: 1'b0 + #pull_en: eth_rxck_pen_i + #pull_sel: eth_rxck_psel_i + - name: rxctl + mux_groups: [muxed_v_08] + description: "Ethernet rxctl in" + connections: + #chip2pad + eth_rxctl_i: pad2chip + input_en: 1'b1 + output_en: 1'b0 + #pull_en: eth_rxctl_pen_i + #pull_sel: eth_rxctl_psel_i + - name: rxd_{i} + multiple: 4 + mux_groups: ["muxed_v_{i+9:2d}"] + description: "Ethernet rxd in" + connections: + #chip2pad + eth_rxd_{i}_i: pad2chip + input_en: 1'b1 + output_en: 1'b0 + #pull_en: eth_rxd_{i}_pen_i + #pull_sel: eth_rxd_{i}_psel_i + - name: txck + mux_groups: [muxed_v_13] + description: "Ethernet txck out" + connections: + chip2pad: eth_txck_o + #pad2chip + input_en: 1'b0 + output_en: 1'b1 + #pull_en: eth_txck_pen_i + #pull_sel: eth_txck_psel_i + - name: txctl + mux_groups: [muxed_v_14] + description: "Ethernet txctl out" + connections: + chip2pad: eth_txctl_o + #pad2chip + input_en: 1'b0 + output_en: 1'b1 + #pull_en: eth_txctl_pen_i + #pull_sel: eth_txctl_psel_i + - name: txd_{i} + multiple: 3 + mux_groups: ["muxed_v_{i+15:2d}"] + description: "Ethernet txd out" + connections: + chip2pad: eth_txd_{i}_o + #pad2chip + input_en: 1'b0 + output_en: 1'b1 + #pull_en: eth_txd_{i}_pen_i + #pull_sel: eth_txd_{i}_psel_i + - name: txd_3 + mux_groups: ["muxed_h_00"] + description: "Ethernet txd out" + connections: + chip2pad: eth_txd_3_o + #pad2chip + input_en: 1'b0 + output_en: 1'b1 + #pull_en: eth_txd_{i}_pen_i + #pull_sel: eth_txd_{i}_psel_i + - name: md + mux_groups: [muxed_h_01] + description: "Ethernet md in/out" + connections: + chip2pad: eth_md_o + eth_md_i: pad2chip + input_en: ~eth_md_oen_i + output_en: eth_md_oen_i + #pull_en: eth_md_pen_i + #pull_sel: eth_md_psel_i + - name: mdc + mux_groups: [muxed_h_02] + description: "Ethernet mdc out" + connections: + chip2pad: eth_mdc_o + #pad2chip + input_en: 1'b0 + output_en: 1'b1 + #pull_en: eth_mdc_pen_i + #pull_sel: eth_mdc_psel_i + - name: rst_n + mux_groups: [muxed_h_03] + description: "Ethernet reset out, active-low" + connections: + chip2pad: eth_rst_no + #pad2chip + input_en: 1'b0 + output_en: 1'b1 + #pull_en: eth_rst_n_pen_i + #pull_sel: eth_rst_n_psel_i + +######################################## +# MUX 1 +######################################## + + - name: can + description: "CAN" + output_defaults: 1'b0 + ports: + - name: rx + mux_groups: [muxed_v_00] + description: "CAN rx in" + connections: + #chip2pad + can_rx_i: pad2chip + input_en: 1'b1 + output_en: 1'b0 + #pull_en: can_rx_pen_i + #pull_sel: can_rx_psel_i + - name: tx + mux_groups: [muxed_v_01] + description: "CAN tx out" + connections: + chip2pad: can_tx_o + #pad2chip + input_en: 1'b0 + output_en: 1'b1 + #pull_en: can_tx_pen_i + #pull_sel: can_tx_psel_i + + - name: serial_link + description: "Serial link" + output_defaults: 1'b1 + ports: + - name: rcv_clk_i + mux_groups: [muxed_v_04] + description: "Serial link rcv_clk in" + connections: + #chip2pad + slink_rcv_clk_i: pad2chip + input_en: 1'b1 + output_en: 1'b0 + #pull_en: slink_rcv_clk_i_pen_i + #pull_sel: slink_rcv_clk_i_psel_i + - name: i_{i} + multiple: 8 + mux_groups: ["muxed_v_{i+5:2d}"] + description: "Serial link in" + connections: + #chip2pad + slink_{i}_i: pad2chip + input_en: 1'b1 + output_en: 1'b0 + #pull_en: slink_i_{i}_pen_i + #pull_sel: slink_i_{i}_psel_i + - name: rcv_clk_o + mux_groups: [muxed_v_13] + description: "Serial link rcv_clk out" + connections: + chip2pad: slink_rcv_clk_o + #pad2chip + input_en: 1'b0 + output_en: 1'b1 + #pull_en: slink_rcv_clk_o_pen_i + #pull_sel: slink_rcv_clk_o_psel_i + - name: o_v_{i} + multiple: 4 + mux_groups: ["muxed_v_{i+14:2d}"] + description: "Serial link out" + connections: + chip2pad: slink_v_{i}_o + #pad2chip + input_en: 1'b0 + output_en: 1'b1 + #pull_en: slink_o_{i}_pen_i + #pull_sel: slink_o_{i}_psel_i + - name: o_h_{i} + multiple: 4 + mux_groups: ["muxed_h_{i:2d}"] + description: "Serial link out" + connections: + chip2pad: slink_h_{i}_o + #pad2chip + input_en: 1'b0 + output_en: 1'b1 + #pull_en: slink_o_{i}_pen_i + #pull_sel: slink_o_{i}_psel_i + +######################################## +# MUX 2 +######################################## + + - name: i2c + description: "I2C" + output_defaults: 1'b0 + ports: + - name: sda + mux_groups: [muxed_v_00] + description: "I2C sda in/out" + connections: + chip2pad: i2c_sda_o + i2c_sda_i: pad2chip + input_en: ~i2c_sda_oen_i + output_en: i2c_sda_oen_i + #pull_en: i2c_sda_pen_i + #pull_sel: i2c_sda_psel_i + - name: scl + mux_groups: [muxed_v_01] + description: "I2C scl in/out" + connections: + chip2pad: i2c_scl_o + i2c_scl_i: pad2chip + input_en: ~i2c_scl_oen_i + output_en: i2c_scl_oen_i + #pull_en: i2c_scl_pen_i + #pull_sel: i2c_scl_psel_i + + - name: tc + description: "TC" + output_defaults: 1'b0 + ports: + - name: active + mux_groups: [muxed_v_07] + description: "TC active in" + connections: + #chip2pad + tc_active_i: pad2chip + input_en: 1'b1 + output_en: 1'b0 + #pull_en: tc_active_pen_i + #pull_sel: tc_active_psel_i + - name: clk + mux_groups: [muxed_v_08] + description: "TC clk in" + connections: + #chip2pad + tc_clk_i: pad2chip + input_en: 1'b1 + output_en: 1'b0 + #pull_en: tc_clk_pen_i + #pull_sel: tc_clk_psel_i + - name: data + mux_groups: [muxed_v_09] + description: "TC data in" + connections: + #chip2pad + tc_data_i: pad2chip + input_en: 1'b1 + output_en: 1'b0 + #pull_en: tc_data_pen_i + #pull_sel: tc_data_psel_i + + - name: ptme + description: "PTME" + output_defaults: 1'b0 + ports: + - name: clk + mux_groups: [muxed_v_10] + description: "PTME clk out" + connections: + chip2pad: ptme_clk_o + #pad2chip + input_en: 1'b0 + output_en: 1'b1 + #pull_en: ptme_clk_pen_i + #pull_sel: ptme_clk_psel_i + - name: enc + mux_groups: [muxed_v_11] + description: "PTME enc out" + connections: + chip2pad: ptme_enc_o + #pad2chip + input_en: 1'b0 + output_en: 1'b1 + #pull_en: ptme_enc_pen_i + #pull_sel: ptme_enc_psel_i + - name: sync + mux_groups: [muxed_v_12] + description: "PTME sync out" + connections: + chip2pad: ptme_sync_o + #pad2chip + input_en: 1'b0 + output_en: 1'b1 + #pull_en: ptme_sync_pen_i + #pull_sel: ptme_sync_psel_i + - name: ext_clk + mux_groups: [muxed_v_13] + description: "TC ext_clk in" + connections: + #chip2pad + ptme_ext_clk_i: pad2chip + input_en: 1'b1 + output_en: 1'b0 + #pull_en: ptme_ext_clk_pen_i + #pull_sel: ptme_ext_clk_psel_i + + - name: hpc + description: "HPC" + output_defaults: 1'b0 + ports: + - name: addr_{i} + multiple: 3 + mux_groups: ["muxed_v_{i+14:2d}"] + description: "HPC addr out" + connections: + chip2pad: hpc_addr_{i}_o + #pad2chip + input_en: 1'b0 + output_en: 1'b1 + #pull_en: hpc_addr_{i}_pen_i + #pull_sel: hpc_addr_{i}_psel_i + - name: cmd_en + mux_groups: [muxed_v_17] + description: "HPC cmd_en out" + connections: + chip2pad: hpc_cmd_en_o + #pad2chip + input_en: 1'b0 + output_en: 1'b1 + #pull_en: hpc_cmd_en_pen_i + #pull_sel: hpc_cmd_en_psel_i + - name: sample + mux_groups: [muxed_h_00] + description: "HPC sample out" + connections: + chip2pad: hpc_sample_o + #pad2chip + input_en: 1'b0 + output_en: 1'b1 + #pull_en: hpc_sample_pen_i + #pull_sel: hpc_sample_psel_i + + - name: llc + description: "LLC" + output_defaults: 1'b0 + ports: + - name: line_{i} + multiple: 2 + mux_groups: ["muxed_h_{i+1:2d}"] + description: "LLC line out" + connections: + chip2pad: llc_line_{i}_o + #pad2chip + input_en: 1'b0 + output_en: 1'b1 + #pull_en: llc_line_{i}_pen_i + #pull_sel: llc_line_{i}_psel_i + + - name: obt + description: "OBT" + output_defaults: 1'b0 + ports: + - name: ext_clk + mux_groups: [muxed_h_03] + description: "OBT ext_clk in" + connections: + #chip2pad + obt_ext_clk_i: pad2chip + input_en: 1'b1 + output_en: 1'b0 + #pull_en: obt_ext_clk_pen_i + #pull_sel: obt_ext_clk_psel_i + +######################################## +# MUX 3 +######################################## + + - name: spi_ot + description: "SPI OT" + output_defaults: 1'b0 + ports: + - name: sck + mux_groups: [muxed_v_00] + description: "SPI OT sck out" + connections: + chip2pad: spih_ot_sck_o + #pad2chip + input_en: 1'b0 + output_en: 1'b1 + #pull_en: spih_ot_sck_pen_i + #pull_sel: spih_ot_sck_psel_i + - name: csb + mux_groups: [muxed_v_01] + description: "SPI OT cs out, active-low" + connections: + chip2pad: spih_ot_csb_o + #pad2chip + input_en: 1'b0 + output_en: 1'b1 + #pull_en: spih_ot_csb_pen_i + #pull_sel: spih_ot_csb_psel_i + - name: sd_{i} + multiple: 4 + mux_groups: ["muxed_v_{i+2:2d}"] + description: "SPI OT sd in/out" + connections: + chip2pad: spih_ot_sd_{i}_o + spih_ot_sd_{i}_i: pad2chip + input_en: ~spih_ot_sd_{i}_oen_i + output_en: spih_ot_sd_{i}_oen_i + #pull_en: spih_ot_sd_{i}_pen_i + #pull_sel: spih_ot_sd_{i}_psel_i + + - name: pll + description: "PLL" + output_defaults: 1'b0 + ports: + - name: io_{i} + multiple: 7 + mux_groups: ["muxed_v_{i+7:2d}"] + description: "PLL in/out" + connections: + chip2pad: pll_{i}_o + pll_{i}_i: pad2chip + input_en: ~pll_{i}_oen_i + output_en: pll_{i}_oen_i + #pull_en: pll_{i}_pen_i + #pull_sel: pll_{i}_psel_i + +######################################## +# MUX 4 +######################################## + + - name: gpio + description: "GPIO" + output_defaults: 1'b0 + ports: + - name: io_v_{i} + multiple: 18 + mux_groups: ["muxed_v_{i:2d}"] + description: "GPIO in/out" + connections: + chip2pad: gpio_v_{i}_o + gpio_v_{i}_i: pad2chip + input_en: ~gpio_v_{i}_oen_i + output_en: gpio_v_{i}_oen_i + #pull_en: gpio_{i}_pen_i + #pull_sel: gpio_{i}_psel_i + - name: io_h_{i} + multiple: 4 + mux_groups: ["muxed_h_{i:2d}"] + description: "GPIO in/out" + connections: + chip2pad: gpio_h_{i}_o + gpio_h_{i}_i: pad2chip + input_en: ~gpio_h_{i}_oen_i + output_en: gpio_h_{i}_oen_i + #pull_en: gpio_{i}_pen_i + #pull_sel: gpio_{i}_psel_i + +# END PORT INSTANCES +################################################################### +################################################################### diff --git a/hw/padframe/astral_padframe/Bender.yml b/hw/padframe/astral_padframe/Bender.yml new file mode 100644 index 00000000..70b474cf --- /dev/null +++ b/hw/padframe/astral_padframe/Bender.yml @@ -0,0 +1,24 @@ + +# File auto-generated by Padrick unknown +package: + name: astral_padframe + authors: + - "Padrick" + +dependencies: + register_interface: { git: "https://github.com/pulp-platform/register_interface.git", version: 0.3.1 } + common_cells: { git: "https://github.com/pulp-platform/common_cells.git", version: 1.21.0 } + +export_include_dirs: +- include + +sources: + - src/pkg_astral_padframe.sv + - src/pkg_internal_astral_padframe_periph.sv + - src/astral_padframe_periph_config_reg_pkg.sv + - src/astral_padframe_periph_config_reg_top.sv + - src/astral_padframe_periph_pads.sv + - src/astral_padframe_periph_muxer.sv + - src/astral_padframe_periph.sv + - src/astral_padframe.sv + diff --git a/hw/padframe/astral_padframe/include/astral_padframe/assign.svh b/hw/padframe/astral_padframe/include/astral_padframe/assign.svh new file mode 100644 index 00000000..a774e5a8 --- /dev/null +++ b/hw/padframe/astral_padframe/include/astral_padframe/assign.svh @@ -0,0 +1,229 @@ + +// File auto-generated by Padrick unknown + +// Assignment Macros +// Assigns all members of port struct to another struct with same names but potentially different order + +`define ASSIGN_PERIPH_SPI_PAD2SOC(load, driver) \ + assign load.spih_sd_0_i = driver.spih_sd_0_i; \ + assign load.spih_sd_1_i = driver.spih_sd_1_i; \ + assign load.spih_sd_2_i = driver.spih_sd_2_i; \ + assign load.spih_sd_3_i = driver.spih_sd_3_i; \ + +`define ASSIGN_PERIPH_SPI_SOC2PAD(load, driver) \ + assign load.spih_csb_0_o = driver.spih_csb_0_o; \ + assign load.spih_csb_1_o = driver.spih_csb_1_o; \ + assign load.spih_sck_o = driver.spih_sck_o; \ + assign load.spih_sd_0_o = driver.spih_sd_0_o; \ + assign load.spih_sd_0_oen_i = driver.spih_sd_0_oen_i; \ + assign load.spih_sd_1_o = driver.spih_sd_1_o; \ + assign load.spih_sd_1_oen_i = driver.spih_sd_1_oen_i; \ + assign load.spih_sd_2_o = driver.spih_sd_2_o; \ + assign load.spih_sd_2_oen_i = driver.spih_sd_2_oen_i; \ + assign load.spih_sd_3_o = driver.spih_sd_3_o; \ + assign load.spih_sd_3_oen_i = driver.spih_sd_3_oen_i; \ + +`define ASSIGN_PERIPH_ETHERNET_PAD2SOC(load, driver) \ + assign load.eth_md_i = driver.eth_md_i; \ + assign load.eth_rxck_i = driver.eth_rxck_i; \ + assign load.eth_rxctl_i = driver.eth_rxctl_i; \ + assign load.eth_rxd_0_i = driver.eth_rxd_0_i; \ + assign load.eth_rxd_1_i = driver.eth_rxd_1_i; \ + assign load.eth_rxd_2_i = driver.eth_rxd_2_i; \ + assign load.eth_rxd_3_i = driver.eth_rxd_3_i; \ + +`define ASSIGN_PERIPH_ETHERNET_SOC2PAD(load, driver) \ + assign load.eth_md_o = driver.eth_md_o; \ + assign load.eth_md_oen_i = driver.eth_md_oen_i; \ + assign load.eth_mdc_o = driver.eth_mdc_o; \ + assign load.eth_rst_no = driver.eth_rst_no; \ + assign load.eth_txck_o = driver.eth_txck_o; \ + assign load.eth_txctl_o = driver.eth_txctl_o; \ + assign load.eth_txd_0_o = driver.eth_txd_0_o; \ + assign load.eth_txd_1_o = driver.eth_txd_1_o; \ + assign load.eth_txd_2_o = driver.eth_txd_2_o; \ + assign load.eth_txd_3_o = driver.eth_txd_3_o; \ + +`define ASSIGN_PERIPH_CAN_PAD2SOC(load, driver) \ + assign load.can_rx_i = driver.can_rx_i; \ + +`define ASSIGN_PERIPH_CAN_SOC2PAD(load, driver) \ + assign load.can_tx_o = driver.can_tx_o; \ + +`define ASSIGN_PERIPH_SERIAL_LINK_PAD2SOC(load, driver) \ + assign load.slink_0_i = driver.slink_0_i; \ + assign load.slink_1_i = driver.slink_1_i; \ + assign load.slink_2_i = driver.slink_2_i; \ + assign load.slink_3_i = driver.slink_3_i; \ + assign load.slink_4_i = driver.slink_4_i; \ + assign load.slink_5_i = driver.slink_5_i; \ + assign load.slink_6_i = driver.slink_6_i; \ + assign load.slink_7_i = driver.slink_7_i; \ + assign load.slink_rcv_clk_i = driver.slink_rcv_clk_i; \ + +`define ASSIGN_PERIPH_SERIAL_LINK_SOC2PAD(load, driver) \ + assign load.slink_h_0_o = driver.slink_h_0_o; \ + assign load.slink_h_1_o = driver.slink_h_1_o; \ + assign load.slink_h_2_o = driver.slink_h_2_o; \ + assign load.slink_h_3_o = driver.slink_h_3_o; \ + assign load.slink_rcv_clk_o = driver.slink_rcv_clk_o; \ + assign load.slink_v_0_o = driver.slink_v_0_o; \ + assign load.slink_v_1_o = driver.slink_v_1_o; \ + assign load.slink_v_2_o = driver.slink_v_2_o; \ + assign load.slink_v_3_o = driver.slink_v_3_o; \ + +`define ASSIGN_PERIPH_I2C_PAD2SOC(load, driver) \ + assign load.i2c_scl_i = driver.i2c_scl_i; \ + assign load.i2c_sda_i = driver.i2c_sda_i; \ + +`define ASSIGN_PERIPH_I2C_SOC2PAD(load, driver) \ + assign load.i2c_scl_o = driver.i2c_scl_o; \ + assign load.i2c_scl_oen_i = driver.i2c_scl_oen_i; \ + assign load.i2c_sda_o = driver.i2c_sda_o; \ + assign load.i2c_sda_oen_i = driver.i2c_sda_oen_i; \ + +`define ASSIGN_PERIPH_TC_PAD2SOC(load, driver) \ + assign load.tc_active_i = driver.tc_active_i; \ + assign load.tc_clk_i = driver.tc_clk_i; \ + assign load.tc_data_i = driver.tc_data_i; \ + + +`define ASSIGN_PERIPH_PTME_PAD2SOC(load, driver) \ + assign load.ptme_ext_clk_i = driver.ptme_ext_clk_i; \ + +`define ASSIGN_PERIPH_PTME_SOC2PAD(load, driver) \ + assign load.ptme_clk_o = driver.ptme_clk_o; \ + assign load.ptme_enc_o = driver.ptme_enc_o; \ + assign load.ptme_sync_o = driver.ptme_sync_o; \ + + +`define ASSIGN_PERIPH_HPC_SOC2PAD(load, driver) \ + assign load.hpc_addr_0_o = driver.hpc_addr_0_o; \ + assign load.hpc_addr_1_o = driver.hpc_addr_1_o; \ + assign load.hpc_addr_2_o = driver.hpc_addr_2_o; \ + assign load.hpc_cmd_en_o = driver.hpc_cmd_en_o; \ + assign load.hpc_sample_o = driver.hpc_sample_o; \ + + +`define ASSIGN_PERIPH_LLC_SOC2PAD(load, driver) \ + assign load.llc_line_0_o = driver.llc_line_0_o; \ + assign load.llc_line_1_o = driver.llc_line_1_o; \ + +`define ASSIGN_PERIPH_OBT_PAD2SOC(load, driver) \ + assign load.obt_ext_clk_i = driver.obt_ext_clk_i; \ + + +`define ASSIGN_PERIPH_SPI_OT_PAD2SOC(load, driver) \ + assign load.spih_ot_sd_0_i = driver.spih_ot_sd_0_i; \ + assign load.spih_ot_sd_1_i = driver.spih_ot_sd_1_i; \ + assign load.spih_ot_sd_2_i = driver.spih_ot_sd_2_i; \ + assign load.spih_ot_sd_3_i = driver.spih_ot_sd_3_i; \ + +`define ASSIGN_PERIPH_SPI_OT_SOC2PAD(load, driver) \ + assign load.spih_ot_csb_o = driver.spih_ot_csb_o; \ + assign load.spih_ot_sck_o = driver.spih_ot_sck_o; \ + assign load.spih_ot_sd_0_o = driver.spih_ot_sd_0_o; \ + assign load.spih_ot_sd_0_oen_i = driver.spih_ot_sd_0_oen_i; \ + assign load.spih_ot_sd_1_o = driver.spih_ot_sd_1_o; \ + assign load.spih_ot_sd_1_oen_i = driver.spih_ot_sd_1_oen_i; \ + assign load.spih_ot_sd_2_o = driver.spih_ot_sd_2_o; \ + assign load.spih_ot_sd_2_oen_i = driver.spih_ot_sd_2_oen_i; \ + assign load.spih_ot_sd_3_o = driver.spih_ot_sd_3_o; \ + assign load.spih_ot_sd_3_oen_i = driver.spih_ot_sd_3_oen_i; \ + +`define ASSIGN_PERIPH_PLL_PAD2SOC(load, driver) \ + assign load.pll_0_i = driver.pll_0_i; \ + assign load.pll_1_i = driver.pll_1_i; \ + assign load.pll_2_i = driver.pll_2_i; \ + assign load.pll_3_i = driver.pll_3_i; \ + assign load.pll_4_i = driver.pll_4_i; \ + assign load.pll_5_i = driver.pll_5_i; \ + assign load.pll_6_i = driver.pll_6_i; \ + +`define ASSIGN_PERIPH_PLL_SOC2PAD(load, driver) \ + assign load.pll_0_o = driver.pll_0_o; \ + assign load.pll_0_oen_i = driver.pll_0_oen_i; \ + assign load.pll_1_o = driver.pll_1_o; \ + assign load.pll_1_oen_i = driver.pll_1_oen_i; \ + assign load.pll_2_o = driver.pll_2_o; \ + assign load.pll_2_oen_i = driver.pll_2_oen_i; \ + assign load.pll_3_o = driver.pll_3_o; \ + assign load.pll_3_oen_i = driver.pll_3_oen_i; \ + assign load.pll_4_o = driver.pll_4_o; \ + assign load.pll_4_oen_i = driver.pll_4_oen_i; \ + assign load.pll_5_o = driver.pll_5_o; \ + assign load.pll_5_oen_i = driver.pll_5_oen_i; \ + assign load.pll_6_o = driver.pll_6_o; \ + assign load.pll_6_oen_i = driver.pll_6_oen_i; \ + +`define ASSIGN_PERIPH_GPIO_PAD2SOC(load, driver) \ + assign load.gpio_h_0_i = driver.gpio_h_0_i; \ + assign load.gpio_h_1_i = driver.gpio_h_1_i; \ + assign load.gpio_h_2_i = driver.gpio_h_2_i; \ + assign load.gpio_h_3_i = driver.gpio_h_3_i; \ + assign load.gpio_v_0_i = driver.gpio_v_0_i; \ + assign load.gpio_v_1_i = driver.gpio_v_1_i; \ + assign load.gpio_v_2_i = driver.gpio_v_2_i; \ + assign load.gpio_v_3_i = driver.gpio_v_3_i; \ + assign load.gpio_v_4_i = driver.gpio_v_4_i; \ + assign load.gpio_v_5_i = driver.gpio_v_5_i; \ + assign load.gpio_v_6_i = driver.gpio_v_6_i; \ + assign load.gpio_v_7_i = driver.gpio_v_7_i; \ + assign load.gpio_v_8_i = driver.gpio_v_8_i; \ + assign load.gpio_v_9_i = driver.gpio_v_9_i; \ + assign load.gpio_v_10_i = driver.gpio_v_10_i; \ + assign load.gpio_v_11_i = driver.gpio_v_11_i; \ + assign load.gpio_v_12_i = driver.gpio_v_12_i; \ + assign load.gpio_v_13_i = driver.gpio_v_13_i; \ + assign load.gpio_v_14_i = driver.gpio_v_14_i; \ + assign load.gpio_v_15_i = driver.gpio_v_15_i; \ + assign load.gpio_v_16_i = driver.gpio_v_16_i; \ + assign load.gpio_v_17_i = driver.gpio_v_17_i; \ + +`define ASSIGN_PERIPH_GPIO_SOC2PAD(load, driver) \ + assign load.gpio_h_0_o = driver.gpio_h_0_o; \ + assign load.gpio_h_0_oen_i = driver.gpio_h_0_oen_i; \ + assign load.gpio_h_1_o = driver.gpio_h_1_o; \ + assign load.gpio_h_1_oen_i = driver.gpio_h_1_oen_i; \ + assign load.gpio_h_2_o = driver.gpio_h_2_o; \ + assign load.gpio_h_2_oen_i = driver.gpio_h_2_oen_i; \ + assign load.gpio_h_3_o = driver.gpio_h_3_o; \ + assign load.gpio_h_3_oen_i = driver.gpio_h_3_oen_i; \ + assign load.gpio_v_0_o = driver.gpio_v_0_o; \ + assign load.gpio_v_0_oen_i = driver.gpio_v_0_oen_i; \ + assign load.gpio_v_1_o = driver.gpio_v_1_o; \ + assign load.gpio_v_1_oen_i = driver.gpio_v_1_oen_i; \ + assign load.gpio_v_2_o = driver.gpio_v_2_o; \ + assign load.gpio_v_2_oen_i = driver.gpio_v_2_oen_i; \ + assign load.gpio_v_3_o = driver.gpio_v_3_o; \ + assign load.gpio_v_3_oen_i = driver.gpio_v_3_oen_i; \ + assign load.gpio_v_4_o = driver.gpio_v_4_o; \ + assign load.gpio_v_4_oen_i = driver.gpio_v_4_oen_i; \ + assign load.gpio_v_5_o = driver.gpio_v_5_o; \ + assign load.gpio_v_5_oen_i = driver.gpio_v_5_oen_i; \ + assign load.gpio_v_6_o = driver.gpio_v_6_o; \ + assign load.gpio_v_6_oen_i = driver.gpio_v_6_oen_i; \ + assign load.gpio_v_7_o = driver.gpio_v_7_o; \ + assign load.gpio_v_7_oen_i = driver.gpio_v_7_oen_i; \ + assign load.gpio_v_8_o = driver.gpio_v_8_o; \ + assign load.gpio_v_8_oen_i = driver.gpio_v_8_oen_i; \ + assign load.gpio_v_9_o = driver.gpio_v_9_o; \ + assign load.gpio_v_9_oen_i = driver.gpio_v_9_oen_i; \ + assign load.gpio_v_10_o = driver.gpio_v_10_o; \ + assign load.gpio_v_10_oen_i = driver.gpio_v_10_oen_i; \ + assign load.gpio_v_11_o = driver.gpio_v_11_o; \ + assign load.gpio_v_11_oen_i = driver.gpio_v_11_oen_i; \ + assign load.gpio_v_12_o = driver.gpio_v_12_o; \ + assign load.gpio_v_12_oen_i = driver.gpio_v_12_oen_i; \ + assign load.gpio_v_13_o = driver.gpio_v_13_o; \ + assign load.gpio_v_13_oen_i = driver.gpio_v_13_oen_i; \ + assign load.gpio_v_14_o = driver.gpio_v_14_o; \ + assign load.gpio_v_14_oen_i = driver.gpio_v_14_oen_i; \ + assign load.gpio_v_15_o = driver.gpio_v_15_o; \ + assign load.gpio_v_15_oen_i = driver.gpio_v_15_oen_i; \ + assign load.gpio_v_16_o = driver.gpio_v_16_o; \ + assign load.gpio_v_16_oen_i = driver.gpio_v_16_oen_i; \ + assign load.gpio_v_17_o = driver.gpio_v_17_o; \ + assign load.gpio_v_17_oen_i = driver.gpio_v_17_oen_i; \ + + diff --git a/hw/padframe/astral_padframe/ips_list.yml b/hw/padframe/astral_padframe/ips_list.yml new file mode 100644 index 00000000..e3f94376 --- /dev/null +++ b/hw/padframe/astral_padframe/ips_list.yml @@ -0,0 +1,18 @@ + +# File auto-generated by Padrick unknown +# IPApprox dependencies for astral_padframe +common_cells: + commit: v1.21.0 + domain: [cluster, soc] + server: https://github.com + group: pulp-platform +register_interface: + commit: v0.2.1 + domain: [soc] + server: https://github.com + group: pulp-platform +axi/axi: + commit: v0.27.0 + domain: [cluster, soc] + server: https://github.com + group: pulp-platform diff --git a/hw/padframe/astral_padframe/src/astral_padframe.sv b/hw/padframe/astral_padframe/src/astral_padframe.sv new file mode 100644 index 00000000..0243abac --- /dev/null +++ b/hw/padframe/astral_padframe/src/astral_padframe.sv @@ -0,0 +1,219 @@ + +// File auto-generated by Padrick unknown +module astral_padframe + import pkg_astral_padframe::*; +#( + parameter int unsigned AW = 32, + parameter int unsigned DW = 32, + parameter type req_t = logic, // reg_interface request type + parameter type resp_t = logic, // reg_interface response type + parameter logic [DW-1:0] DecodeErrRespData = 32'hdeadda7a +)( + input logic clk_i, + input logic rst_ni, + output static_connection_signals_pad2soc_t static_connection_signals_pad2soc, + input static_connection_signals_soc2pad_t static_connection_signals_soc2pad, + output port_signals_pad2soc_t port_signals_pad2soc, + input port_signals_soc2pad_t port_signals_soc2pad, + // Landing Pads + inout wire logic pad_periph_ref_clk_pad, + inout wire logic pad_periph_fll_host_pad, + inout wire logic pad_periph_fll_periph_pad, + inout wire logic pad_periph_fll_alt_pad, + inout wire logic pad_periph_fll_rt_pad, + inout wire logic pad_periph_fll_bypass_pad, + inout wire logic pad_periph_pwr_on_rst_n_pad, + inout wire logic pad_periph_secure_boot_pad, + inout wire logic pad_periph_jtag_tclk_pad, + inout wire logic pad_periph_jtag_trst_n_pad, + inout wire logic pad_periph_jtag_tms_pad, + inout wire logic pad_periph_jtag_tdi_pad, + inout wire logic pad_periph_jtag_tdo_pad, + inout wire logic pad_periph_test_mode_pad, + inout wire logic pad_periph_boot_mode_0_pad, + inout wire logic pad_periph_boot_mode_1_pad, + inout wire logic pad_periph_ot_boot_mode_pad, + inout wire logic pad_periph_jtag_ot_tclk_pad, + inout wire logic pad_periph_jtag_ot_trst_ni_pad, + inout wire logic pad_periph_jtag_ot_tms_pad, + inout wire logic pad_periph_jtag_ot_tdi_pad, + inout wire logic pad_periph_jtag_ot_tdo_pad, + inout wire logic pad_periph_hyper_cs_0_n_pad, + inout wire logic pad_periph_hyper_cs_1_n_pad, + inout wire logic pad_periph_hyper_ck_pad, + inout wire logic pad_periph_hyper_ck_n_pad, + inout wire logic pad_periph_hyper_rwds_pad, + inout wire logic pad_periph_hyper_dq_0_pad, + inout wire logic pad_periph_hyper_dq_1_pad, + inout wire logic pad_periph_hyper_dq_2_pad, + inout wire logic pad_periph_hyper_dq_3_pad, + inout wire logic pad_periph_hyper_dq_4_pad, + inout wire logic pad_periph_hyper_dq_5_pad, + inout wire logic pad_periph_hyper_dq_6_pad, + inout wire logic pad_periph_hyper_dq_7_pad, + inout wire logic pad_periph_hyper_reset_n_pad, + inout wire logic pad_periph_spw_data_in_pad, + inout wire logic pad_periph_spw_strb_in_pad, + inout wire logic pad_periph_spw_data_out_pad, + inout wire logic pad_periph_spw_strb_out_pad, + inout wire logic pad_periph_uart_tx_out_pad, + inout wire logic pad_periph_uart_rx_in_pad, + inout wire logic pad_periph_muxed_v_00_pad, + inout wire logic pad_periph_muxed_v_01_pad, + inout wire logic pad_periph_muxed_v_02_pad, + inout wire logic pad_periph_muxed_v_03_pad, + inout wire logic pad_periph_muxed_v_04_pad, + inout wire logic pad_periph_muxed_v_05_pad, + inout wire logic pad_periph_muxed_v_06_pad, + inout wire logic pad_periph_muxed_v_07_pad, + inout wire logic pad_periph_muxed_v_08_pad, + inout wire logic pad_periph_muxed_v_09_pad, + inout wire logic pad_periph_muxed_v_10_pad, + inout wire logic pad_periph_muxed_v_11_pad, + inout wire logic pad_periph_muxed_v_12_pad, + inout wire logic pad_periph_muxed_v_13_pad, + inout wire logic pad_periph_muxed_v_14_pad, + inout wire logic pad_periph_muxed_v_15_pad, + inout wire logic pad_periph_muxed_v_16_pad, + inout wire logic pad_periph_muxed_v_17_pad, + inout wire logic pad_periph_muxed_h_00_pad, + inout wire logic pad_periph_muxed_h_01_pad, + inout wire logic pad_periph_muxed_h_02_pad, + inout wire logic pad_periph_muxed_h_03_pad, + // Config Interface + input req_t config_req_i, + output resp_t config_rsp_o + ); + + + req_t periph_config_req; + resp_t periph_config_resp; + astral_padframe_periph #( + .req_t(req_t), + .resp_t(resp_t) + ) i_periph ( + .clk_i, + .rst_ni, + .static_connection_signals_pad2soc(static_connection_signals_pad2soc.periph), + .static_connection_signals_soc2pad(static_connection_signals_soc2pad.periph), + .port_signals_pad2soc_o(port_signals_pad2soc.periph), + .port_signals_soc2pad_i(port_signals_soc2pad.periph), + .pad_ref_clk_pad(pad_periph_ref_clk_pad), + .pad_fll_host_pad(pad_periph_fll_host_pad), + .pad_fll_periph_pad(pad_periph_fll_periph_pad), + .pad_fll_alt_pad(pad_periph_fll_alt_pad), + .pad_fll_rt_pad(pad_periph_fll_rt_pad), + .pad_fll_bypass_pad(pad_periph_fll_bypass_pad), + .pad_pwr_on_rst_n_pad(pad_periph_pwr_on_rst_n_pad), + .pad_secure_boot_pad(pad_periph_secure_boot_pad), + .pad_jtag_tclk_pad(pad_periph_jtag_tclk_pad), + .pad_jtag_trst_n_pad(pad_periph_jtag_trst_n_pad), + .pad_jtag_tms_pad(pad_periph_jtag_tms_pad), + .pad_jtag_tdi_pad(pad_periph_jtag_tdi_pad), + .pad_jtag_tdo_pad(pad_periph_jtag_tdo_pad), + .pad_test_mode_pad(pad_periph_test_mode_pad), + .pad_boot_mode_0_pad(pad_periph_boot_mode_0_pad), + .pad_boot_mode_1_pad(pad_periph_boot_mode_1_pad), + .pad_ot_boot_mode_pad(pad_periph_ot_boot_mode_pad), + .pad_jtag_ot_tclk_pad(pad_periph_jtag_ot_tclk_pad), + .pad_jtag_ot_trst_ni_pad(pad_periph_jtag_ot_trst_ni_pad), + .pad_jtag_ot_tms_pad(pad_periph_jtag_ot_tms_pad), + .pad_jtag_ot_tdi_pad(pad_periph_jtag_ot_tdi_pad), + .pad_jtag_ot_tdo_pad(pad_periph_jtag_ot_tdo_pad), + .pad_hyper_cs_0_n_pad(pad_periph_hyper_cs_0_n_pad), + .pad_hyper_cs_1_n_pad(pad_periph_hyper_cs_1_n_pad), + .pad_hyper_ck_pad(pad_periph_hyper_ck_pad), + .pad_hyper_ck_n_pad(pad_periph_hyper_ck_n_pad), + .pad_hyper_rwds_pad(pad_periph_hyper_rwds_pad), + .pad_hyper_dq_0_pad(pad_periph_hyper_dq_0_pad), + .pad_hyper_dq_1_pad(pad_periph_hyper_dq_1_pad), + .pad_hyper_dq_2_pad(pad_periph_hyper_dq_2_pad), + .pad_hyper_dq_3_pad(pad_periph_hyper_dq_3_pad), + .pad_hyper_dq_4_pad(pad_periph_hyper_dq_4_pad), + .pad_hyper_dq_5_pad(pad_periph_hyper_dq_5_pad), + .pad_hyper_dq_6_pad(pad_periph_hyper_dq_6_pad), + .pad_hyper_dq_7_pad(pad_periph_hyper_dq_7_pad), + .pad_hyper_reset_n_pad(pad_periph_hyper_reset_n_pad), + .pad_spw_data_in_pad(pad_periph_spw_data_in_pad), + .pad_spw_strb_in_pad(pad_periph_spw_strb_in_pad), + .pad_spw_data_out_pad(pad_periph_spw_data_out_pad), + .pad_spw_strb_out_pad(pad_periph_spw_strb_out_pad), + .pad_uart_tx_out_pad(pad_periph_uart_tx_out_pad), + .pad_uart_rx_in_pad(pad_periph_uart_rx_in_pad), + .pad_muxed_v_00_pad(pad_periph_muxed_v_00_pad), + .pad_muxed_v_01_pad(pad_periph_muxed_v_01_pad), + .pad_muxed_v_02_pad(pad_periph_muxed_v_02_pad), + .pad_muxed_v_03_pad(pad_periph_muxed_v_03_pad), + .pad_muxed_v_04_pad(pad_periph_muxed_v_04_pad), + .pad_muxed_v_05_pad(pad_periph_muxed_v_05_pad), + .pad_muxed_v_06_pad(pad_periph_muxed_v_06_pad), + .pad_muxed_v_07_pad(pad_periph_muxed_v_07_pad), + .pad_muxed_v_08_pad(pad_periph_muxed_v_08_pad), + .pad_muxed_v_09_pad(pad_periph_muxed_v_09_pad), + .pad_muxed_v_10_pad(pad_periph_muxed_v_10_pad), + .pad_muxed_v_11_pad(pad_periph_muxed_v_11_pad), + .pad_muxed_v_12_pad(pad_periph_muxed_v_12_pad), + .pad_muxed_v_13_pad(pad_periph_muxed_v_13_pad), + .pad_muxed_v_14_pad(pad_periph_muxed_v_14_pad), + .pad_muxed_v_15_pad(pad_periph_muxed_v_15_pad), + .pad_muxed_v_16_pad(pad_periph_muxed_v_16_pad), + .pad_muxed_v_17_pad(pad_periph_muxed_v_17_pad), + .pad_muxed_h_00_pad(pad_periph_muxed_h_00_pad), + .pad_muxed_h_01_pad(pad_periph_muxed_h_01_pad), + .pad_muxed_h_02_pad(pad_periph_muxed_h_02_pad), + .pad_muxed_h_03_pad(pad_periph_muxed_h_03_pad), + .config_req_i(periph_config_req), + .config_rsp_o(periph_config_resp) + ); + + + localparam int unsigned NUM_PAD_DOMAINS = 1; + localparam int unsigned REG_ADDR_WIDTH = 8; + typedef struct packed { + int unsigned idx; + logic [REG_ADDR_WIDTH-1:0] start_addr; + logic [REG_ADDR_WIDTH-1:0] end_addr; + } addr_rule_t; + + localparam addr_rule_t[NUM_PAD_DOMAINS-1:0] ADDR_DEMUX_RULES = '{ + '{ idx: 0, start_addr: 8'd0, end_addr: 8'd180} + }; + logic[$clog2(NUM_PAD_DOMAINS+1)-1:0] pad_domain_sel; // +1 since there is an additional error slave + addr_decode #( + .NoIndices(NUM_PAD_DOMAINS+1), + .NoRules(NUM_PAD_DOMAINS), + .addr_t(logic[REG_ADDR_WIDTH-1:0]), + .rule_t(addr_rule_t) + ) i_addr_decode( + .addr_i(config_req_i.addr[REG_ADDR_WIDTH-1:0]), + .addr_map_i(ADDR_DEMUX_RULES), + .dec_valid_o(), + .dec_error_o(), + .idx_o(pad_domain_sel), + .en_default_idx_i(1'b1), + .default_idx_i(1'd1) // The last entry is the error slave + ); + + req_t error_slave_req; + resp_t error_slave_rsp; + + // Config Interface demultiplexing + reg_demux #( + .NoPorts(NUM_PAD_DOMAINS+1), //+1 for the error slave + .req_t(req_t), + .rsp_t(resp_t) + ) i_config_demuxer ( + .clk_i, + .rst_ni, + .in_select_i(pad_domain_sel), + .in_req_i(config_req_i), + .in_rsp_o(config_rsp_o), + .out_req_o({error_slave_req, periph_config_req}), + .out_rsp_i({error_slave_rsp, periph_config_resp}) + ); + + assign error_slave_rsp.error = 1'b1; + assign error_slave_rsp.rdata = DecodeErrRespData; + assign error_slave_rsp.ready = 1'b1; + +endmodule diff --git a/hw/padframe/astral_padframe/src/astral_padframe_periph.sv b/hw/padframe/astral_padframe/src/astral_padframe_periph.sv new file mode 100644 index 00000000..214c6991 --- /dev/null +++ b/hw/padframe/astral_padframe/src/astral_padframe_periph.sv @@ -0,0 +1,174 @@ + +// File auto-generated by Padrick unknown +module astral_padframe_periph + import pkg_astral_padframe::*; + import pkg_internal_astral_padframe_periph::*; +#( + parameter type req_t = logic, // reg_interface request type + parameter type resp_t = logic // reg_interface response type +) ( + input logic clk_i, + input logic rst_ni, + output pad_domain_periph_static_connection_signals_pad2soc_t static_connection_signals_pad2soc, + input pad_domain_periph_static_connection_signals_soc2pad_t static_connection_signals_soc2pad, + output pad_domain_periph_ports_pad2soc_t port_signals_pad2soc_o, + input pad_domain_periph_ports_soc2pad_t port_signals_soc2pad_i, + inout wire logic pad_ref_clk_pad, + inout wire logic pad_fll_host_pad, + inout wire logic pad_fll_periph_pad, + inout wire logic pad_fll_alt_pad, + inout wire logic pad_fll_rt_pad, + inout wire logic pad_fll_bypass_pad, + inout wire logic pad_pwr_on_rst_n_pad, + inout wire logic pad_secure_boot_pad, + inout wire logic pad_jtag_tclk_pad, + inout wire logic pad_jtag_trst_n_pad, + inout wire logic pad_jtag_tms_pad, + inout wire logic pad_jtag_tdi_pad, + inout wire logic pad_jtag_tdo_pad, + inout wire logic pad_test_mode_pad, + inout wire logic pad_boot_mode_0_pad, + inout wire logic pad_boot_mode_1_pad, + inout wire logic pad_ot_boot_mode_pad, + inout wire logic pad_jtag_ot_tclk_pad, + inout wire logic pad_jtag_ot_trst_ni_pad, + inout wire logic pad_jtag_ot_tms_pad, + inout wire logic pad_jtag_ot_tdi_pad, + inout wire logic pad_jtag_ot_tdo_pad, + inout wire logic pad_hyper_cs_0_n_pad, + inout wire logic pad_hyper_cs_1_n_pad, + inout wire logic pad_hyper_ck_pad, + inout wire logic pad_hyper_ck_n_pad, + inout wire logic pad_hyper_rwds_pad, + inout wire logic pad_hyper_dq_0_pad, + inout wire logic pad_hyper_dq_1_pad, + inout wire logic pad_hyper_dq_2_pad, + inout wire logic pad_hyper_dq_3_pad, + inout wire logic pad_hyper_dq_4_pad, + inout wire logic pad_hyper_dq_5_pad, + inout wire logic pad_hyper_dq_6_pad, + inout wire logic pad_hyper_dq_7_pad, + inout wire logic pad_hyper_reset_n_pad, + inout wire logic pad_spw_data_in_pad, + inout wire logic pad_spw_strb_in_pad, + inout wire logic pad_spw_data_out_pad, + inout wire logic pad_spw_strb_out_pad, + inout wire logic pad_uart_tx_out_pad, + inout wire logic pad_uart_rx_in_pad, + inout wire logic pad_muxed_v_00_pad, + inout wire logic pad_muxed_v_01_pad, + inout wire logic pad_muxed_v_02_pad, + inout wire logic pad_muxed_v_03_pad, + inout wire logic pad_muxed_v_04_pad, + inout wire logic pad_muxed_v_05_pad, + inout wire logic pad_muxed_v_06_pad, + inout wire logic pad_muxed_v_07_pad, + inout wire logic pad_muxed_v_08_pad, + inout wire logic pad_muxed_v_09_pad, + inout wire logic pad_muxed_v_10_pad, + inout wire logic pad_muxed_v_11_pad, + inout wire logic pad_muxed_v_12_pad, + inout wire logic pad_muxed_v_13_pad, + inout wire logic pad_muxed_v_14_pad, + inout wire logic pad_muxed_v_15_pad, + inout wire logic pad_muxed_v_16_pad, + inout wire logic pad_muxed_v_17_pad, + inout wire logic pad_muxed_h_00_pad, + inout wire logic pad_muxed_h_01_pad, + inout wire logic pad_muxed_h_02_pad, + inout wire logic pad_muxed_h_03_pad, + input req_t config_req_i, + output resp_t config_rsp_o +); + + mux_to_pads_t s_mux_to_pads; + pads_to_mux_t s_pads_to_mux; + + astral_padframe_periph_pads i_periph_pads ( + .static_connection_signals_pad2soc, + .static_connection_signals_soc2pad, + .mux_to_pads_i(s_mux_to_pads), + .pads_to_mux_o(s_pads_to_mux), + .pad_ref_clk_pad, + .pad_fll_host_pad, + .pad_fll_periph_pad, + .pad_fll_alt_pad, + .pad_fll_rt_pad, + .pad_fll_bypass_pad, + .pad_pwr_on_rst_n_pad, + .pad_secure_boot_pad, + .pad_jtag_tclk_pad, + .pad_jtag_trst_n_pad, + .pad_jtag_tms_pad, + .pad_jtag_tdi_pad, + .pad_jtag_tdo_pad, + .pad_test_mode_pad, + .pad_boot_mode_0_pad, + .pad_boot_mode_1_pad, + .pad_ot_boot_mode_pad, + .pad_jtag_ot_tclk_pad, + .pad_jtag_ot_trst_ni_pad, + .pad_jtag_ot_tms_pad, + .pad_jtag_ot_tdi_pad, + .pad_jtag_ot_tdo_pad, + .pad_hyper_cs_0_n_pad, + .pad_hyper_cs_1_n_pad, + .pad_hyper_ck_pad, + .pad_hyper_ck_n_pad, + .pad_hyper_rwds_pad, + .pad_hyper_dq_0_pad, + .pad_hyper_dq_1_pad, + .pad_hyper_dq_2_pad, + .pad_hyper_dq_3_pad, + .pad_hyper_dq_4_pad, + .pad_hyper_dq_5_pad, + .pad_hyper_dq_6_pad, + .pad_hyper_dq_7_pad, + .pad_hyper_reset_n_pad, + .pad_spw_data_in_pad, + .pad_spw_strb_in_pad, + .pad_spw_data_out_pad, + .pad_spw_strb_out_pad, + .pad_uart_tx_out_pad, + .pad_uart_rx_in_pad, + .pad_muxed_v_00_pad, + .pad_muxed_v_01_pad, + .pad_muxed_v_02_pad, + .pad_muxed_v_03_pad, + .pad_muxed_v_04_pad, + .pad_muxed_v_05_pad, + .pad_muxed_v_06_pad, + .pad_muxed_v_07_pad, + .pad_muxed_v_08_pad, + .pad_muxed_v_09_pad, + .pad_muxed_v_10_pad, + .pad_muxed_v_11_pad, + .pad_muxed_v_12_pad, + .pad_muxed_v_13_pad, + .pad_muxed_v_14_pad, + .pad_muxed_v_15_pad, + .pad_muxed_v_16_pad, + .pad_muxed_v_17_pad, + .pad_muxed_h_00_pad, + .pad_muxed_h_01_pad, + .pad_muxed_h_02_pad, + .pad_muxed_h_03_pad + + ); + + astral_padframe_periph_muxer #( + .req_t(req_t), + .resp_t(resp_t) + )i_periph_muxer ( + .clk_i, + .rst_ni, + .port_signals_soc2pad_i, + .port_signals_pad2soc_o, + .mux_to_pads_o(s_mux_to_pads), + .pads_to_mux_i(s_pads_to_mux), + // Configuration interface using register_interface protocol + .config_req_i, + .config_rsp_o + ); + +endmodule : astral_padframe_periph diff --git a/hw/padframe/astral_padframe/src/astral_padframe_periph_config_reg_pkg.sv b/hw/padframe/astral_padframe/src/astral_padframe_periph_config_reg_pkg.sv new file mode 100644 index 00000000..d95ed4b0 --- /dev/null +++ b/hw/padframe/astral_padframe/src/astral_padframe_periph_config_reg_pkg.sv @@ -0,0 +1,704 @@ +// Copyright lowRISC contributors. +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +// +// Register Package auto-generated by `reggen` containing data structure + +package astral_padframe_periph_config_reg_pkg; + + // Address widths within the block + parameter int BlockAw = 8; + + //////////////////////////// + // Typedefs for registers // + //////////////////////////// + + typedef struct packed { + struct packed { + logic [15:0] q; + } hw_version; + struct packed { + logic [15:0] q; + } padcount; + } astral_padframe_periph_config_reg2hw_info_reg_t; + + typedef struct packed { + struct packed { + logic q; + } chip2pad; + struct packed { + logic q; + } input_en; + struct packed { + logic q; + } output_en; + struct packed { + logic q; + } pull_en; + struct packed { + logic q; + } pull_sel; + } astral_padframe_periph_config_reg2hw_muxed_v_00_cfg_reg_t; + + typedef struct packed { + logic [2:0] q; + } astral_padframe_periph_config_reg2hw_muxed_v_00_mux_sel_reg_t; + + typedef struct packed { + struct packed { + logic q; + } chip2pad; + struct packed { + logic q; + } input_en; + struct packed { + logic q; + } output_en; + struct packed { + logic q; + } pull_en; + struct packed { + logic q; + } pull_sel; + } astral_padframe_periph_config_reg2hw_muxed_v_01_cfg_reg_t; + + typedef struct packed { + logic [2:0] q; + } astral_padframe_periph_config_reg2hw_muxed_v_01_mux_sel_reg_t; + + typedef struct packed { + struct packed { + logic q; + } chip2pad; + struct packed { + logic q; + } input_en; + struct packed { + logic q; + } output_en; + struct packed { + logic q; + } pull_en; + struct packed { + logic q; + } pull_sel; + } astral_padframe_periph_config_reg2hw_muxed_v_02_cfg_reg_t; + + typedef struct packed { + logic [1:0] q; + } astral_padframe_periph_config_reg2hw_muxed_v_02_mux_sel_reg_t; + + typedef struct packed { + struct packed { + logic q; + } chip2pad; + struct packed { + logic q; + } input_en; + struct packed { + logic q; + } output_en; + struct packed { + logic q; + } pull_en; + struct packed { + logic q; + } pull_sel; + } astral_padframe_periph_config_reg2hw_muxed_v_03_cfg_reg_t; + + typedef struct packed { + logic [1:0] q; + } astral_padframe_periph_config_reg2hw_muxed_v_03_mux_sel_reg_t; + + typedef struct packed { + struct packed { + logic q; + } chip2pad; + struct packed { + logic q; + } input_en; + struct packed { + logic q; + } output_en; + struct packed { + logic q; + } pull_en; + struct packed { + logic q; + } pull_sel; + } astral_padframe_periph_config_reg2hw_muxed_v_04_cfg_reg_t; + + typedef struct packed { + logic [2:0] q; + } astral_padframe_periph_config_reg2hw_muxed_v_04_mux_sel_reg_t; + + typedef struct packed { + struct packed { + logic q; + } chip2pad; + struct packed { + logic q; + } input_en; + struct packed { + logic q; + } output_en; + struct packed { + logic q; + } pull_en; + struct packed { + logic q; + } pull_sel; + } astral_padframe_periph_config_reg2hw_muxed_v_05_cfg_reg_t; + + typedef struct packed { + logic [2:0] q; + } astral_padframe_periph_config_reg2hw_muxed_v_05_mux_sel_reg_t; + + typedef struct packed { + struct packed { + logic q; + } chip2pad; + struct packed { + logic q; + } input_en; + struct packed { + logic q; + } output_en; + struct packed { + logic q; + } pull_en; + struct packed { + logic q; + } pull_sel; + } astral_padframe_periph_config_reg2hw_muxed_v_06_cfg_reg_t; + + typedef struct packed { + logic [1:0] q; + } astral_padframe_periph_config_reg2hw_muxed_v_06_mux_sel_reg_t; + + typedef struct packed { + struct packed { + logic q; + } chip2pad; + struct packed { + logic q; + } input_en; + struct packed { + logic q; + } output_en; + struct packed { + logic q; + } pull_en; + struct packed { + logic q; + } pull_sel; + } astral_padframe_periph_config_reg2hw_muxed_v_07_cfg_reg_t; + + typedef struct packed { + logic [2:0] q; + } astral_padframe_periph_config_reg2hw_muxed_v_07_mux_sel_reg_t; + + typedef struct packed { + struct packed { + logic q; + } chip2pad; + struct packed { + logic q; + } input_en; + struct packed { + logic q; + } output_en; + struct packed { + logic q; + } pull_en; + struct packed { + logic q; + } pull_sel; + } astral_padframe_periph_config_reg2hw_muxed_v_08_cfg_reg_t; + + typedef struct packed { + logic [2:0] q; + } astral_padframe_periph_config_reg2hw_muxed_v_08_mux_sel_reg_t; + + typedef struct packed { + struct packed { + logic q; + } chip2pad; + struct packed { + logic q; + } input_en; + struct packed { + logic q; + } output_en; + struct packed { + logic q; + } pull_en; + struct packed { + logic q; + } pull_sel; + } astral_padframe_periph_config_reg2hw_muxed_v_09_cfg_reg_t; + + typedef struct packed { + logic [2:0] q; + } astral_padframe_periph_config_reg2hw_muxed_v_09_mux_sel_reg_t; + + typedef struct packed { + struct packed { + logic q; + } chip2pad; + struct packed { + logic q; + } input_en; + struct packed { + logic q; + } output_en; + struct packed { + logic q; + } pull_en; + struct packed { + logic q; + } pull_sel; + } astral_padframe_periph_config_reg2hw_muxed_v_10_cfg_reg_t; + + typedef struct packed { + logic [2:0] q; + } astral_padframe_periph_config_reg2hw_muxed_v_10_mux_sel_reg_t; + + typedef struct packed { + struct packed { + logic q; + } chip2pad; + struct packed { + logic q; + } input_en; + struct packed { + logic q; + } output_en; + struct packed { + logic q; + } pull_en; + struct packed { + logic q; + } pull_sel; + } astral_padframe_periph_config_reg2hw_muxed_v_11_cfg_reg_t; + + typedef struct packed { + logic [2:0] q; + } astral_padframe_periph_config_reg2hw_muxed_v_11_mux_sel_reg_t; + + typedef struct packed { + struct packed { + logic q; + } chip2pad; + struct packed { + logic q; + } input_en; + struct packed { + logic q; + } output_en; + struct packed { + logic q; + } pull_en; + struct packed { + logic q; + } pull_sel; + } astral_padframe_periph_config_reg2hw_muxed_v_12_cfg_reg_t; + + typedef struct packed { + logic [2:0] q; + } astral_padframe_periph_config_reg2hw_muxed_v_12_mux_sel_reg_t; + + typedef struct packed { + struct packed { + logic q; + } chip2pad; + struct packed { + logic q; + } input_en; + struct packed { + logic q; + } output_en; + struct packed { + logic q; + } pull_en; + struct packed { + logic q; + } pull_sel; + } astral_padframe_periph_config_reg2hw_muxed_v_13_cfg_reg_t; + + typedef struct packed { + logic [2:0] q; + } astral_padframe_periph_config_reg2hw_muxed_v_13_mux_sel_reg_t; + + typedef struct packed { + struct packed { + logic q; + } chip2pad; + struct packed { + logic q; + } input_en; + struct packed { + logic q; + } output_en; + struct packed { + logic q; + } pull_en; + struct packed { + logic q; + } pull_sel; + } astral_padframe_periph_config_reg2hw_muxed_v_14_cfg_reg_t; + + typedef struct packed { + logic [2:0] q; + } astral_padframe_periph_config_reg2hw_muxed_v_14_mux_sel_reg_t; + + typedef struct packed { + struct packed { + logic q; + } chip2pad; + struct packed { + logic q; + } input_en; + struct packed { + logic q; + } output_en; + struct packed { + logic q; + } pull_en; + struct packed { + logic q; + } pull_sel; + } astral_padframe_periph_config_reg2hw_muxed_v_15_cfg_reg_t; + + typedef struct packed { + logic [2:0] q; + } astral_padframe_periph_config_reg2hw_muxed_v_15_mux_sel_reg_t; + + typedef struct packed { + struct packed { + logic q; + } chip2pad; + struct packed { + logic q; + } input_en; + struct packed { + logic q; + } output_en; + struct packed { + logic q; + } pull_en; + struct packed { + logic q; + } pull_sel; + } astral_padframe_periph_config_reg2hw_muxed_v_16_cfg_reg_t; + + typedef struct packed { + logic [2:0] q; + } astral_padframe_periph_config_reg2hw_muxed_v_16_mux_sel_reg_t; + + typedef struct packed { + struct packed { + logic q; + } chip2pad; + struct packed { + logic q; + } input_en; + struct packed { + logic q; + } output_en; + struct packed { + logic q; + } pull_en; + struct packed { + logic q; + } pull_sel; + } astral_padframe_periph_config_reg2hw_muxed_v_17_cfg_reg_t; + + typedef struct packed { + logic [2:0] q; + } astral_padframe_periph_config_reg2hw_muxed_v_17_mux_sel_reg_t; + + typedef struct packed { + struct packed { + logic q; + } chip2pad; + struct packed { + logic q; + } input_en; + struct packed { + logic q; + } output_en; + struct packed { + logic q; + } pull_en; + struct packed { + logic q; + } pull_sel; + } astral_padframe_periph_config_reg2hw_muxed_h_00_cfg_reg_t; + + typedef struct packed { + logic [2:0] q; + } astral_padframe_periph_config_reg2hw_muxed_h_00_mux_sel_reg_t; + + typedef struct packed { + struct packed { + logic q; + } chip2pad; + struct packed { + logic q; + } input_en; + struct packed { + logic q; + } output_en; + struct packed { + logic q; + } pull_en; + struct packed { + logic q; + } pull_sel; + } astral_padframe_periph_config_reg2hw_muxed_h_01_cfg_reg_t; + + typedef struct packed { + logic [2:0] q; + } astral_padframe_periph_config_reg2hw_muxed_h_01_mux_sel_reg_t; + + typedef struct packed { + struct packed { + logic q; + } chip2pad; + struct packed { + logic q; + } input_en; + struct packed { + logic q; + } output_en; + struct packed { + logic q; + } pull_en; + struct packed { + logic q; + } pull_sel; + } astral_padframe_periph_config_reg2hw_muxed_h_02_cfg_reg_t; + + typedef struct packed { + logic [2:0] q; + } astral_padframe_periph_config_reg2hw_muxed_h_02_mux_sel_reg_t; + + typedef struct packed { + struct packed { + logic q; + } chip2pad; + struct packed { + logic q; + } input_en; + struct packed { + logic q; + } output_en; + struct packed { + logic q; + } pull_en; + struct packed { + logic q; + } pull_sel; + } astral_padframe_periph_config_reg2hw_muxed_h_03_cfg_reg_t; + + typedef struct packed { + logic [2:0] q; + } astral_padframe_periph_config_reg2hw_muxed_h_03_mux_sel_reg_t; + + // Register -> HW type + typedef struct packed { + astral_padframe_periph_config_reg2hw_info_reg_t info; // [204:173] + astral_padframe_periph_config_reg2hw_muxed_v_00_cfg_reg_t muxed_v_00_cfg; // [172:168] + astral_padframe_periph_config_reg2hw_muxed_v_00_mux_sel_reg_t muxed_v_00_mux_sel; // [167:165] + astral_padframe_periph_config_reg2hw_muxed_v_01_cfg_reg_t muxed_v_01_cfg; // [164:160] + astral_padframe_periph_config_reg2hw_muxed_v_01_mux_sel_reg_t muxed_v_01_mux_sel; // [159:157] + astral_padframe_periph_config_reg2hw_muxed_v_02_cfg_reg_t muxed_v_02_cfg; // [156:152] + astral_padframe_periph_config_reg2hw_muxed_v_02_mux_sel_reg_t muxed_v_02_mux_sel; // [151:150] + astral_padframe_periph_config_reg2hw_muxed_v_03_cfg_reg_t muxed_v_03_cfg; // [149:145] + astral_padframe_periph_config_reg2hw_muxed_v_03_mux_sel_reg_t muxed_v_03_mux_sel; // [144:143] + astral_padframe_periph_config_reg2hw_muxed_v_04_cfg_reg_t muxed_v_04_cfg; // [142:138] + astral_padframe_periph_config_reg2hw_muxed_v_04_mux_sel_reg_t muxed_v_04_mux_sel; // [137:135] + astral_padframe_periph_config_reg2hw_muxed_v_05_cfg_reg_t muxed_v_05_cfg; // [134:130] + astral_padframe_periph_config_reg2hw_muxed_v_05_mux_sel_reg_t muxed_v_05_mux_sel; // [129:127] + astral_padframe_periph_config_reg2hw_muxed_v_06_cfg_reg_t muxed_v_06_cfg; // [126:122] + astral_padframe_periph_config_reg2hw_muxed_v_06_mux_sel_reg_t muxed_v_06_mux_sel; // [121:120] + astral_padframe_periph_config_reg2hw_muxed_v_07_cfg_reg_t muxed_v_07_cfg; // [119:115] + astral_padframe_periph_config_reg2hw_muxed_v_07_mux_sel_reg_t muxed_v_07_mux_sel; // [114:112] + astral_padframe_periph_config_reg2hw_muxed_v_08_cfg_reg_t muxed_v_08_cfg; // [111:107] + astral_padframe_periph_config_reg2hw_muxed_v_08_mux_sel_reg_t muxed_v_08_mux_sel; // [106:104] + astral_padframe_periph_config_reg2hw_muxed_v_09_cfg_reg_t muxed_v_09_cfg; // [103:99] + astral_padframe_periph_config_reg2hw_muxed_v_09_mux_sel_reg_t muxed_v_09_mux_sel; // [98:96] + astral_padframe_periph_config_reg2hw_muxed_v_10_cfg_reg_t muxed_v_10_cfg; // [95:91] + astral_padframe_periph_config_reg2hw_muxed_v_10_mux_sel_reg_t muxed_v_10_mux_sel; // [90:88] + astral_padframe_periph_config_reg2hw_muxed_v_11_cfg_reg_t muxed_v_11_cfg; // [87:83] + astral_padframe_periph_config_reg2hw_muxed_v_11_mux_sel_reg_t muxed_v_11_mux_sel; // [82:80] + astral_padframe_periph_config_reg2hw_muxed_v_12_cfg_reg_t muxed_v_12_cfg; // [79:75] + astral_padframe_periph_config_reg2hw_muxed_v_12_mux_sel_reg_t muxed_v_12_mux_sel; // [74:72] + astral_padframe_periph_config_reg2hw_muxed_v_13_cfg_reg_t muxed_v_13_cfg; // [71:67] + astral_padframe_periph_config_reg2hw_muxed_v_13_mux_sel_reg_t muxed_v_13_mux_sel; // [66:64] + astral_padframe_periph_config_reg2hw_muxed_v_14_cfg_reg_t muxed_v_14_cfg; // [63:59] + astral_padframe_periph_config_reg2hw_muxed_v_14_mux_sel_reg_t muxed_v_14_mux_sel; // [58:56] + astral_padframe_periph_config_reg2hw_muxed_v_15_cfg_reg_t muxed_v_15_cfg; // [55:51] + astral_padframe_periph_config_reg2hw_muxed_v_15_mux_sel_reg_t muxed_v_15_mux_sel; // [50:48] + astral_padframe_periph_config_reg2hw_muxed_v_16_cfg_reg_t muxed_v_16_cfg; // [47:43] + astral_padframe_periph_config_reg2hw_muxed_v_16_mux_sel_reg_t muxed_v_16_mux_sel; // [42:40] + astral_padframe_periph_config_reg2hw_muxed_v_17_cfg_reg_t muxed_v_17_cfg; // [39:35] + astral_padframe_periph_config_reg2hw_muxed_v_17_mux_sel_reg_t muxed_v_17_mux_sel; // [34:32] + astral_padframe_periph_config_reg2hw_muxed_h_00_cfg_reg_t muxed_h_00_cfg; // [31:27] + astral_padframe_periph_config_reg2hw_muxed_h_00_mux_sel_reg_t muxed_h_00_mux_sel; // [26:24] + astral_padframe_periph_config_reg2hw_muxed_h_01_cfg_reg_t muxed_h_01_cfg; // [23:19] + astral_padframe_periph_config_reg2hw_muxed_h_01_mux_sel_reg_t muxed_h_01_mux_sel; // [18:16] + astral_padframe_periph_config_reg2hw_muxed_h_02_cfg_reg_t muxed_h_02_cfg; // [15:11] + astral_padframe_periph_config_reg2hw_muxed_h_02_mux_sel_reg_t muxed_h_02_mux_sel; // [10:8] + astral_padframe_periph_config_reg2hw_muxed_h_03_cfg_reg_t muxed_h_03_cfg; // [7:3] + astral_padframe_periph_config_reg2hw_muxed_h_03_mux_sel_reg_t muxed_h_03_mux_sel; // [2:0] + } astral_padframe_periph_config_reg2hw_t; + + // Register offsets + parameter logic [BlockAw-1:0] ASTRAL_PADFRAME_PERIPH_CONFIG_INFO_OFFSET = 8'h 0; + parameter logic [BlockAw-1:0] ASTRAL_PADFRAME_PERIPH_CONFIG_MUXED_V_00_CFG_OFFSET = 8'h 4; + parameter logic [BlockAw-1:0] ASTRAL_PADFRAME_PERIPH_CONFIG_MUXED_V_00_MUX_SEL_OFFSET = 8'h 8; + parameter logic [BlockAw-1:0] ASTRAL_PADFRAME_PERIPH_CONFIG_MUXED_V_01_CFG_OFFSET = 8'h c; + parameter logic [BlockAw-1:0] ASTRAL_PADFRAME_PERIPH_CONFIG_MUXED_V_01_MUX_SEL_OFFSET = 8'h 10; + parameter logic [BlockAw-1:0] ASTRAL_PADFRAME_PERIPH_CONFIG_MUXED_V_02_CFG_OFFSET = 8'h 14; + parameter logic [BlockAw-1:0] ASTRAL_PADFRAME_PERIPH_CONFIG_MUXED_V_02_MUX_SEL_OFFSET = 8'h 18; + parameter logic [BlockAw-1:0] ASTRAL_PADFRAME_PERIPH_CONFIG_MUXED_V_03_CFG_OFFSET = 8'h 1c; + parameter logic [BlockAw-1:0] ASTRAL_PADFRAME_PERIPH_CONFIG_MUXED_V_03_MUX_SEL_OFFSET = 8'h 20; + parameter logic [BlockAw-1:0] ASTRAL_PADFRAME_PERIPH_CONFIG_MUXED_V_04_CFG_OFFSET = 8'h 24; + parameter logic [BlockAw-1:0] ASTRAL_PADFRAME_PERIPH_CONFIG_MUXED_V_04_MUX_SEL_OFFSET = 8'h 28; + parameter logic [BlockAw-1:0] ASTRAL_PADFRAME_PERIPH_CONFIG_MUXED_V_05_CFG_OFFSET = 8'h 2c; + parameter logic [BlockAw-1:0] ASTRAL_PADFRAME_PERIPH_CONFIG_MUXED_V_05_MUX_SEL_OFFSET = 8'h 30; + parameter logic [BlockAw-1:0] ASTRAL_PADFRAME_PERIPH_CONFIG_MUXED_V_06_CFG_OFFSET = 8'h 34; + parameter logic [BlockAw-1:0] ASTRAL_PADFRAME_PERIPH_CONFIG_MUXED_V_06_MUX_SEL_OFFSET = 8'h 38; + parameter logic [BlockAw-1:0] ASTRAL_PADFRAME_PERIPH_CONFIG_MUXED_V_07_CFG_OFFSET = 8'h 3c; + parameter logic [BlockAw-1:0] ASTRAL_PADFRAME_PERIPH_CONFIG_MUXED_V_07_MUX_SEL_OFFSET = 8'h 40; + parameter logic [BlockAw-1:0] ASTRAL_PADFRAME_PERIPH_CONFIG_MUXED_V_08_CFG_OFFSET = 8'h 44; + parameter logic [BlockAw-1:0] ASTRAL_PADFRAME_PERIPH_CONFIG_MUXED_V_08_MUX_SEL_OFFSET = 8'h 48; + parameter logic [BlockAw-1:0] ASTRAL_PADFRAME_PERIPH_CONFIG_MUXED_V_09_CFG_OFFSET = 8'h 4c; + parameter logic [BlockAw-1:0] ASTRAL_PADFRAME_PERIPH_CONFIG_MUXED_V_09_MUX_SEL_OFFSET = 8'h 50; + parameter logic [BlockAw-1:0] ASTRAL_PADFRAME_PERIPH_CONFIG_MUXED_V_10_CFG_OFFSET = 8'h 54; + parameter logic [BlockAw-1:0] ASTRAL_PADFRAME_PERIPH_CONFIG_MUXED_V_10_MUX_SEL_OFFSET = 8'h 58; + parameter logic [BlockAw-1:0] ASTRAL_PADFRAME_PERIPH_CONFIG_MUXED_V_11_CFG_OFFSET = 8'h 5c; + parameter logic [BlockAw-1:0] ASTRAL_PADFRAME_PERIPH_CONFIG_MUXED_V_11_MUX_SEL_OFFSET = 8'h 60; + parameter logic [BlockAw-1:0] ASTRAL_PADFRAME_PERIPH_CONFIG_MUXED_V_12_CFG_OFFSET = 8'h 64; + parameter logic [BlockAw-1:0] ASTRAL_PADFRAME_PERIPH_CONFIG_MUXED_V_12_MUX_SEL_OFFSET = 8'h 68; + parameter logic [BlockAw-1:0] ASTRAL_PADFRAME_PERIPH_CONFIG_MUXED_V_13_CFG_OFFSET = 8'h 6c; + parameter logic [BlockAw-1:0] ASTRAL_PADFRAME_PERIPH_CONFIG_MUXED_V_13_MUX_SEL_OFFSET = 8'h 70; + parameter logic [BlockAw-1:0] ASTRAL_PADFRAME_PERIPH_CONFIG_MUXED_V_14_CFG_OFFSET = 8'h 74; + parameter logic [BlockAw-1:0] ASTRAL_PADFRAME_PERIPH_CONFIG_MUXED_V_14_MUX_SEL_OFFSET = 8'h 78; + parameter logic [BlockAw-1:0] ASTRAL_PADFRAME_PERIPH_CONFIG_MUXED_V_15_CFG_OFFSET = 8'h 7c; + parameter logic [BlockAw-1:0] ASTRAL_PADFRAME_PERIPH_CONFIG_MUXED_V_15_MUX_SEL_OFFSET = 8'h 80; + parameter logic [BlockAw-1:0] ASTRAL_PADFRAME_PERIPH_CONFIG_MUXED_V_16_CFG_OFFSET = 8'h 84; + parameter logic [BlockAw-1:0] ASTRAL_PADFRAME_PERIPH_CONFIG_MUXED_V_16_MUX_SEL_OFFSET = 8'h 88; + parameter logic [BlockAw-1:0] ASTRAL_PADFRAME_PERIPH_CONFIG_MUXED_V_17_CFG_OFFSET = 8'h 8c; + parameter logic [BlockAw-1:0] ASTRAL_PADFRAME_PERIPH_CONFIG_MUXED_V_17_MUX_SEL_OFFSET = 8'h 90; + parameter logic [BlockAw-1:0] ASTRAL_PADFRAME_PERIPH_CONFIG_MUXED_H_00_CFG_OFFSET = 8'h 94; + parameter logic [BlockAw-1:0] ASTRAL_PADFRAME_PERIPH_CONFIG_MUXED_H_00_MUX_SEL_OFFSET = 8'h 98; + parameter logic [BlockAw-1:0] ASTRAL_PADFRAME_PERIPH_CONFIG_MUXED_H_01_CFG_OFFSET = 8'h 9c; + parameter logic [BlockAw-1:0] ASTRAL_PADFRAME_PERIPH_CONFIG_MUXED_H_01_MUX_SEL_OFFSET = 8'h a0; + parameter logic [BlockAw-1:0] ASTRAL_PADFRAME_PERIPH_CONFIG_MUXED_H_02_CFG_OFFSET = 8'h a4; + parameter logic [BlockAw-1:0] ASTRAL_PADFRAME_PERIPH_CONFIG_MUXED_H_02_MUX_SEL_OFFSET = 8'h a8; + parameter logic [BlockAw-1:0] ASTRAL_PADFRAME_PERIPH_CONFIG_MUXED_H_03_CFG_OFFSET = 8'h ac; + parameter logic [BlockAw-1:0] ASTRAL_PADFRAME_PERIPH_CONFIG_MUXED_H_03_MUX_SEL_OFFSET = 8'h b0; + + // Register index + typedef enum int { + ASTRAL_PADFRAME_PERIPH_CONFIG_INFO, + ASTRAL_PADFRAME_PERIPH_CONFIG_MUXED_V_00_CFG, + ASTRAL_PADFRAME_PERIPH_CONFIG_MUXED_V_00_MUX_SEL, + ASTRAL_PADFRAME_PERIPH_CONFIG_MUXED_V_01_CFG, + ASTRAL_PADFRAME_PERIPH_CONFIG_MUXED_V_01_MUX_SEL, + ASTRAL_PADFRAME_PERIPH_CONFIG_MUXED_V_02_CFG, + ASTRAL_PADFRAME_PERIPH_CONFIG_MUXED_V_02_MUX_SEL, + ASTRAL_PADFRAME_PERIPH_CONFIG_MUXED_V_03_CFG, + ASTRAL_PADFRAME_PERIPH_CONFIG_MUXED_V_03_MUX_SEL, + ASTRAL_PADFRAME_PERIPH_CONFIG_MUXED_V_04_CFG, + ASTRAL_PADFRAME_PERIPH_CONFIG_MUXED_V_04_MUX_SEL, + ASTRAL_PADFRAME_PERIPH_CONFIG_MUXED_V_05_CFG, + ASTRAL_PADFRAME_PERIPH_CONFIG_MUXED_V_05_MUX_SEL, + ASTRAL_PADFRAME_PERIPH_CONFIG_MUXED_V_06_CFG, + ASTRAL_PADFRAME_PERIPH_CONFIG_MUXED_V_06_MUX_SEL, + ASTRAL_PADFRAME_PERIPH_CONFIG_MUXED_V_07_CFG, + ASTRAL_PADFRAME_PERIPH_CONFIG_MUXED_V_07_MUX_SEL, + ASTRAL_PADFRAME_PERIPH_CONFIG_MUXED_V_08_CFG, + ASTRAL_PADFRAME_PERIPH_CONFIG_MUXED_V_08_MUX_SEL, + ASTRAL_PADFRAME_PERIPH_CONFIG_MUXED_V_09_CFG, + ASTRAL_PADFRAME_PERIPH_CONFIG_MUXED_V_09_MUX_SEL, + ASTRAL_PADFRAME_PERIPH_CONFIG_MUXED_V_10_CFG, + ASTRAL_PADFRAME_PERIPH_CONFIG_MUXED_V_10_MUX_SEL, + ASTRAL_PADFRAME_PERIPH_CONFIG_MUXED_V_11_CFG, + ASTRAL_PADFRAME_PERIPH_CONFIG_MUXED_V_11_MUX_SEL, + ASTRAL_PADFRAME_PERIPH_CONFIG_MUXED_V_12_CFG, + ASTRAL_PADFRAME_PERIPH_CONFIG_MUXED_V_12_MUX_SEL, + ASTRAL_PADFRAME_PERIPH_CONFIG_MUXED_V_13_CFG, + ASTRAL_PADFRAME_PERIPH_CONFIG_MUXED_V_13_MUX_SEL, + ASTRAL_PADFRAME_PERIPH_CONFIG_MUXED_V_14_CFG, + ASTRAL_PADFRAME_PERIPH_CONFIG_MUXED_V_14_MUX_SEL, + ASTRAL_PADFRAME_PERIPH_CONFIG_MUXED_V_15_CFG, + ASTRAL_PADFRAME_PERIPH_CONFIG_MUXED_V_15_MUX_SEL, + ASTRAL_PADFRAME_PERIPH_CONFIG_MUXED_V_16_CFG, + ASTRAL_PADFRAME_PERIPH_CONFIG_MUXED_V_16_MUX_SEL, + ASTRAL_PADFRAME_PERIPH_CONFIG_MUXED_V_17_CFG, + ASTRAL_PADFRAME_PERIPH_CONFIG_MUXED_V_17_MUX_SEL, + ASTRAL_PADFRAME_PERIPH_CONFIG_MUXED_H_00_CFG, + ASTRAL_PADFRAME_PERIPH_CONFIG_MUXED_H_00_MUX_SEL, + ASTRAL_PADFRAME_PERIPH_CONFIG_MUXED_H_01_CFG, + ASTRAL_PADFRAME_PERIPH_CONFIG_MUXED_H_01_MUX_SEL, + ASTRAL_PADFRAME_PERIPH_CONFIG_MUXED_H_02_CFG, + ASTRAL_PADFRAME_PERIPH_CONFIG_MUXED_H_02_MUX_SEL, + ASTRAL_PADFRAME_PERIPH_CONFIG_MUXED_H_03_CFG, + ASTRAL_PADFRAME_PERIPH_CONFIG_MUXED_H_03_MUX_SEL + } astral_padframe_periph_config_id_e; + + // Register width information to check illegal writes + parameter logic [3:0] ASTRAL_PADFRAME_PERIPH_CONFIG_PERMIT [45] = '{ + 4'b 1111, // index[ 0] ASTRAL_PADFRAME_PERIPH_CONFIG_INFO + 4'b 0001, // index[ 1] ASTRAL_PADFRAME_PERIPH_CONFIG_MUXED_V_00_CFG + 4'b 0001, // index[ 2] ASTRAL_PADFRAME_PERIPH_CONFIG_MUXED_V_00_MUX_SEL + 4'b 0001, // index[ 3] ASTRAL_PADFRAME_PERIPH_CONFIG_MUXED_V_01_CFG + 4'b 0001, // index[ 4] ASTRAL_PADFRAME_PERIPH_CONFIG_MUXED_V_01_MUX_SEL + 4'b 0001, // index[ 5] ASTRAL_PADFRAME_PERIPH_CONFIG_MUXED_V_02_CFG + 4'b 0001, // index[ 6] ASTRAL_PADFRAME_PERIPH_CONFIG_MUXED_V_02_MUX_SEL + 4'b 0001, // index[ 7] ASTRAL_PADFRAME_PERIPH_CONFIG_MUXED_V_03_CFG + 4'b 0001, // index[ 8] ASTRAL_PADFRAME_PERIPH_CONFIG_MUXED_V_03_MUX_SEL + 4'b 0001, // index[ 9] ASTRAL_PADFRAME_PERIPH_CONFIG_MUXED_V_04_CFG + 4'b 0001, // index[10] ASTRAL_PADFRAME_PERIPH_CONFIG_MUXED_V_04_MUX_SEL + 4'b 0001, // index[11] ASTRAL_PADFRAME_PERIPH_CONFIG_MUXED_V_05_CFG + 4'b 0001, // index[12] ASTRAL_PADFRAME_PERIPH_CONFIG_MUXED_V_05_MUX_SEL + 4'b 0001, // index[13] ASTRAL_PADFRAME_PERIPH_CONFIG_MUXED_V_06_CFG + 4'b 0001, // index[14] ASTRAL_PADFRAME_PERIPH_CONFIG_MUXED_V_06_MUX_SEL + 4'b 0001, // index[15] ASTRAL_PADFRAME_PERIPH_CONFIG_MUXED_V_07_CFG + 4'b 0001, // index[16] ASTRAL_PADFRAME_PERIPH_CONFIG_MUXED_V_07_MUX_SEL + 4'b 0001, // index[17] ASTRAL_PADFRAME_PERIPH_CONFIG_MUXED_V_08_CFG + 4'b 0001, // index[18] ASTRAL_PADFRAME_PERIPH_CONFIG_MUXED_V_08_MUX_SEL + 4'b 0001, // index[19] ASTRAL_PADFRAME_PERIPH_CONFIG_MUXED_V_09_CFG + 4'b 0001, // index[20] ASTRAL_PADFRAME_PERIPH_CONFIG_MUXED_V_09_MUX_SEL + 4'b 0001, // index[21] ASTRAL_PADFRAME_PERIPH_CONFIG_MUXED_V_10_CFG + 4'b 0001, // index[22] ASTRAL_PADFRAME_PERIPH_CONFIG_MUXED_V_10_MUX_SEL + 4'b 0001, // index[23] ASTRAL_PADFRAME_PERIPH_CONFIG_MUXED_V_11_CFG + 4'b 0001, // index[24] ASTRAL_PADFRAME_PERIPH_CONFIG_MUXED_V_11_MUX_SEL + 4'b 0001, // index[25] ASTRAL_PADFRAME_PERIPH_CONFIG_MUXED_V_12_CFG + 4'b 0001, // index[26] ASTRAL_PADFRAME_PERIPH_CONFIG_MUXED_V_12_MUX_SEL + 4'b 0001, // index[27] ASTRAL_PADFRAME_PERIPH_CONFIG_MUXED_V_13_CFG + 4'b 0001, // index[28] ASTRAL_PADFRAME_PERIPH_CONFIG_MUXED_V_13_MUX_SEL + 4'b 0001, // index[29] ASTRAL_PADFRAME_PERIPH_CONFIG_MUXED_V_14_CFG + 4'b 0001, // index[30] ASTRAL_PADFRAME_PERIPH_CONFIG_MUXED_V_14_MUX_SEL + 4'b 0001, // index[31] ASTRAL_PADFRAME_PERIPH_CONFIG_MUXED_V_15_CFG + 4'b 0001, // index[32] ASTRAL_PADFRAME_PERIPH_CONFIG_MUXED_V_15_MUX_SEL + 4'b 0001, // index[33] ASTRAL_PADFRAME_PERIPH_CONFIG_MUXED_V_16_CFG + 4'b 0001, // index[34] ASTRAL_PADFRAME_PERIPH_CONFIG_MUXED_V_16_MUX_SEL + 4'b 0001, // index[35] ASTRAL_PADFRAME_PERIPH_CONFIG_MUXED_V_17_CFG + 4'b 0001, // index[36] ASTRAL_PADFRAME_PERIPH_CONFIG_MUXED_V_17_MUX_SEL + 4'b 0001, // index[37] ASTRAL_PADFRAME_PERIPH_CONFIG_MUXED_H_00_CFG + 4'b 0001, // index[38] ASTRAL_PADFRAME_PERIPH_CONFIG_MUXED_H_00_MUX_SEL + 4'b 0001, // index[39] ASTRAL_PADFRAME_PERIPH_CONFIG_MUXED_H_01_CFG + 4'b 0001, // index[40] ASTRAL_PADFRAME_PERIPH_CONFIG_MUXED_H_01_MUX_SEL + 4'b 0001, // index[41] ASTRAL_PADFRAME_PERIPH_CONFIG_MUXED_H_02_CFG + 4'b 0001, // index[42] ASTRAL_PADFRAME_PERIPH_CONFIG_MUXED_H_02_MUX_SEL + 4'b 0001, // index[43] ASTRAL_PADFRAME_PERIPH_CONFIG_MUXED_H_03_CFG + 4'b 0001 // index[44] ASTRAL_PADFRAME_PERIPH_CONFIG_MUXED_H_03_MUX_SEL + }; + +endpackage + diff --git a/hw/padframe/astral_padframe/src/astral_padframe_periph_config_reg_top.sv b/hw/padframe/astral_padframe/src/astral_padframe_periph_config_reg_top.sv new file mode 100644 index 00000000..13c48cc7 --- /dev/null +++ b/hw/padframe/astral_padframe/src/astral_padframe_periph_config_reg_top.sv @@ -0,0 +1,4811 @@ +// Copyright lowRISC contributors. +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +// +// Register Top module auto-generated by `reggen` + + +`include "common_cells/assertions.svh" + +module astral_padframe_periph_config_reg_top #( + parameter type reg_req_t = logic, + parameter type reg_rsp_t = logic, + parameter int AW = 8 +) ( + input clk_i, + input rst_ni, + input reg_req_t reg_req_i, + output reg_rsp_t reg_rsp_o, + // To HW + output astral_padframe_periph_config_reg_pkg::astral_padframe_periph_config_reg2hw_t reg2hw, // Write + + + // Config + input devmode_i // If 1, explicit error return for unmapped register access +); + + import astral_padframe_periph_config_reg_pkg::* ; + + localparam int DW = 32; + localparam int DBW = DW/8; // Byte Width + + // register signals + logic reg_we; + logic reg_re; + logic [AW-1:0] reg_addr; + logic [DW-1:0] reg_wdata; + logic [DBW-1:0] reg_be; + logic [DW-1:0] reg_rdata; + logic reg_error; + + logic addrmiss, wr_err; + + logic [DW-1:0] reg_rdata_next; + + // Below register interface can be changed + reg_req_t reg_intf_req; + reg_rsp_t reg_intf_rsp; + + + assign reg_intf_req = reg_req_i; + assign reg_rsp_o = reg_intf_rsp; + + + assign reg_we = reg_intf_req.valid & reg_intf_req.write; + assign reg_re = reg_intf_req.valid & ~reg_intf_req.write; + assign reg_addr = reg_intf_req.addr; + assign reg_wdata = reg_intf_req.wdata; + assign reg_be = reg_intf_req.wstrb; + assign reg_intf_rsp.rdata = reg_rdata; + assign reg_intf_rsp.error = reg_error; + assign reg_intf_rsp.ready = 1'b1; + + assign reg_rdata = reg_rdata_next ; + assign reg_error = (devmode_i & addrmiss) | wr_err; + + + // Define SW related signals + // Format: __{wd|we|qs} + // or _{wd|we|qs} if field == 1 or 0 + logic [15:0] info_hw_version_qs; + logic [15:0] info_padcount_qs; + logic muxed_v_00_cfg_chip2pad_qs; + logic muxed_v_00_cfg_chip2pad_wd; + logic muxed_v_00_cfg_chip2pad_we; + logic muxed_v_00_cfg_input_en_qs; + logic muxed_v_00_cfg_input_en_wd; + logic muxed_v_00_cfg_input_en_we; + logic muxed_v_00_cfg_output_en_qs; + logic muxed_v_00_cfg_output_en_wd; + logic muxed_v_00_cfg_output_en_we; + logic muxed_v_00_cfg_pull_en_qs; + logic muxed_v_00_cfg_pull_en_wd; + logic muxed_v_00_cfg_pull_en_we; + logic muxed_v_00_cfg_pull_sel_qs; + logic muxed_v_00_cfg_pull_sel_wd; + logic muxed_v_00_cfg_pull_sel_we; + logic [2:0] muxed_v_00_mux_sel_qs; + logic [2:0] muxed_v_00_mux_sel_wd; + logic muxed_v_00_mux_sel_we; + logic muxed_v_01_cfg_chip2pad_qs; + logic muxed_v_01_cfg_chip2pad_wd; + logic muxed_v_01_cfg_chip2pad_we; + logic muxed_v_01_cfg_input_en_qs; + logic muxed_v_01_cfg_input_en_wd; + logic muxed_v_01_cfg_input_en_we; + logic muxed_v_01_cfg_output_en_qs; + logic muxed_v_01_cfg_output_en_wd; + logic muxed_v_01_cfg_output_en_we; + logic muxed_v_01_cfg_pull_en_qs; + logic muxed_v_01_cfg_pull_en_wd; + logic muxed_v_01_cfg_pull_en_we; + logic muxed_v_01_cfg_pull_sel_qs; + logic muxed_v_01_cfg_pull_sel_wd; + logic muxed_v_01_cfg_pull_sel_we; + logic [2:0] muxed_v_01_mux_sel_qs; + logic [2:0] muxed_v_01_mux_sel_wd; + logic muxed_v_01_mux_sel_we; + logic muxed_v_02_cfg_chip2pad_qs; + logic muxed_v_02_cfg_chip2pad_wd; + logic muxed_v_02_cfg_chip2pad_we; + logic muxed_v_02_cfg_input_en_qs; + logic muxed_v_02_cfg_input_en_wd; + logic muxed_v_02_cfg_input_en_we; + logic muxed_v_02_cfg_output_en_qs; + logic muxed_v_02_cfg_output_en_wd; + logic muxed_v_02_cfg_output_en_we; + logic muxed_v_02_cfg_pull_en_qs; + logic muxed_v_02_cfg_pull_en_wd; + logic muxed_v_02_cfg_pull_en_we; + logic muxed_v_02_cfg_pull_sel_qs; + logic muxed_v_02_cfg_pull_sel_wd; + logic muxed_v_02_cfg_pull_sel_we; + logic [1:0] muxed_v_02_mux_sel_qs; + logic [1:0] muxed_v_02_mux_sel_wd; + logic muxed_v_02_mux_sel_we; + logic muxed_v_03_cfg_chip2pad_qs; + logic muxed_v_03_cfg_chip2pad_wd; + logic muxed_v_03_cfg_chip2pad_we; + logic muxed_v_03_cfg_input_en_qs; + logic muxed_v_03_cfg_input_en_wd; + logic muxed_v_03_cfg_input_en_we; + logic muxed_v_03_cfg_output_en_qs; + logic muxed_v_03_cfg_output_en_wd; + logic muxed_v_03_cfg_output_en_we; + logic muxed_v_03_cfg_pull_en_qs; + logic muxed_v_03_cfg_pull_en_wd; + logic muxed_v_03_cfg_pull_en_we; + logic muxed_v_03_cfg_pull_sel_qs; + logic muxed_v_03_cfg_pull_sel_wd; + logic muxed_v_03_cfg_pull_sel_we; + logic [1:0] muxed_v_03_mux_sel_qs; + logic [1:0] muxed_v_03_mux_sel_wd; + logic muxed_v_03_mux_sel_we; + logic muxed_v_04_cfg_chip2pad_qs; + logic muxed_v_04_cfg_chip2pad_wd; + logic muxed_v_04_cfg_chip2pad_we; + logic muxed_v_04_cfg_input_en_qs; + logic muxed_v_04_cfg_input_en_wd; + logic muxed_v_04_cfg_input_en_we; + logic muxed_v_04_cfg_output_en_qs; + logic muxed_v_04_cfg_output_en_wd; + logic muxed_v_04_cfg_output_en_we; + logic muxed_v_04_cfg_pull_en_qs; + logic muxed_v_04_cfg_pull_en_wd; + logic muxed_v_04_cfg_pull_en_we; + logic muxed_v_04_cfg_pull_sel_qs; + logic muxed_v_04_cfg_pull_sel_wd; + logic muxed_v_04_cfg_pull_sel_we; + logic [2:0] muxed_v_04_mux_sel_qs; + logic [2:0] muxed_v_04_mux_sel_wd; + logic muxed_v_04_mux_sel_we; + logic muxed_v_05_cfg_chip2pad_qs; + logic muxed_v_05_cfg_chip2pad_wd; + logic muxed_v_05_cfg_chip2pad_we; + logic muxed_v_05_cfg_input_en_qs; + logic muxed_v_05_cfg_input_en_wd; + logic muxed_v_05_cfg_input_en_we; + logic muxed_v_05_cfg_output_en_qs; + logic muxed_v_05_cfg_output_en_wd; + logic muxed_v_05_cfg_output_en_we; + logic muxed_v_05_cfg_pull_en_qs; + logic muxed_v_05_cfg_pull_en_wd; + logic muxed_v_05_cfg_pull_en_we; + logic muxed_v_05_cfg_pull_sel_qs; + logic muxed_v_05_cfg_pull_sel_wd; + logic muxed_v_05_cfg_pull_sel_we; + logic [2:0] muxed_v_05_mux_sel_qs; + logic [2:0] muxed_v_05_mux_sel_wd; + logic muxed_v_05_mux_sel_we; + logic muxed_v_06_cfg_chip2pad_qs; + logic muxed_v_06_cfg_chip2pad_wd; + logic muxed_v_06_cfg_chip2pad_we; + logic muxed_v_06_cfg_input_en_qs; + logic muxed_v_06_cfg_input_en_wd; + logic muxed_v_06_cfg_input_en_we; + logic muxed_v_06_cfg_output_en_qs; + logic muxed_v_06_cfg_output_en_wd; + logic muxed_v_06_cfg_output_en_we; + logic muxed_v_06_cfg_pull_en_qs; + logic muxed_v_06_cfg_pull_en_wd; + logic muxed_v_06_cfg_pull_en_we; + logic muxed_v_06_cfg_pull_sel_qs; + logic muxed_v_06_cfg_pull_sel_wd; + logic muxed_v_06_cfg_pull_sel_we; + logic [1:0] muxed_v_06_mux_sel_qs; + logic [1:0] muxed_v_06_mux_sel_wd; + logic muxed_v_06_mux_sel_we; + logic muxed_v_07_cfg_chip2pad_qs; + logic muxed_v_07_cfg_chip2pad_wd; + logic muxed_v_07_cfg_chip2pad_we; + logic muxed_v_07_cfg_input_en_qs; + logic muxed_v_07_cfg_input_en_wd; + logic muxed_v_07_cfg_input_en_we; + logic muxed_v_07_cfg_output_en_qs; + logic muxed_v_07_cfg_output_en_wd; + logic muxed_v_07_cfg_output_en_we; + logic muxed_v_07_cfg_pull_en_qs; + logic muxed_v_07_cfg_pull_en_wd; + logic muxed_v_07_cfg_pull_en_we; + logic muxed_v_07_cfg_pull_sel_qs; + logic muxed_v_07_cfg_pull_sel_wd; + logic muxed_v_07_cfg_pull_sel_we; + logic [2:0] muxed_v_07_mux_sel_qs; + logic [2:0] muxed_v_07_mux_sel_wd; + logic muxed_v_07_mux_sel_we; + logic muxed_v_08_cfg_chip2pad_qs; + logic muxed_v_08_cfg_chip2pad_wd; + logic muxed_v_08_cfg_chip2pad_we; + logic muxed_v_08_cfg_input_en_qs; + logic muxed_v_08_cfg_input_en_wd; + logic muxed_v_08_cfg_input_en_we; + logic muxed_v_08_cfg_output_en_qs; + logic muxed_v_08_cfg_output_en_wd; + logic muxed_v_08_cfg_output_en_we; + logic muxed_v_08_cfg_pull_en_qs; + logic muxed_v_08_cfg_pull_en_wd; + logic muxed_v_08_cfg_pull_en_we; + logic muxed_v_08_cfg_pull_sel_qs; + logic muxed_v_08_cfg_pull_sel_wd; + logic muxed_v_08_cfg_pull_sel_we; + logic [2:0] muxed_v_08_mux_sel_qs; + logic [2:0] muxed_v_08_mux_sel_wd; + logic muxed_v_08_mux_sel_we; + logic muxed_v_09_cfg_chip2pad_qs; + logic muxed_v_09_cfg_chip2pad_wd; + logic muxed_v_09_cfg_chip2pad_we; + logic muxed_v_09_cfg_input_en_qs; + logic muxed_v_09_cfg_input_en_wd; + logic muxed_v_09_cfg_input_en_we; + logic muxed_v_09_cfg_output_en_qs; + logic muxed_v_09_cfg_output_en_wd; + logic muxed_v_09_cfg_output_en_we; + logic muxed_v_09_cfg_pull_en_qs; + logic muxed_v_09_cfg_pull_en_wd; + logic muxed_v_09_cfg_pull_en_we; + logic muxed_v_09_cfg_pull_sel_qs; + logic muxed_v_09_cfg_pull_sel_wd; + logic muxed_v_09_cfg_pull_sel_we; + logic [2:0] muxed_v_09_mux_sel_qs; + logic [2:0] muxed_v_09_mux_sel_wd; + logic muxed_v_09_mux_sel_we; + logic muxed_v_10_cfg_chip2pad_qs; + logic muxed_v_10_cfg_chip2pad_wd; + logic muxed_v_10_cfg_chip2pad_we; + logic muxed_v_10_cfg_input_en_qs; + logic muxed_v_10_cfg_input_en_wd; + logic muxed_v_10_cfg_input_en_we; + logic muxed_v_10_cfg_output_en_qs; + logic muxed_v_10_cfg_output_en_wd; + logic muxed_v_10_cfg_output_en_we; + logic muxed_v_10_cfg_pull_en_qs; + logic muxed_v_10_cfg_pull_en_wd; + logic muxed_v_10_cfg_pull_en_we; + logic muxed_v_10_cfg_pull_sel_qs; + logic muxed_v_10_cfg_pull_sel_wd; + logic muxed_v_10_cfg_pull_sel_we; + logic [2:0] muxed_v_10_mux_sel_qs; + logic [2:0] muxed_v_10_mux_sel_wd; + logic muxed_v_10_mux_sel_we; + logic muxed_v_11_cfg_chip2pad_qs; + logic muxed_v_11_cfg_chip2pad_wd; + logic muxed_v_11_cfg_chip2pad_we; + logic muxed_v_11_cfg_input_en_qs; + logic muxed_v_11_cfg_input_en_wd; + logic muxed_v_11_cfg_input_en_we; + logic muxed_v_11_cfg_output_en_qs; + logic muxed_v_11_cfg_output_en_wd; + logic muxed_v_11_cfg_output_en_we; + logic muxed_v_11_cfg_pull_en_qs; + logic muxed_v_11_cfg_pull_en_wd; + logic muxed_v_11_cfg_pull_en_we; + logic muxed_v_11_cfg_pull_sel_qs; + logic muxed_v_11_cfg_pull_sel_wd; + logic muxed_v_11_cfg_pull_sel_we; + logic [2:0] muxed_v_11_mux_sel_qs; + logic [2:0] muxed_v_11_mux_sel_wd; + logic muxed_v_11_mux_sel_we; + logic muxed_v_12_cfg_chip2pad_qs; + logic muxed_v_12_cfg_chip2pad_wd; + logic muxed_v_12_cfg_chip2pad_we; + logic muxed_v_12_cfg_input_en_qs; + logic muxed_v_12_cfg_input_en_wd; + logic muxed_v_12_cfg_input_en_we; + logic muxed_v_12_cfg_output_en_qs; + logic muxed_v_12_cfg_output_en_wd; + logic muxed_v_12_cfg_output_en_we; + logic muxed_v_12_cfg_pull_en_qs; + logic muxed_v_12_cfg_pull_en_wd; + logic muxed_v_12_cfg_pull_en_we; + logic muxed_v_12_cfg_pull_sel_qs; + logic muxed_v_12_cfg_pull_sel_wd; + logic muxed_v_12_cfg_pull_sel_we; + logic [2:0] muxed_v_12_mux_sel_qs; + logic [2:0] muxed_v_12_mux_sel_wd; + logic muxed_v_12_mux_sel_we; + logic muxed_v_13_cfg_chip2pad_qs; + logic muxed_v_13_cfg_chip2pad_wd; + logic muxed_v_13_cfg_chip2pad_we; + logic muxed_v_13_cfg_input_en_qs; + logic muxed_v_13_cfg_input_en_wd; + logic muxed_v_13_cfg_input_en_we; + logic muxed_v_13_cfg_output_en_qs; + logic muxed_v_13_cfg_output_en_wd; + logic muxed_v_13_cfg_output_en_we; + logic muxed_v_13_cfg_pull_en_qs; + logic muxed_v_13_cfg_pull_en_wd; + logic muxed_v_13_cfg_pull_en_we; + logic muxed_v_13_cfg_pull_sel_qs; + logic muxed_v_13_cfg_pull_sel_wd; + logic muxed_v_13_cfg_pull_sel_we; + logic [2:0] muxed_v_13_mux_sel_qs; + logic [2:0] muxed_v_13_mux_sel_wd; + logic muxed_v_13_mux_sel_we; + logic muxed_v_14_cfg_chip2pad_qs; + logic muxed_v_14_cfg_chip2pad_wd; + logic muxed_v_14_cfg_chip2pad_we; + logic muxed_v_14_cfg_input_en_qs; + logic muxed_v_14_cfg_input_en_wd; + logic muxed_v_14_cfg_input_en_we; + logic muxed_v_14_cfg_output_en_qs; + logic muxed_v_14_cfg_output_en_wd; + logic muxed_v_14_cfg_output_en_we; + logic muxed_v_14_cfg_pull_en_qs; + logic muxed_v_14_cfg_pull_en_wd; + logic muxed_v_14_cfg_pull_en_we; + logic muxed_v_14_cfg_pull_sel_qs; + logic muxed_v_14_cfg_pull_sel_wd; + logic muxed_v_14_cfg_pull_sel_we; + logic [2:0] muxed_v_14_mux_sel_qs; + logic [2:0] muxed_v_14_mux_sel_wd; + logic muxed_v_14_mux_sel_we; + logic muxed_v_15_cfg_chip2pad_qs; + logic muxed_v_15_cfg_chip2pad_wd; + logic muxed_v_15_cfg_chip2pad_we; + logic muxed_v_15_cfg_input_en_qs; + logic muxed_v_15_cfg_input_en_wd; + logic muxed_v_15_cfg_input_en_we; + logic muxed_v_15_cfg_output_en_qs; + logic muxed_v_15_cfg_output_en_wd; + logic muxed_v_15_cfg_output_en_we; + logic muxed_v_15_cfg_pull_en_qs; + logic muxed_v_15_cfg_pull_en_wd; + logic muxed_v_15_cfg_pull_en_we; + logic muxed_v_15_cfg_pull_sel_qs; + logic muxed_v_15_cfg_pull_sel_wd; + logic muxed_v_15_cfg_pull_sel_we; + logic [2:0] muxed_v_15_mux_sel_qs; + logic [2:0] muxed_v_15_mux_sel_wd; + logic muxed_v_15_mux_sel_we; + logic muxed_v_16_cfg_chip2pad_qs; + logic muxed_v_16_cfg_chip2pad_wd; + logic muxed_v_16_cfg_chip2pad_we; + logic muxed_v_16_cfg_input_en_qs; + logic muxed_v_16_cfg_input_en_wd; + logic muxed_v_16_cfg_input_en_we; + logic muxed_v_16_cfg_output_en_qs; + logic muxed_v_16_cfg_output_en_wd; + logic muxed_v_16_cfg_output_en_we; + logic muxed_v_16_cfg_pull_en_qs; + logic muxed_v_16_cfg_pull_en_wd; + logic muxed_v_16_cfg_pull_en_we; + logic muxed_v_16_cfg_pull_sel_qs; + logic muxed_v_16_cfg_pull_sel_wd; + logic muxed_v_16_cfg_pull_sel_we; + logic [2:0] muxed_v_16_mux_sel_qs; + logic [2:0] muxed_v_16_mux_sel_wd; + logic muxed_v_16_mux_sel_we; + logic muxed_v_17_cfg_chip2pad_qs; + logic muxed_v_17_cfg_chip2pad_wd; + logic muxed_v_17_cfg_chip2pad_we; + logic muxed_v_17_cfg_input_en_qs; + logic muxed_v_17_cfg_input_en_wd; + logic muxed_v_17_cfg_input_en_we; + logic muxed_v_17_cfg_output_en_qs; + logic muxed_v_17_cfg_output_en_wd; + logic muxed_v_17_cfg_output_en_we; + logic muxed_v_17_cfg_pull_en_qs; + logic muxed_v_17_cfg_pull_en_wd; + logic muxed_v_17_cfg_pull_en_we; + logic muxed_v_17_cfg_pull_sel_qs; + logic muxed_v_17_cfg_pull_sel_wd; + logic muxed_v_17_cfg_pull_sel_we; + logic [2:0] muxed_v_17_mux_sel_qs; + logic [2:0] muxed_v_17_mux_sel_wd; + logic muxed_v_17_mux_sel_we; + logic muxed_h_00_cfg_chip2pad_qs; + logic muxed_h_00_cfg_chip2pad_wd; + logic muxed_h_00_cfg_chip2pad_we; + logic muxed_h_00_cfg_input_en_qs; + logic muxed_h_00_cfg_input_en_wd; + logic muxed_h_00_cfg_input_en_we; + logic muxed_h_00_cfg_output_en_qs; + logic muxed_h_00_cfg_output_en_wd; + logic muxed_h_00_cfg_output_en_we; + logic muxed_h_00_cfg_pull_en_qs; + logic muxed_h_00_cfg_pull_en_wd; + logic muxed_h_00_cfg_pull_en_we; + logic muxed_h_00_cfg_pull_sel_qs; + logic muxed_h_00_cfg_pull_sel_wd; + logic muxed_h_00_cfg_pull_sel_we; + logic [2:0] muxed_h_00_mux_sel_qs; + logic [2:0] muxed_h_00_mux_sel_wd; + logic muxed_h_00_mux_sel_we; + logic muxed_h_01_cfg_chip2pad_qs; + logic muxed_h_01_cfg_chip2pad_wd; + logic muxed_h_01_cfg_chip2pad_we; + logic muxed_h_01_cfg_input_en_qs; + logic muxed_h_01_cfg_input_en_wd; + logic muxed_h_01_cfg_input_en_we; + logic muxed_h_01_cfg_output_en_qs; + logic muxed_h_01_cfg_output_en_wd; + logic muxed_h_01_cfg_output_en_we; + logic muxed_h_01_cfg_pull_en_qs; + logic muxed_h_01_cfg_pull_en_wd; + logic muxed_h_01_cfg_pull_en_we; + logic muxed_h_01_cfg_pull_sel_qs; + logic muxed_h_01_cfg_pull_sel_wd; + logic muxed_h_01_cfg_pull_sel_we; + logic [2:0] muxed_h_01_mux_sel_qs; + logic [2:0] muxed_h_01_mux_sel_wd; + logic muxed_h_01_mux_sel_we; + logic muxed_h_02_cfg_chip2pad_qs; + logic muxed_h_02_cfg_chip2pad_wd; + logic muxed_h_02_cfg_chip2pad_we; + logic muxed_h_02_cfg_input_en_qs; + logic muxed_h_02_cfg_input_en_wd; + logic muxed_h_02_cfg_input_en_we; + logic muxed_h_02_cfg_output_en_qs; + logic muxed_h_02_cfg_output_en_wd; + logic muxed_h_02_cfg_output_en_we; + logic muxed_h_02_cfg_pull_en_qs; + logic muxed_h_02_cfg_pull_en_wd; + logic muxed_h_02_cfg_pull_en_we; + logic muxed_h_02_cfg_pull_sel_qs; + logic muxed_h_02_cfg_pull_sel_wd; + logic muxed_h_02_cfg_pull_sel_we; + logic [2:0] muxed_h_02_mux_sel_qs; + logic [2:0] muxed_h_02_mux_sel_wd; + logic muxed_h_02_mux_sel_we; + logic muxed_h_03_cfg_chip2pad_qs; + logic muxed_h_03_cfg_chip2pad_wd; + logic muxed_h_03_cfg_chip2pad_we; + logic muxed_h_03_cfg_input_en_qs; + logic muxed_h_03_cfg_input_en_wd; + logic muxed_h_03_cfg_input_en_we; + logic muxed_h_03_cfg_output_en_qs; + logic muxed_h_03_cfg_output_en_wd; + logic muxed_h_03_cfg_output_en_we; + logic muxed_h_03_cfg_pull_en_qs; + logic muxed_h_03_cfg_pull_en_wd; + logic muxed_h_03_cfg_pull_en_we; + logic muxed_h_03_cfg_pull_sel_qs; + logic muxed_h_03_cfg_pull_sel_wd; + logic muxed_h_03_cfg_pull_sel_we; + logic [2:0] muxed_h_03_mux_sel_qs; + logic [2:0] muxed_h_03_mux_sel_wd; + logic muxed_h_03_mux_sel_we; + + // Register instances + // R[info]: V(False) + + // F[hw_version]: 15:0 + prim_subreg #( + .DW (16), + .SWACCESS("RO"), + .RESVAL (16'h2) + ) u_info_hw_version ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + .we (1'b0), + .wd ('0 ), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.info.hw_version.q ), + + // to register interface (read) + .qs (info_hw_version_qs) + ); + + + // F[padcount]: 31:16 + prim_subreg #( + .DW (16), + .SWACCESS("RO"), + .RESVAL (16'h16) + ) u_info_padcount ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + .we (1'b0), + .wd ('0 ), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.info.padcount.q ), + + // to register interface (read) + .qs (info_padcount_qs) + ); + + + // R[muxed_v_00_cfg]: V(False) + + // F[chip2pad]: 0:0 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_muxed_v_00_cfg_chip2pad ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (muxed_v_00_cfg_chip2pad_we), + .wd (muxed_v_00_cfg_chip2pad_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.muxed_v_00_cfg.chip2pad.q ), + + // to register interface (read) + .qs (muxed_v_00_cfg_chip2pad_qs) + ); + + + // F[input_en]: 1:1 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_muxed_v_00_cfg_input_en ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (muxed_v_00_cfg_input_en_we), + .wd (muxed_v_00_cfg_input_en_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.muxed_v_00_cfg.input_en.q ), + + // to register interface (read) + .qs (muxed_v_00_cfg_input_en_qs) + ); + + + // F[output_en]: 2:2 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_muxed_v_00_cfg_output_en ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (muxed_v_00_cfg_output_en_we), + .wd (muxed_v_00_cfg_output_en_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.muxed_v_00_cfg.output_en.q ), + + // to register interface (read) + .qs (muxed_v_00_cfg_output_en_qs) + ); + + + // F[pull_en]: 3:3 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_muxed_v_00_cfg_pull_en ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (muxed_v_00_cfg_pull_en_we), + .wd (muxed_v_00_cfg_pull_en_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.muxed_v_00_cfg.pull_en.q ), + + // to register interface (read) + .qs (muxed_v_00_cfg_pull_en_qs) + ); + + + // F[pull_sel]: 4:4 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_muxed_v_00_cfg_pull_sel ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (muxed_v_00_cfg_pull_sel_we), + .wd (muxed_v_00_cfg_pull_sel_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.muxed_v_00_cfg.pull_sel.q ), + + // to register interface (read) + .qs (muxed_v_00_cfg_pull_sel_qs) + ); + + + // R[muxed_v_00_mux_sel]: V(False) + + prim_subreg #( + .DW (3), + .SWACCESS("RW"), + .RESVAL (3'h1) + ) u_muxed_v_00_mux_sel ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (muxed_v_00_mux_sel_we), + .wd (muxed_v_00_mux_sel_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.muxed_v_00_mux_sel.q ), + + // to register interface (read) + .qs (muxed_v_00_mux_sel_qs) + ); + + + // R[muxed_v_01_cfg]: V(False) + + // F[chip2pad]: 0:0 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_muxed_v_01_cfg_chip2pad ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (muxed_v_01_cfg_chip2pad_we), + .wd (muxed_v_01_cfg_chip2pad_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.muxed_v_01_cfg.chip2pad.q ), + + // to register interface (read) + .qs (muxed_v_01_cfg_chip2pad_qs) + ); + + + // F[input_en]: 1:1 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_muxed_v_01_cfg_input_en ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (muxed_v_01_cfg_input_en_we), + .wd (muxed_v_01_cfg_input_en_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.muxed_v_01_cfg.input_en.q ), + + // to register interface (read) + .qs (muxed_v_01_cfg_input_en_qs) + ); + + + // F[output_en]: 2:2 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_muxed_v_01_cfg_output_en ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (muxed_v_01_cfg_output_en_we), + .wd (muxed_v_01_cfg_output_en_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.muxed_v_01_cfg.output_en.q ), + + // to register interface (read) + .qs (muxed_v_01_cfg_output_en_qs) + ); + + + // F[pull_en]: 3:3 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_muxed_v_01_cfg_pull_en ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (muxed_v_01_cfg_pull_en_we), + .wd (muxed_v_01_cfg_pull_en_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.muxed_v_01_cfg.pull_en.q ), + + // to register interface (read) + .qs (muxed_v_01_cfg_pull_en_qs) + ); + + + // F[pull_sel]: 4:4 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_muxed_v_01_cfg_pull_sel ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (muxed_v_01_cfg_pull_sel_we), + .wd (muxed_v_01_cfg_pull_sel_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.muxed_v_01_cfg.pull_sel.q ), + + // to register interface (read) + .qs (muxed_v_01_cfg_pull_sel_qs) + ); + + + // R[muxed_v_01_mux_sel]: V(False) + + prim_subreg #( + .DW (3), + .SWACCESS("RW"), + .RESVAL (3'h1) + ) u_muxed_v_01_mux_sel ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (muxed_v_01_mux_sel_we), + .wd (muxed_v_01_mux_sel_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.muxed_v_01_mux_sel.q ), + + // to register interface (read) + .qs (muxed_v_01_mux_sel_qs) + ); + + + // R[muxed_v_02_cfg]: V(False) + + // F[chip2pad]: 0:0 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_muxed_v_02_cfg_chip2pad ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (muxed_v_02_cfg_chip2pad_we), + .wd (muxed_v_02_cfg_chip2pad_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.muxed_v_02_cfg.chip2pad.q ), + + // to register interface (read) + .qs (muxed_v_02_cfg_chip2pad_qs) + ); + + + // F[input_en]: 1:1 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_muxed_v_02_cfg_input_en ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (muxed_v_02_cfg_input_en_we), + .wd (muxed_v_02_cfg_input_en_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.muxed_v_02_cfg.input_en.q ), + + // to register interface (read) + .qs (muxed_v_02_cfg_input_en_qs) + ); + + + // F[output_en]: 2:2 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_muxed_v_02_cfg_output_en ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (muxed_v_02_cfg_output_en_we), + .wd (muxed_v_02_cfg_output_en_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.muxed_v_02_cfg.output_en.q ), + + // to register interface (read) + .qs (muxed_v_02_cfg_output_en_qs) + ); + + + // F[pull_en]: 3:3 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_muxed_v_02_cfg_pull_en ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (muxed_v_02_cfg_pull_en_we), + .wd (muxed_v_02_cfg_pull_en_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.muxed_v_02_cfg.pull_en.q ), + + // to register interface (read) + .qs (muxed_v_02_cfg_pull_en_qs) + ); + + + // F[pull_sel]: 4:4 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_muxed_v_02_cfg_pull_sel ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (muxed_v_02_cfg_pull_sel_we), + .wd (muxed_v_02_cfg_pull_sel_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.muxed_v_02_cfg.pull_sel.q ), + + // to register interface (read) + .qs (muxed_v_02_cfg_pull_sel_qs) + ); + + + // R[muxed_v_02_mux_sel]: V(False) + + prim_subreg #( + .DW (2), + .SWACCESS("RW"), + .RESVAL (2'h1) + ) u_muxed_v_02_mux_sel ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (muxed_v_02_mux_sel_we), + .wd (muxed_v_02_mux_sel_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.muxed_v_02_mux_sel.q ), + + // to register interface (read) + .qs (muxed_v_02_mux_sel_qs) + ); + + + // R[muxed_v_03_cfg]: V(False) + + // F[chip2pad]: 0:0 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_muxed_v_03_cfg_chip2pad ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (muxed_v_03_cfg_chip2pad_we), + .wd (muxed_v_03_cfg_chip2pad_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.muxed_v_03_cfg.chip2pad.q ), + + // to register interface (read) + .qs (muxed_v_03_cfg_chip2pad_qs) + ); + + + // F[input_en]: 1:1 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_muxed_v_03_cfg_input_en ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (muxed_v_03_cfg_input_en_we), + .wd (muxed_v_03_cfg_input_en_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.muxed_v_03_cfg.input_en.q ), + + // to register interface (read) + .qs (muxed_v_03_cfg_input_en_qs) + ); + + + // F[output_en]: 2:2 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_muxed_v_03_cfg_output_en ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (muxed_v_03_cfg_output_en_we), + .wd (muxed_v_03_cfg_output_en_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.muxed_v_03_cfg.output_en.q ), + + // to register interface (read) + .qs (muxed_v_03_cfg_output_en_qs) + ); + + + // F[pull_en]: 3:3 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_muxed_v_03_cfg_pull_en ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (muxed_v_03_cfg_pull_en_we), + .wd (muxed_v_03_cfg_pull_en_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.muxed_v_03_cfg.pull_en.q ), + + // to register interface (read) + .qs (muxed_v_03_cfg_pull_en_qs) + ); + + + // F[pull_sel]: 4:4 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_muxed_v_03_cfg_pull_sel ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (muxed_v_03_cfg_pull_sel_we), + .wd (muxed_v_03_cfg_pull_sel_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.muxed_v_03_cfg.pull_sel.q ), + + // to register interface (read) + .qs (muxed_v_03_cfg_pull_sel_qs) + ); + + + // R[muxed_v_03_mux_sel]: V(False) + + prim_subreg #( + .DW (2), + .SWACCESS("RW"), + .RESVAL (2'h1) + ) u_muxed_v_03_mux_sel ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (muxed_v_03_mux_sel_we), + .wd (muxed_v_03_mux_sel_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.muxed_v_03_mux_sel.q ), + + // to register interface (read) + .qs (muxed_v_03_mux_sel_qs) + ); + + + // R[muxed_v_04_cfg]: V(False) + + // F[chip2pad]: 0:0 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_muxed_v_04_cfg_chip2pad ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (muxed_v_04_cfg_chip2pad_we), + .wd (muxed_v_04_cfg_chip2pad_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.muxed_v_04_cfg.chip2pad.q ), + + // to register interface (read) + .qs (muxed_v_04_cfg_chip2pad_qs) + ); + + + // F[input_en]: 1:1 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_muxed_v_04_cfg_input_en ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (muxed_v_04_cfg_input_en_we), + .wd (muxed_v_04_cfg_input_en_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.muxed_v_04_cfg.input_en.q ), + + // to register interface (read) + .qs (muxed_v_04_cfg_input_en_qs) + ); + + + // F[output_en]: 2:2 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_muxed_v_04_cfg_output_en ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (muxed_v_04_cfg_output_en_we), + .wd (muxed_v_04_cfg_output_en_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.muxed_v_04_cfg.output_en.q ), + + // to register interface (read) + .qs (muxed_v_04_cfg_output_en_qs) + ); + + + // F[pull_en]: 3:3 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_muxed_v_04_cfg_pull_en ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (muxed_v_04_cfg_pull_en_we), + .wd (muxed_v_04_cfg_pull_en_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.muxed_v_04_cfg.pull_en.q ), + + // to register interface (read) + .qs (muxed_v_04_cfg_pull_en_qs) + ); + + + // F[pull_sel]: 4:4 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_muxed_v_04_cfg_pull_sel ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (muxed_v_04_cfg_pull_sel_we), + .wd (muxed_v_04_cfg_pull_sel_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.muxed_v_04_cfg.pull_sel.q ), + + // to register interface (read) + .qs (muxed_v_04_cfg_pull_sel_qs) + ); + + + // R[muxed_v_04_mux_sel]: V(False) + + prim_subreg #( + .DW (3), + .SWACCESS("RW"), + .RESVAL (3'h2) + ) u_muxed_v_04_mux_sel ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (muxed_v_04_mux_sel_we), + .wd (muxed_v_04_mux_sel_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.muxed_v_04_mux_sel.q ), + + // to register interface (read) + .qs (muxed_v_04_mux_sel_qs) + ); + + + // R[muxed_v_05_cfg]: V(False) + + // F[chip2pad]: 0:0 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_muxed_v_05_cfg_chip2pad ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (muxed_v_05_cfg_chip2pad_we), + .wd (muxed_v_05_cfg_chip2pad_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.muxed_v_05_cfg.chip2pad.q ), + + // to register interface (read) + .qs (muxed_v_05_cfg_chip2pad_qs) + ); + + + // F[input_en]: 1:1 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_muxed_v_05_cfg_input_en ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (muxed_v_05_cfg_input_en_we), + .wd (muxed_v_05_cfg_input_en_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.muxed_v_05_cfg.input_en.q ), + + // to register interface (read) + .qs (muxed_v_05_cfg_input_en_qs) + ); + + + // F[output_en]: 2:2 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_muxed_v_05_cfg_output_en ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (muxed_v_05_cfg_output_en_we), + .wd (muxed_v_05_cfg_output_en_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.muxed_v_05_cfg.output_en.q ), + + // to register interface (read) + .qs (muxed_v_05_cfg_output_en_qs) + ); + + + // F[pull_en]: 3:3 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_muxed_v_05_cfg_pull_en ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (muxed_v_05_cfg_pull_en_we), + .wd (muxed_v_05_cfg_pull_en_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.muxed_v_05_cfg.pull_en.q ), + + // to register interface (read) + .qs (muxed_v_05_cfg_pull_en_qs) + ); + + + // F[pull_sel]: 4:4 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_muxed_v_05_cfg_pull_sel ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (muxed_v_05_cfg_pull_sel_we), + .wd (muxed_v_05_cfg_pull_sel_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.muxed_v_05_cfg.pull_sel.q ), + + // to register interface (read) + .qs (muxed_v_05_cfg_pull_sel_qs) + ); + + + // R[muxed_v_05_mux_sel]: V(False) + + prim_subreg #( + .DW (3), + .SWACCESS("RW"), + .RESVAL (3'h2) + ) u_muxed_v_05_mux_sel ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (muxed_v_05_mux_sel_we), + .wd (muxed_v_05_mux_sel_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.muxed_v_05_mux_sel.q ), + + // to register interface (read) + .qs (muxed_v_05_mux_sel_qs) + ); + + + // R[muxed_v_06_cfg]: V(False) + + // F[chip2pad]: 0:0 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_muxed_v_06_cfg_chip2pad ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (muxed_v_06_cfg_chip2pad_we), + .wd (muxed_v_06_cfg_chip2pad_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.muxed_v_06_cfg.chip2pad.q ), + + // to register interface (read) + .qs (muxed_v_06_cfg_chip2pad_qs) + ); + + + // F[input_en]: 1:1 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_muxed_v_06_cfg_input_en ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (muxed_v_06_cfg_input_en_we), + .wd (muxed_v_06_cfg_input_en_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.muxed_v_06_cfg.input_en.q ), + + // to register interface (read) + .qs (muxed_v_06_cfg_input_en_qs) + ); + + + // F[output_en]: 2:2 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_muxed_v_06_cfg_output_en ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (muxed_v_06_cfg_output_en_we), + .wd (muxed_v_06_cfg_output_en_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.muxed_v_06_cfg.output_en.q ), + + // to register interface (read) + .qs (muxed_v_06_cfg_output_en_qs) + ); + + + // F[pull_en]: 3:3 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_muxed_v_06_cfg_pull_en ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (muxed_v_06_cfg_pull_en_we), + .wd (muxed_v_06_cfg_pull_en_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.muxed_v_06_cfg.pull_en.q ), + + // to register interface (read) + .qs (muxed_v_06_cfg_pull_en_qs) + ); + + + // F[pull_sel]: 4:4 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_muxed_v_06_cfg_pull_sel ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (muxed_v_06_cfg_pull_sel_we), + .wd (muxed_v_06_cfg_pull_sel_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.muxed_v_06_cfg.pull_sel.q ), + + // to register interface (read) + .qs (muxed_v_06_cfg_pull_sel_qs) + ); + + + // R[muxed_v_06_mux_sel]: V(False) + + prim_subreg #( + .DW (2), + .SWACCESS("RW"), + .RESVAL (2'h2) + ) u_muxed_v_06_mux_sel ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (muxed_v_06_mux_sel_we), + .wd (muxed_v_06_mux_sel_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.muxed_v_06_mux_sel.q ), + + // to register interface (read) + .qs (muxed_v_06_mux_sel_qs) + ); + + + // R[muxed_v_07_cfg]: V(False) + + // F[chip2pad]: 0:0 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_muxed_v_07_cfg_chip2pad ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (muxed_v_07_cfg_chip2pad_we), + .wd (muxed_v_07_cfg_chip2pad_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.muxed_v_07_cfg.chip2pad.q ), + + // to register interface (read) + .qs (muxed_v_07_cfg_chip2pad_qs) + ); + + + // F[input_en]: 1:1 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_muxed_v_07_cfg_input_en ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (muxed_v_07_cfg_input_en_we), + .wd (muxed_v_07_cfg_input_en_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.muxed_v_07_cfg.input_en.q ), + + // to register interface (read) + .qs (muxed_v_07_cfg_input_en_qs) + ); + + + // F[output_en]: 2:2 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_muxed_v_07_cfg_output_en ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (muxed_v_07_cfg_output_en_we), + .wd (muxed_v_07_cfg_output_en_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.muxed_v_07_cfg.output_en.q ), + + // to register interface (read) + .qs (muxed_v_07_cfg_output_en_qs) + ); + + + // F[pull_en]: 3:3 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_muxed_v_07_cfg_pull_en ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (muxed_v_07_cfg_pull_en_we), + .wd (muxed_v_07_cfg_pull_en_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.muxed_v_07_cfg.pull_en.q ), + + // to register interface (read) + .qs (muxed_v_07_cfg_pull_en_qs) + ); + + + // F[pull_sel]: 4:4 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_muxed_v_07_cfg_pull_sel ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (muxed_v_07_cfg_pull_sel_we), + .wd (muxed_v_07_cfg_pull_sel_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.muxed_v_07_cfg.pull_sel.q ), + + // to register interface (read) + .qs (muxed_v_07_cfg_pull_sel_qs) + ); + + + // R[muxed_v_07_mux_sel]: V(False) + + prim_subreg #( + .DW (3), + .SWACCESS("RW"), + .RESVAL (3'h4) + ) u_muxed_v_07_mux_sel ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (muxed_v_07_mux_sel_we), + .wd (muxed_v_07_mux_sel_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.muxed_v_07_mux_sel.q ), + + // to register interface (read) + .qs (muxed_v_07_mux_sel_qs) + ); + + + // R[muxed_v_08_cfg]: V(False) + + // F[chip2pad]: 0:0 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_muxed_v_08_cfg_chip2pad ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (muxed_v_08_cfg_chip2pad_we), + .wd (muxed_v_08_cfg_chip2pad_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.muxed_v_08_cfg.chip2pad.q ), + + // to register interface (read) + .qs (muxed_v_08_cfg_chip2pad_qs) + ); + + + // F[input_en]: 1:1 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_muxed_v_08_cfg_input_en ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (muxed_v_08_cfg_input_en_we), + .wd (muxed_v_08_cfg_input_en_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.muxed_v_08_cfg.input_en.q ), + + // to register interface (read) + .qs (muxed_v_08_cfg_input_en_qs) + ); + + + // F[output_en]: 2:2 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_muxed_v_08_cfg_output_en ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (muxed_v_08_cfg_output_en_we), + .wd (muxed_v_08_cfg_output_en_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.muxed_v_08_cfg.output_en.q ), + + // to register interface (read) + .qs (muxed_v_08_cfg_output_en_qs) + ); + + + // F[pull_en]: 3:3 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_muxed_v_08_cfg_pull_en ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (muxed_v_08_cfg_pull_en_we), + .wd (muxed_v_08_cfg_pull_en_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.muxed_v_08_cfg.pull_en.q ), + + // to register interface (read) + .qs (muxed_v_08_cfg_pull_en_qs) + ); + + + // F[pull_sel]: 4:4 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_muxed_v_08_cfg_pull_sel ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (muxed_v_08_cfg_pull_sel_we), + .wd (muxed_v_08_cfg_pull_sel_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.muxed_v_08_cfg.pull_sel.q ), + + // to register interface (read) + .qs (muxed_v_08_cfg_pull_sel_qs) + ); + + + // R[muxed_v_08_mux_sel]: V(False) + + prim_subreg #( + .DW (3), + .SWACCESS("RW"), + .RESVAL (3'h4) + ) u_muxed_v_08_mux_sel ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (muxed_v_08_mux_sel_we), + .wd (muxed_v_08_mux_sel_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.muxed_v_08_mux_sel.q ), + + // to register interface (read) + .qs (muxed_v_08_mux_sel_qs) + ); + + + // R[muxed_v_09_cfg]: V(False) + + // F[chip2pad]: 0:0 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_muxed_v_09_cfg_chip2pad ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (muxed_v_09_cfg_chip2pad_we), + .wd (muxed_v_09_cfg_chip2pad_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.muxed_v_09_cfg.chip2pad.q ), + + // to register interface (read) + .qs (muxed_v_09_cfg_chip2pad_qs) + ); + + + // F[input_en]: 1:1 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_muxed_v_09_cfg_input_en ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (muxed_v_09_cfg_input_en_we), + .wd (muxed_v_09_cfg_input_en_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.muxed_v_09_cfg.input_en.q ), + + // to register interface (read) + .qs (muxed_v_09_cfg_input_en_qs) + ); + + + // F[output_en]: 2:2 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_muxed_v_09_cfg_output_en ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (muxed_v_09_cfg_output_en_we), + .wd (muxed_v_09_cfg_output_en_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.muxed_v_09_cfg.output_en.q ), + + // to register interface (read) + .qs (muxed_v_09_cfg_output_en_qs) + ); + + + // F[pull_en]: 3:3 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_muxed_v_09_cfg_pull_en ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (muxed_v_09_cfg_pull_en_we), + .wd (muxed_v_09_cfg_pull_en_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.muxed_v_09_cfg.pull_en.q ), + + // to register interface (read) + .qs (muxed_v_09_cfg_pull_en_qs) + ); + + + // F[pull_sel]: 4:4 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_muxed_v_09_cfg_pull_sel ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (muxed_v_09_cfg_pull_sel_we), + .wd (muxed_v_09_cfg_pull_sel_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.muxed_v_09_cfg.pull_sel.q ), + + // to register interface (read) + .qs (muxed_v_09_cfg_pull_sel_qs) + ); + + + // R[muxed_v_09_mux_sel]: V(False) + + prim_subreg #( + .DW (3), + .SWACCESS("RW"), + .RESVAL (3'h4) + ) u_muxed_v_09_mux_sel ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (muxed_v_09_mux_sel_we), + .wd (muxed_v_09_mux_sel_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.muxed_v_09_mux_sel.q ), + + // to register interface (read) + .qs (muxed_v_09_mux_sel_qs) + ); + + + // R[muxed_v_10_cfg]: V(False) + + // F[chip2pad]: 0:0 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_muxed_v_10_cfg_chip2pad ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (muxed_v_10_cfg_chip2pad_we), + .wd (muxed_v_10_cfg_chip2pad_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.muxed_v_10_cfg.chip2pad.q ), + + // to register interface (read) + .qs (muxed_v_10_cfg_chip2pad_qs) + ); + + + // F[input_en]: 1:1 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_muxed_v_10_cfg_input_en ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (muxed_v_10_cfg_input_en_we), + .wd (muxed_v_10_cfg_input_en_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.muxed_v_10_cfg.input_en.q ), + + // to register interface (read) + .qs (muxed_v_10_cfg_input_en_qs) + ); + + + // F[output_en]: 2:2 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_muxed_v_10_cfg_output_en ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (muxed_v_10_cfg_output_en_we), + .wd (muxed_v_10_cfg_output_en_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.muxed_v_10_cfg.output_en.q ), + + // to register interface (read) + .qs (muxed_v_10_cfg_output_en_qs) + ); + + + // F[pull_en]: 3:3 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_muxed_v_10_cfg_pull_en ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (muxed_v_10_cfg_pull_en_we), + .wd (muxed_v_10_cfg_pull_en_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.muxed_v_10_cfg.pull_en.q ), + + // to register interface (read) + .qs (muxed_v_10_cfg_pull_en_qs) + ); + + + // F[pull_sel]: 4:4 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_muxed_v_10_cfg_pull_sel ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (muxed_v_10_cfg_pull_sel_we), + .wd (muxed_v_10_cfg_pull_sel_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.muxed_v_10_cfg.pull_sel.q ), + + // to register interface (read) + .qs (muxed_v_10_cfg_pull_sel_qs) + ); + + + // R[muxed_v_10_mux_sel]: V(False) + + prim_subreg #( + .DW (3), + .SWACCESS("RW"), + .RESVAL (3'h5) + ) u_muxed_v_10_mux_sel ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (muxed_v_10_mux_sel_we), + .wd (muxed_v_10_mux_sel_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.muxed_v_10_mux_sel.q ), + + // to register interface (read) + .qs (muxed_v_10_mux_sel_qs) + ); + + + // R[muxed_v_11_cfg]: V(False) + + // F[chip2pad]: 0:0 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_muxed_v_11_cfg_chip2pad ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (muxed_v_11_cfg_chip2pad_we), + .wd (muxed_v_11_cfg_chip2pad_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.muxed_v_11_cfg.chip2pad.q ), + + // to register interface (read) + .qs (muxed_v_11_cfg_chip2pad_qs) + ); + + + // F[input_en]: 1:1 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_muxed_v_11_cfg_input_en ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (muxed_v_11_cfg_input_en_we), + .wd (muxed_v_11_cfg_input_en_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.muxed_v_11_cfg.input_en.q ), + + // to register interface (read) + .qs (muxed_v_11_cfg_input_en_qs) + ); + + + // F[output_en]: 2:2 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_muxed_v_11_cfg_output_en ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (muxed_v_11_cfg_output_en_we), + .wd (muxed_v_11_cfg_output_en_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.muxed_v_11_cfg.output_en.q ), + + // to register interface (read) + .qs (muxed_v_11_cfg_output_en_qs) + ); + + + // F[pull_en]: 3:3 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_muxed_v_11_cfg_pull_en ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (muxed_v_11_cfg_pull_en_we), + .wd (muxed_v_11_cfg_pull_en_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.muxed_v_11_cfg.pull_en.q ), + + // to register interface (read) + .qs (muxed_v_11_cfg_pull_en_qs) + ); + + + // F[pull_sel]: 4:4 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_muxed_v_11_cfg_pull_sel ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (muxed_v_11_cfg_pull_sel_we), + .wd (muxed_v_11_cfg_pull_sel_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.muxed_v_11_cfg.pull_sel.q ), + + // to register interface (read) + .qs (muxed_v_11_cfg_pull_sel_qs) + ); + + + // R[muxed_v_11_mux_sel]: V(False) + + prim_subreg #( + .DW (3), + .SWACCESS("RW"), + .RESVAL (3'h5) + ) u_muxed_v_11_mux_sel ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (muxed_v_11_mux_sel_we), + .wd (muxed_v_11_mux_sel_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.muxed_v_11_mux_sel.q ), + + // to register interface (read) + .qs (muxed_v_11_mux_sel_qs) + ); + + + // R[muxed_v_12_cfg]: V(False) + + // F[chip2pad]: 0:0 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_muxed_v_12_cfg_chip2pad ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (muxed_v_12_cfg_chip2pad_we), + .wd (muxed_v_12_cfg_chip2pad_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.muxed_v_12_cfg.chip2pad.q ), + + // to register interface (read) + .qs (muxed_v_12_cfg_chip2pad_qs) + ); + + + // F[input_en]: 1:1 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_muxed_v_12_cfg_input_en ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (muxed_v_12_cfg_input_en_we), + .wd (muxed_v_12_cfg_input_en_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.muxed_v_12_cfg.input_en.q ), + + // to register interface (read) + .qs (muxed_v_12_cfg_input_en_qs) + ); + + + // F[output_en]: 2:2 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_muxed_v_12_cfg_output_en ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (muxed_v_12_cfg_output_en_we), + .wd (muxed_v_12_cfg_output_en_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.muxed_v_12_cfg.output_en.q ), + + // to register interface (read) + .qs (muxed_v_12_cfg_output_en_qs) + ); + + + // F[pull_en]: 3:3 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_muxed_v_12_cfg_pull_en ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (muxed_v_12_cfg_pull_en_we), + .wd (muxed_v_12_cfg_pull_en_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.muxed_v_12_cfg.pull_en.q ), + + // to register interface (read) + .qs (muxed_v_12_cfg_pull_en_qs) + ); + + + // F[pull_sel]: 4:4 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_muxed_v_12_cfg_pull_sel ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (muxed_v_12_cfg_pull_sel_we), + .wd (muxed_v_12_cfg_pull_sel_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.muxed_v_12_cfg.pull_sel.q ), + + // to register interface (read) + .qs (muxed_v_12_cfg_pull_sel_qs) + ); + + + // R[muxed_v_12_mux_sel]: V(False) + + prim_subreg #( + .DW (3), + .SWACCESS("RW"), + .RESVAL (3'h5) + ) u_muxed_v_12_mux_sel ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (muxed_v_12_mux_sel_we), + .wd (muxed_v_12_mux_sel_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.muxed_v_12_mux_sel.q ), + + // to register interface (read) + .qs (muxed_v_12_mux_sel_qs) + ); + + + // R[muxed_v_13_cfg]: V(False) + + // F[chip2pad]: 0:0 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_muxed_v_13_cfg_chip2pad ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (muxed_v_13_cfg_chip2pad_we), + .wd (muxed_v_13_cfg_chip2pad_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.muxed_v_13_cfg.chip2pad.q ), + + // to register interface (read) + .qs (muxed_v_13_cfg_chip2pad_qs) + ); + + + // F[input_en]: 1:1 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_muxed_v_13_cfg_input_en ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (muxed_v_13_cfg_input_en_we), + .wd (muxed_v_13_cfg_input_en_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.muxed_v_13_cfg.input_en.q ), + + // to register interface (read) + .qs (muxed_v_13_cfg_input_en_qs) + ); + + + // F[output_en]: 2:2 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_muxed_v_13_cfg_output_en ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (muxed_v_13_cfg_output_en_we), + .wd (muxed_v_13_cfg_output_en_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.muxed_v_13_cfg.output_en.q ), + + // to register interface (read) + .qs (muxed_v_13_cfg_output_en_qs) + ); + + + // F[pull_en]: 3:3 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_muxed_v_13_cfg_pull_en ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (muxed_v_13_cfg_pull_en_we), + .wd (muxed_v_13_cfg_pull_en_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.muxed_v_13_cfg.pull_en.q ), + + // to register interface (read) + .qs (muxed_v_13_cfg_pull_en_qs) + ); + + + // F[pull_sel]: 4:4 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_muxed_v_13_cfg_pull_sel ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (muxed_v_13_cfg_pull_sel_we), + .wd (muxed_v_13_cfg_pull_sel_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.muxed_v_13_cfg.pull_sel.q ), + + // to register interface (read) + .qs (muxed_v_13_cfg_pull_sel_qs) + ); + + + // R[muxed_v_13_mux_sel]: V(False) + + prim_subreg #( + .DW (3), + .SWACCESS("RW"), + .RESVAL (3'h5) + ) u_muxed_v_13_mux_sel ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (muxed_v_13_mux_sel_we), + .wd (muxed_v_13_mux_sel_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.muxed_v_13_mux_sel.q ), + + // to register interface (read) + .qs (muxed_v_13_mux_sel_qs) + ); + + + // R[muxed_v_14_cfg]: V(False) + + // F[chip2pad]: 0:0 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_muxed_v_14_cfg_chip2pad ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (muxed_v_14_cfg_chip2pad_we), + .wd (muxed_v_14_cfg_chip2pad_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.muxed_v_14_cfg.chip2pad.q ), + + // to register interface (read) + .qs (muxed_v_14_cfg_chip2pad_qs) + ); + + + // F[input_en]: 1:1 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_muxed_v_14_cfg_input_en ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (muxed_v_14_cfg_input_en_we), + .wd (muxed_v_14_cfg_input_en_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.muxed_v_14_cfg.input_en.q ), + + // to register interface (read) + .qs (muxed_v_14_cfg_input_en_qs) + ); + + + // F[output_en]: 2:2 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_muxed_v_14_cfg_output_en ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (muxed_v_14_cfg_output_en_we), + .wd (muxed_v_14_cfg_output_en_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.muxed_v_14_cfg.output_en.q ), + + // to register interface (read) + .qs (muxed_v_14_cfg_output_en_qs) + ); + + + // F[pull_en]: 3:3 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_muxed_v_14_cfg_pull_en ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (muxed_v_14_cfg_pull_en_we), + .wd (muxed_v_14_cfg_pull_en_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.muxed_v_14_cfg.pull_en.q ), + + // to register interface (read) + .qs (muxed_v_14_cfg_pull_en_qs) + ); + + + // F[pull_sel]: 4:4 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_muxed_v_14_cfg_pull_sel ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (muxed_v_14_cfg_pull_sel_we), + .wd (muxed_v_14_cfg_pull_sel_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.muxed_v_14_cfg.pull_sel.q ), + + // to register interface (read) + .qs (muxed_v_14_cfg_pull_sel_qs) + ); + + + // R[muxed_v_14_mux_sel]: V(False) + + prim_subreg #( + .DW (3), + .SWACCESS("RW"), + .RESVAL (3'h4) + ) u_muxed_v_14_mux_sel ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (muxed_v_14_mux_sel_we), + .wd (muxed_v_14_mux_sel_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.muxed_v_14_mux_sel.q ), + + // to register interface (read) + .qs (muxed_v_14_mux_sel_qs) + ); + + + // R[muxed_v_15_cfg]: V(False) + + // F[chip2pad]: 0:0 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_muxed_v_15_cfg_chip2pad ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (muxed_v_15_cfg_chip2pad_we), + .wd (muxed_v_15_cfg_chip2pad_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.muxed_v_15_cfg.chip2pad.q ), + + // to register interface (read) + .qs (muxed_v_15_cfg_chip2pad_qs) + ); + + + // F[input_en]: 1:1 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_muxed_v_15_cfg_input_en ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (muxed_v_15_cfg_input_en_we), + .wd (muxed_v_15_cfg_input_en_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.muxed_v_15_cfg.input_en.q ), + + // to register interface (read) + .qs (muxed_v_15_cfg_input_en_qs) + ); + + + // F[output_en]: 2:2 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_muxed_v_15_cfg_output_en ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (muxed_v_15_cfg_output_en_we), + .wd (muxed_v_15_cfg_output_en_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.muxed_v_15_cfg.output_en.q ), + + // to register interface (read) + .qs (muxed_v_15_cfg_output_en_qs) + ); + + + // F[pull_en]: 3:3 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_muxed_v_15_cfg_pull_en ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (muxed_v_15_cfg_pull_en_we), + .wd (muxed_v_15_cfg_pull_en_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.muxed_v_15_cfg.pull_en.q ), + + // to register interface (read) + .qs (muxed_v_15_cfg_pull_en_qs) + ); + + + // F[pull_sel]: 4:4 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_muxed_v_15_cfg_pull_sel ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (muxed_v_15_cfg_pull_sel_we), + .wd (muxed_v_15_cfg_pull_sel_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.muxed_v_15_cfg.pull_sel.q ), + + // to register interface (read) + .qs (muxed_v_15_cfg_pull_sel_qs) + ); + + + // R[muxed_v_15_mux_sel]: V(False) + + prim_subreg #( + .DW (3), + .SWACCESS("RW"), + .RESVAL (3'h4) + ) u_muxed_v_15_mux_sel ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (muxed_v_15_mux_sel_we), + .wd (muxed_v_15_mux_sel_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.muxed_v_15_mux_sel.q ), + + // to register interface (read) + .qs (muxed_v_15_mux_sel_qs) + ); + + + // R[muxed_v_16_cfg]: V(False) + + // F[chip2pad]: 0:0 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_muxed_v_16_cfg_chip2pad ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (muxed_v_16_cfg_chip2pad_we), + .wd (muxed_v_16_cfg_chip2pad_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.muxed_v_16_cfg.chip2pad.q ), + + // to register interface (read) + .qs (muxed_v_16_cfg_chip2pad_qs) + ); + + + // F[input_en]: 1:1 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_muxed_v_16_cfg_input_en ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (muxed_v_16_cfg_input_en_we), + .wd (muxed_v_16_cfg_input_en_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.muxed_v_16_cfg.input_en.q ), + + // to register interface (read) + .qs (muxed_v_16_cfg_input_en_qs) + ); + + + // F[output_en]: 2:2 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_muxed_v_16_cfg_output_en ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (muxed_v_16_cfg_output_en_we), + .wd (muxed_v_16_cfg_output_en_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.muxed_v_16_cfg.output_en.q ), + + // to register interface (read) + .qs (muxed_v_16_cfg_output_en_qs) + ); + + + // F[pull_en]: 3:3 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_muxed_v_16_cfg_pull_en ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (muxed_v_16_cfg_pull_en_we), + .wd (muxed_v_16_cfg_pull_en_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.muxed_v_16_cfg.pull_en.q ), + + // to register interface (read) + .qs (muxed_v_16_cfg_pull_en_qs) + ); + + + // F[pull_sel]: 4:4 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_muxed_v_16_cfg_pull_sel ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (muxed_v_16_cfg_pull_sel_we), + .wd (muxed_v_16_cfg_pull_sel_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.muxed_v_16_cfg.pull_sel.q ), + + // to register interface (read) + .qs (muxed_v_16_cfg_pull_sel_qs) + ); + + + // R[muxed_v_16_mux_sel]: V(False) + + prim_subreg #( + .DW (3), + .SWACCESS("RW"), + .RESVAL (3'h4) + ) u_muxed_v_16_mux_sel ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (muxed_v_16_mux_sel_we), + .wd (muxed_v_16_mux_sel_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.muxed_v_16_mux_sel.q ), + + // to register interface (read) + .qs (muxed_v_16_mux_sel_qs) + ); + + + // R[muxed_v_17_cfg]: V(False) + + // F[chip2pad]: 0:0 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_muxed_v_17_cfg_chip2pad ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (muxed_v_17_cfg_chip2pad_we), + .wd (muxed_v_17_cfg_chip2pad_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.muxed_v_17_cfg.chip2pad.q ), + + // to register interface (read) + .qs (muxed_v_17_cfg_chip2pad_qs) + ); + + + // F[input_en]: 1:1 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_muxed_v_17_cfg_input_en ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (muxed_v_17_cfg_input_en_we), + .wd (muxed_v_17_cfg_input_en_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.muxed_v_17_cfg.input_en.q ), + + // to register interface (read) + .qs (muxed_v_17_cfg_input_en_qs) + ); + + + // F[output_en]: 2:2 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_muxed_v_17_cfg_output_en ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (muxed_v_17_cfg_output_en_we), + .wd (muxed_v_17_cfg_output_en_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.muxed_v_17_cfg.output_en.q ), + + // to register interface (read) + .qs (muxed_v_17_cfg_output_en_qs) + ); + + + // F[pull_en]: 3:3 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_muxed_v_17_cfg_pull_en ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (muxed_v_17_cfg_pull_en_we), + .wd (muxed_v_17_cfg_pull_en_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.muxed_v_17_cfg.pull_en.q ), + + // to register interface (read) + .qs (muxed_v_17_cfg_pull_en_qs) + ); + + + // F[pull_sel]: 4:4 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_muxed_v_17_cfg_pull_sel ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (muxed_v_17_cfg_pull_sel_we), + .wd (muxed_v_17_cfg_pull_sel_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.muxed_v_17_cfg.pull_sel.q ), + + // to register interface (read) + .qs (muxed_v_17_cfg_pull_sel_qs) + ); + + + // R[muxed_v_17_mux_sel]: V(False) + + prim_subreg #( + .DW (3), + .SWACCESS("RW"), + .RESVAL (3'h4) + ) u_muxed_v_17_mux_sel ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (muxed_v_17_mux_sel_we), + .wd (muxed_v_17_mux_sel_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.muxed_v_17_mux_sel.q ), + + // to register interface (read) + .qs (muxed_v_17_mux_sel_qs) + ); + + + // R[muxed_h_00_cfg]: V(False) + + // F[chip2pad]: 0:0 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_muxed_h_00_cfg_chip2pad ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (muxed_h_00_cfg_chip2pad_we), + .wd (muxed_h_00_cfg_chip2pad_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.muxed_h_00_cfg.chip2pad.q ), + + // to register interface (read) + .qs (muxed_h_00_cfg_chip2pad_qs) + ); + + + // F[input_en]: 1:1 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_muxed_h_00_cfg_input_en ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (muxed_h_00_cfg_input_en_we), + .wd (muxed_h_00_cfg_input_en_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.muxed_h_00_cfg.input_en.q ), + + // to register interface (read) + .qs (muxed_h_00_cfg_input_en_qs) + ); + + + // F[output_en]: 2:2 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_muxed_h_00_cfg_output_en ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (muxed_h_00_cfg_output_en_we), + .wd (muxed_h_00_cfg_output_en_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.muxed_h_00_cfg.output_en.q ), + + // to register interface (read) + .qs (muxed_h_00_cfg_output_en_qs) + ); + + + // F[pull_en]: 3:3 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_muxed_h_00_cfg_pull_en ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (muxed_h_00_cfg_pull_en_we), + .wd (muxed_h_00_cfg_pull_en_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.muxed_h_00_cfg.pull_en.q ), + + // to register interface (read) + .qs (muxed_h_00_cfg_pull_en_qs) + ); + + + // F[pull_sel]: 4:4 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_muxed_h_00_cfg_pull_sel ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (muxed_h_00_cfg_pull_sel_we), + .wd (muxed_h_00_cfg_pull_sel_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.muxed_h_00_cfg.pull_sel.q ), + + // to register interface (read) + .qs (muxed_h_00_cfg_pull_sel_qs) + ); + + + // R[muxed_h_00_mux_sel]: V(False) + + prim_subreg #( + .DW (3), + .SWACCESS("RW"), + .RESVAL (3'h4) + ) u_muxed_h_00_mux_sel ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (muxed_h_00_mux_sel_we), + .wd (muxed_h_00_mux_sel_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.muxed_h_00_mux_sel.q ), + + // to register interface (read) + .qs (muxed_h_00_mux_sel_qs) + ); + + + // R[muxed_h_01_cfg]: V(False) + + // F[chip2pad]: 0:0 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_muxed_h_01_cfg_chip2pad ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (muxed_h_01_cfg_chip2pad_we), + .wd (muxed_h_01_cfg_chip2pad_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.muxed_h_01_cfg.chip2pad.q ), + + // to register interface (read) + .qs (muxed_h_01_cfg_chip2pad_qs) + ); + + + // F[input_en]: 1:1 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_muxed_h_01_cfg_input_en ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (muxed_h_01_cfg_input_en_we), + .wd (muxed_h_01_cfg_input_en_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.muxed_h_01_cfg.input_en.q ), + + // to register interface (read) + .qs (muxed_h_01_cfg_input_en_qs) + ); + + + // F[output_en]: 2:2 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_muxed_h_01_cfg_output_en ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (muxed_h_01_cfg_output_en_we), + .wd (muxed_h_01_cfg_output_en_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.muxed_h_01_cfg.output_en.q ), + + // to register interface (read) + .qs (muxed_h_01_cfg_output_en_qs) + ); + + + // F[pull_en]: 3:3 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_muxed_h_01_cfg_pull_en ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (muxed_h_01_cfg_pull_en_we), + .wd (muxed_h_01_cfg_pull_en_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.muxed_h_01_cfg.pull_en.q ), + + // to register interface (read) + .qs (muxed_h_01_cfg_pull_en_qs) + ); + + + // F[pull_sel]: 4:4 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_muxed_h_01_cfg_pull_sel ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (muxed_h_01_cfg_pull_sel_we), + .wd (muxed_h_01_cfg_pull_sel_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.muxed_h_01_cfg.pull_sel.q ), + + // to register interface (read) + .qs (muxed_h_01_cfg_pull_sel_qs) + ); + + + // R[muxed_h_01_mux_sel]: V(False) + + prim_subreg #( + .DW (3), + .SWACCESS("RW"), + .RESVAL (3'h4) + ) u_muxed_h_01_mux_sel ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (muxed_h_01_mux_sel_we), + .wd (muxed_h_01_mux_sel_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.muxed_h_01_mux_sel.q ), + + // to register interface (read) + .qs (muxed_h_01_mux_sel_qs) + ); + + + // R[muxed_h_02_cfg]: V(False) + + // F[chip2pad]: 0:0 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_muxed_h_02_cfg_chip2pad ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (muxed_h_02_cfg_chip2pad_we), + .wd (muxed_h_02_cfg_chip2pad_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.muxed_h_02_cfg.chip2pad.q ), + + // to register interface (read) + .qs (muxed_h_02_cfg_chip2pad_qs) + ); + + + // F[input_en]: 1:1 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_muxed_h_02_cfg_input_en ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (muxed_h_02_cfg_input_en_we), + .wd (muxed_h_02_cfg_input_en_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.muxed_h_02_cfg.input_en.q ), + + // to register interface (read) + .qs (muxed_h_02_cfg_input_en_qs) + ); + + + // F[output_en]: 2:2 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_muxed_h_02_cfg_output_en ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (muxed_h_02_cfg_output_en_we), + .wd (muxed_h_02_cfg_output_en_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.muxed_h_02_cfg.output_en.q ), + + // to register interface (read) + .qs (muxed_h_02_cfg_output_en_qs) + ); + + + // F[pull_en]: 3:3 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_muxed_h_02_cfg_pull_en ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (muxed_h_02_cfg_pull_en_we), + .wd (muxed_h_02_cfg_pull_en_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.muxed_h_02_cfg.pull_en.q ), + + // to register interface (read) + .qs (muxed_h_02_cfg_pull_en_qs) + ); + + + // F[pull_sel]: 4:4 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_muxed_h_02_cfg_pull_sel ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (muxed_h_02_cfg_pull_sel_we), + .wd (muxed_h_02_cfg_pull_sel_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.muxed_h_02_cfg.pull_sel.q ), + + // to register interface (read) + .qs (muxed_h_02_cfg_pull_sel_qs) + ); + + + // R[muxed_h_02_mux_sel]: V(False) + + prim_subreg #( + .DW (3), + .SWACCESS("RW"), + .RESVAL (3'h4) + ) u_muxed_h_02_mux_sel ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (muxed_h_02_mux_sel_we), + .wd (muxed_h_02_mux_sel_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.muxed_h_02_mux_sel.q ), + + // to register interface (read) + .qs (muxed_h_02_mux_sel_qs) + ); + + + // R[muxed_h_03_cfg]: V(False) + + // F[chip2pad]: 0:0 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_muxed_h_03_cfg_chip2pad ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (muxed_h_03_cfg_chip2pad_we), + .wd (muxed_h_03_cfg_chip2pad_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.muxed_h_03_cfg.chip2pad.q ), + + // to register interface (read) + .qs (muxed_h_03_cfg_chip2pad_qs) + ); + + + // F[input_en]: 1:1 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_muxed_h_03_cfg_input_en ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (muxed_h_03_cfg_input_en_we), + .wd (muxed_h_03_cfg_input_en_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.muxed_h_03_cfg.input_en.q ), + + // to register interface (read) + .qs (muxed_h_03_cfg_input_en_qs) + ); + + + // F[output_en]: 2:2 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_muxed_h_03_cfg_output_en ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (muxed_h_03_cfg_output_en_we), + .wd (muxed_h_03_cfg_output_en_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.muxed_h_03_cfg.output_en.q ), + + // to register interface (read) + .qs (muxed_h_03_cfg_output_en_qs) + ); + + + // F[pull_en]: 3:3 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_muxed_h_03_cfg_pull_en ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (muxed_h_03_cfg_pull_en_we), + .wd (muxed_h_03_cfg_pull_en_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.muxed_h_03_cfg.pull_en.q ), + + // to register interface (read) + .qs (muxed_h_03_cfg_pull_en_qs) + ); + + + // F[pull_sel]: 4:4 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_muxed_h_03_cfg_pull_sel ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (muxed_h_03_cfg_pull_sel_we), + .wd (muxed_h_03_cfg_pull_sel_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.muxed_h_03_cfg.pull_sel.q ), + + // to register interface (read) + .qs (muxed_h_03_cfg_pull_sel_qs) + ); + + + // R[muxed_h_03_mux_sel]: V(False) + + prim_subreg #( + .DW (3), + .SWACCESS("RW"), + .RESVAL (3'h4) + ) u_muxed_h_03_mux_sel ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (muxed_h_03_mux_sel_we), + .wd (muxed_h_03_mux_sel_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.muxed_h_03_mux_sel.q ), + + // to register interface (read) + .qs (muxed_h_03_mux_sel_qs) + ); + + + + + logic [44:0] addr_hit; + always_comb begin + addr_hit = '0; + addr_hit[ 0] = (reg_addr == ASTRAL_PADFRAME_PERIPH_CONFIG_INFO_OFFSET); + addr_hit[ 1] = (reg_addr == ASTRAL_PADFRAME_PERIPH_CONFIG_MUXED_V_00_CFG_OFFSET); + addr_hit[ 2] = (reg_addr == ASTRAL_PADFRAME_PERIPH_CONFIG_MUXED_V_00_MUX_SEL_OFFSET); + addr_hit[ 3] = (reg_addr == ASTRAL_PADFRAME_PERIPH_CONFIG_MUXED_V_01_CFG_OFFSET); + addr_hit[ 4] = (reg_addr == ASTRAL_PADFRAME_PERIPH_CONFIG_MUXED_V_01_MUX_SEL_OFFSET); + addr_hit[ 5] = (reg_addr == ASTRAL_PADFRAME_PERIPH_CONFIG_MUXED_V_02_CFG_OFFSET); + addr_hit[ 6] = (reg_addr == ASTRAL_PADFRAME_PERIPH_CONFIG_MUXED_V_02_MUX_SEL_OFFSET); + addr_hit[ 7] = (reg_addr == ASTRAL_PADFRAME_PERIPH_CONFIG_MUXED_V_03_CFG_OFFSET); + addr_hit[ 8] = (reg_addr == ASTRAL_PADFRAME_PERIPH_CONFIG_MUXED_V_03_MUX_SEL_OFFSET); + addr_hit[ 9] = (reg_addr == ASTRAL_PADFRAME_PERIPH_CONFIG_MUXED_V_04_CFG_OFFSET); + addr_hit[10] = (reg_addr == ASTRAL_PADFRAME_PERIPH_CONFIG_MUXED_V_04_MUX_SEL_OFFSET); + addr_hit[11] = (reg_addr == ASTRAL_PADFRAME_PERIPH_CONFIG_MUXED_V_05_CFG_OFFSET); + addr_hit[12] = (reg_addr == ASTRAL_PADFRAME_PERIPH_CONFIG_MUXED_V_05_MUX_SEL_OFFSET); + addr_hit[13] = (reg_addr == ASTRAL_PADFRAME_PERIPH_CONFIG_MUXED_V_06_CFG_OFFSET); + addr_hit[14] = (reg_addr == ASTRAL_PADFRAME_PERIPH_CONFIG_MUXED_V_06_MUX_SEL_OFFSET); + addr_hit[15] = (reg_addr == ASTRAL_PADFRAME_PERIPH_CONFIG_MUXED_V_07_CFG_OFFSET); + addr_hit[16] = (reg_addr == ASTRAL_PADFRAME_PERIPH_CONFIG_MUXED_V_07_MUX_SEL_OFFSET); + addr_hit[17] = (reg_addr == ASTRAL_PADFRAME_PERIPH_CONFIG_MUXED_V_08_CFG_OFFSET); + addr_hit[18] = (reg_addr == ASTRAL_PADFRAME_PERIPH_CONFIG_MUXED_V_08_MUX_SEL_OFFSET); + addr_hit[19] = (reg_addr == ASTRAL_PADFRAME_PERIPH_CONFIG_MUXED_V_09_CFG_OFFSET); + addr_hit[20] = (reg_addr == ASTRAL_PADFRAME_PERIPH_CONFIG_MUXED_V_09_MUX_SEL_OFFSET); + addr_hit[21] = (reg_addr == ASTRAL_PADFRAME_PERIPH_CONFIG_MUXED_V_10_CFG_OFFSET); + addr_hit[22] = (reg_addr == ASTRAL_PADFRAME_PERIPH_CONFIG_MUXED_V_10_MUX_SEL_OFFSET); + addr_hit[23] = (reg_addr == ASTRAL_PADFRAME_PERIPH_CONFIG_MUXED_V_11_CFG_OFFSET); + addr_hit[24] = (reg_addr == ASTRAL_PADFRAME_PERIPH_CONFIG_MUXED_V_11_MUX_SEL_OFFSET); + addr_hit[25] = (reg_addr == ASTRAL_PADFRAME_PERIPH_CONFIG_MUXED_V_12_CFG_OFFSET); + addr_hit[26] = (reg_addr == ASTRAL_PADFRAME_PERIPH_CONFIG_MUXED_V_12_MUX_SEL_OFFSET); + addr_hit[27] = (reg_addr == ASTRAL_PADFRAME_PERIPH_CONFIG_MUXED_V_13_CFG_OFFSET); + addr_hit[28] = (reg_addr == ASTRAL_PADFRAME_PERIPH_CONFIG_MUXED_V_13_MUX_SEL_OFFSET); + addr_hit[29] = (reg_addr == ASTRAL_PADFRAME_PERIPH_CONFIG_MUXED_V_14_CFG_OFFSET); + addr_hit[30] = (reg_addr == ASTRAL_PADFRAME_PERIPH_CONFIG_MUXED_V_14_MUX_SEL_OFFSET); + addr_hit[31] = (reg_addr == ASTRAL_PADFRAME_PERIPH_CONFIG_MUXED_V_15_CFG_OFFSET); + addr_hit[32] = (reg_addr == ASTRAL_PADFRAME_PERIPH_CONFIG_MUXED_V_15_MUX_SEL_OFFSET); + addr_hit[33] = (reg_addr == ASTRAL_PADFRAME_PERIPH_CONFIG_MUXED_V_16_CFG_OFFSET); + addr_hit[34] = (reg_addr == ASTRAL_PADFRAME_PERIPH_CONFIG_MUXED_V_16_MUX_SEL_OFFSET); + addr_hit[35] = (reg_addr == ASTRAL_PADFRAME_PERIPH_CONFIG_MUXED_V_17_CFG_OFFSET); + addr_hit[36] = (reg_addr == ASTRAL_PADFRAME_PERIPH_CONFIG_MUXED_V_17_MUX_SEL_OFFSET); + addr_hit[37] = (reg_addr == ASTRAL_PADFRAME_PERIPH_CONFIG_MUXED_H_00_CFG_OFFSET); + addr_hit[38] = (reg_addr == ASTRAL_PADFRAME_PERIPH_CONFIG_MUXED_H_00_MUX_SEL_OFFSET); + addr_hit[39] = (reg_addr == ASTRAL_PADFRAME_PERIPH_CONFIG_MUXED_H_01_CFG_OFFSET); + addr_hit[40] = (reg_addr == ASTRAL_PADFRAME_PERIPH_CONFIG_MUXED_H_01_MUX_SEL_OFFSET); + addr_hit[41] = (reg_addr == ASTRAL_PADFRAME_PERIPH_CONFIG_MUXED_H_02_CFG_OFFSET); + addr_hit[42] = (reg_addr == ASTRAL_PADFRAME_PERIPH_CONFIG_MUXED_H_02_MUX_SEL_OFFSET); + addr_hit[43] = (reg_addr == ASTRAL_PADFRAME_PERIPH_CONFIG_MUXED_H_03_CFG_OFFSET); + addr_hit[44] = (reg_addr == ASTRAL_PADFRAME_PERIPH_CONFIG_MUXED_H_03_MUX_SEL_OFFSET); + end + + assign addrmiss = (reg_re || reg_we) ? ~|addr_hit : 1'b0 ; + + // Check sub-word write is permitted + always_comb begin + wr_err = (reg_we & + ((addr_hit[ 0] & (|(ASTRAL_PADFRAME_PERIPH_CONFIG_PERMIT[ 0] & ~reg_be))) | + (addr_hit[ 1] & (|(ASTRAL_PADFRAME_PERIPH_CONFIG_PERMIT[ 1] & ~reg_be))) | + (addr_hit[ 2] & (|(ASTRAL_PADFRAME_PERIPH_CONFIG_PERMIT[ 2] & ~reg_be))) | + (addr_hit[ 3] & (|(ASTRAL_PADFRAME_PERIPH_CONFIG_PERMIT[ 3] & ~reg_be))) | + (addr_hit[ 4] & (|(ASTRAL_PADFRAME_PERIPH_CONFIG_PERMIT[ 4] & ~reg_be))) | + (addr_hit[ 5] & (|(ASTRAL_PADFRAME_PERIPH_CONFIG_PERMIT[ 5] & ~reg_be))) | + (addr_hit[ 6] & (|(ASTRAL_PADFRAME_PERIPH_CONFIG_PERMIT[ 6] & ~reg_be))) | + (addr_hit[ 7] & (|(ASTRAL_PADFRAME_PERIPH_CONFIG_PERMIT[ 7] & ~reg_be))) | + (addr_hit[ 8] & (|(ASTRAL_PADFRAME_PERIPH_CONFIG_PERMIT[ 8] & ~reg_be))) | + (addr_hit[ 9] & (|(ASTRAL_PADFRAME_PERIPH_CONFIG_PERMIT[ 9] & ~reg_be))) | + (addr_hit[10] & (|(ASTRAL_PADFRAME_PERIPH_CONFIG_PERMIT[10] & ~reg_be))) | + (addr_hit[11] & (|(ASTRAL_PADFRAME_PERIPH_CONFIG_PERMIT[11] & ~reg_be))) | + (addr_hit[12] & (|(ASTRAL_PADFRAME_PERIPH_CONFIG_PERMIT[12] & ~reg_be))) | + (addr_hit[13] & (|(ASTRAL_PADFRAME_PERIPH_CONFIG_PERMIT[13] & ~reg_be))) | + (addr_hit[14] & (|(ASTRAL_PADFRAME_PERIPH_CONFIG_PERMIT[14] & ~reg_be))) | + (addr_hit[15] & (|(ASTRAL_PADFRAME_PERIPH_CONFIG_PERMIT[15] & ~reg_be))) | + (addr_hit[16] & (|(ASTRAL_PADFRAME_PERIPH_CONFIG_PERMIT[16] & ~reg_be))) | + (addr_hit[17] & (|(ASTRAL_PADFRAME_PERIPH_CONFIG_PERMIT[17] & ~reg_be))) | + (addr_hit[18] & (|(ASTRAL_PADFRAME_PERIPH_CONFIG_PERMIT[18] & ~reg_be))) | + (addr_hit[19] & (|(ASTRAL_PADFRAME_PERIPH_CONFIG_PERMIT[19] & ~reg_be))) | + (addr_hit[20] & (|(ASTRAL_PADFRAME_PERIPH_CONFIG_PERMIT[20] & ~reg_be))) | + (addr_hit[21] & (|(ASTRAL_PADFRAME_PERIPH_CONFIG_PERMIT[21] & ~reg_be))) | + (addr_hit[22] & (|(ASTRAL_PADFRAME_PERIPH_CONFIG_PERMIT[22] & ~reg_be))) | + (addr_hit[23] & (|(ASTRAL_PADFRAME_PERIPH_CONFIG_PERMIT[23] & ~reg_be))) | + (addr_hit[24] & (|(ASTRAL_PADFRAME_PERIPH_CONFIG_PERMIT[24] & ~reg_be))) | + (addr_hit[25] & (|(ASTRAL_PADFRAME_PERIPH_CONFIG_PERMIT[25] & ~reg_be))) | + (addr_hit[26] & (|(ASTRAL_PADFRAME_PERIPH_CONFIG_PERMIT[26] & ~reg_be))) | + (addr_hit[27] & (|(ASTRAL_PADFRAME_PERIPH_CONFIG_PERMIT[27] & ~reg_be))) | + (addr_hit[28] & (|(ASTRAL_PADFRAME_PERIPH_CONFIG_PERMIT[28] & ~reg_be))) | + (addr_hit[29] & (|(ASTRAL_PADFRAME_PERIPH_CONFIG_PERMIT[29] & ~reg_be))) | + (addr_hit[30] & (|(ASTRAL_PADFRAME_PERIPH_CONFIG_PERMIT[30] & ~reg_be))) | + (addr_hit[31] & (|(ASTRAL_PADFRAME_PERIPH_CONFIG_PERMIT[31] & ~reg_be))) | + (addr_hit[32] & (|(ASTRAL_PADFRAME_PERIPH_CONFIG_PERMIT[32] & ~reg_be))) | + (addr_hit[33] & (|(ASTRAL_PADFRAME_PERIPH_CONFIG_PERMIT[33] & ~reg_be))) | + (addr_hit[34] & (|(ASTRAL_PADFRAME_PERIPH_CONFIG_PERMIT[34] & ~reg_be))) | + (addr_hit[35] & (|(ASTRAL_PADFRAME_PERIPH_CONFIG_PERMIT[35] & ~reg_be))) | + (addr_hit[36] & (|(ASTRAL_PADFRAME_PERIPH_CONFIG_PERMIT[36] & ~reg_be))) | + (addr_hit[37] & (|(ASTRAL_PADFRAME_PERIPH_CONFIG_PERMIT[37] & ~reg_be))) | + (addr_hit[38] & (|(ASTRAL_PADFRAME_PERIPH_CONFIG_PERMIT[38] & ~reg_be))) | + (addr_hit[39] & (|(ASTRAL_PADFRAME_PERIPH_CONFIG_PERMIT[39] & ~reg_be))) | + (addr_hit[40] & (|(ASTRAL_PADFRAME_PERIPH_CONFIG_PERMIT[40] & ~reg_be))) | + (addr_hit[41] & (|(ASTRAL_PADFRAME_PERIPH_CONFIG_PERMIT[41] & ~reg_be))) | + (addr_hit[42] & (|(ASTRAL_PADFRAME_PERIPH_CONFIG_PERMIT[42] & ~reg_be))) | + (addr_hit[43] & (|(ASTRAL_PADFRAME_PERIPH_CONFIG_PERMIT[43] & ~reg_be))) | + (addr_hit[44] & (|(ASTRAL_PADFRAME_PERIPH_CONFIG_PERMIT[44] & ~reg_be))))); + end + + assign muxed_v_00_cfg_chip2pad_we = addr_hit[1] & reg_we & !reg_error; + assign muxed_v_00_cfg_chip2pad_wd = reg_wdata[0]; + + assign muxed_v_00_cfg_input_en_we = addr_hit[1] & reg_we & !reg_error; + assign muxed_v_00_cfg_input_en_wd = reg_wdata[1]; + + assign muxed_v_00_cfg_output_en_we = addr_hit[1] & reg_we & !reg_error; + assign muxed_v_00_cfg_output_en_wd = reg_wdata[2]; + + assign muxed_v_00_cfg_pull_en_we = addr_hit[1] & reg_we & !reg_error; + assign muxed_v_00_cfg_pull_en_wd = reg_wdata[3]; + + assign muxed_v_00_cfg_pull_sel_we = addr_hit[1] & reg_we & !reg_error; + assign muxed_v_00_cfg_pull_sel_wd = reg_wdata[4]; + + assign muxed_v_00_mux_sel_we = addr_hit[2] & reg_we & !reg_error; + assign muxed_v_00_mux_sel_wd = reg_wdata[2:0]; + + assign muxed_v_01_cfg_chip2pad_we = addr_hit[3] & reg_we & !reg_error; + assign muxed_v_01_cfg_chip2pad_wd = reg_wdata[0]; + + assign muxed_v_01_cfg_input_en_we = addr_hit[3] & reg_we & !reg_error; + assign muxed_v_01_cfg_input_en_wd = reg_wdata[1]; + + assign muxed_v_01_cfg_output_en_we = addr_hit[3] & reg_we & !reg_error; + assign muxed_v_01_cfg_output_en_wd = reg_wdata[2]; + + assign muxed_v_01_cfg_pull_en_we = addr_hit[3] & reg_we & !reg_error; + assign muxed_v_01_cfg_pull_en_wd = reg_wdata[3]; + + assign muxed_v_01_cfg_pull_sel_we = addr_hit[3] & reg_we & !reg_error; + assign muxed_v_01_cfg_pull_sel_wd = reg_wdata[4]; + + assign muxed_v_01_mux_sel_we = addr_hit[4] & reg_we & !reg_error; + assign muxed_v_01_mux_sel_wd = reg_wdata[2:0]; + + assign muxed_v_02_cfg_chip2pad_we = addr_hit[5] & reg_we & !reg_error; + assign muxed_v_02_cfg_chip2pad_wd = reg_wdata[0]; + + assign muxed_v_02_cfg_input_en_we = addr_hit[5] & reg_we & !reg_error; + assign muxed_v_02_cfg_input_en_wd = reg_wdata[1]; + + assign muxed_v_02_cfg_output_en_we = addr_hit[5] & reg_we & !reg_error; + assign muxed_v_02_cfg_output_en_wd = reg_wdata[2]; + + assign muxed_v_02_cfg_pull_en_we = addr_hit[5] & reg_we & !reg_error; + assign muxed_v_02_cfg_pull_en_wd = reg_wdata[3]; + + assign muxed_v_02_cfg_pull_sel_we = addr_hit[5] & reg_we & !reg_error; + assign muxed_v_02_cfg_pull_sel_wd = reg_wdata[4]; + + assign muxed_v_02_mux_sel_we = addr_hit[6] & reg_we & !reg_error; + assign muxed_v_02_mux_sel_wd = reg_wdata[1:0]; + + assign muxed_v_03_cfg_chip2pad_we = addr_hit[7] & reg_we & !reg_error; + assign muxed_v_03_cfg_chip2pad_wd = reg_wdata[0]; + + assign muxed_v_03_cfg_input_en_we = addr_hit[7] & reg_we & !reg_error; + assign muxed_v_03_cfg_input_en_wd = reg_wdata[1]; + + assign muxed_v_03_cfg_output_en_we = addr_hit[7] & reg_we & !reg_error; + assign muxed_v_03_cfg_output_en_wd = reg_wdata[2]; + + assign muxed_v_03_cfg_pull_en_we = addr_hit[7] & reg_we & !reg_error; + assign muxed_v_03_cfg_pull_en_wd = reg_wdata[3]; + + assign muxed_v_03_cfg_pull_sel_we = addr_hit[7] & reg_we & !reg_error; + assign muxed_v_03_cfg_pull_sel_wd = reg_wdata[4]; + + assign muxed_v_03_mux_sel_we = addr_hit[8] & reg_we & !reg_error; + assign muxed_v_03_mux_sel_wd = reg_wdata[1:0]; + + assign muxed_v_04_cfg_chip2pad_we = addr_hit[9] & reg_we & !reg_error; + assign muxed_v_04_cfg_chip2pad_wd = reg_wdata[0]; + + assign muxed_v_04_cfg_input_en_we = addr_hit[9] & reg_we & !reg_error; + assign muxed_v_04_cfg_input_en_wd = reg_wdata[1]; + + assign muxed_v_04_cfg_output_en_we = addr_hit[9] & reg_we & !reg_error; + assign muxed_v_04_cfg_output_en_wd = reg_wdata[2]; + + assign muxed_v_04_cfg_pull_en_we = addr_hit[9] & reg_we & !reg_error; + assign muxed_v_04_cfg_pull_en_wd = reg_wdata[3]; + + assign muxed_v_04_cfg_pull_sel_we = addr_hit[9] & reg_we & !reg_error; + assign muxed_v_04_cfg_pull_sel_wd = reg_wdata[4]; + + assign muxed_v_04_mux_sel_we = addr_hit[10] & reg_we & !reg_error; + assign muxed_v_04_mux_sel_wd = reg_wdata[2:0]; + + assign muxed_v_05_cfg_chip2pad_we = addr_hit[11] & reg_we & !reg_error; + assign muxed_v_05_cfg_chip2pad_wd = reg_wdata[0]; + + assign muxed_v_05_cfg_input_en_we = addr_hit[11] & reg_we & !reg_error; + assign muxed_v_05_cfg_input_en_wd = reg_wdata[1]; + + assign muxed_v_05_cfg_output_en_we = addr_hit[11] & reg_we & !reg_error; + assign muxed_v_05_cfg_output_en_wd = reg_wdata[2]; + + assign muxed_v_05_cfg_pull_en_we = addr_hit[11] & reg_we & !reg_error; + assign muxed_v_05_cfg_pull_en_wd = reg_wdata[3]; + + assign muxed_v_05_cfg_pull_sel_we = addr_hit[11] & reg_we & !reg_error; + assign muxed_v_05_cfg_pull_sel_wd = reg_wdata[4]; + + assign muxed_v_05_mux_sel_we = addr_hit[12] & reg_we & !reg_error; + assign muxed_v_05_mux_sel_wd = reg_wdata[2:0]; + + assign muxed_v_06_cfg_chip2pad_we = addr_hit[13] & reg_we & !reg_error; + assign muxed_v_06_cfg_chip2pad_wd = reg_wdata[0]; + + assign muxed_v_06_cfg_input_en_we = addr_hit[13] & reg_we & !reg_error; + assign muxed_v_06_cfg_input_en_wd = reg_wdata[1]; + + assign muxed_v_06_cfg_output_en_we = addr_hit[13] & reg_we & !reg_error; + assign muxed_v_06_cfg_output_en_wd = reg_wdata[2]; + + assign muxed_v_06_cfg_pull_en_we = addr_hit[13] & reg_we & !reg_error; + assign muxed_v_06_cfg_pull_en_wd = reg_wdata[3]; + + assign muxed_v_06_cfg_pull_sel_we = addr_hit[13] & reg_we & !reg_error; + assign muxed_v_06_cfg_pull_sel_wd = reg_wdata[4]; + + assign muxed_v_06_mux_sel_we = addr_hit[14] & reg_we & !reg_error; + assign muxed_v_06_mux_sel_wd = reg_wdata[1:0]; + + assign muxed_v_07_cfg_chip2pad_we = addr_hit[15] & reg_we & !reg_error; + assign muxed_v_07_cfg_chip2pad_wd = reg_wdata[0]; + + assign muxed_v_07_cfg_input_en_we = addr_hit[15] & reg_we & !reg_error; + assign muxed_v_07_cfg_input_en_wd = reg_wdata[1]; + + assign muxed_v_07_cfg_output_en_we = addr_hit[15] & reg_we & !reg_error; + assign muxed_v_07_cfg_output_en_wd = reg_wdata[2]; + + assign muxed_v_07_cfg_pull_en_we = addr_hit[15] & reg_we & !reg_error; + assign muxed_v_07_cfg_pull_en_wd = reg_wdata[3]; + + assign muxed_v_07_cfg_pull_sel_we = addr_hit[15] & reg_we & !reg_error; + assign muxed_v_07_cfg_pull_sel_wd = reg_wdata[4]; + + assign muxed_v_07_mux_sel_we = addr_hit[16] & reg_we & !reg_error; + assign muxed_v_07_mux_sel_wd = reg_wdata[2:0]; + + assign muxed_v_08_cfg_chip2pad_we = addr_hit[17] & reg_we & !reg_error; + assign muxed_v_08_cfg_chip2pad_wd = reg_wdata[0]; + + assign muxed_v_08_cfg_input_en_we = addr_hit[17] & reg_we & !reg_error; + assign muxed_v_08_cfg_input_en_wd = reg_wdata[1]; + + assign muxed_v_08_cfg_output_en_we = addr_hit[17] & reg_we & !reg_error; + assign muxed_v_08_cfg_output_en_wd = reg_wdata[2]; + + assign muxed_v_08_cfg_pull_en_we = addr_hit[17] & reg_we & !reg_error; + assign muxed_v_08_cfg_pull_en_wd = reg_wdata[3]; + + assign muxed_v_08_cfg_pull_sel_we = addr_hit[17] & reg_we & !reg_error; + assign muxed_v_08_cfg_pull_sel_wd = reg_wdata[4]; + + assign muxed_v_08_mux_sel_we = addr_hit[18] & reg_we & !reg_error; + assign muxed_v_08_mux_sel_wd = reg_wdata[2:0]; + + assign muxed_v_09_cfg_chip2pad_we = addr_hit[19] & reg_we & !reg_error; + assign muxed_v_09_cfg_chip2pad_wd = reg_wdata[0]; + + assign muxed_v_09_cfg_input_en_we = addr_hit[19] & reg_we & !reg_error; + assign muxed_v_09_cfg_input_en_wd = reg_wdata[1]; + + assign muxed_v_09_cfg_output_en_we = addr_hit[19] & reg_we & !reg_error; + assign muxed_v_09_cfg_output_en_wd = reg_wdata[2]; + + assign muxed_v_09_cfg_pull_en_we = addr_hit[19] & reg_we & !reg_error; + assign muxed_v_09_cfg_pull_en_wd = reg_wdata[3]; + + assign muxed_v_09_cfg_pull_sel_we = addr_hit[19] & reg_we & !reg_error; + assign muxed_v_09_cfg_pull_sel_wd = reg_wdata[4]; + + assign muxed_v_09_mux_sel_we = addr_hit[20] & reg_we & !reg_error; + assign muxed_v_09_mux_sel_wd = reg_wdata[2:0]; + + assign muxed_v_10_cfg_chip2pad_we = addr_hit[21] & reg_we & !reg_error; + assign muxed_v_10_cfg_chip2pad_wd = reg_wdata[0]; + + assign muxed_v_10_cfg_input_en_we = addr_hit[21] & reg_we & !reg_error; + assign muxed_v_10_cfg_input_en_wd = reg_wdata[1]; + + assign muxed_v_10_cfg_output_en_we = addr_hit[21] & reg_we & !reg_error; + assign muxed_v_10_cfg_output_en_wd = reg_wdata[2]; + + assign muxed_v_10_cfg_pull_en_we = addr_hit[21] & reg_we & !reg_error; + assign muxed_v_10_cfg_pull_en_wd = reg_wdata[3]; + + assign muxed_v_10_cfg_pull_sel_we = addr_hit[21] & reg_we & !reg_error; + assign muxed_v_10_cfg_pull_sel_wd = reg_wdata[4]; + + assign muxed_v_10_mux_sel_we = addr_hit[22] & reg_we & !reg_error; + assign muxed_v_10_mux_sel_wd = reg_wdata[2:0]; + + assign muxed_v_11_cfg_chip2pad_we = addr_hit[23] & reg_we & !reg_error; + assign muxed_v_11_cfg_chip2pad_wd = reg_wdata[0]; + + assign muxed_v_11_cfg_input_en_we = addr_hit[23] & reg_we & !reg_error; + assign muxed_v_11_cfg_input_en_wd = reg_wdata[1]; + + assign muxed_v_11_cfg_output_en_we = addr_hit[23] & reg_we & !reg_error; + assign muxed_v_11_cfg_output_en_wd = reg_wdata[2]; + + assign muxed_v_11_cfg_pull_en_we = addr_hit[23] & reg_we & !reg_error; + assign muxed_v_11_cfg_pull_en_wd = reg_wdata[3]; + + assign muxed_v_11_cfg_pull_sel_we = addr_hit[23] & reg_we & !reg_error; + assign muxed_v_11_cfg_pull_sel_wd = reg_wdata[4]; + + assign muxed_v_11_mux_sel_we = addr_hit[24] & reg_we & !reg_error; + assign muxed_v_11_mux_sel_wd = reg_wdata[2:0]; + + assign muxed_v_12_cfg_chip2pad_we = addr_hit[25] & reg_we & !reg_error; + assign muxed_v_12_cfg_chip2pad_wd = reg_wdata[0]; + + assign muxed_v_12_cfg_input_en_we = addr_hit[25] & reg_we & !reg_error; + assign muxed_v_12_cfg_input_en_wd = reg_wdata[1]; + + assign muxed_v_12_cfg_output_en_we = addr_hit[25] & reg_we & !reg_error; + assign muxed_v_12_cfg_output_en_wd = reg_wdata[2]; + + assign muxed_v_12_cfg_pull_en_we = addr_hit[25] & reg_we & !reg_error; + assign muxed_v_12_cfg_pull_en_wd = reg_wdata[3]; + + assign muxed_v_12_cfg_pull_sel_we = addr_hit[25] & reg_we & !reg_error; + assign muxed_v_12_cfg_pull_sel_wd = reg_wdata[4]; + + assign muxed_v_12_mux_sel_we = addr_hit[26] & reg_we & !reg_error; + assign muxed_v_12_mux_sel_wd = reg_wdata[2:0]; + + assign muxed_v_13_cfg_chip2pad_we = addr_hit[27] & reg_we & !reg_error; + assign muxed_v_13_cfg_chip2pad_wd = reg_wdata[0]; + + assign muxed_v_13_cfg_input_en_we = addr_hit[27] & reg_we & !reg_error; + assign muxed_v_13_cfg_input_en_wd = reg_wdata[1]; + + assign muxed_v_13_cfg_output_en_we = addr_hit[27] & reg_we & !reg_error; + assign muxed_v_13_cfg_output_en_wd = reg_wdata[2]; + + assign muxed_v_13_cfg_pull_en_we = addr_hit[27] & reg_we & !reg_error; + assign muxed_v_13_cfg_pull_en_wd = reg_wdata[3]; + + assign muxed_v_13_cfg_pull_sel_we = addr_hit[27] & reg_we & !reg_error; + assign muxed_v_13_cfg_pull_sel_wd = reg_wdata[4]; + + assign muxed_v_13_mux_sel_we = addr_hit[28] & reg_we & !reg_error; + assign muxed_v_13_mux_sel_wd = reg_wdata[2:0]; + + assign muxed_v_14_cfg_chip2pad_we = addr_hit[29] & reg_we & !reg_error; + assign muxed_v_14_cfg_chip2pad_wd = reg_wdata[0]; + + assign muxed_v_14_cfg_input_en_we = addr_hit[29] & reg_we & !reg_error; + assign muxed_v_14_cfg_input_en_wd = reg_wdata[1]; + + assign muxed_v_14_cfg_output_en_we = addr_hit[29] & reg_we & !reg_error; + assign muxed_v_14_cfg_output_en_wd = reg_wdata[2]; + + assign muxed_v_14_cfg_pull_en_we = addr_hit[29] & reg_we & !reg_error; + assign muxed_v_14_cfg_pull_en_wd = reg_wdata[3]; + + assign muxed_v_14_cfg_pull_sel_we = addr_hit[29] & reg_we & !reg_error; + assign muxed_v_14_cfg_pull_sel_wd = reg_wdata[4]; + + assign muxed_v_14_mux_sel_we = addr_hit[30] & reg_we & !reg_error; + assign muxed_v_14_mux_sel_wd = reg_wdata[2:0]; + + assign muxed_v_15_cfg_chip2pad_we = addr_hit[31] & reg_we & !reg_error; + assign muxed_v_15_cfg_chip2pad_wd = reg_wdata[0]; + + assign muxed_v_15_cfg_input_en_we = addr_hit[31] & reg_we & !reg_error; + assign muxed_v_15_cfg_input_en_wd = reg_wdata[1]; + + assign muxed_v_15_cfg_output_en_we = addr_hit[31] & reg_we & !reg_error; + assign muxed_v_15_cfg_output_en_wd = reg_wdata[2]; + + assign muxed_v_15_cfg_pull_en_we = addr_hit[31] & reg_we & !reg_error; + assign muxed_v_15_cfg_pull_en_wd = reg_wdata[3]; + + assign muxed_v_15_cfg_pull_sel_we = addr_hit[31] & reg_we & !reg_error; + assign muxed_v_15_cfg_pull_sel_wd = reg_wdata[4]; + + assign muxed_v_15_mux_sel_we = addr_hit[32] & reg_we & !reg_error; + assign muxed_v_15_mux_sel_wd = reg_wdata[2:0]; + + assign muxed_v_16_cfg_chip2pad_we = addr_hit[33] & reg_we & !reg_error; + assign muxed_v_16_cfg_chip2pad_wd = reg_wdata[0]; + + assign muxed_v_16_cfg_input_en_we = addr_hit[33] & reg_we & !reg_error; + assign muxed_v_16_cfg_input_en_wd = reg_wdata[1]; + + assign muxed_v_16_cfg_output_en_we = addr_hit[33] & reg_we & !reg_error; + assign muxed_v_16_cfg_output_en_wd = reg_wdata[2]; + + assign muxed_v_16_cfg_pull_en_we = addr_hit[33] & reg_we & !reg_error; + assign muxed_v_16_cfg_pull_en_wd = reg_wdata[3]; + + assign muxed_v_16_cfg_pull_sel_we = addr_hit[33] & reg_we & !reg_error; + assign muxed_v_16_cfg_pull_sel_wd = reg_wdata[4]; + + assign muxed_v_16_mux_sel_we = addr_hit[34] & reg_we & !reg_error; + assign muxed_v_16_mux_sel_wd = reg_wdata[2:0]; + + assign muxed_v_17_cfg_chip2pad_we = addr_hit[35] & reg_we & !reg_error; + assign muxed_v_17_cfg_chip2pad_wd = reg_wdata[0]; + + assign muxed_v_17_cfg_input_en_we = addr_hit[35] & reg_we & !reg_error; + assign muxed_v_17_cfg_input_en_wd = reg_wdata[1]; + + assign muxed_v_17_cfg_output_en_we = addr_hit[35] & reg_we & !reg_error; + assign muxed_v_17_cfg_output_en_wd = reg_wdata[2]; + + assign muxed_v_17_cfg_pull_en_we = addr_hit[35] & reg_we & !reg_error; + assign muxed_v_17_cfg_pull_en_wd = reg_wdata[3]; + + assign muxed_v_17_cfg_pull_sel_we = addr_hit[35] & reg_we & !reg_error; + assign muxed_v_17_cfg_pull_sel_wd = reg_wdata[4]; + + assign muxed_v_17_mux_sel_we = addr_hit[36] & reg_we & !reg_error; + assign muxed_v_17_mux_sel_wd = reg_wdata[2:0]; + + assign muxed_h_00_cfg_chip2pad_we = addr_hit[37] & reg_we & !reg_error; + assign muxed_h_00_cfg_chip2pad_wd = reg_wdata[0]; + + assign muxed_h_00_cfg_input_en_we = addr_hit[37] & reg_we & !reg_error; + assign muxed_h_00_cfg_input_en_wd = reg_wdata[1]; + + assign muxed_h_00_cfg_output_en_we = addr_hit[37] & reg_we & !reg_error; + assign muxed_h_00_cfg_output_en_wd = reg_wdata[2]; + + assign muxed_h_00_cfg_pull_en_we = addr_hit[37] & reg_we & !reg_error; + assign muxed_h_00_cfg_pull_en_wd = reg_wdata[3]; + + assign muxed_h_00_cfg_pull_sel_we = addr_hit[37] & reg_we & !reg_error; + assign muxed_h_00_cfg_pull_sel_wd = reg_wdata[4]; + + assign muxed_h_00_mux_sel_we = addr_hit[38] & reg_we & !reg_error; + assign muxed_h_00_mux_sel_wd = reg_wdata[2:0]; + + assign muxed_h_01_cfg_chip2pad_we = addr_hit[39] & reg_we & !reg_error; + assign muxed_h_01_cfg_chip2pad_wd = reg_wdata[0]; + + assign muxed_h_01_cfg_input_en_we = addr_hit[39] & reg_we & !reg_error; + assign muxed_h_01_cfg_input_en_wd = reg_wdata[1]; + + assign muxed_h_01_cfg_output_en_we = addr_hit[39] & reg_we & !reg_error; + assign muxed_h_01_cfg_output_en_wd = reg_wdata[2]; + + assign muxed_h_01_cfg_pull_en_we = addr_hit[39] & reg_we & !reg_error; + assign muxed_h_01_cfg_pull_en_wd = reg_wdata[3]; + + assign muxed_h_01_cfg_pull_sel_we = addr_hit[39] & reg_we & !reg_error; + assign muxed_h_01_cfg_pull_sel_wd = reg_wdata[4]; + + assign muxed_h_01_mux_sel_we = addr_hit[40] & reg_we & !reg_error; + assign muxed_h_01_mux_sel_wd = reg_wdata[2:0]; + + assign muxed_h_02_cfg_chip2pad_we = addr_hit[41] & reg_we & !reg_error; + assign muxed_h_02_cfg_chip2pad_wd = reg_wdata[0]; + + assign muxed_h_02_cfg_input_en_we = addr_hit[41] & reg_we & !reg_error; + assign muxed_h_02_cfg_input_en_wd = reg_wdata[1]; + + assign muxed_h_02_cfg_output_en_we = addr_hit[41] & reg_we & !reg_error; + assign muxed_h_02_cfg_output_en_wd = reg_wdata[2]; + + assign muxed_h_02_cfg_pull_en_we = addr_hit[41] & reg_we & !reg_error; + assign muxed_h_02_cfg_pull_en_wd = reg_wdata[3]; + + assign muxed_h_02_cfg_pull_sel_we = addr_hit[41] & reg_we & !reg_error; + assign muxed_h_02_cfg_pull_sel_wd = reg_wdata[4]; + + assign muxed_h_02_mux_sel_we = addr_hit[42] & reg_we & !reg_error; + assign muxed_h_02_mux_sel_wd = reg_wdata[2:0]; + + assign muxed_h_03_cfg_chip2pad_we = addr_hit[43] & reg_we & !reg_error; + assign muxed_h_03_cfg_chip2pad_wd = reg_wdata[0]; + + assign muxed_h_03_cfg_input_en_we = addr_hit[43] & reg_we & !reg_error; + assign muxed_h_03_cfg_input_en_wd = reg_wdata[1]; + + assign muxed_h_03_cfg_output_en_we = addr_hit[43] & reg_we & !reg_error; + assign muxed_h_03_cfg_output_en_wd = reg_wdata[2]; + + assign muxed_h_03_cfg_pull_en_we = addr_hit[43] & reg_we & !reg_error; + assign muxed_h_03_cfg_pull_en_wd = reg_wdata[3]; + + assign muxed_h_03_cfg_pull_sel_we = addr_hit[43] & reg_we & !reg_error; + assign muxed_h_03_cfg_pull_sel_wd = reg_wdata[4]; + + assign muxed_h_03_mux_sel_we = addr_hit[44] & reg_we & !reg_error; + assign muxed_h_03_mux_sel_wd = reg_wdata[2:0]; + + // Read data return + always_comb begin + reg_rdata_next = '0; + unique case (1'b1) + addr_hit[0]: begin + reg_rdata_next[15:0] = info_hw_version_qs; + reg_rdata_next[31:16] = info_padcount_qs; + end + + addr_hit[1]: begin + reg_rdata_next[0] = muxed_v_00_cfg_chip2pad_qs; + reg_rdata_next[1] = muxed_v_00_cfg_input_en_qs; + reg_rdata_next[2] = muxed_v_00_cfg_output_en_qs; + reg_rdata_next[3] = muxed_v_00_cfg_pull_en_qs; + reg_rdata_next[4] = muxed_v_00_cfg_pull_sel_qs; + end + + addr_hit[2]: begin + reg_rdata_next[2:0] = muxed_v_00_mux_sel_qs; + end + + addr_hit[3]: begin + reg_rdata_next[0] = muxed_v_01_cfg_chip2pad_qs; + reg_rdata_next[1] = muxed_v_01_cfg_input_en_qs; + reg_rdata_next[2] = muxed_v_01_cfg_output_en_qs; + reg_rdata_next[3] = muxed_v_01_cfg_pull_en_qs; + reg_rdata_next[4] = muxed_v_01_cfg_pull_sel_qs; + end + + addr_hit[4]: begin + reg_rdata_next[2:0] = muxed_v_01_mux_sel_qs; + end + + addr_hit[5]: begin + reg_rdata_next[0] = muxed_v_02_cfg_chip2pad_qs; + reg_rdata_next[1] = muxed_v_02_cfg_input_en_qs; + reg_rdata_next[2] = muxed_v_02_cfg_output_en_qs; + reg_rdata_next[3] = muxed_v_02_cfg_pull_en_qs; + reg_rdata_next[4] = muxed_v_02_cfg_pull_sel_qs; + end + + addr_hit[6]: begin + reg_rdata_next[1:0] = muxed_v_02_mux_sel_qs; + end + + addr_hit[7]: begin + reg_rdata_next[0] = muxed_v_03_cfg_chip2pad_qs; + reg_rdata_next[1] = muxed_v_03_cfg_input_en_qs; + reg_rdata_next[2] = muxed_v_03_cfg_output_en_qs; + reg_rdata_next[3] = muxed_v_03_cfg_pull_en_qs; + reg_rdata_next[4] = muxed_v_03_cfg_pull_sel_qs; + end + + addr_hit[8]: begin + reg_rdata_next[1:0] = muxed_v_03_mux_sel_qs; + end + + addr_hit[9]: begin + reg_rdata_next[0] = muxed_v_04_cfg_chip2pad_qs; + reg_rdata_next[1] = muxed_v_04_cfg_input_en_qs; + reg_rdata_next[2] = muxed_v_04_cfg_output_en_qs; + reg_rdata_next[3] = muxed_v_04_cfg_pull_en_qs; + reg_rdata_next[4] = muxed_v_04_cfg_pull_sel_qs; + end + + addr_hit[10]: begin + reg_rdata_next[2:0] = muxed_v_04_mux_sel_qs; + end + + addr_hit[11]: begin + reg_rdata_next[0] = muxed_v_05_cfg_chip2pad_qs; + reg_rdata_next[1] = muxed_v_05_cfg_input_en_qs; + reg_rdata_next[2] = muxed_v_05_cfg_output_en_qs; + reg_rdata_next[3] = muxed_v_05_cfg_pull_en_qs; + reg_rdata_next[4] = muxed_v_05_cfg_pull_sel_qs; + end + + addr_hit[12]: begin + reg_rdata_next[2:0] = muxed_v_05_mux_sel_qs; + end + + addr_hit[13]: begin + reg_rdata_next[0] = muxed_v_06_cfg_chip2pad_qs; + reg_rdata_next[1] = muxed_v_06_cfg_input_en_qs; + reg_rdata_next[2] = muxed_v_06_cfg_output_en_qs; + reg_rdata_next[3] = muxed_v_06_cfg_pull_en_qs; + reg_rdata_next[4] = muxed_v_06_cfg_pull_sel_qs; + end + + addr_hit[14]: begin + reg_rdata_next[1:0] = muxed_v_06_mux_sel_qs; + end + + addr_hit[15]: begin + reg_rdata_next[0] = muxed_v_07_cfg_chip2pad_qs; + reg_rdata_next[1] = muxed_v_07_cfg_input_en_qs; + reg_rdata_next[2] = muxed_v_07_cfg_output_en_qs; + reg_rdata_next[3] = muxed_v_07_cfg_pull_en_qs; + reg_rdata_next[4] = muxed_v_07_cfg_pull_sel_qs; + end + + addr_hit[16]: begin + reg_rdata_next[2:0] = muxed_v_07_mux_sel_qs; + end + + addr_hit[17]: begin + reg_rdata_next[0] = muxed_v_08_cfg_chip2pad_qs; + reg_rdata_next[1] = muxed_v_08_cfg_input_en_qs; + reg_rdata_next[2] = muxed_v_08_cfg_output_en_qs; + reg_rdata_next[3] = muxed_v_08_cfg_pull_en_qs; + reg_rdata_next[4] = muxed_v_08_cfg_pull_sel_qs; + end + + addr_hit[18]: begin + reg_rdata_next[2:0] = muxed_v_08_mux_sel_qs; + end + + addr_hit[19]: begin + reg_rdata_next[0] = muxed_v_09_cfg_chip2pad_qs; + reg_rdata_next[1] = muxed_v_09_cfg_input_en_qs; + reg_rdata_next[2] = muxed_v_09_cfg_output_en_qs; + reg_rdata_next[3] = muxed_v_09_cfg_pull_en_qs; + reg_rdata_next[4] = muxed_v_09_cfg_pull_sel_qs; + end + + addr_hit[20]: begin + reg_rdata_next[2:0] = muxed_v_09_mux_sel_qs; + end + + addr_hit[21]: begin + reg_rdata_next[0] = muxed_v_10_cfg_chip2pad_qs; + reg_rdata_next[1] = muxed_v_10_cfg_input_en_qs; + reg_rdata_next[2] = muxed_v_10_cfg_output_en_qs; + reg_rdata_next[3] = muxed_v_10_cfg_pull_en_qs; + reg_rdata_next[4] = muxed_v_10_cfg_pull_sel_qs; + end + + addr_hit[22]: begin + reg_rdata_next[2:0] = muxed_v_10_mux_sel_qs; + end + + addr_hit[23]: begin + reg_rdata_next[0] = muxed_v_11_cfg_chip2pad_qs; + reg_rdata_next[1] = muxed_v_11_cfg_input_en_qs; + reg_rdata_next[2] = muxed_v_11_cfg_output_en_qs; + reg_rdata_next[3] = muxed_v_11_cfg_pull_en_qs; + reg_rdata_next[4] = muxed_v_11_cfg_pull_sel_qs; + end + + addr_hit[24]: begin + reg_rdata_next[2:0] = muxed_v_11_mux_sel_qs; + end + + addr_hit[25]: begin + reg_rdata_next[0] = muxed_v_12_cfg_chip2pad_qs; + reg_rdata_next[1] = muxed_v_12_cfg_input_en_qs; + reg_rdata_next[2] = muxed_v_12_cfg_output_en_qs; + reg_rdata_next[3] = muxed_v_12_cfg_pull_en_qs; + reg_rdata_next[4] = muxed_v_12_cfg_pull_sel_qs; + end + + addr_hit[26]: begin + reg_rdata_next[2:0] = muxed_v_12_mux_sel_qs; + end + + addr_hit[27]: begin + reg_rdata_next[0] = muxed_v_13_cfg_chip2pad_qs; + reg_rdata_next[1] = muxed_v_13_cfg_input_en_qs; + reg_rdata_next[2] = muxed_v_13_cfg_output_en_qs; + reg_rdata_next[3] = muxed_v_13_cfg_pull_en_qs; + reg_rdata_next[4] = muxed_v_13_cfg_pull_sel_qs; + end + + addr_hit[28]: begin + reg_rdata_next[2:0] = muxed_v_13_mux_sel_qs; + end + + addr_hit[29]: begin + reg_rdata_next[0] = muxed_v_14_cfg_chip2pad_qs; + reg_rdata_next[1] = muxed_v_14_cfg_input_en_qs; + reg_rdata_next[2] = muxed_v_14_cfg_output_en_qs; + reg_rdata_next[3] = muxed_v_14_cfg_pull_en_qs; + reg_rdata_next[4] = muxed_v_14_cfg_pull_sel_qs; + end + + addr_hit[30]: begin + reg_rdata_next[2:0] = muxed_v_14_mux_sel_qs; + end + + addr_hit[31]: begin + reg_rdata_next[0] = muxed_v_15_cfg_chip2pad_qs; + reg_rdata_next[1] = muxed_v_15_cfg_input_en_qs; + reg_rdata_next[2] = muxed_v_15_cfg_output_en_qs; + reg_rdata_next[3] = muxed_v_15_cfg_pull_en_qs; + reg_rdata_next[4] = muxed_v_15_cfg_pull_sel_qs; + end + + addr_hit[32]: begin + reg_rdata_next[2:0] = muxed_v_15_mux_sel_qs; + end + + addr_hit[33]: begin + reg_rdata_next[0] = muxed_v_16_cfg_chip2pad_qs; + reg_rdata_next[1] = muxed_v_16_cfg_input_en_qs; + reg_rdata_next[2] = muxed_v_16_cfg_output_en_qs; + reg_rdata_next[3] = muxed_v_16_cfg_pull_en_qs; + reg_rdata_next[4] = muxed_v_16_cfg_pull_sel_qs; + end + + addr_hit[34]: begin + reg_rdata_next[2:0] = muxed_v_16_mux_sel_qs; + end + + addr_hit[35]: begin + reg_rdata_next[0] = muxed_v_17_cfg_chip2pad_qs; + reg_rdata_next[1] = muxed_v_17_cfg_input_en_qs; + reg_rdata_next[2] = muxed_v_17_cfg_output_en_qs; + reg_rdata_next[3] = muxed_v_17_cfg_pull_en_qs; + reg_rdata_next[4] = muxed_v_17_cfg_pull_sel_qs; + end + + addr_hit[36]: begin + reg_rdata_next[2:0] = muxed_v_17_mux_sel_qs; + end + + addr_hit[37]: begin + reg_rdata_next[0] = muxed_h_00_cfg_chip2pad_qs; + reg_rdata_next[1] = muxed_h_00_cfg_input_en_qs; + reg_rdata_next[2] = muxed_h_00_cfg_output_en_qs; + reg_rdata_next[3] = muxed_h_00_cfg_pull_en_qs; + reg_rdata_next[4] = muxed_h_00_cfg_pull_sel_qs; + end + + addr_hit[38]: begin + reg_rdata_next[2:0] = muxed_h_00_mux_sel_qs; + end + + addr_hit[39]: begin + reg_rdata_next[0] = muxed_h_01_cfg_chip2pad_qs; + reg_rdata_next[1] = muxed_h_01_cfg_input_en_qs; + reg_rdata_next[2] = muxed_h_01_cfg_output_en_qs; + reg_rdata_next[3] = muxed_h_01_cfg_pull_en_qs; + reg_rdata_next[4] = muxed_h_01_cfg_pull_sel_qs; + end + + addr_hit[40]: begin + reg_rdata_next[2:0] = muxed_h_01_mux_sel_qs; + end + + addr_hit[41]: begin + reg_rdata_next[0] = muxed_h_02_cfg_chip2pad_qs; + reg_rdata_next[1] = muxed_h_02_cfg_input_en_qs; + reg_rdata_next[2] = muxed_h_02_cfg_output_en_qs; + reg_rdata_next[3] = muxed_h_02_cfg_pull_en_qs; + reg_rdata_next[4] = muxed_h_02_cfg_pull_sel_qs; + end + + addr_hit[42]: begin + reg_rdata_next[2:0] = muxed_h_02_mux_sel_qs; + end + + addr_hit[43]: begin + reg_rdata_next[0] = muxed_h_03_cfg_chip2pad_qs; + reg_rdata_next[1] = muxed_h_03_cfg_input_en_qs; + reg_rdata_next[2] = muxed_h_03_cfg_output_en_qs; + reg_rdata_next[3] = muxed_h_03_cfg_pull_en_qs; + reg_rdata_next[4] = muxed_h_03_cfg_pull_sel_qs; + end + + addr_hit[44]: begin + reg_rdata_next[2:0] = muxed_h_03_mux_sel_qs; + end + + default: begin + reg_rdata_next = '1; + end + endcase + end + + // Unused signal tieoff + + // wdata / byte enable are not always fully used + // add a blanket unused statement to handle lint waivers + logic unused_wdata; + logic unused_be; + assign unused_wdata = ^reg_wdata; + assign unused_be = ^reg_be; + + // Assertions for Register Interface + `ASSERT(en2addrHit, (reg_we || reg_re) |-> $onehot0(addr_hit)) + +endmodule diff --git a/hw/padframe/astral_padframe/src/astral_padframe_periph_muxer.sv b/hw/padframe/astral_padframe/src/astral_padframe_periph_muxer.sv new file mode 100644 index 00000000..619eee34 --- /dev/null +++ b/hw/padframe/astral_padframe/src/astral_padframe_periph_muxer.sv @@ -0,0 +1,3128 @@ + +// File auto-generated by Padrick unknown +module astral_padframe_periph_muxer + import pkg_internal_astral_padframe_periph::*; + import pkg_astral_padframe::*; + import astral_padframe_periph_config_reg_pkg::*; +#( + parameter type req_t = logic, // reg_interface request type + parameter type resp_t = logic // reg_interface response type +) ( + input logic clk_i, + input logic rst_ni, + input pad_domain_periph_ports_soc2pad_t port_signals_soc2pad_i, + output pad_domain_periph_ports_pad2soc_t port_signals_pad2soc_o, + output mux_to_pads_t mux_to_pads_o, + input pads_to_mux_t pads_to_mux_i, + // Configuration interface using register_interface protocol + input req_t config_req_i, + output resp_t config_rsp_o +); + // Connections between register file and pads + astral_padframe_periph_config_reg2hw_t s_reg2hw; + + // Register File Instantiation + astral_padframe_periph_config_reg_top #( + .reg_req_t(req_t), + .reg_rsp_t(resp_t) + ) i_regfile ( + .clk_i, + .rst_ni, + .reg2hw(s_reg2hw), + .reg_req_i(config_req_i), + .reg_rsp_o(config_rsp_o), + .devmode_i(1'b1) + ); + + + // SoC -> Pad Multiplex Logic + // Pad muxed_v_00 + always_comb begin + unique case (s_reg2hw.muxed_v_00_mux_sel.q) + PAD_MUX_GROUP_MUXED_V_00_SEL_DEFAULT: begin + mux_to_pads_o.muxed_v_00.chip2pad = s_reg2hw.muxed_v_00_cfg.chip2pad.q; + mux_to_pads_o.muxed_v_00.input_en = s_reg2hw.muxed_v_00_cfg.input_en.q; + mux_to_pads_o.muxed_v_00.output_en = s_reg2hw.muxed_v_00_cfg.output_en.q; + mux_to_pads_o.muxed_v_00.pull_en = s_reg2hw.muxed_v_00_cfg.pull_en.q; + mux_to_pads_o.muxed_v_00.pull_sel = s_reg2hw.muxed_v_00_cfg.pull_sel.q; + end + PAD_MUX_GROUP_MUXED_V_00_SEL_SPI_SCK: begin + mux_to_pads_o.muxed_v_00.chip2pad = port_signals_soc2pad_i.spi.spih_sck_o; + mux_to_pads_o.muxed_v_00.input_en = 1'b0; + mux_to_pads_o.muxed_v_00.output_en = 1'b1; + mux_to_pads_o.muxed_v_00.pull_en = s_reg2hw.muxed_v_00_cfg.pull_en.q; + mux_to_pads_o.muxed_v_00.pull_sel = s_reg2hw.muxed_v_00_cfg.pull_sel.q; + end + PAD_MUX_GROUP_MUXED_V_00_SEL_CAN_RX: begin + mux_to_pads_o.muxed_v_00.chip2pad = s_reg2hw.muxed_v_00_cfg.chip2pad.q; + mux_to_pads_o.muxed_v_00.input_en = 1'b1; + mux_to_pads_o.muxed_v_00.output_en = 1'b0; + mux_to_pads_o.muxed_v_00.pull_en = s_reg2hw.muxed_v_00_cfg.pull_en.q; + mux_to_pads_o.muxed_v_00.pull_sel = s_reg2hw.muxed_v_00_cfg.pull_sel.q; + end + PAD_MUX_GROUP_MUXED_V_00_SEL_I2C_SDA: begin + mux_to_pads_o.muxed_v_00.chip2pad = port_signals_soc2pad_i.i2c.i2c_sda_o; + mux_to_pads_o.muxed_v_00.input_en = ~port_signals_soc2pad_i.i2c.i2c_sda_oen_i; + mux_to_pads_o.muxed_v_00.output_en = port_signals_soc2pad_i.i2c.i2c_sda_oen_i; + mux_to_pads_o.muxed_v_00.pull_en = s_reg2hw.muxed_v_00_cfg.pull_en.q; + mux_to_pads_o.muxed_v_00.pull_sel = s_reg2hw.muxed_v_00_cfg.pull_sel.q; + end + PAD_MUX_GROUP_MUXED_V_00_SEL_SPI_OT_SCK: begin + mux_to_pads_o.muxed_v_00.chip2pad = port_signals_soc2pad_i.spi_ot.spih_ot_sck_o; + mux_to_pads_o.muxed_v_00.input_en = 1'b0; + mux_to_pads_o.muxed_v_00.output_en = 1'b1; + mux_to_pads_o.muxed_v_00.pull_en = s_reg2hw.muxed_v_00_cfg.pull_en.q; + mux_to_pads_o.muxed_v_00.pull_sel = s_reg2hw.muxed_v_00_cfg.pull_sel.q; + end + PAD_MUX_GROUP_MUXED_V_00_SEL_GPIO_IO_V_0: begin + mux_to_pads_o.muxed_v_00.chip2pad = port_signals_soc2pad_i.gpio.gpio_v_0_o; + mux_to_pads_o.muxed_v_00.input_en = ~port_signals_soc2pad_i.gpio.gpio_v_0_oen_i; + mux_to_pads_o.muxed_v_00.output_en = port_signals_soc2pad_i.gpio.gpio_v_0_oen_i; + mux_to_pads_o.muxed_v_00.pull_en = s_reg2hw.muxed_v_00_cfg.pull_en.q; + mux_to_pads_o.muxed_v_00.pull_sel = s_reg2hw.muxed_v_00_cfg.pull_sel.q; + end + default: begin + mux_to_pads_o.muxed_v_00.chip2pad = s_reg2hw.muxed_v_00_cfg.chip2pad.q; + mux_to_pads_o.muxed_v_00.input_en = s_reg2hw.muxed_v_00_cfg.input_en.q; + mux_to_pads_o.muxed_v_00.output_en = s_reg2hw.muxed_v_00_cfg.output_en.q; + mux_to_pads_o.muxed_v_00.pull_en = s_reg2hw.muxed_v_00_cfg.pull_en.q; + mux_to_pads_o.muxed_v_00.pull_sel = s_reg2hw.muxed_v_00_cfg.pull_sel.q; + end + endcase + end // always_comb + + // Pad muxed_v_01 + always_comb begin + unique case (s_reg2hw.muxed_v_01_mux_sel.q) + PAD_MUX_GROUP_MUXED_V_01_SEL_DEFAULT: begin + mux_to_pads_o.muxed_v_01.chip2pad = s_reg2hw.muxed_v_01_cfg.chip2pad.q; + mux_to_pads_o.muxed_v_01.input_en = s_reg2hw.muxed_v_01_cfg.input_en.q; + mux_to_pads_o.muxed_v_01.output_en = s_reg2hw.muxed_v_01_cfg.output_en.q; + mux_to_pads_o.muxed_v_01.pull_en = s_reg2hw.muxed_v_01_cfg.pull_en.q; + mux_to_pads_o.muxed_v_01.pull_sel = s_reg2hw.muxed_v_01_cfg.pull_sel.q; + end + PAD_MUX_GROUP_MUXED_V_01_SEL_SPI_CSB_0: begin + mux_to_pads_o.muxed_v_01.chip2pad = port_signals_soc2pad_i.spi.spih_csb_0_o; + mux_to_pads_o.muxed_v_01.input_en = 1'b0; + mux_to_pads_o.muxed_v_01.output_en = 1'b1; + mux_to_pads_o.muxed_v_01.pull_en = s_reg2hw.muxed_v_01_cfg.pull_en.q; + mux_to_pads_o.muxed_v_01.pull_sel = s_reg2hw.muxed_v_01_cfg.pull_sel.q; + end + PAD_MUX_GROUP_MUXED_V_01_SEL_CAN_TX: begin + mux_to_pads_o.muxed_v_01.chip2pad = port_signals_soc2pad_i.can.can_tx_o; + mux_to_pads_o.muxed_v_01.input_en = 1'b0; + mux_to_pads_o.muxed_v_01.output_en = 1'b1; + mux_to_pads_o.muxed_v_01.pull_en = s_reg2hw.muxed_v_01_cfg.pull_en.q; + mux_to_pads_o.muxed_v_01.pull_sel = s_reg2hw.muxed_v_01_cfg.pull_sel.q; + end + PAD_MUX_GROUP_MUXED_V_01_SEL_I2C_SCL: begin + mux_to_pads_o.muxed_v_01.chip2pad = port_signals_soc2pad_i.i2c.i2c_scl_o; + mux_to_pads_o.muxed_v_01.input_en = ~port_signals_soc2pad_i.i2c.i2c_scl_oen_i; + mux_to_pads_o.muxed_v_01.output_en = port_signals_soc2pad_i.i2c.i2c_scl_oen_i; + mux_to_pads_o.muxed_v_01.pull_en = s_reg2hw.muxed_v_01_cfg.pull_en.q; + mux_to_pads_o.muxed_v_01.pull_sel = s_reg2hw.muxed_v_01_cfg.pull_sel.q; + end + PAD_MUX_GROUP_MUXED_V_01_SEL_SPI_OT_CSB: begin + mux_to_pads_o.muxed_v_01.chip2pad = port_signals_soc2pad_i.spi_ot.spih_ot_csb_o; + mux_to_pads_o.muxed_v_01.input_en = 1'b0; + mux_to_pads_o.muxed_v_01.output_en = 1'b1; + mux_to_pads_o.muxed_v_01.pull_en = s_reg2hw.muxed_v_01_cfg.pull_en.q; + mux_to_pads_o.muxed_v_01.pull_sel = s_reg2hw.muxed_v_01_cfg.pull_sel.q; + end + PAD_MUX_GROUP_MUXED_V_01_SEL_GPIO_IO_V_1: begin + mux_to_pads_o.muxed_v_01.chip2pad = port_signals_soc2pad_i.gpio.gpio_v_1_o; + mux_to_pads_o.muxed_v_01.input_en = ~port_signals_soc2pad_i.gpio.gpio_v_1_oen_i; + mux_to_pads_o.muxed_v_01.output_en = port_signals_soc2pad_i.gpio.gpio_v_1_oen_i; + mux_to_pads_o.muxed_v_01.pull_en = s_reg2hw.muxed_v_01_cfg.pull_en.q; + mux_to_pads_o.muxed_v_01.pull_sel = s_reg2hw.muxed_v_01_cfg.pull_sel.q; + end + default: begin + mux_to_pads_o.muxed_v_01.chip2pad = s_reg2hw.muxed_v_01_cfg.chip2pad.q; + mux_to_pads_o.muxed_v_01.input_en = s_reg2hw.muxed_v_01_cfg.input_en.q; + mux_to_pads_o.muxed_v_01.output_en = s_reg2hw.muxed_v_01_cfg.output_en.q; + mux_to_pads_o.muxed_v_01.pull_en = s_reg2hw.muxed_v_01_cfg.pull_en.q; + mux_to_pads_o.muxed_v_01.pull_sel = s_reg2hw.muxed_v_01_cfg.pull_sel.q; + end + endcase + end // always_comb + + // Pad muxed_v_02 + always_comb begin + unique case (s_reg2hw.muxed_v_02_mux_sel.q) + PAD_MUX_GROUP_MUXED_V_02_SEL_DEFAULT: begin + mux_to_pads_o.muxed_v_02.chip2pad = s_reg2hw.muxed_v_02_cfg.chip2pad.q; + mux_to_pads_o.muxed_v_02.input_en = s_reg2hw.muxed_v_02_cfg.input_en.q; + mux_to_pads_o.muxed_v_02.output_en = s_reg2hw.muxed_v_02_cfg.output_en.q; + mux_to_pads_o.muxed_v_02.pull_en = s_reg2hw.muxed_v_02_cfg.pull_en.q; + mux_to_pads_o.muxed_v_02.pull_sel = s_reg2hw.muxed_v_02_cfg.pull_sel.q; + end + PAD_MUX_GROUP_MUXED_V_02_SEL_SPI_CSB_1: begin + mux_to_pads_o.muxed_v_02.chip2pad = port_signals_soc2pad_i.spi.spih_csb_1_o; + mux_to_pads_o.muxed_v_02.input_en = 1'b0; + mux_to_pads_o.muxed_v_02.output_en = 1'b1; + mux_to_pads_o.muxed_v_02.pull_en = s_reg2hw.muxed_v_02_cfg.pull_en.q; + mux_to_pads_o.muxed_v_02.pull_sel = s_reg2hw.muxed_v_02_cfg.pull_sel.q; + end + PAD_MUX_GROUP_MUXED_V_02_SEL_SPI_OT_SD_0: begin + mux_to_pads_o.muxed_v_02.chip2pad = port_signals_soc2pad_i.spi_ot.spih_ot_sd_0_o; + mux_to_pads_o.muxed_v_02.input_en = ~port_signals_soc2pad_i.spi_ot.spih_ot_sd_0_oen_i; + mux_to_pads_o.muxed_v_02.output_en = port_signals_soc2pad_i.spi_ot.spih_ot_sd_0_oen_i; + mux_to_pads_o.muxed_v_02.pull_en = s_reg2hw.muxed_v_02_cfg.pull_en.q; + mux_to_pads_o.muxed_v_02.pull_sel = s_reg2hw.muxed_v_02_cfg.pull_sel.q; + end + PAD_MUX_GROUP_MUXED_V_02_SEL_GPIO_IO_V_2: begin + mux_to_pads_o.muxed_v_02.chip2pad = port_signals_soc2pad_i.gpio.gpio_v_2_o; + mux_to_pads_o.muxed_v_02.input_en = ~port_signals_soc2pad_i.gpio.gpio_v_2_oen_i; + mux_to_pads_o.muxed_v_02.output_en = port_signals_soc2pad_i.gpio.gpio_v_2_oen_i; + mux_to_pads_o.muxed_v_02.pull_en = s_reg2hw.muxed_v_02_cfg.pull_en.q; + mux_to_pads_o.muxed_v_02.pull_sel = s_reg2hw.muxed_v_02_cfg.pull_sel.q; + end + default: begin + mux_to_pads_o.muxed_v_02.chip2pad = s_reg2hw.muxed_v_02_cfg.chip2pad.q; + mux_to_pads_o.muxed_v_02.input_en = s_reg2hw.muxed_v_02_cfg.input_en.q; + mux_to_pads_o.muxed_v_02.output_en = s_reg2hw.muxed_v_02_cfg.output_en.q; + mux_to_pads_o.muxed_v_02.pull_en = s_reg2hw.muxed_v_02_cfg.pull_en.q; + mux_to_pads_o.muxed_v_02.pull_sel = s_reg2hw.muxed_v_02_cfg.pull_sel.q; + end + endcase + end // always_comb + + // Pad muxed_v_03 + always_comb begin + unique case (s_reg2hw.muxed_v_03_mux_sel.q) + PAD_MUX_GROUP_MUXED_V_03_SEL_DEFAULT: begin + mux_to_pads_o.muxed_v_03.chip2pad = s_reg2hw.muxed_v_03_cfg.chip2pad.q; + mux_to_pads_o.muxed_v_03.input_en = s_reg2hw.muxed_v_03_cfg.input_en.q; + mux_to_pads_o.muxed_v_03.output_en = s_reg2hw.muxed_v_03_cfg.output_en.q; + mux_to_pads_o.muxed_v_03.pull_en = s_reg2hw.muxed_v_03_cfg.pull_en.q; + mux_to_pads_o.muxed_v_03.pull_sel = s_reg2hw.muxed_v_03_cfg.pull_sel.q; + end + PAD_MUX_GROUP_MUXED_V_03_SEL_SPI_SD_0: begin + mux_to_pads_o.muxed_v_03.chip2pad = port_signals_soc2pad_i.spi.spih_sd_0_o; + mux_to_pads_o.muxed_v_03.input_en = ~port_signals_soc2pad_i.spi.spih_sd_0_oen_i; + mux_to_pads_o.muxed_v_03.output_en = port_signals_soc2pad_i.spi.spih_sd_0_oen_i; + mux_to_pads_o.muxed_v_03.pull_en = s_reg2hw.muxed_v_03_cfg.pull_en.q; + mux_to_pads_o.muxed_v_03.pull_sel = s_reg2hw.muxed_v_03_cfg.pull_sel.q; + end + PAD_MUX_GROUP_MUXED_V_03_SEL_SPI_OT_SD_1: begin + mux_to_pads_o.muxed_v_03.chip2pad = port_signals_soc2pad_i.spi_ot.spih_ot_sd_1_o; + mux_to_pads_o.muxed_v_03.input_en = ~port_signals_soc2pad_i.spi_ot.spih_ot_sd_1_oen_i; + mux_to_pads_o.muxed_v_03.output_en = port_signals_soc2pad_i.spi_ot.spih_ot_sd_1_oen_i; + mux_to_pads_o.muxed_v_03.pull_en = s_reg2hw.muxed_v_03_cfg.pull_en.q; + mux_to_pads_o.muxed_v_03.pull_sel = s_reg2hw.muxed_v_03_cfg.pull_sel.q; + end + PAD_MUX_GROUP_MUXED_V_03_SEL_GPIO_IO_V_3: begin + mux_to_pads_o.muxed_v_03.chip2pad = port_signals_soc2pad_i.gpio.gpio_v_3_o; + mux_to_pads_o.muxed_v_03.input_en = ~port_signals_soc2pad_i.gpio.gpio_v_3_oen_i; + mux_to_pads_o.muxed_v_03.output_en = port_signals_soc2pad_i.gpio.gpio_v_3_oen_i; + mux_to_pads_o.muxed_v_03.pull_en = s_reg2hw.muxed_v_03_cfg.pull_en.q; + mux_to_pads_o.muxed_v_03.pull_sel = s_reg2hw.muxed_v_03_cfg.pull_sel.q; + end + default: begin + mux_to_pads_o.muxed_v_03.chip2pad = s_reg2hw.muxed_v_03_cfg.chip2pad.q; + mux_to_pads_o.muxed_v_03.input_en = s_reg2hw.muxed_v_03_cfg.input_en.q; + mux_to_pads_o.muxed_v_03.output_en = s_reg2hw.muxed_v_03_cfg.output_en.q; + mux_to_pads_o.muxed_v_03.pull_en = s_reg2hw.muxed_v_03_cfg.pull_en.q; + mux_to_pads_o.muxed_v_03.pull_sel = s_reg2hw.muxed_v_03_cfg.pull_sel.q; + end + endcase + end // always_comb + + // Pad muxed_v_04 + always_comb begin + unique case (s_reg2hw.muxed_v_04_mux_sel.q) + PAD_MUX_GROUP_MUXED_V_04_SEL_DEFAULT: begin + mux_to_pads_o.muxed_v_04.chip2pad = s_reg2hw.muxed_v_04_cfg.chip2pad.q; + mux_to_pads_o.muxed_v_04.input_en = s_reg2hw.muxed_v_04_cfg.input_en.q; + mux_to_pads_o.muxed_v_04.output_en = s_reg2hw.muxed_v_04_cfg.output_en.q; + mux_to_pads_o.muxed_v_04.pull_en = s_reg2hw.muxed_v_04_cfg.pull_en.q; + mux_to_pads_o.muxed_v_04.pull_sel = s_reg2hw.muxed_v_04_cfg.pull_sel.q; + end + PAD_MUX_GROUP_MUXED_V_04_SEL_SPI_SD_1: begin + mux_to_pads_o.muxed_v_04.chip2pad = port_signals_soc2pad_i.spi.spih_sd_1_o; + mux_to_pads_o.muxed_v_04.input_en = ~port_signals_soc2pad_i.spi.spih_sd_1_oen_i; + mux_to_pads_o.muxed_v_04.output_en = port_signals_soc2pad_i.spi.spih_sd_1_oen_i; + mux_to_pads_o.muxed_v_04.pull_en = s_reg2hw.muxed_v_04_cfg.pull_en.q; + mux_to_pads_o.muxed_v_04.pull_sel = s_reg2hw.muxed_v_04_cfg.pull_sel.q; + end + PAD_MUX_GROUP_MUXED_V_04_SEL_SERIAL_LINK_RCV_CLK_I: begin + mux_to_pads_o.muxed_v_04.chip2pad = s_reg2hw.muxed_v_04_cfg.chip2pad.q; + mux_to_pads_o.muxed_v_04.input_en = 1'b1; + mux_to_pads_o.muxed_v_04.output_en = 1'b0; + mux_to_pads_o.muxed_v_04.pull_en = s_reg2hw.muxed_v_04_cfg.pull_en.q; + mux_to_pads_o.muxed_v_04.pull_sel = s_reg2hw.muxed_v_04_cfg.pull_sel.q; + end + PAD_MUX_GROUP_MUXED_V_04_SEL_SPI_OT_SD_2: begin + mux_to_pads_o.muxed_v_04.chip2pad = port_signals_soc2pad_i.spi_ot.spih_ot_sd_2_o; + mux_to_pads_o.muxed_v_04.input_en = ~port_signals_soc2pad_i.spi_ot.spih_ot_sd_2_oen_i; + mux_to_pads_o.muxed_v_04.output_en = port_signals_soc2pad_i.spi_ot.spih_ot_sd_2_oen_i; + mux_to_pads_o.muxed_v_04.pull_en = s_reg2hw.muxed_v_04_cfg.pull_en.q; + mux_to_pads_o.muxed_v_04.pull_sel = s_reg2hw.muxed_v_04_cfg.pull_sel.q; + end + PAD_MUX_GROUP_MUXED_V_04_SEL_GPIO_IO_V_4: begin + mux_to_pads_o.muxed_v_04.chip2pad = port_signals_soc2pad_i.gpio.gpio_v_4_o; + mux_to_pads_o.muxed_v_04.input_en = ~port_signals_soc2pad_i.gpio.gpio_v_4_oen_i; + mux_to_pads_o.muxed_v_04.output_en = port_signals_soc2pad_i.gpio.gpio_v_4_oen_i; + mux_to_pads_o.muxed_v_04.pull_en = s_reg2hw.muxed_v_04_cfg.pull_en.q; + mux_to_pads_o.muxed_v_04.pull_sel = s_reg2hw.muxed_v_04_cfg.pull_sel.q; + end + default: begin + mux_to_pads_o.muxed_v_04.chip2pad = s_reg2hw.muxed_v_04_cfg.chip2pad.q; + mux_to_pads_o.muxed_v_04.input_en = s_reg2hw.muxed_v_04_cfg.input_en.q; + mux_to_pads_o.muxed_v_04.output_en = s_reg2hw.muxed_v_04_cfg.output_en.q; + mux_to_pads_o.muxed_v_04.pull_en = s_reg2hw.muxed_v_04_cfg.pull_en.q; + mux_to_pads_o.muxed_v_04.pull_sel = s_reg2hw.muxed_v_04_cfg.pull_sel.q; + end + endcase + end // always_comb + + // Pad muxed_v_05 + always_comb begin + unique case (s_reg2hw.muxed_v_05_mux_sel.q) + PAD_MUX_GROUP_MUXED_V_05_SEL_DEFAULT: begin + mux_to_pads_o.muxed_v_05.chip2pad = s_reg2hw.muxed_v_05_cfg.chip2pad.q; + mux_to_pads_o.muxed_v_05.input_en = s_reg2hw.muxed_v_05_cfg.input_en.q; + mux_to_pads_o.muxed_v_05.output_en = s_reg2hw.muxed_v_05_cfg.output_en.q; + mux_to_pads_o.muxed_v_05.pull_en = s_reg2hw.muxed_v_05_cfg.pull_en.q; + mux_to_pads_o.muxed_v_05.pull_sel = s_reg2hw.muxed_v_05_cfg.pull_sel.q; + end + PAD_MUX_GROUP_MUXED_V_05_SEL_SPI_SD_2: begin + mux_to_pads_o.muxed_v_05.chip2pad = port_signals_soc2pad_i.spi.spih_sd_2_o; + mux_to_pads_o.muxed_v_05.input_en = ~port_signals_soc2pad_i.spi.spih_sd_2_oen_i; + mux_to_pads_o.muxed_v_05.output_en = port_signals_soc2pad_i.spi.spih_sd_2_oen_i; + mux_to_pads_o.muxed_v_05.pull_en = s_reg2hw.muxed_v_05_cfg.pull_en.q; + mux_to_pads_o.muxed_v_05.pull_sel = s_reg2hw.muxed_v_05_cfg.pull_sel.q; + end + PAD_MUX_GROUP_MUXED_V_05_SEL_SERIAL_LINK_I_0: begin + mux_to_pads_o.muxed_v_05.chip2pad = s_reg2hw.muxed_v_05_cfg.chip2pad.q; + mux_to_pads_o.muxed_v_05.input_en = 1'b1; + mux_to_pads_o.muxed_v_05.output_en = 1'b0; + mux_to_pads_o.muxed_v_05.pull_en = s_reg2hw.muxed_v_05_cfg.pull_en.q; + mux_to_pads_o.muxed_v_05.pull_sel = s_reg2hw.muxed_v_05_cfg.pull_sel.q; + end + PAD_MUX_GROUP_MUXED_V_05_SEL_SPI_OT_SD_3: begin + mux_to_pads_o.muxed_v_05.chip2pad = port_signals_soc2pad_i.spi_ot.spih_ot_sd_3_o; + mux_to_pads_o.muxed_v_05.input_en = ~port_signals_soc2pad_i.spi_ot.spih_ot_sd_3_oen_i; + mux_to_pads_o.muxed_v_05.output_en = port_signals_soc2pad_i.spi_ot.spih_ot_sd_3_oen_i; + mux_to_pads_o.muxed_v_05.pull_en = s_reg2hw.muxed_v_05_cfg.pull_en.q; + mux_to_pads_o.muxed_v_05.pull_sel = s_reg2hw.muxed_v_05_cfg.pull_sel.q; + end + PAD_MUX_GROUP_MUXED_V_05_SEL_GPIO_IO_V_5: begin + mux_to_pads_o.muxed_v_05.chip2pad = port_signals_soc2pad_i.gpio.gpio_v_5_o; + mux_to_pads_o.muxed_v_05.input_en = ~port_signals_soc2pad_i.gpio.gpio_v_5_oen_i; + mux_to_pads_o.muxed_v_05.output_en = port_signals_soc2pad_i.gpio.gpio_v_5_oen_i; + mux_to_pads_o.muxed_v_05.pull_en = s_reg2hw.muxed_v_05_cfg.pull_en.q; + mux_to_pads_o.muxed_v_05.pull_sel = s_reg2hw.muxed_v_05_cfg.pull_sel.q; + end + default: begin + mux_to_pads_o.muxed_v_05.chip2pad = s_reg2hw.muxed_v_05_cfg.chip2pad.q; + mux_to_pads_o.muxed_v_05.input_en = s_reg2hw.muxed_v_05_cfg.input_en.q; + mux_to_pads_o.muxed_v_05.output_en = s_reg2hw.muxed_v_05_cfg.output_en.q; + mux_to_pads_o.muxed_v_05.pull_en = s_reg2hw.muxed_v_05_cfg.pull_en.q; + mux_to_pads_o.muxed_v_05.pull_sel = s_reg2hw.muxed_v_05_cfg.pull_sel.q; + end + endcase + end // always_comb + + // Pad muxed_v_06 + always_comb begin + unique case (s_reg2hw.muxed_v_06_mux_sel.q) + PAD_MUX_GROUP_MUXED_V_06_SEL_DEFAULT: begin + mux_to_pads_o.muxed_v_06.chip2pad = s_reg2hw.muxed_v_06_cfg.chip2pad.q; + mux_to_pads_o.muxed_v_06.input_en = s_reg2hw.muxed_v_06_cfg.input_en.q; + mux_to_pads_o.muxed_v_06.output_en = s_reg2hw.muxed_v_06_cfg.output_en.q; + mux_to_pads_o.muxed_v_06.pull_en = s_reg2hw.muxed_v_06_cfg.pull_en.q; + mux_to_pads_o.muxed_v_06.pull_sel = s_reg2hw.muxed_v_06_cfg.pull_sel.q; + end + PAD_MUX_GROUP_MUXED_V_06_SEL_SPI_SD_3: begin + mux_to_pads_o.muxed_v_06.chip2pad = port_signals_soc2pad_i.spi.spih_sd_3_o; + mux_to_pads_o.muxed_v_06.input_en = ~port_signals_soc2pad_i.spi.spih_sd_3_oen_i; + mux_to_pads_o.muxed_v_06.output_en = port_signals_soc2pad_i.spi.spih_sd_3_oen_i; + mux_to_pads_o.muxed_v_06.pull_en = s_reg2hw.muxed_v_06_cfg.pull_en.q; + mux_to_pads_o.muxed_v_06.pull_sel = s_reg2hw.muxed_v_06_cfg.pull_sel.q; + end + PAD_MUX_GROUP_MUXED_V_06_SEL_SERIAL_LINK_I_1: begin + mux_to_pads_o.muxed_v_06.chip2pad = s_reg2hw.muxed_v_06_cfg.chip2pad.q; + mux_to_pads_o.muxed_v_06.input_en = 1'b1; + mux_to_pads_o.muxed_v_06.output_en = 1'b0; + mux_to_pads_o.muxed_v_06.pull_en = s_reg2hw.muxed_v_06_cfg.pull_en.q; + mux_to_pads_o.muxed_v_06.pull_sel = s_reg2hw.muxed_v_06_cfg.pull_sel.q; + end + PAD_MUX_GROUP_MUXED_V_06_SEL_GPIO_IO_V_6: begin + mux_to_pads_o.muxed_v_06.chip2pad = port_signals_soc2pad_i.gpio.gpio_v_6_o; + mux_to_pads_o.muxed_v_06.input_en = ~port_signals_soc2pad_i.gpio.gpio_v_6_oen_i; + mux_to_pads_o.muxed_v_06.output_en = port_signals_soc2pad_i.gpio.gpio_v_6_oen_i; + mux_to_pads_o.muxed_v_06.pull_en = s_reg2hw.muxed_v_06_cfg.pull_en.q; + mux_to_pads_o.muxed_v_06.pull_sel = s_reg2hw.muxed_v_06_cfg.pull_sel.q; + end + default: begin + mux_to_pads_o.muxed_v_06.chip2pad = s_reg2hw.muxed_v_06_cfg.chip2pad.q; + mux_to_pads_o.muxed_v_06.input_en = s_reg2hw.muxed_v_06_cfg.input_en.q; + mux_to_pads_o.muxed_v_06.output_en = s_reg2hw.muxed_v_06_cfg.output_en.q; + mux_to_pads_o.muxed_v_06.pull_en = s_reg2hw.muxed_v_06_cfg.pull_en.q; + mux_to_pads_o.muxed_v_06.pull_sel = s_reg2hw.muxed_v_06_cfg.pull_sel.q; + end + endcase + end // always_comb + + // Pad muxed_v_07 + always_comb begin + unique case (s_reg2hw.muxed_v_07_mux_sel.q) + PAD_MUX_GROUP_MUXED_V_07_SEL_DEFAULT: begin + mux_to_pads_o.muxed_v_07.chip2pad = s_reg2hw.muxed_v_07_cfg.chip2pad.q; + mux_to_pads_o.muxed_v_07.input_en = s_reg2hw.muxed_v_07_cfg.input_en.q; + mux_to_pads_o.muxed_v_07.output_en = s_reg2hw.muxed_v_07_cfg.output_en.q; + mux_to_pads_o.muxed_v_07.pull_en = s_reg2hw.muxed_v_07_cfg.pull_en.q; + mux_to_pads_o.muxed_v_07.pull_sel = s_reg2hw.muxed_v_07_cfg.pull_sel.q; + end + PAD_MUX_GROUP_MUXED_V_07_SEL_ETHERNET_RXCK: begin + mux_to_pads_o.muxed_v_07.chip2pad = s_reg2hw.muxed_v_07_cfg.chip2pad.q; + mux_to_pads_o.muxed_v_07.input_en = 1'b1; + mux_to_pads_o.muxed_v_07.output_en = 1'b0; + mux_to_pads_o.muxed_v_07.pull_en = s_reg2hw.muxed_v_07_cfg.pull_en.q; + mux_to_pads_o.muxed_v_07.pull_sel = s_reg2hw.muxed_v_07_cfg.pull_sel.q; + end + PAD_MUX_GROUP_MUXED_V_07_SEL_SERIAL_LINK_I_2: begin + mux_to_pads_o.muxed_v_07.chip2pad = s_reg2hw.muxed_v_07_cfg.chip2pad.q; + mux_to_pads_o.muxed_v_07.input_en = 1'b1; + mux_to_pads_o.muxed_v_07.output_en = 1'b0; + mux_to_pads_o.muxed_v_07.pull_en = s_reg2hw.muxed_v_07_cfg.pull_en.q; + mux_to_pads_o.muxed_v_07.pull_sel = s_reg2hw.muxed_v_07_cfg.pull_sel.q; + end + PAD_MUX_GROUP_MUXED_V_07_SEL_TC_ACTIVE: begin + mux_to_pads_o.muxed_v_07.chip2pad = s_reg2hw.muxed_v_07_cfg.chip2pad.q; + mux_to_pads_o.muxed_v_07.input_en = 1'b1; + mux_to_pads_o.muxed_v_07.output_en = 1'b0; + mux_to_pads_o.muxed_v_07.pull_en = s_reg2hw.muxed_v_07_cfg.pull_en.q; + mux_to_pads_o.muxed_v_07.pull_sel = s_reg2hw.muxed_v_07_cfg.pull_sel.q; + end + PAD_MUX_GROUP_MUXED_V_07_SEL_PLL_IO_0: begin + mux_to_pads_o.muxed_v_07.chip2pad = port_signals_soc2pad_i.pll.pll_0_o; + mux_to_pads_o.muxed_v_07.input_en = ~port_signals_soc2pad_i.pll.pll_0_oen_i; + mux_to_pads_o.muxed_v_07.output_en = port_signals_soc2pad_i.pll.pll_0_oen_i; + mux_to_pads_o.muxed_v_07.pull_en = s_reg2hw.muxed_v_07_cfg.pull_en.q; + mux_to_pads_o.muxed_v_07.pull_sel = s_reg2hw.muxed_v_07_cfg.pull_sel.q; + end + PAD_MUX_GROUP_MUXED_V_07_SEL_GPIO_IO_V_7: begin + mux_to_pads_o.muxed_v_07.chip2pad = port_signals_soc2pad_i.gpio.gpio_v_7_o; + mux_to_pads_o.muxed_v_07.input_en = ~port_signals_soc2pad_i.gpio.gpio_v_7_oen_i; + mux_to_pads_o.muxed_v_07.output_en = port_signals_soc2pad_i.gpio.gpio_v_7_oen_i; + mux_to_pads_o.muxed_v_07.pull_en = s_reg2hw.muxed_v_07_cfg.pull_en.q; + mux_to_pads_o.muxed_v_07.pull_sel = s_reg2hw.muxed_v_07_cfg.pull_sel.q; + end + default: begin + mux_to_pads_o.muxed_v_07.chip2pad = s_reg2hw.muxed_v_07_cfg.chip2pad.q; + mux_to_pads_o.muxed_v_07.input_en = s_reg2hw.muxed_v_07_cfg.input_en.q; + mux_to_pads_o.muxed_v_07.output_en = s_reg2hw.muxed_v_07_cfg.output_en.q; + mux_to_pads_o.muxed_v_07.pull_en = s_reg2hw.muxed_v_07_cfg.pull_en.q; + mux_to_pads_o.muxed_v_07.pull_sel = s_reg2hw.muxed_v_07_cfg.pull_sel.q; + end + endcase + end // always_comb + + // Pad muxed_v_08 + always_comb begin + unique case (s_reg2hw.muxed_v_08_mux_sel.q) + PAD_MUX_GROUP_MUXED_V_08_SEL_DEFAULT: begin + mux_to_pads_o.muxed_v_08.chip2pad = s_reg2hw.muxed_v_08_cfg.chip2pad.q; + mux_to_pads_o.muxed_v_08.input_en = s_reg2hw.muxed_v_08_cfg.input_en.q; + mux_to_pads_o.muxed_v_08.output_en = s_reg2hw.muxed_v_08_cfg.output_en.q; + mux_to_pads_o.muxed_v_08.pull_en = s_reg2hw.muxed_v_08_cfg.pull_en.q; + mux_to_pads_o.muxed_v_08.pull_sel = s_reg2hw.muxed_v_08_cfg.pull_sel.q; + end + PAD_MUX_GROUP_MUXED_V_08_SEL_ETHERNET_RXCTL: begin + mux_to_pads_o.muxed_v_08.chip2pad = s_reg2hw.muxed_v_08_cfg.chip2pad.q; + mux_to_pads_o.muxed_v_08.input_en = 1'b1; + mux_to_pads_o.muxed_v_08.output_en = 1'b0; + mux_to_pads_o.muxed_v_08.pull_en = s_reg2hw.muxed_v_08_cfg.pull_en.q; + mux_to_pads_o.muxed_v_08.pull_sel = s_reg2hw.muxed_v_08_cfg.pull_sel.q; + end + PAD_MUX_GROUP_MUXED_V_08_SEL_SERIAL_LINK_I_3: begin + mux_to_pads_o.muxed_v_08.chip2pad = s_reg2hw.muxed_v_08_cfg.chip2pad.q; + mux_to_pads_o.muxed_v_08.input_en = 1'b1; + mux_to_pads_o.muxed_v_08.output_en = 1'b0; + mux_to_pads_o.muxed_v_08.pull_en = s_reg2hw.muxed_v_08_cfg.pull_en.q; + mux_to_pads_o.muxed_v_08.pull_sel = s_reg2hw.muxed_v_08_cfg.pull_sel.q; + end + PAD_MUX_GROUP_MUXED_V_08_SEL_TC_CLK: begin + mux_to_pads_o.muxed_v_08.chip2pad = s_reg2hw.muxed_v_08_cfg.chip2pad.q; + mux_to_pads_o.muxed_v_08.input_en = 1'b1; + mux_to_pads_o.muxed_v_08.output_en = 1'b0; + mux_to_pads_o.muxed_v_08.pull_en = s_reg2hw.muxed_v_08_cfg.pull_en.q; + mux_to_pads_o.muxed_v_08.pull_sel = s_reg2hw.muxed_v_08_cfg.pull_sel.q; + end + PAD_MUX_GROUP_MUXED_V_08_SEL_PLL_IO_1: begin + mux_to_pads_o.muxed_v_08.chip2pad = port_signals_soc2pad_i.pll.pll_1_o; + mux_to_pads_o.muxed_v_08.input_en = ~port_signals_soc2pad_i.pll.pll_1_oen_i; + mux_to_pads_o.muxed_v_08.output_en = port_signals_soc2pad_i.pll.pll_1_oen_i; + mux_to_pads_o.muxed_v_08.pull_en = s_reg2hw.muxed_v_08_cfg.pull_en.q; + mux_to_pads_o.muxed_v_08.pull_sel = s_reg2hw.muxed_v_08_cfg.pull_sel.q; + end + PAD_MUX_GROUP_MUXED_V_08_SEL_GPIO_IO_V_8: begin + mux_to_pads_o.muxed_v_08.chip2pad = port_signals_soc2pad_i.gpio.gpio_v_8_o; + mux_to_pads_o.muxed_v_08.input_en = ~port_signals_soc2pad_i.gpio.gpio_v_8_oen_i; + mux_to_pads_o.muxed_v_08.output_en = port_signals_soc2pad_i.gpio.gpio_v_8_oen_i; + mux_to_pads_o.muxed_v_08.pull_en = s_reg2hw.muxed_v_08_cfg.pull_en.q; + mux_to_pads_o.muxed_v_08.pull_sel = s_reg2hw.muxed_v_08_cfg.pull_sel.q; + end + default: begin + mux_to_pads_o.muxed_v_08.chip2pad = s_reg2hw.muxed_v_08_cfg.chip2pad.q; + mux_to_pads_o.muxed_v_08.input_en = s_reg2hw.muxed_v_08_cfg.input_en.q; + mux_to_pads_o.muxed_v_08.output_en = s_reg2hw.muxed_v_08_cfg.output_en.q; + mux_to_pads_o.muxed_v_08.pull_en = s_reg2hw.muxed_v_08_cfg.pull_en.q; + mux_to_pads_o.muxed_v_08.pull_sel = s_reg2hw.muxed_v_08_cfg.pull_sel.q; + end + endcase + end // always_comb + + // Pad muxed_v_09 + always_comb begin + unique case (s_reg2hw.muxed_v_09_mux_sel.q) + PAD_MUX_GROUP_MUXED_V_09_SEL_DEFAULT: begin + mux_to_pads_o.muxed_v_09.chip2pad = s_reg2hw.muxed_v_09_cfg.chip2pad.q; + mux_to_pads_o.muxed_v_09.input_en = s_reg2hw.muxed_v_09_cfg.input_en.q; + mux_to_pads_o.muxed_v_09.output_en = s_reg2hw.muxed_v_09_cfg.output_en.q; + mux_to_pads_o.muxed_v_09.pull_en = s_reg2hw.muxed_v_09_cfg.pull_en.q; + mux_to_pads_o.muxed_v_09.pull_sel = s_reg2hw.muxed_v_09_cfg.pull_sel.q; + end + PAD_MUX_GROUP_MUXED_V_09_SEL_ETHERNET_RXD_0: begin + mux_to_pads_o.muxed_v_09.chip2pad = s_reg2hw.muxed_v_09_cfg.chip2pad.q; + mux_to_pads_o.muxed_v_09.input_en = 1'b1; + mux_to_pads_o.muxed_v_09.output_en = 1'b0; + mux_to_pads_o.muxed_v_09.pull_en = s_reg2hw.muxed_v_09_cfg.pull_en.q; + mux_to_pads_o.muxed_v_09.pull_sel = s_reg2hw.muxed_v_09_cfg.pull_sel.q; + end + PAD_MUX_GROUP_MUXED_V_09_SEL_SERIAL_LINK_I_4: begin + mux_to_pads_o.muxed_v_09.chip2pad = s_reg2hw.muxed_v_09_cfg.chip2pad.q; + mux_to_pads_o.muxed_v_09.input_en = 1'b1; + mux_to_pads_o.muxed_v_09.output_en = 1'b0; + mux_to_pads_o.muxed_v_09.pull_en = s_reg2hw.muxed_v_09_cfg.pull_en.q; + mux_to_pads_o.muxed_v_09.pull_sel = s_reg2hw.muxed_v_09_cfg.pull_sel.q; + end + PAD_MUX_GROUP_MUXED_V_09_SEL_TC_DATA: begin + mux_to_pads_o.muxed_v_09.chip2pad = s_reg2hw.muxed_v_09_cfg.chip2pad.q; + mux_to_pads_o.muxed_v_09.input_en = 1'b1; + mux_to_pads_o.muxed_v_09.output_en = 1'b0; + mux_to_pads_o.muxed_v_09.pull_en = s_reg2hw.muxed_v_09_cfg.pull_en.q; + mux_to_pads_o.muxed_v_09.pull_sel = s_reg2hw.muxed_v_09_cfg.pull_sel.q; + end + PAD_MUX_GROUP_MUXED_V_09_SEL_PLL_IO_2: begin + mux_to_pads_o.muxed_v_09.chip2pad = port_signals_soc2pad_i.pll.pll_2_o; + mux_to_pads_o.muxed_v_09.input_en = ~port_signals_soc2pad_i.pll.pll_2_oen_i; + mux_to_pads_o.muxed_v_09.output_en = port_signals_soc2pad_i.pll.pll_2_oen_i; + mux_to_pads_o.muxed_v_09.pull_en = s_reg2hw.muxed_v_09_cfg.pull_en.q; + mux_to_pads_o.muxed_v_09.pull_sel = s_reg2hw.muxed_v_09_cfg.pull_sel.q; + end + PAD_MUX_GROUP_MUXED_V_09_SEL_GPIO_IO_V_9: begin + mux_to_pads_o.muxed_v_09.chip2pad = port_signals_soc2pad_i.gpio.gpio_v_9_o; + mux_to_pads_o.muxed_v_09.input_en = ~port_signals_soc2pad_i.gpio.gpio_v_9_oen_i; + mux_to_pads_o.muxed_v_09.output_en = port_signals_soc2pad_i.gpio.gpio_v_9_oen_i; + mux_to_pads_o.muxed_v_09.pull_en = s_reg2hw.muxed_v_09_cfg.pull_en.q; + mux_to_pads_o.muxed_v_09.pull_sel = s_reg2hw.muxed_v_09_cfg.pull_sel.q; + end + default: begin + mux_to_pads_o.muxed_v_09.chip2pad = s_reg2hw.muxed_v_09_cfg.chip2pad.q; + mux_to_pads_o.muxed_v_09.input_en = s_reg2hw.muxed_v_09_cfg.input_en.q; + mux_to_pads_o.muxed_v_09.output_en = s_reg2hw.muxed_v_09_cfg.output_en.q; + mux_to_pads_o.muxed_v_09.pull_en = s_reg2hw.muxed_v_09_cfg.pull_en.q; + mux_to_pads_o.muxed_v_09.pull_sel = s_reg2hw.muxed_v_09_cfg.pull_sel.q; + end + endcase + end // always_comb + + // Pad muxed_v_10 + always_comb begin + unique case (s_reg2hw.muxed_v_10_mux_sel.q) + PAD_MUX_GROUP_MUXED_V_10_SEL_DEFAULT: begin + mux_to_pads_o.muxed_v_10.chip2pad = s_reg2hw.muxed_v_10_cfg.chip2pad.q; + mux_to_pads_o.muxed_v_10.input_en = s_reg2hw.muxed_v_10_cfg.input_en.q; + mux_to_pads_o.muxed_v_10.output_en = s_reg2hw.muxed_v_10_cfg.output_en.q; + mux_to_pads_o.muxed_v_10.pull_en = s_reg2hw.muxed_v_10_cfg.pull_en.q; + mux_to_pads_o.muxed_v_10.pull_sel = s_reg2hw.muxed_v_10_cfg.pull_sel.q; + end + PAD_MUX_GROUP_MUXED_V_10_SEL_ETHERNET_RXD_1: begin + mux_to_pads_o.muxed_v_10.chip2pad = s_reg2hw.muxed_v_10_cfg.chip2pad.q; + mux_to_pads_o.muxed_v_10.input_en = 1'b1; + mux_to_pads_o.muxed_v_10.output_en = 1'b0; + mux_to_pads_o.muxed_v_10.pull_en = s_reg2hw.muxed_v_10_cfg.pull_en.q; + mux_to_pads_o.muxed_v_10.pull_sel = s_reg2hw.muxed_v_10_cfg.pull_sel.q; + end + PAD_MUX_GROUP_MUXED_V_10_SEL_SERIAL_LINK_I_5: begin + mux_to_pads_o.muxed_v_10.chip2pad = s_reg2hw.muxed_v_10_cfg.chip2pad.q; + mux_to_pads_o.muxed_v_10.input_en = 1'b1; + mux_to_pads_o.muxed_v_10.output_en = 1'b0; + mux_to_pads_o.muxed_v_10.pull_en = s_reg2hw.muxed_v_10_cfg.pull_en.q; + mux_to_pads_o.muxed_v_10.pull_sel = s_reg2hw.muxed_v_10_cfg.pull_sel.q; + end + PAD_MUX_GROUP_MUXED_V_10_SEL_PTME_CLK: begin + mux_to_pads_o.muxed_v_10.chip2pad = port_signals_soc2pad_i.ptme.ptme_clk_o; + mux_to_pads_o.muxed_v_10.input_en = 1'b0; + mux_to_pads_o.muxed_v_10.output_en = 1'b1; + mux_to_pads_o.muxed_v_10.pull_en = s_reg2hw.muxed_v_10_cfg.pull_en.q; + mux_to_pads_o.muxed_v_10.pull_sel = s_reg2hw.muxed_v_10_cfg.pull_sel.q; + end + PAD_MUX_GROUP_MUXED_V_10_SEL_PLL_IO_3: begin + mux_to_pads_o.muxed_v_10.chip2pad = port_signals_soc2pad_i.pll.pll_3_o; + mux_to_pads_o.muxed_v_10.input_en = ~port_signals_soc2pad_i.pll.pll_3_oen_i; + mux_to_pads_o.muxed_v_10.output_en = port_signals_soc2pad_i.pll.pll_3_oen_i; + mux_to_pads_o.muxed_v_10.pull_en = s_reg2hw.muxed_v_10_cfg.pull_en.q; + mux_to_pads_o.muxed_v_10.pull_sel = s_reg2hw.muxed_v_10_cfg.pull_sel.q; + end + PAD_MUX_GROUP_MUXED_V_10_SEL_GPIO_IO_V_10: begin + mux_to_pads_o.muxed_v_10.chip2pad = port_signals_soc2pad_i.gpio.gpio_v_10_o; + mux_to_pads_o.muxed_v_10.input_en = ~port_signals_soc2pad_i.gpio.gpio_v_10_oen_i; + mux_to_pads_o.muxed_v_10.output_en = port_signals_soc2pad_i.gpio.gpio_v_10_oen_i; + mux_to_pads_o.muxed_v_10.pull_en = s_reg2hw.muxed_v_10_cfg.pull_en.q; + mux_to_pads_o.muxed_v_10.pull_sel = s_reg2hw.muxed_v_10_cfg.pull_sel.q; + end + default: begin + mux_to_pads_o.muxed_v_10.chip2pad = s_reg2hw.muxed_v_10_cfg.chip2pad.q; + mux_to_pads_o.muxed_v_10.input_en = s_reg2hw.muxed_v_10_cfg.input_en.q; + mux_to_pads_o.muxed_v_10.output_en = s_reg2hw.muxed_v_10_cfg.output_en.q; + mux_to_pads_o.muxed_v_10.pull_en = s_reg2hw.muxed_v_10_cfg.pull_en.q; + mux_to_pads_o.muxed_v_10.pull_sel = s_reg2hw.muxed_v_10_cfg.pull_sel.q; + end + endcase + end // always_comb + + // Pad muxed_v_11 + always_comb begin + unique case (s_reg2hw.muxed_v_11_mux_sel.q) + PAD_MUX_GROUP_MUXED_V_11_SEL_DEFAULT: begin + mux_to_pads_o.muxed_v_11.chip2pad = s_reg2hw.muxed_v_11_cfg.chip2pad.q; + mux_to_pads_o.muxed_v_11.input_en = s_reg2hw.muxed_v_11_cfg.input_en.q; + mux_to_pads_o.muxed_v_11.output_en = s_reg2hw.muxed_v_11_cfg.output_en.q; + mux_to_pads_o.muxed_v_11.pull_en = s_reg2hw.muxed_v_11_cfg.pull_en.q; + mux_to_pads_o.muxed_v_11.pull_sel = s_reg2hw.muxed_v_11_cfg.pull_sel.q; + end + PAD_MUX_GROUP_MUXED_V_11_SEL_ETHERNET_RXD_2: begin + mux_to_pads_o.muxed_v_11.chip2pad = s_reg2hw.muxed_v_11_cfg.chip2pad.q; + mux_to_pads_o.muxed_v_11.input_en = 1'b1; + mux_to_pads_o.muxed_v_11.output_en = 1'b0; + mux_to_pads_o.muxed_v_11.pull_en = s_reg2hw.muxed_v_11_cfg.pull_en.q; + mux_to_pads_o.muxed_v_11.pull_sel = s_reg2hw.muxed_v_11_cfg.pull_sel.q; + end + PAD_MUX_GROUP_MUXED_V_11_SEL_SERIAL_LINK_I_6: begin + mux_to_pads_o.muxed_v_11.chip2pad = s_reg2hw.muxed_v_11_cfg.chip2pad.q; + mux_to_pads_o.muxed_v_11.input_en = 1'b1; + mux_to_pads_o.muxed_v_11.output_en = 1'b0; + mux_to_pads_o.muxed_v_11.pull_en = s_reg2hw.muxed_v_11_cfg.pull_en.q; + mux_to_pads_o.muxed_v_11.pull_sel = s_reg2hw.muxed_v_11_cfg.pull_sel.q; + end + PAD_MUX_GROUP_MUXED_V_11_SEL_PTME_ENC: begin + mux_to_pads_o.muxed_v_11.chip2pad = port_signals_soc2pad_i.ptme.ptme_enc_o; + mux_to_pads_o.muxed_v_11.input_en = 1'b0; + mux_to_pads_o.muxed_v_11.output_en = 1'b1; + mux_to_pads_o.muxed_v_11.pull_en = s_reg2hw.muxed_v_11_cfg.pull_en.q; + mux_to_pads_o.muxed_v_11.pull_sel = s_reg2hw.muxed_v_11_cfg.pull_sel.q; + end + PAD_MUX_GROUP_MUXED_V_11_SEL_PLL_IO_4: begin + mux_to_pads_o.muxed_v_11.chip2pad = port_signals_soc2pad_i.pll.pll_4_o; + mux_to_pads_o.muxed_v_11.input_en = ~port_signals_soc2pad_i.pll.pll_4_oen_i; + mux_to_pads_o.muxed_v_11.output_en = port_signals_soc2pad_i.pll.pll_4_oen_i; + mux_to_pads_o.muxed_v_11.pull_en = s_reg2hw.muxed_v_11_cfg.pull_en.q; + mux_to_pads_o.muxed_v_11.pull_sel = s_reg2hw.muxed_v_11_cfg.pull_sel.q; + end + PAD_MUX_GROUP_MUXED_V_11_SEL_GPIO_IO_V_11: begin + mux_to_pads_o.muxed_v_11.chip2pad = port_signals_soc2pad_i.gpio.gpio_v_11_o; + mux_to_pads_o.muxed_v_11.input_en = ~port_signals_soc2pad_i.gpio.gpio_v_11_oen_i; + mux_to_pads_o.muxed_v_11.output_en = port_signals_soc2pad_i.gpio.gpio_v_11_oen_i; + mux_to_pads_o.muxed_v_11.pull_en = s_reg2hw.muxed_v_11_cfg.pull_en.q; + mux_to_pads_o.muxed_v_11.pull_sel = s_reg2hw.muxed_v_11_cfg.pull_sel.q; + end + default: begin + mux_to_pads_o.muxed_v_11.chip2pad = s_reg2hw.muxed_v_11_cfg.chip2pad.q; + mux_to_pads_o.muxed_v_11.input_en = s_reg2hw.muxed_v_11_cfg.input_en.q; + mux_to_pads_o.muxed_v_11.output_en = s_reg2hw.muxed_v_11_cfg.output_en.q; + mux_to_pads_o.muxed_v_11.pull_en = s_reg2hw.muxed_v_11_cfg.pull_en.q; + mux_to_pads_o.muxed_v_11.pull_sel = s_reg2hw.muxed_v_11_cfg.pull_sel.q; + end + endcase + end // always_comb + + // Pad muxed_v_12 + always_comb begin + unique case (s_reg2hw.muxed_v_12_mux_sel.q) + PAD_MUX_GROUP_MUXED_V_12_SEL_DEFAULT: begin + mux_to_pads_o.muxed_v_12.chip2pad = s_reg2hw.muxed_v_12_cfg.chip2pad.q; + mux_to_pads_o.muxed_v_12.input_en = s_reg2hw.muxed_v_12_cfg.input_en.q; + mux_to_pads_o.muxed_v_12.output_en = s_reg2hw.muxed_v_12_cfg.output_en.q; + mux_to_pads_o.muxed_v_12.pull_en = s_reg2hw.muxed_v_12_cfg.pull_en.q; + mux_to_pads_o.muxed_v_12.pull_sel = s_reg2hw.muxed_v_12_cfg.pull_sel.q; + end + PAD_MUX_GROUP_MUXED_V_12_SEL_ETHERNET_RXD_3: begin + mux_to_pads_o.muxed_v_12.chip2pad = s_reg2hw.muxed_v_12_cfg.chip2pad.q; + mux_to_pads_o.muxed_v_12.input_en = 1'b1; + mux_to_pads_o.muxed_v_12.output_en = 1'b0; + mux_to_pads_o.muxed_v_12.pull_en = s_reg2hw.muxed_v_12_cfg.pull_en.q; + mux_to_pads_o.muxed_v_12.pull_sel = s_reg2hw.muxed_v_12_cfg.pull_sel.q; + end + PAD_MUX_GROUP_MUXED_V_12_SEL_SERIAL_LINK_I_7: begin + mux_to_pads_o.muxed_v_12.chip2pad = s_reg2hw.muxed_v_12_cfg.chip2pad.q; + mux_to_pads_o.muxed_v_12.input_en = 1'b1; + mux_to_pads_o.muxed_v_12.output_en = 1'b0; + mux_to_pads_o.muxed_v_12.pull_en = s_reg2hw.muxed_v_12_cfg.pull_en.q; + mux_to_pads_o.muxed_v_12.pull_sel = s_reg2hw.muxed_v_12_cfg.pull_sel.q; + end + PAD_MUX_GROUP_MUXED_V_12_SEL_PTME_SYNC: begin + mux_to_pads_o.muxed_v_12.chip2pad = port_signals_soc2pad_i.ptme.ptme_sync_o; + mux_to_pads_o.muxed_v_12.input_en = 1'b0; + mux_to_pads_o.muxed_v_12.output_en = 1'b1; + mux_to_pads_o.muxed_v_12.pull_en = s_reg2hw.muxed_v_12_cfg.pull_en.q; + mux_to_pads_o.muxed_v_12.pull_sel = s_reg2hw.muxed_v_12_cfg.pull_sel.q; + end + PAD_MUX_GROUP_MUXED_V_12_SEL_PLL_IO_5: begin + mux_to_pads_o.muxed_v_12.chip2pad = port_signals_soc2pad_i.pll.pll_5_o; + mux_to_pads_o.muxed_v_12.input_en = ~port_signals_soc2pad_i.pll.pll_5_oen_i; + mux_to_pads_o.muxed_v_12.output_en = port_signals_soc2pad_i.pll.pll_5_oen_i; + mux_to_pads_o.muxed_v_12.pull_en = s_reg2hw.muxed_v_12_cfg.pull_en.q; + mux_to_pads_o.muxed_v_12.pull_sel = s_reg2hw.muxed_v_12_cfg.pull_sel.q; + end + PAD_MUX_GROUP_MUXED_V_12_SEL_GPIO_IO_V_12: begin + mux_to_pads_o.muxed_v_12.chip2pad = port_signals_soc2pad_i.gpio.gpio_v_12_o; + mux_to_pads_o.muxed_v_12.input_en = ~port_signals_soc2pad_i.gpio.gpio_v_12_oen_i; + mux_to_pads_o.muxed_v_12.output_en = port_signals_soc2pad_i.gpio.gpio_v_12_oen_i; + mux_to_pads_o.muxed_v_12.pull_en = s_reg2hw.muxed_v_12_cfg.pull_en.q; + mux_to_pads_o.muxed_v_12.pull_sel = s_reg2hw.muxed_v_12_cfg.pull_sel.q; + end + default: begin + mux_to_pads_o.muxed_v_12.chip2pad = s_reg2hw.muxed_v_12_cfg.chip2pad.q; + mux_to_pads_o.muxed_v_12.input_en = s_reg2hw.muxed_v_12_cfg.input_en.q; + mux_to_pads_o.muxed_v_12.output_en = s_reg2hw.muxed_v_12_cfg.output_en.q; + mux_to_pads_o.muxed_v_12.pull_en = s_reg2hw.muxed_v_12_cfg.pull_en.q; + mux_to_pads_o.muxed_v_12.pull_sel = s_reg2hw.muxed_v_12_cfg.pull_sel.q; + end + endcase + end // always_comb + + // Pad muxed_v_13 + always_comb begin + unique case (s_reg2hw.muxed_v_13_mux_sel.q) + PAD_MUX_GROUP_MUXED_V_13_SEL_DEFAULT: begin + mux_to_pads_o.muxed_v_13.chip2pad = s_reg2hw.muxed_v_13_cfg.chip2pad.q; + mux_to_pads_o.muxed_v_13.input_en = s_reg2hw.muxed_v_13_cfg.input_en.q; + mux_to_pads_o.muxed_v_13.output_en = s_reg2hw.muxed_v_13_cfg.output_en.q; + mux_to_pads_o.muxed_v_13.pull_en = s_reg2hw.muxed_v_13_cfg.pull_en.q; + mux_to_pads_o.muxed_v_13.pull_sel = s_reg2hw.muxed_v_13_cfg.pull_sel.q; + end + PAD_MUX_GROUP_MUXED_V_13_SEL_ETHERNET_TXCK: begin + mux_to_pads_o.muxed_v_13.chip2pad = port_signals_soc2pad_i.ethernet.eth_txck_o; + mux_to_pads_o.muxed_v_13.input_en = 1'b0; + mux_to_pads_o.muxed_v_13.output_en = 1'b1; + mux_to_pads_o.muxed_v_13.pull_en = s_reg2hw.muxed_v_13_cfg.pull_en.q; + mux_to_pads_o.muxed_v_13.pull_sel = s_reg2hw.muxed_v_13_cfg.pull_sel.q; + end + PAD_MUX_GROUP_MUXED_V_13_SEL_SERIAL_LINK_RCV_CLK_O: begin + mux_to_pads_o.muxed_v_13.chip2pad = port_signals_soc2pad_i.serial_link.slink_rcv_clk_o; + mux_to_pads_o.muxed_v_13.input_en = 1'b0; + mux_to_pads_o.muxed_v_13.output_en = 1'b1; + mux_to_pads_o.muxed_v_13.pull_en = s_reg2hw.muxed_v_13_cfg.pull_en.q; + mux_to_pads_o.muxed_v_13.pull_sel = s_reg2hw.muxed_v_13_cfg.pull_sel.q; + end + PAD_MUX_GROUP_MUXED_V_13_SEL_PTME_EXT_CLK: begin + mux_to_pads_o.muxed_v_13.chip2pad = s_reg2hw.muxed_v_13_cfg.chip2pad.q; + mux_to_pads_o.muxed_v_13.input_en = 1'b1; + mux_to_pads_o.muxed_v_13.output_en = 1'b0; + mux_to_pads_o.muxed_v_13.pull_en = s_reg2hw.muxed_v_13_cfg.pull_en.q; + mux_to_pads_o.muxed_v_13.pull_sel = s_reg2hw.muxed_v_13_cfg.pull_sel.q; + end + PAD_MUX_GROUP_MUXED_V_13_SEL_PLL_IO_6: begin + mux_to_pads_o.muxed_v_13.chip2pad = port_signals_soc2pad_i.pll.pll_6_o; + mux_to_pads_o.muxed_v_13.input_en = ~port_signals_soc2pad_i.pll.pll_6_oen_i; + mux_to_pads_o.muxed_v_13.output_en = port_signals_soc2pad_i.pll.pll_6_oen_i; + mux_to_pads_o.muxed_v_13.pull_en = s_reg2hw.muxed_v_13_cfg.pull_en.q; + mux_to_pads_o.muxed_v_13.pull_sel = s_reg2hw.muxed_v_13_cfg.pull_sel.q; + end + PAD_MUX_GROUP_MUXED_V_13_SEL_GPIO_IO_V_13: begin + mux_to_pads_o.muxed_v_13.chip2pad = port_signals_soc2pad_i.gpio.gpio_v_13_o; + mux_to_pads_o.muxed_v_13.input_en = ~port_signals_soc2pad_i.gpio.gpio_v_13_oen_i; + mux_to_pads_o.muxed_v_13.output_en = port_signals_soc2pad_i.gpio.gpio_v_13_oen_i; + mux_to_pads_o.muxed_v_13.pull_en = s_reg2hw.muxed_v_13_cfg.pull_en.q; + mux_to_pads_o.muxed_v_13.pull_sel = s_reg2hw.muxed_v_13_cfg.pull_sel.q; + end + default: begin + mux_to_pads_o.muxed_v_13.chip2pad = s_reg2hw.muxed_v_13_cfg.chip2pad.q; + mux_to_pads_o.muxed_v_13.input_en = s_reg2hw.muxed_v_13_cfg.input_en.q; + mux_to_pads_o.muxed_v_13.output_en = s_reg2hw.muxed_v_13_cfg.output_en.q; + mux_to_pads_o.muxed_v_13.pull_en = s_reg2hw.muxed_v_13_cfg.pull_en.q; + mux_to_pads_o.muxed_v_13.pull_sel = s_reg2hw.muxed_v_13_cfg.pull_sel.q; + end + endcase + end // always_comb + + // Pad muxed_v_14 + always_comb begin + unique case (s_reg2hw.muxed_v_14_mux_sel.q) + PAD_MUX_GROUP_MUXED_V_14_SEL_DEFAULT: begin + mux_to_pads_o.muxed_v_14.chip2pad = s_reg2hw.muxed_v_14_cfg.chip2pad.q; + mux_to_pads_o.muxed_v_14.input_en = s_reg2hw.muxed_v_14_cfg.input_en.q; + mux_to_pads_o.muxed_v_14.output_en = s_reg2hw.muxed_v_14_cfg.output_en.q; + mux_to_pads_o.muxed_v_14.pull_en = s_reg2hw.muxed_v_14_cfg.pull_en.q; + mux_to_pads_o.muxed_v_14.pull_sel = s_reg2hw.muxed_v_14_cfg.pull_sel.q; + end + PAD_MUX_GROUP_MUXED_V_14_SEL_ETHERNET_TXCTL: begin + mux_to_pads_o.muxed_v_14.chip2pad = port_signals_soc2pad_i.ethernet.eth_txctl_o; + mux_to_pads_o.muxed_v_14.input_en = 1'b0; + mux_to_pads_o.muxed_v_14.output_en = 1'b1; + mux_to_pads_o.muxed_v_14.pull_en = s_reg2hw.muxed_v_14_cfg.pull_en.q; + mux_to_pads_o.muxed_v_14.pull_sel = s_reg2hw.muxed_v_14_cfg.pull_sel.q; + end + PAD_MUX_GROUP_MUXED_V_14_SEL_SERIAL_LINK_O_V_0: begin + mux_to_pads_o.muxed_v_14.chip2pad = port_signals_soc2pad_i.serial_link.slink_v_0_o; + mux_to_pads_o.muxed_v_14.input_en = 1'b0; + mux_to_pads_o.muxed_v_14.output_en = 1'b1; + mux_to_pads_o.muxed_v_14.pull_en = s_reg2hw.muxed_v_14_cfg.pull_en.q; + mux_to_pads_o.muxed_v_14.pull_sel = s_reg2hw.muxed_v_14_cfg.pull_sel.q; + end + PAD_MUX_GROUP_MUXED_V_14_SEL_HPC_ADDR_0: begin + mux_to_pads_o.muxed_v_14.chip2pad = port_signals_soc2pad_i.hpc.hpc_addr_0_o; + mux_to_pads_o.muxed_v_14.input_en = 1'b0; + mux_to_pads_o.muxed_v_14.output_en = 1'b1; + mux_to_pads_o.muxed_v_14.pull_en = s_reg2hw.muxed_v_14_cfg.pull_en.q; + mux_to_pads_o.muxed_v_14.pull_sel = s_reg2hw.muxed_v_14_cfg.pull_sel.q; + end + PAD_MUX_GROUP_MUXED_V_14_SEL_GPIO_IO_V_14: begin + mux_to_pads_o.muxed_v_14.chip2pad = port_signals_soc2pad_i.gpio.gpio_v_14_o; + mux_to_pads_o.muxed_v_14.input_en = ~port_signals_soc2pad_i.gpio.gpio_v_14_oen_i; + mux_to_pads_o.muxed_v_14.output_en = port_signals_soc2pad_i.gpio.gpio_v_14_oen_i; + mux_to_pads_o.muxed_v_14.pull_en = s_reg2hw.muxed_v_14_cfg.pull_en.q; + mux_to_pads_o.muxed_v_14.pull_sel = s_reg2hw.muxed_v_14_cfg.pull_sel.q; + end + default: begin + mux_to_pads_o.muxed_v_14.chip2pad = s_reg2hw.muxed_v_14_cfg.chip2pad.q; + mux_to_pads_o.muxed_v_14.input_en = s_reg2hw.muxed_v_14_cfg.input_en.q; + mux_to_pads_o.muxed_v_14.output_en = s_reg2hw.muxed_v_14_cfg.output_en.q; + mux_to_pads_o.muxed_v_14.pull_en = s_reg2hw.muxed_v_14_cfg.pull_en.q; + mux_to_pads_o.muxed_v_14.pull_sel = s_reg2hw.muxed_v_14_cfg.pull_sel.q; + end + endcase + end // always_comb + + // Pad muxed_v_15 + always_comb begin + unique case (s_reg2hw.muxed_v_15_mux_sel.q) + PAD_MUX_GROUP_MUXED_V_15_SEL_DEFAULT: begin + mux_to_pads_o.muxed_v_15.chip2pad = s_reg2hw.muxed_v_15_cfg.chip2pad.q; + mux_to_pads_o.muxed_v_15.input_en = s_reg2hw.muxed_v_15_cfg.input_en.q; + mux_to_pads_o.muxed_v_15.output_en = s_reg2hw.muxed_v_15_cfg.output_en.q; + mux_to_pads_o.muxed_v_15.pull_en = s_reg2hw.muxed_v_15_cfg.pull_en.q; + mux_to_pads_o.muxed_v_15.pull_sel = s_reg2hw.muxed_v_15_cfg.pull_sel.q; + end + PAD_MUX_GROUP_MUXED_V_15_SEL_ETHERNET_TXD_0: begin + mux_to_pads_o.muxed_v_15.chip2pad = port_signals_soc2pad_i.ethernet.eth_txd_0_o; + mux_to_pads_o.muxed_v_15.input_en = 1'b0; + mux_to_pads_o.muxed_v_15.output_en = 1'b1; + mux_to_pads_o.muxed_v_15.pull_en = s_reg2hw.muxed_v_15_cfg.pull_en.q; + mux_to_pads_o.muxed_v_15.pull_sel = s_reg2hw.muxed_v_15_cfg.pull_sel.q; + end + PAD_MUX_GROUP_MUXED_V_15_SEL_SERIAL_LINK_O_V_1: begin + mux_to_pads_o.muxed_v_15.chip2pad = port_signals_soc2pad_i.serial_link.slink_v_1_o; + mux_to_pads_o.muxed_v_15.input_en = 1'b0; + mux_to_pads_o.muxed_v_15.output_en = 1'b1; + mux_to_pads_o.muxed_v_15.pull_en = s_reg2hw.muxed_v_15_cfg.pull_en.q; + mux_to_pads_o.muxed_v_15.pull_sel = s_reg2hw.muxed_v_15_cfg.pull_sel.q; + end + PAD_MUX_GROUP_MUXED_V_15_SEL_HPC_ADDR_1: begin + mux_to_pads_o.muxed_v_15.chip2pad = port_signals_soc2pad_i.hpc.hpc_addr_1_o; + mux_to_pads_o.muxed_v_15.input_en = 1'b0; + mux_to_pads_o.muxed_v_15.output_en = 1'b1; + mux_to_pads_o.muxed_v_15.pull_en = s_reg2hw.muxed_v_15_cfg.pull_en.q; + mux_to_pads_o.muxed_v_15.pull_sel = s_reg2hw.muxed_v_15_cfg.pull_sel.q; + end + PAD_MUX_GROUP_MUXED_V_15_SEL_GPIO_IO_V_15: begin + mux_to_pads_o.muxed_v_15.chip2pad = port_signals_soc2pad_i.gpio.gpio_v_15_o; + mux_to_pads_o.muxed_v_15.input_en = ~port_signals_soc2pad_i.gpio.gpio_v_15_oen_i; + mux_to_pads_o.muxed_v_15.output_en = port_signals_soc2pad_i.gpio.gpio_v_15_oen_i; + mux_to_pads_o.muxed_v_15.pull_en = s_reg2hw.muxed_v_15_cfg.pull_en.q; + mux_to_pads_o.muxed_v_15.pull_sel = s_reg2hw.muxed_v_15_cfg.pull_sel.q; + end + default: begin + mux_to_pads_o.muxed_v_15.chip2pad = s_reg2hw.muxed_v_15_cfg.chip2pad.q; + mux_to_pads_o.muxed_v_15.input_en = s_reg2hw.muxed_v_15_cfg.input_en.q; + mux_to_pads_o.muxed_v_15.output_en = s_reg2hw.muxed_v_15_cfg.output_en.q; + mux_to_pads_o.muxed_v_15.pull_en = s_reg2hw.muxed_v_15_cfg.pull_en.q; + mux_to_pads_o.muxed_v_15.pull_sel = s_reg2hw.muxed_v_15_cfg.pull_sel.q; + end + endcase + end // always_comb + + // Pad muxed_v_16 + always_comb begin + unique case (s_reg2hw.muxed_v_16_mux_sel.q) + PAD_MUX_GROUP_MUXED_V_16_SEL_DEFAULT: begin + mux_to_pads_o.muxed_v_16.chip2pad = s_reg2hw.muxed_v_16_cfg.chip2pad.q; + mux_to_pads_o.muxed_v_16.input_en = s_reg2hw.muxed_v_16_cfg.input_en.q; + mux_to_pads_o.muxed_v_16.output_en = s_reg2hw.muxed_v_16_cfg.output_en.q; + mux_to_pads_o.muxed_v_16.pull_en = s_reg2hw.muxed_v_16_cfg.pull_en.q; + mux_to_pads_o.muxed_v_16.pull_sel = s_reg2hw.muxed_v_16_cfg.pull_sel.q; + end + PAD_MUX_GROUP_MUXED_V_16_SEL_ETHERNET_TXD_1: begin + mux_to_pads_o.muxed_v_16.chip2pad = port_signals_soc2pad_i.ethernet.eth_txd_1_o; + mux_to_pads_o.muxed_v_16.input_en = 1'b0; + mux_to_pads_o.muxed_v_16.output_en = 1'b1; + mux_to_pads_o.muxed_v_16.pull_en = s_reg2hw.muxed_v_16_cfg.pull_en.q; + mux_to_pads_o.muxed_v_16.pull_sel = s_reg2hw.muxed_v_16_cfg.pull_sel.q; + end + PAD_MUX_GROUP_MUXED_V_16_SEL_SERIAL_LINK_O_V_2: begin + mux_to_pads_o.muxed_v_16.chip2pad = port_signals_soc2pad_i.serial_link.slink_v_2_o; + mux_to_pads_o.muxed_v_16.input_en = 1'b0; + mux_to_pads_o.muxed_v_16.output_en = 1'b1; + mux_to_pads_o.muxed_v_16.pull_en = s_reg2hw.muxed_v_16_cfg.pull_en.q; + mux_to_pads_o.muxed_v_16.pull_sel = s_reg2hw.muxed_v_16_cfg.pull_sel.q; + end + PAD_MUX_GROUP_MUXED_V_16_SEL_HPC_ADDR_2: begin + mux_to_pads_o.muxed_v_16.chip2pad = port_signals_soc2pad_i.hpc.hpc_addr_2_o; + mux_to_pads_o.muxed_v_16.input_en = 1'b0; + mux_to_pads_o.muxed_v_16.output_en = 1'b1; + mux_to_pads_o.muxed_v_16.pull_en = s_reg2hw.muxed_v_16_cfg.pull_en.q; + mux_to_pads_o.muxed_v_16.pull_sel = s_reg2hw.muxed_v_16_cfg.pull_sel.q; + end + PAD_MUX_GROUP_MUXED_V_16_SEL_GPIO_IO_V_16: begin + mux_to_pads_o.muxed_v_16.chip2pad = port_signals_soc2pad_i.gpio.gpio_v_16_o; + mux_to_pads_o.muxed_v_16.input_en = ~port_signals_soc2pad_i.gpio.gpio_v_16_oen_i; + mux_to_pads_o.muxed_v_16.output_en = port_signals_soc2pad_i.gpio.gpio_v_16_oen_i; + mux_to_pads_o.muxed_v_16.pull_en = s_reg2hw.muxed_v_16_cfg.pull_en.q; + mux_to_pads_o.muxed_v_16.pull_sel = s_reg2hw.muxed_v_16_cfg.pull_sel.q; + end + default: begin + mux_to_pads_o.muxed_v_16.chip2pad = s_reg2hw.muxed_v_16_cfg.chip2pad.q; + mux_to_pads_o.muxed_v_16.input_en = s_reg2hw.muxed_v_16_cfg.input_en.q; + mux_to_pads_o.muxed_v_16.output_en = s_reg2hw.muxed_v_16_cfg.output_en.q; + mux_to_pads_o.muxed_v_16.pull_en = s_reg2hw.muxed_v_16_cfg.pull_en.q; + mux_to_pads_o.muxed_v_16.pull_sel = s_reg2hw.muxed_v_16_cfg.pull_sel.q; + end + endcase + end // always_comb + + // Pad muxed_v_17 + always_comb begin + unique case (s_reg2hw.muxed_v_17_mux_sel.q) + PAD_MUX_GROUP_MUXED_V_17_SEL_DEFAULT: begin + mux_to_pads_o.muxed_v_17.chip2pad = s_reg2hw.muxed_v_17_cfg.chip2pad.q; + mux_to_pads_o.muxed_v_17.input_en = s_reg2hw.muxed_v_17_cfg.input_en.q; + mux_to_pads_o.muxed_v_17.output_en = s_reg2hw.muxed_v_17_cfg.output_en.q; + mux_to_pads_o.muxed_v_17.pull_en = s_reg2hw.muxed_v_17_cfg.pull_en.q; + mux_to_pads_o.muxed_v_17.pull_sel = s_reg2hw.muxed_v_17_cfg.pull_sel.q; + end + PAD_MUX_GROUP_MUXED_V_17_SEL_ETHERNET_TXD_2: begin + mux_to_pads_o.muxed_v_17.chip2pad = port_signals_soc2pad_i.ethernet.eth_txd_2_o; + mux_to_pads_o.muxed_v_17.input_en = 1'b0; + mux_to_pads_o.muxed_v_17.output_en = 1'b1; + mux_to_pads_o.muxed_v_17.pull_en = s_reg2hw.muxed_v_17_cfg.pull_en.q; + mux_to_pads_o.muxed_v_17.pull_sel = s_reg2hw.muxed_v_17_cfg.pull_sel.q; + end + PAD_MUX_GROUP_MUXED_V_17_SEL_SERIAL_LINK_O_V_3: begin + mux_to_pads_o.muxed_v_17.chip2pad = port_signals_soc2pad_i.serial_link.slink_v_3_o; + mux_to_pads_o.muxed_v_17.input_en = 1'b0; + mux_to_pads_o.muxed_v_17.output_en = 1'b1; + mux_to_pads_o.muxed_v_17.pull_en = s_reg2hw.muxed_v_17_cfg.pull_en.q; + mux_to_pads_o.muxed_v_17.pull_sel = s_reg2hw.muxed_v_17_cfg.pull_sel.q; + end + PAD_MUX_GROUP_MUXED_V_17_SEL_HPC_CMD_EN: begin + mux_to_pads_o.muxed_v_17.chip2pad = port_signals_soc2pad_i.hpc.hpc_cmd_en_o; + mux_to_pads_o.muxed_v_17.input_en = 1'b0; + mux_to_pads_o.muxed_v_17.output_en = 1'b1; + mux_to_pads_o.muxed_v_17.pull_en = s_reg2hw.muxed_v_17_cfg.pull_en.q; + mux_to_pads_o.muxed_v_17.pull_sel = s_reg2hw.muxed_v_17_cfg.pull_sel.q; + end + PAD_MUX_GROUP_MUXED_V_17_SEL_GPIO_IO_V_17: begin + mux_to_pads_o.muxed_v_17.chip2pad = port_signals_soc2pad_i.gpio.gpio_v_17_o; + mux_to_pads_o.muxed_v_17.input_en = ~port_signals_soc2pad_i.gpio.gpio_v_17_oen_i; + mux_to_pads_o.muxed_v_17.output_en = port_signals_soc2pad_i.gpio.gpio_v_17_oen_i; + mux_to_pads_o.muxed_v_17.pull_en = s_reg2hw.muxed_v_17_cfg.pull_en.q; + mux_to_pads_o.muxed_v_17.pull_sel = s_reg2hw.muxed_v_17_cfg.pull_sel.q; + end + default: begin + mux_to_pads_o.muxed_v_17.chip2pad = s_reg2hw.muxed_v_17_cfg.chip2pad.q; + mux_to_pads_o.muxed_v_17.input_en = s_reg2hw.muxed_v_17_cfg.input_en.q; + mux_to_pads_o.muxed_v_17.output_en = s_reg2hw.muxed_v_17_cfg.output_en.q; + mux_to_pads_o.muxed_v_17.pull_en = s_reg2hw.muxed_v_17_cfg.pull_en.q; + mux_to_pads_o.muxed_v_17.pull_sel = s_reg2hw.muxed_v_17_cfg.pull_sel.q; + end + endcase + end // always_comb + + // Pad muxed_h_00 + always_comb begin + unique case (s_reg2hw.muxed_h_00_mux_sel.q) + PAD_MUX_GROUP_MUXED_H_00_SEL_DEFAULT: begin + mux_to_pads_o.muxed_h_00.chip2pad = s_reg2hw.muxed_h_00_cfg.chip2pad.q; + mux_to_pads_o.muxed_h_00.input_en = s_reg2hw.muxed_h_00_cfg.input_en.q; + mux_to_pads_o.muxed_h_00.output_en = s_reg2hw.muxed_h_00_cfg.output_en.q; + mux_to_pads_o.muxed_h_00.pull_en = s_reg2hw.muxed_h_00_cfg.pull_en.q; + mux_to_pads_o.muxed_h_00.pull_sel = s_reg2hw.muxed_h_00_cfg.pull_sel.q; + end + PAD_MUX_GROUP_MUXED_H_00_SEL_ETHERNET_TXD_3: begin + mux_to_pads_o.muxed_h_00.chip2pad = port_signals_soc2pad_i.ethernet.eth_txd_3_o; + mux_to_pads_o.muxed_h_00.input_en = 1'b0; + mux_to_pads_o.muxed_h_00.output_en = 1'b1; + mux_to_pads_o.muxed_h_00.pull_en = s_reg2hw.muxed_h_00_cfg.pull_en.q; + mux_to_pads_o.muxed_h_00.pull_sel = s_reg2hw.muxed_h_00_cfg.pull_sel.q; + end + PAD_MUX_GROUP_MUXED_H_00_SEL_SERIAL_LINK_O_H_0: begin + mux_to_pads_o.muxed_h_00.chip2pad = port_signals_soc2pad_i.serial_link.slink_h_0_o; + mux_to_pads_o.muxed_h_00.input_en = 1'b0; + mux_to_pads_o.muxed_h_00.output_en = 1'b1; + mux_to_pads_o.muxed_h_00.pull_en = s_reg2hw.muxed_h_00_cfg.pull_en.q; + mux_to_pads_o.muxed_h_00.pull_sel = s_reg2hw.muxed_h_00_cfg.pull_sel.q; + end + PAD_MUX_GROUP_MUXED_H_00_SEL_HPC_SAMPLE: begin + mux_to_pads_o.muxed_h_00.chip2pad = port_signals_soc2pad_i.hpc.hpc_sample_o; + mux_to_pads_o.muxed_h_00.input_en = 1'b0; + mux_to_pads_o.muxed_h_00.output_en = 1'b1; + mux_to_pads_o.muxed_h_00.pull_en = s_reg2hw.muxed_h_00_cfg.pull_en.q; + mux_to_pads_o.muxed_h_00.pull_sel = s_reg2hw.muxed_h_00_cfg.pull_sel.q; + end + PAD_MUX_GROUP_MUXED_H_00_SEL_GPIO_IO_H_0: begin + mux_to_pads_o.muxed_h_00.chip2pad = port_signals_soc2pad_i.gpio.gpio_h_0_o; + mux_to_pads_o.muxed_h_00.input_en = ~port_signals_soc2pad_i.gpio.gpio_h_0_oen_i; + mux_to_pads_o.muxed_h_00.output_en = port_signals_soc2pad_i.gpio.gpio_h_0_oen_i; + mux_to_pads_o.muxed_h_00.pull_en = s_reg2hw.muxed_h_00_cfg.pull_en.q; + mux_to_pads_o.muxed_h_00.pull_sel = s_reg2hw.muxed_h_00_cfg.pull_sel.q; + end + default: begin + mux_to_pads_o.muxed_h_00.chip2pad = s_reg2hw.muxed_h_00_cfg.chip2pad.q; + mux_to_pads_o.muxed_h_00.input_en = s_reg2hw.muxed_h_00_cfg.input_en.q; + mux_to_pads_o.muxed_h_00.output_en = s_reg2hw.muxed_h_00_cfg.output_en.q; + mux_to_pads_o.muxed_h_00.pull_en = s_reg2hw.muxed_h_00_cfg.pull_en.q; + mux_to_pads_o.muxed_h_00.pull_sel = s_reg2hw.muxed_h_00_cfg.pull_sel.q; + end + endcase + end // always_comb + + // Pad muxed_h_01 + always_comb begin + unique case (s_reg2hw.muxed_h_01_mux_sel.q) + PAD_MUX_GROUP_MUXED_H_01_SEL_DEFAULT: begin + mux_to_pads_o.muxed_h_01.chip2pad = s_reg2hw.muxed_h_01_cfg.chip2pad.q; + mux_to_pads_o.muxed_h_01.input_en = s_reg2hw.muxed_h_01_cfg.input_en.q; + mux_to_pads_o.muxed_h_01.output_en = s_reg2hw.muxed_h_01_cfg.output_en.q; + mux_to_pads_o.muxed_h_01.pull_en = s_reg2hw.muxed_h_01_cfg.pull_en.q; + mux_to_pads_o.muxed_h_01.pull_sel = s_reg2hw.muxed_h_01_cfg.pull_sel.q; + end + PAD_MUX_GROUP_MUXED_H_01_SEL_ETHERNET_MD: begin + mux_to_pads_o.muxed_h_01.chip2pad = port_signals_soc2pad_i.ethernet.eth_md_o; + mux_to_pads_o.muxed_h_01.input_en = ~port_signals_soc2pad_i.ethernet.eth_md_oen_i; + mux_to_pads_o.muxed_h_01.output_en = port_signals_soc2pad_i.ethernet.eth_md_oen_i; + mux_to_pads_o.muxed_h_01.pull_en = s_reg2hw.muxed_h_01_cfg.pull_en.q; + mux_to_pads_o.muxed_h_01.pull_sel = s_reg2hw.muxed_h_01_cfg.pull_sel.q; + end + PAD_MUX_GROUP_MUXED_H_01_SEL_SERIAL_LINK_O_H_1: begin + mux_to_pads_o.muxed_h_01.chip2pad = port_signals_soc2pad_i.serial_link.slink_h_1_o; + mux_to_pads_o.muxed_h_01.input_en = 1'b0; + mux_to_pads_o.muxed_h_01.output_en = 1'b1; + mux_to_pads_o.muxed_h_01.pull_en = s_reg2hw.muxed_h_01_cfg.pull_en.q; + mux_to_pads_o.muxed_h_01.pull_sel = s_reg2hw.muxed_h_01_cfg.pull_sel.q; + end + PAD_MUX_GROUP_MUXED_H_01_SEL_LLC_LINE_0: begin + mux_to_pads_o.muxed_h_01.chip2pad = port_signals_soc2pad_i.llc.llc_line_0_o; + mux_to_pads_o.muxed_h_01.input_en = 1'b0; + mux_to_pads_o.muxed_h_01.output_en = 1'b1; + mux_to_pads_o.muxed_h_01.pull_en = s_reg2hw.muxed_h_01_cfg.pull_en.q; + mux_to_pads_o.muxed_h_01.pull_sel = s_reg2hw.muxed_h_01_cfg.pull_sel.q; + end + PAD_MUX_GROUP_MUXED_H_01_SEL_GPIO_IO_H_1: begin + mux_to_pads_o.muxed_h_01.chip2pad = port_signals_soc2pad_i.gpio.gpio_h_1_o; + mux_to_pads_o.muxed_h_01.input_en = ~port_signals_soc2pad_i.gpio.gpio_h_1_oen_i; + mux_to_pads_o.muxed_h_01.output_en = port_signals_soc2pad_i.gpio.gpio_h_1_oen_i; + mux_to_pads_o.muxed_h_01.pull_en = s_reg2hw.muxed_h_01_cfg.pull_en.q; + mux_to_pads_o.muxed_h_01.pull_sel = s_reg2hw.muxed_h_01_cfg.pull_sel.q; + end + default: begin + mux_to_pads_o.muxed_h_01.chip2pad = s_reg2hw.muxed_h_01_cfg.chip2pad.q; + mux_to_pads_o.muxed_h_01.input_en = s_reg2hw.muxed_h_01_cfg.input_en.q; + mux_to_pads_o.muxed_h_01.output_en = s_reg2hw.muxed_h_01_cfg.output_en.q; + mux_to_pads_o.muxed_h_01.pull_en = s_reg2hw.muxed_h_01_cfg.pull_en.q; + mux_to_pads_o.muxed_h_01.pull_sel = s_reg2hw.muxed_h_01_cfg.pull_sel.q; + end + endcase + end // always_comb + + // Pad muxed_h_02 + always_comb begin + unique case (s_reg2hw.muxed_h_02_mux_sel.q) + PAD_MUX_GROUP_MUXED_H_02_SEL_DEFAULT: begin + mux_to_pads_o.muxed_h_02.chip2pad = s_reg2hw.muxed_h_02_cfg.chip2pad.q; + mux_to_pads_o.muxed_h_02.input_en = s_reg2hw.muxed_h_02_cfg.input_en.q; + mux_to_pads_o.muxed_h_02.output_en = s_reg2hw.muxed_h_02_cfg.output_en.q; + mux_to_pads_o.muxed_h_02.pull_en = s_reg2hw.muxed_h_02_cfg.pull_en.q; + mux_to_pads_o.muxed_h_02.pull_sel = s_reg2hw.muxed_h_02_cfg.pull_sel.q; + end + PAD_MUX_GROUP_MUXED_H_02_SEL_ETHERNET_MDC: begin + mux_to_pads_o.muxed_h_02.chip2pad = port_signals_soc2pad_i.ethernet.eth_mdc_o; + mux_to_pads_o.muxed_h_02.input_en = 1'b0; + mux_to_pads_o.muxed_h_02.output_en = 1'b1; + mux_to_pads_o.muxed_h_02.pull_en = s_reg2hw.muxed_h_02_cfg.pull_en.q; + mux_to_pads_o.muxed_h_02.pull_sel = s_reg2hw.muxed_h_02_cfg.pull_sel.q; + end + PAD_MUX_GROUP_MUXED_H_02_SEL_SERIAL_LINK_O_H_2: begin + mux_to_pads_o.muxed_h_02.chip2pad = port_signals_soc2pad_i.serial_link.slink_h_2_o; + mux_to_pads_o.muxed_h_02.input_en = 1'b0; + mux_to_pads_o.muxed_h_02.output_en = 1'b1; + mux_to_pads_o.muxed_h_02.pull_en = s_reg2hw.muxed_h_02_cfg.pull_en.q; + mux_to_pads_o.muxed_h_02.pull_sel = s_reg2hw.muxed_h_02_cfg.pull_sel.q; + end + PAD_MUX_GROUP_MUXED_H_02_SEL_LLC_LINE_1: begin + mux_to_pads_o.muxed_h_02.chip2pad = port_signals_soc2pad_i.llc.llc_line_1_o; + mux_to_pads_o.muxed_h_02.input_en = 1'b0; + mux_to_pads_o.muxed_h_02.output_en = 1'b1; + mux_to_pads_o.muxed_h_02.pull_en = s_reg2hw.muxed_h_02_cfg.pull_en.q; + mux_to_pads_o.muxed_h_02.pull_sel = s_reg2hw.muxed_h_02_cfg.pull_sel.q; + end + PAD_MUX_GROUP_MUXED_H_02_SEL_GPIO_IO_H_2: begin + mux_to_pads_o.muxed_h_02.chip2pad = port_signals_soc2pad_i.gpio.gpio_h_2_o; + mux_to_pads_o.muxed_h_02.input_en = ~port_signals_soc2pad_i.gpio.gpio_h_2_oen_i; + mux_to_pads_o.muxed_h_02.output_en = port_signals_soc2pad_i.gpio.gpio_h_2_oen_i; + mux_to_pads_o.muxed_h_02.pull_en = s_reg2hw.muxed_h_02_cfg.pull_en.q; + mux_to_pads_o.muxed_h_02.pull_sel = s_reg2hw.muxed_h_02_cfg.pull_sel.q; + end + default: begin + mux_to_pads_o.muxed_h_02.chip2pad = s_reg2hw.muxed_h_02_cfg.chip2pad.q; + mux_to_pads_o.muxed_h_02.input_en = s_reg2hw.muxed_h_02_cfg.input_en.q; + mux_to_pads_o.muxed_h_02.output_en = s_reg2hw.muxed_h_02_cfg.output_en.q; + mux_to_pads_o.muxed_h_02.pull_en = s_reg2hw.muxed_h_02_cfg.pull_en.q; + mux_to_pads_o.muxed_h_02.pull_sel = s_reg2hw.muxed_h_02_cfg.pull_sel.q; + end + endcase + end // always_comb + + // Pad muxed_h_03 + always_comb begin + unique case (s_reg2hw.muxed_h_03_mux_sel.q) + PAD_MUX_GROUP_MUXED_H_03_SEL_DEFAULT: begin + mux_to_pads_o.muxed_h_03.chip2pad = s_reg2hw.muxed_h_03_cfg.chip2pad.q; + mux_to_pads_o.muxed_h_03.input_en = s_reg2hw.muxed_h_03_cfg.input_en.q; + mux_to_pads_o.muxed_h_03.output_en = s_reg2hw.muxed_h_03_cfg.output_en.q; + mux_to_pads_o.muxed_h_03.pull_en = s_reg2hw.muxed_h_03_cfg.pull_en.q; + mux_to_pads_o.muxed_h_03.pull_sel = s_reg2hw.muxed_h_03_cfg.pull_sel.q; + end + PAD_MUX_GROUP_MUXED_H_03_SEL_ETHERNET_RST_N: begin + mux_to_pads_o.muxed_h_03.chip2pad = port_signals_soc2pad_i.ethernet.eth_rst_no; + mux_to_pads_o.muxed_h_03.input_en = 1'b0; + mux_to_pads_o.muxed_h_03.output_en = 1'b1; + mux_to_pads_o.muxed_h_03.pull_en = s_reg2hw.muxed_h_03_cfg.pull_en.q; + mux_to_pads_o.muxed_h_03.pull_sel = s_reg2hw.muxed_h_03_cfg.pull_sel.q; + end + PAD_MUX_GROUP_MUXED_H_03_SEL_SERIAL_LINK_O_H_3: begin + mux_to_pads_o.muxed_h_03.chip2pad = port_signals_soc2pad_i.serial_link.slink_h_3_o; + mux_to_pads_o.muxed_h_03.input_en = 1'b0; + mux_to_pads_o.muxed_h_03.output_en = 1'b1; + mux_to_pads_o.muxed_h_03.pull_en = s_reg2hw.muxed_h_03_cfg.pull_en.q; + mux_to_pads_o.muxed_h_03.pull_sel = s_reg2hw.muxed_h_03_cfg.pull_sel.q; + end + PAD_MUX_GROUP_MUXED_H_03_SEL_OBT_EXT_CLK: begin + mux_to_pads_o.muxed_h_03.chip2pad = s_reg2hw.muxed_h_03_cfg.chip2pad.q; + mux_to_pads_o.muxed_h_03.input_en = 1'b1; + mux_to_pads_o.muxed_h_03.output_en = 1'b0; + mux_to_pads_o.muxed_h_03.pull_en = s_reg2hw.muxed_h_03_cfg.pull_en.q; + mux_to_pads_o.muxed_h_03.pull_sel = s_reg2hw.muxed_h_03_cfg.pull_sel.q; + end + PAD_MUX_GROUP_MUXED_H_03_SEL_GPIO_IO_H_3: begin + mux_to_pads_o.muxed_h_03.chip2pad = port_signals_soc2pad_i.gpio.gpio_h_3_o; + mux_to_pads_o.muxed_h_03.input_en = ~port_signals_soc2pad_i.gpio.gpio_h_3_oen_i; + mux_to_pads_o.muxed_h_03.output_en = port_signals_soc2pad_i.gpio.gpio_h_3_oen_i; + mux_to_pads_o.muxed_h_03.pull_en = s_reg2hw.muxed_h_03_cfg.pull_en.q; + mux_to_pads_o.muxed_h_03.pull_sel = s_reg2hw.muxed_h_03_cfg.pull_sel.q; + end + default: begin + mux_to_pads_o.muxed_h_03.chip2pad = s_reg2hw.muxed_h_03_cfg.chip2pad.q; + mux_to_pads_o.muxed_h_03.input_en = s_reg2hw.muxed_h_03_cfg.input_en.q; + mux_to_pads_o.muxed_h_03.output_en = s_reg2hw.muxed_h_03_cfg.output_en.q; + mux_to_pads_o.muxed_h_03.pull_en = s_reg2hw.muxed_h_03_cfg.pull_en.q; + mux_to_pads_o.muxed_h_03.pull_sel = s_reg2hw.muxed_h_03_cfg.pull_sel.q; + end + endcase + end // always_comb + + + // Pad -> SoC Multiplex Logic + // Port Group spi + + + + + // Port Signal spih_sd_0_i + logic [0:0] port_mux_sel_spi_spih_sd_0_i_req; + logic [PORT_MUX_GROUP_MUXED_V_03_SEL_WIDTH-1:0] port_mux_sel_spi_spih_sd_0_i_arbitrated; + logic port_mux_sel_spi_spih_sd_0_i_no_connection; + + assign port_mux_sel_spi_spih_sd_0_i_req[PORT_MUX_GROUP_MUXED_V_03_SEL_MUXED_V_03] = s_reg2hw.muxed_v_03_mux_sel.q == PAD_MUX_GROUP_MUXED_V_03_SEL_SPI_SD_0 ? 1'b1 : 1'b0; + + lzc #( + .WIDTH(1), + .MODE(1'b0) + ) i_port_muxsel_spi_spih_sd_0_i_arbiter ( + .in_i(port_mux_sel_spi_spih_sd_0_i_req), + .cnt_o(port_mux_sel_spi_spih_sd_0_i_arbitrated), + .empty_o(port_mux_sel_spi_spih_sd_0_i_no_connection) + ); + + always_comb begin + if (port_mux_sel_spi_spih_sd_0_i_no_connection) begin + port_signals_pad2soc_o.spi.spih_sd_0_i = 1'b0; + end else begin + unique case (port_mux_sel_spi_spih_sd_0_i_arbitrated) + PORT_MUX_GROUP_MUXED_V_03_SEL_MUXED_V_03: begin + port_signals_pad2soc_o.spi.spih_sd_0_i = pads_to_mux_i.muxed_v_03.pad2chip; + end + default: begin + port_signals_pad2soc_o.spi.spih_sd_0_i = 1'b0; + end + endcase + end + end + + + // Port Signal spih_sd_1_i + logic [0:0] port_mux_sel_spi_spih_sd_1_i_req; + logic [PORT_MUX_GROUP_MUXED_V_04_SEL_WIDTH-1:0] port_mux_sel_spi_spih_sd_1_i_arbitrated; + logic port_mux_sel_spi_spih_sd_1_i_no_connection; + + assign port_mux_sel_spi_spih_sd_1_i_req[PORT_MUX_GROUP_MUXED_V_04_SEL_MUXED_V_04] = s_reg2hw.muxed_v_04_mux_sel.q == PAD_MUX_GROUP_MUXED_V_04_SEL_SPI_SD_1 ? 1'b1 : 1'b0; + + lzc #( + .WIDTH(1), + .MODE(1'b0) + ) i_port_muxsel_spi_spih_sd_1_i_arbiter ( + .in_i(port_mux_sel_spi_spih_sd_1_i_req), + .cnt_o(port_mux_sel_spi_spih_sd_1_i_arbitrated), + .empty_o(port_mux_sel_spi_spih_sd_1_i_no_connection) + ); + + always_comb begin + if (port_mux_sel_spi_spih_sd_1_i_no_connection) begin + port_signals_pad2soc_o.spi.spih_sd_1_i = 1'b0; + end else begin + unique case (port_mux_sel_spi_spih_sd_1_i_arbitrated) + PORT_MUX_GROUP_MUXED_V_04_SEL_MUXED_V_04: begin + port_signals_pad2soc_o.spi.spih_sd_1_i = pads_to_mux_i.muxed_v_04.pad2chip; + end + default: begin + port_signals_pad2soc_o.spi.spih_sd_1_i = 1'b0; + end + endcase + end + end + + + // Port Signal spih_sd_2_i + logic [0:0] port_mux_sel_spi_spih_sd_2_i_req; + logic [PORT_MUX_GROUP_MUXED_V_05_SEL_WIDTH-1:0] port_mux_sel_spi_spih_sd_2_i_arbitrated; + logic port_mux_sel_spi_spih_sd_2_i_no_connection; + + assign port_mux_sel_spi_spih_sd_2_i_req[PORT_MUX_GROUP_MUXED_V_05_SEL_MUXED_V_05] = s_reg2hw.muxed_v_05_mux_sel.q == PAD_MUX_GROUP_MUXED_V_05_SEL_SPI_SD_2 ? 1'b1 : 1'b0; + + lzc #( + .WIDTH(1), + .MODE(1'b0) + ) i_port_muxsel_spi_spih_sd_2_i_arbiter ( + .in_i(port_mux_sel_spi_spih_sd_2_i_req), + .cnt_o(port_mux_sel_spi_spih_sd_2_i_arbitrated), + .empty_o(port_mux_sel_spi_spih_sd_2_i_no_connection) + ); + + always_comb begin + if (port_mux_sel_spi_spih_sd_2_i_no_connection) begin + port_signals_pad2soc_o.spi.spih_sd_2_i = 1'b0; + end else begin + unique case (port_mux_sel_spi_spih_sd_2_i_arbitrated) + PORT_MUX_GROUP_MUXED_V_05_SEL_MUXED_V_05: begin + port_signals_pad2soc_o.spi.spih_sd_2_i = pads_to_mux_i.muxed_v_05.pad2chip; + end + default: begin + port_signals_pad2soc_o.spi.spih_sd_2_i = 1'b0; + end + endcase + end + end + + + // Port Signal spih_sd_3_i + logic [0:0] port_mux_sel_spi_spih_sd_3_i_req; + logic [PORT_MUX_GROUP_MUXED_V_06_SEL_WIDTH-1:0] port_mux_sel_spi_spih_sd_3_i_arbitrated; + logic port_mux_sel_spi_spih_sd_3_i_no_connection; + + assign port_mux_sel_spi_spih_sd_3_i_req[PORT_MUX_GROUP_MUXED_V_06_SEL_MUXED_V_06] = s_reg2hw.muxed_v_06_mux_sel.q == PAD_MUX_GROUP_MUXED_V_06_SEL_SPI_SD_3 ? 1'b1 : 1'b0; + + lzc #( + .WIDTH(1), + .MODE(1'b0) + ) i_port_muxsel_spi_spih_sd_3_i_arbiter ( + .in_i(port_mux_sel_spi_spih_sd_3_i_req), + .cnt_o(port_mux_sel_spi_spih_sd_3_i_arbitrated), + .empty_o(port_mux_sel_spi_spih_sd_3_i_no_connection) + ); + + always_comb begin + if (port_mux_sel_spi_spih_sd_3_i_no_connection) begin + port_signals_pad2soc_o.spi.spih_sd_3_i = 1'b0; + end else begin + unique case (port_mux_sel_spi_spih_sd_3_i_arbitrated) + PORT_MUX_GROUP_MUXED_V_06_SEL_MUXED_V_06: begin + port_signals_pad2soc_o.spi.spih_sd_3_i = pads_to_mux_i.muxed_v_06.pad2chip; + end + default: begin + port_signals_pad2soc_o.spi.spih_sd_3_i = 1'b0; + end + endcase + end + end + + // Port Group ethernet + + // Port Signal eth_rxck_i + logic [0:0] port_mux_sel_ethernet_eth_rxck_i_req; + logic [PORT_MUX_GROUP_MUXED_V_07_SEL_WIDTH-1:0] port_mux_sel_ethernet_eth_rxck_i_arbitrated; + logic port_mux_sel_ethernet_eth_rxck_i_no_connection; + + assign port_mux_sel_ethernet_eth_rxck_i_req[PORT_MUX_GROUP_MUXED_V_07_SEL_MUXED_V_07] = s_reg2hw.muxed_v_07_mux_sel.q == PAD_MUX_GROUP_MUXED_V_07_SEL_ETHERNET_RXCK ? 1'b1 : 1'b0; + + lzc #( + .WIDTH(1), + .MODE(1'b0) + ) i_port_muxsel_ethernet_eth_rxck_i_arbiter ( + .in_i(port_mux_sel_ethernet_eth_rxck_i_req), + .cnt_o(port_mux_sel_ethernet_eth_rxck_i_arbitrated), + .empty_o(port_mux_sel_ethernet_eth_rxck_i_no_connection) + ); + + always_comb begin + if (port_mux_sel_ethernet_eth_rxck_i_no_connection) begin + port_signals_pad2soc_o.ethernet.eth_rxck_i = 1'b0; + end else begin + unique case (port_mux_sel_ethernet_eth_rxck_i_arbitrated) + PORT_MUX_GROUP_MUXED_V_07_SEL_MUXED_V_07: begin + port_signals_pad2soc_o.ethernet.eth_rxck_i = pads_to_mux_i.muxed_v_07.pad2chip; + end + default: begin + port_signals_pad2soc_o.ethernet.eth_rxck_i = 1'b0; + end + endcase + end + end + + + // Port Signal eth_rxctl_i + logic [0:0] port_mux_sel_ethernet_eth_rxctl_i_req; + logic [PORT_MUX_GROUP_MUXED_V_08_SEL_WIDTH-1:0] port_mux_sel_ethernet_eth_rxctl_i_arbitrated; + logic port_mux_sel_ethernet_eth_rxctl_i_no_connection; + + assign port_mux_sel_ethernet_eth_rxctl_i_req[PORT_MUX_GROUP_MUXED_V_08_SEL_MUXED_V_08] = s_reg2hw.muxed_v_08_mux_sel.q == PAD_MUX_GROUP_MUXED_V_08_SEL_ETHERNET_RXCTL ? 1'b1 : 1'b0; + + lzc #( + .WIDTH(1), + .MODE(1'b0) + ) i_port_muxsel_ethernet_eth_rxctl_i_arbiter ( + .in_i(port_mux_sel_ethernet_eth_rxctl_i_req), + .cnt_o(port_mux_sel_ethernet_eth_rxctl_i_arbitrated), + .empty_o(port_mux_sel_ethernet_eth_rxctl_i_no_connection) + ); + + always_comb begin + if (port_mux_sel_ethernet_eth_rxctl_i_no_connection) begin + port_signals_pad2soc_o.ethernet.eth_rxctl_i = 1'b0; + end else begin + unique case (port_mux_sel_ethernet_eth_rxctl_i_arbitrated) + PORT_MUX_GROUP_MUXED_V_08_SEL_MUXED_V_08: begin + port_signals_pad2soc_o.ethernet.eth_rxctl_i = pads_to_mux_i.muxed_v_08.pad2chip; + end + default: begin + port_signals_pad2soc_o.ethernet.eth_rxctl_i = 1'b0; + end + endcase + end + end + + + // Port Signal eth_rxd_0_i + logic [0:0] port_mux_sel_ethernet_eth_rxd_0_i_req; + logic [PORT_MUX_GROUP_MUXED_V_09_SEL_WIDTH-1:0] port_mux_sel_ethernet_eth_rxd_0_i_arbitrated; + logic port_mux_sel_ethernet_eth_rxd_0_i_no_connection; + + assign port_mux_sel_ethernet_eth_rxd_0_i_req[PORT_MUX_GROUP_MUXED_V_09_SEL_MUXED_V_09] = s_reg2hw.muxed_v_09_mux_sel.q == PAD_MUX_GROUP_MUXED_V_09_SEL_ETHERNET_RXD_0 ? 1'b1 : 1'b0; + + lzc #( + .WIDTH(1), + .MODE(1'b0) + ) i_port_muxsel_ethernet_eth_rxd_0_i_arbiter ( + .in_i(port_mux_sel_ethernet_eth_rxd_0_i_req), + .cnt_o(port_mux_sel_ethernet_eth_rxd_0_i_arbitrated), + .empty_o(port_mux_sel_ethernet_eth_rxd_0_i_no_connection) + ); + + always_comb begin + if (port_mux_sel_ethernet_eth_rxd_0_i_no_connection) begin + port_signals_pad2soc_o.ethernet.eth_rxd_0_i = 1'b0; + end else begin + unique case (port_mux_sel_ethernet_eth_rxd_0_i_arbitrated) + PORT_MUX_GROUP_MUXED_V_09_SEL_MUXED_V_09: begin + port_signals_pad2soc_o.ethernet.eth_rxd_0_i = pads_to_mux_i.muxed_v_09.pad2chip; + end + default: begin + port_signals_pad2soc_o.ethernet.eth_rxd_0_i = 1'b0; + end + endcase + end + end + + + // Port Signal eth_rxd_1_i + logic [0:0] port_mux_sel_ethernet_eth_rxd_1_i_req; + logic [PORT_MUX_GROUP_MUXED_V_10_SEL_WIDTH-1:0] port_mux_sel_ethernet_eth_rxd_1_i_arbitrated; + logic port_mux_sel_ethernet_eth_rxd_1_i_no_connection; + + assign port_mux_sel_ethernet_eth_rxd_1_i_req[PORT_MUX_GROUP_MUXED_V_10_SEL_MUXED_V_10] = s_reg2hw.muxed_v_10_mux_sel.q == PAD_MUX_GROUP_MUXED_V_10_SEL_ETHERNET_RXD_1 ? 1'b1 : 1'b0; + + lzc #( + .WIDTH(1), + .MODE(1'b0) + ) i_port_muxsel_ethernet_eth_rxd_1_i_arbiter ( + .in_i(port_mux_sel_ethernet_eth_rxd_1_i_req), + .cnt_o(port_mux_sel_ethernet_eth_rxd_1_i_arbitrated), + .empty_o(port_mux_sel_ethernet_eth_rxd_1_i_no_connection) + ); + + always_comb begin + if (port_mux_sel_ethernet_eth_rxd_1_i_no_connection) begin + port_signals_pad2soc_o.ethernet.eth_rxd_1_i = 1'b0; + end else begin + unique case (port_mux_sel_ethernet_eth_rxd_1_i_arbitrated) + PORT_MUX_GROUP_MUXED_V_10_SEL_MUXED_V_10: begin + port_signals_pad2soc_o.ethernet.eth_rxd_1_i = pads_to_mux_i.muxed_v_10.pad2chip; + end + default: begin + port_signals_pad2soc_o.ethernet.eth_rxd_1_i = 1'b0; + end + endcase + end + end + + + // Port Signal eth_rxd_2_i + logic [0:0] port_mux_sel_ethernet_eth_rxd_2_i_req; + logic [PORT_MUX_GROUP_MUXED_V_11_SEL_WIDTH-1:0] port_mux_sel_ethernet_eth_rxd_2_i_arbitrated; + logic port_mux_sel_ethernet_eth_rxd_2_i_no_connection; + + assign port_mux_sel_ethernet_eth_rxd_2_i_req[PORT_MUX_GROUP_MUXED_V_11_SEL_MUXED_V_11] = s_reg2hw.muxed_v_11_mux_sel.q == PAD_MUX_GROUP_MUXED_V_11_SEL_ETHERNET_RXD_2 ? 1'b1 : 1'b0; + + lzc #( + .WIDTH(1), + .MODE(1'b0) + ) i_port_muxsel_ethernet_eth_rxd_2_i_arbiter ( + .in_i(port_mux_sel_ethernet_eth_rxd_2_i_req), + .cnt_o(port_mux_sel_ethernet_eth_rxd_2_i_arbitrated), + .empty_o(port_mux_sel_ethernet_eth_rxd_2_i_no_connection) + ); + + always_comb begin + if (port_mux_sel_ethernet_eth_rxd_2_i_no_connection) begin + port_signals_pad2soc_o.ethernet.eth_rxd_2_i = 1'b0; + end else begin + unique case (port_mux_sel_ethernet_eth_rxd_2_i_arbitrated) + PORT_MUX_GROUP_MUXED_V_11_SEL_MUXED_V_11: begin + port_signals_pad2soc_o.ethernet.eth_rxd_2_i = pads_to_mux_i.muxed_v_11.pad2chip; + end + default: begin + port_signals_pad2soc_o.ethernet.eth_rxd_2_i = 1'b0; + end + endcase + end + end + + + // Port Signal eth_rxd_3_i + logic [0:0] port_mux_sel_ethernet_eth_rxd_3_i_req; + logic [PORT_MUX_GROUP_MUXED_V_12_SEL_WIDTH-1:0] port_mux_sel_ethernet_eth_rxd_3_i_arbitrated; + logic port_mux_sel_ethernet_eth_rxd_3_i_no_connection; + + assign port_mux_sel_ethernet_eth_rxd_3_i_req[PORT_MUX_GROUP_MUXED_V_12_SEL_MUXED_V_12] = s_reg2hw.muxed_v_12_mux_sel.q == PAD_MUX_GROUP_MUXED_V_12_SEL_ETHERNET_RXD_3 ? 1'b1 : 1'b0; + + lzc #( + .WIDTH(1), + .MODE(1'b0) + ) i_port_muxsel_ethernet_eth_rxd_3_i_arbiter ( + .in_i(port_mux_sel_ethernet_eth_rxd_3_i_req), + .cnt_o(port_mux_sel_ethernet_eth_rxd_3_i_arbitrated), + .empty_o(port_mux_sel_ethernet_eth_rxd_3_i_no_connection) + ); + + always_comb begin + if (port_mux_sel_ethernet_eth_rxd_3_i_no_connection) begin + port_signals_pad2soc_o.ethernet.eth_rxd_3_i = 1'b0; + end else begin + unique case (port_mux_sel_ethernet_eth_rxd_3_i_arbitrated) + PORT_MUX_GROUP_MUXED_V_12_SEL_MUXED_V_12: begin + port_signals_pad2soc_o.ethernet.eth_rxd_3_i = pads_to_mux_i.muxed_v_12.pad2chip; + end + default: begin + port_signals_pad2soc_o.ethernet.eth_rxd_3_i = 1'b0; + end + endcase + end + end + + + + + + + + + // Port Signal eth_md_i + logic [0:0] port_mux_sel_ethernet_eth_md_i_req; + logic [PORT_MUX_GROUP_MUXED_H_01_SEL_WIDTH-1:0] port_mux_sel_ethernet_eth_md_i_arbitrated; + logic port_mux_sel_ethernet_eth_md_i_no_connection; + + assign port_mux_sel_ethernet_eth_md_i_req[PORT_MUX_GROUP_MUXED_H_01_SEL_MUXED_H_01] = s_reg2hw.muxed_h_01_mux_sel.q == PAD_MUX_GROUP_MUXED_H_01_SEL_ETHERNET_MD ? 1'b1 : 1'b0; + + lzc #( + .WIDTH(1), + .MODE(1'b0) + ) i_port_muxsel_ethernet_eth_md_i_arbiter ( + .in_i(port_mux_sel_ethernet_eth_md_i_req), + .cnt_o(port_mux_sel_ethernet_eth_md_i_arbitrated), + .empty_o(port_mux_sel_ethernet_eth_md_i_no_connection) + ); + + always_comb begin + if (port_mux_sel_ethernet_eth_md_i_no_connection) begin + port_signals_pad2soc_o.ethernet.eth_md_i = 1'b0; + end else begin + unique case (port_mux_sel_ethernet_eth_md_i_arbitrated) + PORT_MUX_GROUP_MUXED_H_01_SEL_MUXED_H_01: begin + port_signals_pad2soc_o.ethernet.eth_md_i = pads_to_mux_i.muxed_h_01.pad2chip; + end + default: begin + port_signals_pad2soc_o.ethernet.eth_md_i = 1'b0; + end + endcase + end + end + + + + // Port Group can + + // Port Signal can_rx_i + logic [0:0] port_mux_sel_can_can_rx_i_req; + logic [PORT_MUX_GROUP_MUXED_V_00_SEL_WIDTH-1:0] port_mux_sel_can_can_rx_i_arbitrated; + logic port_mux_sel_can_can_rx_i_no_connection; + + assign port_mux_sel_can_can_rx_i_req[PORT_MUX_GROUP_MUXED_V_00_SEL_MUXED_V_00] = s_reg2hw.muxed_v_00_mux_sel.q == PAD_MUX_GROUP_MUXED_V_00_SEL_CAN_RX ? 1'b1 : 1'b0; + + lzc #( + .WIDTH(1), + .MODE(1'b0) + ) i_port_muxsel_can_can_rx_i_arbiter ( + .in_i(port_mux_sel_can_can_rx_i_req), + .cnt_o(port_mux_sel_can_can_rx_i_arbitrated), + .empty_o(port_mux_sel_can_can_rx_i_no_connection) + ); + + always_comb begin + if (port_mux_sel_can_can_rx_i_no_connection) begin + port_signals_pad2soc_o.can.can_rx_i = 1'b0; + end else begin + unique case (port_mux_sel_can_can_rx_i_arbitrated) + PORT_MUX_GROUP_MUXED_V_00_SEL_MUXED_V_00: begin + port_signals_pad2soc_o.can.can_rx_i = pads_to_mux_i.muxed_v_00.pad2chip; + end + default: begin + port_signals_pad2soc_o.can.can_rx_i = 1'b0; + end + endcase + end + end + + + // Port Group serial_link + + // Port Signal slink_rcv_clk_i + logic [0:0] port_mux_sel_serial_link_slink_rcv_clk_i_req; + logic [PORT_MUX_GROUP_MUXED_V_04_SEL_WIDTH-1:0] port_mux_sel_serial_link_slink_rcv_clk_i_arbitrated; + logic port_mux_sel_serial_link_slink_rcv_clk_i_no_connection; + + assign port_mux_sel_serial_link_slink_rcv_clk_i_req[PORT_MUX_GROUP_MUXED_V_04_SEL_MUXED_V_04] = s_reg2hw.muxed_v_04_mux_sel.q == PAD_MUX_GROUP_MUXED_V_04_SEL_SERIAL_LINK_RCV_CLK_I ? 1'b1 : 1'b0; + + lzc #( + .WIDTH(1), + .MODE(1'b0) + ) i_port_muxsel_serial_link_slink_rcv_clk_i_arbiter ( + .in_i(port_mux_sel_serial_link_slink_rcv_clk_i_req), + .cnt_o(port_mux_sel_serial_link_slink_rcv_clk_i_arbitrated), + .empty_o(port_mux_sel_serial_link_slink_rcv_clk_i_no_connection) + ); + + always_comb begin + if (port_mux_sel_serial_link_slink_rcv_clk_i_no_connection) begin + port_signals_pad2soc_o.serial_link.slink_rcv_clk_i = 1'b1; + end else begin + unique case (port_mux_sel_serial_link_slink_rcv_clk_i_arbitrated) + PORT_MUX_GROUP_MUXED_V_04_SEL_MUXED_V_04: begin + port_signals_pad2soc_o.serial_link.slink_rcv_clk_i = pads_to_mux_i.muxed_v_04.pad2chip; + end + default: begin + port_signals_pad2soc_o.serial_link.slink_rcv_clk_i = 1'b1; + end + endcase + end + end + + + // Port Signal slink_0_i + logic [0:0] port_mux_sel_serial_link_slink_0_i_req; + logic [PORT_MUX_GROUP_MUXED_V_05_SEL_WIDTH-1:0] port_mux_sel_serial_link_slink_0_i_arbitrated; + logic port_mux_sel_serial_link_slink_0_i_no_connection; + + assign port_mux_sel_serial_link_slink_0_i_req[PORT_MUX_GROUP_MUXED_V_05_SEL_MUXED_V_05] = s_reg2hw.muxed_v_05_mux_sel.q == PAD_MUX_GROUP_MUXED_V_05_SEL_SERIAL_LINK_I_0 ? 1'b1 : 1'b0; + + lzc #( + .WIDTH(1), + .MODE(1'b0) + ) i_port_muxsel_serial_link_slink_0_i_arbiter ( + .in_i(port_mux_sel_serial_link_slink_0_i_req), + .cnt_o(port_mux_sel_serial_link_slink_0_i_arbitrated), + .empty_o(port_mux_sel_serial_link_slink_0_i_no_connection) + ); + + always_comb begin + if (port_mux_sel_serial_link_slink_0_i_no_connection) begin + port_signals_pad2soc_o.serial_link.slink_0_i = 1'b1; + end else begin + unique case (port_mux_sel_serial_link_slink_0_i_arbitrated) + PORT_MUX_GROUP_MUXED_V_05_SEL_MUXED_V_05: begin + port_signals_pad2soc_o.serial_link.slink_0_i = pads_to_mux_i.muxed_v_05.pad2chip; + end + default: begin + port_signals_pad2soc_o.serial_link.slink_0_i = 1'b1; + end + endcase + end + end + + + // Port Signal slink_1_i + logic [0:0] port_mux_sel_serial_link_slink_1_i_req; + logic [PORT_MUX_GROUP_MUXED_V_06_SEL_WIDTH-1:0] port_mux_sel_serial_link_slink_1_i_arbitrated; + logic port_mux_sel_serial_link_slink_1_i_no_connection; + + assign port_mux_sel_serial_link_slink_1_i_req[PORT_MUX_GROUP_MUXED_V_06_SEL_MUXED_V_06] = s_reg2hw.muxed_v_06_mux_sel.q == PAD_MUX_GROUP_MUXED_V_06_SEL_SERIAL_LINK_I_1 ? 1'b1 : 1'b0; + + lzc #( + .WIDTH(1), + .MODE(1'b0) + ) i_port_muxsel_serial_link_slink_1_i_arbiter ( + .in_i(port_mux_sel_serial_link_slink_1_i_req), + .cnt_o(port_mux_sel_serial_link_slink_1_i_arbitrated), + .empty_o(port_mux_sel_serial_link_slink_1_i_no_connection) + ); + + always_comb begin + if (port_mux_sel_serial_link_slink_1_i_no_connection) begin + port_signals_pad2soc_o.serial_link.slink_1_i = 1'b1; + end else begin + unique case (port_mux_sel_serial_link_slink_1_i_arbitrated) + PORT_MUX_GROUP_MUXED_V_06_SEL_MUXED_V_06: begin + port_signals_pad2soc_o.serial_link.slink_1_i = pads_to_mux_i.muxed_v_06.pad2chip; + end + default: begin + port_signals_pad2soc_o.serial_link.slink_1_i = 1'b1; + end + endcase + end + end + + + // Port Signal slink_2_i + logic [0:0] port_mux_sel_serial_link_slink_2_i_req; + logic [PORT_MUX_GROUP_MUXED_V_07_SEL_WIDTH-1:0] port_mux_sel_serial_link_slink_2_i_arbitrated; + logic port_mux_sel_serial_link_slink_2_i_no_connection; + + assign port_mux_sel_serial_link_slink_2_i_req[PORT_MUX_GROUP_MUXED_V_07_SEL_MUXED_V_07] = s_reg2hw.muxed_v_07_mux_sel.q == PAD_MUX_GROUP_MUXED_V_07_SEL_SERIAL_LINK_I_2 ? 1'b1 : 1'b0; + + lzc #( + .WIDTH(1), + .MODE(1'b0) + ) i_port_muxsel_serial_link_slink_2_i_arbiter ( + .in_i(port_mux_sel_serial_link_slink_2_i_req), + .cnt_o(port_mux_sel_serial_link_slink_2_i_arbitrated), + .empty_o(port_mux_sel_serial_link_slink_2_i_no_connection) + ); + + always_comb begin + if (port_mux_sel_serial_link_slink_2_i_no_connection) begin + port_signals_pad2soc_o.serial_link.slink_2_i = 1'b1; + end else begin + unique case (port_mux_sel_serial_link_slink_2_i_arbitrated) + PORT_MUX_GROUP_MUXED_V_07_SEL_MUXED_V_07: begin + port_signals_pad2soc_o.serial_link.slink_2_i = pads_to_mux_i.muxed_v_07.pad2chip; + end + default: begin + port_signals_pad2soc_o.serial_link.slink_2_i = 1'b1; + end + endcase + end + end + + + // Port Signal slink_3_i + logic [0:0] port_mux_sel_serial_link_slink_3_i_req; + logic [PORT_MUX_GROUP_MUXED_V_08_SEL_WIDTH-1:0] port_mux_sel_serial_link_slink_3_i_arbitrated; + logic port_mux_sel_serial_link_slink_3_i_no_connection; + + assign port_mux_sel_serial_link_slink_3_i_req[PORT_MUX_GROUP_MUXED_V_08_SEL_MUXED_V_08] = s_reg2hw.muxed_v_08_mux_sel.q == PAD_MUX_GROUP_MUXED_V_08_SEL_SERIAL_LINK_I_3 ? 1'b1 : 1'b0; + + lzc #( + .WIDTH(1), + .MODE(1'b0) + ) i_port_muxsel_serial_link_slink_3_i_arbiter ( + .in_i(port_mux_sel_serial_link_slink_3_i_req), + .cnt_o(port_mux_sel_serial_link_slink_3_i_arbitrated), + .empty_o(port_mux_sel_serial_link_slink_3_i_no_connection) + ); + + always_comb begin + if (port_mux_sel_serial_link_slink_3_i_no_connection) begin + port_signals_pad2soc_o.serial_link.slink_3_i = 1'b1; + end else begin + unique case (port_mux_sel_serial_link_slink_3_i_arbitrated) + PORT_MUX_GROUP_MUXED_V_08_SEL_MUXED_V_08: begin + port_signals_pad2soc_o.serial_link.slink_3_i = pads_to_mux_i.muxed_v_08.pad2chip; + end + default: begin + port_signals_pad2soc_o.serial_link.slink_3_i = 1'b1; + end + endcase + end + end + + + // Port Signal slink_4_i + logic [0:0] port_mux_sel_serial_link_slink_4_i_req; + logic [PORT_MUX_GROUP_MUXED_V_09_SEL_WIDTH-1:0] port_mux_sel_serial_link_slink_4_i_arbitrated; + logic port_mux_sel_serial_link_slink_4_i_no_connection; + + assign port_mux_sel_serial_link_slink_4_i_req[PORT_MUX_GROUP_MUXED_V_09_SEL_MUXED_V_09] = s_reg2hw.muxed_v_09_mux_sel.q == PAD_MUX_GROUP_MUXED_V_09_SEL_SERIAL_LINK_I_4 ? 1'b1 : 1'b0; + + lzc #( + .WIDTH(1), + .MODE(1'b0) + ) i_port_muxsel_serial_link_slink_4_i_arbiter ( + .in_i(port_mux_sel_serial_link_slink_4_i_req), + .cnt_o(port_mux_sel_serial_link_slink_4_i_arbitrated), + .empty_o(port_mux_sel_serial_link_slink_4_i_no_connection) + ); + + always_comb begin + if (port_mux_sel_serial_link_slink_4_i_no_connection) begin + port_signals_pad2soc_o.serial_link.slink_4_i = 1'b1; + end else begin + unique case (port_mux_sel_serial_link_slink_4_i_arbitrated) + PORT_MUX_GROUP_MUXED_V_09_SEL_MUXED_V_09: begin + port_signals_pad2soc_o.serial_link.slink_4_i = pads_to_mux_i.muxed_v_09.pad2chip; + end + default: begin + port_signals_pad2soc_o.serial_link.slink_4_i = 1'b1; + end + endcase + end + end + + + // Port Signal slink_5_i + logic [0:0] port_mux_sel_serial_link_slink_5_i_req; + logic [PORT_MUX_GROUP_MUXED_V_10_SEL_WIDTH-1:0] port_mux_sel_serial_link_slink_5_i_arbitrated; + logic port_mux_sel_serial_link_slink_5_i_no_connection; + + assign port_mux_sel_serial_link_slink_5_i_req[PORT_MUX_GROUP_MUXED_V_10_SEL_MUXED_V_10] = s_reg2hw.muxed_v_10_mux_sel.q == PAD_MUX_GROUP_MUXED_V_10_SEL_SERIAL_LINK_I_5 ? 1'b1 : 1'b0; + + lzc #( + .WIDTH(1), + .MODE(1'b0) + ) i_port_muxsel_serial_link_slink_5_i_arbiter ( + .in_i(port_mux_sel_serial_link_slink_5_i_req), + .cnt_o(port_mux_sel_serial_link_slink_5_i_arbitrated), + .empty_o(port_mux_sel_serial_link_slink_5_i_no_connection) + ); + + always_comb begin + if (port_mux_sel_serial_link_slink_5_i_no_connection) begin + port_signals_pad2soc_o.serial_link.slink_5_i = 1'b1; + end else begin + unique case (port_mux_sel_serial_link_slink_5_i_arbitrated) + PORT_MUX_GROUP_MUXED_V_10_SEL_MUXED_V_10: begin + port_signals_pad2soc_o.serial_link.slink_5_i = pads_to_mux_i.muxed_v_10.pad2chip; + end + default: begin + port_signals_pad2soc_o.serial_link.slink_5_i = 1'b1; + end + endcase + end + end + + + // Port Signal slink_6_i + logic [0:0] port_mux_sel_serial_link_slink_6_i_req; + logic [PORT_MUX_GROUP_MUXED_V_11_SEL_WIDTH-1:0] port_mux_sel_serial_link_slink_6_i_arbitrated; + logic port_mux_sel_serial_link_slink_6_i_no_connection; + + assign port_mux_sel_serial_link_slink_6_i_req[PORT_MUX_GROUP_MUXED_V_11_SEL_MUXED_V_11] = s_reg2hw.muxed_v_11_mux_sel.q == PAD_MUX_GROUP_MUXED_V_11_SEL_SERIAL_LINK_I_6 ? 1'b1 : 1'b0; + + lzc #( + .WIDTH(1), + .MODE(1'b0) + ) i_port_muxsel_serial_link_slink_6_i_arbiter ( + .in_i(port_mux_sel_serial_link_slink_6_i_req), + .cnt_o(port_mux_sel_serial_link_slink_6_i_arbitrated), + .empty_o(port_mux_sel_serial_link_slink_6_i_no_connection) + ); + + always_comb begin + if (port_mux_sel_serial_link_slink_6_i_no_connection) begin + port_signals_pad2soc_o.serial_link.slink_6_i = 1'b1; + end else begin + unique case (port_mux_sel_serial_link_slink_6_i_arbitrated) + PORT_MUX_GROUP_MUXED_V_11_SEL_MUXED_V_11: begin + port_signals_pad2soc_o.serial_link.slink_6_i = pads_to_mux_i.muxed_v_11.pad2chip; + end + default: begin + port_signals_pad2soc_o.serial_link.slink_6_i = 1'b1; + end + endcase + end + end + + + // Port Signal slink_7_i + logic [0:0] port_mux_sel_serial_link_slink_7_i_req; + logic [PORT_MUX_GROUP_MUXED_V_12_SEL_WIDTH-1:0] port_mux_sel_serial_link_slink_7_i_arbitrated; + logic port_mux_sel_serial_link_slink_7_i_no_connection; + + assign port_mux_sel_serial_link_slink_7_i_req[PORT_MUX_GROUP_MUXED_V_12_SEL_MUXED_V_12] = s_reg2hw.muxed_v_12_mux_sel.q == PAD_MUX_GROUP_MUXED_V_12_SEL_SERIAL_LINK_I_7 ? 1'b1 : 1'b0; + + lzc #( + .WIDTH(1), + .MODE(1'b0) + ) i_port_muxsel_serial_link_slink_7_i_arbiter ( + .in_i(port_mux_sel_serial_link_slink_7_i_req), + .cnt_o(port_mux_sel_serial_link_slink_7_i_arbitrated), + .empty_o(port_mux_sel_serial_link_slink_7_i_no_connection) + ); + + always_comb begin + if (port_mux_sel_serial_link_slink_7_i_no_connection) begin + port_signals_pad2soc_o.serial_link.slink_7_i = 1'b1; + end else begin + unique case (port_mux_sel_serial_link_slink_7_i_arbitrated) + PORT_MUX_GROUP_MUXED_V_12_SEL_MUXED_V_12: begin + port_signals_pad2soc_o.serial_link.slink_7_i = pads_to_mux_i.muxed_v_12.pad2chip; + end + default: begin + port_signals_pad2soc_o.serial_link.slink_7_i = 1'b1; + end + endcase + end + end + + + + + + + + + + + // Port Group i2c + + // Port Signal i2c_sda_i + logic [0:0] port_mux_sel_i2c_i2c_sda_i_req; + logic [PORT_MUX_GROUP_MUXED_V_00_SEL_WIDTH-1:0] port_mux_sel_i2c_i2c_sda_i_arbitrated; + logic port_mux_sel_i2c_i2c_sda_i_no_connection; + + assign port_mux_sel_i2c_i2c_sda_i_req[PORT_MUX_GROUP_MUXED_V_00_SEL_MUXED_V_00] = s_reg2hw.muxed_v_00_mux_sel.q == PAD_MUX_GROUP_MUXED_V_00_SEL_I2C_SDA ? 1'b1 : 1'b0; + + lzc #( + .WIDTH(1), + .MODE(1'b0) + ) i_port_muxsel_i2c_i2c_sda_i_arbiter ( + .in_i(port_mux_sel_i2c_i2c_sda_i_req), + .cnt_o(port_mux_sel_i2c_i2c_sda_i_arbitrated), + .empty_o(port_mux_sel_i2c_i2c_sda_i_no_connection) + ); + + always_comb begin + if (port_mux_sel_i2c_i2c_sda_i_no_connection) begin + port_signals_pad2soc_o.i2c.i2c_sda_i = 1'b0; + end else begin + unique case (port_mux_sel_i2c_i2c_sda_i_arbitrated) + PORT_MUX_GROUP_MUXED_V_00_SEL_MUXED_V_00: begin + port_signals_pad2soc_o.i2c.i2c_sda_i = pads_to_mux_i.muxed_v_00.pad2chip; + end + default: begin + port_signals_pad2soc_o.i2c.i2c_sda_i = 1'b0; + end + endcase + end + end + + + // Port Signal i2c_scl_i + logic [0:0] port_mux_sel_i2c_i2c_scl_i_req; + logic [PORT_MUX_GROUP_MUXED_V_01_SEL_WIDTH-1:0] port_mux_sel_i2c_i2c_scl_i_arbitrated; + logic port_mux_sel_i2c_i2c_scl_i_no_connection; + + assign port_mux_sel_i2c_i2c_scl_i_req[PORT_MUX_GROUP_MUXED_V_01_SEL_MUXED_V_01] = s_reg2hw.muxed_v_01_mux_sel.q == PAD_MUX_GROUP_MUXED_V_01_SEL_I2C_SCL ? 1'b1 : 1'b0; + + lzc #( + .WIDTH(1), + .MODE(1'b0) + ) i_port_muxsel_i2c_i2c_scl_i_arbiter ( + .in_i(port_mux_sel_i2c_i2c_scl_i_req), + .cnt_o(port_mux_sel_i2c_i2c_scl_i_arbitrated), + .empty_o(port_mux_sel_i2c_i2c_scl_i_no_connection) + ); + + always_comb begin + if (port_mux_sel_i2c_i2c_scl_i_no_connection) begin + port_signals_pad2soc_o.i2c.i2c_scl_i = 1'b0; + end else begin + unique case (port_mux_sel_i2c_i2c_scl_i_arbitrated) + PORT_MUX_GROUP_MUXED_V_01_SEL_MUXED_V_01: begin + port_signals_pad2soc_o.i2c.i2c_scl_i = pads_to_mux_i.muxed_v_01.pad2chip; + end + default: begin + port_signals_pad2soc_o.i2c.i2c_scl_i = 1'b0; + end + endcase + end + end + + // Port Group tc + + // Port Signal tc_active_i + logic [0:0] port_mux_sel_tc_tc_active_i_req; + logic [PORT_MUX_GROUP_MUXED_V_07_SEL_WIDTH-1:0] port_mux_sel_tc_tc_active_i_arbitrated; + logic port_mux_sel_tc_tc_active_i_no_connection; + + assign port_mux_sel_tc_tc_active_i_req[PORT_MUX_GROUP_MUXED_V_07_SEL_MUXED_V_07] = s_reg2hw.muxed_v_07_mux_sel.q == PAD_MUX_GROUP_MUXED_V_07_SEL_TC_ACTIVE ? 1'b1 : 1'b0; + + lzc #( + .WIDTH(1), + .MODE(1'b0) + ) i_port_muxsel_tc_tc_active_i_arbiter ( + .in_i(port_mux_sel_tc_tc_active_i_req), + .cnt_o(port_mux_sel_tc_tc_active_i_arbitrated), + .empty_o(port_mux_sel_tc_tc_active_i_no_connection) + ); + + always_comb begin + if (port_mux_sel_tc_tc_active_i_no_connection) begin + port_signals_pad2soc_o.tc.tc_active_i = 1'b0; + end else begin + unique case (port_mux_sel_tc_tc_active_i_arbitrated) + PORT_MUX_GROUP_MUXED_V_07_SEL_MUXED_V_07: begin + port_signals_pad2soc_o.tc.tc_active_i = pads_to_mux_i.muxed_v_07.pad2chip; + end + default: begin + port_signals_pad2soc_o.tc.tc_active_i = 1'b0; + end + endcase + end + end + + + // Port Signal tc_clk_i + logic [0:0] port_mux_sel_tc_tc_clk_i_req; + logic [PORT_MUX_GROUP_MUXED_V_08_SEL_WIDTH-1:0] port_mux_sel_tc_tc_clk_i_arbitrated; + logic port_mux_sel_tc_tc_clk_i_no_connection; + + assign port_mux_sel_tc_tc_clk_i_req[PORT_MUX_GROUP_MUXED_V_08_SEL_MUXED_V_08] = s_reg2hw.muxed_v_08_mux_sel.q == PAD_MUX_GROUP_MUXED_V_08_SEL_TC_CLK ? 1'b1 : 1'b0; + + lzc #( + .WIDTH(1), + .MODE(1'b0) + ) i_port_muxsel_tc_tc_clk_i_arbiter ( + .in_i(port_mux_sel_tc_tc_clk_i_req), + .cnt_o(port_mux_sel_tc_tc_clk_i_arbitrated), + .empty_o(port_mux_sel_tc_tc_clk_i_no_connection) + ); + + always_comb begin + if (port_mux_sel_tc_tc_clk_i_no_connection) begin + port_signals_pad2soc_o.tc.tc_clk_i = 1'b0; + end else begin + unique case (port_mux_sel_tc_tc_clk_i_arbitrated) + PORT_MUX_GROUP_MUXED_V_08_SEL_MUXED_V_08: begin + port_signals_pad2soc_o.tc.tc_clk_i = pads_to_mux_i.muxed_v_08.pad2chip; + end + default: begin + port_signals_pad2soc_o.tc.tc_clk_i = 1'b0; + end + endcase + end + end + + + // Port Signal tc_data_i + logic [0:0] port_mux_sel_tc_tc_data_i_req; + logic [PORT_MUX_GROUP_MUXED_V_09_SEL_WIDTH-1:0] port_mux_sel_tc_tc_data_i_arbitrated; + logic port_mux_sel_tc_tc_data_i_no_connection; + + assign port_mux_sel_tc_tc_data_i_req[PORT_MUX_GROUP_MUXED_V_09_SEL_MUXED_V_09] = s_reg2hw.muxed_v_09_mux_sel.q == PAD_MUX_GROUP_MUXED_V_09_SEL_TC_DATA ? 1'b1 : 1'b0; + + lzc #( + .WIDTH(1), + .MODE(1'b0) + ) i_port_muxsel_tc_tc_data_i_arbiter ( + .in_i(port_mux_sel_tc_tc_data_i_req), + .cnt_o(port_mux_sel_tc_tc_data_i_arbitrated), + .empty_o(port_mux_sel_tc_tc_data_i_no_connection) + ); + + always_comb begin + if (port_mux_sel_tc_tc_data_i_no_connection) begin + port_signals_pad2soc_o.tc.tc_data_i = 1'b0; + end else begin + unique case (port_mux_sel_tc_tc_data_i_arbitrated) + PORT_MUX_GROUP_MUXED_V_09_SEL_MUXED_V_09: begin + port_signals_pad2soc_o.tc.tc_data_i = pads_to_mux_i.muxed_v_09.pad2chip; + end + default: begin + port_signals_pad2soc_o.tc.tc_data_i = 1'b0; + end + endcase + end + end + + // Port Group ptme + + + + + // Port Signal ptme_ext_clk_i + logic [0:0] port_mux_sel_ptme_ptme_ext_clk_i_req; + logic [PORT_MUX_GROUP_MUXED_V_13_SEL_WIDTH-1:0] port_mux_sel_ptme_ptme_ext_clk_i_arbitrated; + logic port_mux_sel_ptme_ptme_ext_clk_i_no_connection; + + assign port_mux_sel_ptme_ptme_ext_clk_i_req[PORT_MUX_GROUP_MUXED_V_13_SEL_MUXED_V_13] = s_reg2hw.muxed_v_13_mux_sel.q == PAD_MUX_GROUP_MUXED_V_13_SEL_PTME_EXT_CLK ? 1'b1 : 1'b0; + + lzc #( + .WIDTH(1), + .MODE(1'b0) + ) i_port_muxsel_ptme_ptme_ext_clk_i_arbiter ( + .in_i(port_mux_sel_ptme_ptme_ext_clk_i_req), + .cnt_o(port_mux_sel_ptme_ptme_ext_clk_i_arbitrated), + .empty_o(port_mux_sel_ptme_ptme_ext_clk_i_no_connection) + ); + + always_comb begin + if (port_mux_sel_ptme_ptme_ext_clk_i_no_connection) begin + port_signals_pad2soc_o.ptme.ptme_ext_clk_i = 1'b0; + end else begin + unique case (port_mux_sel_ptme_ptme_ext_clk_i_arbitrated) + PORT_MUX_GROUP_MUXED_V_13_SEL_MUXED_V_13: begin + port_signals_pad2soc_o.ptme.ptme_ext_clk_i = pads_to_mux_i.muxed_v_13.pad2chip; + end + default: begin + port_signals_pad2soc_o.ptme.ptme_ext_clk_i = 1'b0; + end + endcase + end + end + + // Port Group obt + + // Port Signal obt_ext_clk_i + logic [0:0] port_mux_sel_obt_obt_ext_clk_i_req; + logic [PORT_MUX_GROUP_MUXED_H_03_SEL_WIDTH-1:0] port_mux_sel_obt_obt_ext_clk_i_arbitrated; + logic port_mux_sel_obt_obt_ext_clk_i_no_connection; + + assign port_mux_sel_obt_obt_ext_clk_i_req[PORT_MUX_GROUP_MUXED_H_03_SEL_MUXED_H_03] = s_reg2hw.muxed_h_03_mux_sel.q == PAD_MUX_GROUP_MUXED_H_03_SEL_OBT_EXT_CLK ? 1'b1 : 1'b0; + + lzc #( + .WIDTH(1), + .MODE(1'b0) + ) i_port_muxsel_obt_obt_ext_clk_i_arbiter ( + .in_i(port_mux_sel_obt_obt_ext_clk_i_req), + .cnt_o(port_mux_sel_obt_obt_ext_clk_i_arbitrated), + .empty_o(port_mux_sel_obt_obt_ext_clk_i_no_connection) + ); + + always_comb begin + if (port_mux_sel_obt_obt_ext_clk_i_no_connection) begin + port_signals_pad2soc_o.obt.obt_ext_clk_i = 1'b0; + end else begin + unique case (port_mux_sel_obt_obt_ext_clk_i_arbitrated) + PORT_MUX_GROUP_MUXED_H_03_SEL_MUXED_H_03: begin + port_signals_pad2soc_o.obt.obt_ext_clk_i = pads_to_mux_i.muxed_h_03.pad2chip; + end + default: begin + port_signals_pad2soc_o.obt.obt_ext_clk_i = 1'b0; + end + endcase + end + end + + // Port Group spi_ot + + + + // Port Signal spih_ot_sd_0_i + logic [0:0] port_mux_sel_spi_ot_spih_ot_sd_0_i_req; + logic [PORT_MUX_GROUP_MUXED_V_02_SEL_WIDTH-1:0] port_mux_sel_spi_ot_spih_ot_sd_0_i_arbitrated; + logic port_mux_sel_spi_ot_spih_ot_sd_0_i_no_connection; + + assign port_mux_sel_spi_ot_spih_ot_sd_0_i_req[PORT_MUX_GROUP_MUXED_V_02_SEL_MUXED_V_02] = s_reg2hw.muxed_v_02_mux_sel.q == PAD_MUX_GROUP_MUXED_V_02_SEL_SPI_OT_SD_0 ? 1'b1 : 1'b0; + + lzc #( + .WIDTH(1), + .MODE(1'b0) + ) i_port_muxsel_spi_ot_spih_ot_sd_0_i_arbiter ( + .in_i(port_mux_sel_spi_ot_spih_ot_sd_0_i_req), + .cnt_o(port_mux_sel_spi_ot_spih_ot_sd_0_i_arbitrated), + .empty_o(port_mux_sel_spi_ot_spih_ot_sd_0_i_no_connection) + ); + + always_comb begin + if (port_mux_sel_spi_ot_spih_ot_sd_0_i_no_connection) begin + port_signals_pad2soc_o.spi_ot.spih_ot_sd_0_i = 1'b0; + end else begin + unique case (port_mux_sel_spi_ot_spih_ot_sd_0_i_arbitrated) + PORT_MUX_GROUP_MUXED_V_02_SEL_MUXED_V_02: begin + port_signals_pad2soc_o.spi_ot.spih_ot_sd_0_i = pads_to_mux_i.muxed_v_02.pad2chip; + end + default: begin + port_signals_pad2soc_o.spi_ot.spih_ot_sd_0_i = 1'b0; + end + endcase + end + end + + + // Port Signal spih_ot_sd_1_i + logic [0:0] port_mux_sel_spi_ot_spih_ot_sd_1_i_req; + logic [PORT_MUX_GROUP_MUXED_V_03_SEL_WIDTH-1:0] port_mux_sel_spi_ot_spih_ot_sd_1_i_arbitrated; + logic port_mux_sel_spi_ot_spih_ot_sd_1_i_no_connection; + + assign port_mux_sel_spi_ot_spih_ot_sd_1_i_req[PORT_MUX_GROUP_MUXED_V_03_SEL_MUXED_V_03] = s_reg2hw.muxed_v_03_mux_sel.q == PAD_MUX_GROUP_MUXED_V_03_SEL_SPI_OT_SD_1 ? 1'b1 : 1'b0; + + lzc #( + .WIDTH(1), + .MODE(1'b0) + ) i_port_muxsel_spi_ot_spih_ot_sd_1_i_arbiter ( + .in_i(port_mux_sel_spi_ot_spih_ot_sd_1_i_req), + .cnt_o(port_mux_sel_spi_ot_spih_ot_sd_1_i_arbitrated), + .empty_o(port_mux_sel_spi_ot_spih_ot_sd_1_i_no_connection) + ); + + always_comb begin + if (port_mux_sel_spi_ot_spih_ot_sd_1_i_no_connection) begin + port_signals_pad2soc_o.spi_ot.spih_ot_sd_1_i = 1'b0; + end else begin + unique case (port_mux_sel_spi_ot_spih_ot_sd_1_i_arbitrated) + PORT_MUX_GROUP_MUXED_V_03_SEL_MUXED_V_03: begin + port_signals_pad2soc_o.spi_ot.spih_ot_sd_1_i = pads_to_mux_i.muxed_v_03.pad2chip; + end + default: begin + port_signals_pad2soc_o.spi_ot.spih_ot_sd_1_i = 1'b0; + end + endcase + end + end + + + // Port Signal spih_ot_sd_2_i + logic [0:0] port_mux_sel_spi_ot_spih_ot_sd_2_i_req; + logic [PORT_MUX_GROUP_MUXED_V_04_SEL_WIDTH-1:0] port_mux_sel_spi_ot_spih_ot_sd_2_i_arbitrated; + logic port_mux_sel_spi_ot_spih_ot_sd_2_i_no_connection; + + assign port_mux_sel_spi_ot_spih_ot_sd_2_i_req[PORT_MUX_GROUP_MUXED_V_04_SEL_MUXED_V_04] = s_reg2hw.muxed_v_04_mux_sel.q == PAD_MUX_GROUP_MUXED_V_04_SEL_SPI_OT_SD_2 ? 1'b1 : 1'b0; + + lzc #( + .WIDTH(1), + .MODE(1'b0) + ) i_port_muxsel_spi_ot_spih_ot_sd_2_i_arbiter ( + .in_i(port_mux_sel_spi_ot_spih_ot_sd_2_i_req), + .cnt_o(port_mux_sel_spi_ot_spih_ot_sd_2_i_arbitrated), + .empty_o(port_mux_sel_spi_ot_spih_ot_sd_2_i_no_connection) + ); + + always_comb begin + if (port_mux_sel_spi_ot_spih_ot_sd_2_i_no_connection) begin + port_signals_pad2soc_o.spi_ot.spih_ot_sd_2_i = 1'b0; + end else begin + unique case (port_mux_sel_spi_ot_spih_ot_sd_2_i_arbitrated) + PORT_MUX_GROUP_MUXED_V_04_SEL_MUXED_V_04: begin + port_signals_pad2soc_o.spi_ot.spih_ot_sd_2_i = pads_to_mux_i.muxed_v_04.pad2chip; + end + default: begin + port_signals_pad2soc_o.spi_ot.spih_ot_sd_2_i = 1'b0; + end + endcase + end + end + + + // Port Signal spih_ot_sd_3_i + logic [0:0] port_mux_sel_spi_ot_spih_ot_sd_3_i_req; + logic [PORT_MUX_GROUP_MUXED_V_05_SEL_WIDTH-1:0] port_mux_sel_spi_ot_spih_ot_sd_3_i_arbitrated; + logic port_mux_sel_spi_ot_spih_ot_sd_3_i_no_connection; + + assign port_mux_sel_spi_ot_spih_ot_sd_3_i_req[PORT_MUX_GROUP_MUXED_V_05_SEL_MUXED_V_05] = s_reg2hw.muxed_v_05_mux_sel.q == PAD_MUX_GROUP_MUXED_V_05_SEL_SPI_OT_SD_3 ? 1'b1 : 1'b0; + + lzc #( + .WIDTH(1), + .MODE(1'b0) + ) i_port_muxsel_spi_ot_spih_ot_sd_3_i_arbiter ( + .in_i(port_mux_sel_spi_ot_spih_ot_sd_3_i_req), + .cnt_o(port_mux_sel_spi_ot_spih_ot_sd_3_i_arbitrated), + .empty_o(port_mux_sel_spi_ot_spih_ot_sd_3_i_no_connection) + ); + + always_comb begin + if (port_mux_sel_spi_ot_spih_ot_sd_3_i_no_connection) begin + port_signals_pad2soc_o.spi_ot.spih_ot_sd_3_i = 1'b0; + end else begin + unique case (port_mux_sel_spi_ot_spih_ot_sd_3_i_arbitrated) + PORT_MUX_GROUP_MUXED_V_05_SEL_MUXED_V_05: begin + port_signals_pad2soc_o.spi_ot.spih_ot_sd_3_i = pads_to_mux_i.muxed_v_05.pad2chip; + end + default: begin + port_signals_pad2soc_o.spi_ot.spih_ot_sd_3_i = 1'b0; + end + endcase + end + end + + // Port Group pll + + // Port Signal pll_0_i + logic [0:0] port_mux_sel_pll_pll_0_i_req; + logic [PORT_MUX_GROUP_MUXED_V_07_SEL_WIDTH-1:0] port_mux_sel_pll_pll_0_i_arbitrated; + logic port_mux_sel_pll_pll_0_i_no_connection; + + assign port_mux_sel_pll_pll_0_i_req[PORT_MUX_GROUP_MUXED_V_07_SEL_MUXED_V_07] = s_reg2hw.muxed_v_07_mux_sel.q == PAD_MUX_GROUP_MUXED_V_07_SEL_PLL_IO_0 ? 1'b1 : 1'b0; + + lzc #( + .WIDTH(1), + .MODE(1'b0) + ) i_port_muxsel_pll_pll_0_i_arbiter ( + .in_i(port_mux_sel_pll_pll_0_i_req), + .cnt_o(port_mux_sel_pll_pll_0_i_arbitrated), + .empty_o(port_mux_sel_pll_pll_0_i_no_connection) + ); + + always_comb begin + if (port_mux_sel_pll_pll_0_i_no_connection) begin + port_signals_pad2soc_o.pll.pll_0_i = 1'b0; + end else begin + unique case (port_mux_sel_pll_pll_0_i_arbitrated) + PORT_MUX_GROUP_MUXED_V_07_SEL_MUXED_V_07: begin + port_signals_pad2soc_o.pll.pll_0_i = pads_to_mux_i.muxed_v_07.pad2chip; + end + default: begin + port_signals_pad2soc_o.pll.pll_0_i = 1'b0; + end + endcase + end + end + + + // Port Signal pll_1_i + logic [0:0] port_mux_sel_pll_pll_1_i_req; + logic [PORT_MUX_GROUP_MUXED_V_08_SEL_WIDTH-1:0] port_mux_sel_pll_pll_1_i_arbitrated; + logic port_mux_sel_pll_pll_1_i_no_connection; + + assign port_mux_sel_pll_pll_1_i_req[PORT_MUX_GROUP_MUXED_V_08_SEL_MUXED_V_08] = s_reg2hw.muxed_v_08_mux_sel.q == PAD_MUX_GROUP_MUXED_V_08_SEL_PLL_IO_1 ? 1'b1 : 1'b0; + + lzc #( + .WIDTH(1), + .MODE(1'b0) + ) i_port_muxsel_pll_pll_1_i_arbiter ( + .in_i(port_mux_sel_pll_pll_1_i_req), + .cnt_o(port_mux_sel_pll_pll_1_i_arbitrated), + .empty_o(port_mux_sel_pll_pll_1_i_no_connection) + ); + + always_comb begin + if (port_mux_sel_pll_pll_1_i_no_connection) begin + port_signals_pad2soc_o.pll.pll_1_i = 1'b0; + end else begin + unique case (port_mux_sel_pll_pll_1_i_arbitrated) + PORT_MUX_GROUP_MUXED_V_08_SEL_MUXED_V_08: begin + port_signals_pad2soc_o.pll.pll_1_i = pads_to_mux_i.muxed_v_08.pad2chip; + end + default: begin + port_signals_pad2soc_o.pll.pll_1_i = 1'b0; + end + endcase + end + end + + + // Port Signal pll_2_i + logic [0:0] port_mux_sel_pll_pll_2_i_req; + logic [PORT_MUX_GROUP_MUXED_V_09_SEL_WIDTH-1:0] port_mux_sel_pll_pll_2_i_arbitrated; + logic port_mux_sel_pll_pll_2_i_no_connection; + + assign port_mux_sel_pll_pll_2_i_req[PORT_MUX_GROUP_MUXED_V_09_SEL_MUXED_V_09] = s_reg2hw.muxed_v_09_mux_sel.q == PAD_MUX_GROUP_MUXED_V_09_SEL_PLL_IO_2 ? 1'b1 : 1'b0; + + lzc #( + .WIDTH(1), + .MODE(1'b0) + ) i_port_muxsel_pll_pll_2_i_arbiter ( + .in_i(port_mux_sel_pll_pll_2_i_req), + .cnt_o(port_mux_sel_pll_pll_2_i_arbitrated), + .empty_o(port_mux_sel_pll_pll_2_i_no_connection) + ); + + always_comb begin + if (port_mux_sel_pll_pll_2_i_no_connection) begin + port_signals_pad2soc_o.pll.pll_2_i = 1'b0; + end else begin + unique case (port_mux_sel_pll_pll_2_i_arbitrated) + PORT_MUX_GROUP_MUXED_V_09_SEL_MUXED_V_09: begin + port_signals_pad2soc_o.pll.pll_2_i = pads_to_mux_i.muxed_v_09.pad2chip; + end + default: begin + port_signals_pad2soc_o.pll.pll_2_i = 1'b0; + end + endcase + end + end + + + // Port Signal pll_3_i + logic [0:0] port_mux_sel_pll_pll_3_i_req; + logic [PORT_MUX_GROUP_MUXED_V_10_SEL_WIDTH-1:0] port_mux_sel_pll_pll_3_i_arbitrated; + logic port_mux_sel_pll_pll_3_i_no_connection; + + assign port_mux_sel_pll_pll_3_i_req[PORT_MUX_GROUP_MUXED_V_10_SEL_MUXED_V_10] = s_reg2hw.muxed_v_10_mux_sel.q == PAD_MUX_GROUP_MUXED_V_10_SEL_PLL_IO_3 ? 1'b1 : 1'b0; + + lzc #( + .WIDTH(1), + .MODE(1'b0) + ) i_port_muxsel_pll_pll_3_i_arbiter ( + .in_i(port_mux_sel_pll_pll_3_i_req), + .cnt_o(port_mux_sel_pll_pll_3_i_arbitrated), + .empty_o(port_mux_sel_pll_pll_3_i_no_connection) + ); + + always_comb begin + if (port_mux_sel_pll_pll_3_i_no_connection) begin + port_signals_pad2soc_o.pll.pll_3_i = 1'b0; + end else begin + unique case (port_mux_sel_pll_pll_3_i_arbitrated) + PORT_MUX_GROUP_MUXED_V_10_SEL_MUXED_V_10: begin + port_signals_pad2soc_o.pll.pll_3_i = pads_to_mux_i.muxed_v_10.pad2chip; + end + default: begin + port_signals_pad2soc_o.pll.pll_3_i = 1'b0; + end + endcase + end + end + + + // Port Signal pll_4_i + logic [0:0] port_mux_sel_pll_pll_4_i_req; + logic [PORT_MUX_GROUP_MUXED_V_11_SEL_WIDTH-1:0] port_mux_sel_pll_pll_4_i_arbitrated; + logic port_mux_sel_pll_pll_4_i_no_connection; + + assign port_mux_sel_pll_pll_4_i_req[PORT_MUX_GROUP_MUXED_V_11_SEL_MUXED_V_11] = s_reg2hw.muxed_v_11_mux_sel.q == PAD_MUX_GROUP_MUXED_V_11_SEL_PLL_IO_4 ? 1'b1 : 1'b0; + + lzc #( + .WIDTH(1), + .MODE(1'b0) + ) i_port_muxsel_pll_pll_4_i_arbiter ( + .in_i(port_mux_sel_pll_pll_4_i_req), + .cnt_o(port_mux_sel_pll_pll_4_i_arbitrated), + .empty_o(port_mux_sel_pll_pll_4_i_no_connection) + ); + + always_comb begin + if (port_mux_sel_pll_pll_4_i_no_connection) begin + port_signals_pad2soc_o.pll.pll_4_i = 1'b0; + end else begin + unique case (port_mux_sel_pll_pll_4_i_arbitrated) + PORT_MUX_GROUP_MUXED_V_11_SEL_MUXED_V_11: begin + port_signals_pad2soc_o.pll.pll_4_i = pads_to_mux_i.muxed_v_11.pad2chip; + end + default: begin + port_signals_pad2soc_o.pll.pll_4_i = 1'b0; + end + endcase + end + end + + + // Port Signal pll_5_i + logic [0:0] port_mux_sel_pll_pll_5_i_req; + logic [PORT_MUX_GROUP_MUXED_V_12_SEL_WIDTH-1:0] port_mux_sel_pll_pll_5_i_arbitrated; + logic port_mux_sel_pll_pll_5_i_no_connection; + + assign port_mux_sel_pll_pll_5_i_req[PORT_MUX_GROUP_MUXED_V_12_SEL_MUXED_V_12] = s_reg2hw.muxed_v_12_mux_sel.q == PAD_MUX_GROUP_MUXED_V_12_SEL_PLL_IO_5 ? 1'b1 : 1'b0; + + lzc #( + .WIDTH(1), + .MODE(1'b0) + ) i_port_muxsel_pll_pll_5_i_arbiter ( + .in_i(port_mux_sel_pll_pll_5_i_req), + .cnt_o(port_mux_sel_pll_pll_5_i_arbitrated), + .empty_o(port_mux_sel_pll_pll_5_i_no_connection) + ); + + always_comb begin + if (port_mux_sel_pll_pll_5_i_no_connection) begin + port_signals_pad2soc_o.pll.pll_5_i = 1'b0; + end else begin + unique case (port_mux_sel_pll_pll_5_i_arbitrated) + PORT_MUX_GROUP_MUXED_V_12_SEL_MUXED_V_12: begin + port_signals_pad2soc_o.pll.pll_5_i = pads_to_mux_i.muxed_v_12.pad2chip; + end + default: begin + port_signals_pad2soc_o.pll.pll_5_i = 1'b0; + end + endcase + end + end + + + // Port Signal pll_6_i + logic [0:0] port_mux_sel_pll_pll_6_i_req; + logic [PORT_MUX_GROUP_MUXED_V_13_SEL_WIDTH-1:0] port_mux_sel_pll_pll_6_i_arbitrated; + logic port_mux_sel_pll_pll_6_i_no_connection; + + assign port_mux_sel_pll_pll_6_i_req[PORT_MUX_GROUP_MUXED_V_13_SEL_MUXED_V_13] = s_reg2hw.muxed_v_13_mux_sel.q == PAD_MUX_GROUP_MUXED_V_13_SEL_PLL_IO_6 ? 1'b1 : 1'b0; + + lzc #( + .WIDTH(1), + .MODE(1'b0) + ) i_port_muxsel_pll_pll_6_i_arbiter ( + .in_i(port_mux_sel_pll_pll_6_i_req), + .cnt_o(port_mux_sel_pll_pll_6_i_arbitrated), + .empty_o(port_mux_sel_pll_pll_6_i_no_connection) + ); + + always_comb begin + if (port_mux_sel_pll_pll_6_i_no_connection) begin + port_signals_pad2soc_o.pll.pll_6_i = 1'b0; + end else begin + unique case (port_mux_sel_pll_pll_6_i_arbitrated) + PORT_MUX_GROUP_MUXED_V_13_SEL_MUXED_V_13: begin + port_signals_pad2soc_o.pll.pll_6_i = pads_to_mux_i.muxed_v_13.pad2chip; + end + default: begin + port_signals_pad2soc_o.pll.pll_6_i = 1'b0; + end + endcase + end + end + + // Port Group gpio + + // Port Signal gpio_v_0_i + logic [0:0] port_mux_sel_gpio_gpio_v_0_i_req; + logic [PORT_MUX_GROUP_MUXED_V_00_SEL_WIDTH-1:0] port_mux_sel_gpio_gpio_v_0_i_arbitrated; + logic port_mux_sel_gpio_gpio_v_0_i_no_connection; + + assign port_mux_sel_gpio_gpio_v_0_i_req[PORT_MUX_GROUP_MUXED_V_00_SEL_MUXED_V_00] = s_reg2hw.muxed_v_00_mux_sel.q == PAD_MUX_GROUP_MUXED_V_00_SEL_GPIO_IO_V_0 ? 1'b1 : 1'b0; + + lzc #( + .WIDTH(1), + .MODE(1'b0) + ) i_port_muxsel_gpio_gpio_v_0_i_arbiter ( + .in_i(port_mux_sel_gpio_gpio_v_0_i_req), + .cnt_o(port_mux_sel_gpio_gpio_v_0_i_arbitrated), + .empty_o(port_mux_sel_gpio_gpio_v_0_i_no_connection) + ); + + always_comb begin + if (port_mux_sel_gpio_gpio_v_0_i_no_connection) begin + port_signals_pad2soc_o.gpio.gpio_v_0_i = 1'b0; + end else begin + unique case (port_mux_sel_gpio_gpio_v_0_i_arbitrated) + PORT_MUX_GROUP_MUXED_V_00_SEL_MUXED_V_00: begin + port_signals_pad2soc_o.gpio.gpio_v_0_i = pads_to_mux_i.muxed_v_00.pad2chip; + end + default: begin + port_signals_pad2soc_o.gpio.gpio_v_0_i = 1'b0; + end + endcase + end + end + + + // Port Signal gpio_v_1_i + logic [0:0] port_mux_sel_gpio_gpio_v_1_i_req; + logic [PORT_MUX_GROUP_MUXED_V_01_SEL_WIDTH-1:0] port_mux_sel_gpio_gpio_v_1_i_arbitrated; + logic port_mux_sel_gpio_gpio_v_1_i_no_connection; + + assign port_mux_sel_gpio_gpio_v_1_i_req[PORT_MUX_GROUP_MUXED_V_01_SEL_MUXED_V_01] = s_reg2hw.muxed_v_01_mux_sel.q == PAD_MUX_GROUP_MUXED_V_01_SEL_GPIO_IO_V_1 ? 1'b1 : 1'b0; + + lzc #( + .WIDTH(1), + .MODE(1'b0) + ) i_port_muxsel_gpio_gpio_v_1_i_arbiter ( + .in_i(port_mux_sel_gpio_gpio_v_1_i_req), + .cnt_o(port_mux_sel_gpio_gpio_v_1_i_arbitrated), + .empty_o(port_mux_sel_gpio_gpio_v_1_i_no_connection) + ); + + always_comb begin + if (port_mux_sel_gpio_gpio_v_1_i_no_connection) begin + port_signals_pad2soc_o.gpio.gpio_v_1_i = 1'b0; + end else begin + unique case (port_mux_sel_gpio_gpio_v_1_i_arbitrated) + PORT_MUX_GROUP_MUXED_V_01_SEL_MUXED_V_01: begin + port_signals_pad2soc_o.gpio.gpio_v_1_i = pads_to_mux_i.muxed_v_01.pad2chip; + end + default: begin + port_signals_pad2soc_o.gpio.gpio_v_1_i = 1'b0; + end + endcase + end + end + + + // Port Signal gpio_v_2_i + logic [0:0] port_mux_sel_gpio_gpio_v_2_i_req; + logic [PORT_MUX_GROUP_MUXED_V_02_SEL_WIDTH-1:0] port_mux_sel_gpio_gpio_v_2_i_arbitrated; + logic port_mux_sel_gpio_gpio_v_2_i_no_connection; + + assign port_mux_sel_gpio_gpio_v_2_i_req[PORT_MUX_GROUP_MUXED_V_02_SEL_MUXED_V_02] = s_reg2hw.muxed_v_02_mux_sel.q == PAD_MUX_GROUP_MUXED_V_02_SEL_GPIO_IO_V_2 ? 1'b1 : 1'b0; + + lzc #( + .WIDTH(1), + .MODE(1'b0) + ) i_port_muxsel_gpio_gpio_v_2_i_arbiter ( + .in_i(port_mux_sel_gpio_gpio_v_2_i_req), + .cnt_o(port_mux_sel_gpio_gpio_v_2_i_arbitrated), + .empty_o(port_mux_sel_gpio_gpio_v_2_i_no_connection) + ); + + always_comb begin + if (port_mux_sel_gpio_gpio_v_2_i_no_connection) begin + port_signals_pad2soc_o.gpio.gpio_v_2_i = 1'b0; + end else begin + unique case (port_mux_sel_gpio_gpio_v_2_i_arbitrated) + PORT_MUX_GROUP_MUXED_V_02_SEL_MUXED_V_02: begin + port_signals_pad2soc_o.gpio.gpio_v_2_i = pads_to_mux_i.muxed_v_02.pad2chip; + end + default: begin + port_signals_pad2soc_o.gpio.gpio_v_2_i = 1'b0; + end + endcase + end + end + + + // Port Signal gpio_v_3_i + logic [0:0] port_mux_sel_gpio_gpio_v_3_i_req; + logic [PORT_MUX_GROUP_MUXED_V_03_SEL_WIDTH-1:0] port_mux_sel_gpio_gpio_v_3_i_arbitrated; + logic port_mux_sel_gpio_gpio_v_3_i_no_connection; + + assign port_mux_sel_gpio_gpio_v_3_i_req[PORT_MUX_GROUP_MUXED_V_03_SEL_MUXED_V_03] = s_reg2hw.muxed_v_03_mux_sel.q == PAD_MUX_GROUP_MUXED_V_03_SEL_GPIO_IO_V_3 ? 1'b1 : 1'b0; + + lzc #( + .WIDTH(1), + .MODE(1'b0) + ) i_port_muxsel_gpio_gpio_v_3_i_arbiter ( + .in_i(port_mux_sel_gpio_gpio_v_3_i_req), + .cnt_o(port_mux_sel_gpio_gpio_v_3_i_arbitrated), + .empty_o(port_mux_sel_gpio_gpio_v_3_i_no_connection) + ); + + always_comb begin + if (port_mux_sel_gpio_gpio_v_3_i_no_connection) begin + port_signals_pad2soc_o.gpio.gpio_v_3_i = 1'b0; + end else begin + unique case (port_mux_sel_gpio_gpio_v_3_i_arbitrated) + PORT_MUX_GROUP_MUXED_V_03_SEL_MUXED_V_03: begin + port_signals_pad2soc_o.gpio.gpio_v_3_i = pads_to_mux_i.muxed_v_03.pad2chip; + end + default: begin + port_signals_pad2soc_o.gpio.gpio_v_3_i = 1'b0; + end + endcase + end + end + + + // Port Signal gpio_v_4_i + logic [0:0] port_mux_sel_gpio_gpio_v_4_i_req; + logic [PORT_MUX_GROUP_MUXED_V_04_SEL_WIDTH-1:0] port_mux_sel_gpio_gpio_v_4_i_arbitrated; + logic port_mux_sel_gpio_gpio_v_4_i_no_connection; + + assign port_mux_sel_gpio_gpio_v_4_i_req[PORT_MUX_GROUP_MUXED_V_04_SEL_MUXED_V_04] = s_reg2hw.muxed_v_04_mux_sel.q == PAD_MUX_GROUP_MUXED_V_04_SEL_GPIO_IO_V_4 ? 1'b1 : 1'b0; + + lzc #( + .WIDTH(1), + .MODE(1'b0) + ) i_port_muxsel_gpio_gpio_v_4_i_arbiter ( + .in_i(port_mux_sel_gpio_gpio_v_4_i_req), + .cnt_o(port_mux_sel_gpio_gpio_v_4_i_arbitrated), + .empty_o(port_mux_sel_gpio_gpio_v_4_i_no_connection) + ); + + always_comb begin + if (port_mux_sel_gpio_gpio_v_4_i_no_connection) begin + port_signals_pad2soc_o.gpio.gpio_v_4_i = 1'b0; + end else begin + unique case (port_mux_sel_gpio_gpio_v_4_i_arbitrated) + PORT_MUX_GROUP_MUXED_V_04_SEL_MUXED_V_04: begin + port_signals_pad2soc_o.gpio.gpio_v_4_i = pads_to_mux_i.muxed_v_04.pad2chip; + end + default: begin + port_signals_pad2soc_o.gpio.gpio_v_4_i = 1'b0; + end + endcase + end + end + + + // Port Signal gpio_v_5_i + logic [0:0] port_mux_sel_gpio_gpio_v_5_i_req; + logic [PORT_MUX_GROUP_MUXED_V_05_SEL_WIDTH-1:0] port_mux_sel_gpio_gpio_v_5_i_arbitrated; + logic port_mux_sel_gpio_gpio_v_5_i_no_connection; + + assign port_mux_sel_gpio_gpio_v_5_i_req[PORT_MUX_GROUP_MUXED_V_05_SEL_MUXED_V_05] = s_reg2hw.muxed_v_05_mux_sel.q == PAD_MUX_GROUP_MUXED_V_05_SEL_GPIO_IO_V_5 ? 1'b1 : 1'b0; + + lzc #( + .WIDTH(1), + .MODE(1'b0) + ) i_port_muxsel_gpio_gpio_v_5_i_arbiter ( + .in_i(port_mux_sel_gpio_gpio_v_5_i_req), + .cnt_o(port_mux_sel_gpio_gpio_v_5_i_arbitrated), + .empty_o(port_mux_sel_gpio_gpio_v_5_i_no_connection) + ); + + always_comb begin + if (port_mux_sel_gpio_gpio_v_5_i_no_connection) begin + port_signals_pad2soc_o.gpio.gpio_v_5_i = 1'b0; + end else begin + unique case (port_mux_sel_gpio_gpio_v_5_i_arbitrated) + PORT_MUX_GROUP_MUXED_V_05_SEL_MUXED_V_05: begin + port_signals_pad2soc_o.gpio.gpio_v_5_i = pads_to_mux_i.muxed_v_05.pad2chip; + end + default: begin + port_signals_pad2soc_o.gpio.gpio_v_5_i = 1'b0; + end + endcase + end + end + + + // Port Signal gpio_v_6_i + logic [0:0] port_mux_sel_gpio_gpio_v_6_i_req; + logic [PORT_MUX_GROUP_MUXED_V_06_SEL_WIDTH-1:0] port_mux_sel_gpio_gpio_v_6_i_arbitrated; + logic port_mux_sel_gpio_gpio_v_6_i_no_connection; + + assign port_mux_sel_gpio_gpio_v_6_i_req[PORT_MUX_GROUP_MUXED_V_06_SEL_MUXED_V_06] = s_reg2hw.muxed_v_06_mux_sel.q == PAD_MUX_GROUP_MUXED_V_06_SEL_GPIO_IO_V_6 ? 1'b1 : 1'b0; + + lzc #( + .WIDTH(1), + .MODE(1'b0) + ) i_port_muxsel_gpio_gpio_v_6_i_arbiter ( + .in_i(port_mux_sel_gpio_gpio_v_6_i_req), + .cnt_o(port_mux_sel_gpio_gpio_v_6_i_arbitrated), + .empty_o(port_mux_sel_gpio_gpio_v_6_i_no_connection) + ); + + always_comb begin + if (port_mux_sel_gpio_gpio_v_6_i_no_connection) begin + port_signals_pad2soc_o.gpio.gpio_v_6_i = 1'b0; + end else begin + unique case (port_mux_sel_gpio_gpio_v_6_i_arbitrated) + PORT_MUX_GROUP_MUXED_V_06_SEL_MUXED_V_06: begin + port_signals_pad2soc_o.gpio.gpio_v_6_i = pads_to_mux_i.muxed_v_06.pad2chip; + end + default: begin + port_signals_pad2soc_o.gpio.gpio_v_6_i = 1'b0; + end + endcase + end + end + + + // Port Signal gpio_v_7_i + logic [0:0] port_mux_sel_gpio_gpio_v_7_i_req; + logic [PORT_MUX_GROUP_MUXED_V_07_SEL_WIDTH-1:0] port_mux_sel_gpio_gpio_v_7_i_arbitrated; + logic port_mux_sel_gpio_gpio_v_7_i_no_connection; + + assign port_mux_sel_gpio_gpio_v_7_i_req[PORT_MUX_GROUP_MUXED_V_07_SEL_MUXED_V_07] = s_reg2hw.muxed_v_07_mux_sel.q == PAD_MUX_GROUP_MUXED_V_07_SEL_GPIO_IO_V_7 ? 1'b1 : 1'b0; + + lzc #( + .WIDTH(1), + .MODE(1'b0) + ) i_port_muxsel_gpio_gpio_v_7_i_arbiter ( + .in_i(port_mux_sel_gpio_gpio_v_7_i_req), + .cnt_o(port_mux_sel_gpio_gpio_v_7_i_arbitrated), + .empty_o(port_mux_sel_gpio_gpio_v_7_i_no_connection) + ); + + always_comb begin + if (port_mux_sel_gpio_gpio_v_7_i_no_connection) begin + port_signals_pad2soc_o.gpio.gpio_v_7_i = 1'b0; + end else begin + unique case (port_mux_sel_gpio_gpio_v_7_i_arbitrated) + PORT_MUX_GROUP_MUXED_V_07_SEL_MUXED_V_07: begin + port_signals_pad2soc_o.gpio.gpio_v_7_i = pads_to_mux_i.muxed_v_07.pad2chip; + end + default: begin + port_signals_pad2soc_o.gpio.gpio_v_7_i = 1'b0; + end + endcase + end + end + + + // Port Signal gpio_v_8_i + logic [0:0] port_mux_sel_gpio_gpio_v_8_i_req; + logic [PORT_MUX_GROUP_MUXED_V_08_SEL_WIDTH-1:0] port_mux_sel_gpio_gpio_v_8_i_arbitrated; + logic port_mux_sel_gpio_gpio_v_8_i_no_connection; + + assign port_mux_sel_gpio_gpio_v_8_i_req[PORT_MUX_GROUP_MUXED_V_08_SEL_MUXED_V_08] = s_reg2hw.muxed_v_08_mux_sel.q == PAD_MUX_GROUP_MUXED_V_08_SEL_GPIO_IO_V_8 ? 1'b1 : 1'b0; + + lzc #( + .WIDTH(1), + .MODE(1'b0) + ) i_port_muxsel_gpio_gpio_v_8_i_arbiter ( + .in_i(port_mux_sel_gpio_gpio_v_8_i_req), + .cnt_o(port_mux_sel_gpio_gpio_v_8_i_arbitrated), + .empty_o(port_mux_sel_gpio_gpio_v_8_i_no_connection) + ); + + always_comb begin + if (port_mux_sel_gpio_gpio_v_8_i_no_connection) begin + port_signals_pad2soc_o.gpio.gpio_v_8_i = 1'b0; + end else begin + unique case (port_mux_sel_gpio_gpio_v_8_i_arbitrated) + PORT_MUX_GROUP_MUXED_V_08_SEL_MUXED_V_08: begin + port_signals_pad2soc_o.gpio.gpio_v_8_i = pads_to_mux_i.muxed_v_08.pad2chip; + end + default: begin + port_signals_pad2soc_o.gpio.gpio_v_8_i = 1'b0; + end + endcase + end + end + + + // Port Signal gpio_v_9_i + logic [0:0] port_mux_sel_gpio_gpio_v_9_i_req; + logic [PORT_MUX_GROUP_MUXED_V_09_SEL_WIDTH-1:0] port_mux_sel_gpio_gpio_v_9_i_arbitrated; + logic port_mux_sel_gpio_gpio_v_9_i_no_connection; + + assign port_mux_sel_gpio_gpio_v_9_i_req[PORT_MUX_GROUP_MUXED_V_09_SEL_MUXED_V_09] = s_reg2hw.muxed_v_09_mux_sel.q == PAD_MUX_GROUP_MUXED_V_09_SEL_GPIO_IO_V_9 ? 1'b1 : 1'b0; + + lzc #( + .WIDTH(1), + .MODE(1'b0) + ) i_port_muxsel_gpio_gpio_v_9_i_arbiter ( + .in_i(port_mux_sel_gpio_gpio_v_9_i_req), + .cnt_o(port_mux_sel_gpio_gpio_v_9_i_arbitrated), + .empty_o(port_mux_sel_gpio_gpio_v_9_i_no_connection) + ); + + always_comb begin + if (port_mux_sel_gpio_gpio_v_9_i_no_connection) begin + port_signals_pad2soc_o.gpio.gpio_v_9_i = 1'b0; + end else begin + unique case (port_mux_sel_gpio_gpio_v_9_i_arbitrated) + PORT_MUX_GROUP_MUXED_V_09_SEL_MUXED_V_09: begin + port_signals_pad2soc_o.gpio.gpio_v_9_i = pads_to_mux_i.muxed_v_09.pad2chip; + end + default: begin + port_signals_pad2soc_o.gpio.gpio_v_9_i = 1'b0; + end + endcase + end + end + + + // Port Signal gpio_v_10_i + logic [0:0] port_mux_sel_gpio_gpio_v_10_i_req; + logic [PORT_MUX_GROUP_MUXED_V_10_SEL_WIDTH-1:0] port_mux_sel_gpio_gpio_v_10_i_arbitrated; + logic port_mux_sel_gpio_gpio_v_10_i_no_connection; + + assign port_mux_sel_gpio_gpio_v_10_i_req[PORT_MUX_GROUP_MUXED_V_10_SEL_MUXED_V_10] = s_reg2hw.muxed_v_10_mux_sel.q == PAD_MUX_GROUP_MUXED_V_10_SEL_GPIO_IO_V_10 ? 1'b1 : 1'b0; + + lzc #( + .WIDTH(1), + .MODE(1'b0) + ) i_port_muxsel_gpio_gpio_v_10_i_arbiter ( + .in_i(port_mux_sel_gpio_gpio_v_10_i_req), + .cnt_o(port_mux_sel_gpio_gpio_v_10_i_arbitrated), + .empty_o(port_mux_sel_gpio_gpio_v_10_i_no_connection) + ); + + always_comb begin + if (port_mux_sel_gpio_gpio_v_10_i_no_connection) begin + port_signals_pad2soc_o.gpio.gpio_v_10_i = 1'b0; + end else begin + unique case (port_mux_sel_gpio_gpio_v_10_i_arbitrated) + PORT_MUX_GROUP_MUXED_V_10_SEL_MUXED_V_10: begin + port_signals_pad2soc_o.gpio.gpio_v_10_i = pads_to_mux_i.muxed_v_10.pad2chip; + end + default: begin + port_signals_pad2soc_o.gpio.gpio_v_10_i = 1'b0; + end + endcase + end + end + + + // Port Signal gpio_v_11_i + logic [0:0] port_mux_sel_gpio_gpio_v_11_i_req; + logic [PORT_MUX_GROUP_MUXED_V_11_SEL_WIDTH-1:0] port_mux_sel_gpio_gpio_v_11_i_arbitrated; + logic port_mux_sel_gpio_gpio_v_11_i_no_connection; + + assign port_mux_sel_gpio_gpio_v_11_i_req[PORT_MUX_GROUP_MUXED_V_11_SEL_MUXED_V_11] = s_reg2hw.muxed_v_11_mux_sel.q == PAD_MUX_GROUP_MUXED_V_11_SEL_GPIO_IO_V_11 ? 1'b1 : 1'b0; + + lzc #( + .WIDTH(1), + .MODE(1'b0) + ) i_port_muxsel_gpio_gpio_v_11_i_arbiter ( + .in_i(port_mux_sel_gpio_gpio_v_11_i_req), + .cnt_o(port_mux_sel_gpio_gpio_v_11_i_arbitrated), + .empty_o(port_mux_sel_gpio_gpio_v_11_i_no_connection) + ); + + always_comb begin + if (port_mux_sel_gpio_gpio_v_11_i_no_connection) begin + port_signals_pad2soc_o.gpio.gpio_v_11_i = 1'b0; + end else begin + unique case (port_mux_sel_gpio_gpio_v_11_i_arbitrated) + PORT_MUX_GROUP_MUXED_V_11_SEL_MUXED_V_11: begin + port_signals_pad2soc_o.gpio.gpio_v_11_i = pads_to_mux_i.muxed_v_11.pad2chip; + end + default: begin + port_signals_pad2soc_o.gpio.gpio_v_11_i = 1'b0; + end + endcase + end + end + + + // Port Signal gpio_v_12_i + logic [0:0] port_mux_sel_gpio_gpio_v_12_i_req; + logic [PORT_MUX_GROUP_MUXED_V_12_SEL_WIDTH-1:0] port_mux_sel_gpio_gpio_v_12_i_arbitrated; + logic port_mux_sel_gpio_gpio_v_12_i_no_connection; + + assign port_mux_sel_gpio_gpio_v_12_i_req[PORT_MUX_GROUP_MUXED_V_12_SEL_MUXED_V_12] = s_reg2hw.muxed_v_12_mux_sel.q == PAD_MUX_GROUP_MUXED_V_12_SEL_GPIO_IO_V_12 ? 1'b1 : 1'b0; + + lzc #( + .WIDTH(1), + .MODE(1'b0) + ) i_port_muxsel_gpio_gpio_v_12_i_arbiter ( + .in_i(port_mux_sel_gpio_gpio_v_12_i_req), + .cnt_o(port_mux_sel_gpio_gpio_v_12_i_arbitrated), + .empty_o(port_mux_sel_gpio_gpio_v_12_i_no_connection) + ); + + always_comb begin + if (port_mux_sel_gpio_gpio_v_12_i_no_connection) begin + port_signals_pad2soc_o.gpio.gpio_v_12_i = 1'b0; + end else begin + unique case (port_mux_sel_gpio_gpio_v_12_i_arbitrated) + PORT_MUX_GROUP_MUXED_V_12_SEL_MUXED_V_12: begin + port_signals_pad2soc_o.gpio.gpio_v_12_i = pads_to_mux_i.muxed_v_12.pad2chip; + end + default: begin + port_signals_pad2soc_o.gpio.gpio_v_12_i = 1'b0; + end + endcase + end + end + + + // Port Signal gpio_v_13_i + logic [0:0] port_mux_sel_gpio_gpio_v_13_i_req; + logic [PORT_MUX_GROUP_MUXED_V_13_SEL_WIDTH-1:0] port_mux_sel_gpio_gpio_v_13_i_arbitrated; + logic port_mux_sel_gpio_gpio_v_13_i_no_connection; + + assign port_mux_sel_gpio_gpio_v_13_i_req[PORT_MUX_GROUP_MUXED_V_13_SEL_MUXED_V_13] = s_reg2hw.muxed_v_13_mux_sel.q == PAD_MUX_GROUP_MUXED_V_13_SEL_GPIO_IO_V_13 ? 1'b1 : 1'b0; + + lzc #( + .WIDTH(1), + .MODE(1'b0) + ) i_port_muxsel_gpio_gpio_v_13_i_arbiter ( + .in_i(port_mux_sel_gpio_gpio_v_13_i_req), + .cnt_o(port_mux_sel_gpio_gpio_v_13_i_arbitrated), + .empty_o(port_mux_sel_gpio_gpio_v_13_i_no_connection) + ); + + always_comb begin + if (port_mux_sel_gpio_gpio_v_13_i_no_connection) begin + port_signals_pad2soc_o.gpio.gpio_v_13_i = 1'b0; + end else begin + unique case (port_mux_sel_gpio_gpio_v_13_i_arbitrated) + PORT_MUX_GROUP_MUXED_V_13_SEL_MUXED_V_13: begin + port_signals_pad2soc_o.gpio.gpio_v_13_i = pads_to_mux_i.muxed_v_13.pad2chip; + end + default: begin + port_signals_pad2soc_o.gpio.gpio_v_13_i = 1'b0; + end + endcase + end + end + + + // Port Signal gpio_v_14_i + logic [0:0] port_mux_sel_gpio_gpio_v_14_i_req; + logic [PORT_MUX_GROUP_MUXED_V_14_SEL_WIDTH-1:0] port_mux_sel_gpio_gpio_v_14_i_arbitrated; + logic port_mux_sel_gpio_gpio_v_14_i_no_connection; + + assign port_mux_sel_gpio_gpio_v_14_i_req[PORT_MUX_GROUP_MUXED_V_14_SEL_MUXED_V_14] = s_reg2hw.muxed_v_14_mux_sel.q == PAD_MUX_GROUP_MUXED_V_14_SEL_GPIO_IO_V_14 ? 1'b1 : 1'b0; + + lzc #( + .WIDTH(1), + .MODE(1'b0) + ) i_port_muxsel_gpio_gpio_v_14_i_arbiter ( + .in_i(port_mux_sel_gpio_gpio_v_14_i_req), + .cnt_o(port_mux_sel_gpio_gpio_v_14_i_arbitrated), + .empty_o(port_mux_sel_gpio_gpio_v_14_i_no_connection) + ); + + always_comb begin + if (port_mux_sel_gpio_gpio_v_14_i_no_connection) begin + port_signals_pad2soc_o.gpio.gpio_v_14_i = 1'b0; + end else begin + unique case (port_mux_sel_gpio_gpio_v_14_i_arbitrated) + PORT_MUX_GROUP_MUXED_V_14_SEL_MUXED_V_14: begin + port_signals_pad2soc_o.gpio.gpio_v_14_i = pads_to_mux_i.muxed_v_14.pad2chip; + end + default: begin + port_signals_pad2soc_o.gpio.gpio_v_14_i = 1'b0; + end + endcase + end + end + + + // Port Signal gpio_v_15_i + logic [0:0] port_mux_sel_gpio_gpio_v_15_i_req; + logic [PORT_MUX_GROUP_MUXED_V_15_SEL_WIDTH-1:0] port_mux_sel_gpio_gpio_v_15_i_arbitrated; + logic port_mux_sel_gpio_gpio_v_15_i_no_connection; + + assign port_mux_sel_gpio_gpio_v_15_i_req[PORT_MUX_GROUP_MUXED_V_15_SEL_MUXED_V_15] = s_reg2hw.muxed_v_15_mux_sel.q == PAD_MUX_GROUP_MUXED_V_15_SEL_GPIO_IO_V_15 ? 1'b1 : 1'b0; + + lzc #( + .WIDTH(1), + .MODE(1'b0) + ) i_port_muxsel_gpio_gpio_v_15_i_arbiter ( + .in_i(port_mux_sel_gpio_gpio_v_15_i_req), + .cnt_o(port_mux_sel_gpio_gpio_v_15_i_arbitrated), + .empty_o(port_mux_sel_gpio_gpio_v_15_i_no_connection) + ); + + always_comb begin + if (port_mux_sel_gpio_gpio_v_15_i_no_connection) begin + port_signals_pad2soc_o.gpio.gpio_v_15_i = 1'b0; + end else begin + unique case (port_mux_sel_gpio_gpio_v_15_i_arbitrated) + PORT_MUX_GROUP_MUXED_V_15_SEL_MUXED_V_15: begin + port_signals_pad2soc_o.gpio.gpio_v_15_i = pads_to_mux_i.muxed_v_15.pad2chip; + end + default: begin + port_signals_pad2soc_o.gpio.gpio_v_15_i = 1'b0; + end + endcase + end + end + + + // Port Signal gpio_v_16_i + logic [0:0] port_mux_sel_gpio_gpio_v_16_i_req; + logic [PORT_MUX_GROUP_MUXED_V_16_SEL_WIDTH-1:0] port_mux_sel_gpio_gpio_v_16_i_arbitrated; + logic port_mux_sel_gpio_gpio_v_16_i_no_connection; + + assign port_mux_sel_gpio_gpio_v_16_i_req[PORT_MUX_GROUP_MUXED_V_16_SEL_MUXED_V_16] = s_reg2hw.muxed_v_16_mux_sel.q == PAD_MUX_GROUP_MUXED_V_16_SEL_GPIO_IO_V_16 ? 1'b1 : 1'b0; + + lzc #( + .WIDTH(1), + .MODE(1'b0) + ) i_port_muxsel_gpio_gpio_v_16_i_arbiter ( + .in_i(port_mux_sel_gpio_gpio_v_16_i_req), + .cnt_o(port_mux_sel_gpio_gpio_v_16_i_arbitrated), + .empty_o(port_mux_sel_gpio_gpio_v_16_i_no_connection) + ); + + always_comb begin + if (port_mux_sel_gpio_gpio_v_16_i_no_connection) begin + port_signals_pad2soc_o.gpio.gpio_v_16_i = 1'b0; + end else begin + unique case (port_mux_sel_gpio_gpio_v_16_i_arbitrated) + PORT_MUX_GROUP_MUXED_V_16_SEL_MUXED_V_16: begin + port_signals_pad2soc_o.gpio.gpio_v_16_i = pads_to_mux_i.muxed_v_16.pad2chip; + end + default: begin + port_signals_pad2soc_o.gpio.gpio_v_16_i = 1'b0; + end + endcase + end + end + + + // Port Signal gpio_v_17_i + logic [0:0] port_mux_sel_gpio_gpio_v_17_i_req; + logic [PORT_MUX_GROUP_MUXED_V_17_SEL_WIDTH-1:0] port_mux_sel_gpio_gpio_v_17_i_arbitrated; + logic port_mux_sel_gpio_gpio_v_17_i_no_connection; + + assign port_mux_sel_gpio_gpio_v_17_i_req[PORT_MUX_GROUP_MUXED_V_17_SEL_MUXED_V_17] = s_reg2hw.muxed_v_17_mux_sel.q == PAD_MUX_GROUP_MUXED_V_17_SEL_GPIO_IO_V_17 ? 1'b1 : 1'b0; + + lzc #( + .WIDTH(1), + .MODE(1'b0) + ) i_port_muxsel_gpio_gpio_v_17_i_arbiter ( + .in_i(port_mux_sel_gpio_gpio_v_17_i_req), + .cnt_o(port_mux_sel_gpio_gpio_v_17_i_arbitrated), + .empty_o(port_mux_sel_gpio_gpio_v_17_i_no_connection) + ); + + always_comb begin + if (port_mux_sel_gpio_gpio_v_17_i_no_connection) begin + port_signals_pad2soc_o.gpio.gpio_v_17_i = 1'b0; + end else begin + unique case (port_mux_sel_gpio_gpio_v_17_i_arbitrated) + PORT_MUX_GROUP_MUXED_V_17_SEL_MUXED_V_17: begin + port_signals_pad2soc_o.gpio.gpio_v_17_i = pads_to_mux_i.muxed_v_17.pad2chip; + end + default: begin + port_signals_pad2soc_o.gpio.gpio_v_17_i = 1'b0; + end + endcase + end + end + + + // Port Signal gpio_h_0_i + logic [0:0] port_mux_sel_gpio_gpio_h_0_i_req; + logic [PORT_MUX_GROUP_MUXED_H_00_SEL_WIDTH-1:0] port_mux_sel_gpio_gpio_h_0_i_arbitrated; + logic port_mux_sel_gpio_gpio_h_0_i_no_connection; + + assign port_mux_sel_gpio_gpio_h_0_i_req[PORT_MUX_GROUP_MUXED_H_00_SEL_MUXED_H_00] = s_reg2hw.muxed_h_00_mux_sel.q == PAD_MUX_GROUP_MUXED_H_00_SEL_GPIO_IO_H_0 ? 1'b1 : 1'b0; + + lzc #( + .WIDTH(1), + .MODE(1'b0) + ) i_port_muxsel_gpio_gpio_h_0_i_arbiter ( + .in_i(port_mux_sel_gpio_gpio_h_0_i_req), + .cnt_o(port_mux_sel_gpio_gpio_h_0_i_arbitrated), + .empty_o(port_mux_sel_gpio_gpio_h_0_i_no_connection) + ); + + always_comb begin + if (port_mux_sel_gpio_gpio_h_0_i_no_connection) begin + port_signals_pad2soc_o.gpio.gpio_h_0_i = 1'b0; + end else begin + unique case (port_mux_sel_gpio_gpio_h_0_i_arbitrated) + PORT_MUX_GROUP_MUXED_H_00_SEL_MUXED_H_00: begin + port_signals_pad2soc_o.gpio.gpio_h_0_i = pads_to_mux_i.muxed_h_00.pad2chip; + end + default: begin + port_signals_pad2soc_o.gpio.gpio_h_0_i = 1'b0; + end + endcase + end + end + + + // Port Signal gpio_h_1_i + logic [0:0] port_mux_sel_gpio_gpio_h_1_i_req; + logic [PORT_MUX_GROUP_MUXED_H_01_SEL_WIDTH-1:0] port_mux_sel_gpio_gpio_h_1_i_arbitrated; + logic port_mux_sel_gpio_gpio_h_1_i_no_connection; + + assign port_mux_sel_gpio_gpio_h_1_i_req[PORT_MUX_GROUP_MUXED_H_01_SEL_MUXED_H_01] = s_reg2hw.muxed_h_01_mux_sel.q == PAD_MUX_GROUP_MUXED_H_01_SEL_GPIO_IO_H_1 ? 1'b1 : 1'b0; + + lzc #( + .WIDTH(1), + .MODE(1'b0) + ) i_port_muxsel_gpio_gpio_h_1_i_arbiter ( + .in_i(port_mux_sel_gpio_gpio_h_1_i_req), + .cnt_o(port_mux_sel_gpio_gpio_h_1_i_arbitrated), + .empty_o(port_mux_sel_gpio_gpio_h_1_i_no_connection) + ); + + always_comb begin + if (port_mux_sel_gpio_gpio_h_1_i_no_connection) begin + port_signals_pad2soc_o.gpio.gpio_h_1_i = 1'b0; + end else begin + unique case (port_mux_sel_gpio_gpio_h_1_i_arbitrated) + PORT_MUX_GROUP_MUXED_H_01_SEL_MUXED_H_01: begin + port_signals_pad2soc_o.gpio.gpio_h_1_i = pads_to_mux_i.muxed_h_01.pad2chip; + end + default: begin + port_signals_pad2soc_o.gpio.gpio_h_1_i = 1'b0; + end + endcase + end + end + + + // Port Signal gpio_h_2_i + logic [0:0] port_mux_sel_gpio_gpio_h_2_i_req; + logic [PORT_MUX_GROUP_MUXED_H_02_SEL_WIDTH-1:0] port_mux_sel_gpio_gpio_h_2_i_arbitrated; + logic port_mux_sel_gpio_gpio_h_2_i_no_connection; + + assign port_mux_sel_gpio_gpio_h_2_i_req[PORT_MUX_GROUP_MUXED_H_02_SEL_MUXED_H_02] = s_reg2hw.muxed_h_02_mux_sel.q == PAD_MUX_GROUP_MUXED_H_02_SEL_GPIO_IO_H_2 ? 1'b1 : 1'b0; + + lzc #( + .WIDTH(1), + .MODE(1'b0) + ) i_port_muxsel_gpio_gpio_h_2_i_arbiter ( + .in_i(port_mux_sel_gpio_gpio_h_2_i_req), + .cnt_o(port_mux_sel_gpio_gpio_h_2_i_arbitrated), + .empty_o(port_mux_sel_gpio_gpio_h_2_i_no_connection) + ); + + always_comb begin + if (port_mux_sel_gpio_gpio_h_2_i_no_connection) begin + port_signals_pad2soc_o.gpio.gpio_h_2_i = 1'b0; + end else begin + unique case (port_mux_sel_gpio_gpio_h_2_i_arbitrated) + PORT_MUX_GROUP_MUXED_H_02_SEL_MUXED_H_02: begin + port_signals_pad2soc_o.gpio.gpio_h_2_i = pads_to_mux_i.muxed_h_02.pad2chip; + end + default: begin + port_signals_pad2soc_o.gpio.gpio_h_2_i = 1'b0; + end + endcase + end + end + + + // Port Signal gpio_h_3_i + logic [0:0] port_mux_sel_gpio_gpio_h_3_i_req; + logic [PORT_MUX_GROUP_MUXED_H_03_SEL_WIDTH-1:0] port_mux_sel_gpio_gpio_h_3_i_arbitrated; + logic port_mux_sel_gpio_gpio_h_3_i_no_connection; + + assign port_mux_sel_gpio_gpio_h_3_i_req[PORT_MUX_GROUP_MUXED_H_03_SEL_MUXED_H_03] = s_reg2hw.muxed_h_03_mux_sel.q == PAD_MUX_GROUP_MUXED_H_03_SEL_GPIO_IO_H_3 ? 1'b1 : 1'b0; + + lzc #( + .WIDTH(1), + .MODE(1'b0) + ) i_port_muxsel_gpio_gpio_h_3_i_arbiter ( + .in_i(port_mux_sel_gpio_gpio_h_3_i_req), + .cnt_o(port_mux_sel_gpio_gpio_h_3_i_arbitrated), + .empty_o(port_mux_sel_gpio_gpio_h_3_i_no_connection) + ); + + always_comb begin + if (port_mux_sel_gpio_gpio_h_3_i_no_connection) begin + port_signals_pad2soc_o.gpio.gpio_h_3_i = 1'b0; + end else begin + unique case (port_mux_sel_gpio_gpio_h_3_i_arbitrated) + PORT_MUX_GROUP_MUXED_H_03_SEL_MUXED_H_03: begin + port_signals_pad2soc_o.gpio.gpio_h_3_i = pads_to_mux_i.muxed_h_03.pad2chip; + end + default: begin + port_signals_pad2soc_o.gpio.gpio_h_3_i = 1'b0; + end + endcase + end + end + +endmodule : astral_padframe_periph_muxer diff --git a/hw/padframe/astral_padframe/src/astral_padframe_periph_pads.sv b/hw/padframe/astral_padframe/src/astral_padframe_periph_pads.sv new file mode 100644 index 00000000..2469469f --- /dev/null +++ b/hw/padframe/astral_padframe/src/astral_padframe_periph_pads.sv @@ -0,0 +1,1280 @@ + +// File auto-generated by Padrick unknown +module astral_padframe_periph_pads + import pkg_astral_padframe::*; + import pkg_internal_astral_padframe_periph::*; +( + output pad_domain_periph_static_connection_signals_pad2soc_t static_connection_signals_pad2soc, + input pad_domain_periph_static_connection_signals_soc2pad_t static_connection_signals_soc2pad, + // Dynamic Pad control signals, these signals are controlled by the multiplexer in the correpsongin pad_controller module + input mux_to_pads_t mux_to_pads_i, + output pads_to_mux_t pads_to_mux_o, + // Landing Pads + inout wire logic pad_ref_clk_pad, + inout wire logic pad_fll_host_pad, + inout wire logic pad_fll_periph_pad, + inout wire logic pad_fll_alt_pad, + inout wire logic pad_fll_rt_pad, + inout wire logic pad_fll_bypass_pad, + inout wire logic pad_pwr_on_rst_n_pad, + inout wire logic pad_secure_boot_pad, + inout wire logic pad_jtag_tclk_pad, + inout wire logic pad_jtag_trst_n_pad, + inout wire logic pad_jtag_tms_pad, + inout wire logic pad_jtag_tdi_pad, + inout wire logic pad_jtag_tdo_pad, + inout wire logic pad_test_mode_pad, + inout wire logic pad_boot_mode_0_pad, + inout wire logic pad_boot_mode_1_pad, + inout wire logic pad_ot_boot_mode_pad, + inout wire logic pad_jtag_ot_tclk_pad, + inout wire logic pad_jtag_ot_trst_ni_pad, + inout wire logic pad_jtag_ot_tms_pad, + inout wire logic pad_jtag_ot_tdi_pad, + inout wire logic pad_jtag_ot_tdo_pad, + inout wire logic pad_hyper_cs_0_n_pad, + inout wire logic pad_hyper_cs_1_n_pad, + inout wire logic pad_hyper_ck_pad, + inout wire logic pad_hyper_ck_n_pad, + inout wire logic pad_hyper_rwds_pad, + inout wire logic pad_hyper_dq_0_pad, + inout wire logic pad_hyper_dq_1_pad, + inout wire logic pad_hyper_dq_2_pad, + inout wire logic pad_hyper_dq_3_pad, + inout wire logic pad_hyper_dq_4_pad, + inout wire logic pad_hyper_dq_5_pad, + inout wire logic pad_hyper_dq_6_pad, + inout wire logic pad_hyper_dq_7_pad, + inout wire logic pad_hyper_reset_n_pad, + inout wire logic pad_spw_data_in_pad, + inout wire logic pad_spw_strb_in_pad, + inout wire logic pad_spw_data_out_pad, + inout wire logic pad_spw_strb_out_pad, + inout wire logic pad_uart_tx_out_pad, + inout wire logic pad_uart_rx_in_pad, + inout wire logic pad_muxed_v_00_pad, + inout wire logic pad_muxed_v_01_pad, + inout wire logic pad_muxed_v_02_pad, + inout wire logic pad_muxed_v_03_pad, + inout wire logic pad_muxed_v_04_pad, + inout wire logic pad_muxed_v_05_pad, + inout wire logic pad_muxed_v_06_pad, + inout wire logic pad_muxed_v_07_pad, + inout wire logic pad_muxed_v_08_pad, + inout wire logic pad_muxed_v_09_pad, + inout wire logic pad_muxed_v_10_pad, + inout wire logic pad_muxed_v_11_pad, + inout wire logic pad_muxed_v_12_pad, + inout wire logic pad_muxed_v_13_pad, + inout wire logic pad_muxed_v_14_pad, + inout wire logic pad_muxed_v_15_pad, + inout wire logic pad_muxed_v_16_pad, + inout wire logic pad_muxed_v_17_pad, + inout wire logic pad_muxed_h_00_pad, + inout wire logic pad_muxed_h_01_pad, + inout wire logic pad_muxed_h_02_pad, + inout wire logic pad_muxed_h_03_pad + ); + + // Pad instantiations + wire io_pads_rto; + wire io_pads_sns; + + PDVDDTIE_18_18_NT_DR_V i_pad_tie_io ( + .SNS( io_pads_sns ), + .RTO( io_pads_rto ) + ); + PDVDD_18_18_NT_DR_H i_pad_dvdd_io_h_0 ( .SNS( io_pads_sns ), .RTO( io_pads_rto ) ); + PDVDD_18_18_NT_DR_H i_pad_dvdd_io_h_1 ( .SNS( io_pads_sns ), .RTO( io_pads_rto ) ); + PDVDD_18_18_NT_DR_V i_pad_dvdd_io_v_0 ( .SNS( io_pads_sns ), .RTO( io_pads_rto ) ); + PDVDD_18_18_NT_DR_V i_pad_dvdd_io_v_1 ( .SNS( io_pads_sns ), .RTO( io_pads_rto ) ); + PDVDD_18_18_NT_DR_V i_pad_dvdd_io_v_2 ( .SNS( io_pads_sns ), .RTO( io_pads_rto ) ); + PDVDD_18_18_NT_DR_V i_pad_dvdd_io_v_3 ( .SNS( io_pads_sns ), .RTO( io_pads_rto ) ); + PDVDD_18_18_NT_DR_V i_pad_dvdd_io_v_4 ( .SNS( io_pads_sns ), .RTO( io_pads_rto ) ); + PDVDD_18_18_NT_DR_V i_pad_dvdd_io_v_5 ( .SNS( io_pads_sns ), .RTO( io_pads_rto ) ); + PDVSS_18_18_NT_DR_H i_pad_dvss_io_h_0 ( .SNS( io_pads_sns ), .RTO( io_pads_rto ) ); + PDVSS_18_18_NT_DR_H i_pad_dvss_io_h_1 ( .SNS( io_pads_sns ), .RTO( io_pads_rto ) ); + PDVSS_18_18_NT_DR_V i_pad_dvss_io_v_0 ( .SNS( io_pads_sns ), .RTO( io_pads_rto ) ); + PDVSS_18_18_NT_DR_V i_pad_dvss_io_v_1 ( .SNS( io_pads_sns ), .RTO( io_pads_rto ) ); + PDVSS_18_18_NT_DR_V i_pad_dvss_io_v_2 ( .SNS( io_pads_sns ), .RTO( io_pads_rto ) ); + PDVSS_18_18_NT_DR_V i_pad_dvss_io_v_3 ( .SNS( io_pads_sns ), .RTO( io_pads_rto ) ); + PDVSS_18_18_NT_DR_V i_pad_dvss_io_v_4 ( .SNS( io_pads_sns ), .RTO( io_pads_rto ) ); + PDVSS_18_18_NT_DR_V i_pad_dvss_io_v_5 ( .SNS( io_pads_sns ), .RTO( io_pads_rto ) ); + PVDD_08_08_NT_DR_H i_pad_vdd_core_h_0 ( .SNS( io_pads_sns ), .RTO( io_pads_rto ) ); + PVDD_08_08_NT_DR_H i_pad_vdd_core_h_1 ( .SNS( io_pads_sns ), .RTO( io_pads_rto ) ); + PVDD_08_08_NT_DR_H i_pad_vdd_core_h_2 ( .SNS( io_pads_sns ), .RTO( io_pads_rto ) ); + PVDD_08_08_NT_DR_H i_pad_vdd_core_h_3 ( .SNS( io_pads_sns ), .RTO( io_pads_rto ) ); + PVDD_08_08_NT_DR_V i_pad_vdd_core_v_0 ( .SNS( io_pads_sns ), .RTO( io_pads_rto ) ); + PVDD_08_08_NT_DR_V i_pad_vdd_core_v_1 ( .SNS( io_pads_sns ), .RTO( io_pads_rto ) ); + PVDD_08_08_NT_DR_V i_pad_vdd_core_v_2 ( .SNS( io_pads_sns ), .RTO( io_pads_rto ) ); + PVDD_08_08_NT_DR_V i_pad_vdd_core_v_3 ( .SNS( io_pads_sns ), .RTO( io_pads_rto ) ); + PVDD_08_08_NT_DR_V i_pad_vdd_core_v_4 ( .SNS( io_pads_sns ), .RTO( io_pads_rto ) ); + PVDD_08_08_NT_DR_V i_pad_vdd_core_v_5 ( .SNS( io_pads_sns ), .RTO( io_pads_rto ) ); + PVSS_08_08_NT_DR_H i_pad_vss_core_h_0 ( .SNS( io_pads_sns ), .RTO( io_pads_rto ) ); + PVSS_08_08_NT_DR_H i_pad_vss_core_h_1 ( .SNS( io_pads_sns ), .RTO( io_pads_rto ) ); + PVSS_08_08_NT_DR_H i_pad_vss_core_h_2 ( .SNS( io_pads_sns ), .RTO( io_pads_rto ) ); + PVSS_08_08_NT_DR_H i_pad_vss_core_h_3 ( .SNS( io_pads_sns ), .RTO( io_pads_rto ) ); + PVSS_08_08_NT_DR_V i_pad_vss_core_v_0 ( .SNS( io_pads_sns ), .RTO( io_pads_rto ) ); + PVSS_08_08_NT_DR_V i_pad_vss_core_v_1 ( .SNS( io_pads_sns ), .RTO( io_pads_rto ) ); + PVSS_08_08_NT_DR_V i_pad_vss_core_v_2 ( .SNS( io_pads_sns ), .RTO( io_pads_rto ) ); + PVSS_08_08_NT_DR_V i_pad_vss_core_v_3 ( .SNS( io_pads_sns ), .RTO( io_pads_rto ) ); + PVSS_08_08_NT_DR_V i_pad_vss_core_v_4 ( .SNS( io_pads_sns ), .RTO( io_pads_rto ) ); + PVSS_08_08_NT_DR_V i_pad_vss_core_v_5 ( .SNS( io_pads_sns ), .RTO( io_pads_rto ) ); + PCORNER_18_18_NT_DR i_pad_corner_0 ( .SNS( io_pads_sns ), .RTO( io_pads_rto ) ); + PCORNER_18_18_NT_DR i_pad_corner_1 ( .SNS( io_pads_sns ), .RTO( io_pads_rto ) ); + PCORNER_18_18_NT_DR i_pad_corner_2 ( .SNS( io_pads_sns ), .RTO( io_pads_rto ) ); + PCORNER_18_18_NT_DR i_pad_corner_3 ( .SNS( io_pads_sns ), .RTO( io_pads_rto ) ); + (* dont_touch *) + PBIDIR_18_18_NT_DR_H i_ref_clk ( + .PO ( ), + .Y ( static_connection_signals_pad2soc.ref_clk_i ), + .PAD ( pad_ref_clk_pad ), + .A ( 1'b0 ), + .DS0 ( 1'b0 ), + .DS1 ( 1'b0 ), + .IE ( 1'b1 ), + .IS ( 1'b0 ), + .OE ( 1'b0 ), + .PE ( 1'b0 ), + .POE ( 1'b0 ), + .PS ( 1'b0 ), + .RTO ( io_pads_rto ), + .SNS ( io_pads_sns ), + .SR ( 1'b0 ) + ); + (* dont_touch *) + PBIDIR_18_18_NT_DR_H i_fll_host ( + .PO ( ), + .Y ( ), + .PAD ( pad_fll_host_pad ), + .A ( static_connection_signals_soc2pad.fll_host_clk_o ), + .DS0 ( 1'b0 ), + .DS1 ( 1'b0 ), + .IE ( 1'b0 ), + .IS ( 1'b0 ), + .OE ( 1'b1 ), + .PE ( 1'b0 ), + .POE ( 1'b0 ), + .PS ( 1'b0 ), + .RTO ( io_pads_rto ), + .SNS ( io_pads_sns ), + .SR ( 1'b0 ) + ); + (* dont_touch *) + PBIDIR_18_18_NT_DR_H i_fll_periph ( + .PO ( ), + .Y ( ), + .PAD ( pad_fll_periph_pad ), + .A ( static_connection_signals_soc2pad.fll_periph_clk_o ), + .DS0 ( 1'b0 ), + .DS1 ( 1'b0 ), + .IE ( 1'b0 ), + .IS ( 1'b0 ), + .OE ( 1'b1 ), + .PE ( 1'b0 ), + .POE ( 1'b0 ), + .PS ( 1'b0 ), + .RTO ( io_pads_rto ), + .SNS ( io_pads_sns ), + .SR ( 1'b0 ) + ); + (* dont_touch *) + PBIDIR_18_18_NT_DR_H i_fll_alt ( + .PO ( ), + .Y ( ), + .PAD ( pad_fll_alt_pad ), + .A ( static_connection_signals_soc2pad.fll_alt_clk_o ), + .DS0 ( 1'b0 ), + .DS1 ( 1'b0 ), + .IE ( 1'b0 ), + .IS ( 1'b0 ), + .OE ( 1'b1 ), + .PE ( 1'b0 ), + .POE ( 1'b0 ), + .PS ( 1'b0 ), + .RTO ( io_pads_rto ), + .SNS ( io_pads_sns ), + .SR ( 1'b0 ) + ); + (* dont_touch *) + PBIDIR_18_18_NT_DR_H i_fll_rt ( + .PO ( ), + .Y ( ), + .PAD ( pad_fll_rt_pad ), + .A ( static_connection_signals_soc2pad.fll_rt_clk_o ), + .DS0 ( 1'b0 ), + .DS1 ( 1'b0 ), + .IE ( 1'b0 ), + .IS ( 1'b0 ), + .OE ( 1'b1 ), + .PE ( 1'b0 ), + .POE ( 1'b0 ), + .PS ( 1'b0 ), + .RTO ( io_pads_rto ), + .SNS ( io_pads_sns ), + .SR ( 1'b0 ) + ); + (* dont_touch *) + PBIDIR_18_18_NT_DR_H i_fll_bypass ( + .PO ( ), + .Y ( static_connection_signals_pad2soc.fll_bypass_i ), + .PAD ( pad_fll_bypass_pad ), + .A ( 1'b0 ), + .DS0 ( 1'b0 ), + .DS1 ( 1'b0 ), + .IE ( 1'b1 ), + .IS ( 1'b0 ), + .OE ( 1'b0 ), + .PE ( 1'b0 ), + .POE ( 1'b0 ), + .PS ( 1'b0 ), + .RTO ( io_pads_rto ), + .SNS ( io_pads_sns ), + .SR ( 1'b0 ) + ); + (* dont_touch *) + PBIDIR_18_18_NT_DR_H i_pwr_on_rst_n ( + .PO ( ), + .Y ( static_connection_signals_pad2soc.pwr_on_rst_ni ), + .PAD ( pad_pwr_on_rst_n_pad ), + .A ( 1'b0 ), + .DS0 ( 1'b0 ), + .DS1 ( 1'b0 ), + .IE ( 1'b1 ), + .IS ( 1'b0 ), + .OE ( 1'b0 ), + .PE ( 1'b0 ), + .POE ( 1'b0 ), + .PS ( 1'b0 ), + .RTO ( io_pads_rto ), + .SNS ( io_pads_sns ), + .SR ( 1'b0 ) + ); + (* dont_touch *) + PBIDIR_18_18_NT_DR_H i_secure_boot ( + .PO ( ), + .Y ( static_connection_signals_pad2soc.secure_boot_i ), + .PAD ( pad_secure_boot_pad ), + .A ( 1'b0 ), + .DS0 ( 1'b0 ), + .DS1 ( 1'b0 ), + .IE ( 1'b1 ), + .IS ( 1'b0 ), + .OE ( 1'b0 ), + .PE ( 1'b0 ), + .POE ( 1'b0 ), + .PS ( 1'b0 ), + .RTO ( io_pads_rto ), + .SNS ( io_pads_sns ), + .SR ( 1'b0 ) + ); + (* dont_touch *) + PBIDIR_18_18_NT_DR_H i_jtag_tclk ( + .PO ( ), + .Y ( static_connection_signals_pad2soc.jtag_tclk_i ), + .PAD ( pad_jtag_tclk_pad ), + .A ( 1'b0 ), + .DS0 ( 1'b0 ), + .DS1 ( 1'b0 ), + .IE ( 1'b1 ), + .IS ( 1'b0 ), + .OE ( 1'b0 ), + .PE ( 1'b0 ), + .POE ( 1'b0 ), + .PS ( 1'b0 ), + .RTO ( io_pads_rto ), + .SNS ( io_pads_sns ), + .SR ( 1'b0 ) + ); + (* dont_touch *) + PBIDIR_18_18_NT_DR_H i_jtag_trst_n ( + .PO ( ), + .Y ( static_connection_signals_pad2soc.jtag_trst_ni ), + .PAD ( pad_jtag_trst_n_pad ), + .A ( 1'b0 ), + .DS0 ( 1'b0 ), + .DS1 ( 1'b0 ), + .IE ( 1'b1 ), + .IS ( 1'b0 ), + .OE ( 1'b0 ), + .PE ( 1'b0 ), + .POE ( 1'b0 ), + .PS ( 1'b0 ), + .RTO ( io_pads_rto ), + .SNS ( io_pads_sns ), + .SR ( 1'b0 ) + ); + (* dont_touch *) + PBIDIR_18_18_NT_DR_H i_jtag_tms ( + .PO ( ), + .Y ( static_connection_signals_pad2soc.jtag_tms_i ), + .PAD ( pad_jtag_tms_pad ), + .A ( 1'b0 ), + .DS0 ( 1'b0 ), + .DS1 ( 1'b0 ), + .IE ( 1'b1 ), + .IS ( 1'b0 ), + .OE ( 1'b0 ), + .PE ( 1'b0 ), + .POE ( 1'b0 ), + .PS ( 1'b0 ), + .RTO ( io_pads_rto ), + .SNS ( io_pads_sns ), + .SR ( 1'b0 ) + ); + (* dont_touch *) + PBIDIR_18_18_NT_DR_H i_jtag_tdi ( + .PO ( ), + .Y ( static_connection_signals_pad2soc.jtag_tdi_i ), + .PAD ( pad_jtag_tdi_pad ), + .A ( 1'b0 ), + .DS0 ( 1'b0 ), + .DS1 ( 1'b0 ), + .IE ( 1'b1 ), + .IS ( 1'b0 ), + .OE ( 1'b0 ), + .PE ( 1'b0 ), + .POE ( 1'b0 ), + .PS ( 1'b0 ), + .RTO ( io_pads_rto ), + .SNS ( io_pads_sns ), + .SR ( 1'b0 ) + ); + (* dont_touch *) + PBIDIR_18_18_NT_DR_H i_jtag_tdo ( + .PO ( ), + .Y ( ), + .PAD ( pad_jtag_tdo_pad ), + .A ( static_connection_signals_soc2pad.jtag_tdo_o ), + .DS0 ( 1'b0 ), + .DS1 ( 1'b0 ), + .IE ( 1'b0 ), + .IS ( 1'b0 ), + .OE ( 1'b1 ), + .PE ( 1'b0 ), + .POE ( 1'b0 ), + .PS ( 1'b0 ), + .RTO ( io_pads_rto ), + .SNS ( io_pads_sns ), + .SR ( 1'b0 ) + ); + (* dont_touch *) + PBIDIR_18_18_NT_DR_H i_test_mode ( + .PO ( ), + .Y ( static_connection_signals_pad2soc.test_mode_i ), + .PAD ( pad_test_mode_pad ), + .A ( 1'b0 ), + .DS0 ( 1'b0 ), + .DS1 ( 1'b0 ), + .IE ( 1'b1 ), + .IS ( 1'b0 ), + .OE ( 1'b0 ), + .PE ( 1'b0 ), + .POE ( 1'b0 ), + .PS ( 1'b0 ), + .RTO ( io_pads_rto ), + .SNS ( io_pads_sns ), + .SR ( 1'b0 ) + ); + (* dont_touch *) + PBIDIR_18_18_NT_DR_H i_boot_mode_0 ( + .PO ( ), + .Y ( static_connection_signals_pad2soc.boot_mode_0_i ), + .PAD ( pad_boot_mode_0_pad ), + .A ( 1'b0 ), + .DS0 ( 1'b0 ), + .DS1 ( 1'b0 ), + .IE ( 1'b1 ), + .IS ( 1'b0 ), + .OE ( 1'b0 ), + .PE ( 1'b0 ), + .POE ( 1'b0 ), + .PS ( 1'b0 ), + .RTO ( io_pads_rto ), + .SNS ( io_pads_sns ), + .SR ( 1'b0 ) + ); + (* dont_touch *) + PBIDIR_18_18_NT_DR_H i_boot_mode_1 ( + .PO ( ), + .Y ( static_connection_signals_pad2soc.boot_mode_1_i ), + .PAD ( pad_boot_mode_1_pad ), + .A ( 1'b0 ), + .DS0 ( 1'b0 ), + .DS1 ( 1'b0 ), + .IE ( 1'b1 ), + .IS ( 1'b0 ), + .OE ( 1'b0 ), + .PE ( 1'b0 ), + .POE ( 1'b0 ), + .PS ( 1'b0 ), + .RTO ( io_pads_rto ), + .SNS ( io_pads_sns ), + .SR ( 1'b0 ) + ); + (* dont_touch *) + PBIDIR_18_18_NT_DR_H i_ot_boot_mode ( + .PO ( ), + .Y ( static_connection_signals_pad2soc.ot_boot_mode_i ), + .PAD ( pad_ot_boot_mode_pad ), + .A ( 1'b0 ), + .DS0 ( 1'b0 ), + .DS1 ( 1'b0 ), + .IE ( 1'b1 ), + .IS ( 1'b0 ), + .OE ( 1'b0 ), + .PE ( 1'b0 ), + .POE ( 1'b0 ), + .PS ( 1'b0 ), + .RTO ( io_pads_rto ), + .SNS ( io_pads_sns ), + .SR ( 1'b0 ) + ); + (* dont_touch *) + PBIDIR_18_18_NT_DR_H i_jtag_ot_tclk ( + .PO ( ), + .Y ( static_connection_signals_pad2soc.jtag_ot_tclk_i ), + .PAD ( pad_jtag_ot_tclk_pad ), + .A ( 1'b0 ), + .DS0 ( 1'b0 ), + .DS1 ( 1'b0 ), + .IE ( 1'b1 ), + .IS ( 1'b0 ), + .OE ( 1'b0 ), + .PE ( 1'b0 ), + .POE ( 1'b0 ), + .PS ( 1'b0 ), + .RTO ( io_pads_rto ), + .SNS ( io_pads_sns ), + .SR ( 1'b0 ) + ); + (* dont_touch *) + PBIDIR_18_18_NT_DR_H i_jtag_ot_trst_ni ( + .PO ( ), + .Y ( static_connection_signals_pad2soc.jtag_ot_trst_ni ), + .PAD ( pad_jtag_ot_trst_ni_pad ), + .A ( 1'b0 ), + .DS0 ( 1'b0 ), + .DS1 ( 1'b0 ), + .IE ( 1'b1 ), + .IS ( 1'b0 ), + .OE ( 1'b0 ), + .PE ( 1'b0 ), + .POE ( 1'b0 ), + .PS ( 1'b0 ), + .RTO ( io_pads_rto ), + .SNS ( io_pads_sns ), + .SR ( 1'b0 ) + ); + (* dont_touch *) + PBIDIR_18_18_NT_DR_H i_jtag_ot_tms ( + .PO ( ), + .Y ( static_connection_signals_pad2soc.jtag_ot_tms_i ), + .PAD ( pad_jtag_ot_tms_pad ), + .A ( 1'b0 ), + .DS0 ( 1'b0 ), + .DS1 ( 1'b0 ), + .IE ( 1'b1 ), + .IS ( 1'b0 ), + .OE ( 1'b0 ), + .PE ( 1'b0 ), + .POE ( 1'b0 ), + .PS ( 1'b0 ), + .RTO ( io_pads_rto ), + .SNS ( io_pads_sns ), + .SR ( 1'b0 ) + ); + (* dont_touch *) + PBIDIR_18_18_NT_DR_H i_jtag_ot_tdi ( + .PO ( ), + .Y ( static_connection_signals_pad2soc.jtag_ot_tdi_i ), + .PAD ( pad_jtag_ot_tdi_pad ), + .A ( 1'b0 ), + .DS0 ( 1'b0 ), + .DS1 ( 1'b0 ), + .IE ( 1'b1 ), + .IS ( 1'b0 ), + .OE ( 1'b0 ), + .PE ( 1'b0 ), + .POE ( 1'b0 ), + .PS ( 1'b0 ), + .RTO ( io_pads_rto ), + .SNS ( io_pads_sns ), + .SR ( 1'b0 ) + ); + (* dont_touch *) + PBIDIR_18_18_NT_DR_H i_jtag_ot_tdo ( + .PO ( ), + .Y ( ), + .PAD ( pad_jtag_ot_tdo_pad ), + .A ( static_connection_signals_soc2pad.jtag_ot_tdo_o ), + .DS0 ( 1'b0 ), + .DS1 ( 1'b0 ), + .IE ( 1'b0 ), + .IS ( 1'b0 ), + .OE ( 1'b1 ), + .PE ( 1'b0 ), + .POE ( 1'b0 ), + .PS ( 1'b0 ), + .RTO ( io_pads_rto ), + .SNS ( io_pads_sns ), + .SR ( 1'b0 ) + ); + (* dont_touch *) + PBIDIR_18_18_NT_DR_V i_hyper_cs_0_n ( + .PO ( ), + .Y ( ), + .PAD ( pad_hyper_cs_0_n_pad ), + .A ( static_connection_signals_soc2pad.hyper_cs_0_no ), + .DS0 ( 1'b0 ), + .DS1 ( 1'b0 ), + .IE ( 1'b0 ), + .IS ( 1'b0 ), + .OE ( 1'b1 ), + .PE ( 1'b0 ), + .POE ( 1'b0 ), + .PS ( 1'b0 ), + .RTO ( io_pads_rto ), + .SNS ( io_pads_sns ), + .SR ( 1'b0 ) + ); + (* dont_touch *) + PBIDIR_18_18_NT_DR_V i_hyper_cs_1_n ( + .PO ( ), + .Y ( ), + .PAD ( pad_hyper_cs_1_n_pad ), + .A ( static_connection_signals_soc2pad.hyper_cs_1_no ), + .DS0 ( 1'b0 ), + .DS1 ( 1'b0 ), + .IE ( 1'b0 ), + .IS ( 1'b0 ), + .OE ( 1'b1 ), + .PE ( 1'b0 ), + .POE ( 1'b0 ), + .PS ( 1'b0 ), + .RTO ( io_pads_rto ), + .SNS ( io_pads_sns ), + .SR ( 1'b0 ) + ); + (* dont_touch *) + PBIDIR_18_18_NT_DR_V i_hyper_ck ( + .PO ( ), + .Y ( ), + .PAD ( pad_hyper_ck_pad ), + .A ( static_connection_signals_soc2pad.hyper_ck_o ), + .DS0 ( 1'b0 ), + .DS1 ( 1'b0 ), + .IE ( 1'b0 ), + .IS ( 1'b0 ), + .OE ( 1'b1 ), + .PE ( 1'b0 ), + .POE ( 1'b0 ), + .PS ( 1'b0 ), + .RTO ( io_pads_rto ), + .SNS ( io_pads_sns ), + .SR ( 1'b0 ) + ); + (* dont_touch *) + PBIDIR_18_18_NT_DR_V i_hyper_ck_n ( + .PO ( ), + .Y ( ), + .PAD ( pad_hyper_ck_n_pad ), + .A ( static_connection_signals_soc2pad.hyper_ck_no ), + .DS0 ( 1'b0 ), + .DS1 ( 1'b0 ), + .IE ( 1'b0 ), + .IS ( 1'b0 ), + .OE ( 1'b1 ), + .PE ( 1'b0 ), + .POE ( 1'b0 ), + .PS ( 1'b0 ), + .RTO ( io_pads_rto ), + .SNS ( io_pads_sns ), + .SR ( 1'b0 ) + ); + (* dont_touch *) + PBIDIR_18_18_NT_DR_V i_hyper_rwds ( + .PO ( ), + .Y ( static_connection_signals_pad2soc.hyper_rwds_i ), + .PAD ( pad_hyper_rwds_pad ), + .A ( static_connection_signals_soc2pad.hyper_rwds_o ), + .DS0 ( 1'b0 ), + .DS1 ( 1'b0 ), + .IE ( ~static_connection_signals_soc2pad.hyper_rwds_oen_i ), + .IS ( 1'b0 ), + .OE ( static_connection_signals_soc2pad.hyper_rwds_oen_i ), + .PE ( 1'b0 ), + .POE ( 1'b0 ), + .PS ( 1'b0 ), + .RTO ( io_pads_rto ), + .SNS ( io_pads_sns ), + .SR ( 1'b0 ) + ); + (* dont_touch *) + PBIDIR_18_18_NT_DR_V i_hyper_dq_0 ( + .PO ( ), + .Y ( static_connection_signals_pad2soc.hyper_dq_0_i ), + .PAD ( pad_hyper_dq_0_pad ), + .A ( static_connection_signals_soc2pad.hyper_dq_0_o ), + .DS0 ( 1'b0 ), + .DS1 ( 1'b0 ), + .IE ( ~static_connection_signals_soc2pad.hyper_dq_oen_i ), + .IS ( 1'b0 ), + .OE ( static_connection_signals_soc2pad.hyper_dq_oen_i ), + .PE ( 1'b0 ), + .POE ( 1'b0 ), + .PS ( 1'b0 ), + .RTO ( io_pads_rto ), + .SNS ( io_pads_sns ), + .SR ( 1'b0 ) + ); + (* dont_touch *) + PBIDIR_18_18_NT_DR_V i_hyper_dq_1 ( + .PO ( ), + .Y ( static_connection_signals_pad2soc.hyper_dq_1_i ), + .PAD ( pad_hyper_dq_1_pad ), + .A ( static_connection_signals_soc2pad.hyper_dq_1_o ), + .DS0 ( 1'b0 ), + .DS1 ( 1'b0 ), + .IE ( ~static_connection_signals_soc2pad.hyper_dq_oen_i ), + .IS ( 1'b0 ), + .OE ( static_connection_signals_soc2pad.hyper_dq_oen_i ), + .PE ( 1'b0 ), + .POE ( 1'b0 ), + .PS ( 1'b0 ), + .RTO ( io_pads_rto ), + .SNS ( io_pads_sns ), + .SR ( 1'b0 ) + ); + (* dont_touch *) + PBIDIR_18_18_NT_DR_V i_hyper_dq_2 ( + .PO ( ), + .Y ( static_connection_signals_pad2soc.hyper_dq_2_i ), + .PAD ( pad_hyper_dq_2_pad ), + .A ( static_connection_signals_soc2pad.hyper_dq_2_o ), + .DS0 ( 1'b0 ), + .DS1 ( 1'b0 ), + .IE ( ~static_connection_signals_soc2pad.hyper_dq_oen_i ), + .IS ( 1'b0 ), + .OE ( static_connection_signals_soc2pad.hyper_dq_oen_i ), + .PE ( 1'b0 ), + .POE ( 1'b0 ), + .PS ( 1'b0 ), + .RTO ( io_pads_rto ), + .SNS ( io_pads_sns ), + .SR ( 1'b0 ) + ); + (* dont_touch *) + PBIDIR_18_18_NT_DR_V i_hyper_dq_3 ( + .PO ( ), + .Y ( static_connection_signals_pad2soc.hyper_dq_3_i ), + .PAD ( pad_hyper_dq_3_pad ), + .A ( static_connection_signals_soc2pad.hyper_dq_3_o ), + .DS0 ( 1'b0 ), + .DS1 ( 1'b0 ), + .IE ( ~static_connection_signals_soc2pad.hyper_dq_oen_i ), + .IS ( 1'b0 ), + .OE ( static_connection_signals_soc2pad.hyper_dq_oen_i ), + .PE ( 1'b0 ), + .POE ( 1'b0 ), + .PS ( 1'b0 ), + .RTO ( io_pads_rto ), + .SNS ( io_pads_sns ), + .SR ( 1'b0 ) + ); + (* dont_touch *) + PBIDIR_18_18_NT_DR_V i_hyper_dq_4 ( + .PO ( ), + .Y ( static_connection_signals_pad2soc.hyper_dq_4_i ), + .PAD ( pad_hyper_dq_4_pad ), + .A ( static_connection_signals_soc2pad.hyper_dq_4_o ), + .DS0 ( 1'b0 ), + .DS1 ( 1'b0 ), + .IE ( ~static_connection_signals_soc2pad.hyper_dq_oen_i ), + .IS ( 1'b0 ), + .OE ( static_connection_signals_soc2pad.hyper_dq_oen_i ), + .PE ( 1'b0 ), + .POE ( 1'b0 ), + .PS ( 1'b0 ), + .RTO ( io_pads_rto ), + .SNS ( io_pads_sns ), + .SR ( 1'b0 ) + ); + (* dont_touch *) + PBIDIR_18_18_NT_DR_V i_hyper_dq_5 ( + .PO ( ), + .Y ( static_connection_signals_pad2soc.hyper_dq_5_i ), + .PAD ( pad_hyper_dq_5_pad ), + .A ( static_connection_signals_soc2pad.hyper_dq_5_o ), + .DS0 ( 1'b0 ), + .DS1 ( 1'b0 ), + .IE ( ~static_connection_signals_soc2pad.hyper_dq_oen_i ), + .IS ( 1'b0 ), + .OE ( static_connection_signals_soc2pad.hyper_dq_oen_i ), + .PE ( 1'b0 ), + .POE ( 1'b0 ), + .PS ( 1'b0 ), + .RTO ( io_pads_rto ), + .SNS ( io_pads_sns ), + .SR ( 1'b0 ) + ); + (* dont_touch *) + PBIDIR_18_18_NT_DR_V i_hyper_dq_6 ( + .PO ( ), + .Y ( static_connection_signals_pad2soc.hyper_dq_6_i ), + .PAD ( pad_hyper_dq_6_pad ), + .A ( static_connection_signals_soc2pad.hyper_dq_6_o ), + .DS0 ( 1'b0 ), + .DS1 ( 1'b0 ), + .IE ( ~static_connection_signals_soc2pad.hyper_dq_oen_i ), + .IS ( 1'b0 ), + .OE ( static_connection_signals_soc2pad.hyper_dq_oen_i ), + .PE ( 1'b0 ), + .POE ( 1'b0 ), + .PS ( 1'b0 ), + .RTO ( io_pads_rto ), + .SNS ( io_pads_sns ), + .SR ( 1'b0 ) + ); + (* dont_touch *) + PBIDIR_18_18_NT_DR_V i_hyper_dq_7 ( + .PO ( ), + .Y ( static_connection_signals_pad2soc.hyper_dq_7_i ), + .PAD ( pad_hyper_dq_7_pad ), + .A ( static_connection_signals_soc2pad.hyper_dq_7_o ), + .DS0 ( 1'b0 ), + .DS1 ( 1'b0 ), + .IE ( ~static_connection_signals_soc2pad.hyper_dq_oen_i ), + .IS ( 1'b0 ), + .OE ( static_connection_signals_soc2pad.hyper_dq_oen_i ), + .PE ( 1'b0 ), + .POE ( 1'b0 ), + .PS ( 1'b0 ), + .RTO ( io_pads_rto ), + .SNS ( io_pads_sns ), + .SR ( 1'b0 ) + ); + (* dont_touch *) + PBIDIR_18_18_NT_DR_V i_hyper_reset_n ( + .PO ( ), + .Y ( ), + .PAD ( pad_hyper_reset_n_pad ), + .A ( static_connection_signals_soc2pad.hyper_reset_no ), + .DS0 ( 1'b0 ), + .DS1 ( 1'b0 ), + .IE ( 1'b0 ), + .IS ( 1'b0 ), + .OE ( 1'b1 ), + .PE ( 1'b0 ), + .POE ( 1'b0 ), + .PS ( 1'b0 ), + .RTO ( io_pads_rto ), + .SNS ( io_pads_sns ), + .SR ( 1'b0 ) + ); + (* dont_touch *) + PBIDIR_18_18_NT_DR_H i_spw_data_in ( + .PO ( ), + .Y ( static_connection_signals_pad2soc.spw_data_i ), + .PAD ( pad_spw_data_in_pad ), + .A ( 1'b0 ), + .DS0 ( 1'b0 ), + .DS1 ( 1'b0 ), + .IE ( 1'b1 ), + .IS ( 1'b0 ), + .OE ( 1'b0 ), + .PE ( 1'b0 ), + .POE ( 1'b0 ), + .PS ( 1'b0 ), + .RTO ( io_pads_rto ), + .SNS ( io_pads_sns ), + .SR ( 1'b0 ) + ); + (* dont_touch *) + PBIDIR_18_18_NT_DR_H i_spw_strb_in ( + .PO ( ), + .Y ( static_connection_signals_pad2soc.spw_strb_i ), + .PAD ( pad_spw_strb_in_pad ), + .A ( 1'b0 ), + .DS0 ( 1'b0 ), + .DS1 ( 1'b0 ), + .IE ( 1'b1 ), + .IS ( 1'b0 ), + .OE ( 1'b0 ), + .PE ( 1'b0 ), + .POE ( 1'b0 ), + .PS ( 1'b0 ), + .RTO ( io_pads_rto ), + .SNS ( io_pads_sns ), + .SR ( 1'b0 ) + ); + (* dont_touch *) + PBIDIR_18_18_NT_DR_H i_spw_data_out ( + .PO ( ), + .Y ( ), + .PAD ( pad_spw_data_out_pad ), + .A ( static_connection_signals_soc2pad.spw_data_o ), + .DS0 ( 1'b0 ), + .DS1 ( 1'b0 ), + .IE ( 1'b0 ), + .IS ( 1'b0 ), + .OE ( 1'b1 ), + .PE ( 1'b0 ), + .POE ( 1'b0 ), + .PS ( 1'b0 ), + .RTO ( io_pads_rto ), + .SNS ( io_pads_sns ), + .SR ( 1'b0 ) + ); + (* dont_touch *) + PBIDIR_18_18_NT_DR_H i_spw_strb_out ( + .PO ( ), + .Y ( ), + .PAD ( pad_spw_strb_out_pad ), + .A ( static_connection_signals_soc2pad.spw_strb_o ), + .DS0 ( 1'b0 ), + .DS1 ( 1'b0 ), + .IE ( 1'b0 ), + .IS ( 1'b0 ), + .OE ( 1'b1 ), + .PE ( 1'b0 ), + .POE ( 1'b0 ), + .PS ( 1'b0 ), + .RTO ( io_pads_rto ), + .SNS ( io_pads_sns ), + .SR ( 1'b0 ) + ); + (* dont_touch *) + PBIDIR_18_18_NT_DR_H i_uart_tx_out ( + .PO ( ), + .Y ( ), + .PAD ( pad_uart_tx_out_pad ), + .A ( static_connection_signals_soc2pad.uart_tx_o ), + .DS0 ( 1'b0 ), + .DS1 ( 1'b0 ), + .IE ( 1'b0 ), + .IS ( 1'b0 ), + .OE ( 1'b1 ), + .PE ( 1'b0 ), + .POE ( 1'b0 ), + .PS ( 1'b0 ), + .RTO ( io_pads_rto ), + .SNS ( io_pads_sns ), + .SR ( 1'b0 ) + ); + (* dont_touch *) + PBIDIR_18_18_NT_DR_H i_uart_rx_in ( + .PO ( ), + .Y ( static_connection_signals_pad2soc.uart_rx_i ), + .PAD ( pad_uart_rx_in_pad ), + .A ( 1'b0 ), + .DS0 ( 1'b0 ), + .DS1 ( 1'b0 ), + .IE ( 1'b1 ), + .IS ( 1'b0 ), + .OE ( 1'b0 ), + .PE ( 1'b0 ), + .POE ( 1'b0 ), + .PS ( 1'b0 ), + .RTO ( io_pads_rto ), + .SNS ( io_pads_sns ), + .SR ( 1'b0 ) + ); + (* dont_touch *) + PBIDIR_18_18_NT_DR_V i_muxed_v_00 ( + .PO ( ), + .Y ( pads_to_mux_o.muxed_v_00.pad2chip ), + .PAD ( pad_muxed_v_00_pad ), + .A ( mux_to_pads_i.muxed_v_00.chip2pad ), + .DS0 ( 1'b0 ), + .DS1 ( 1'b0 ), + .IE ( mux_to_pads_i.muxed_v_00.input_en ), + .IS ( 1'b0 ), + .OE ( mux_to_pads_i.muxed_v_00.output_en ), + .PE ( mux_to_pads_i.muxed_v_00.pull_en ), + .POE ( 1'b0 ), + .PS ( mux_to_pads_i.muxed_v_00.pull_sel ), + .RTO ( io_pads_rto ), + .SNS ( io_pads_sns ), + .SR ( 1'b0 ) + ); + (* dont_touch *) + PBIDIR_18_18_NT_DR_V i_muxed_v_01 ( + .PO ( ), + .Y ( pads_to_mux_o.muxed_v_01.pad2chip ), + .PAD ( pad_muxed_v_01_pad ), + .A ( mux_to_pads_i.muxed_v_01.chip2pad ), + .DS0 ( 1'b0 ), + .DS1 ( 1'b0 ), + .IE ( mux_to_pads_i.muxed_v_01.input_en ), + .IS ( 1'b0 ), + .OE ( mux_to_pads_i.muxed_v_01.output_en ), + .PE ( mux_to_pads_i.muxed_v_01.pull_en ), + .POE ( 1'b0 ), + .PS ( mux_to_pads_i.muxed_v_01.pull_sel ), + .RTO ( io_pads_rto ), + .SNS ( io_pads_sns ), + .SR ( 1'b0 ) + ); + (* dont_touch *) + PBIDIR_18_18_NT_DR_V i_muxed_v_02 ( + .PO ( ), + .Y ( pads_to_mux_o.muxed_v_02.pad2chip ), + .PAD ( pad_muxed_v_02_pad ), + .A ( mux_to_pads_i.muxed_v_02.chip2pad ), + .DS0 ( 1'b0 ), + .DS1 ( 1'b0 ), + .IE ( mux_to_pads_i.muxed_v_02.input_en ), + .IS ( 1'b0 ), + .OE ( mux_to_pads_i.muxed_v_02.output_en ), + .PE ( mux_to_pads_i.muxed_v_02.pull_en ), + .POE ( 1'b0 ), + .PS ( mux_to_pads_i.muxed_v_02.pull_sel ), + .RTO ( io_pads_rto ), + .SNS ( io_pads_sns ), + .SR ( 1'b0 ) + ); + (* dont_touch *) + PBIDIR_18_18_NT_DR_V i_muxed_v_03 ( + .PO ( ), + .Y ( pads_to_mux_o.muxed_v_03.pad2chip ), + .PAD ( pad_muxed_v_03_pad ), + .A ( mux_to_pads_i.muxed_v_03.chip2pad ), + .DS0 ( 1'b0 ), + .DS1 ( 1'b0 ), + .IE ( mux_to_pads_i.muxed_v_03.input_en ), + .IS ( 1'b0 ), + .OE ( mux_to_pads_i.muxed_v_03.output_en ), + .PE ( mux_to_pads_i.muxed_v_03.pull_en ), + .POE ( 1'b0 ), + .PS ( mux_to_pads_i.muxed_v_03.pull_sel ), + .RTO ( io_pads_rto ), + .SNS ( io_pads_sns ), + .SR ( 1'b0 ) + ); + (* dont_touch *) + PBIDIR_18_18_NT_DR_V i_muxed_v_04 ( + .PO ( ), + .Y ( pads_to_mux_o.muxed_v_04.pad2chip ), + .PAD ( pad_muxed_v_04_pad ), + .A ( mux_to_pads_i.muxed_v_04.chip2pad ), + .DS0 ( 1'b0 ), + .DS1 ( 1'b0 ), + .IE ( mux_to_pads_i.muxed_v_04.input_en ), + .IS ( 1'b0 ), + .OE ( mux_to_pads_i.muxed_v_04.output_en ), + .PE ( mux_to_pads_i.muxed_v_04.pull_en ), + .POE ( 1'b0 ), + .PS ( mux_to_pads_i.muxed_v_04.pull_sel ), + .RTO ( io_pads_rto ), + .SNS ( io_pads_sns ), + .SR ( 1'b0 ) + ); + (* dont_touch *) + PBIDIR_18_18_NT_DR_V i_muxed_v_05 ( + .PO ( ), + .Y ( pads_to_mux_o.muxed_v_05.pad2chip ), + .PAD ( pad_muxed_v_05_pad ), + .A ( mux_to_pads_i.muxed_v_05.chip2pad ), + .DS0 ( 1'b0 ), + .DS1 ( 1'b0 ), + .IE ( mux_to_pads_i.muxed_v_05.input_en ), + .IS ( 1'b0 ), + .OE ( mux_to_pads_i.muxed_v_05.output_en ), + .PE ( mux_to_pads_i.muxed_v_05.pull_en ), + .POE ( 1'b0 ), + .PS ( mux_to_pads_i.muxed_v_05.pull_sel ), + .RTO ( io_pads_rto ), + .SNS ( io_pads_sns ), + .SR ( 1'b0 ) + ); + (* dont_touch *) + PBIDIR_18_18_NT_DR_V i_muxed_v_06 ( + .PO ( ), + .Y ( pads_to_mux_o.muxed_v_06.pad2chip ), + .PAD ( pad_muxed_v_06_pad ), + .A ( mux_to_pads_i.muxed_v_06.chip2pad ), + .DS0 ( 1'b0 ), + .DS1 ( 1'b0 ), + .IE ( mux_to_pads_i.muxed_v_06.input_en ), + .IS ( 1'b0 ), + .OE ( mux_to_pads_i.muxed_v_06.output_en ), + .PE ( mux_to_pads_i.muxed_v_06.pull_en ), + .POE ( 1'b0 ), + .PS ( mux_to_pads_i.muxed_v_06.pull_sel ), + .RTO ( io_pads_rto ), + .SNS ( io_pads_sns ), + .SR ( 1'b0 ) + ); + (* dont_touch *) + PBIDIR_18_18_NT_DR_V i_muxed_v_07 ( + .PO ( ), + .Y ( pads_to_mux_o.muxed_v_07.pad2chip ), + .PAD ( pad_muxed_v_07_pad ), + .A ( mux_to_pads_i.muxed_v_07.chip2pad ), + .DS0 ( 1'b0 ), + .DS1 ( 1'b0 ), + .IE ( mux_to_pads_i.muxed_v_07.input_en ), + .IS ( 1'b0 ), + .OE ( mux_to_pads_i.muxed_v_07.output_en ), + .PE ( mux_to_pads_i.muxed_v_07.pull_en ), + .POE ( 1'b0 ), + .PS ( mux_to_pads_i.muxed_v_07.pull_sel ), + .RTO ( io_pads_rto ), + .SNS ( io_pads_sns ), + .SR ( 1'b0 ) + ); + (* dont_touch *) + PBIDIR_18_18_NT_DR_V i_muxed_v_08 ( + .PO ( ), + .Y ( pads_to_mux_o.muxed_v_08.pad2chip ), + .PAD ( pad_muxed_v_08_pad ), + .A ( mux_to_pads_i.muxed_v_08.chip2pad ), + .DS0 ( 1'b0 ), + .DS1 ( 1'b0 ), + .IE ( mux_to_pads_i.muxed_v_08.input_en ), + .IS ( 1'b0 ), + .OE ( mux_to_pads_i.muxed_v_08.output_en ), + .PE ( mux_to_pads_i.muxed_v_08.pull_en ), + .POE ( 1'b0 ), + .PS ( mux_to_pads_i.muxed_v_08.pull_sel ), + .RTO ( io_pads_rto ), + .SNS ( io_pads_sns ), + .SR ( 1'b0 ) + ); + (* dont_touch *) + PBIDIR_18_18_NT_DR_V i_muxed_v_09 ( + .PO ( ), + .Y ( pads_to_mux_o.muxed_v_09.pad2chip ), + .PAD ( pad_muxed_v_09_pad ), + .A ( mux_to_pads_i.muxed_v_09.chip2pad ), + .DS0 ( 1'b0 ), + .DS1 ( 1'b0 ), + .IE ( mux_to_pads_i.muxed_v_09.input_en ), + .IS ( 1'b0 ), + .OE ( mux_to_pads_i.muxed_v_09.output_en ), + .PE ( mux_to_pads_i.muxed_v_09.pull_en ), + .POE ( 1'b0 ), + .PS ( mux_to_pads_i.muxed_v_09.pull_sel ), + .RTO ( io_pads_rto ), + .SNS ( io_pads_sns ), + .SR ( 1'b0 ) + ); + (* dont_touch *) + PBIDIR_18_18_NT_DR_V i_muxed_v_10 ( + .PO ( ), + .Y ( pads_to_mux_o.muxed_v_10.pad2chip ), + .PAD ( pad_muxed_v_10_pad ), + .A ( mux_to_pads_i.muxed_v_10.chip2pad ), + .DS0 ( 1'b0 ), + .DS1 ( 1'b0 ), + .IE ( mux_to_pads_i.muxed_v_10.input_en ), + .IS ( 1'b0 ), + .OE ( mux_to_pads_i.muxed_v_10.output_en ), + .PE ( mux_to_pads_i.muxed_v_10.pull_en ), + .POE ( 1'b0 ), + .PS ( mux_to_pads_i.muxed_v_10.pull_sel ), + .RTO ( io_pads_rto ), + .SNS ( io_pads_sns ), + .SR ( 1'b0 ) + ); + (* dont_touch *) + PBIDIR_18_18_NT_DR_V i_muxed_v_11 ( + .PO ( ), + .Y ( pads_to_mux_o.muxed_v_11.pad2chip ), + .PAD ( pad_muxed_v_11_pad ), + .A ( mux_to_pads_i.muxed_v_11.chip2pad ), + .DS0 ( 1'b0 ), + .DS1 ( 1'b0 ), + .IE ( mux_to_pads_i.muxed_v_11.input_en ), + .IS ( 1'b0 ), + .OE ( mux_to_pads_i.muxed_v_11.output_en ), + .PE ( mux_to_pads_i.muxed_v_11.pull_en ), + .POE ( 1'b0 ), + .PS ( mux_to_pads_i.muxed_v_11.pull_sel ), + .RTO ( io_pads_rto ), + .SNS ( io_pads_sns ), + .SR ( 1'b0 ) + ); + (* dont_touch *) + PBIDIR_18_18_NT_DR_V i_muxed_v_12 ( + .PO ( ), + .Y ( pads_to_mux_o.muxed_v_12.pad2chip ), + .PAD ( pad_muxed_v_12_pad ), + .A ( mux_to_pads_i.muxed_v_12.chip2pad ), + .DS0 ( 1'b0 ), + .DS1 ( 1'b0 ), + .IE ( mux_to_pads_i.muxed_v_12.input_en ), + .IS ( 1'b0 ), + .OE ( mux_to_pads_i.muxed_v_12.output_en ), + .PE ( mux_to_pads_i.muxed_v_12.pull_en ), + .POE ( 1'b0 ), + .PS ( mux_to_pads_i.muxed_v_12.pull_sel ), + .RTO ( io_pads_rto ), + .SNS ( io_pads_sns ), + .SR ( 1'b0 ) + ); + (* dont_touch *) + PBIDIR_18_18_NT_DR_V i_muxed_v_13 ( + .PO ( ), + .Y ( pads_to_mux_o.muxed_v_13.pad2chip ), + .PAD ( pad_muxed_v_13_pad ), + .A ( mux_to_pads_i.muxed_v_13.chip2pad ), + .DS0 ( 1'b0 ), + .DS1 ( 1'b0 ), + .IE ( mux_to_pads_i.muxed_v_13.input_en ), + .IS ( 1'b0 ), + .OE ( mux_to_pads_i.muxed_v_13.output_en ), + .PE ( mux_to_pads_i.muxed_v_13.pull_en ), + .POE ( 1'b0 ), + .PS ( mux_to_pads_i.muxed_v_13.pull_sel ), + .RTO ( io_pads_rto ), + .SNS ( io_pads_sns ), + .SR ( 1'b0 ) + ); + (* dont_touch *) + PBIDIR_18_18_NT_DR_V i_muxed_v_14 ( + .PO ( ), + .Y ( pads_to_mux_o.muxed_v_14.pad2chip ), + .PAD ( pad_muxed_v_14_pad ), + .A ( mux_to_pads_i.muxed_v_14.chip2pad ), + .DS0 ( 1'b0 ), + .DS1 ( 1'b0 ), + .IE ( mux_to_pads_i.muxed_v_14.input_en ), + .IS ( 1'b0 ), + .OE ( mux_to_pads_i.muxed_v_14.output_en ), + .PE ( mux_to_pads_i.muxed_v_14.pull_en ), + .POE ( 1'b0 ), + .PS ( mux_to_pads_i.muxed_v_14.pull_sel ), + .RTO ( io_pads_rto ), + .SNS ( io_pads_sns ), + .SR ( 1'b0 ) + ); + (* dont_touch *) + PBIDIR_18_18_NT_DR_V i_muxed_v_15 ( + .PO ( ), + .Y ( pads_to_mux_o.muxed_v_15.pad2chip ), + .PAD ( pad_muxed_v_15_pad ), + .A ( mux_to_pads_i.muxed_v_15.chip2pad ), + .DS0 ( 1'b0 ), + .DS1 ( 1'b0 ), + .IE ( mux_to_pads_i.muxed_v_15.input_en ), + .IS ( 1'b0 ), + .OE ( mux_to_pads_i.muxed_v_15.output_en ), + .PE ( mux_to_pads_i.muxed_v_15.pull_en ), + .POE ( 1'b0 ), + .PS ( mux_to_pads_i.muxed_v_15.pull_sel ), + .RTO ( io_pads_rto ), + .SNS ( io_pads_sns ), + .SR ( 1'b0 ) + ); + (* dont_touch *) + PBIDIR_18_18_NT_DR_V i_muxed_v_16 ( + .PO ( ), + .Y ( pads_to_mux_o.muxed_v_16.pad2chip ), + .PAD ( pad_muxed_v_16_pad ), + .A ( mux_to_pads_i.muxed_v_16.chip2pad ), + .DS0 ( 1'b0 ), + .DS1 ( 1'b0 ), + .IE ( mux_to_pads_i.muxed_v_16.input_en ), + .IS ( 1'b0 ), + .OE ( mux_to_pads_i.muxed_v_16.output_en ), + .PE ( mux_to_pads_i.muxed_v_16.pull_en ), + .POE ( 1'b0 ), + .PS ( mux_to_pads_i.muxed_v_16.pull_sel ), + .RTO ( io_pads_rto ), + .SNS ( io_pads_sns ), + .SR ( 1'b0 ) + ); + (* dont_touch *) + PBIDIR_18_18_NT_DR_V i_muxed_v_17 ( + .PO ( ), + .Y ( pads_to_mux_o.muxed_v_17.pad2chip ), + .PAD ( pad_muxed_v_17_pad ), + .A ( mux_to_pads_i.muxed_v_17.chip2pad ), + .DS0 ( 1'b0 ), + .DS1 ( 1'b0 ), + .IE ( mux_to_pads_i.muxed_v_17.input_en ), + .IS ( 1'b0 ), + .OE ( mux_to_pads_i.muxed_v_17.output_en ), + .PE ( mux_to_pads_i.muxed_v_17.pull_en ), + .POE ( 1'b0 ), + .PS ( mux_to_pads_i.muxed_v_17.pull_sel ), + .RTO ( io_pads_rto ), + .SNS ( io_pads_sns ), + .SR ( 1'b0 ) + ); + (* dont_touch *) + PBIDIR_18_18_NT_DR_H i_muxed_h_00 ( + .PO ( ), + .Y ( pads_to_mux_o.muxed_h_00.pad2chip ), + .PAD ( pad_muxed_h_00_pad ), + .A ( mux_to_pads_i.muxed_h_00.chip2pad ), + .DS0 ( 1'b0 ), + .DS1 ( 1'b0 ), + .IE ( mux_to_pads_i.muxed_h_00.input_en ), + .IS ( 1'b0 ), + .OE ( mux_to_pads_i.muxed_h_00.output_en ), + .PE ( mux_to_pads_i.muxed_h_00.pull_en ), + .POE ( 1'b0 ), + .PS ( mux_to_pads_i.muxed_h_00.pull_sel ), + .RTO ( io_pads_rto ), + .SNS ( io_pads_sns ), + .SR ( 1'b0 ) + ); + (* dont_touch *) + PBIDIR_18_18_NT_DR_H i_muxed_h_01 ( + .PO ( ), + .Y ( pads_to_mux_o.muxed_h_01.pad2chip ), + .PAD ( pad_muxed_h_01_pad ), + .A ( mux_to_pads_i.muxed_h_01.chip2pad ), + .DS0 ( 1'b0 ), + .DS1 ( 1'b0 ), + .IE ( mux_to_pads_i.muxed_h_01.input_en ), + .IS ( 1'b0 ), + .OE ( mux_to_pads_i.muxed_h_01.output_en ), + .PE ( mux_to_pads_i.muxed_h_01.pull_en ), + .POE ( 1'b0 ), + .PS ( mux_to_pads_i.muxed_h_01.pull_sel ), + .RTO ( io_pads_rto ), + .SNS ( io_pads_sns ), + .SR ( 1'b0 ) + ); + (* dont_touch *) + PBIDIR_18_18_NT_DR_H i_muxed_h_02 ( + .PO ( ), + .Y ( pads_to_mux_o.muxed_h_02.pad2chip ), + .PAD ( pad_muxed_h_02_pad ), + .A ( mux_to_pads_i.muxed_h_02.chip2pad ), + .DS0 ( 1'b0 ), + .DS1 ( 1'b0 ), + .IE ( mux_to_pads_i.muxed_h_02.input_en ), + .IS ( 1'b0 ), + .OE ( mux_to_pads_i.muxed_h_02.output_en ), + .PE ( mux_to_pads_i.muxed_h_02.pull_en ), + .POE ( 1'b0 ), + .PS ( mux_to_pads_i.muxed_h_02.pull_sel ), + .RTO ( io_pads_rto ), + .SNS ( io_pads_sns ), + .SR ( 1'b0 ) + ); + (* dont_touch *) + PBIDIR_18_18_NT_DR_H i_muxed_h_03 ( + .PO ( ), + .Y ( pads_to_mux_o.muxed_h_03.pad2chip ), + .PAD ( pad_muxed_h_03_pad ), + .A ( mux_to_pads_i.muxed_h_03.chip2pad ), + .DS0 ( 1'b0 ), + .DS1 ( 1'b0 ), + .IE ( mux_to_pads_i.muxed_h_03.input_en ), + .IS ( 1'b0 ), + .OE ( mux_to_pads_i.muxed_h_03.output_en ), + .PE ( mux_to_pads_i.muxed_h_03.pull_en ), + .POE ( 1'b0 ), + .PS ( mux_to_pads_i.muxed_h_03.pull_sel ), + .RTO ( io_pads_rto ), + .SNS ( io_pads_sns ), + .SR ( 1'b0 ) + ); + +endmodule : astral_padframe_periph_pads diff --git a/hw/padframe/astral_padframe/src/astral_padframe_periph_pads.sv.original b/hw/padframe/astral_padframe/src/astral_padframe_periph_pads.sv.original new file mode 100644 index 00000000..2469469f --- /dev/null +++ b/hw/padframe/astral_padframe/src/astral_padframe_periph_pads.sv.original @@ -0,0 +1,1280 @@ + +// File auto-generated by Padrick unknown +module astral_padframe_periph_pads + import pkg_astral_padframe::*; + import pkg_internal_astral_padframe_periph::*; +( + output pad_domain_periph_static_connection_signals_pad2soc_t static_connection_signals_pad2soc, + input pad_domain_periph_static_connection_signals_soc2pad_t static_connection_signals_soc2pad, + // Dynamic Pad control signals, these signals are controlled by the multiplexer in the correpsongin pad_controller module + input mux_to_pads_t mux_to_pads_i, + output pads_to_mux_t pads_to_mux_o, + // Landing Pads + inout wire logic pad_ref_clk_pad, + inout wire logic pad_fll_host_pad, + inout wire logic pad_fll_periph_pad, + inout wire logic pad_fll_alt_pad, + inout wire logic pad_fll_rt_pad, + inout wire logic pad_fll_bypass_pad, + inout wire logic pad_pwr_on_rst_n_pad, + inout wire logic pad_secure_boot_pad, + inout wire logic pad_jtag_tclk_pad, + inout wire logic pad_jtag_trst_n_pad, + inout wire logic pad_jtag_tms_pad, + inout wire logic pad_jtag_tdi_pad, + inout wire logic pad_jtag_tdo_pad, + inout wire logic pad_test_mode_pad, + inout wire logic pad_boot_mode_0_pad, + inout wire logic pad_boot_mode_1_pad, + inout wire logic pad_ot_boot_mode_pad, + inout wire logic pad_jtag_ot_tclk_pad, + inout wire logic pad_jtag_ot_trst_ni_pad, + inout wire logic pad_jtag_ot_tms_pad, + inout wire logic pad_jtag_ot_tdi_pad, + inout wire logic pad_jtag_ot_tdo_pad, + inout wire logic pad_hyper_cs_0_n_pad, + inout wire logic pad_hyper_cs_1_n_pad, + inout wire logic pad_hyper_ck_pad, + inout wire logic pad_hyper_ck_n_pad, + inout wire logic pad_hyper_rwds_pad, + inout wire logic pad_hyper_dq_0_pad, + inout wire logic pad_hyper_dq_1_pad, + inout wire logic pad_hyper_dq_2_pad, + inout wire logic pad_hyper_dq_3_pad, + inout wire logic pad_hyper_dq_4_pad, + inout wire logic pad_hyper_dq_5_pad, + inout wire logic pad_hyper_dq_6_pad, + inout wire logic pad_hyper_dq_7_pad, + inout wire logic pad_hyper_reset_n_pad, + inout wire logic pad_spw_data_in_pad, + inout wire logic pad_spw_strb_in_pad, + inout wire logic pad_spw_data_out_pad, + inout wire logic pad_spw_strb_out_pad, + inout wire logic pad_uart_tx_out_pad, + inout wire logic pad_uart_rx_in_pad, + inout wire logic pad_muxed_v_00_pad, + inout wire logic pad_muxed_v_01_pad, + inout wire logic pad_muxed_v_02_pad, + inout wire logic pad_muxed_v_03_pad, + inout wire logic pad_muxed_v_04_pad, + inout wire logic pad_muxed_v_05_pad, + inout wire logic pad_muxed_v_06_pad, + inout wire logic pad_muxed_v_07_pad, + inout wire logic pad_muxed_v_08_pad, + inout wire logic pad_muxed_v_09_pad, + inout wire logic pad_muxed_v_10_pad, + inout wire logic pad_muxed_v_11_pad, + inout wire logic pad_muxed_v_12_pad, + inout wire logic pad_muxed_v_13_pad, + inout wire logic pad_muxed_v_14_pad, + inout wire logic pad_muxed_v_15_pad, + inout wire logic pad_muxed_v_16_pad, + inout wire logic pad_muxed_v_17_pad, + inout wire logic pad_muxed_h_00_pad, + inout wire logic pad_muxed_h_01_pad, + inout wire logic pad_muxed_h_02_pad, + inout wire logic pad_muxed_h_03_pad + ); + + // Pad instantiations + wire io_pads_rto; + wire io_pads_sns; + + PDVDDTIE_18_18_NT_DR_V i_pad_tie_io ( + .SNS( io_pads_sns ), + .RTO( io_pads_rto ) + ); + PDVDD_18_18_NT_DR_H i_pad_dvdd_io_h_0 ( .SNS( io_pads_sns ), .RTO( io_pads_rto ) ); + PDVDD_18_18_NT_DR_H i_pad_dvdd_io_h_1 ( .SNS( io_pads_sns ), .RTO( io_pads_rto ) ); + PDVDD_18_18_NT_DR_V i_pad_dvdd_io_v_0 ( .SNS( io_pads_sns ), .RTO( io_pads_rto ) ); + PDVDD_18_18_NT_DR_V i_pad_dvdd_io_v_1 ( .SNS( io_pads_sns ), .RTO( io_pads_rto ) ); + PDVDD_18_18_NT_DR_V i_pad_dvdd_io_v_2 ( .SNS( io_pads_sns ), .RTO( io_pads_rto ) ); + PDVDD_18_18_NT_DR_V i_pad_dvdd_io_v_3 ( .SNS( io_pads_sns ), .RTO( io_pads_rto ) ); + PDVDD_18_18_NT_DR_V i_pad_dvdd_io_v_4 ( .SNS( io_pads_sns ), .RTO( io_pads_rto ) ); + PDVDD_18_18_NT_DR_V i_pad_dvdd_io_v_5 ( .SNS( io_pads_sns ), .RTO( io_pads_rto ) ); + PDVSS_18_18_NT_DR_H i_pad_dvss_io_h_0 ( .SNS( io_pads_sns ), .RTO( io_pads_rto ) ); + PDVSS_18_18_NT_DR_H i_pad_dvss_io_h_1 ( .SNS( io_pads_sns ), .RTO( io_pads_rto ) ); + PDVSS_18_18_NT_DR_V i_pad_dvss_io_v_0 ( .SNS( io_pads_sns ), .RTO( io_pads_rto ) ); + PDVSS_18_18_NT_DR_V i_pad_dvss_io_v_1 ( .SNS( io_pads_sns ), .RTO( io_pads_rto ) ); + PDVSS_18_18_NT_DR_V i_pad_dvss_io_v_2 ( .SNS( io_pads_sns ), .RTO( io_pads_rto ) ); + PDVSS_18_18_NT_DR_V i_pad_dvss_io_v_3 ( .SNS( io_pads_sns ), .RTO( io_pads_rto ) ); + PDVSS_18_18_NT_DR_V i_pad_dvss_io_v_4 ( .SNS( io_pads_sns ), .RTO( io_pads_rto ) ); + PDVSS_18_18_NT_DR_V i_pad_dvss_io_v_5 ( .SNS( io_pads_sns ), .RTO( io_pads_rto ) ); + PVDD_08_08_NT_DR_H i_pad_vdd_core_h_0 ( .SNS( io_pads_sns ), .RTO( io_pads_rto ) ); + PVDD_08_08_NT_DR_H i_pad_vdd_core_h_1 ( .SNS( io_pads_sns ), .RTO( io_pads_rto ) ); + PVDD_08_08_NT_DR_H i_pad_vdd_core_h_2 ( .SNS( io_pads_sns ), .RTO( io_pads_rto ) ); + PVDD_08_08_NT_DR_H i_pad_vdd_core_h_3 ( .SNS( io_pads_sns ), .RTO( io_pads_rto ) ); + PVDD_08_08_NT_DR_V i_pad_vdd_core_v_0 ( .SNS( io_pads_sns ), .RTO( io_pads_rto ) ); + PVDD_08_08_NT_DR_V i_pad_vdd_core_v_1 ( .SNS( io_pads_sns ), .RTO( io_pads_rto ) ); + PVDD_08_08_NT_DR_V i_pad_vdd_core_v_2 ( .SNS( io_pads_sns ), .RTO( io_pads_rto ) ); + PVDD_08_08_NT_DR_V i_pad_vdd_core_v_3 ( .SNS( io_pads_sns ), .RTO( io_pads_rto ) ); + PVDD_08_08_NT_DR_V i_pad_vdd_core_v_4 ( .SNS( io_pads_sns ), .RTO( io_pads_rto ) ); + PVDD_08_08_NT_DR_V i_pad_vdd_core_v_5 ( .SNS( io_pads_sns ), .RTO( io_pads_rto ) ); + PVSS_08_08_NT_DR_H i_pad_vss_core_h_0 ( .SNS( io_pads_sns ), .RTO( io_pads_rto ) ); + PVSS_08_08_NT_DR_H i_pad_vss_core_h_1 ( .SNS( io_pads_sns ), .RTO( io_pads_rto ) ); + PVSS_08_08_NT_DR_H i_pad_vss_core_h_2 ( .SNS( io_pads_sns ), .RTO( io_pads_rto ) ); + PVSS_08_08_NT_DR_H i_pad_vss_core_h_3 ( .SNS( io_pads_sns ), .RTO( io_pads_rto ) ); + PVSS_08_08_NT_DR_V i_pad_vss_core_v_0 ( .SNS( io_pads_sns ), .RTO( io_pads_rto ) ); + PVSS_08_08_NT_DR_V i_pad_vss_core_v_1 ( .SNS( io_pads_sns ), .RTO( io_pads_rto ) ); + PVSS_08_08_NT_DR_V i_pad_vss_core_v_2 ( .SNS( io_pads_sns ), .RTO( io_pads_rto ) ); + PVSS_08_08_NT_DR_V i_pad_vss_core_v_3 ( .SNS( io_pads_sns ), .RTO( io_pads_rto ) ); + PVSS_08_08_NT_DR_V i_pad_vss_core_v_4 ( .SNS( io_pads_sns ), .RTO( io_pads_rto ) ); + PVSS_08_08_NT_DR_V i_pad_vss_core_v_5 ( .SNS( io_pads_sns ), .RTO( io_pads_rto ) ); + PCORNER_18_18_NT_DR i_pad_corner_0 ( .SNS( io_pads_sns ), .RTO( io_pads_rto ) ); + PCORNER_18_18_NT_DR i_pad_corner_1 ( .SNS( io_pads_sns ), .RTO( io_pads_rto ) ); + PCORNER_18_18_NT_DR i_pad_corner_2 ( .SNS( io_pads_sns ), .RTO( io_pads_rto ) ); + PCORNER_18_18_NT_DR i_pad_corner_3 ( .SNS( io_pads_sns ), .RTO( io_pads_rto ) ); + (* dont_touch *) + PBIDIR_18_18_NT_DR_H i_ref_clk ( + .PO ( ), + .Y ( static_connection_signals_pad2soc.ref_clk_i ), + .PAD ( pad_ref_clk_pad ), + .A ( 1'b0 ), + .DS0 ( 1'b0 ), + .DS1 ( 1'b0 ), + .IE ( 1'b1 ), + .IS ( 1'b0 ), + .OE ( 1'b0 ), + .PE ( 1'b0 ), + .POE ( 1'b0 ), + .PS ( 1'b0 ), + .RTO ( io_pads_rto ), + .SNS ( io_pads_sns ), + .SR ( 1'b0 ) + ); + (* dont_touch *) + PBIDIR_18_18_NT_DR_H i_fll_host ( + .PO ( ), + .Y ( ), + .PAD ( pad_fll_host_pad ), + .A ( static_connection_signals_soc2pad.fll_host_clk_o ), + .DS0 ( 1'b0 ), + .DS1 ( 1'b0 ), + .IE ( 1'b0 ), + .IS ( 1'b0 ), + .OE ( 1'b1 ), + .PE ( 1'b0 ), + .POE ( 1'b0 ), + .PS ( 1'b0 ), + .RTO ( io_pads_rto ), + .SNS ( io_pads_sns ), + .SR ( 1'b0 ) + ); + (* dont_touch *) + PBIDIR_18_18_NT_DR_H i_fll_periph ( + .PO ( ), + .Y ( ), + .PAD ( pad_fll_periph_pad ), + .A ( static_connection_signals_soc2pad.fll_periph_clk_o ), + .DS0 ( 1'b0 ), + .DS1 ( 1'b0 ), + .IE ( 1'b0 ), + .IS ( 1'b0 ), + .OE ( 1'b1 ), + .PE ( 1'b0 ), + .POE ( 1'b0 ), + .PS ( 1'b0 ), + .RTO ( io_pads_rto ), + .SNS ( io_pads_sns ), + .SR ( 1'b0 ) + ); + (* dont_touch *) + PBIDIR_18_18_NT_DR_H i_fll_alt ( + .PO ( ), + .Y ( ), + .PAD ( pad_fll_alt_pad ), + .A ( static_connection_signals_soc2pad.fll_alt_clk_o ), + .DS0 ( 1'b0 ), + .DS1 ( 1'b0 ), + .IE ( 1'b0 ), + .IS ( 1'b0 ), + .OE ( 1'b1 ), + .PE ( 1'b0 ), + .POE ( 1'b0 ), + .PS ( 1'b0 ), + .RTO ( io_pads_rto ), + .SNS ( io_pads_sns ), + .SR ( 1'b0 ) + ); + (* dont_touch *) + PBIDIR_18_18_NT_DR_H i_fll_rt ( + .PO ( ), + .Y ( ), + .PAD ( pad_fll_rt_pad ), + .A ( static_connection_signals_soc2pad.fll_rt_clk_o ), + .DS0 ( 1'b0 ), + .DS1 ( 1'b0 ), + .IE ( 1'b0 ), + .IS ( 1'b0 ), + .OE ( 1'b1 ), + .PE ( 1'b0 ), + .POE ( 1'b0 ), + .PS ( 1'b0 ), + .RTO ( io_pads_rto ), + .SNS ( io_pads_sns ), + .SR ( 1'b0 ) + ); + (* dont_touch *) + PBIDIR_18_18_NT_DR_H i_fll_bypass ( + .PO ( ), + .Y ( static_connection_signals_pad2soc.fll_bypass_i ), + .PAD ( pad_fll_bypass_pad ), + .A ( 1'b0 ), + .DS0 ( 1'b0 ), + .DS1 ( 1'b0 ), + .IE ( 1'b1 ), + .IS ( 1'b0 ), + .OE ( 1'b0 ), + .PE ( 1'b0 ), + .POE ( 1'b0 ), + .PS ( 1'b0 ), + .RTO ( io_pads_rto ), + .SNS ( io_pads_sns ), + .SR ( 1'b0 ) + ); + (* dont_touch *) + PBIDIR_18_18_NT_DR_H i_pwr_on_rst_n ( + .PO ( ), + .Y ( static_connection_signals_pad2soc.pwr_on_rst_ni ), + .PAD ( pad_pwr_on_rst_n_pad ), + .A ( 1'b0 ), + .DS0 ( 1'b0 ), + .DS1 ( 1'b0 ), + .IE ( 1'b1 ), + .IS ( 1'b0 ), + .OE ( 1'b0 ), + .PE ( 1'b0 ), + .POE ( 1'b0 ), + .PS ( 1'b0 ), + .RTO ( io_pads_rto ), + .SNS ( io_pads_sns ), + .SR ( 1'b0 ) + ); + (* dont_touch *) + PBIDIR_18_18_NT_DR_H i_secure_boot ( + .PO ( ), + .Y ( static_connection_signals_pad2soc.secure_boot_i ), + .PAD ( pad_secure_boot_pad ), + .A ( 1'b0 ), + .DS0 ( 1'b0 ), + .DS1 ( 1'b0 ), + .IE ( 1'b1 ), + .IS ( 1'b0 ), + .OE ( 1'b0 ), + .PE ( 1'b0 ), + .POE ( 1'b0 ), + .PS ( 1'b0 ), + .RTO ( io_pads_rto ), + .SNS ( io_pads_sns ), + .SR ( 1'b0 ) + ); + (* dont_touch *) + PBIDIR_18_18_NT_DR_H i_jtag_tclk ( + .PO ( ), + .Y ( static_connection_signals_pad2soc.jtag_tclk_i ), + .PAD ( pad_jtag_tclk_pad ), + .A ( 1'b0 ), + .DS0 ( 1'b0 ), + .DS1 ( 1'b0 ), + .IE ( 1'b1 ), + .IS ( 1'b0 ), + .OE ( 1'b0 ), + .PE ( 1'b0 ), + .POE ( 1'b0 ), + .PS ( 1'b0 ), + .RTO ( io_pads_rto ), + .SNS ( io_pads_sns ), + .SR ( 1'b0 ) + ); + (* dont_touch *) + PBIDIR_18_18_NT_DR_H i_jtag_trst_n ( + .PO ( ), + .Y ( static_connection_signals_pad2soc.jtag_trst_ni ), + .PAD ( pad_jtag_trst_n_pad ), + .A ( 1'b0 ), + .DS0 ( 1'b0 ), + .DS1 ( 1'b0 ), + .IE ( 1'b1 ), + .IS ( 1'b0 ), + .OE ( 1'b0 ), + .PE ( 1'b0 ), + .POE ( 1'b0 ), + .PS ( 1'b0 ), + .RTO ( io_pads_rto ), + .SNS ( io_pads_sns ), + .SR ( 1'b0 ) + ); + (* dont_touch *) + PBIDIR_18_18_NT_DR_H i_jtag_tms ( + .PO ( ), + .Y ( static_connection_signals_pad2soc.jtag_tms_i ), + .PAD ( pad_jtag_tms_pad ), + .A ( 1'b0 ), + .DS0 ( 1'b0 ), + .DS1 ( 1'b0 ), + .IE ( 1'b1 ), + .IS ( 1'b0 ), + .OE ( 1'b0 ), + .PE ( 1'b0 ), + .POE ( 1'b0 ), + .PS ( 1'b0 ), + .RTO ( io_pads_rto ), + .SNS ( io_pads_sns ), + .SR ( 1'b0 ) + ); + (* dont_touch *) + PBIDIR_18_18_NT_DR_H i_jtag_tdi ( + .PO ( ), + .Y ( static_connection_signals_pad2soc.jtag_tdi_i ), + .PAD ( pad_jtag_tdi_pad ), + .A ( 1'b0 ), + .DS0 ( 1'b0 ), + .DS1 ( 1'b0 ), + .IE ( 1'b1 ), + .IS ( 1'b0 ), + .OE ( 1'b0 ), + .PE ( 1'b0 ), + .POE ( 1'b0 ), + .PS ( 1'b0 ), + .RTO ( io_pads_rto ), + .SNS ( io_pads_sns ), + .SR ( 1'b0 ) + ); + (* dont_touch *) + PBIDIR_18_18_NT_DR_H i_jtag_tdo ( + .PO ( ), + .Y ( ), + .PAD ( pad_jtag_tdo_pad ), + .A ( static_connection_signals_soc2pad.jtag_tdo_o ), + .DS0 ( 1'b0 ), + .DS1 ( 1'b0 ), + .IE ( 1'b0 ), + .IS ( 1'b0 ), + .OE ( 1'b1 ), + .PE ( 1'b0 ), + .POE ( 1'b0 ), + .PS ( 1'b0 ), + .RTO ( io_pads_rto ), + .SNS ( io_pads_sns ), + .SR ( 1'b0 ) + ); + (* dont_touch *) + PBIDIR_18_18_NT_DR_H i_test_mode ( + .PO ( ), + .Y ( static_connection_signals_pad2soc.test_mode_i ), + .PAD ( pad_test_mode_pad ), + .A ( 1'b0 ), + .DS0 ( 1'b0 ), + .DS1 ( 1'b0 ), + .IE ( 1'b1 ), + .IS ( 1'b0 ), + .OE ( 1'b0 ), + .PE ( 1'b0 ), + .POE ( 1'b0 ), + .PS ( 1'b0 ), + .RTO ( io_pads_rto ), + .SNS ( io_pads_sns ), + .SR ( 1'b0 ) + ); + (* dont_touch *) + PBIDIR_18_18_NT_DR_H i_boot_mode_0 ( + .PO ( ), + .Y ( static_connection_signals_pad2soc.boot_mode_0_i ), + .PAD ( pad_boot_mode_0_pad ), + .A ( 1'b0 ), + .DS0 ( 1'b0 ), + .DS1 ( 1'b0 ), + .IE ( 1'b1 ), + .IS ( 1'b0 ), + .OE ( 1'b0 ), + .PE ( 1'b0 ), + .POE ( 1'b0 ), + .PS ( 1'b0 ), + .RTO ( io_pads_rto ), + .SNS ( io_pads_sns ), + .SR ( 1'b0 ) + ); + (* dont_touch *) + PBIDIR_18_18_NT_DR_H i_boot_mode_1 ( + .PO ( ), + .Y ( static_connection_signals_pad2soc.boot_mode_1_i ), + .PAD ( pad_boot_mode_1_pad ), + .A ( 1'b0 ), + .DS0 ( 1'b0 ), + .DS1 ( 1'b0 ), + .IE ( 1'b1 ), + .IS ( 1'b0 ), + .OE ( 1'b0 ), + .PE ( 1'b0 ), + .POE ( 1'b0 ), + .PS ( 1'b0 ), + .RTO ( io_pads_rto ), + .SNS ( io_pads_sns ), + .SR ( 1'b0 ) + ); + (* dont_touch *) + PBIDIR_18_18_NT_DR_H i_ot_boot_mode ( + .PO ( ), + .Y ( static_connection_signals_pad2soc.ot_boot_mode_i ), + .PAD ( pad_ot_boot_mode_pad ), + .A ( 1'b0 ), + .DS0 ( 1'b0 ), + .DS1 ( 1'b0 ), + .IE ( 1'b1 ), + .IS ( 1'b0 ), + .OE ( 1'b0 ), + .PE ( 1'b0 ), + .POE ( 1'b0 ), + .PS ( 1'b0 ), + .RTO ( io_pads_rto ), + .SNS ( io_pads_sns ), + .SR ( 1'b0 ) + ); + (* dont_touch *) + PBIDIR_18_18_NT_DR_H i_jtag_ot_tclk ( + .PO ( ), + .Y ( static_connection_signals_pad2soc.jtag_ot_tclk_i ), + .PAD ( pad_jtag_ot_tclk_pad ), + .A ( 1'b0 ), + .DS0 ( 1'b0 ), + .DS1 ( 1'b0 ), + .IE ( 1'b1 ), + .IS ( 1'b0 ), + .OE ( 1'b0 ), + .PE ( 1'b0 ), + .POE ( 1'b0 ), + .PS ( 1'b0 ), + .RTO ( io_pads_rto ), + .SNS ( io_pads_sns ), + .SR ( 1'b0 ) + ); + (* dont_touch *) + PBIDIR_18_18_NT_DR_H i_jtag_ot_trst_ni ( + .PO ( ), + .Y ( static_connection_signals_pad2soc.jtag_ot_trst_ni ), + .PAD ( pad_jtag_ot_trst_ni_pad ), + .A ( 1'b0 ), + .DS0 ( 1'b0 ), + .DS1 ( 1'b0 ), + .IE ( 1'b1 ), + .IS ( 1'b0 ), + .OE ( 1'b0 ), + .PE ( 1'b0 ), + .POE ( 1'b0 ), + .PS ( 1'b0 ), + .RTO ( io_pads_rto ), + .SNS ( io_pads_sns ), + .SR ( 1'b0 ) + ); + (* dont_touch *) + PBIDIR_18_18_NT_DR_H i_jtag_ot_tms ( + .PO ( ), + .Y ( static_connection_signals_pad2soc.jtag_ot_tms_i ), + .PAD ( pad_jtag_ot_tms_pad ), + .A ( 1'b0 ), + .DS0 ( 1'b0 ), + .DS1 ( 1'b0 ), + .IE ( 1'b1 ), + .IS ( 1'b0 ), + .OE ( 1'b0 ), + .PE ( 1'b0 ), + .POE ( 1'b0 ), + .PS ( 1'b0 ), + .RTO ( io_pads_rto ), + .SNS ( io_pads_sns ), + .SR ( 1'b0 ) + ); + (* dont_touch *) + PBIDIR_18_18_NT_DR_H i_jtag_ot_tdi ( + .PO ( ), + .Y ( static_connection_signals_pad2soc.jtag_ot_tdi_i ), + .PAD ( pad_jtag_ot_tdi_pad ), + .A ( 1'b0 ), + .DS0 ( 1'b0 ), + .DS1 ( 1'b0 ), + .IE ( 1'b1 ), + .IS ( 1'b0 ), + .OE ( 1'b0 ), + .PE ( 1'b0 ), + .POE ( 1'b0 ), + .PS ( 1'b0 ), + .RTO ( io_pads_rto ), + .SNS ( io_pads_sns ), + .SR ( 1'b0 ) + ); + (* dont_touch *) + PBIDIR_18_18_NT_DR_H i_jtag_ot_tdo ( + .PO ( ), + .Y ( ), + .PAD ( pad_jtag_ot_tdo_pad ), + .A ( static_connection_signals_soc2pad.jtag_ot_tdo_o ), + .DS0 ( 1'b0 ), + .DS1 ( 1'b0 ), + .IE ( 1'b0 ), + .IS ( 1'b0 ), + .OE ( 1'b1 ), + .PE ( 1'b0 ), + .POE ( 1'b0 ), + .PS ( 1'b0 ), + .RTO ( io_pads_rto ), + .SNS ( io_pads_sns ), + .SR ( 1'b0 ) + ); + (* dont_touch *) + PBIDIR_18_18_NT_DR_V i_hyper_cs_0_n ( + .PO ( ), + .Y ( ), + .PAD ( pad_hyper_cs_0_n_pad ), + .A ( static_connection_signals_soc2pad.hyper_cs_0_no ), + .DS0 ( 1'b0 ), + .DS1 ( 1'b0 ), + .IE ( 1'b0 ), + .IS ( 1'b0 ), + .OE ( 1'b1 ), + .PE ( 1'b0 ), + .POE ( 1'b0 ), + .PS ( 1'b0 ), + .RTO ( io_pads_rto ), + .SNS ( io_pads_sns ), + .SR ( 1'b0 ) + ); + (* dont_touch *) + PBIDIR_18_18_NT_DR_V i_hyper_cs_1_n ( + .PO ( ), + .Y ( ), + .PAD ( pad_hyper_cs_1_n_pad ), + .A ( static_connection_signals_soc2pad.hyper_cs_1_no ), + .DS0 ( 1'b0 ), + .DS1 ( 1'b0 ), + .IE ( 1'b0 ), + .IS ( 1'b0 ), + .OE ( 1'b1 ), + .PE ( 1'b0 ), + .POE ( 1'b0 ), + .PS ( 1'b0 ), + .RTO ( io_pads_rto ), + .SNS ( io_pads_sns ), + .SR ( 1'b0 ) + ); + (* dont_touch *) + PBIDIR_18_18_NT_DR_V i_hyper_ck ( + .PO ( ), + .Y ( ), + .PAD ( pad_hyper_ck_pad ), + .A ( static_connection_signals_soc2pad.hyper_ck_o ), + .DS0 ( 1'b0 ), + .DS1 ( 1'b0 ), + .IE ( 1'b0 ), + .IS ( 1'b0 ), + .OE ( 1'b1 ), + .PE ( 1'b0 ), + .POE ( 1'b0 ), + .PS ( 1'b0 ), + .RTO ( io_pads_rto ), + .SNS ( io_pads_sns ), + .SR ( 1'b0 ) + ); + (* dont_touch *) + PBIDIR_18_18_NT_DR_V i_hyper_ck_n ( + .PO ( ), + .Y ( ), + .PAD ( pad_hyper_ck_n_pad ), + .A ( static_connection_signals_soc2pad.hyper_ck_no ), + .DS0 ( 1'b0 ), + .DS1 ( 1'b0 ), + .IE ( 1'b0 ), + .IS ( 1'b0 ), + .OE ( 1'b1 ), + .PE ( 1'b0 ), + .POE ( 1'b0 ), + .PS ( 1'b0 ), + .RTO ( io_pads_rto ), + .SNS ( io_pads_sns ), + .SR ( 1'b0 ) + ); + (* dont_touch *) + PBIDIR_18_18_NT_DR_V i_hyper_rwds ( + .PO ( ), + .Y ( static_connection_signals_pad2soc.hyper_rwds_i ), + .PAD ( pad_hyper_rwds_pad ), + .A ( static_connection_signals_soc2pad.hyper_rwds_o ), + .DS0 ( 1'b0 ), + .DS1 ( 1'b0 ), + .IE ( ~static_connection_signals_soc2pad.hyper_rwds_oen_i ), + .IS ( 1'b0 ), + .OE ( static_connection_signals_soc2pad.hyper_rwds_oen_i ), + .PE ( 1'b0 ), + .POE ( 1'b0 ), + .PS ( 1'b0 ), + .RTO ( io_pads_rto ), + .SNS ( io_pads_sns ), + .SR ( 1'b0 ) + ); + (* dont_touch *) + PBIDIR_18_18_NT_DR_V i_hyper_dq_0 ( + .PO ( ), + .Y ( static_connection_signals_pad2soc.hyper_dq_0_i ), + .PAD ( pad_hyper_dq_0_pad ), + .A ( static_connection_signals_soc2pad.hyper_dq_0_o ), + .DS0 ( 1'b0 ), + .DS1 ( 1'b0 ), + .IE ( ~static_connection_signals_soc2pad.hyper_dq_oen_i ), + .IS ( 1'b0 ), + .OE ( static_connection_signals_soc2pad.hyper_dq_oen_i ), + .PE ( 1'b0 ), + .POE ( 1'b0 ), + .PS ( 1'b0 ), + .RTO ( io_pads_rto ), + .SNS ( io_pads_sns ), + .SR ( 1'b0 ) + ); + (* dont_touch *) + PBIDIR_18_18_NT_DR_V i_hyper_dq_1 ( + .PO ( ), + .Y ( static_connection_signals_pad2soc.hyper_dq_1_i ), + .PAD ( pad_hyper_dq_1_pad ), + .A ( static_connection_signals_soc2pad.hyper_dq_1_o ), + .DS0 ( 1'b0 ), + .DS1 ( 1'b0 ), + .IE ( ~static_connection_signals_soc2pad.hyper_dq_oen_i ), + .IS ( 1'b0 ), + .OE ( static_connection_signals_soc2pad.hyper_dq_oen_i ), + .PE ( 1'b0 ), + .POE ( 1'b0 ), + .PS ( 1'b0 ), + .RTO ( io_pads_rto ), + .SNS ( io_pads_sns ), + .SR ( 1'b0 ) + ); + (* dont_touch *) + PBIDIR_18_18_NT_DR_V i_hyper_dq_2 ( + .PO ( ), + .Y ( static_connection_signals_pad2soc.hyper_dq_2_i ), + .PAD ( pad_hyper_dq_2_pad ), + .A ( static_connection_signals_soc2pad.hyper_dq_2_o ), + .DS0 ( 1'b0 ), + .DS1 ( 1'b0 ), + .IE ( ~static_connection_signals_soc2pad.hyper_dq_oen_i ), + .IS ( 1'b0 ), + .OE ( static_connection_signals_soc2pad.hyper_dq_oen_i ), + .PE ( 1'b0 ), + .POE ( 1'b0 ), + .PS ( 1'b0 ), + .RTO ( io_pads_rto ), + .SNS ( io_pads_sns ), + .SR ( 1'b0 ) + ); + (* dont_touch *) + PBIDIR_18_18_NT_DR_V i_hyper_dq_3 ( + .PO ( ), + .Y ( static_connection_signals_pad2soc.hyper_dq_3_i ), + .PAD ( pad_hyper_dq_3_pad ), + .A ( static_connection_signals_soc2pad.hyper_dq_3_o ), + .DS0 ( 1'b0 ), + .DS1 ( 1'b0 ), + .IE ( ~static_connection_signals_soc2pad.hyper_dq_oen_i ), + .IS ( 1'b0 ), + .OE ( static_connection_signals_soc2pad.hyper_dq_oen_i ), + .PE ( 1'b0 ), + .POE ( 1'b0 ), + .PS ( 1'b0 ), + .RTO ( io_pads_rto ), + .SNS ( io_pads_sns ), + .SR ( 1'b0 ) + ); + (* dont_touch *) + PBIDIR_18_18_NT_DR_V i_hyper_dq_4 ( + .PO ( ), + .Y ( static_connection_signals_pad2soc.hyper_dq_4_i ), + .PAD ( pad_hyper_dq_4_pad ), + .A ( static_connection_signals_soc2pad.hyper_dq_4_o ), + .DS0 ( 1'b0 ), + .DS1 ( 1'b0 ), + .IE ( ~static_connection_signals_soc2pad.hyper_dq_oen_i ), + .IS ( 1'b0 ), + .OE ( static_connection_signals_soc2pad.hyper_dq_oen_i ), + .PE ( 1'b0 ), + .POE ( 1'b0 ), + .PS ( 1'b0 ), + .RTO ( io_pads_rto ), + .SNS ( io_pads_sns ), + .SR ( 1'b0 ) + ); + (* dont_touch *) + PBIDIR_18_18_NT_DR_V i_hyper_dq_5 ( + .PO ( ), + .Y ( static_connection_signals_pad2soc.hyper_dq_5_i ), + .PAD ( pad_hyper_dq_5_pad ), + .A ( static_connection_signals_soc2pad.hyper_dq_5_o ), + .DS0 ( 1'b0 ), + .DS1 ( 1'b0 ), + .IE ( ~static_connection_signals_soc2pad.hyper_dq_oen_i ), + .IS ( 1'b0 ), + .OE ( static_connection_signals_soc2pad.hyper_dq_oen_i ), + .PE ( 1'b0 ), + .POE ( 1'b0 ), + .PS ( 1'b0 ), + .RTO ( io_pads_rto ), + .SNS ( io_pads_sns ), + .SR ( 1'b0 ) + ); + (* dont_touch *) + PBIDIR_18_18_NT_DR_V i_hyper_dq_6 ( + .PO ( ), + .Y ( static_connection_signals_pad2soc.hyper_dq_6_i ), + .PAD ( pad_hyper_dq_6_pad ), + .A ( static_connection_signals_soc2pad.hyper_dq_6_o ), + .DS0 ( 1'b0 ), + .DS1 ( 1'b0 ), + .IE ( ~static_connection_signals_soc2pad.hyper_dq_oen_i ), + .IS ( 1'b0 ), + .OE ( static_connection_signals_soc2pad.hyper_dq_oen_i ), + .PE ( 1'b0 ), + .POE ( 1'b0 ), + .PS ( 1'b0 ), + .RTO ( io_pads_rto ), + .SNS ( io_pads_sns ), + .SR ( 1'b0 ) + ); + (* dont_touch *) + PBIDIR_18_18_NT_DR_V i_hyper_dq_7 ( + .PO ( ), + .Y ( static_connection_signals_pad2soc.hyper_dq_7_i ), + .PAD ( pad_hyper_dq_7_pad ), + .A ( static_connection_signals_soc2pad.hyper_dq_7_o ), + .DS0 ( 1'b0 ), + .DS1 ( 1'b0 ), + .IE ( ~static_connection_signals_soc2pad.hyper_dq_oen_i ), + .IS ( 1'b0 ), + .OE ( static_connection_signals_soc2pad.hyper_dq_oen_i ), + .PE ( 1'b0 ), + .POE ( 1'b0 ), + .PS ( 1'b0 ), + .RTO ( io_pads_rto ), + .SNS ( io_pads_sns ), + .SR ( 1'b0 ) + ); + (* dont_touch *) + PBIDIR_18_18_NT_DR_V i_hyper_reset_n ( + .PO ( ), + .Y ( ), + .PAD ( pad_hyper_reset_n_pad ), + .A ( static_connection_signals_soc2pad.hyper_reset_no ), + .DS0 ( 1'b0 ), + .DS1 ( 1'b0 ), + .IE ( 1'b0 ), + .IS ( 1'b0 ), + .OE ( 1'b1 ), + .PE ( 1'b0 ), + .POE ( 1'b0 ), + .PS ( 1'b0 ), + .RTO ( io_pads_rto ), + .SNS ( io_pads_sns ), + .SR ( 1'b0 ) + ); + (* dont_touch *) + PBIDIR_18_18_NT_DR_H i_spw_data_in ( + .PO ( ), + .Y ( static_connection_signals_pad2soc.spw_data_i ), + .PAD ( pad_spw_data_in_pad ), + .A ( 1'b0 ), + .DS0 ( 1'b0 ), + .DS1 ( 1'b0 ), + .IE ( 1'b1 ), + .IS ( 1'b0 ), + .OE ( 1'b0 ), + .PE ( 1'b0 ), + .POE ( 1'b0 ), + .PS ( 1'b0 ), + .RTO ( io_pads_rto ), + .SNS ( io_pads_sns ), + .SR ( 1'b0 ) + ); + (* dont_touch *) + PBIDIR_18_18_NT_DR_H i_spw_strb_in ( + .PO ( ), + .Y ( static_connection_signals_pad2soc.spw_strb_i ), + .PAD ( pad_spw_strb_in_pad ), + .A ( 1'b0 ), + .DS0 ( 1'b0 ), + .DS1 ( 1'b0 ), + .IE ( 1'b1 ), + .IS ( 1'b0 ), + .OE ( 1'b0 ), + .PE ( 1'b0 ), + .POE ( 1'b0 ), + .PS ( 1'b0 ), + .RTO ( io_pads_rto ), + .SNS ( io_pads_sns ), + .SR ( 1'b0 ) + ); + (* dont_touch *) + PBIDIR_18_18_NT_DR_H i_spw_data_out ( + .PO ( ), + .Y ( ), + .PAD ( pad_spw_data_out_pad ), + .A ( static_connection_signals_soc2pad.spw_data_o ), + .DS0 ( 1'b0 ), + .DS1 ( 1'b0 ), + .IE ( 1'b0 ), + .IS ( 1'b0 ), + .OE ( 1'b1 ), + .PE ( 1'b0 ), + .POE ( 1'b0 ), + .PS ( 1'b0 ), + .RTO ( io_pads_rto ), + .SNS ( io_pads_sns ), + .SR ( 1'b0 ) + ); + (* dont_touch *) + PBIDIR_18_18_NT_DR_H i_spw_strb_out ( + .PO ( ), + .Y ( ), + .PAD ( pad_spw_strb_out_pad ), + .A ( static_connection_signals_soc2pad.spw_strb_o ), + .DS0 ( 1'b0 ), + .DS1 ( 1'b0 ), + .IE ( 1'b0 ), + .IS ( 1'b0 ), + .OE ( 1'b1 ), + .PE ( 1'b0 ), + .POE ( 1'b0 ), + .PS ( 1'b0 ), + .RTO ( io_pads_rto ), + .SNS ( io_pads_sns ), + .SR ( 1'b0 ) + ); + (* dont_touch *) + PBIDIR_18_18_NT_DR_H i_uart_tx_out ( + .PO ( ), + .Y ( ), + .PAD ( pad_uart_tx_out_pad ), + .A ( static_connection_signals_soc2pad.uart_tx_o ), + .DS0 ( 1'b0 ), + .DS1 ( 1'b0 ), + .IE ( 1'b0 ), + .IS ( 1'b0 ), + .OE ( 1'b1 ), + .PE ( 1'b0 ), + .POE ( 1'b0 ), + .PS ( 1'b0 ), + .RTO ( io_pads_rto ), + .SNS ( io_pads_sns ), + .SR ( 1'b0 ) + ); + (* dont_touch *) + PBIDIR_18_18_NT_DR_H i_uart_rx_in ( + .PO ( ), + .Y ( static_connection_signals_pad2soc.uart_rx_i ), + .PAD ( pad_uart_rx_in_pad ), + .A ( 1'b0 ), + .DS0 ( 1'b0 ), + .DS1 ( 1'b0 ), + .IE ( 1'b1 ), + .IS ( 1'b0 ), + .OE ( 1'b0 ), + .PE ( 1'b0 ), + .POE ( 1'b0 ), + .PS ( 1'b0 ), + .RTO ( io_pads_rto ), + .SNS ( io_pads_sns ), + .SR ( 1'b0 ) + ); + (* dont_touch *) + PBIDIR_18_18_NT_DR_V i_muxed_v_00 ( + .PO ( ), + .Y ( pads_to_mux_o.muxed_v_00.pad2chip ), + .PAD ( pad_muxed_v_00_pad ), + .A ( mux_to_pads_i.muxed_v_00.chip2pad ), + .DS0 ( 1'b0 ), + .DS1 ( 1'b0 ), + .IE ( mux_to_pads_i.muxed_v_00.input_en ), + .IS ( 1'b0 ), + .OE ( mux_to_pads_i.muxed_v_00.output_en ), + .PE ( mux_to_pads_i.muxed_v_00.pull_en ), + .POE ( 1'b0 ), + .PS ( mux_to_pads_i.muxed_v_00.pull_sel ), + .RTO ( io_pads_rto ), + .SNS ( io_pads_sns ), + .SR ( 1'b0 ) + ); + (* dont_touch *) + PBIDIR_18_18_NT_DR_V i_muxed_v_01 ( + .PO ( ), + .Y ( pads_to_mux_o.muxed_v_01.pad2chip ), + .PAD ( pad_muxed_v_01_pad ), + .A ( mux_to_pads_i.muxed_v_01.chip2pad ), + .DS0 ( 1'b0 ), + .DS1 ( 1'b0 ), + .IE ( mux_to_pads_i.muxed_v_01.input_en ), + .IS ( 1'b0 ), + .OE ( mux_to_pads_i.muxed_v_01.output_en ), + .PE ( mux_to_pads_i.muxed_v_01.pull_en ), + .POE ( 1'b0 ), + .PS ( mux_to_pads_i.muxed_v_01.pull_sel ), + .RTO ( io_pads_rto ), + .SNS ( io_pads_sns ), + .SR ( 1'b0 ) + ); + (* dont_touch *) + PBIDIR_18_18_NT_DR_V i_muxed_v_02 ( + .PO ( ), + .Y ( pads_to_mux_o.muxed_v_02.pad2chip ), + .PAD ( pad_muxed_v_02_pad ), + .A ( mux_to_pads_i.muxed_v_02.chip2pad ), + .DS0 ( 1'b0 ), + .DS1 ( 1'b0 ), + .IE ( mux_to_pads_i.muxed_v_02.input_en ), + .IS ( 1'b0 ), + .OE ( mux_to_pads_i.muxed_v_02.output_en ), + .PE ( mux_to_pads_i.muxed_v_02.pull_en ), + .POE ( 1'b0 ), + .PS ( mux_to_pads_i.muxed_v_02.pull_sel ), + .RTO ( io_pads_rto ), + .SNS ( io_pads_sns ), + .SR ( 1'b0 ) + ); + (* dont_touch *) + PBIDIR_18_18_NT_DR_V i_muxed_v_03 ( + .PO ( ), + .Y ( pads_to_mux_o.muxed_v_03.pad2chip ), + .PAD ( pad_muxed_v_03_pad ), + .A ( mux_to_pads_i.muxed_v_03.chip2pad ), + .DS0 ( 1'b0 ), + .DS1 ( 1'b0 ), + .IE ( mux_to_pads_i.muxed_v_03.input_en ), + .IS ( 1'b0 ), + .OE ( mux_to_pads_i.muxed_v_03.output_en ), + .PE ( mux_to_pads_i.muxed_v_03.pull_en ), + .POE ( 1'b0 ), + .PS ( mux_to_pads_i.muxed_v_03.pull_sel ), + .RTO ( io_pads_rto ), + .SNS ( io_pads_sns ), + .SR ( 1'b0 ) + ); + (* dont_touch *) + PBIDIR_18_18_NT_DR_V i_muxed_v_04 ( + .PO ( ), + .Y ( pads_to_mux_o.muxed_v_04.pad2chip ), + .PAD ( pad_muxed_v_04_pad ), + .A ( mux_to_pads_i.muxed_v_04.chip2pad ), + .DS0 ( 1'b0 ), + .DS1 ( 1'b0 ), + .IE ( mux_to_pads_i.muxed_v_04.input_en ), + .IS ( 1'b0 ), + .OE ( mux_to_pads_i.muxed_v_04.output_en ), + .PE ( mux_to_pads_i.muxed_v_04.pull_en ), + .POE ( 1'b0 ), + .PS ( mux_to_pads_i.muxed_v_04.pull_sel ), + .RTO ( io_pads_rto ), + .SNS ( io_pads_sns ), + .SR ( 1'b0 ) + ); + (* dont_touch *) + PBIDIR_18_18_NT_DR_V i_muxed_v_05 ( + .PO ( ), + .Y ( pads_to_mux_o.muxed_v_05.pad2chip ), + .PAD ( pad_muxed_v_05_pad ), + .A ( mux_to_pads_i.muxed_v_05.chip2pad ), + .DS0 ( 1'b0 ), + .DS1 ( 1'b0 ), + .IE ( mux_to_pads_i.muxed_v_05.input_en ), + .IS ( 1'b0 ), + .OE ( mux_to_pads_i.muxed_v_05.output_en ), + .PE ( mux_to_pads_i.muxed_v_05.pull_en ), + .POE ( 1'b0 ), + .PS ( mux_to_pads_i.muxed_v_05.pull_sel ), + .RTO ( io_pads_rto ), + .SNS ( io_pads_sns ), + .SR ( 1'b0 ) + ); + (* dont_touch *) + PBIDIR_18_18_NT_DR_V i_muxed_v_06 ( + .PO ( ), + .Y ( pads_to_mux_o.muxed_v_06.pad2chip ), + .PAD ( pad_muxed_v_06_pad ), + .A ( mux_to_pads_i.muxed_v_06.chip2pad ), + .DS0 ( 1'b0 ), + .DS1 ( 1'b0 ), + .IE ( mux_to_pads_i.muxed_v_06.input_en ), + .IS ( 1'b0 ), + .OE ( mux_to_pads_i.muxed_v_06.output_en ), + .PE ( mux_to_pads_i.muxed_v_06.pull_en ), + .POE ( 1'b0 ), + .PS ( mux_to_pads_i.muxed_v_06.pull_sel ), + .RTO ( io_pads_rto ), + .SNS ( io_pads_sns ), + .SR ( 1'b0 ) + ); + (* dont_touch *) + PBIDIR_18_18_NT_DR_V i_muxed_v_07 ( + .PO ( ), + .Y ( pads_to_mux_o.muxed_v_07.pad2chip ), + .PAD ( pad_muxed_v_07_pad ), + .A ( mux_to_pads_i.muxed_v_07.chip2pad ), + .DS0 ( 1'b0 ), + .DS1 ( 1'b0 ), + .IE ( mux_to_pads_i.muxed_v_07.input_en ), + .IS ( 1'b0 ), + .OE ( mux_to_pads_i.muxed_v_07.output_en ), + .PE ( mux_to_pads_i.muxed_v_07.pull_en ), + .POE ( 1'b0 ), + .PS ( mux_to_pads_i.muxed_v_07.pull_sel ), + .RTO ( io_pads_rto ), + .SNS ( io_pads_sns ), + .SR ( 1'b0 ) + ); + (* dont_touch *) + PBIDIR_18_18_NT_DR_V i_muxed_v_08 ( + .PO ( ), + .Y ( pads_to_mux_o.muxed_v_08.pad2chip ), + .PAD ( pad_muxed_v_08_pad ), + .A ( mux_to_pads_i.muxed_v_08.chip2pad ), + .DS0 ( 1'b0 ), + .DS1 ( 1'b0 ), + .IE ( mux_to_pads_i.muxed_v_08.input_en ), + .IS ( 1'b0 ), + .OE ( mux_to_pads_i.muxed_v_08.output_en ), + .PE ( mux_to_pads_i.muxed_v_08.pull_en ), + .POE ( 1'b0 ), + .PS ( mux_to_pads_i.muxed_v_08.pull_sel ), + .RTO ( io_pads_rto ), + .SNS ( io_pads_sns ), + .SR ( 1'b0 ) + ); + (* dont_touch *) + PBIDIR_18_18_NT_DR_V i_muxed_v_09 ( + .PO ( ), + .Y ( pads_to_mux_o.muxed_v_09.pad2chip ), + .PAD ( pad_muxed_v_09_pad ), + .A ( mux_to_pads_i.muxed_v_09.chip2pad ), + .DS0 ( 1'b0 ), + .DS1 ( 1'b0 ), + .IE ( mux_to_pads_i.muxed_v_09.input_en ), + .IS ( 1'b0 ), + .OE ( mux_to_pads_i.muxed_v_09.output_en ), + .PE ( mux_to_pads_i.muxed_v_09.pull_en ), + .POE ( 1'b0 ), + .PS ( mux_to_pads_i.muxed_v_09.pull_sel ), + .RTO ( io_pads_rto ), + .SNS ( io_pads_sns ), + .SR ( 1'b0 ) + ); + (* dont_touch *) + PBIDIR_18_18_NT_DR_V i_muxed_v_10 ( + .PO ( ), + .Y ( pads_to_mux_o.muxed_v_10.pad2chip ), + .PAD ( pad_muxed_v_10_pad ), + .A ( mux_to_pads_i.muxed_v_10.chip2pad ), + .DS0 ( 1'b0 ), + .DS1 ( 1'b0 ), + .IE ( mux_to_pads_i.muxed_v_10.input_en ), + .IS ( 1'b0 ), + .OE ( mux_to_pads_i.muxed_v_10.output_en ), + .PE ( mux_to_pads_i.muxed_v_10.pull_en ), + .POE ( 1'b0 ), + .PS ( mux_to_pads_i.muxed_v_10.pull_sel ), + .RTO ( io_pads_rto ), + .SNS ( io_pads_sns ), + .SR ( 1'b0 ) + ); + (* dont_touch *) + PBIDIR_18_18_NT_DR_V i_muxed_v_11 ( + .PO ( ), + .Y ( pads_to_mux_o.muxed_v_11.pad2chip ), + .PAD ( pad_muxed_v_11_pad ), + .A ( mux_to_pads_i.muxed_v_11.chip2pad ), + .DS0 ( 1'b0 ), + .DS1 ( 1'b0 ), + .IE ( mux_to_pads_i.muxed_v_11.input_en ), + .IS ( 1'b0 ), + .OE ( mux_to_pads_i.muxed_v_11.output_en ), + .PE ( mux_to_pads_i.muxed_v_11.pull_en ), + .POE ( 1'b0 ), + .PS ( mux_to_pads_i.muxed_v_11.pull_sel ), + .RTO ( io_pads_rto ), + .SNS ( io_pads_sns ), + .SR ( 1'b0 ) + ); + (* dont_touch *) + PBIDIR_18_18_NT_DR_V i_muxed_v_12 ( + .PO ( ), + .Y ( pads_to_mux_o.muxed_v_12.pad2chip ), + .PAD ( pad_muxed_v_12_pad ), + .A ( mux_to_pads_i.muxed_v_12.chip2pad ), + .DS0 ( 1'b0 ), + .DS1 ( 1'b0 ), + .IE ( mux_to_pads_i.muxed_v_12.input_en ), + .IS ( 1'b0 ), + .OE ( mux_to_pads_i.muxed_v_12.output_en ), + .PE ( mux_to_pads_i.muxed_v_12.pull_en ), + .POE ( 1'b0 ), + .PS ( mux_to_pads_i.muxed_v_12.pull_sel ), + .RTO ( io_pads_rto ), + .SNS ( io_pads_sns ), + .SR ( 1'b0 ) + ); + (* dont_touch *) + PBIDIR_18_18_NT_DR_V i_muxed_v_13 ( + .PO ( ), + .Y ( pads_to_mux_o.muxed_v_13.pad2chip ), + .PAD ( pad_muxed_v_13_pad ), + .A ( mux_to_pads_i.muxed_v_13.chip2pad ), + .DS0 ( 1'b0 ), + .DS1 ( 1'b0 ), + .IE ( mux_to_pads_i.muxed_v_13.input_en ), + .IS ( 1'b0 ), + .OE ( mux_to_pads_i.muxed_v_13.output_en ), + .PE ( mux_to_pads_i.muxed_v_13.pull_en ), + .POE ( 1'b0 ), + .PS ( mux_to_pads_i.muxed_v_13.pull_sel ), + .RTO ( io_pads_rto ), + .SNS ( io_pads_sns ), + .SR ( 1'b0 ) + ); + (* dont_touch *) + PBIDIR_18_18_NT_DR_V i_muxed_v_14 ( + .PO ( ), + .Y ( pads_to_mux_o.muxed_v_14.pad2chip ), + .PAD ( pad_muxed_v_14_pad ), + .A ( mux_to_pads_i.muxed_v_14.chip2pad ), + .DS0 ( 1'b0 ), + .DS1 ( 1'b0 ), + .IE ( mux_to_pads_i.muxed_v_14.input_en ), + .IS ( 1'b0 ), + .OE ( mux_to_pads_i.muxed_v_14.output_en ), + .PE ( mux_to_pads_i.muxed_v_14.pull_en ), + .POE ( 1'b0 ), + .PS ( mux_to_pads_i.muxed_v_14.pull_sel ), + .RTO ( io_pads_rto ), + .SNS ( io_pads_sns ), + .SR ( 1'b0 ) + ); + (* dont_touch *) + PBIDIR_18_18_NT_DR_V i_muxed_v_15 ( + .PO ( ), + .Y ( pads_to_mux_o.muxed_v_15.pad2chip ), + .PAD ( pad_muxed_v_15_pad ), + .A ( mux_to_pads_i.muxed_v_15.chip2pad ), + .DS0 ( 1'b0 ), + .DS1 ( 1'b0 ), + .IE ( mux_to_pads_i.muxed_v_15.input_en ), + .IS ( 1'b0 ), + .OE ( mux_to_pads_i.muxed_v_15.output_en ), + .PE ( mux_to_pads_i.muxed_v_15.pull_en ), + .POE ( 1'b0 ), + .PS ( mux_to_pads_i.muxed_v_15.pull_sel ), + .RTO ( io_pads_rto ), + .SNS ( io_pads_sns ), + .SR ( 1'b0 ) + ); + (* dont_touch *) + PBIDIR_18_18_NT_DR_V i_muxed_v_16 ( + .PO ( ), + .Y ( pads_to_mux_o.muxed_v_16.pad2chip ), + .PAD ( pad_muxed_v_16_pad ), + .A ( mux_to_pads_i.muxed_v_16.chip2pad ), + .DS0 ( 1'b0 ), + .DS1 ( 1'b0 ), + .IE ( mux_to_pads_i.muxed_v_16.input_en ), + .IS ( 1'b0 ), + .OE ( mux_to_pads_i.muxed_v_16.output_en ), + .PE ( mux_to_pads_i.muxed_v_16.pull_en ), + .POE ( 1'b0 ), + .PS ( mux_to_pads_i.muxed_v_16.pull_sel ), + .RTO ( io_pads_rto ), + .SNS ( io_pads_sns ), + .SR ( 1'b0 ) + ); + (* dont_touch *) + PBIDIR_18_18_NT_DR_V i_muxed_v_17 ( + .PO ( ), + .Y ( pads_to_mux_o.muxed_v_17.pad2chip ), + .PAD ( pad_muxed_v_17_pad ), + .A ( mux_to_pads_i.muxed_v_17.chip2pad ), + .DS0 ( 1'b0 ), + .DS1 ( 1'b0 ), + .IE ( mux_to_pads_i.muxed_v_17.input_en ), + .IS ( 1'b0 ), + .OE ( mux_to_pads_i.muxed_v_17.output_en ), + .PE ( mux_to_pads_i.muxed_v_17.pull_en ), + .POE ( 1'b0 ), + .PS ( mux_to_pads_i.muxed_v_17.pull_sel ), + .RTO ( io_pads_rto ), + .SNS ( io_pads_sns ), + .SR ( 1'b0 ) + ); + (* dont_touch *) + PBIDIR_18_18_NT_DR_H i_muxed_h_00 ( + .PO ( ), + .Y ( pads_to_mux_o.muxed_h_00.pad2chip ), + .PAD ( pad_muxed_h_00_pad ), + .A ( mux_to_pads_i.muxed_h_00.chip2pad ), + .DS0 ( 1'b0 ), + .DS1 ( 1'b0 ), + .IE ( mux_to_pads_i.muxed_h_00.input_en ), + .IS ( 1'b0 ), + .OE ( mux_to_pads_i.muxed_h_00.output_en ), + .PE ( mux_to_pads_i.muxed_h_00.pull_en ), + .POE ( 1'b0 ), + .PS ( mux_to_pads_i.muxed_h_00.pull_sel ), + .RTO ( io_pads_rto ), + .SNS ( io_pads_sns ), + .SR ( 1'b0 ) + ); + (* dont_touch *) + PBIDIR_18_18_NT_DR_H i_muxed_h_01 ( + .PO ( ), + .Y ( pads_to_mux_o.muxed_h_01.pad2chip ), + .PAD ( pad_muxed_h_01_pad ), + .A ( mux_to_pads_i.muxed_h_01.chip2pad ), + .DS0 ( 1'b0 ), + .DS1 ( 1'b0 ), + .IE ( mux_to_pads_i.muxed_h_01.input_en ), + .IS ( 1'b0 ), + .OE ( mux_to_pads_i.muxed_h_01.output_en ), + .PE ( mux_to_pads_i.muxed_h_01.pull_en ), + .POE ( 1'b0 ), + .PS ( mux_to_pads_i.muxed_h_01.pull_sel ), + .RTO ( io_pads_rto ), + .SNS ( io_pads_sns ), + .SR ( 1'b0 ) + ); + (* dont_touch *) + PBIDIR_18_18_NT_DR_H i_muxed_h_02 ( + .PO ( ), + .Y ( pads_to_mux_o.muxed_h_02.pad2chip ), + .PAD ( pad_muxed_h_02_pad ), + .A ( mux_to_pads_i.muxed_h_02.chip2pad ), + .DS0 ( 1'b0 ), + .DS1 ( 1'b0 ), + .IE ( mux_to_pads_i.muxed_h_02.input_en ), + .IS ( 1'b0 ), + .OE ( mux_to_pads_i.muxed_h_02.output_en ), + .PE ( mux_to_pads_i.muxed_h_02.pull_en ), + .POE ( 1'b0 ), + .PS ( mux_to_pads_i.muxed_h_02.pull_sel ), + .RTO ( io_pads_rto ), + .SNS ( io_pads_sns ), + .SR ( 1'b0 ) + ); + (* dont_touch *) + PBIDIR_18_18_NT_DR_H i_muxed_h_03 ( + .PO ( ), + .Y ( pads_to_mux_o.muxed_h_03.pad2chip ), + .PAD ( pad_muxed_h_03_pad ), + .A ( mux_to_pads_i.muxed_h_03.chip2pad ), + .DS0 ( 1'b0 ), + .DS1 ( 1'b0 ), + .IE ( mux_to_pads_i.muxed_h_03.input_en ), + .IS ( 1'b0 ), + .OE ( mux_to_pads_i.muxed_h_03.output_en ), + .PE ( mux_to_pads_i.muxed_h_03.pull_en ), + .POE ( 1'b0 ), + .PS ( mux_to_pads_i.muxed_h_03.pull_sel ), + .RTO ( io_pads_rto ), + .SNS ( io_pads_sns ), + .SR ( 1'b0 ) + ); + +endmodule : astral_padframe_periph_pads diff --git a/hw/padframe/astral_padframe/src/astral_padframe_periph_regs.hjson b/hw/padframe/astral_padframe/src/astral_padframe_periph_regs.hjson new file mode 100644 index 00000000..440266c3 --- /dev/null +++ b/hw/padframe/astral_padframe/src/astral_padframe_periph_regs.hjson @@ -0,0 +1,1950 @@ + + +{ + # File auto-generated by Padrick unknown + name: "astral_padframe_periph_config" + clock_primary: "clk_i" + reset_primary: "rst_ni" + bus_interfaces: [ + { protocol: "reg_iface", direction: "device"} + ] + regwidth: 32, + registers: [ + {skipto: "0x0"}, + { + name: INFO + desc: "Read-only IP Information register" + swaccess: "ro" + hwaccess: "hro" + fields: [ + { + bits: "15:0" + name: HW_VERSION + desc: "Hardware version ID." + resval: 2 + }, + { + bits:"31:16" + name: PADCOUNT + desc: "The number of muxable pads in this IP." + resval: "22" + } + ] + } + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + { + name: MUXED_V_00_CFG + desc: ''' + Pad signal configuration. + ''' + swaccess: "rw" + fields: [ + { + bits: "0" + name: chip2pad + desc: ''' + Data input pin from chip to padframe + ''' + swaccess: "rw" + hwaccess: "hro" + resval: "0" + }, + { + bits: "1" + name: input_en + desc: ''' + Input enable signal, active high + ''' + swaccess: "rw" + hwaccess: "hro" + resval: "0" + }, + { + bits: "2" + name: output_en + desc: ''' + Output enable signal, active high + ''' + swaccess: "rw" + hwaccess: "hro" + resval: "0" + }, + { + bits: "3" + name: pull_en + desc: ''' + Pull-up/-down enable signal, active high + ''' + swaccess: "rw" + hwaccess: "hro" + resval: "0" + }, + { + bits: "4" + name: pull_sel + desc: ''' + Pull-up/-down select signal, high: pull-up, low: pull-down + ''' + swaccess: "rw" + hwaccess: "hro" + resval: "0" + }, + ] + } + + { + name: MUXED_V_00_MUX_SEL + desc: ''' + Pad signal port multiplex selection for pad muxed_v_00. The programmed value defines which port + is connected to the pad. + ''' + swaccess: "rw" + hwaccess: "hro" + resval: 1 + fields: [ + { + bits: "2:0" + enum: [ + { value: "0", name: "register", desc: "Connects the Pad to the internal configuration register."} + { value: "1", name: "port_can_rx", desc: "Connect port rx from port group can to this pad." } + { value: "2", name: "port_gpio_io_v_0", desc: "Connect port io_v_0 from port group gpio to this pad." } + { value: "3", name: "port_i2c_sda", desc: "Connect port sda from port group i2c to this pad." } + { value: "4", name: "port_spi_sck", desc: "Connect port sck from port group spi to this pad." } + { value: "5", name: "port_spi_ot_sck", desc: "Connect port sck from port group spi_ot to this pad." } + ] + } + ] + } + + { + name: MUXED_V_01_CFG + desc: ''' + Pad signal configuration. + ''' + swaccess: "rw" + fields: [ + { + bits: "0" + name: chip2pad + desc: ''' + Data input pin from chip to padframe + ''' + swaccess: "rw" + hwaccess: "hro" + resval: "0" + }, + { + bits: "1" + name: input_en + desc: ''' + Input enable signal, active high + ''' + swaccess: "rw" + hwaccess: "hro" + resval: "0" + }, + { + bits: "2" + name: output_en + desc: ''' + Output enable signal, active high + ''' + swaccess: "rw" + hwaccess: "hro" + resval: "0" + }, + { + bits: "3" + name: pull_en + desc: ''' + Pull-up/-down enable signal, active high + ''' + swaccess: "rw" + hwaccess: "hro" + resval: "0" + }, + { + bits: "4" + name: pull_sel + desc: ''' + Pull-up/-down select signal, high: pull-up, low: pull-down + ''' + swaccess: "rw" + hwaccess: "hro" + resval: "0" + }, + ] + } + + { + name: MUXED_V_01_MUX_SEL + desc: ''' + Pad signal port multiplex selection for pad muxed_v_01. The programmed value defines which port + is connected to the pad. + ''' + swaccess: "rw" + hwaccess: "hro" + resval: 1 + fields: [ + { + bits: "2:0" + enum: [ + { value: "0", name: "register", desc: "Connects the Pad to the internal configuration register."} + { value: "1", name: "port_can_tx", desc: "Connect port tx from port group can to this pad." } + { value: "2", name: "port_gpio_io_v_1", desc: "Connect port io_v_1 from port group gpio to this pad." } + { value: "3", name: "port_i2c_scl", desc: "Connect port scl from port group i2c to this pad." } + { value: "4", name: "port_spi_csb_0", desc: "Connect port csb_0 from port group spi to this pad." } + { value: "5", name: "port_spi_ot_csb", desc: "Connect port csb from port group spi_ot to this pad." } + ] + } + ] + } + + { + name: MUXED_V_02_CFG + desc: ''' + Pad signal configuration. + ''' + swaccess: "rw" + fields: [ + { + bits: "0" + name: chip2pad + desc: ''' + Data input pin from chip to padframe + ''' + swaccess: "rw" + hwaccess: "hro" + resval: "0" + }, + { + bits: "1" + name: input_en + desc: ''' + Input enable signal, active high + ''' + swaccess: "rw" + hwaccess: "hro" + resval: "0" + }, + { + bits: "2" + name: output_en + desc: ''' + Output enable signal, active high + ''' + swaccess: "rw" + hwaccess: "hro" + resval: "0" + }, + { + bits: "3" + name: pull_en + desc: ''' + Pull-up/-down enable signal, active high + ''' + swaccess: "rw" + hwaccess: "hro" + resval: "0" + }, + { + bits: "4" + name: pull_sel + desc: ''' + Pull-up/-down select signal, high: pull-up, low: pull-down + ''' + swaccess: "rw" + hwaccess: "hro" + resval: "0" + }, + ] + } + + { + name: MUXED_V_02_MUX_SEL + desc: ''' + Pad signal port multiplex selection for pad muxed_v_02. The programmed value defines which port + is connected to the pad. + ''' + swaccess: "rw" + hwaccess: "hro" + resval: 1 + fields: [ + { + bits: "1:0" + enum: [ + { value: "0", name: "register", desc: "Connects the Pad to the internal configuration register."} + { value: "1", name: "port_gpio_io_v_2", desc: "Connect port io_v_2 from port group gpio to this pad." } + { value: "2", name: "port_spi_csb_1", desc: "Connect port csb_1 from port group spi to this pad." } + { value: "3", name: "port_spi_ot_sd_0", desc: "Connect port sd_0 from port group spi_ot to this pad." } + ] + } + ] + } + + { + name: MUXED_V_03_CFG + desc: ''' + Pad signal configuration. + ''' + swaccess: "rw" + fields: [ + { + bits: "0" + name: chip2pad + desc: ''' + Data input pin from chip to padframe + ''' + swaccess: "rw" + hwaccess: "hro" + resval: "0" + }, + { + bits: "1" + name: input_en + desc: ''' + Input enable signal, active high + ''' + swaccess: "rw" + hwaccess: "hro" + resval: "0" + }, + { + bits: "2" + name: output_en + desc: ''' + Output enable signal, active high + ''' + swaccess: "rw" + hwaccess: "hro" + resval: "0" + }, + { + bits: "3" + name: pull_en + desc: ''' + Pull-up/-down enable signal, active high + ''' + swaccess: "rw" + hwaccess: "hro" + resval: "0" + }, + { + bits: "4" + name: pull_sel + desc: ''' + Pull-up/-down select signal, high: pull-up, low: pull-down + ''' + swaccess: "rw" + hwaccess: "hro" + resval: "0" + }, + ] + } + + { + name: MUXED_V_03_MUX_SEL + desc: ''' + Pad signal port multiplex selection for pad muxed_v_03. The programmed value defines which port + is connected to the pad. + ''' + swaccess: "rw" + hwaccess: "hro" + resval: 1 + fields: [ + { + bits: "1:0" + enum: [ + { value: "0", name: "register", desc: "Connects the Pad to the internal configuration register."} + { value: "1", name: "port_gpio_io_v_3", desc: "Connect port io_v_3 from port group gpio to this pad." } + { value: "2", name: "port_spi_sd_0", desc: "Connect port sd_0 from port group spi to this pad." } + { value: "3", name: "port_spi_ot_sd_1", desc: "Connect port sd_1 from port group spi_ot to this pad." } + ] + } + ] + } + + { + name: MUXED_V_04_CFG + desc: ''' + Pad signal configuration. + ''' + swaccess: "rw" + fields: [ + { + bits: "0" + name: chip2pad + desc: ''' + Data input pin from chip to padframe + ''' + swaccess: "rw" + hwaccess: "hro" + resval: "0" + }, + { + bits: "1" + name: input_en + desc: ''' + Input enable signal, active high + ''' + swaccess: "rw" + hwaccess: "hro" + resval: "0" + }, + { + bits: "2" + name: output_en + desc: ''' + Output enable signal, active high + ''' + swaccess: "rw" + hwaccess: "hro" + resval: "0" + }, + { + bits: "3" + name: pull_en + desc: ''' + Pull-up/-down enable signal, active high + ''' + swaccess: "rw" + hwaccess: "hro" + resval: "0" + }, + { + bits: "4" + name: pull_sel + desc: ''' + Pull-up/-down select signal, high: pull-up, low: pull-down + ''' + swaccess: "rw" + hwaccess: "hro" + resval: "0" + }, + ] + } + + { + name: MUXED_V_04_MUX_SEL + desc: ''' + Pad signal port multiplex selection for pad muxed_v_04. The programmed value defines which port + is connected to the pad. + ''' + swaccess: "rw" + hwaccess: "hro" + resval: 2 + fields: [ + { + bits: "2:0" + enum: [ + { value: "0", name: "register", desc: "Connects the Pad to the internal configuration register."} + { value: "1", name: "port_gpio_io_v_4", desc: "Connect port io_v_4 from port group gpio to this pad." } + { value: "2", name: "port_serial_link_rcv_clk_i", desc: "Connect port rcv_clk_i from port group serial_link to this pad." } + { value: "3", name: "port_spi_sd_1", desc: "Connect port sd_1 from port group spi to this pad." } + { value: "4", name: "port_spi_ot_sd_2", desc: "Connect port sd_2 from port group spi_ot to this pad." } + ] + } + ] + } + + { + name: MUXED_V_05_CFG + desc: ''' + Pad signal configuration. + ''' + swaccess: "rw" + fields: [ + { + bits: "0" + name: chip2pad + desc: ''' + Data input pin from chip to padframe + ''' + swaccess: "rw" + hwaccess: "hro" + resval: "0" + }, + { + bits: "1" + name: input_en + desc: ''' + Input enable signal, active high + ''' + swaccess: "rw" + hwaccess: "hro" + resval: "0" + }, + { + bits: "2" + name: output_en + desc: ''' + Output enable signal, active high + ''' + swaccess: "rw" + hwaccess: "hro" + resval: "0" + }, + { + bits: "3" + name: pull_en + desc: ''' + Pull-up/-down enable signal, active high + ''' + swaccess: "rw" + hwaccess: "hro" + resval: "0" + }, + { + bits: "4" + name: pull_sel + desc: ''' + Pull-up/-down select signal, high: pull-up, low: pull-down + ''' + swaccess: "rw" + hwaccess: "hro" + resval: "0" + }, + ] + } + + { + name: MUXED_V_05_MUX_SEL + desc: ''' + Pad signal port multiplex selection for pad muxed_v_05. The programmed value defines which port + is connected to the pad. + ''' + swaccess: "rw" + hwaccess: "hro" + resval: 2 + fields: [ + { + bits: "2:0" + enum: [ + { value: "0", name: "register", desc: "Connects the Pad to the internal configuration register."} + { value: "1", name: "port_gpio_io_v_5", desc: "Connect port io_v_5 from port group gpio to this pad." } + { value: "2", name: "port_serial_link_i_0", desc: "Connect port i_0 from port group serial_link to this pad." } + { value: "3", name: "port_spi_sd_2", desc: "Connect port sd_2 from port group spi to this pad." } + { value: "4", name: "port_spi_ot_sd_3", desc: "Connect port sd_3 from port group spi_ot to this pad." } + ] + } + ] + } + + { + name: MUXED_V_06_CFG + desc: ''' + Pad signal configuration. + ''' + swaccess: "rw" + fields: [ + { + bits: "0" + name: chip2pad + desc: ''' + Data input pin from chip to padframe + ''' + swaccess: "rw" + hwaccess: "hro" + resval: "0" + }, + { + bits: "1" + name: input_en + desc: ''' + Input enable signal, active high + ''' + swaccess: "rw" + hwaccess: "hro" + resval: "0" + }, + { + bits: "2" + name: output_en + desc: ''' + Output enable signal, active high + ''' + swaccess: "rw" + hwaccess: "hro" + resval: "0" + }, + { + bits: "3" + name: pull_en + desc: ''' + Pull-up/-down enable signal, active high + ''' + swaccess: "rw" + hwaccess: "hro" + resval: "0" + }, + { + bits: "4" + name: pull_sel + desc: ''' + Pull-up/-down select signal, high: pull-up, low: pull-down + ''' + swaccess: "rw" + hwaccess: "hro" + resval: "0" + }, + ] + } + + { + name: MUXED_V_06_MUX_SEL + desc: ''' + Pad signal port multiplex selection for pad muxed_v_06. The programmed value defines which port + is connected to the pad. + ''' + swaccess: "rw" + hwaccess: "hro" + resval: 2 + fields: [ + { + bits: "1:0" + enum: [ + { value: "0", name: "register", desc: "Connects the Pad to the internal configuration register."} + { value: "1", name: "port_gpio_io_v_6", desc: "Connect port io_v_6 from port group gpio to this pad." } + { value: "2", name: "port_serial_link_i_1", desc: "Connect port i_1 from port group serial_link to this pad." } + { value: "3", name: "port_spi_sd_3", desc: "Connect port sd_3 from port group spi to this pad." } + ] + } + ] + } + + { + name: MUXED_V_07_CFG + desc: ''' + Pad signal configuration. + ''' + swaccess: "rw" + fields: [ + { + bits: "0" + name: chip2pad + desc: ''' + Data input pin from chip to padframe + ''' + swaccess: "rw" + hwaccess: "hro" + resval: "0" + }, + { + bits: "1" + name: input_en + desc: ''' + Input enable signal, active high + ''' + swaccess: "rw" + hwaccess: "hro" + resval: "0" + }, + { + bits: "2" + name: output_en + desc: ''' + Output enable signal, active high + ''' + swaccess: "rw" + hwaccess: "hro" + resval: "0" + }, + { + bits: "3" + name: pull_en + desc: ''' + Pull-up/-down enable signal, active high + ''' + swaccess: "rw" + hwaccess: "hro" + resval: "0" + }, + { + bits: "4" + name: pull_sel + desc: ''' + Pull-up/-down select signal, high: pull-up, low: pull-down + ''' + swaccess: "rw" + hwaccess: "hro" + resval: "0" + }, + ] + } + + { + name: MUXED_V_07_MUX_SEL + desc: ''' + Pad signal port multiplex selection for pad muxed_v_07. The programmed value defines which port + is connected to the pad. + ''' + swaccess: "rw" + hwaccess: "hro" + resval: 4 + fields: [ + { + bits: "2:0" + enum: [ + { value: "0", name: "register", desc: "Connects the Pad to the internal configuration register."} + { value: "1", name: "port_ethernet_rxck", desc: "Connect port rxck from port group ethernet to this pad." } + { value: "2", name: "port_gpio_io_v_7", desc: "Connect port io_v_7 from port group gpio to this pad." } + { value: "3", name: "port_pll_io_0", desc: "Connect port io_0 from port group pll to this pad." } + { value: "4", name: "port_serial_link_i_2", desc: "Connect port i_2 from port group serial_link to this pad." } + { value: "5", name: "port_tc_active", desc: "Connect port active from port group tc to this pad." } + ] + } + ] + } + + { + name: MUXED_V_08_CFG + desc: ''' + Pad signal configuration. + ''' + swaccess: "rw" + fields: [ + { + bits: "0" + name: chip2pad + desc: ''' + Data input pin from chip to padframe + ''' + swaccess: "rw" + hwaccess: "hro" + resval: "0" + }, + { + bits: "1" + name: input_en + desc: ''' + Input enable signal, active high + ''' + swaccess: "rw" + hwaccess: "hro" + resval: "0" + }, + { + bits: "2" + name: output_en + desc: ''' + Output enable signal, active high + ''' + swaccess: "rw" + hwaccess: "hro" + resval: "0" + }, + { + bits: "3" + name: pull_en + desc: ''' + Pull-up/-down enable signal, active high + ''' + swaccess: "rw" + hwaccess: "hro" + resval: "0" + }, + { + bits: "4" + name: pull_sel + desc: ''' + Pull-up/-down select signal, high: pull-up, low: pull-down + ''' + swaccess: "rw" + hwaccess: "hro" + resval: "0" + }, + ] + } + + { + name: MUXED_V_08_MUX_SEL + desc: ''' + Pad signal port multiplex selection for pad muxed_v_08. The programmed value defines which port + is connected to the pad. + ''' + swaccess: "rw" + hwaccess: "hro" + resval: 4 + fields: [ + { + bits: "2:0" + enum: [ + { value: "0", name: "register", desc: "Connects the Pad to the internal configuration register."} + { value: "1", name: "port_ethernet_rxctl", desc: "Connect port rxctl from port group ethernet to this pad." } + { value: "2", name: "port_gpio_io_v_8", desc: "Connect port io_v_8 from port group gpio to this pad." } + { value: "3", name: "port_pll_io_1", desc: "Connect port io_1 from port group pll to this pad." } + { value: "4", name: "port_serial_link_i_3", desc: "Connect port i_3 from port group serial_link to this pad." } + { value: "5", name: "port_tc_clk", desc: "Connect port clk from port group tc to this pad." } + ] + } + ] + } + + { + name: MUXED_V_09_CFG + desc: ''' + Pad signal configuration. + ''' + swaccess: "rw" + fields: [ + { + bits: "0" + name: chip2pad + desc: ''' + Data input pin from chip to padframe + ''' + swaccess: "rw" + hwaccess: "hro" + resval: "0" + }, + { + bits: "1" + name: input_en + desc: ''' + Input enable signal, active high + ''' + swaccess: "rw" + hwaccess: "hro" + resval: "0" + }, + { + bits: "2" + name: output_en + desc: ''' + Output enable signal, active high + ''' + swaccess: "rw" + hwaccess: "hro" + resval: "0" + }, + { + bits: "3" + name: pull_en + desc: ''' + Pull-up/-down enable signal, active high + ''' + swaccess: "rw" + hwaccess: "hro" + resval: "0" + }, + { + bits: "4" + name: pull_sel + desc: ''' + Pull-up/-down select signal, high: pull-up, low: pull-down + ''' + swaccess: "rw" + hwaccess: "hro" + resval: "0" + }, + ] + } + + { + name: MUXED_V_09_MUX_SEL + desc: ''' + Pad signal port multiplex selection for pad muxed_v_09. The programmed value defines which port + is connected to the pad. + ''' + swaccess: "rw" + hwaccess: "hro" + resval: 4 + fields: [ + { + bits: "2:0" + enum: [ + { value: "0", name: "register", desc: "Connects the Pad to the internal configuration register."} + { value: "1", name: "port_ethernet_rxd_0", desc: "Connect port rxd_0 from port group ethernet to this pad." } + { value: "2", name: "port_gpio_io_v_9", desc: "Connect port io_v_9 from port group gpio to this pad." } + { value: "3", name: "port_pll_io_2", desc: "Connect port io_2 from port group pll to this pad." } + { value: "4", name: "port_serial_link_i_4", desc: "Connect port i_4 from port group serial_link to this pad." } + { value: "5", name: "port_tc_data", desc: "Connect port data from port group tc to this pad." } + ] + } + ] + } + + { + name: MUXED_V_10_CFG + desc: ''' + Pad signal configuration. + ''' + swaccess: "rw" + fields: [ + { + bits: "0" + name: chip2pad + desc: ''' + Data input pin from chip to padframe + ''' + swaccess: "rw" + hwaccess: "hro" + resval: "0" + }, + { + bits: "1" + name: input_en + desc: ''' + Input enable signal, active high + ''' + swaccess: "rw" + hwaccess: "hro" + resval: "0" + }, + { + bits: "2" + name: output_en + desc: ''' + Output enable signal, active high + ''' + swaccess: "rw" + hwaccess: "hro" + resval: "0" + }, + { + bits: "3" + name: pull_en + desc: ''' + Pull-up/-down enable signal, active high + ''' + swaccess: "rw" + hwaccess: "hro" + resval: "0" + }, + { + bits: "4" + name: pull_sel + desc: ''' + Pull-up/-down select signal, high: pull-up, low: pull-down + ''' + swaccess: "rw" + hwaccess: "hro" + resval: "0" + }, + ] + } + + { + name: MUXED_V_10_MUX_SEL + desc: ''' + Pad signal port multiplex selection for pad muxed_v_10. The programmed value defines which port + is connected to the pad. + ''' + swaccess: "rw" + hwaccess: "hro" + resval: 5 + fields: [ + { + bits: "2:0" + enum: [ + { value: "0", name: "register", desc: "Connects the Pad to the internal configuration register."} + { value: "1", name: "port_ethernet_rxd_1", desc: "Connect port rxd_1 from port group ethernet to this pad." } + { value: "2", name: "port_gpio_io_v_10", desc: "Connect port io_v_10 from port group gpio to this pad." } + { value: "3", name: "port_pll_io_3", desc: "Connect port io_3 from port group pll to this pad." } + { value: "4", name: "port_ptme_clk", desc: "Connect port clk from port group ptme to this pad." } + { value: "5", name: "port_serial_link_i_5", desc: "Connect port i_5 from port group serial_link to this pad." } + ] + } + ] + } + + { + name: MUXED_V_11_CFG + desc: ''' + Pad signal configuration. + ''' + swaccess: "rw" + fields: [ + { + bits: "0" + name: chip2pad + desc: ''' + Data input pin from chip to padframe + ''' + swaccess: "rw" + hwaccess: "hro" + resval: "0" + }, + { + bits: "1" + name: input_en + desc: ''' + Input enable signal, active high + ''' + swaccess: "rw" + hwaccess: "hro" + resval: "0" + }, + { + bits: "2" + name: output_en + desc: ''' + Output enable signal, active high + ''' + swaccess: "rw" + hwaccess: "hro" + resval: "0" + }, + { + bits: "3" + name: pull_en + desc: ''' + Pull-up/-down enable signal, active high + ''' + swaccess: "rw" + hwaccess: "hro" + resval: "0" + }, + { + bits: "4" + name: pull_sel + desc: ''' + Pull-up/-down select signal, high: pull-up, low: pull-down + ''' + swaccess: "rw" + hwaccess: "hro" + resval: "0" + }, + ] + } + + { + name: MUXED_V_11_MUX_SEL + desc: ''' + Pad signal port multiplex selection for pad muxed_v_11. The programmed value defines which port + is connected to the pad. + ''' + swaccess: "rw" + hwaccess: "hro" + resval: 5 + fields: [ + { + bits: "2:0" + enum: [ + { value: "0", name: "register", desc: "Connects the Pad to the internal configuration register."} + { value: "1", name: "port_ethernet_rxd_2", desc: "Connect port rxd_2 from port group ethernet to this pad." } + { value: "2", name: "port_gpio_io_v_11", desc: "Connect port io_v_11 from port group gpio to this pad." } + { value: "3", name: "port_pll_io_4", desc: "Connect port io_4 from port group pll to this pad." } + { value: "4", name: "port_ptme_enc", desc: "Connect port enc from port group ptme to this pad." } + { value: "5", name: "port_serial_link_i_6", desc: "Connect port i_6 from port group serial_link to this pad." } + ] + } + ] + } + + { + name: MUXED_V_12_CFG + desc: ''' + Pad signal configuration. + ''' + swaccess: "rw" + fields: [ + { + bits: "0" + name: chip2pad + desc: ''' + Data input pin from chip to padframe + ''' + swaccess: "rw" + hwaccess: "hro" + resval: "0" + }, + { + bits: "1" + name: input_en + desc: ''' + Input enable signal, active high + ''' + swaccess: "rw" + hwaccess: "hro" + resval: "0" + }, + { + bits: "2" + name: output_en + desc: ''' + Output enable signal, active high + ''' + swaccess: "rw" + hwaccess: "hro" + resval: "0" + }, + { + bits: "3" + name: pull_en + desc: ''' + Pull-up/-down enable signal, active high + ''' + swaccess: "rw" + hwaccess: "hro" + resval: "0" + }, + { + bits: "4" + name: pull_sel + desc: ''' + Pull-up/-down select signal, high: pull-up, low: pull-down + ''' + swaccess: "rw" + hwaccess: "hro" + resval: "0" + }, + ] + } + + { + name: MUXED_V_12_MUX_SEL + desc: ''' + Pad signal port multiplex selection for pad muxed_v_12. The programmed value defines which port + is connected to the pad. + ''' + swaccess: "rw" + hwaccess: "hro" + resval: 5 + fields: [ + { + bits: "2:0" + enum: [ + { value: "0", name: "register", desc: "Connects the Pad to the internal configuration register."} + { value: "1", name: "port_ethernet_rxd_3", desc: "Connect port rxd_3 from port group ethernet to this pad." } + { value: "2", name: "port_gpio_io_v_12", desc: "Connect port io_v_12 from port group gpio to this pad." } + { value: "3", name: "port_pll_io_5", desc: "Connect port io_5 from port group pll to this pad." } + { value: "4", name: "port_ptme_sync", desc: "Connect port sync from port group ptme to this pad." } + { value: "5", name: "port_serial_link_i_7", desc: "Connect port i_7 from port group serial_link to this pad." } + ] + } + ] + } + + { + name: MUXED_V_13_CFG + desc: ''' + Pad signal configuration. + ''' + swaccess: "rw" + fields: [ + { + bits: "0" + name: chip2pad + desc: ''' + Data input pin from chip to padframe + ''' + swaccess: "rw" + hwaccess: "hro" + resval: "0" + }, + { + bits: "1" + name: input_en + desc: ''' + Input enable signal, active high + ''' + swaccess: "rw" + hwaccess: "hro" + resval: "0" + }, + { + bits: "2" + name: output_en + desc: ''' + Output enable signal, active high + ''' + swaccess: "rw" + hwaccess: "hro" + resval: "0" + }, + { + bits: "3" + name: pull_en + desc: ''' + Pull-up/-down enable signal, active high + ''' + swaccess: "rw" + hwaccess: "hro" + resval: "0" + }, + { + bits: "4" + name: pull_sel + desc: ''' + Pull-up/-down select signal, high: pull-up, low: pull-down + ''' + swaccess: "rw" + hwaccess: "hro" + resval: "0" + }, + ] + } + + { + name: MUXED_V_13_MUX_SEL + desc: ''' + Pad signal port multiplex selection for pad muxed_v_13. The programmed value defines which port + is connected to the pad. + ''' + swaccess: "rw" + hwaccess: "hro" + resval: 5 + fields: [ + { + bits: "2:0" + enum: [ + { value: "0", name: "register", desc: "Connects the Pad to the internal configuration register."} + { value: "1", name: "port_ethernet_txck", desc: "Connect port txck from port group ethernet to this pad." } + { value: "2", name: "port_gpio_io_v_13", desc: "Connect port io_v_13 from port group gpio to this pad." } + { value: "3", name: "port_pll_io_6", desc: "Connect port io_6 from port group pll to this pad." } + { value: "4", name: "port_ptme_ext_clk", desc: "Connect port ext_clk from port group ptme to this pad." } + { value: "5", name: "port_serial_link_rcv_clk_o", desc: "Connect port rcv_clk_o from port group serial_link to this pad." } + ] + } + ] + } + + { + name: MUXED_V_14_CFG + desc: ''' + Pad signal configuration. + ''' + swaccess: "rw" + fields: [ + { + bits: "0" + name: chip2pad + desc: ''' + Data input pin from chip to padframe + ''' + swaccess: "rw" + hwaccess: "hro" + resval: "0" + }, + { + bits: "1" + name: input_en + desc: ''' + Input enable signal, active high + ''' + swaccess: "rw" + hwaccess: "hro" + resval: "0" + }, + { + bits: "2" + name: output_en + desc: ''' + Output enable signal, active high + ''' + swaccess: "rw" + hwaccess: "hro" + resval: "0" + }, + { + bits: "3" + name: pull_en + desc: ''' + Pull-up/-down enable signal, active high + ''' + swaccess: "rw" + hwaccess: "hro" + resval: "0" + }, + { + bits: "4" + name: pull_sel + desc: ''' + Pull-up/-down select signal, high: pull-up, low: pull-down + ''' + swaccess: "rw" + hwaccess: "hro" + resval: "0" + }, + ] + } + + { + name: MUXED_V_14_MUX_SEL + desc: ''' + Pad signal port multiplex selection for pad muxed_v_14. The programmed value defines which port + is connected to the pad. + ''' + swaccess: "rw" + hwaccess: "hro" + resval: 4 + fields: [ + { + bits: "2:0" + enum: [ + { value: "0", name: "register", desc: "Connects the Pad to the internal configuration register."} + { value: "1", name: "port_ethernet_txctl", desc: "Connect port txctl from port group ethernet to this pad." } + { value: "2", name: "port_gpio_io_v_14", desc: "Connect port io_v_14 from port group gpio to this pad." } + { value: "3", name: "port_hpc_addr_0", desc: "Connect port addr_0 from port group hpc to this pad." } + { value: "4", name: "port_serial_link_o_v_0", desc: "Connect port o_v_0 from port group serial_link to this pad." } + ] + } + ] + } + + { + name: MUXED_V_15_CFG + desc: ''' + Pad signal configuration. + ''' + swaccess: "rw" + fields: [ + { + bits: "0" + name: chip2pad + desc: ''' + Data input pin from chip to padframe + ''' + swaccess: "rw" + hwaccess: "hro" + resval: "0" + }, + { + bits: "1" + name: input_en + desc: ''' + Input enable signal, active high + ''' + swaccess: "rw" + hwaccess: "hro" + resval: "0" + }, + { + bits: "2" + name: output_en + desc: ''' + Output enable signal, active high + ''' + swaccess: "rw" + hwaccess: "hro" + resval: "0" + }, + { + bits: "3" + name: pull_en + desc: ''' + Pull-up/-down enable signal, active high + ''' + swaccess: "rw" + hwaccess: "hro" + resval: "0" + }, + { + bits: "4" + name: pull_sel + desc: ''' + Pull-up/-down select signal, high: pull-up, low: pull-down + ''' + swaccess: "rw" + hwaccess: "hro" + resval: "0" + }, + ] + } + + { + name: MUXED_V_15_MUX_SEL + desc: ''' + Pad signal port multiplex selection for pad muxed_v_15. The programmed value defines which port + is connected to the pad. + ''' + swaccess: "rw" + hwaccess: "hro" + resval: 4 + fields: [ + { + bits: "2:0" + enum: [ + { value: "0", name: "register", desc: "Connects the Pad to the internal configuration register."} + { value: "1", name: "port_ethernet_txd_0", desc: "Connect port txd_0 from port group ethernet to this pad." } + { value: "2", name: "port_gpio_io_v_15", desc: "Connect port io_v_15 from port group gpio to this pad." } + { value: "3", name: "port_hpc_addr_1", desc: "Connect port addr_1 from port group hpc to this pad." } + { value: "4", name: "port_serial_link_o_v_1", desc: "Connect port o_v_1 from port group serial_link to this pad." } + ] + } + ] + } + + { + name: MUXED_V_16_CFG + desc: ''' + Pad signal configuration. + ''' + swaccess: "rw" + fields: [ + { + bits: "0" + name: chip2pad + desc: ''' + Data input pin from chip to padframe + ''' + swaccess: "rw" + hwaccess: "hro" + resval: "0" + }, + { + bits: "1" + name: input_en + desc: ''' + Input enable signal, active high + ''' + swaccess: "rw" + hwaccess: "hro" + resval: "0" + }, + { + bits: "2" + name: output_en + desc: ''' + Output enable signal, active high + ''' + swaccess: "rw" + hwaccess: "hro" + resval: "0" + }, + { + bits: "3" + name: pull_en + desc: ''' + Pull-up/-down enable signal, active high + ''' + swaccess: "rw" + hwaccess: "hro" + resval: "0" + }, + { + bits: "4" + name: pull_sel + desc: ''' + Pull-up/-down select signal, high: pull-up, low: pull-down + ''' + swaccess: "rw" + hwaccess: "hro" + resval: "0" + }, + ] + } + + { + name: MUXED_V_16_MUX_SEL + desc: ''' + Pad signal port multiplex selection for pad muxed_v_16. The programmed value defines which port + is connected to the pad. + ''' + swaccess: "rw" + hwaccess: "hro" + resval: 4 + fields: [ + { + bits: "2:0" + enum: [ + { value: "0", name: "register", desc: "Connects the Pad to the internal configuration register."} + { value: "1", name: "port_ethernet_txd_1", desc: "Connect port txd_1 from port group ethernet to this pad." } + { value: "2", name: "port_gpio_io_v_16", desc: "Connect port io_v_16 from port group gpio to this pad." } + { value: "3", name: "port_hpc_addr_2", desc: "Connect port addr_2 from port group hpc to this pad." } + { value: "4", name: "port_serial_link_o_v_2", desc: "Connect port o_v_2 from port group serial_link to this pad." } + ] + } + ] + } + + { + name: MUXED_V_17_CFG + desc: ''' + Pad signal configuration. + ''' + swaccess: "rw" + fields: [ + { + bits: "0" + name: chip2pad + desc: ''' + Data input pin from chip to padframe + ''' + swaccess: "rw" + hwaccess: "hro" + resval: "0" + }, + { + bits: "1" + name: input_en + desc: ''' + Input enable signal, active high + ''' + swaccess: "rw" + hwaccess: "hro" + resval: "0" + }, + { + bits: "2" + name: output_en + desc: ''' + Output enable signal, active high + ''' + swaccess: "rw" + hwaccess: "hro" + resval: "0" + }, + { + bits: "3" + name: pull_en + desc: ''' + Pull-up/-down enable signal, active high + ''' + swaccess: "rw" + hwaccess: "hro" + resval: "0" + }, + { + bits: "4" + name: pull_sel + desc: ''' + Pull-up/-down select signal, high: pull-up, low: pull-down + ''' + swaccess: "rw" + hwaccess: "hro" + resval: "0" + }, + ] + } + + { + name: MUXED_V_17_MUX_SEL + desc: ''' + Pad signal port multiplex selection for pad muxed_v_17. The programmed value defines which port + is connected to the pad. + ''' + swaccess: "rw" + hwaccess: "hro" + resval: 4 + fields: [ + { + bits: "2:0" + enum: [ + { value: "0", name: "register", desc: "Connects the Pad to the internal configuration register."} + { value: "1", name: "port_ethernet_txd_2", desc: "Connect port txd_2 from port group ethernet to this pad." } + { value: "2", name: "port_gpio_io_v_17", desc: "Connect port io_v_17 from port group gpio to this pad." } + { value: "3", name: "port_hpc_cmd_en", desc: "Connect port cmd_en from port group hpc to this pad." } + { value: "4", name: "port_serial_link_o_v_3", desc: "Connect port o_v_3 from port group serial_link to this pad." } + ] + } + ] + } + + { + name: MUXED_H_00_CFG + desc: ''' + Pad signal configuration. + ''' + swaccess: "rw" + fields: [ + { + bits: "0" + name: chip2pad + desc: ''' + Data input pin from chip to padframe + ''' + swaccess: "rw" + hwaccess: "hro" + resval: "0" + }, + { + bits: "1" + name: input_en + desc: ''' + Input enable signal, active high + ''' + swaccess: "rw" + hwaccess: "hro" + resval: "0" + }, + { + bits: "2" + name: output_en + desc: ''' + Output enable signal, active high + ''' + swaccess: "rw" + hwaccess: "hro" + resval: "0" + }, + { + bits: "3" + name: pull_en + desc: ''' + Pull-up/-down enable signal, active high + ''' + swaccess: "rw" + hwaccess: "hro" + resval: "0" + }, + { + bits: "4" + name: pull_sel + desc: ''' + Pull-up/-down select signal, high: pull-up, low: pull-down + ''' + swaccess: "rw" + hwaccess: "hro" + resval: "0" + }, + ] + } + + { + name: MUXED_H_00_MUX_SEL + desc: ''' + Pad signal port multiplex selection for pad muxed_h_00. The programmed value defines which port + is connected to the pad. + ''' + swaccess: "rw" + hwaccess: "hro" + resval: 4 + fields: [ + { + bits: "2:0" + enum: [ + { value: "0", name: "register", desc: "Connects the Pad to the internal configuration register."} + { value: "1", name: "port_ethernet_txd_3", desc: "Connect port txd_3 from port group ethernet to this pad." } + { value: "2", name: "port_gpio_io_h_0", desc: "Connect port io_h_0 from port group gpio to this pad." } + { value: "3", name: "port_hpc_sample", desc: "Connect port sample from port group hpc to this pad." } + { value: "4", name: "port_serial_link_o_h_0", desc: "Connect port o_h_0 from port group serial_link to this pad." } + ] + } + ] + } + + { + name: MUXED_H_01_CFG + desc: ''' + Pad signal configuration. + ''' + swaccess: "rw" + fields: [ + { + bits: "0" + name: chip2pad + desc: ''' + Data input pin from chip to padframe + ''' + swaccess: "rw" + hwaccess: "hro" + resval: "0" + }, + { + bits: "1" + name: input_en + desc: ''' + Input enable signal, active high + ''' + swaccess: "rw" + hwaccess: "hro" + resval: "0" + }, + { + bits: "2" + name: output_en + desc: ''' + Output enable signal, active high + ''' + swaccess: "rw" + hwaccess: "hro" + resval: "0" + }, + { + bits: "3" + name: pull_en + desc: ''' + Pull-up/-down enable signal, active high + ''' + swaccess: "rw" + hwaccess: "hro" + resval: "0" + }, + { + bits: "4" + name: pull_sel + desc: ''' + Pull-up/-down select signal, high: pull-up, low: pull-down + ''' + swaccess: "rw" + hwaccess: "hro" + resval: "0" + }, + ] + } + + { + name: MUXED_H_01_MUX_SEL + desc: ''' + Pad signal port multiplex selection for pad muxed_h_01. The programmed value defines which port + is connected to the pad. + ''' + swaccess: "rw" + hwaccess: "hro" + resval: 4 + fields: [ + { + bits: "2:0" + enum: [ + { value: "0", name: "register", desc: "Connects the Pad to the internal configuration register."} + { value: "1", name: "port_ethernet_md", desc: "Connect port md from port group ethernet to this pad." } + { value: "2", name: "port_gpio_io_h_1", desc: "Connect port io_h_1 from port group gpio to this pad." } + { value: "3", name: "port_llc_line_0", desc: "Connect port line_0 from port group llc to this pad." } + { value: "4", name: "port_serial_link_o_h_1", desc: "Connect port o_h_1 from port group serial_link to this pad." } + ] + } + ] + } + + { + name: MUXED_H_02_CFG + desc: ''' + Pad signal configuration. + ''' + swaccess: "rw" + fields: [ + { + bits: "0" + name: chip2pad + desc: ''' + Data input pin from chip to padframe + ''' + swaccess: "rw" + hwaccess: "hro" + resval: "0" + }, + { + bits: "1" + name: input_en + desc: ''' + Input enable signal, active high + ''' + swaccess: "rw" + hwaccess: "hro" + resval: "0" + }, + { + bits: "2" + name: output_en + desc: ''' + Output enable signal, active high + ''' + swaccess: "rw" + hwaccess: "hro" + resval: "0" + }, + { + bits: "3" + name: pull_en + desc: ''' + Pull-up/-down enable signal, active high + ''' + swaccess: "rw" + hwaccess: "hro" + resval: "0" + }, + { + bits: "4" + name: pull_sel + desc: ''' + Pull-up/-down select signal, high: pull-up, low: pull-down + ''' + swaccess: "rw" + hwaccess: "hro" + resval: "0" + }, + ] + } + + { + name: MUXED_H_02_MUX_SEL + desc: ''' + Pad signal port multiplex selection for pad muxed_h_02. The programmed value defines which port + is connected to the pad. + ''' + swaccess: "rw" + hwaccess: "hro" + resval: 4 + fields: [ + { + bits: "2:0" + enum: [ + { value: "0", name: "register", desc: "Connects the Pad to the internal configuration register."} + { value: "1", name: "port_ethernet_mdc", desc: "Connect port mdc from port group ethernet to this pad." } + { value: "2", name: "port_gpio_io_h_2", desc: "Connect port io_h_2 from port group gpio to this pad." } + { value: "3", name: "port_llc_line_1", desc: "Connect port line_1 from port group llc to this pad." } + { value: "4", name: "port_serial_link_o_h_2", desc: "Connect port o_h_2 from port group serial_link to this pad." } + ] + } + ] + } + + { + name: MUXED_H_03_CFG + desc: ''' + Pad signal configuration. + ''' + swaccess: "rw" + fields: [ + { + bits: "0" + name: chip2pad + desc: ''' + Data input pin from chip to padframe + ''' + swaccess: "rw" + hwaccess: "hro" + resval: "0" + }, + { + bits: "1" + name: input_en + desc: ''' + Input enable signal, active high + ''' + swaccess: "rw" + hwaccess: "hro" + resval: "0" + }, + { + bits: "2" + name: output_en + desc: ''' + Output enable signal, active high + ''' + swaccess: "rw" + hwaccess: "hro" + resval: "0" + }, + { + bits: "3" + name: pull_en + desc: ''' + Pull-up/-down enable signal, active high + ''' + swaccess: "rw" + hwaccess: "hro" + resval: "0" + }, + { + bits: "4" + name: pull_sel + desc: ''' + Pull-up/-down select signal, high: pull-up, low: pull-down + ''' + swaccess: "rw" + hwaccess: "hro" + resval: "0" + }, + ] + } + + { + name: MUXED_H_03_MUX_SEL + desc: ''' + Pad signal port multiplex selection for pad muxed_h_03. The programmed value defines which port + is connected to the pad. + ''' + swaccess: "rw" + hwaccess: "hro" + resval: 4 + fields: [ + { + bits: "2:0" + enum: [ + { value: "0", name: "register", desc: "Connects the Pad to the internal configuration register."} + { value: "1", name: "port_ethernet_rst_n", desc: "Connect port rst_n from port group ethernet to this pad." } + { value: "2", name: "port_gpio_io_h_3", desc: "Connect port io_h_3 from port group gpio to this pad." } + { value: "3", name: "port_obt_ext_clk", desc: "Connect port ext_clk from port group obt to this pad." } + { value: "4", name: "port_serial_link_o_h_3", desc: "Connect port o_h_3 from port group serial_link to this pad." } + ] + } + ] + } + + ] +} diff --git a/hw/padframe/astral_padframe/src/pkg_astral_padframe.sv b/hw/padframe/astral_padframe/src/pkg_astral_padframe.sv new file mode 100644 index 00000000..3d0ff9da --- /dev/null +++ b/hw/padframe/astral_padframe/src/pkg_astral_padframe.sv @@ -0,0 +1,356 @@ + +// File auto-generated by Padrick unknown +package pkg_astral_padframe; + + //Structs for periph + + //Static connections signals + typedef struct packed { + logic fll_alt_clk_o; + logic fll_host_clk_o; + logic fll_periph_clk_o; + logic fll_rt_clk_o; + logic hyper_ck_no; + logic hyper_ck_o; + logic hyper_cs_0_no; + logic hyper_cs_1_no; + logic hyper_dq_0_o; + logic hyper_dq_1_o; + logic hyper_dq_2_o; + logic hyper_dq_3_o; + logic hyper_dq_4_o; + logic hyper_dq_5_o; + logic hyper_dq_6_o; + logic hyper_dq_7_o; + logic hyper_dq_oen_i; + logic hyper_reset_no; + logic hyper_rwds_o; + logic hyper_rwds_oen_i; + logic jtag_ot_tdo_o; + logic jtag_tdo_o; + logic spw_data_o; + logic spw_strb_o; + logic uart_tx_o; + } pad_domain_periph_static_connection_signals_soc2pad_t; + + typedef struct packed { + logic boot_mode_0_i; + logic boot_mode_1_i; + logic fll_bypass_i; + logic hyper_dq_0_i; + logic hyper_dq_1_i; + logic hyper_dq_2_i; + logic hyper_dq_3_i; + logic hyper_dq_4_i; + logic hyper_dq_5_i; + logic hyper_dq_6_i; + logic hyper_dq_7_i; + logic hyper_rwds_i; + logic jtag_ot_tclk_i; + logic jtag_ot_tdi_i; + logic jtag_ot_tms_i; + logic jtag_ot_trst_ni; + logic jtag_tclk_i; + logic jtag_tdi_i; + logic jtag_tms_i; + logic jtag_trst_ni; + logic ot_boot_mode_i; + logic pwr_on_rst_ni; + logic ref_clk_i; + logic secure_boot_i; + logic spw_data_i; + logic spw_strb_i; + logic test_mode_i; + logic uart_rx_i; + } pad_domain_periph_static_connection_signals_pad2soc_t; + + // Port Group signals + typedef struct packed { + logic spih_csb_0_o; + logic spih_csb_1_o; + logic spih_sck_o; + logic spih_sd_0_o; + logic spih_sd_0_oen_i; + logic spih_sd_1_o; + logic spih_sd_1_oen_i; + logic spih_sd_2_o; + logic spih_sd_2_oen_i; + logic spih_sd_3_o; + logic spih_sd_3_oen_i; + } pad_domain_periph_port_group_spi_soc2pad_t; + + typedef struct packed { + logic spih_sd_0_i; + logic spih_sd_1_i; + logic spih_sd_2_i; + logic spih_sd_3_i; + } pad_domain_periph_port_group_spi_pad2soc_t; + + typedef struct packed { + logic eth_md_o; + logic eth_md_oen_i; + logic eth_mdc_o; + logic eth_rst_no; + logic eth_txck_o; + logic eth_txctl_o; + logic eth_txd_0_o; + logic eth_txd_1_o; + logic eth_txd_2_o; + logic eth_txd_3_o; + } pad_domain_periph_port_group_ethernet_soc2pad_t; + + typedef struct packed { + logic eth_md_i; + logic eth_rxck_i; + logic eth_rxctl_i; + logic eth_rxd_0_i; + logic eth_rxd_1_i; + logic eth_rxd_2_i; + logic eth_rxd_3_i; + } pad_domain_periph_port_group_ethernet_pad2soc_t; + + typedef struct packed { + logic can_tx_o; + } pad_domain_periph_port_group_can_soc2pad_t; + + typedef struct packed { + logic can_rx_i; + } pad_domain_periph_port_group_can_pad2soc_t; + + typedef struct packed { + logic slink_h_0_o; + logic slink_h_1_o; + logic slink_h_2_o; + logic slink_h_3_o; + logic slink_rcv_clk_o; + logic slink_v_0_o; + logic slink_v_1_o; + logic slink_v_2_o; + logic slink_v_3_o; + } pad_domain_periph_port_group_serial_link_soc2pad_t; + + typedef struct packed { + logic slink_0_i; + logic slink_1_i; + logic slink_2_i; + logic slink_3_i; + logic slink_4_i; + logic slink_5_i; + logic slink_6_i; + logic slink_7_i; + logic slink_rcv_clk_i; + } pad_domain_periph_port_group_serial_link_pad2soc_t; + + typedef struct packed { + logic i2c_scl_o; + logic i2c_scl_oen_i; + logic i2c_sda_o; + logic i2c_sda_oen_i; + } pad_domain_periph_port_group_i2c_soc2pad_t; + + typedef struct packed { + logic i2c_scl_i; + logic i2c_sda_i; + } pad_domain_periph_port_group_i2c_pad2soc_t; + + typedef struct packed { + logic tc_active_i; + logic tc_clk_i; + logic tc_data_i; + } pad_domain_periph_port_group_tc_pad2soc_t; + + typedef struct packed { + logic ptme_clk_o; + logic ptme_enc_o; + logic ptme_sync_o; + } pad_domain_periph_port_group_ptme_soc2pad_t; + + typedef struct packed { + logic ptme_ext_clk_i; + } pad_domain_periph_port_group_ptme_pad2soc_t; + + typedef struct packed { + logic hpc_addr_0_o; + logic hpc_addr_1_o; + logic hpc_addr_2_o; + logic hpc_cmd_en_o; + logic hpc_sample_o; + } pad_domain_periph_port_group_hpc_soc2pad_t; + + typedef struct packed { + logic llc_line_0_o; + logic llc_line_1_o; + } pad_domain_periph_port_group_llc_soc2pad_t; + + typedef struct packed { + logic obt_ext_clk_i; + } pad_domain_periph_port_group_obt_pad2soc_t; + + typedef struct packed { + logic spih_ot_csb_o; + logic spih_ot_sck_o; + logic spih_ot_sd_0_o; + logic spih_ot_sd_0_oen_i; + logic spih_ot_sd_1_o; + logic spih_ot_sd_1_oen_i; + logic spih_ot_sd_2_o; + logic spih_ot_sd_2_oen_i; + logic spih_ot_sd_3_o; + logic spih_ot_sd_3_oen_i; + } pad_domain_periph_port_group_spi_ot_soc2pad_t; + + typedef struct packed { + logic spih_ot_sd_0_i; + logic spih_ot_sd_1_i; + logic spih_ot_sd_2_i; + logic spih_ot_sd_3_i; + } pad_domain_periph_port_group_spi_ot_pad2soc_t; + + typedef struct packed { + logic pll_0_o; + logic pll_0_oen_i; + logic pll_1_o; + logic pll_1_oen_i; + logic pll_2_o; + logic pll_2_oen_i; + logic pll_3_o; + logic pll_3_oen_i; + logic pll_4_o; + logic pll_4_oen_i; + logic pll_5_o; + logic pll_5_oen_i; + logic pll_6_o; + logic pll_6_oen_i; + } pad_domain_periph_port_group_pll_soc2pad_t; + + typedef struct packed { + logic pll_0_i; + logic pll_1_i; + logic pll_2_i; + logic pll_3_i; + logic pll_4_i; + logic pll_5_i; + logic pll_6_i; + } pad_domain_periph_port_group_pll_pad2soc_t; + + typedef struct packed { + logic gpio_h_0_o; + logic gpio_h_0_oen_i; + logic gpio_h_1_o; + logic gpio_h_1_oen_i; + logic gpio_h_2_o; + logic gpio_h_2_oen_i; + logic gpio_h_3_o; + logic gpio_h_3_oen_i; + logic gpio_v_0_o; + logic gpio_v_0_oen_i; + logic gpio_v_1_o; + logic gpio_v_1_oen_i; + logic gpio_v_2_o; + logic gpio_v_2_oen_i; + logic gpio_v_3_o; + logic gpio_v_3_oen_i; + logic gpio_v_4_o; + logic gpio_v_4_oen_i; + logic gpio_v_5_o; + logic gpio_v_5_oen_i; + logic gpio_v_6_o; + logic gpio_v_6_oen_i; + logic gpio_v_7_o; + logic gpio_v_7_oen_i; + logic gpio_v_8_o; + logic gpio_v_8_oen_i; + logic gpio_v_9_o; + logic gpio_v_9_oen_i; + logic gpio_v_10_o; + logic gpio_v_10_oen_i; + logic gpio_v_11_o; + logic gpio_v_11_oen_i; + logic gpio_v_12_o; + logic gpio_v_12_oen_i; + logic gpio_v_13_o; + logic gpio_v_13_oen_i; + logic gpio_v_14_o; + logic gpio_v_14_oen_i; + logic gpio_v_15_o; + logic gpio_v_15_oen_i; + logic gpio_v_16_o; + logic gpio_v_16_oen_i; + logic gpio_v_17_o; + logic gpio_v_17_oen_i; + } pad_domain_periph_port_group_gpio_soc2pad_t; + + typedef struct packed { + logic gpio_h_0_i; + logic gpio_h_1_i; + logic gpio_h_2_i; + logic gpio_h_3_i; + logic gpio_v_0_i; + logic gpio_v_1_i; + logic gpio_v_2_i; + logic gpio_v_3_i; + logic gpio_v_4_i; + logic gpio_v_5_i; + logic gpio_v_6_i; + logic gpio_v_7_i; + logic gpio_v_8_i; + logic gpio_v_9_i; + logic gpio_v_10_i; + logic gpio_v_11_i; + logic gpio_v_12_i; + logic gpio_v_13_i; + logic gpio_v_14_i; + logic gpio_v_15_i; + logic gpio_v_16_i; + logic gpio_v_17_i; + } pad_domain_periph_port_group_gpio_pad2soc_t; + + typedef struct packed { + pad_domain_periph_port_group_spi_soc2pad_t spi; + pad_domain_periph_port_group_ethernet_soc2pad_t ethernet; + pad_domain_periph_port_group_can_soc2pad_t can; + pad_domain_periph_port_group_serial_link_soc2pad_t serial_link; + pad_domain_periph_port_group_i2c_soc2pad_t i2c; + pad_domain_periph_port_group_ptme_soc2pad_t ptme; + pad_domain_periph_port_group_hpc_soc2pad_t hpc; + pad_domain_periph_port_group_llc_soc2pad_t llc; + pad_domain_periph_port_group_spi_ot_soc2pad_t spi_ot; + pad_domain_periph_port_group_pll_soc2pad_t pll; + pad_domain_periph_port_group_gpio_soc2pad_t gpio; + } pad_domain_periph_ports_soc2pad_t; + + typedef struct packed { + pad_domain_periph_port_group_spi_pad2soc_t spi; + pad_domain_periph_port_group_ethernet_pad2soc_t ethernet; + pad_domain_periph_port_group_can_pad2soc_t can; + pad_domain_periph_port_group_serial_link_pad2soc_t serial_link; + pad_domain_periph_port_group_i2c_pad2soc_t i2c; + pad_domain_periph_port_group_tc_pad2soc_t tc; + pad_domain_periph_port_group_ptme_pad2soc_t ptme; + pad_domain_periph_port_group_obt_pad2soc_t obt; + pad_domain_periph_port_group_spi_ot_pad2soc_t spi_ot; + pad_domain_periph_port_group_pll_pad2soc_t pll; + pad_domain_periph_port_group_gpio_pad2soc_t gpio; + } pad_domain_periph_ports_pad2soc_t; + + + //Toplevel structs + + typedef struct packed { + pad_domain_periph_static_connection_signals_pad2soc_t periph; + } static_connection_signals_pad2soc_t; + + typedef struct packed { + pad_domain_periph_static_connection_signals_soc2pad_t periph; + } static_connection_signals_soc2pad_t; + + typedef struct packed { + pad_domain_periph_ports_pad2soc_t periph; + } port_signals_pad2soc_t; + + typedef struct packed { + pad_domain_periph_ports_soc2pad_t periph; + } port_signals_soc2pad_t; + + +endpackage : pkg_astral_padframe diff --git a/hw/padframe/astral_padframe/src/pkg_internal_astral_padframe_periph.sv b/hw/padframe/astral_padframe/src/pkg_internal_astral_padframe_periph.sv new file mode 100644 index 00000000..9fad7717 --- /dev/null +++ b/hw/padframe/astral_padframe/src/pkg_internal_astral_padframe_periph.sv @@ -0,0 +1,549 @@ + +// File auto-generated by Padrick unknown +package pkg_internal_astral_padframe_periph; + typedef struct packed{ + logic chip2pad; + logic input_en; + logic output_en; + logic pull_en; + logic pull_sel; + } mux_to_pad_muxed_v_00_t; + + typedef struct packed{ + logic pad2chip; + } pad_to_mux_muxed_v_00_t; + + typedef struct packed{ + logic chip2pad; + logic input_en; + logic output_en; + logic pull_en; + logic pull_sel; + } mux_to_pad_muxed_v_01_t; + + typedef struct packed{ + logic pad2chip; + } pad_to_mux_muxed_v_01_t; + + typedef struct packed{ + logic chip2pad; + logic input_en; + logic output_en; + logic pull_en; + logic pull_sel; + } mux_to_pad_muxed_v_02_t; + + typedef struct packed{ + logic pad2chip; + } pad_to_mux_muxed_v_02_t; + + typedef struct packed{ + logic chip2pad; + logic input_en; + logic output_en; + logic pull_en; + logic pull_sel; + } mux_to_pad_muxed_v_03_t; + + typedef struct packed{ + logic pad2chip; + } pad_to_mux_muxed_v_03_t; + + typedef struct packed{ + logic chip2pad; + logic input_en; + logic output_en; + logic pull_en; + logic pull_sel; + } mux_to_pad_muxed_v_04_t; + + typedef struct packed{ + logic pad2chip; + } pad_to_mux_muxed_v_04_t; + + typedef struct packed{ + logic chip2pad; + logic input_en; + logic output_en; + logic pull_en; + logic pull_sel; + } mux_to_pad_muxed_v_05_t; + + typedef struct packed{ + logic pad2chip; + } pad_to_mux_muxed_v_05_t; + + typedef struct packed{ + logic chip2pad; + logic input_en; + logic output_en; + logic pull_en; + logic pull_sel; + } mux_to_pad_muxed_v_06_t; + + typedef struct packed{ + logic pad2chip; + } pad_to_mux_muxed_v_06_t; + + typedef struct packed{ + logic chip2pad; + logic input_en; + logic output_en; + logic pull_en; + logic pull_sel; + } mux_to_pad_muxed_v_07_t; + + typedef struct packed{ + logic pad2chip; + } pad_to_mux_muxed_v_07_t; + + typedef struct packed{ + logic chip2pad; + logic input_en; + logic output_en; + logic pull_en; + logic pull_sel; + } mux_to_pad_muxed_v_08_t; + + typedef struct packed{ + logic pad2chip; + } pad_to_mux_muxed_v_08_t; + + typedef struct packed{ + logic chip2pad; + logic input_en; + logic output_en; + logic pull_en; + logic pull_sel; + } mux_to_pad_muxed_v_09_t; + + typedef struct packed{ + logic pad2chip; + } pad_to_mux_muxed_v_09_t; + + typedef struct packed{ + logic chip2pad; + logic input_en; + logic output_en; + logic pull_en; + logic pull_sel; + } mux_to_pad_muxed_v_10_t; + + typedef struct packed{ + logic pad2chip; + } pad_to_mux_muxed_v_10_t; + + typedef struct packed{ + logic chip2pad; + logic input_en; + logic output_en; + logic pull_en; + logic pull_sel; + } mux_to_pad_muxed_v_11_t; + + typedef struct packed{ + logic pad2chip; + } pad_to_mux_muxed_v_11_t; + + typedef struct packed{ + logic chip2pad; + logic input_en; + logic output_en; + logic pull_en; + logic pull_sel; + } mux_to_pad_muxed_v_12_t; + + typedef struct packed{ + logic pad2chip; + } pad_to_mux_muxed_v_12_t; + + typedef struct packed{ + logic chip2pad; + logic input_en; + logic output_en; + logic pull_en; + logic pull_sel; + } mux_to_pad_muxed_v_13_t; + + typedef struct packed{ + logic pad2chip; + } pad_to_mux_muxed_v_13_t; + + typedef struct packed{ + logic chip2pad; + logic input_en; + logic output_en; + logic pull_en; + logic pull_sel; + } mux_to_pad_muxed_v_14_t; + + typedef struct packed{ + logic pad2chip; + } pad_to_mux_muxed_v_14_t; + + typedef struct packed{ + logic chip2pad; + logic input_en; + logic output_en; + logic pull_en; + logic pull_sel; + } mux_to_pad_muxed_v_15_t; + + typedef struct packed{ + logic pad2chip; + } pad_to_mux_muxed_v_15_t; + + typedef struct packed{ + logic chip2pad; + logic input_en; + logic output_en; + logic pull_en; + logic pull_sel; + } mux_to_pad_muxed_v_16_t; + + typedef struct packed{ + logic pad2chip; + } pad_to_mux_muxed_v_16_t; + + typedef struct packed{ + logic chip2pad; + logic input_en; + logic output_en; + logic pull_en; + logic pull_sel; + } mux_to_pad_muxed_v_17_t; + + typedef struct packed{ + logic pad2chip; + } pad_to_mux_muxed_v_17_t; + + typedef struct packed{ + logic chip2pad; + logic input_en; + logic output_en; + logic pull_en; + logic pull_sel; + } mux_to_pad_muxed_h_00_t; + + typedef struct packed{ + logic pad2chip; + } pad_to_mux_muxed_h_00_t; + + typedef struct packed{ + logic chip2pad; + logic input_en; + logic output_en; + logic pull_en; + logic pull_sel; + } mux_to_pad_muxed_h_01_t; + + typedef struct packed{ + logic pad2chip; + } pad_to_mux_muxed_h_01_t; + + typedef struct packed{ + logic chip2pad; + logic input_en; + logic output_en; + logic pull_en; + logic pull_sel; + } mux_to_pad_muxed_h_02_t; + + typedef struct packed{ + logic pad2chip; + } pad_to_mux_muxed_h_02_t; + + typedef struct packed{ + logic chip2pad; + logic input_en; + logic output_en; + logic pull_en; + logic pull_sel; + } mux_to_pad_muxed_h_03_t; + + typedef struct packed{ + logic pad2chip; + } pad_to_mux_muxed_h_03_t; + + typedef struct packed{ + mux_to_pad_muxed_v_00_t muxed_v_00; + mux_to_pad_muxed_v_01_t muxed_v_01; + mux_to_pad_muxed_v_02_t muxed_v_02; + mux_to_pad_muxed_v_03_t muxed_v_03; + mux_to_pad_muxed_v_04_t muxed_v_04; + mux_to_pad_muxed_v_05_t muxed_v_05; + mux_to_pad_muxed_v_06_t muxed_v_06; + mux_to_pad_muxed_v_07_t muxed_v_07; + mux_to_pad_muxed_v_08_t muxed_v_08; + mux_to_pad_muxed_v_09_t muxed_v_09; + mux_to_pad_muxed_v_10_t muxed_v_10; + mux_to_pad_muxed_v_11_t muxed_v_11; + mux_to_pad_muxed_v_12_t muxed_v_12; + mux_to_pad_muxed_v_13_t muxed_v_13; + mux_to_pad_muxed_v_14_t muxed_v_14; + mux_to_pad_muxed_v_15_t muxed_v_15; + mux_to_pad_muxed_v_16_t muxed_v_16; + mux_to_pad_muxed_v_17_t muxed_v_17; + mux_to_pad_muxed_h_00_t muxed_h_00; + mux_to_pad_muxed_h_01_t muxed_h_01; + mux_to_pad_muxed_h_02_t muxed_h_02; + mux_to_pad_muxed_h_03_t muxed_h_03; + } mux_to_pads_t; + + typedef struct packed{ + pad_to_mux_muxed_v_00_t muxed_v_00; + pad_to_mux_muxed_v_01_t muxed_v_01; + pad_to_mux_muxed_v_02_t muxed_v_02; + pad_to_mux_muxed_v_03_t muxed_v_03; + pad_to_mux_muxed_v_04_t muxed_v_04; + pad_to_mux_muxed_v_05_t muxed_v_05; + pad_to_mux_muxed_v_06_t muxed_v_06; + pad_to_mux_muxed_v_07_t muxed_v_07; + pad_to_mux_muxed_v_08_t muxed_v_08; + pad_to_mux_muxed_v_09_t muxed_v_09; + pad_to_mux_muxed_v_10_t muxed_v_10; + pad_to_mux_muxed_v_11_t muxed_v_11; + pad_to_mux_muxed_v_12_t muxed_v_12; + pad_to_mux_muxed_v_13_t muxed_v_13; + pad_to_mux_muxed_v_14_t muxed_v_14; + pad_to_mux_muxed_v_15_t muxed_v_15; + pad_to_mux_muxed_v_16_t muxed_v_16; + pad_to_mux_muxed_v_17_t muxed_v_17; + pad_to_mux_muxed_h_00_t muxed_h_00; + pad_to_mux_muxed_h_01_t muxed_h_01; + pad_to_mux_muxed_h_02_t muxed_h_02; + pad_to_mux_muxed_h_03_t muxed_h_03; + } pads_to_mux_t; + + + + // Indices definitions + + parameter PAD_MUX_GROUP_MUXED_H_00_SEL_WIDTH = 3; + parameter logic[2:0] PAD_MUX_GROUP_MUXED_H_00_SEL_DEFAULT = 3'd0; + parameter logic[2:0] PAD_MUX_GROUP_MUXED_H_00_SEL_ETHERNET_TXD_3 = 3'd1; + parameter logic[2:0] PAD_MUX_GROUP_MUXED_H_00_SEL_GPIO_IO_H_0 = 3'd2; + parameter logic[2:0] PAD_MUX_GROUP_MUXED_H_00_SEL_HPC_SAMPLE = 3'd3; + parameter logic[2:0] PAD_MUX_GROUP_MUXED_H_00_SEL_SERIAL_LINK_O_H_0 = 3'd4; + + parameter PAD_MUX_GROUP_MUXED_H_01_SEL_WIDTH = 3; + parameter logic[2:0] PAD_MUX_GROUP_MUXED_H_01_SEL_DEFAULT = 3'd0; + parameter logic[2:0] PAD_MUX_GROUP_MUXED_H_01_SEL_ETHERNET_MD = 3'd1; + parameter logic[2:0] PAD_MUX_GROUP_MUXED_H_01_SEL_GPIO_IO_H_1 = 3'd2; + parameter logic[2:0] PAD_MUX_GROUP_MUXED_H_01_SEL_LLC_LINE_0 = 3'd3; + parameter logic[2:0] PAD_MUX_GROUP_MUXED_H_01_SEL_SERIAL_LINK_O_H_1 = 3'd4; + + parameter PAD_MUX_GROUP_MUXED_H_02_SEL_WIDTH = 3; + parameter logic[2:0] PAD_MUX_GROUP_MUXED_H_02_SEL_DEFAULT = 3'd0; + parameter logic[2:0] PAD_MUX_GROUP_MUXED_H_02_SEL_ETHERNET_MDC = 3'd1; + parameter logic[2:0] PAD_MUX_GROUP_MUXED_H_02_SEL_GPIO_IO_H_2 = 3'd2; + parameter logic[2:0] PAD_MUX_GROUP_MUXED_H_02_SEL_LLC_LINE_1 = 3'd3; + parameter logic[2:0] PAD_MUX_GROUP_MUXED_H_02_SEL_SERIAL_LINK_O_H_2 = 3'd4; + + parameter PAD_MUX_GROUP_MUXED_H_03_SEL_WIDTH = 3; + parameter logic[2:0] PAD_MUX_GROUP_MUXED_H_03_SEL_DEFAULT = 3'd0; + parameter logic[2:0] PAD_MUX_GROUP_MUXED_H_03_SEL_ETHERNET_RST_N = 3'd1; + parameter logic[2:0] PAD_MUX_GROUP_MUXED_H_03_SEL_GPIO_IO_H_3 = 3'd2; + parameter logic[2:0] PAD_MUX_GROUP_MUXED_H_03_SEL_OBT_EXT_CLK = 3'd3; + parameter logic[2:0] PAD_MUX_GROUP_MUXED_H_03_SEL_SERIAL_LINK_O_H_3 = 3'd4; + + parameter PAD_MUX_GROUP_MUXED_V_00_SEL_WIDTH = 3; + parameter logic[2:0] PAD_MUX_GROUP_MUXED_V_00_SEL_DEFAULT = 3'd0; + parameter logic[2:0] PAD_MUX_GROUP_MUXED_V_00_SEL_CAN_RX = 3'd1; + parameter logic[2:0] PAD_MUX_GROUP_MUXED_V_00_SEL_GPIO_IO_V_0 = 3'd2; + parameter logic[2:0] PAD_MUX_GROUP_MUXED_V_00_SEL_I2C_SDA = 3'd3; + parameter logic[2:0] PAD_MUX_GROUP_MUXED_V_00_SEL_SPI_SCK = 3'd4; + parameter logic[2:0] PAD_MUX_GROUP_MUXED_V_00_SEL_SPI_OT_SCK = 3'd5; + + parameter PAD_MUX_GROUP_MUXED_V_01_SEL_WIDTH = 3; + parameter logic[2:0] PAD_MUX_GROUP_MUXED_V_01_SEL_DEFAULT = 3'd0; + parameter logic[2:0] PAD_MUX_GROUP_MUXED_V_01_SEL_CAN_TX = 3'd1; + parameter logic[2:0] PAD_MUX_GROUP_MUXED_V_01_SEL_GPIO_IO_V_1 = 3'd2; + parameter logic[2:0] PAD_MUX_GROUP_MUXED_V_01_SEL_I2C_SCL = 3'd3; + parameter logic[2:0] PAD_MUX_GROUP_MUXED_V_01_SEL_SPI_CSB_0 = 3'd4; + parameter logic[2:0] PAD_MUX_GROUP_MUXED_V_01_SEL_SPI_OT_CSB = 3'd5; + + parameter PAD_MUX_GROUP_MUXED_V_02_SEL_WIDTH = 2; + parameter logic[1:0] PAD_MUX_GROUP_MUXED_V_02_SEL_DEFAULT = 2'd0; + parameter logic[1:0] PAD_MUX_GROUP_MUXED_V_02_SEL_GPIO_IO_V_2 = 2'd1; + parameter logic[1:0] PAD_MUX_GROUP_MUXED_V_02_SEL_SPI_CSB_1 = 2'd2; + parameter logic[1:0] PAD_MUX_GROUP_MUXED_V_02_SEL_SPI_OT_SD_0 = 2'd3; + + parameter PAD_MUX_GROUP_MUXED_V_03_SEL_WIDTH = 2; + parameter logic[1:0] PAD_MUX_GROUP_MUXED_V_03_SEL_DEFAULT = 2'd0; + parameter logic[1:0] PAD_MUX_GROUP_MUXED_V_03_SEL_GPIO_IO_V_3 = 2'd1; + parameter logic[1:0] PAD_MUX_GROUP_MUXED_V_03_SEL_SPI_SD_0 = 2'd2; + parameter logic[1:0] PAD_MUX_GROUP_MUXED_V_03_SEL_SPI_OT_SD_1 = 2'd3; + + parameter PAD_MUX_GROUP_MUXED_V_04_SEL_WIDTH = 3; + parameter logic[2:0] PAD_MUX_GROUP_MUXED_V_04_SEL_DEFAULT = 3'd0; + parameter logic[2:0] PAD_MUX_GROUP_MUXED_V_04_SEL_GPIO_IO_V_4 = 3'd1; + parameter logic[2:0] PAD_MUX_GROUP_MUXED_V_04_SEL_SERIAL_LINK_RCV_CLK_I = 3'd2; + parameter logic[2:0] PAD_MUX_GROUP_MUXED_V_04_SEL_SPI_SD_1 = 3'd3; + parameter logic[2:0] PAD_MUX_GROUP_MUXED_V_04_SEL_SPI_OT_SD_2 = 3'd4; + + parameter PAD_MUX_GROUP_MUXED_V_05_SEL_WIDTH = 3; + parameter logic[2:0] PAD_MUX_GROUP_MUXED_V_05_SEL_DEFAULT = 3'd0; + parameter logic[2:0] PAD_MUX_GROUP_MUXED_V_05_SEL_GPIO_IO_V_5 = 3'd1; + parameter logic[2:0] PAD_MUX_GROUP_MUXED_V_05_SEL_SERIAL_LINK_I_0 = 3'd2; + parameter logic[2:0] PAD_MUX_GROUP_MUXED_V_05_SEL_SPI_SD_2 = 3'd3; + parameter logic[2:0] PAD_MUX_GROUP_MUXED_V_05_SEL_SPI_OT_SD_3 = 3'd4; + + parameter PAD_MUX_GROUP_MUXED_V_06_SEL_WIDTH = 2; + parameter logic[1:0] PAD_MUX_GROUP_MUXED_V_06_SEL_DEFAULT = 2'd0; + parameter logic[1:0] PAD_MUX_GROUP_MUXED_V_06_SEL_GPIO_IO_V_6 = 2'd1; + parameter logic[1:0] PAD_MUX_GROUP_MUXED_V_06_SEL_SERIAL_LINK_I_1 = 2'd2; + parameter logic[1:0] PAD_MUX_GROUP_MUXED_V_06_SEL_SPI_SD_3 = 2'd3; + + parameter PAD_MUX_GROUP_MUXED_V_07_SEL_WIDTH = 3; + parameter logic[2:0] PAD_MUX_GROUP_MUXED_V_07_SEL_DEFAULT = 3'd0; + parameter logic[2:0] PAD_MUX_GROUP_MUXED_V_07_SEL_ETHERNET_RXCK = 3'd1; + parameter logic[2:0] PAD_MUX_GROUP_MUXED_V_07_SEL_GPIO_IO_V_7 = 3'd2; + parameter logic[2:0] PAD_MUX_GROUP_MUXED_V_07_SEL_PLL_IO_0 = 3'd3; + parameter logic[2:0] PAD_MUX_GROUP_MUXED_V_07_SEL_SERIAL_LINK_I_2 = 3'd4; + parameter logic[2:0] PAD_MUX_GROUP_MUXED_V_07_SEL_TC_ACTIVE = 3'd5; + + parameter PAD_MUX_GROUP_MUXED_V_08_SEL_WIDTH = 3; + parameter logic[2:0] PAD_MUX_GROUP_MUXED_V_08_SEL_DEFAULT = 3'd0; + parameter logic[2:0] PAD_MUX_GROUP_MUXED_V_08_SEL_ETHERNET_RXCTL = 3'd1; + parameter logic[2:0] PAD_MUX_GROUP_MUXED_V_08_SEL_GPIO_IO_V_8 = 3'd2; + parameter logic[2:0] PAD_MUX_GROUP_MUXED_V_08_SEL_PLL_IO_1 = 3'd3; + parameter logic[2:0] PAD_MUX_GROUP_MUXED_V_08_SEL_SERIAL_LINK_I_3 = 3'd4; + parameter logic[2:0] PAD_MUX_GROUP_MUXED_V_08_SEL_TC_CLK = 3'd5; + + parameter PAD_MUX_GROUP_MUXED_V_09_SEL_WIDTH = 3; + parameter logic[2:0] PAD_MUX_GROUP_MUXED_V_09_SEL_DEFAULT = 3'd0; + parameter logic[2:0] PAD_MUX_GROUP_MUXED_V_09_SEL_ETHERNET_RXD_0 = 3'd1; + parameter logic[2:0] PAD_MUX_GROUP_MUXED_V_09_SEL_GPIO_IO_V_9 = 3'd2; + parameter logic[2:0] PAD_MUX_GROUP_MUXED_V_09_SEL_PLL_IO_2 = 3'd3; + parameter logic[2:0] PAD_MUX_GROUP_MUXED_V_09_SEL_SERIAL_LINK_I_4 = 3'd4; + parameter logic[2:0] PAD_MUX_GROUP_MUXED_V_09_SEL_TC_DATA = 3'd5; + + parameter PAD_MUX_GROUP_MUXED_V_10_SEL_WIDTH = 3; + parameter logic[2:0] PAD_MUX_GROUP_MUXED_V_10_SEL_DEFAULT = 3'd0; + parameter logic[2:0] PAD_MUX_GROUP_MUXED_V_10_SEL_ETHERNET_RXD_1 = 3'd1; + parameter logic[2:0] PAD_MUX_GROUP_MUXED_V_10_SEL_GPIO_IO_V_10 = 3'd2; + parameter logic[2:0] PAD_MUX_GROUP_MUXED_V_10_SEL_PLL_IO_3 = 3'd3; + parameter logic[2:0] PAD_MUX_GROUP_MUXED_V_10_SEL_PTME_CLK = 3'd4; + parameter logic[2:0] PAD_MUX_GROUP_MUXED_V_10_SEL_SERIAL_LINK_I_5 = 3'd5; + + parameter PAD_MUX_GROUP_MUXED_V_11_SEL_WIDTH = 3; + parameter logic[2:0] PAD_MUX_GROUP_MUXED_V_11_SEL_DEFAULT = 3'd0; + parameter logic[2:0] PAD_MUX_GROUP_MUXED_V_11_SEL_ETHERNET_RXD_2 = 3'd1; + parameter logic[2:0] PAD_MUX_GROUP_MUXED_V_11_SEL_GPIO_IO_V_11 = 3'd2; + parameter logic[2:0] PAD_MUX_GROUP_MUXED_V_11_SEL_PLL_IO_4 = 3'd3; + parameter logic[2:0] PAD_MUX_GROUP_MUXED_V_11_SEL_PTME_ENC = 3'd4; + parameter logic[2:0] PAD_MUX_GROUP_MUXED_V_11_SEL_SERIAL_LINK_I_6 = 3'd5; + + parameter PAD_MUX_GROUP_MUXED_V_12_SEL_WIDTH = 3; + parameter logic[2:0] PAD_MUX_GROUP_MUXED_V_12_SEL_DEFAULT = 3'd0; + parameter logic[2:0] PAD_MUX_GROUP_MUXED_V_12_SEL_ETHERNET_RXD_3 = 3'd1; + parameter logic[2:0] PAD_MUX_GROUP_MUXED_V_12_SEL_GPIO_IO_V_12 = 3'd2; + parameter logic[2:0] PAD_MUX_GROUP_MUXED_V_12_SEL_PLL_IO_5 = 3'd3; + parameter logic[2:0] PAD_MUX_GROUP_MUXED_V_12_SEL_PTME_SYNC = 3'd4; + parameter logic[2:0] PAD_MUX_GROUP_MUXED_V_12_SEL_SERIAL_LINK_I_7 = 3'd5; + + parameter PAD_MUX_GROUP_MUXED_V_13_SEL_WIDTH = 3; + parameter logic[2:0] PAD_MUX_GROUP_MUXED_V_13_SEL_DEFAULT = 3'd0; + parameter logic[2:0] PAD_MUX_GROUP_MUXED_V_13_SEL_ETHERNET_TXCK = 3'd1; + parameter logic[2:0] PAD_MUX_GROUP_MUXED_V_13_SEL_GPIO_IO_V_13 = 3'd2; + parameter logic[2:0] PAD_MUX_GROUP_MUXED_V_13_SEL_PLL_IO_6 = 3'd3; + parameter logic[2:0] PAD_MUX_GROUP_MUXED_V_13_SEL_PTME_EXT_CLK = 3'd4; + parameter logic[2:0] PAD_MUX_GROUP_MUXED_V_13_SEL_SERIAL_LINK_RCV_CLK_O = 3'd5; + + parameter PAD_MUX_GROUP_MUXED_V_14_SEL_WIDTH = 3; + parameter logic[2:0] PAD_MUX_GROUP_MUXED_V_14_SEL_DEFAULT = 3'd0; + parameter logic[2:0] PAD_MUX_GROUP_MUXED_V_14_SEL_ETHERNET_TXCTL = 3'd1; + parameter logic[2:0] PAD_MUX_GROUP_MUXED_V_14_SEL_GPIO_IO_V_14 = 3'd2; + parameter logic[2:0] PAD_MUX_GROUP_MUXED_V_14_SEL_HPC_ADDR_0 = 3'd3; + parameter logic[2:0] PAD_MUX_GROUP_MUXED_V_14_SEL_SERIAL_LINK_O_V_0 = 3'd4; + + parameter PAD_MUX_GROUP_MUXED_V_15_SEL_WIDTH = 3; + parameter logic[2:0] PAD_MUX_GROUP_MUXED_V_15_SEL_DEFAULT = 3'd0; + parameter logic[2:0] PAD_MUX_GROUP_MUXED_V_15_SEL_ETHERNET_TXD_0 = 3'd1; + parameter logic[2:0] PAD_MUX_GROUP_MUXED_V_15_SEL_GPIO_IO_V_15 = 3'd2; + parameter logic[2:0] PAD_MUX_GROUP_MUXED_V_15_SEL_HPC_ADDR_1 = 3'd3; + parameter logic[2:0] PAD_MUX_GROUP_MUXED_V_15_SEL_SERIAL_LINK_O_V_1 = 3'd4; + + parameter PAD_MUX_GROUP_MUXED_V_16_SEL_WIDTH = 3; + parameter logic[2:0] PAD_MUX_GROUP_MUXED_V_16_SEL_DEFAULT = 3'd0; + parameter logic[2:0] PAD_MUX_GROUP_MUXED_V_16_SEL_ETHERNET_TXD_1 = 3'd1; + parameter logic[2:0] PAD_MUX_GROUP_MUXED_V_16_SEL_GPIO_IO_V_16 = 3'd2; + parameter logic[2:0] PAD_MUX_GROUP_MUXED_V_16_SEL_HPC_ADDR_2 = 3'd3; + parameter logic[2:0] PAD_MUX_GROUP_MUXED_V_16_SEL_SERIAL_LINK_O_V_2 = 3'd4; + + parameter PAD_MUX_GROUP_MUXED_V_17_SEL_WIDTH = 3; + parameter logic[2:0] PAD_MUX_GROUP_MUXED_V_17_SEL_DEFAULT = 3'd0; + parameter logic[2:0] PAD_MUX_GROUP_MUXED_V_17_SEL_ETHERNET_TXD_2 = 3'd1; + parameter logic[2:0] PAD_MUX_GROUP_MUXED_V_17_SEL_GPIO_IO_V_17 = 3'd2; + parameter logic[2:0] PAD_MUX_GROUP_MUXED_V_17_SEL_HPC_CMD_EN = 3'd3; + parameter logic[2:0] PAD_MUX_GROUP_MUXED_V_17_SEL_SERIAL_LINK_O_V_3 = 3'd4; + + // Dynamic Pad instance index + + parameter PORT_MUX_GROUP_MUXED_H_00_SEL_WIDTH = 1; + parameter logic[0:0] PORT_MUX_GROUP_MUXED_H_00_SEL_MUXED_H_00 = 1'd0; + + parameter PORT_MUX_GROUP_MUXED_H_01_SEL_WIDTH = 1; + parameter logic[0:0] PORT_MUX_GROUP_MUXED_H_01_SEL_MUXED_H_01 = 1'd0; + + parameter PORT_MUX_GROUP_MUXED_H_02_SEL_WIDTH = 1; + parameter logic[0:0] PORT_MUX_GROUP_MUXED_H_02_SEL_MUXED_H_02 = 1'd0; + + parameter PORT_MUX_GROUP_MUXED_H_03_SEL_WIDTH = 1; + parameter logic[0:0] PORT_MUX_GROUP_MUXED_H_03_SEL_MUXED_H_03 = 1'd0; + + parameter PORT_MUX_GROUP_MUXED_V_00_SEL_WIDTH = 1; + parameter logic[0:0] PORT_MUX_GROUP_MUXED_V_00_SEL_MUXED_V_00 = 1'd0; + + parameter PORT_MUX_GROUP_MUXED_V_01_SEL_WIDTH = 1; + parameter logic[0:0] PORT_MUX_GROUP_MUXED_V_01_SEL_MUXED_V_01 = 1'd0; + + parameter PORT_MUX_GROUP_MUXED_V_02_SEL_WIDTH = 1; + parameter logic[0:0] PORT_MUX_GROUP_MUXED_V_02_SEL_MUXED_V_02 = 1'd0; + + parameter PORT_MUX_GROUP_MUXED_V_03_SEL_WIDTH = 1; + parameter logic[0:0] PORT_MUX_GROUP_MUXED_V_03_SEL_MUXED_V_03 = 1'd0; + + parameter PORT_MUX_GROUP_MUXED_V_04_SEL_WIDTH = 1; + parameter logic[0:0] PORT_MUX_GROUP_MUXED_V_04_SEL_MUXED_V_04 = 1'd0; + + parameter PORT_MUX_GROUP_MUXED_V_05_SEL_WIDTH = 1; + parameter logic[0:0] PORT_MUX_GROUP_MUXED_V_05_SEL_MUXED_V_05 = 1'd0; + + parameter PORT_MUX_GROUP_MUXED_V_06_SEL_WIDTH = 1; + parameter logic[0:0] PORT_MUX_GROUP_MUXED_V_06_SEL_MUXED_V_06 = 1'd0; + + parameter PORT_MUX_GROUP_MUXED_V_07_SEL_WIDTH = 1; + parameter logic[0:0] PORT_MUX_GROUP_MUXED_V_07_SEL_MUXED_V_07 = 1'd0; + + parameter PORT_MUX_GROUP_MUXED_V_08_SEL_WIDTH = 1; + parameter logic[0:0] PORT_MUX_GROUP_MUXED_V_08_SEL_MUXED_V_08 = 1'd0; + + parameter PORT_MUX_GROUP_MUXED_V_09_SEL_WIDTH = 1; + parameter logic[0:0] PORT_MUX_GROUP_MUXED_V_09_SEL_MUXED_V_09 = 1'd0; + + parameter PORT_MUX_GROUP_MUXED_V_10_SEL_WIDTH = 1; + parameter logic[0:0] PORT_MUX_GROUP_MUXED_V_10_SEL_MUXED_V_10 = 1'd0; + + parameter PORT_MUX_GROUP_MUXED_V_11_SEL_WIDTH = 1; + parameter logic[0:0] PORT_MUX_GROUP_MUXED_V_11_SEL_MUXED_V_11 = 1'd0; + + parameter PORT_MUX_GROUP_MUXED_V_12_SEL_WIDTH = 1; + parameter logic[0:0] PORT_MUX_GROUP_MUXED_V_12_SEL_MUXED_V_12 = 1'd0; + + parameter PORT_MUX_GROUP_MUXED_V_13_SEL_WIDTH = 1; + parameter logic[0:0] PORT_MUX_GROUP_MUXED_V_13_SEL_MUXED_V_13 = 1'd0; + + parameter PORT_MUX_GROUP_MUXED_V_14_SEL_WIDTH = 1; + parameter logic[0:0] PORT_MUX_GROUP_MUXED_V_14_SEL_MUXED_V_14 = 1'd0; + + parameter PORT_MUX_GROUP_MUXED_V_15_SEL_WIDTH = 1; + parameter logic[0:0] PORT_MUX_GROUP_MUXED_V_15_SEL_MUXED_V_15 = 1'd0; + + parameter PORT_MUX_GROUP_MUXED_V_16_SEL_WIDTH = 1; + parameter logic[0:0] PORT_MUX_GROUP_MUXED_V_16_SEL_MUXED_V_16 = 1'd0; + + parameter PORT_MUX_GROUP_MUXED_V_17_SEL_WIDTH = 1; + parameter logic[0:0] PORT_MUX_GROUP_MUXED_V_17_SEL_MUXED_V_17 = 1'd0; +endpackage : pkg_internal_astral_padframe_periph diff --git a/hw/padframe/astral_padframe/src_files.yml b/hw/padframe/astral_padframe/src_files.yml new file mode 100644 index 00000000..1ebdf92d --- /dev/null +++ b/hw/padframe/astral_padframe/src_files.yml @@ -0,0 +1,14 @@ + +# File auto-generated by Padrick unknown +astral_padframe: + files: + - src/pkg_astral_padframe.sv + - src/pkg_internal_astral_padframe_periph.sv + - src/astral_padframe_periph_config_reg_pkg.sv + - src/astral_padframe_periph_config_reg_top.sv + - src/astral_padframe_periph_pads.sv + - src/astral_padframe_periph_muxer.sv + - src/astral_padframe_periph.sv + - src/astral_padframe.sv + vlog_opts: + - -L axi_lib \ No newline at end of file diff --git a/hw/padframe/pad_behav.sv b/hw/padframe/pad_behav.sv new file mode 100644 index 00000000..98c3b15f --- /dev/null +++ b/hw/padframe/pad_behav.sv @@ -0,0 +1,139 @@ +// Copyright 2023 ETH Zurich and University of Bologna. +// Solderpad Hardware License, Version 0.51, see LICENSE for details. +// SPDX-License-Identifier: SHL-0.51 +// +// Behavioural models of the pads used by Astral's padframe +// +// Author: Victor Isachi + +module PDVDDTIE_18_18_NT_DR_V ( + output logic SNS, + output logic RTO +); + + assign SNS = 1'b1; + assign RTO = 1'b1; + +endmodule: PDVDDTIE_18_18_NT_DR_V + +module PVDD_08_08_NT_DR_H ( + input logic SNS, + input logic RTO +); +endmodule: PVDD_08_08_NT_DR_H + +module PVDD_08_08_NT_DR_V ( + input logic SNS, + input logic RTO +); +endmodule: PVDD_08_08_NT_DR_V + +module PVSS_08_08_NT_DR_H ( + input logic SNS, + input logic RTO +); +endmodule: PVSS_08_08_NT_DR_H + +module PVSS_08_08_NT_DR_V ( + input logic SNS, + input logic RTO +); +endmodule: PVSS_08_08_NT_DR_V + +module PDVDD_18_18_NT_DR_H ( + input logic SNS, + input logic RTO +); +endmodule: PDVDD_18_18_NT_DR_H + +module PDVDD_18_18_NT_DR_V ( + input logic SNS, + input logic RTO +); +endmodule: PDVDD_18_18_NT_DR_V + +module PDVSS_18_18_NT_DR_H ( + input logic SNS, + input logic RTO +); +endmodule: PDVSS_18_18_NT_DR_H + +module PDVSS_18_18_NT_DR_V ( + input logic SNS, + input logic RTO +); +endmodule: PDVSS_18_18_NT_DR_V + +module PCORNER_18_18_NT_DR ( + input logic SNS, + input logic RTO +); +endmodule: PCORNER_18_18_NT_DR + + +module POSCP_18_18_NT_DR_H ( + output logic CK, + output logic CK_IOV, + output logic PO, + input logic PADO, + input logic E0, + input logic PADI, + input logic POE, + input logic RTO, + input logic SF0, + input logic SF1, + input logic SNS, + input logic SP, + input logic TE +); + + buf(CK, PADI); + buf(CK_IOV, PADI); + +endmodule: POSCP_18_18_NT_DR_H + +module PBIDIR_18_18_NT_DR_H ( + output logic PO, + output logic Y, + inout logic PAD, + input logic A, + input logic DS0, + input logic DS1, + input logic IE, + input logic IS, + input logic OE, + input logic PE, + input logic POE, + input logic PS, + input logic RTO, + input logic SNS, + input logic SR +); + + bufif1 (PAD, A, OE); + bufif1 (Y, PAD, IE); + +endmodule: PBIDIR_18_18_NT_DR_H + +module PBIDIR_18_18_NT_DR_V ( + output logic PO, + output logic Y, + inout logic PAD, + input logic A, + input logic DS0, + input logic DS1, + input logic IE, + input logic IS, + input logic OE, + input logic PE, + input logic POE, + input logic PS, + input logic RTO, + input logic SNS, + input logic SR +); + + bufif1 (PAD, A, OE); + bufif1 (Y, PAD, IE); + +endmodule: PBIDIR_18_18_NT_DR_V diff --git a/hw/padframe/padrick b/hw/padframe/padrick new file mode 100755 index 00000000..1e5ad35b Binary files /dev/null and b/hw/padframe/padrick differ diff --git a/hw/regs/carfield_reg_pkg.sv b/hw/regs/carfield_reg_pkg.sv index 6f9836e8..6ac16530 100644 --- a/hw/regs/carfield_reg_pkg.sv +++ b/hw/regs/carfield_reg_pkg.sv @@ -7,7 +7,7 @@ package carfield_reg_pkg; // Address widths within the block - parameter int BlockAw = 8; + parameter int BlockAw = 9; //////////////////////////// // Typedefs for registers // @@ -227,6 +227,16 @@ package carfield_reg_pkg; logic qe; } carfield_reg2hw_hyperbus_clk_div_value_reg_t; + typedef struct packed { + logic q; + logic qe; + } carfield_reg2hw_streamer_clk_div_enable_reg_t; + + typedef struct packed { + logic [5:0] q; + logic qe; + } carfield_reg2hw_streamer_clk_div_value_reg_t; + typedef struct packed { logic [31:0] d; logic de; @@ -282,140 +292,158 @@ package carfield_reg_pkg; logic de; } carfield_hw2reg_pulp_cluster_eoc_reg_t; + typedef struct packed { + logic d; + logic de; + } carfield_hw2reg_streamer_general_irq_reg_t; + + typedef struct packed { + logic d; + logic de; + } carfield_hw2reg_spw_general_irq_reg_t; + // Register -> HW type typedef struct packed { - carfield_reg2hw_generic_scratch0_reg_t generic_scratch0; // [460:429] - carfield_reg2hw_generic_scratch1_reg_t generic_scratch1; // [428:397] - carfield_reg2hw_host_rst_reg_t host_rst; // [396:396] - carfield_reg2hw_periph_rst_reg_t periph_rst; // [395:395] - carfield_reg2hw_safety_island_rst_reg_t safety_island_rst; // [394:394] - carfield_reg2hw_security_island_rst_reg_t security_island_rst; // [393:393] - carfield_reg2hw_pulp_cluster_rst_reg_t pulp_cluster_rst; // [392:392] - carfield_reg2hw_spatz_cluster_rst_reg_t spatz_cluster_rst; // [391:391] - carfield_reg2hw_l2_rst_reg_t l2_rst; // [390:390] - carfield_reg2hw_periph_isolate_reg_t periph_isolate; // [389:389] - carfield_reg2hw_safety_island_isolate_reg_t safety_island_isolate; // [388:388] - carfield_reg2hw_security_island_isolate_reg_t security_island_isolate; // [387:387] - carfield_reg2hw_pulp_cluster_isolate_reg_t pulp_cluster_isolate; // [386:386] - carfield_reg2hw_spatz_cluster_isolate_reg_t spatz_cluster_isolate; // [385:385] - carfield_reg2hw_l2_isolate_reg_t l2_isolate; // [384:384] - carfield_reg2hw_periph_clk_en_reg_t periph_clk_en; // [383:383] - carfield_reg2hw_safety_island_clk_en_reg_t safety_island_clk_en; // [382:382] - carfield_reg2hw_security_island_clk_en_reg_t security_island_clk_en; // [381:381] - carfield_reg2hw_pulp_cluster_clk_en_reg_t pulp_cluster_clk_en; // [380:380] - carfield_reg2hw_spatz_cluster_clk_en_reg_t spatz_cluster_clk_en; // [379:379] - carfield_reg2hw_l2_clk_en_reg_t l2_clk_en; // [378:378] - carfield_reg2hw_periph_clk_sel_reg_t periph_clk_sel; // [377:376] - carfield_reg2hw_safety_island_clk_sel_reg_t safety_island_clk_sel; // [375:374] - carfield_reg2hw_security_island_clk_sel_reg_t security_island_clk_sel; // [373:372] - carfield_reg2hw_pulp_cluster_clk_sel_reg_t pulp_cluster_clk_sel; // [371:370] - carfield_reg2hw_spatz_cluster_clk_sel_reg_t spatz_cluster_clk_sel; // [369:368] - carfield_reg2hw_l2_clk_sel_reg_t l2_clk_sel; // [367:366] - carfield_reg2hw_periph_clk_div_value_reg_t periph_clk_div_value; // [365:341] - carfield_reg2hw_safety_island_clk_div_value_reg_t safety_island_clk_div_value; // [340:316] - carfield_reg2hw_security_island_clk_div_value_reg_t security_island_clk_div_value; // [315:291] - carfield_reg2hw_pulp_cluster_clk_div_value_reg_t pulp_cluster_clk_div_value; // [290:266] - carfield_reg2hw_spatz_cluster_clk_div_value_reg_t spatz_cluster_clk_div_value; // [265:241] - carfield_reg2hw_l2_clk_div_value_reg_t l2_clk_div_value; // [240:216] - carfield_reg2hw_host_fetch_enable_reg_t host_fetch_enable; // [215:215] - carfield_reg2hw_safety_island_fetch_enable_reg_t safety_island_fetch_enable; // [214:214] - carfield_reg2hw_security_island_fetch_enable_reg_t security_island_fetch_enable; // [213:213] - carfield_reg2hw_pulp_cluster_fetch_enable_reg_t pulp_cluster_fetch_enable; // [212:212] - carfield_reg2hw_spatz_cluster_debug_req_reg_t spatz_cluster_debug_req; // [211:210] - carfield_reg2hw_host_boot_addr_reg_t host_boot_addr; // [209:178] - carfield_reg2hw_safety_island_boot_addr_reg_t safety_island_boot_addr; // [177:146] - carfield_reg2hw_security_island_boot_addr_reg_t security_island_boot_addr; // [145:114] - carfield_reg2hw_pulp_cluster_boot_addr_reg_t pulp_cluster_boot_addr; // [113:82] - carfield_reg2hw_spatz_cluster_boot_addr_reg_t spatz_cluster_boot_addr; // [81:50] - carfield_reg2hw_pulp_cluster_boot_enable_reg_t pulp_cluster_boot_enable; // [49:49] - carfield_reg2hw_spatz_cluster_busy_reg_t spatz_cluster_busy; // [48:48] - carfield_reg2hw_pulp_cluster_busy_reg_t pulp_cluster_busy; // [47:47] - carfield_reg2hw_pulp_cluster_eoc_reg_t pulp_cluster_eoc; // [46:46] - carfield_reg2hw_eth_clk_div_en_reg_t eth_clk_div_en; // [45:44] - carfield_reg2hw_eth_clk_div_value_reg_t eth_clk_div_value; // [43:23] - carfield_reg2hw_hyperbus_clk_div_en_reg_t hyperbus_clk_div_en; // [22:21] - carfield_reg2hw_hyperbus_clk_div_value_reg_t hyperbus_clk_div_value; // [20:0] + carfield_reg2hw_generic_scratch0_reg_t generic_scratch0; // [469:438] + carfield_reg2hw_generic_scratch1_reg_t generic_scratch1; // [437:406] + carfield_reg2hw_host_rst_reg_t host_rst; // [405:405] + carfield_reg2hw_periph_rst_reg_t periph_rst; // [404:404] + carfield_reg2hw_safety_island_rst_reg_t safety_island_rst; // [403:403] + carfield_reg2hw_security_island_rst_reg_t security_island_rst; // [402:402] + carfield_reg2hw_pulp_cluster_rst_reg_t pulp_cluster_rst; // [401:401] + carfield_reg2hw_spatz_cluster_rst_reg_t spatz_cluster_rst; // [400:400] + carfield_reg2hw_l2_rst_reg_t l2_rst; // [399:399] + carfield_reg2hw_periph_isolate_reg_t periph_isolate; // [398:398] + carfield_reg2hw_safety_island_isolate_reg_t safety_island_isolate; // [397:397] + carfield_reg2hw_security_island_isolate_reg_t security_island_isolate; // [396:396] + carfield_reg2hw_pulp_cluster_isolate_reg_t pulp_cluster_isolate; // [395:395] + carfield_reg2hw_spatz_cluster_isolate_reg_t spatz_cluster_isolate; // [394:394] + carfield_reg2hw_l2_isolate_reg_t l2_isolate; // [393:393] + carfield_reg2hw_periph_clk_en_reg_t periph_clk_en; // [392:392] + carfield_reg2hw_safety_island_clk_en_reg_t safety_island_clk_en; // [391:391] + carfield_reg2hw_security_island_clk_en_reg_t security_island_clk_en; // [390:390] + carfield_reg2hw_pulp_cluster_clk_en_reg_t pulp_cluster_clk_en; // [389:389] + carfield_reg2hw_spatz_cluster_clk_en_reg_t spatz_cluster_clk_en; // [388:388] + carfield_reg2hw_l2_clk_en_reg_t l2_clk_en; // [387:387] + carfield_reg2hw_periph_clk_sel_reg_t periph_clk_sel; // [386:385] + carfield_reg2hw_safety_island_clk_sel_reg_t safety_island_clk_sel; // [384:383] + carfield_reg2hw_security_island_clk_sel_reg_t security_island_clk_sel; // [382:381] + carfield_reg2hw_pulp_cluster_clk_sel_reg_t pulp_cluster_clk_sel; // [380:379] + carfield_reg2hw_spatz_cluster_clk_sel_reg_t spatz_cluster_clk_sel; // [378:377] + carfield_reg2hw_l2_clk_sel_reg_t l2_clk_sel; // [376:375] + carfield_reg2hw_periph_clk_div_value_reg_t periph_clk_div_value; // [374:350] + carfield_reg2hw_safety_island_clk_div_value_reg_t safety_island_clk_div_value; // [349:325] + carfield_reg2hw_security_island_clk_div_value_reg_t security_island_clk_div_value; // [324:300] + carfield_reg2hw_pulp_cluster_clk_div_value_reg_t pulp_cluster_clk_div_value; // [299:275] + carfield_reg2hw_spatz_cluster_clk_div_value_reg_t spatz_cluster_clk_div_value; // [274:250] + carfield_reg2hw_l2_clk_div_value_reg_t l2_clk_div_value; // [249:225] + carfield_reg2hw_host_fetch_enable_reg_t host_fetch_enable; // [224:224] + carfield_reg2hw_safety_island_fetch_enable_reg_t safety_island_fetch_enable; // [223:223] + carfield_reg2hw_security_island_fetch_enable_reg_t security_island_fetch_enable; // [222:222] + carfield_reg2hw_pulp_cluster_fetch_enable_reg_t pulp_cluster_fetch_enable; // [221:221] + carfield_reg2hw_spatz_cluster_debug_req_reg_t spatz_cluster_debug_req; // [220:219] + carfield_reg2hw_host_boot_addr_reg_t host_boot_addr; // [218:187] + carfield_reg2hw_safety_island_boot_addr_reg_t safety_island_boot_addr; // [186:155] + carfield_reg2hw_security_island_boot_addr_reg_t security_island_boot_addr; // [154:123] + carfield_reg2hw_pulp_cluster_boot_addr_reg_t pulp_cluster_boot_addr; // [122:91] + carfield_reg2hw_spatz_cluster_boot_addr_reg_t spatz_cluster_boot_addr; // [90:59] + carfield_reg2hw_pulp_cluster_boot_enable_reg_t pulp_cluster_boot_enable; // [58:58] + carfield_reg2hw_spatz_cluster_busy_reg_t spatz_cluster_busy; // [57:57] + carfield_reg2hw_pulp_cluster_busy_reg_t pulp_cluster_busy; // [56:56] + carfield_reg2hw_pulp_cluster_eoc_reg_t pulp_cluster_eoc; // [55:55] + carfield_reg2hw_eth_clk_div_en_reg_t eth_clk_div_en; // [54:53] + carfield_reg2hw_eth_clk_div_value_reg_t eth_clk_div_value; // [52:32] + carfield_reg2hw_hyperbus_clk_div_en_reg_t hyperbus_clk_div_en; // [31:30] + carfield_reg2hw_hyperbus_clk_div_value_reg_t hyperbus_clk_div_value; // [29:9] + carfield_reg2hw_streamer_clk_div_enable_reg_t streamer_clk_div_enable; // [8:7] + carfield_reg2hw_streamer_clk_div_value_reg_t streamer_clk_div_value; // [6:0] } carfield_reg2hw_t; // HW -> register type typedef struct packed { - carfield_hw2reg_generic_scratch0_reg_t generic_scratch0; // [83:51] - carfield_hw2reg_generic_scratch1_reg_t generic_scratch1; // [50:18] - carfield_hw2reg_periph_isolate_status_reg_t periph_isolate_status; // [17:16] - carfield_hw2reg_safety_island_isolate_status_reg_t safety_island_isolate_status; // [15:14] - carfield_hw2reg_security_island_isolate_status_reg_t security_island_isolate_status; // [13:12] - carfield_hw2reg_pulp_cluster_isolate_status_reg_t pulp_cluster_isolate_status; // [11:10] - carfield_hw2reg_spatz_cluster_isolate_status_reg_t spatz_cluster_isolate_status; // [9:8] - carfield_hw2reg_l2_isolate_status_reg_t l2_isolate_status; // [7:6] - carfield_hw2reg_spatz_cluster_busy_reg_t spatz_cluster_busy; // [5:4] - carfield_hw2reg_pulp_cluster_busy_reg_t pulp_cluster_busy; // [3:2] - carfield_hw2reg_pulp_cluster_eoc_reg_t pulp_cluster_eoc; // [1:0] + carfield_hw2reg_generic_scratch0_reg_t generic_scratch0; // [87:55] + carfield_hw2reg_generic_scratch1_reg_t generic_scratch1; // [54:22] + carfield_hw2reg_periph_isolate_status_reg_t periph_isolate_status; // [21:20] + carfield_hw2reg_safety_island_isolate_status_reg_t safety_island_isolate_status; // [19:18] + carfield_hw2reg_security_island_isolate_status_reg_t security_island_isolate_status; // [17:16] + carfield_hw2reg_pulp_cluster_isolate_status_reg_t pulp_cluster_isolate_status; // [15:14] + carfield_hw2reg_spatz_cluster_isolate_status_reg_t spatz_cluster_isolate_status; // [13:12] + carfield_hw2reg_l2_isolate_status_reg_t l2_isolate_status; // [11:10] + carfield_hw2reg_spatz_cluster_busy_reg_t spatz_cluster_busy; // [9:8] + carfield_hw2reg_pulp_cluster_busy_reg_t pulp_cluster_busy; // [7:6] + carfield_hw2reg_pulp_cluster_eoc_reg_t pulp_cluster_eoc; // [5:4] + carfield_hw2reg_streamer_general_irq_reg_t streamer_general_irq; // [3:2] + carfield_hw2reg_spw_general_irq_reg_t spw_general_irq; // [1:0] } carfield_hw2reg_t; // Register offsets - parameter logic [BlockAw-1:0] CARFIELD_VERSION0_OFFSET = 8'h 0; - parameter logic [BlockAw-1:0] CARFIELD_VERSION1_OFFSET = 8'h 4; - parameter logic [BlockAw-1:0] CARFIELD_VERSION2_OFFSET = 8'h 8; - parameter logic [BlockAw-1:0] CARFIELD_VERSION3_OFFSET = 8'h c; - parameter logic [BlockAw-1:0] CARFIELD_VERSION4_OFFSET = 8'h 10; - parameter logic [BlockAw-1:0] CARFIELD_JEDEC_IDCODE_OFFSET = 8'h 14; - parameter logic [BlockAw-1:0] CARFIELD_GENERIC_SCRATCH0_OFFSET = 8'h 18; - parameter logic [BlockAw-1:0] CARFIELD_GENERIC_SCRATCH1_OFFSET = 8'h 1c; - parameter logic [BlockAw-1:0] CARFIELD_HOST_RST_OFFSET = 8'h 20; - parameter logic [BlockAw-1:0] CARFIELD_PERIPH_RST_OFFSET = 8'h 24; - parameter logic [BlockAw-1:0] CARFIELD_SAFETY_ISLAND_RST_OFFSET = 8'h 28; - parameter logic [BlockAw-1:0] CARFIELD_SECURITY_ISLAND_RST_OFFSET = 8'h 2c; - parameter logic [BlockAw-1:0] CARFIELD_PULP_CLUSTER_RST_OFFSET = 8'h 30; - parameter logic [BlockAw-1:0] CARFIELD_SPATZ_CLUSTER_RST_OFFSET = 8'h 34; - parameter logic [BlockAw-1:0] CARFIELD_L2_RST_OFFSET = 8'h 38; - parameter logic [BlockAw-1:0] CARFIELD_PERIPH_ISOLATE_OFFSET = 8'h 3c; - parameter logic [BlockAw-1:0] CARFIELD_SAFETY_ISLAND_ISOLATE_OFFSET = 8'h 40; - parameter logic [BlockAw-1:0] CARFIELD_SECURITY_ISLAND_ISOLATE_OFFSET = 8'h 44; - parameter logic [BlockAw-1:0] CARFIELD_PULP_CLUSTER_ISOLATE_OFFSET = 8'h 48; - parameter logic [BlockAw-1:0] CARFIELD_SPATZ_CLUSTER_ISOLATE_OFFSET = 8'h 4c; - parameter logic [BlockAw-1:0] CARFIELD_L2_ISOLATE_OFFSET = 8'h 50; - parameter logic [BlockAw-1:0] CARFIELD_PERIPH_ISOLATE_STATUS_OFFSET = 8'h 54; - parameter logic [BlockAw-1:0] CARFIELD_SAFETY_ISLAND_ISOLATE_STATUS_OFFSET = 8'h 58; - parameter logic [BlockAw-1:0] CARFIELD_SECURITY_ISLAND_ISOLATE_STATUS_OFFSET = 8'h 5c; - parameter logic [BlockAw-1:0] CARFIELD_PULP_CLUSTER_ISOLATE_STATUS_OFFSET = 8'h 60; - parameter logic [BlockAw-1:0] CARFIELD_SPATZ_CLUSTER_ISOLATE_STATUS_OFFSET = 8'h 64; - parameter logic [BlockAw-1:0] CARFIELD_L2_ISOLATE_STATUS_OFFSET = 8'h 68; - parameter logic [BlockAw-1:0] CARFIELD_PERIPH_CLK_EN_OFFSET = 8'h 6c; - parameter logic [BlockAw-1:0] CARFIELD_SAFETY_ISLAND_CLK_EN_OFFSET = 8'h 70; - parameter logic [BlockAw-1:0] CARFIELD_SECURITY_ISLAND_CLK_EN_OFFSET = 8'h 74; - parameter logic [BlockAw-1:0] CARFIELD_PULP_CLUSTER_CLK_EN_OFFSET = 8'h 78; - parameter logic [BlockAw-1:0] CARFIELD_SPATZ_CLUSTER_CLK_EN_OFFSET = 8'h 7c; - parameter logic [BlockAw-1:0] CARFIELD_L2_CLK_EN_OFFSET = 8'h 80; - parameter logic [BlockAw-1:0] CARFIELD_PERIPH_CLK_SEL_OFFSET = 8'h 84; - parameter logic [BlockAw-1:0] CARFIELD_SAFETY_ISLAND_CLK_SEL_OFFSET = 8'h 88; - parameter logic [BlockAw-1:0] CARFIELD_SECURITY_ISLAND_CLK_SEL_OFFSET = 8'h 8c; - parameter logic [BlockAw-1:0] CARFIELD_PULP_CLUSTER_CLK_SEL_OFFSET = 8'h 90; - parameter logic [BlockAw-1:0] CARFIELD_SPATZ_CLUSTER_CLK_SEL_OFFSET = 8'h 94; - parameter logic [BlockAw-1:0] CARFIELD_L2_CLK_SEL_OFFSET = 8'h 98; - parameter logic [BlockAw-1:0] CARFIELD_PERIPH_CLK_DIV_VALUE_OFFSET = 8'h 9c; - parameter logic [BlockAw-1:0] CARFIELD_SAFETY_ISLAND_CLK_DIV_VALUE_OFFSET = 8'h a0; - parameter logic [BlockAw-1:0] CARFIELD_SECURITY_ISLAND_CLK_DIV_VALUE_OFFSET = 8'h a4; - parameter logic [BlockAw-1:0] CARFIELD_PULP_CLUSTER_CLK_DIV_VALUE_OFFSET = 8'h a8; - parameter logic [BlockAw-1:0] CARFIELD_SPATZ_CLUSTER_CLK_DIV_VALUE_OFFSET = 8'h ac; - parameter logic [BlockAw-1:0] CARFIELD_L2_CLK_DIV_VALUE_OFFSET = 8'h b0; - parameter logic [BlockAw-1:0] CARFIELD_HOST_FETCH_ENABLE_OFFSET = 8'h b4; - parameter logic [BlockAw-1:0] CARFIELD_SAFETY_ISLAND_FETCH_ENABLE_OFFSET = 8'h b8; - parameter logic [BlockAw-1:0] CARFIELD_SECURITY_ISLAND_FETCH_ENABLE_OFFSET = 8'h bc; - parameter logic [BlockAw-1:0] CARFIELD_PULP_CLUSTER_FETCH_ENABLE_OFFSET = 8'h c0; - parameter logic [BlockAw-1:0] CARFIELD_SPATZ_CLUSTER_DEBUG_REQ_OFFSET = 8'h c4; - parameter logic [BlockAw-1:0] CARFIELD_HOST_BOOT_ADDR_OFFSET = 8'h c8; - parameter logic [BlockAw-1:0] CARFIELD_SAFETY_ISLAND_BOOT_ADDR_OFFSET = 8'h cc; - parameter logic [BlockAw-1:0] CARFIELD_SECURITY_ISLAND_BOOT_ADDR_OFFSET = 8'h d0; - parameter logic [BlockAw-1:0] CARFIELD_PULP_CLUSTER_BOOT_ADDR_OFFSET = 8'h d4; - parameter logic [BlockAw-1:0] CARFIELD_SPATZ_CLUSTER_BOOT_ADDR_OFFSET = 8'h d8; - parameter logic [BlockAw-1:0] CARFIELD_PULP_CLUSTER_BOOT_ENABLE_OFFSET = 8'h dc; - parameter logic [BlockAw-1:0] CARFIELD_SPATZ_CLUSTER_BUSY_OFFSET = 8'h e0; - parameter logic [BlockAw-1:0] CARFIELD_PULP_CLUSTER_BUSY_OFFSET = 8'h e4; - parameter logic [BlockAw-1:0] CARFIELD_PULP_CLUSTER_EOC_OFFSET = 8'h e8; - parameter logic [BlockAw-1:0] CARFIELD_ETH_CLK_DIV_EN_OFFSET = 8'h ec; - parameter logic [BlockAw-1:0] CARFIELD_ETH_CLK_DIV_VALUE_OFFSET = 8'h f0; - parameter logic [BlockAw-1:0] CARFIELD_HYPERBUS_CLK_DIV_EN_OFFSET = 8'h f4; - parameter logic [BlockAw-1:0] CARFIELD_HYPERBUS_CLK_DIV_VALUE_OFFSET = 8'h f8; + parameter logic [BlockAw-1:0] CARFIELD_VERSION0_OFFSET = 9'h 0; + parameter logic [BlockAw-1:0] CARFIELD_VERSION1_OFFSET = 9'h 4; + parameter logic [BlockAw-1:0] CARFIELD_VERSION2_OFFSET = 9'h 8; + parameter logic [BlockAw-1:0] CARFIELD_VERSION3_OFFSET = 9'h c; + parameter logic [BlockAw-1:0] CARFIELD_VERSION4_OFFSET = 9'h 10; + parameter logic [BlockAw-1:0] CARFIELD_JEDEC_IDCODE_OFFSET = 9'h 14; + parameter logic [BlockAw-1:0] CARFIELD_GENERIC_SCRATCH0_OFFSET = 9'h 18; + parameter logic [BlockAw-1:0] CARFIELD_GENERIC_SCRATCH1_OFFSET = 9'h 1c; + parameter logic [BlockAw-1:0] CARFIELD_HOST_RST_OFFSET = 9'h 20; + parameter logic [BlockAw-1:0] CARFIELD_PERIPH_RST_OFFSET = 9'h 24; + parameter logic [BlockAw-1:0] CARFIELD_SAFETY_ISLAND_RST_OFFSET = 9'h 28; + parameter logic [BlockAw-1:0] CARFIELD_SECURITY_ISLAND_RST_OFFSET = 9'h 2c; + parameter logic [BlockAw-1:0] CARFIELD_PULP_CLUSTER_RST_OFFSET = 9'h 30; + parameter logic [BlockAw-1:0] CARFIELD_SPATZ_CLUSTER_RST_OFFSET = 9'h 34; + parameter logic [BlockAw-1:0] CARFIELD_L2_RST_OFFSET = 9'h 38; + parameter logic [BlockAw-1:0] CARFIELD_PERIPH_ISOLATE_OFFSET = 9'h 3c; + parameter logic [BlockAw-1:0] CARFIELD_SAFETY_ISLAND_ISOLATE_OFFSET = 9'h 40; + parameter logic [BlockAw-1:0] CARFIELD_SECURITY_ISLAND_ISOLATE_OFFSET = 9'h 44; + parameter logic [BlockAw-1:0] CARFIELD_PULP_CLUSTER_ISOLATE_OFFSET = 9'h 48; + parameter logic [BlockAw-1:0] CARFIELD_SPATZ_CLUSTER_ISOLATE_OFFSET = 9'h 4c; + parameter logic [BlockAw-1:0] CARFIELD_L2_ISOLATE_OFFSET = 9'h 50; + parameter logic [BlockAw-1:0] CARFIELD_PERIPH_ISOLATE_STATUS_OFFSET = 9'h 54; + parameter logic [BlockAw-1:0] CARFIELD_SAFETY_ISLAND_ISOLATE_STATUS_OFFSET = 9'h 58; + parameter logic [BlockAw-1:0] CARFIELD_SECURITY_ISLAND_ISOLATE_STATUS_OFFSET = 9'h 5c; + parameter logic [BlockAw-1:0] CARFIELD_PULP_CLUSTER_ISOLATE_STATUS_OFFSET = 9'h 60; + parameter logic [BlockAw-1:0] CARFIELD_SPATZ_CLUSTER_ISOLATE_STATUS_OFFSET = 9'h 64; + parameter logic [BlockAw-1:0] CARFIELD_L2_ISOLATE_STATUS_OFFSET = 9'h 68; + parameter logic [BlockAw-1:0] CARFIELD_PERIPH_CLK_EN_OFFSET = 9'h 6c; + parameter logic [BlockAw-1:0] CARFIELD_SAFETY_ISLAND_CLK_EN_OFFSET = 9'h 70; + parameter logic [BlockAw-1:0] CARFIELD_SECURITY_ISLAND_CLK_EN_OFFSET = 9'h 74; + parameter logic [BlockAw-1:0] CARFIELD_PULP_CLUSTER_CLK_EN_OFFSET = 9'h 78; + parameter logic [BlockAw-1:0] CARFIELD_SPATZ_CLUSTER_CLK_EN_OFFSET = 9'h 7c; + parameter logic [BlockAw-1:0] CARFIELD_L2_CLK_EN_OFFSET = 9'h 80; + parameter logic [BlockAw-1:0] CARFIELD_PERIPH_CLK_SEL_OFFSET = 9'h 84; + parameter logic [BlockAw-1:0] CARFIELD_SAFETY_ISLAND_CLK_SEL_OFFSET = 9'h 88; + parameter logic [BlockAw-1:0] CARFIELD_SECURITY_ISLAND_CLK_SEL_OFFSET = 9'h 8c; + parameter logic [BlockAw-1:0] CARFIELD_PULP_CLUSTER_CLK_SEL_OFFSET = 9'h 90; + parameter logic [BlockAw-1:0] CARFIELD_SPATZ_CLUSTER_CLK_SEL_OFFSET = 9'h 94; + parameter logic [BlockAw-1:0] CARFIELD_L2_CLK_SEL_OFFSET = 9'h 98; + parameter logic [BlockAw-1:0] CARFIELD_PERIPH_CLK_DIV_VALUE_OFFSET = 9'h 9c; + parameter logic [BlockAw-1:0] CARFIELD_SAFETY_ISLAND_CLK_DIV_VALUE_OFFSET = 9'h a0; + parameter logic [BlockAw-1:0] CARFIELD_SECURITY_ISLAND_CLK_DIV_VALUE_OFFSET = 9'h a4; + parameter logic [BlockAw-1:0] CARFIELD_PULP_CLUSTER_CLK_DIV_VALUE_OFFSET = 9'h a8; + parameter logic [BlockAw-1:0] CARFIELD_SPATZ_CLUSTER_CLK_DIV_VALUE_OFFSET = 9'h ac; + parameter logic [BlockAw-1:0] CARFIELD_L2_CLK_DIV_VALUE_OFFSET = 9'h b0; + parameter logic [BlockAw-1:0] CARFIELD_HOST_FETCH_ENABLE_OFFSET = 9'h b4; + parameter logic [BlockAw-1:0] CARFIELD_SAFETY_ISLAND_FETCH_ENABLE_OFFSET = 9'h b8; + parameter logic [BlockAw-1:0] CARFIELD_SECURITY_ISLAND_FETCH_ENABLE_OFFSET = 9'h bc; + parameter logic [BlockAw-1:0] CARFIELD_PULP_CLUSTER_FETCH_ENABLE_OFFSET = 9'h c0; + parameter logic [BlockAw-1:0] CARFIELD_SPATZ_CLUSTER_DEBUG_REQ_OFFSET = 9'h c4; + parameter logic [BlockAw-1:0] CARFIELD_HOST_BOOT_ADDR_OFFSET = 9'h c8; + parameter logic [BlockAw-1:0] CARFIELD_SAFETY_ISLAND_BOOT_ADDR_OFFSET = 9'h cc; + parameter logic [BlockAw-1:0] CARFIELD_SECURITY_ISLAND_BOOT_ADDR_OFFSET = 9'h d0; + parameter logic [BlockAw-1:0] CARFIELD_PULP_CLUSTER_BOOT_ADDR_OFFSET = 9'h d4; + parameter logic [BlockAw-1:0] CARFIELD_SPATZ_CLUSTER_BOOT_ADDR_OFFSET = 9'h d8; + parameter logic [BlockAw-1:0] CARFIELD_PULP_CLUSTER_BOOT_ENABLE_OFFSET = 9'h dc; + parameter logic [BlockAw-1:0] CARFIELD_SPATZ_CLUSTER_BUSY_OFFSET = 9'h e0; + parameter logic [BlockAw-1:0] CARFIELD_PULP_CLUSTER_BUSY_OFFSET = 9'h e4; + parameter logic [BlockAw-1:0] CARFIELD_PULP_CLUSTER_EOC_OFFSET = 9'h e8; + parameter logic [BlockAw-1:0] CARFIELD_ETH_CLK_DIV_EN_OFFSET = 9'h ec; + parameter logic [BlockAw-1:0] CARFIELD_ETH_CLK_DIV_VALUE_OFFSET = 9'h f0; + parameter logic [BlockAw-1:0] CARFIELD_HYPERBUS_CLK_DIV_EN_OFFSET = 9'h f4; + parameter logic [BlockAw-1:0] CARFIELD_HYPERBUS_CLK_DIV_VALUE_OFFSET = 9'h f8; + parameter logic [BlockAw-1:0] CARFIELD_STREAMER_CLK_DIV_ENABLE_OFFSET = 9'h fc; + parameter logic [BlockAw-1:0] CARFIELD_STREAMER_CLK_DIV_VALUE_OFFSET = 9'h 100; + parameter logic [BlockAw-1:0] CARFIELD_STREAMER_GENERAL_IRQ_OFFSET = 9'h 104; + parameter logic [BlockAw-1:0] CARFIELD_SPW_GENERAL_IRQ_OFFSET = 9'h 108; // Register index typedef enum int { @@ -481,11 +509,15 @@ package carfield_reg_pkg; CARFIELD_ETH_CLK_DIV_EN, CARFIELD_ETH_CLK_DIV_VALUE, CARFIELD_HYPERBUS_CLK_DIV_EN, - CARFIELD_HYPERBUS_CLK_DIV_VALUE + CARFIELD_HYPERBUS_CLK_DIV_VALUE, + CARFIELD_STREAMER_CLK_DIV_ENABLE, + CARFIELD_STREAMER_CLK_DIV_VALUE, + CARFIELD_STREAMER_GENERAL_IRQ, + CARFIELD_SPW_GENERAL_IRQ } carfield_id_e; // Register width information to check illegal writes - parameter logic [3:0] CARFIELD_PERMIT [63] = '{ + parameter logic [3:0] CARFIELD_PERMIT [67] = '{ 4'b 1111, // index[ 0] CARFIELD_VERSION0 4'b 1111, // index[ 1] CARFIELD_VERSION1 4'b 1111, // index[ 2] CARFIELD_VERSION2 @@ -548,7 +580,11 @@ package carfield_reg_pkg; 4'b 0001, // index[59] CARFIELD_ETH_CLK_DIV_EN 4'b 0111, // index[60] CARFIELD_ETH_CLK_DIV_VALUE 4'b 0001, // index[61] CARFIELD_HYPERBUS_CLK_DIV_EN - 4'b 0111 // index[62] CARFIELD_HYPERBUS_CLK_DIV_VALUE + 4'b 0111, // index[62] CARFIELD_HYPERBUS_CLK_DIV_VALUE + 4'b 0001, // index[63] CARFIELD_STREAMER_CLK_DIV_ENABLE + 4'b 0001, // index[64] CARFIELD_STREAMER_CLK_DIV_VALUE + 4'b 0001, // index[65] CARFIELD_STREAMER_GENERAL_IRQ + 4'b 0001 // index[66] CARFIELD_SPW_GENERAL_IRQ }; endpackage diff --git a/hw/regs/carfield_reg_top.sv b/hw/regs/carfield_reg_top.sv index 801f53ed..84362016 100644 --- a/hw/regs/carfield_reg_top.sv +++ b/hw/regs/carfield_reg_top.sv @@ -10,7 +10,7 @@ module carfield_reg_top #( parameter type reg_req_t = logic, parameter type reg_rsp_t = logic, - parameter int AW = 8 + parameter int AW = 9 ) ( input logic clk_i, input logic rst_ni, @@ -237,6 +237,18 @@ module carfield_reg_top #( logic [19:0] hyperbus_clk_div_value_qs; logic [19:0] hyperbus_clk_div_value_wd; logic hyperbus_clk_div_value_we; + logic streamer_clk_div_enable_qs; + logic streamer_clk_div_enable_wd; + logic streamer_clk_div_enable_we; + logic [5:0] streamer_clk_div_value_qs; + logic [5:0] streamer_clk_div_value_wd; + logic streamer_clk_div_value_we; + logic streamer_general_irq_qs; + logic streamer_general_irq_wd; + logic streamer_general_irq_we; + logic spw_general_irq_qs; + logic spw_general_irq_wd; + logic spw_general_irq_we; // Register instances // R[version0]: V(False) @@ -1083,7 +1095,7 @@ module carfield_reg_top #( prim_subreg #( .DW (2), .SWACCESS("RW"), - .RESVAL (2'h1) + .RESVAL (2'h3) ) u_security_island_clk_sel ( .clk_i (clk_i ), .rst_ni (rst_ni ), @@ -1830,9 +1842,117 @@ module carfield_reg_top #( ); + // R[streamer_clk_div_enable]: V(False) + + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_streamer_clk_div_enable ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (streamer_clk_div_enable_we), + .wd (streamer_clk_div_enable_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (reg2hw.streamer_clk_div_enable.qe), + .q (reg2hw.streamer_clk_div_enable.q ), + + // to register interface (read) + .qs (streamer_clk_div_enable_qs) + ); + + + // R[streamer_clk_div_value]: V(False) + + prim_subreg #( + .DW (6), + .SWACCESS("RW"), + .RESVAL (6'h1) + ) u_streamer_clk_div_value ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (streamer_clk_div_value_we), + .wd (streamer_clk_div_value_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (reg2hw.streamer_clk_div_value.qe), + .q (reg2hw.streamer_clk_div_value.q ), + + // to register interface (read) + .qs (streamer_clk_div_value_qs) + ); + + + // R[streamer_general_irq]: V(False) + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_streamer_general_irq ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), - logic [62:0] addr_hit; + // from register interface + .we (streamer_general_irq_we), + .wd (streamer_general_irq_wd), + + // from internal hardware + .de (hw2reg.streamer_general_irq.de), + .d (hw2reg.streamer_general_irq.d ), + + // to internal hardware + .qe (), + .q (), + + // to register interface (read) + .qs (streamer_general_irq_qs) + ); + + + // R[spw_general_irq]: V(False) + + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_spw_general_irq ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (spw_general_irq_we), + .wd (spw_general_irq_wd), + + // from internal hardware + .de (hw2reg.spw_general_irq.de), + .d (hw2reg.spw_general_irq.d ), + + // to internal hardware + .qe (), + .q (), + + // to register interface (read) + .qs (spw_general_irq_qs) + ); + + + + + logic [66:0] addr_hit; always_comb begin addr_hit = '0; addr_hit[ 0] = (reg_addr == CARFIELD_VERSION0_OFFSET); @@ -1898,6 +2018,10 @@ module carfield_reg_top #( addr_hit[60] = (reg_addr == CARFIELD_ETH_CLK_DIV_VALUE_OFFSET); addr_hit[61] = (reg_addr == CARFIELD_HYPERBUS_CLK_DIV_EN_OFFSET); addr_hit[62] = (reg_addr == CARFIELD_HYPERBUS_CLK_DIV_VALUE_OFFSET); + addr_hit[63] = (reg_addr == CARFIELD_STREAMER_CLK_DIV_ENABLE_OFFSET); + addr_hit[64] = (reg_addr == CARFIELD_STREAMER_CLK_DIV_VALUE_OFFSET); + addr_hit[65] = (reg_addr == CARFIELD_STREAMER_GENERAL_IRQ_OFFSET); + addr_hit[66] = (reg_addr == CARFIELD_SPW_GENERAL_IRQ_OFFSET); end assign addrmiss = (reg_re || reg_we) ? ~|addr_hit : 1'b0 ; @@ -1967,7 +2091,11 @@ module carfield_reg_top #( (addr_hit[59] & (|(CARFIELD_PERMIT[59] & ~reg_be))) | (addr_hit[60] & (|(CARFIELD_PERMIT[60] & ~reg_be))) | (addr_hit[61] & (|(CARFIELD_PERMIT[61] & ~reg_be))) | - (addr_hit[62] & (|(CARFIELD_PERMIT[62] & ~reg_be))))); + (addr_hit[62] & (|(CARFIELD_PERMIT[62] & ~reg_be))) | + (addr_hit[63] & (|(CARFIELD_PERMIT[63] & ~reg_be))) | + (addr_hit[64] & (|(CARFIELD_PERMIT[64] & ~reg_be))) | + (addr_hit[65] & (|(CARFIELD_PERMIT[65] & ~reg_be))) | + (addr_hit[66] & (|(CARFIELD_PERMIT[66] & ~reg_be))))); end assign jedec_idcode_we = addr_hit[5] & reg_we & !reg_error; @@ -2129,6 +2257,18 @@ module carfield_reg_top #( assign hyperbus_clk_div_value_we = addr_hit[62] & reg_we & !reg_error; assign hyperbus_clk_div_value_wd = reg_wdata[19:0]; + assign streamer_clk_div_enable_we = addr_hit[63] & reg_we & !reg_error; + assign streamer_clk_div_enable_wd = reg_wdata[0]; + + assign streamer_clk_div_value_we = addr_hit[64] & reg_we & !reg_error; + assign streamer_clk_div_value_wd = reg_wdata[5:0]; + + assign streamer_general_irq_we = addr_hit[65] & reg_we & !reg_error; + assign streamer_general_irq_wd = reg_wdata[0]; + + assign spw_general_irq_we = addr_hit[66] & reg_we & !reg_error; + assign spw_general_irq_wd = reg_wdata[0]; + // Read data return always_comb begin reg_rdata_next = '0; @@ -2385,6 +2525,22 @@ module carfield_reg_top #( reg_rdata_next[19:0] = hyperbus_clk_div_value_qs; end + addr_hit[63]: begin + reg_rdata_next[0] = streamer_clk_div_enable_qs; + end + + addr_hit[64]: begin + reg_rdata_next[5:0] = streamer_clk_div_value_qs; + end + + addr_hit[65]: begin + reg_rdata_next[0] = streamer_general_irq_qs; + end + + addr_hit[66]: begin + reg_rdata_next[0] = spw_general_irq_qs; + end + default: begin reg_rdata_next = '1; end @@ -2407,7 +2563,7 @@ endmodule module carfield_reg_top_intf #( - parameter int AW = 8, + parameter int AW = 9, localparam int DW = 32 ) ( input logic clk_i, diff --git a/hw/regs/carfield_regs.csv b/hw/regs/carfield_regs.csv index b7bb2e5e..c2d31b75 100644 --- a/hw/regs/carfield_regs.csv +++ b/hw/regs/carfield_regs.csv @@ -32,12 +32,12 @@ SECURITY_ISLAND_CLK_EN,1,rw,hro,0,0,Security Island clk gate enable PULP_CLUSTER_CLK_EN,1,rw,hro,0,0,PULP Cluster clk gate enable SPATZ_CLUSTER_CLK_EN,1,rw,hro,0,0,Spatz Cluster clk gate enable L2_CLK_EN,1,rw,hro,0,1,Shared L2 memory clk gate enable -PERIPH_CLK_SEL,2,rw,hro,0,2,"Periph Domain pll select (0 -> host pll, 1 -> alt PLL, 2 -> per pll)" -SAFETY_ISLAND_CLK_SEL,2,rw,hro,0,1,"Safety Island pll select (0 -> host pll, 1 -> alt PLL, 2 -> per pll)" -SECURITY_ISLAND_CLK_SEL,2,rw,hro,0,1,"Security Island pll select (0 -> host pll, 1 -> alt PLL, 2 -> per pll)" -PULP_CLUSTER_CLK_SEL,2,rw,hro,0,1,"PULP Cluster pll select (0 -> host pll, 1 -> alt PLL, 2 -> per pll)" -SPATZ_CLUSTER_CLK_SEL,2,rw,hro,0,1,"Spatz Cluster pll select (0 -> host pll, 1 -> alt PLL, 2 -> per pll)" -L2_CLK_SEL,2,rw,hro,0,1,"L2 Memory pll select (0 -> host pll, 1 -> alt PLL, 2 -> per pll)" +PERIPH_CLK_SEL,2,rw,hro,0,2,"Periph Domain fll select (0 -> host fll, 1 -> alt fll, 2 -> per fll, 3 -> secd fll)" +SAFETY_ISLAND_CLK_SEL,2,rw,hro,0,1,"Safety Island fll select (0 -> host fll, 1 -> alt fll, 2 -> per fll, 3 -> secd fll)" +SECURITY_ISLAND_CLK_SEL,2,rw,hro,0,3,"Security Island fll select (0 -> host fll, 1 -> alt fll, 2 -> per fll, 3 -> secd fll)" +PULP_CLUSTER_CLK_SEL,2,rw,hro,0,1,"PULP Cluster fll select (0 -> host fll, 1 -> alt fll, 2 -> per fll, 3 -> secd fll)" +SPATZ_CLUSTER_CLK_SEL,2,rw,hro,0,1,"Spatz Cluster fll select (0 -> host fll, 1 -> alt fll, 2 -> per fll, 3 -> secd fll)" +L2_CLK_SEL,2,rw,hro,0,1,"L2 Memory fll select (0 -> host fll, 1 -> alt fll, 2 -> per fll, 3 -> secd fll)" PERIPH_CLK_DIV_VALUE,24,rw,hro,1,1,Periph Domain clk divider value SAFETY_ISLAND_CLK_DIV_VALUE,24,rw,hro,1,1,Safety Island clk divider value SECURITY_ISLAND_CLK_DIV_VALUE,24,rw,hro,1,1,Security Island clk divider value @@ -62,3 +62,7 @@ ETH_CLK_DIV_EN,1,rw,hro,1,1,Ethernet clock divider enable bit ETH_CLK_DIV_VALUE,20,rw,hro,1,10,Ethernet clock divider value HYPERBUS_CLK_DIV_EN,1,rw,hro,1,1,Hyperbus clock divider enable bit HYPERBUS_CLK_DIV_VALUE,20,rw,hro,1,1,Hyperbus clock divider value +STREAMER_CLK_DIV_ENABLE,1,rw,hro,1,0,Streamer clock divider enable +STREAMER_CLK_DIV_VALUE,6,rw,hro,1,1,Streamer clock divider value +STREAMER_GENERAL_IRQ,1,rw,hwo,1,0,Streamer general interrupt +SPW_GENERAL_IRQ,1,rw,hwo,1,0,SpaceWire general interrupt \ No newline at end of file diff --git a/hw/regs/carfield_regs.hjson b/hw/regs/carfield_regs.hjson index a5f131ea..783bccfd 100644 --- a/hw/regs/carfield_regs.hjson +++ b/hw/regs/carfield_regs.hjson @@ -376,7 +376,7 @@ } { name: "PERIPH_CLK_SEL", - desc: "Periph Domain pll select (0 -> host pll, 1 -> alt PLL, 2 -> per pll)", + desc: "Periph Domain fll select (0 -> host fll, 1 -> alt fll, 2 -> per fll, 3 -> secd fll)", swaccess: "rw", hwaccess: "hro", resval: "2", @@ -387,7 +387,7 @@ } { name: "SAFETY_ISLAND_CLK_SEL", - desc: "Safety Island pll select (0 -> host pll, 1 -> alt PLL, 2 -> per pll)", + desc: "Safety Island fll select (0 -> host fll, 1 -> alt fll, 2 -> per fll, 3 -> secd fll)", swaccess: "rw", hwaccess: "hro", resval: "1", @@ -398,10 +398,10 @@ } { name: "SECURITY_ISLAND_CLK_SEL", - desc: "Security Island pll select (0 -> host pll, 1 -> alt PLL, 2 -> per pll)", + desc: "Security Island fll select (0 -> host fll, 1 -> alt fll, 2 -> per fll, 3 -> secd fll)", swaccess: "rw", hwaccess: "hro", - resval: "1", + resval: "3", hwqe: "0", fields: [ { bits: "1:0" } @@ -409,7 +409,7 @@ } { name: "PULP_CLUSTER_CLK_SEL", - desc: "PULP Cluster pll select (0 -> host pll, 1 -> alt PLL, 2 -> per pll)", + desc: "PULP Cluster fll select (0 -> host fll, 1 -> alt fll, 2 -> per fll, 3 -> secd fll)", swaccess: "rw", hwaccess: "hro", resval: "1", @@ -420,7 +420,7 @@ } { name: "SPATZ_CLUSTER_CLK_SEL", - desc: "Spatz Cluster pll select (0 -> host pll, 1 -> alt PLL, 2 -> per pll)", + desc: "Spatz Cluster fll select (0 -> host fll, 1 -> alt fll, 2 -> per fll, 3 -> secd fll)", swaccess: "rw", hwaccess: "hro", resval: "1", @@ -431,7 +431,7 @@ } { name: "L2_CLK_SEL", - desc: "L2 Memory pll select (0 -> host pll, 1 -> alt PLL, 2 -> per pll)", + desc: "L2 Memory fll select (0 -> host fll, 1 -> alt fll, 2 -> per fll, 3 -> secd fll)", swaccess: "rw", hwaccess: "hro", resval: "1", @@ -704,5 +704,49 @@ { bits: "19:0" } ], } + + { name: "STREAMER_CLK_DIV_ENABLE", + desc: "Streamer clock divider enable", + swaccess: "rw", + hwaccess: "hro", + resval: "0", + hwqe: "1", + fields: [ + { bits: "0:0" } + ], + } + + { name: "STREAMER_CLK_DIV_VALUE", + desc: "Streamer clock divider value", + swaccess: "rw", + hwaccess: "hro", + resval: "1", + hwqe: "1", + fields: [ + { bits: "5:0" } + ], + } + + { name: "STREAMER_GENERAL_IRQ", + desc: "Streamer general interrupt", + swaccess: "rw", + hwaccess: "hwo", + resval: "0", + hwqe: "1", + fields: [ + { bits: "0:0" } + ], + } + + { name: "SPW_GENERAL_IRQ", + desc: "SpaceWire general interrupt", + swaccess: "rw", + hwaccess: "hwo", + resval: "0", + hwqe: "1", + fields: [ + { bits: "0:0" } + ], + } ], } diff --git a/hw/regs/pcr.md b/hw/regs/pcr.md index babed51e..4766f20b 100644 --- a/hw/regs/pcr.md +++ b/hw/regs/pcr.md @@ -1,70 +1,74 @@ ## Summary -| Name | Offset | Length | Description | -|:-----------------------------------------------------------------------------|:---------|---------:|:-----------------------------------------------------------------------| -| carfield.[`VERSION0`](#version0) | 0x0 | 4 | Cheshire sha256 commit | -| carfield.[`VERSION1`](#version1) | 0x4 | 4 | Safety Island sha256 commit | -| carfield.[`VERSION2`](#version2) | 0x8 | 4 | Security Island sha256 commit | -| carfield.[`VERSION3`](#version3) | 0xc | 4 | PULP Cluster sha256 commit | -| carfield.[`VERSION4`](#version4) | 0x10 | 4 | Spatz CLuster sha256 commit | -| carfield.[`JEDEC_IDCODE`](#jedec_idcode) | 0x14 | 4 | JEDEC ID CODE -TODO assign- | -| carfield.[`GENERIC_SCRATCH0`](#generic_scratch0) | 0x18 | 4 | Scratch | -| carfield.[`GENERIC_SCRATCH1`](#generic_scratch1) | 0x1c | 4 | Scratch | -| carfield.[`HOST_RST`](#host_rst) | 0x20 | 4 | Host Domain reset -active high, inverted in HW- | -| carfield.[`PERIPH_RST`](#periph_rst) | 0x24 | 4 | Periph Domain reset -active high, inverted in HW- | -| carfield.[`SAFETY_ISLAND_RST`](#safety_island_rst) | 0x28 | 4 | Safety Island reset -active high, inverted in HW- | -| carfield.[`SECURITY_ISLAND_RST`](#security_island_rst) | 0x2c | 4 | Security Island reset -active high, inverted in HW- | -| carfield.[`PULP_CLUSTER_RST`](#pulp_cluster_rst) | 0x30 | 4 | PULP Cluster reset -active high, inverted in HW- | -| carfield.[`SPATZ_CLUSTER_RST`](#spatz_cluster_rst) | 0x34 | 4 | Spatz Cluster reset -active high, inverted in HW- | -| carfield.[`L2_RST`](#l2_rst) | 0x38 | 4 | L2 reset -active high, inverted in HW- | -| carfield.[`PERIPH_ISOLATE`](#periph_isolate) | 0x3c | 4 | Periph Domain AXI isolate | -| carfield.[`SAFETY_ISLAND_ISOLATE`](#safety_island_isolate) | 0x40 | 4 | Safety Island AXI isolate | -| carfield.[`SECURITY_ISLAND_ISOLATE`](#security_island_isolate) | 0x44 | 4 | Security Island AXI isolate | -| carfield.[`PULP_CLUSTER_ISOLATE`](#pulp_cluster_isolate) | 0x48 | 4 | PULP Cluster AXI isolate | -| carfield.[`SPATZ_CLUSTER_ISOLATE`](#spatz_cluster_isolate) | 0x4c | 4 | Spatz Cluster AXI isolate | -| carfield.[`L2_ISOLATE`](#l2_isolate) | 0x50 | 4 | L2 AXI isolate | -| carfield.[`PERIPH_ISOLATE_STATUS`](#periph_isolate_status) | 0x54 | 4 | Periph Domain AXI isolate status | -| carfield.[`SAFETY_ISLAND_ISOLATE_STATUS`](#safety_island_isolate_status) | 0x58 | 4 | Safety Island AXI isolate status | -| carfield.[`SECURITY_ISLAND_ISOLATE_STATUS`](#security_island_isolate_status) | 0x5c | 4 | Security Island AXI isolate status | -| carfield.[`PULP_CLUSTER_ISOLATE_STATUS`](#pulp_cluster_isolate_status) | 0x60 | 4 | PULP Cluster AXI isolate status | -| carfield.[`SPATZ_CLUSTER_ISOLATE_STATUS`](#spatz_cluster_isolate_status) | 0x64 | 4 | Spatz Cluster AXI isolate status | -| carfield.[`L2_ISOLATE_STATUS`](#l2_isolate_status) | 0x68 | 4 | L2 AXI isolate status | -| carfield.[`PERIPH_CLK_EN`](#periph_clk_en) | 0x6c | 4 | Periph Domain clk gate enable | -| carfield.[`SAFETY_ISLAND_CLK_EN`](#safety_island_clk_en) | 0x70 | 4 | Safety Island clk gate enable | -| carfield.[`SECURITY_ISLAND_CLK_EN`](#security_island_clk_en) | 0x74 | 4 | Security Island clk gate enable | -| carfield.[`PULP_CLUSTER_CLK_EN`](#pulp_cluster_clk_en) | 0x78 | 4 | PULP Cluster clk gate enable | -| carfield.[`SPATZ_CLUSTER_CLK_EN`](#spatz_cluster_clk_en) | 0x7c | 4 | Spatz Cluster clk gate enable | -| carfield.[`L2_CLK_EN`](#l2_clk_en) | 0x80 | 4 | Shared L2 memory clk gate enable | -| carfield.[`PERIPH_CLK_SEL`](#periph_clk_sel) | 0x84 | 4 | Periph Domain pll select (0 -> host pll, 1 -> alt PLL, 2 -> per pll) | -| carfield.[`SAFETY_ISLAND_CLK_SEL`](#safety_island_clk_sel) | 0x88 | 4 | Safety Island pll select (0 -> host pll, 1 -> alt PLL, 2 -> per pll) | -| carfield.[`SECURITY_ISLAND_CLK_SEL`](#security_island_clk_sel) | 0x8c | 4 | Security Island pll select (0 -> host pll, 1 -> alt PLL, 2 -> per pll) | -| carfield.[`PULP_CLUSTER_CLK_SEL`](#pulp_cluster_clk_sel) | 0x90 | 4 | PULP Cluster pll select (0 -> host pll, 1 -> alt PLL, 2 -> per pll) | -| carfield.[`SPATZ_CLUSTER_CLK_SEL`](#spatz_cluster_clk_sel) | 0x94 | 4 | Spatz Cluster pll select (0 -> host pll, 1 -> alt PLL, 2 -> per pll) | -| carfield.[`L2_CLK_SEL`](#l2_clk_sel) | 0x98 | 4 | L2 Memory pll select (0 -> host pll, 1 -> alt PLL, 2 -> per pll) | -| carfield.[`PERIPH_CLK_DIV_VALUE`](#periph_clk_div_value) | 0x9c | 4 | Periph Domain clk divider value | -| carfield.[`SAFETY_ISLAND_CLK_DIV_VALUE`](#safety_island_clk_div_value) | 0xa0 | 4 | Safety Island clk divider value | -| carfield.[`SECURITY_ISLAND_CLK_DIV_VALUE`](#security_island_clk_div_value) | 0xa4 | 4 | Security Island clk divider value | -| carfield.[`PULP_CLUSTER_CLK_DIV_VALUE`](#pulp_cluster_clk_div_value) | 0xa8 | 4 | PULP Cluster clk divider value | -| carfield.[`SPATZ_CLUSTER_CLK_DIV_VALUE`](#spatz_cluster_clk_div_value) | 0xac | 4 | Spatz Cluster clk divider value | -| carfield.[`L2_CLK_DIV_VALUE`](#l2_clk_div_value) | 0xb0 | 4 | L2 Memory clk divider value | -| carfield.[`HOST_FETCH_ENABLE`](#host_fetch_enable) | 0xb4 | 4 | Host Domain fetch enable | -| carfield.[`SAFETY_ISLAND_FETCH_ENABLE`](#safety_island_fetch_enable) | 0xb8 | 4 | Safety Island fetch enable | -| carfield.[`SECURITY_ISLAND_FETCH_ENABLE`](#security_island_fetch_enable) | 0xbc | 4 | Security Island fetch enable | -| carfield.[`PULP_CLUSTER_FETCH_ENABLE`](#pulp_cluster_fetch_enable) | 0xc0 | 4 | PULP Cluster fetch enable | -| carfield.[`SPATZ_CLUSTER_DEBUG_REQ`](#spatz_cluster_debug_req) | 0xc4 | 4 | Spatz Cluster debug req | -| carfield.[`HOST_BOOT_ADDR`](#host_boot_addr) | 0xc8 | 4 | Host boot address | -| carfield.[`SAFETY_ISLAND_BOOT_ADDR`](#safety_island_boot_addr) | 0xcc | 4 | Safety Island boot address | -| carfield.[`SECURITY_ISLAND_BOOT_ADDR`](#security_island_boot_addr) | 0xd0 | 4 | Security Island boot address | -| carfield.[`PULP_CLUSTER_BOOT_ADDR`](#pulp_cluster_boot_addr) | 0xd4 | 4 | PULP Cluster boot address | -| carfield.[`SPATZ_CLUSTER_BOOT_ADDR`](#spatz_cluster_boot_addr) | 0xd8 | 4 | Spatz Cluster boot address | -| carfield.[`PULP_CLUSTER_BOOT_ENABLE`](#pulp_cluster_boot_enable) | 0xdc | 4 | PULP Cluster boot enable | -| carfield.[`SPATZ_CLUSTER_BUSY`](#spatz_cluster_busy) | 0xe0 | 4 | Spatz Cluster busy | -| carfield.[`PULP_CLUSTER_BUSY`](#pulp_cluster_busy) | 0xe4 | 4 | PULP Cluster busy | -| carfield.[`PULP_CLUSTER_EOC`](#pulp_cluster_eoc) | 0xe8 | 4 | PULP Cluster end of computation | -| carfield.[`ETH_CLK_DIV_EN`](#eth_clk_div_en) | 0xec | 4 | Ethernet clock divider enable bit | -| carfield.[`ETH_CLK_DIV_VALUE`](#eth_clk_div_value) | 0xf0 | 4 | Ethernet clock divider value | -| carfield.[`HYPERBUS_CLK_DIV_EN`](#hyperbus_clk_div_en) | 0xf4 | 4 | Hyperbus clock divider enable bit | -| carfield.[`HYPERBUS_CLK_DIV_VALUE`](#hyperbus_clk_div_value) | 0xf8 | 4 | Hyperbus clock divider value | +| Name | Offset | Length | Description | +|:-----------------------------------------------------------------------------|:---------|---------:|:--------------------------------------------------------------------------------------| +| carfield.[`VERSION0`](#version0) | 0x0 | 4 | Cheshire sha256 commit | +| carfield.[`VERSION1`](#version1) | 0x4 | 4 | Safety Island sha256 commit | +| carfield.[`VERSION2`](#version2) | 0x8 | 4 | Security Island sha256 commit | +| carfield.[`VERSION3`](#version3) | 0xc | 4 | PULP Cluster sha256 commit | +| carfield.[`VERSION4`](#version4) | 0x10 | 4 | Spatz CLuster sha256 commit | +| carfield.[`JEDEC_IDCODE`](#jedec_idcode) | 0x14 | 4 | JEDEC ID CODE -TODO assign- | +| carfield.[`GENERIC_SCRATCH0`](#generic_scratch0) | 0x18 | 4 | Scratch | +| carfield.[`GENERIC_SCRATCH1`](#generic_scratch1) | 0x1c | 4 | Scratch | +| carfield.[`HOST_RST`](#host_rst) | 0x20 | 4 | Host Domain reset -active high, inverted in HW- | +| carfield.[`PERIPH_RST`](#periph_rst) | 0x24 | 4 | Periph Domain reset -active high, inverted in HW- | +| carfield.[`SAFETY_ISLAND_RST`](#safety_island_rst) | 0x28 | 4 | Safety Island reset -active high, inverted in HW- | +| carfield.[`SECURITY_ISLAND_RST`](#security_island_rst) | 0x2c | 4 | Security Island reset -active high, inverted in HW- | +| carfield.[`PULP_CLUSTER_RST`](#pulp_cluster_rst) | 0x30 | 4 | PULP Cluster reset -active high, inverted in HW- | +| carfield.[`SPATZ_CLUSTER_RST`](#spatz_cluster_rst) | 0x34 | 4 | Spatz Cluster reset -active high, inverted in HW- | +| carfield.[`L2_RST`](#l2_rst) | 0x38 | 4 | L2 reset -active high, inverted in HW- | +| carfield.[`PERIPH_ISOLATE`](#periph_isolate) | 0x3c | 4 | Periph Domain AXI isolate | +| carfield.[`SAFETY_ISLAND_ISOLATE`](#safety_island_isolate) | 0x40 | 4 | Safety Island AXI isolate | +| carfield.[`SECURITY_ISLAND_ISOLATE`](#security_island_isolate) | 0x44 | 4 | Security Island AXI isolate | +| carfield.[`PULP_CLUSTER_ISOLATE`](#pulp_cluster_isolate) | 0x48 | 4 | PULP Cluster AXI isolate | +| carfield.[`SPATZ_CLUSTER_ISOLATE`](#spatz_cluster_isolate) | 0x4c | 4 | Spatz Cluster AXI isolate | +| carfield.[`L2_ISOLATE`](#l2_isolate) | 0x50 | 4 | L2 AXI isolate | +| carfield.[`PERIPH_ISOLATE_STATUS`](#periph_isolate_status) | 0x54 | 4 | Periph Domain AXI isolate status | +| carfield.[`SAFETY_ISLAND_ISOLATE_STATUS`](#safety_island_isolate_status) | 0x58 | 4 | Safety Island AXI isolate status | +| carfield.[`SECURITY_ISLAND_ISOLATE_STATUS`](#security_island_isolate_status) | 0x5c | 4 | Security Island AXI isolate status | +| carfield.[`PULP_CLUSTER_ISOLATE_STATUS`](#pulp_cluster_isolate_status) | 0x60 | 4 | PULP Cluster AXI isolate status | +| carfield.[`SPATZ_CLUSTER_ISOLATE_STATUS`](#spatz_cluster_isolate_status) | 0x64 | 4 | Spatz Cluster AXI isolate status | +| carfield.[`L2_ISOLATE_STATUS`](#l2_isolate_status) | 0x68 | 4 | L2 AXI isolate status | +| carfield.[`PERIPH_CLK_EN`](#periph_clk_en) | 0x6c | 4 | Periph Domain clk gate enable | +| carfield.[`SAFETY_ISLAND_CLK_EN`](#safety_island_clk_en) | 0x70 | 4 | Safety Island clk gate enable | +| carfield.[`SECURITY_ISLAND_CLK_EN`](#security_island_clk_en) | 0x74 | 4 | Security Island clk gate enable | +| carfield.[`PULP_CLUSTER_CLK_EN`](#pulp_cluster_clk_en) | 0x78 | 4 | PULP Cluster clk gate enable | +| carfield.[`SPATZ_CLUSTER_CLK_EN`](#spatz_cluster_clk_en) | 0x7c | 4 | Spatz Cluster clk gate enable | +| carfield.[`L2_CLK_EN`](#l2_clk_en) | 0x80 | 4 | Shared L2 memory clk gate enable | +| carfield.[`PERIPH_CLK_SEL`](#periph_clk_sel) | 0x84 | 4 | Periph Domain fll select (0 -> host fll, 1 -> alt fll, 2 -> per fll, 3 -> secd fll) | +| carfield.[`SAFETY_ISLAND_CLK_SEL`](#safety_island_clk_sel) | 0x88 | 4 | Safety Island fll select (0 -> host fll, 1 -> alt fll, 2 -> per fll, 3 -> secd fll) | +| carfield.[`SECURITY_ISLAND_CLK_SEL`](#security_island_clk_sel) | 0x8c | 4 | Security Island fll select (0 -> host fll, 1 -> alt fll, 2 -> per fll, 3 -> secd fll) | +| carfield.[`PULP_CLUSTER_CLK_SEL`](#pulp_cluster_clk_sel) | 0x90 | 4 | PULP Cluster fll select (0 -> host fll, 1 -> alt fll, 2 -> per fll, 3 -> secd fll) | +| carfield.[`SPATZ_CLUSTER_CLK_SEL`](#spatz_cluster_clk_sel) | 0x94 | 4 | Spatz Cluster fll select (0 -> host fll, 1 -> alt fll, 2 -> per fll, 3 -> secd fll) | +| carfield.[`L2_CLK_SEL`](#l2_clk_sel) | 0x98 | 4 | L2 Memory fll select (0 -> host fll, 1 -> alt fll, 2 -> per fll, 3 -> secd fll) | +| carfield.[`PERIPH_CLK_DIV_VALUE`](#periph_clk_div_value) | 0x9c | 4 | Periph Domain clk divider value | +| carfield.[`SAFETY_ISLAND_CLK_DIV_VALUE`](#safety_island_clk_div_value) | 0xa0 | 4 | Safety Island clk divider value | +| carfield.[`SECURITY_ISLAND_CLK_DIV_VALUE`](#security_island_clk_div_value) | 0xa4 | 4 | Security Island clk divider value | +| carfield.[`PULP_CLUSTER_CLK_DIV_VALUE`](#pulp_cluster_clk_div_value) | 0xa8 | 4 | PULP Cluster clk divider value | +| carfield.[`SPATZ_CLUSTER_CLK_DIV_VALUE`](#spatz_cluster_clk_div_value) | 0xac | 4 | Spatz Cluster clk divider value | +| carfield.[`L2_CLK_DIV_VALUE`](#l2_clk_div_value) | 0xb0 | 4 | L2 Memory clk divider value | +| carfield.[`HOST_FETCH_ENABLE`](#host_fetch_enable) | 0xb4 | 4 | Host Domain fetch enable | +| carfield.[`SAFETY_ISLAND_FETCH_ENABLE`](#safety_island_fetch_enable) | 0xb8 | 4 | Safety Island fetch enable | +| carfield.[`SECURITY_ISLAND_FETCH_ENABLE`](#security_island_fetch_enable) | 0xbc | 4 | Security Island fetch enable | +| carfield.[`PULP_CLUSTER_FETCH_ENABLE`](#pulp_cluster_fetch_enable) | 0xc0 | 4 | PULP Cluster fetch enable | +| carfield.[`SPATZ_CLUSTER_DEBUG_REQ`](#spatz_cluster_debug_req) | 0xc4 | 4 | Spatz Cluster debug req | +| carfield.[`HOST_BOOT_ADDR`](#host_boot_addr) | 0xc8 | 4 | Host boot address | +| carfield.[`SAFETY_ISLAND_BOOT_ADDR`](#safety_island_boot_addr) | 0xcc | 4 | Safety Island boot address | +| carfield.[`SECURITY_ISLAND_BOOT_ADDR`](#security_island_boot_addr) | 0xd0 | 4 | Security Island boot address | +| carfield.[`PULP_CLUSTER_BOOT_ADDR`](#pulp_cluster_boot_addr) | 0xd4 | 4 | PULP Cluster boot address | +| carfield.[`SPATZ_CLUSTER_BOOT_ADDR`](#spatz_cluster_boot_addr) | 0xd8 | 4 | Spatz Cluster boot address | +| carfield.[`PULP_CLUSTER_BOOT_ENABLE`](#pulp_cluster_boot_enable) | 0xdc | 4 | PULP Cluster boot enable | +| carfield.[`SPATZ_CLUSTER_BUSY`](#spatz_cluster_busy) | 0xe0 | 4 | Spatz Cluster busy | +| carfield.[`PULP_CLUSTER_BUSY`](#pulp_cluster_busy) | 0xe4 | 4 | PULP Cluster busy | +| carfield.[`PULP_CLUSTER_EOC`](#pulp_cluster_eoc) | 0xe8 | 4 | PULP Cluster end of computation | +| carfield.[`ETH_CLK_DIV_EN`](#eth_clk_div_en) | 0xec | 4 | Ethernet clock divider enable bit | +| carfield.[`ETH_CLK_DIV_VALUE`](#eth_clk_div_value) | 0xf0 | 4 | Ethernet clock divider value | +| carfield.[`HYPERBUS_CLK_DIV_EN`](#hyperbus_clk_div_en) | 0xf4 | 4 | Hyperbus clock divider enable bit | +| carfield.[`HYPERBUS_CLK_DIV_VALUE`](#hyperbus_clk_div_value) | 0xf8 | 4 | Hyperbus clock divider value | +| carfield.[`STREAMER_CLK_DIV_ENABLE`](#streamer_clk_div_enable) | 0xfc | 4 | Streamer clock divider enable | +| carfield.[`STREAMER_CLK_DIV_VALUE`](#streamer_clk_div_value) | 0x100 | 4 | Streamer clock divider value | +| carfield.[`STREAMER_GENERAL_IRQ`](#streamer_general_irq) | 0x104 | 4 | Streamer general interrupt | +| carfield.[`SPW_GENERAL_IRQ`](#spw_general_irq) | 0x108 | 4 | SpaceWire general interrupt | ## VERSION0 Cheshire sha256 commit @@ -620,7 +624,7 @@ Shared L2 memory clk gate enable | 0 | rw | 0x1 | L2_CLK_EN | | ## PERIPH_CLK_SEL -Periph Domain pll select (0 -> host pll, 1 -> alt PLL, 2 -> per pll) +Periph Domain fll select (0 -> host fll, 1 -> alt fll, 2 -> per fll, 3 -> secd fll) - Offset: `0x84` - Reset default: `0x2` - Reset mask: `0x3` @@ -637,7 +641,7 @@ Periph Domain pll select (0 -> host pll, 1 -> alt PLL, 2 -> per pll) | 1:0 | rw | 0x2 | PERIPH_CLK_SEL | | ## SAFETY_ISLAND_CLK_SEL -Safety Island pll select (0 -> host pll, 1 -> alt PLL, 2 -> per pll) +Safety Island fll select (0 -> host fll, 1 -> alt fll, 2 -> per fll, 3 -> secd fll) - Offset: `0x88` - Reset default: `0x1` - Reset mask: `0x3` @@ -654,9 +658,9 @@ Safety Island pll select (0 -> host pll, 1 -> alt PLL, 2 -> per pll) | 1:0 | rw | 0x1 | SAFETY_ISLAND_CLK_SEL | | ## SECURITY_ISLAND_CLK_SEL -Security Island pll select (0 -> host pll, 1 -> alt PLL, 2 -> per pll) +Security Island fll select (0 -> host fll, 1 -> alt fll, 2 -> per fll, 3 -> secd fll) - Offset: `0x8c` -- Reset default: `0x1` +- Reset default: `0x3` - Reset mask: `0x3` ### Fields @@ -668,10 +672,10 @@ Security Island pll select (0 -> host pll, 1 -> alt PLL, 2 -> per pll) | Bits | Type | Reset | Name | Description | |:------:|:------:|:-------:|:------------------------|:--------------| | 31:2 | | | | Reserved | -| 1:0 | rw | 0x1 | SECURITY_ISLAND_CLK_SEL | | +| 1:0 | rw | 0x3 | SECURITY_ISLAND_CLK_SEL | | ## PULP_CLUSTER_CLK_SEL -PULP Cluster pll select (0 -> host pll, 1 -> alt PLL, 2 -> per pll) +PULP Cluster fll select (0 -> host fll, 1 -> alt fll, 2 -> per fll, 3 -> secd fll) - Offset: `0x90` - Reset default: `0x1` - Reset mask: `0x3` @@ -688,7 +692,7 @@ PULP Cluster pll select (0 -> host pll, 1 -> alt PLL, 2 -> per pll) | 1:0 | rw | 0x1 | PULP_CLUSTER_CLK_SEL | | ## SPATZ_CLUSTER_CLK_SEL -Spatz Cluster pll select (0 -> host pll, 1 -> alt PLL, 2 -> per pll) +Spatz Cluster fll select (0 -> host fll, 1 -> alt fll, 2 -> per fll, 3 -> secd fll) - Offset: `0x94` - Reset default: `0x1` - Reset mask: `0x3` @@ -705,7 +709,7 @@ Spatz Cluster pll select (0 -> host pll, 1 -> alt PLL, 2 -> per pll) | 1:0 | rw | 0x1 | SPATZ_CLUSTER_CLK_SEL | | ## L2_CLK_SEL -L2 Memory pll select (0 -> host pll, 1 -> alt PLL, 2 -> per pll) +L2 Memory fll select (0 -> host fll, 1 -> alt fll, 2 -> per fll, 3 -> secd fll) - Offset: `0x98` - Reset default: `0x1` - Reset mask: `0x3` @@ -1124,3 +1128,71 @@ Hyperbus clock divider value | 31:20 | | | | Reserved | | 19:0 | rw | 0x1 | HYPERBUS_CLK_DIV_VALUE | | +## STREAMER_CLK_DIV_ENABLE +Streamer clock divider enable +- Offset: `0xfc` +- Reset default: `0x0` +- Reset mask: `0x1` + +### Fields + +```wavejson +{"reg": [{"name": "STREAMER_CLK_DIV_ENABLE", "bits": 1, "attr": ["rw"], "rotate": -90}, {"bits": 31}], "config": {"lanes": 1, "fontsize": 10, "vspace": 250}} +``` + +| Bits | Type | Reset | Name | Description | +|:------:|:------:|:-------:|:------------------------|:--------------| +| 31:1 | | | | Reserved | +| 0 | rw | 0x0 | STREAMER_CLK_DIV_ENABLE | | + +## STREAMER_CLK_DIV_VALUE +Streamer clock divider value +- Offset: `0x100` +- Reset default: `0x1` +- Reset mask: `0x3f` + +### Fields + +```wavejson +{"reg": [{"name": "STREAMER_CLK_DIV_VALUE", "bits": 6, "attr": ["rw"], "rotate": -90}, {"bits": 26}], "config": {"lanes": 1, "fontsize": 10, "vspace": 240}} +``` + +| Bits | Type | Reset | Name | Description | +|:------:|:------:|:-------:|:-----------------------|:--------------| +| 31:6 | | | | Reserved | +| 5:0 | rw | 0x1 | STREAMER_CLK_DIV_VALUE | | + +## STREAMER_GENERAL_IRQ +Streamer general interrupt +- Offset: `0x104` +- Reset default: `0x0` +- Reset mask: `0x1` + +### Fields + +```wavejson +{"reg": [{"name": "STREAMER_GENERAL_IRQ", "bits": 1, "attr": ["rw"], "rotate": -90}, {"bits": 31}], "config": {"lanes": 1, "fontsize": 10, "vspace": 220}} +``` + +| Bits | Type | Reset | Name | Description | +|:------:|:------:|:-------:|:---------------------|:--------------| +| 31:1 | | | | Reserved | +| 0 | rw | 0x0 | STREAMER_GENERAL_IRQ | | + +## SPW_GENERAL_IRQ +SpaceWire general interrupt +- Offset: `0x108` +- Reset default: `0x0` +- Reset mask: `0x1` + +### Fields + +```wavejson +{"reg": [{"name": "SPW_GENERAL_IRQ", "bits": 1, "attr": ["rw"], "rotate": -90}, {"bits": 31}], "config": {"lanes": 1, "fontsize": 10, "vspace": 170}} +``` + +| Bits | Type | Reset | Name | Description | +|:------:|:------:|:-------:|:----------------|:--------------| +| 31:1 | | | | Reserved | +| 0 | rw | 0x0 | SPW_GENERAL_IRQ | | + diff --git a/sw/include/car_memory_map.h b/sw/include/car_memory_map.h index 9729716b..ea0460db 100644 --- a/sw/include/car_memory_map.h +++ b/sw/include/car_memory_map.h @@ -121,6 +121,8 @@ extern void *__base_l2; #define CAR_ADVANCED_TIMER_OFFSET 0x0005000 #define CAR_WATCHDOG_TIMER_OFFSET 0x0007000 #define CAR_HYPERBUS_CFG_OFFSET 0x0008000 +#define CAR_STREAMER_CFG_OFFSET 0x0009000 +#define CAR_STREAMER_APB_OFFSET 0x0011000 #define CAR_PAD_CFG_OFFSET 0x1000000 #define CAR_ETHERNET_BASE_ADDR (CAR_PERIPHS_BASE_ADDR + CAR_ETHERNET_OFFSET) @@ -129,6 +131,8 @@ extern void *__base_l2; #define CAR_ADVANCED_TIMER_BASE_ADDR (CAR_PERIPHS_BASE_ADDR + CAR_ADVANCED_TIMER_OFFSET) #define CAR_WATCHDOG_TIMER_BASE_ADDR (CAR_PERIPHS_BASE_ADDR + CAR_WATCHDOG_TIMER_OFFSET) #define CAR_HYPERBUS_CFG_BASE_ADDR (CAR_PERIPHS_BASE_ADDR + CAR_HYPERBUS_CFG_OFFSET) +#define CAR_STREAMER_CFG_BASE_ADDR (CAR_PERIPHS_BASE_ADDR + CAR_STREAMER_CFG_OFFSET) +#define CAR_STREAMER_APB_BASE_ADDR (CAR_PERIPHS_BASE_ADDR + CAR_STREAMER_APB_OFFSET) #define CAR_PAD_CFG_BASE_ADDR (CAR_PERIPHS_BASE_ADDR + CAR_PAD_CFG_OFFSET) #define CAR_SOC_CTRL_BASE_ADDR(BASE) BASE @@ -158,10 +162,213 @@ extern void *__base_l2; #define MBOX_CAR_LETTER0(id) (CAR_MBOX_BASE_ADDR + MBOX_LETTER0_OFFSET + (id*0x100)) #define MBOX_CAR_LETTER1(id) (CAR_MBOX_BASE_ADDR + MBOX_LETTER1_OFFSET + (id*0x100)) -// PLL -#define CAR_PLL_BASE_ADDRESS 0x21003000 -#define PLL_ADDR_SPACE 0x200 -#define PLL_BASE_ADDRESS(id) (CAR_PLL_BASE_ADDRESS + (id+1)*PLL_ADDR_SPACE) +//TCTM Streamer +#define TCTM_STREAMER_CFG_OFFS 0x0 +#define TCTM_STREAMER_MAP_ROUTER_OFFS 0x0 +#define TCTM_STREAMER_HPC_OFFS 0x80 +#define TCTM_STREAMER_OBT_OFFS 0x100 +#define TCTM_STREAMER_PTME_OFFS 0x180 +#define TCTM_STREAMER_PTD_OFFS 0x200 +#define TCTM_STREAMER_LLC_OFFS 0x280 + +#define TCTM_STREAMER_PTME_CFG_OFFS 0x000 +#define TCTM_STREAMER_TM_PACKETS_OFFS 0x400 +#define TCTM_STREAMER_TC_BUFFER_OFFS 0x800 +#define TCTM_STREAMER_TX_BUFFER_OFFS 0xC00 + +#define TCTM_STREAMER_CFG_MAP_ROUTER_BASE CAR_STREAMER_CFG_BASE_ADDR + TCTM_STREAMER_MAP_ROUTER_OFFS +#define TCTM_STREAMER_CFG_HPC_BASE CAR_STREAMER_CFG_BASE_ADDR + TCTM_STREAMER_HPC_OFFS +#define TCTM_STREAMER_CFG_OBT_BASE CAR_STREAMER_CFG_BASE_ADDR + TCTM_STREAMER_OBT_OFFS +#define TCTM_STREAMER_CFG_PTME_BASE CAR_STREAMER_CFG_BASE_ADDR + TCTM_STREAMER_PTME_OFFS +#define TCTM_STREAMER_CFG_PTD_BASE CAR_STREAMER_CFG_BASE_ADDR + TCTM_STREAMER_PTD_OFFS +#define TCTM_STREAMER_CFG_LLC_BASE CAR_STREAMER_CFG_BASE_ADDR + TCTM_STREAMER_LLC_OFFS + +#define TCTM_STREAMER_APB_PTME_CFG CAR_STREAMER_APB_BASE_ADDR + TCTM_STREAMER_PTME_CFG_OFFS +#define TCTM_STREAMER_APB_TM_PACKET_BASE CAR_STREAMER_APB_BASE_ADDR + TCTM_STREAMER_TM_PACKETS_OFFS +#define TCTM_STREAMER_APB_TC_BUFFER_BASE CAR_STREAMER_APB_BASE_ADDR + TCTM_STREAMER_TC_BUFFER_OFFS +#define TCTM_STREAMER_APB_TX_BUFFER_BASE CAR_STREAMER_APB_BASE_ADDR + TCTM_STREAMER_TX_BUFFER_OFFS + +// FLL +#define FLL_ADDR_SPACE 0x20 +#define FLL_HOST_ID 0x0 +#define FLL_PERIPH_ID 0x1 +#define FLL_ALT_ID 0x2 +#define FLL_SECD_ID 0x3 +#define FLL_RT_ID 0x4 +#define FLL_BASE_ADDRESS(id) (fll + (id)*FLL_ADDR_SPACE) + +#define FLL_STATUS_REG_I 0x00 +#define FLL_CONFIG_REG_I 0x08 +#define FLL_CONFIG_REG_II 0x10 +#define FLL_INTEGR_REG 0x18 + +// Padframe +#define PADFRAME_BASE_ADDRESS padframe + +#define PADFRAME_CONFIG_INFO 0x0 + +#define PADFRAME_CONFIG_MUXED_V_00_CFG 0x4 +#define PADFRAME_CONFIG_MUXED_V_01_CFG 0xc +#define PADFRAME_CONFIG_MUXED_V_02_CFG 0x14 +#define PADFRAME_CONFIG_MUXED_V_03_CFG 0x1c +#define PADFRAME_CONFIG_MUXED_V_04_CFG 0x24 +#define PADFRAME_CONFIG_MUXED_V_05_CFG 0x2c +#define PADFRAME_CONFIG_MUXED_V_06_CFG 0x34 +#define PADFRAME_CONFIG_MUXED_V_07_CFG 0x3c +#define PADFRAME_CONFIG_MUXED_V_08_CFG 0x44 +#define PADFRAME_CONFIG_MUXED_V_09_CFG 0x4c +#define PADFRAME_CONFIG_MUXED_V_10_CFG 0x54 +#define PADFRAME_CONFIG_MUXED_V_11_CFG 0x5c +#define PADFRAME_CONFIG_MUXED_V_12_CFG 0x64 +#define PADFRAME_CONFIG_MUXED_V_13_CFG 0x6c +#define PADFRAME_CONFIG_MUXED_V_14_CFG 0x74 +#define PADFRAME_CONFIG_MUXED_V_15_CFG 0x7c +#define PADFRAME_CONFIG_MUXED_V_16_CFG 0x84 +#define PADFRAME_CONFIG_MUXED_V_17_CFG 0x8c +#define PADFRAME_CONFIG_MUXED_H_00_CFG 0x94 +#define PADFRAME_CONFIG_MUXED_H_01_CFG 0x9c +#define PADFRAME_CONFIG_MUXED_H_02_CFG 0xa4 +#define PADFRAME_CONFIG_MUXED_H_03_CFG 0xac + +#define PADFRAME_CONFIG_MUXED_V_00_MUX_SEL 0x8 +#define PADFRAME_CONFIG_MUXED_V_01_MUX_SEL 0x10 +#define PADFRAME_CONFIG_MUXED_V_02_MUX_SEL 0x18 +#define PADFRAME_CONFIG_MUXED_V_03_MUX_SEL 0x20 +#define PADFRAME_CONFIG_MUXED_V_04_MUX_SEL 0x28 +#define PADFRAME_CONFIG_MUXED_V_05_MUX_SEL 0x30 +#define PADFRAME_CONFIG_MUXED_V_06_MUX_SEL 0x38 +#define PADFRAME_CONFIG_MUXED_V_07_MUX_SEL 0x40 +#define PADFRAME_CONFIG_MUXED_V_08_MUX_SEL 0x48 +#define PADFRAME_CONFIG_MUXED_V_09_MUX_SEL 0x50 +#define PADFRAME_CONFIG_MUXED_V_10_MUX_SEL 0x58 +#define PADFRAME_CONFIG_MUXED_V_11_MUX_SEL 0x60 +#define PADFRAME_CONFIG_MUXED_V_12_MUX_SEL 0x68 +#define PADFRAME_CONFIG_MUXED_V_13_MUX_SEL 0x70 +#define PADFRAME_CONFIG_MUXED_V_14_MUX_SEL 0x78 +#define PADFRAME_CONFIG_MUXED_V_15_MUX_SEL 0x80 +#define PADFRAME_CONFIG_MUXED_V_16_MUX_SEL 0x88 +#define PADFRAME_CONFIG_MUXED_V_17_MUX_SEL 0x90 +#define PADFRAME_CONFIG_MUXED_H_00_MUX_SEL 0x98 +#define PADFRAME_CONFIG_MUXED_H_01_MUX_SEL 0xa0 +#define PADFRAME_CONFIG_MUXED_H_02_MUX_SEL 0xa8 +#define PADFRAME_CONFIG_MUXED_H_03_MUX_SEL 0xb0 + +#define PADFRAME_MUXED_V_00_SEL_DEFAULT 0x0 +#define PADFRAME_MUXED_V_00_SEL_CAN_RX 0x1 +#define PADFRAME_MUXED_V_00_SEL_GPIO_IO_V_0 0x2 +#define PADFRAME_MUXED_V_00_SEL_I2C_SDA 0x3 +#define PADFRAME_MUXED_V_00_SEL_SPI_SCK 0x4 +#define PADFRAME_MUXED_V_00_SEL_SPI_OT_SCK 0x5 +#define PADFRAME_MUXED_V_01_SEL_DEFAULT 0x0 +#define PADFRAME_MUXED_V_01_SEL_CAN_TX 0x1 +#define PADFRAME_MUXED_V_01_SEL_GPIO_IO_V_1 0x2 +#define PADFRAME_MUXED_V_01_SEL_I2C_SCL 0x3 +#define PADFRAME_MUXED_V_01_SEL_SPI_CSB_0 0x4 +#define PADFRAME_MUXED_V_01_SEL_SPI_OT_CSB 0x5 +#define PADFRAME_MUXED_V_02_SEL_DEFAULT 0x0 +#define PADFRAME_MUXED_V_02_SEL_GPIO_IO_V_2 0x1 +#define PADFRAME_MUXED_V_02_SEL_SPI_CSB_1 0x2 +#define PADFRAME_MUXED_V_02_SEL_SPI_OT_SD_0 0x3 +#define PADFRAME_MUXED_V_03_SEL_DEFAULT 0x0 +#define PADFRAME_MUXED_V_03_SEL_GPIO_IO_V_3 0x1 +#define PADFRAME_MUXED_V_03_SEL_SPI_SD_0 0x2 +#define PADFRAME_MUXED_V_03_SEL_SPI_OT_SD_1 0x3 +#define PADFRAME_MUXED_V_04_SEL_DEFAULT 0x0 +#define PADFRAME_MUXED_V_04_SEL_GPIO_IO_V_4 0x1 +#define PADFRAME_MUXED_V_04_SEL_SERIAL_LINK_RCV_CLK_I 0x2 +#define PADFRAME_MUXED_V_04_SEL_SPI_SD_1 0x3 +#define PADFRAME_MUXED_V_04_SEL_SPI_OT_SD_2 0x4 +#define PADFRAME_MUXED_V_05_SEL_DEFAULT 0x0 +#define PADFRAME_MUXED_V_05_SEL_GPIO_IO_V_5 0x1 +#define PADFRAME_MUXED_V_05_SEL_SERIAL_LINK_I_0 0x2 +#define PADFRAME_MUXED_V_05_SEL_SPI_SD_2 0x3 +#define PADFRAME_MUXED_V_05_SEL_SPI_OT_SD_3 0x4 +#define PADFRAME_MUXED_V_06_SEL_DEFAULT 0x0 +#define PADFRAME_MUXED_V_06_SEL_GPIO_IO_V_6 0x1 +#define PADFRAME_MUXED_V_06_SEL_SERIAL_LINK_I_1 0x2 +#define PADFRAME_MUXED_V_06_SEL_SPI_SD_3 0x3 +#define PADFRAME_MUXED_V_07_SEL_DEFAULT 0x0 +#define PADFRAME_MUXED_V_07_SEL_ETHERNET_RXCK 0x1 +#define PADFRAME_MUXED_V_07_SEL_GPIO_IO_V_7 0x2 +#define PADFRAME_MUXED_V_07_SEL_PLL_IO_0 0x3 +#define PADFRAME_MUXED_V_07_SEL_SERIAL_LINK_I_2 0x4 +#define PADFRAME_MUXED_V_07_SEL_TC_ACTIVE 0x5 +#define PADFRAME_MUXED_V_08_SEL_DEFAULT 0x0 +#define PADFRAME_MUXED_V_08_SEL_ETHERNET_RXCTL 0x1 +#define PADFRAME_MUXED_V_08_SEL_GPIO_IO_V_8 0x2 +#define PADFRAME_MUXED_V_08_SEL_PLL_IO_1 0x3 +#define PADFRAME_MUXED_V_08_SEL_SERIAL_LINK_I_3 0x4 +#define PADFRAME_MUXED_V_08_SEL_TC_CLK 0x5 +#define PADFRAME_MUXED_V_09_SEL_DEFAULT 0x0 +#define PADFRAME_MUXED_V_09_SEL_ETHERNET_RXD_0 0x1 +#define PADFRAME_MUXED_V_09_SEL_GPIO_IO_V_9 0x2 +#define PADFRAME_MUXED_V_09_SEL_PLL_IO_2 0x3 +#define PADFRAME_MUXED_V_09_SEL_SERIAL_LINK_I_4 0x4 +#define PADFRAME_MUXED_V_09_SEL_TC_DATA 0x5 +#define PADFRAME_MUXED_V_10_SEL_DEFAULT 0x0 +#define PADFRAME_MUXED_V_10_SEL_ETHERNET_RXD_1 0x1 +#define PADFRAME_MUXED_V_10_SEL_GPIO_IO_V_10 0x2 +#define PADFRAME_MUXED_V_10_SEL_PLL_IO_3 0x3 +#define PADFRAME_MUXED_V_10_SEL_PTME_CLK 0x4 +#define PADFRAME_MUXED_V_10_SEL_SERIAL_LINK_I_5 0x5 +#define PADFRAME_MUXED_V_11_SEL_DEFAULT 0x0 +#define PADFRAME_MUXED_V_11_SEL_ETHERNET_RXD_2 0x1 +#define PADFRAME_MUXED_V_11_SEL_GPIO_IO_V_11 0x2 +#define PADFRAME_MUXED_V_11_SEL_PLL_IO_4 0x3 +#define PADFRAME_MUXED_V_11_SEL_PTME_ENC 0x4 +#define PADFRAME_MUXED_V_11_SEL_SERIAL_LINK_I_6 0x5 +#define PADFRAME_MUXED_V_12_SEL_DEFAULT 0x0 +#define PADFRAME_MUXED_V_12_SEL_ETHERNET_RXD_3 0x1 +#define PADFRAME_MUXED_V_12_SEL_GPIO_IO_V_12 0x2 +#define PADFRAME_MUXED_V_12_SEL_PLL_IO_5 0x3 +#define PADFRAME_MUXED_V_12_SEL_PTME_SYNC 0x4 +#define PADFRAME_MUXED_V_12_SEL_SERIAL_LINK_I_7 0x5 +#define PADFRAME_MUXED_V_13_SEL_DEFAULT 0x0 +#define PADFRAME_MUXED_V_13_SEL_ETHERNET_TXCK 0x1 +#define PADFRAME_MUXED_V_13_SEL_GPIO_IO_V_13 0x2 +#define PADFRAME_MUXED_V_13_SEL_PLL_IO_6 0x3 +#define PADFRAME_MUXED_V_13_SEL_PTME_EXT_CLK 0x4 +#define PADFRAME_MUXED_V_13_SEL_SERIAL_LINK_RCV_CLK_O 0x5 +#define PADFRAME_MUXED_V_14_SEL_DEFAULT 0x0 +#define PADFRAME_MUXED_V_14_SEL_ETHERNET_TXCTL 0x1 +#define PADFRAME_MUXED_V_14_SEL_GPIO_IO_V_14 0x2 +#define PADFRAME_MUXED_V_14_SEL_HPC_ADDR_0 0x3 +#define PADFRAME_MUXED_V_14_SEL_SERIAL_LINK_O_V_0 0x4 +#define PADFRAME_MUXED_V_15_SEL_DEFAULT 0x0 +#define PADFRAME_MUXED_V_15_SEL_ETHERNET_TXD_0 0x1 +#define PADFRAME_MUXED_V_15_SEL_GPIO_IO_V_15 0x2 +#define PADFRAME_MUXED_V_15_SEL_HPC_ADDR_1 0x3 +#define PADFRAME_MUXED_V_15_SEL_SERIAL_LINK_O_V_1 0x4 +#define PADFRAME_MUXED_V_16_SEL_DEFAULT 0x0 +#define PADFRAME_MUXED_V_16_SEL_ETHERNET_TXD_1 0x1 +#define PADFRAME_MUXED_V_16_SEL_GPIO_IO_V_16 0x2 +#define PADFRAME_MUXED_V_16_SEL_HPC_ADDR_2 0x3 +#define PADFRAME_MUXED_V_16_SEL_SERIAL_LINK_O_V_2 0x4 +#define PADFRAME_MUXED_V_17_SEL_DEFAULT 0x0 +#define PADFRAME_MUXED_V_17_SEL_ETHERNET_TXD_2 0x1 +#define PADFRAME_MUXED_V_17_SEL_GPIO_IO_V_17 0x2 +#define PADFRAME_MUXED_V_17_SEL_HPC_CMD_EN 0x3 +#define PADFRAME_MUXED_V_17_SEL_SERIAL_LINK_O_V_3 0x4 +#define PADFRAME_MUXED_H_00_SEL_DEFAULT 0x0 +#define PADFRAME_MUXED_H_00_SEL_ETHERNET_TXD_3 0x1 +#define PADFRAME_MUXED_H_00_SEL_GPIO_IO_H_0 0x2 +#define PADFRAME_MUXED_H_00_SEL_HPC_SAMPLE 0x3 +#define PADFRAME_MUXED_H_00_SEL_SERIAL_LINK_O_H_0 0x4 +#define PADFRAME_MUXED_H_01_SEL_DEFAULT 0x0 +#define PADFRAME_MUXED_H_01_SEL_ETHERNET_MD 0x1 +#define PADFRAME_MUXED_H_01_SEL_GPIO_IO_H_1 0x2 +#define PADFRAME_MUXED_H_01_SEL_LLC_LINE_0 0x3 +#define PADFRAME_MUXED_H_01_SEL_SERIAL_LINK_O_H_1 0x4 +#define PADFRAME_MUXED_H_02_SEL_DEFAULT 0x0 +#define PADFRAME_MUXED_H_02_SEL_ETHERNET_MDC 0x1 +#define PADFRAME_MUXED_H_02_SEL_GPIO_IO_H_2 0x2 +#define PADFRAME_MUXED_H_02_SEL_LLC_LINE_1 0x3 +#define PADFRAME_MUXED_H_02_SEL_SERIAL_LINK_O_H_2 0x4 +#define PADFRAME_MUXED_H_03_SEL_DEFAULT 0x0 +#define PADFRAME_MUXED_H_03_SEL_ETHERNET_RST_N 0x1 +#define PADFRAME_MUXED_H_03_SEL_GPIO_IO_H_3 0x2 +#define PADFRAME_MUXED_H_03_SEL_OBT_EXT_CLK 0x3 +#define PADFRAME_MUXED_H_03_SEL_SERIAL_LINK_O_H_3 0x4 // Error codes #define EHOSTDEXEC 1 // Execution error host domain diff --git a/sw/include/car_params.h b/sw/include/car_params.h index ab515a23..905b8cf5 100644 --- a/sw/include/car_params.h +++ b/sw/include/car_params.h @@ -18,6 +18,8 @@ const void* car_l2_intl_0 = 0x78000000; const void* car_l2_cont_0 = 0x78010000; const void* car_l2_intl_1 = 0x78020000; const void* car_l2_cont_1 = 0x78030000; +const void* fll = 0x21003000; +const void* padframe = 0x21000000; #else // Pointers to be mapped by the driver void* car_soc_ctrl; @@ -28,4 +30,6 @@ void* car_l2_intl_0; void* car_l2_cont_0; void* car_l2_intl_1; void* car_l2_cont_1; +void* fll; +void* padframe; #endif diff --git a/sw/include/car_util.h b/sw/include/car_util.h index 03e3a9f9..af0b1c02 100644 --- a/sw/include/car_util.h +++ b/sw/include/car_util.h @@ -379,12 +379,6 @@ uint32_t pulp_cluster_get_return(){ return readw(pulp_return_addr); } -// Wake up sleeping hart using CLINT -static inline void wakeup_hart(unsigned int hart_id) { - writew(0x1, CAR_CLINT_BASE_ADDR + 0x4*(hart_id)); - writew(0x0, CAR_CLINT_BASE_ADDR + 0x4*(hart_id)); -} - // Write synchronization request in Cheshire's dedicated register static inline void sync_req(){ writew(readw(CHESHIRE_HARTS_SYNC) | (0x1 << hart_id()), CHESHIRE_HARTS_SYNC); diff --git a/sw/include/fll.h b/sw/include/fll.h new file mode 100644 index 00000000..e68d37d5 --- /dev/null +++ b/sw/include/fll.h @@ -0,0 +1,74 @@ +// Copyright 2022 ETH Zurich and University of Bologna. +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +// +// Victor Isachi +// +// FLL driver + +#ifndef __FLL_H +#define __FLL_H + +#include "car_util.h" + +#define FLL_DCO_CODE_MASK (0x03FF0000) +#define FLL_CLK_DIV_MASK (0x3C000000) +#define FLL_CLK_MUL_MASK (0x0000FFFF) +#define FLL_MODE_MASK (0x80000000) + +#define FLL_DCO_CODE_OFFSET (16) +#define FLL_CLK_DIV_OFFSET (26) +#define FLL_CLK_MUL_OFFSET (0) +#define FLL_MODE_OFFSET (31) + +inline uint32_t set_bitfield(uint32_t val, uint32_t src_reg, uint32_t bitfield_mask, uint32_t bitfield_offset){ + return (src_reg & ~bitfield_mask) | ((val << bitfield_offset) & bitfield_mask); +} + +inline uint32_t read_fll_reg(uint8_t fll_id, uint8_t reg_offset){ + return readw(FLL_BASE_ADDRESS(fll_id) + reg_offset); +} + +inline void write_fll_reg(uint32_t val, uint8_t fll_id, uint8_t reg_offset){ + writew(val, FLL_BASE_ADDRESS(fll_id) + reg_offset); +} + +void write_fll_bitfield(uint32_t val, uint8_t fll_id, uint8_t reg_offset, uint32_t bitfield_mask, uint8_t bitfield_offset){ + uint32_t fll_reg; + fll_reg = read_fll_reg(fll_id, reg_offset); + fll_reg = set_bitfield(val, fll_reg, bitfield_mask, bitfield_offset); + write_fll_reg(fll_reg, fll_id, reg_offset); +} + +void fll_stand_alone(uint8_t fll_id){ + write_fll_bitfield(0x0, fll_id, FLL_CONFIG_REG_I, FLL_MODE_MASK, FLL_MODE_OFFSET); +} + +void fll_normal(uint8_t fll_id){ + write_fll_bitfield(0x1, fll_id, FLL_CONFIG_REG_I, FLL_MODE_MASK, FLL_MODE_OFFSET); +} + +void set_fll_dco_code(uint32_t dco_code, uint8_t fll_id){ + write_fll_bitfield(dco_code, fll_id, FLL_CONFIG_REG_I, FLL_DCO_CODE_MASK, FLL_DCO_CODE_OFFSET); +} + +// When programmed in normal mode, the FLL computes the final frequency as: +// freq = (clk_mul + 1)/clk_div. For example, to set up the FLL for 500 MHz, one option is to +// set clk_mul = 999, and clk_div = 2. +void set_fll_clk_div(uint32_t clk_div, uint8_t fll_id){ + write_fll_bitfield(clk_div, fll_id, FLL_CONFIG_REG_I, FLL_CLK_DIV_MASK, FLL_CLK_DIV_OFFSET); +} + +void set_fll_clk_mul(uint32_t clk_mul, uint8_t fll_id){ + write_fll_bitfield(clk_mul, fll_id, FLL_CONFIG_REG_I, FLL_CLK_MUL_MASK, FLL_CLK_MUL_OFFSET); +} + +// The following API uses a default divider by 2 to program the peripheral FLL +void set_periph_fll_div2(uint32_t clk_freq){ + unsigned int divdier = 2; + fll_normal(FLL_PERIPH_ID); + set_fll_clk_mul((divdier*clk_freq) - 1, FLL_PERIPH_ID); + set_fll_clk_div(divdier, FLL_PERIPH_ID); +} + +#endif /*__FLL_H*/ diff --git a/sw/include/hmr.h b/sw/include/hmr.h deleted file mode 100644 index 983978a5..00000000 --- a/sw/include/hmr.h +++ /dev/null @@ -1,189 +0,0 @@ -// Copyright 2023 ETH Zurich and University of Bologna. -// Licensed under the Apache License, Version 2.0, see LICENSE for details. -// SPDX-License-Identifier: Apache-2.0 -// -// Yvan Tortorella - -#include "car_util.h" - -#define QUAUX(X) #X -#define QU(X) QUAUX(X) - -// We save 31 32-bit registers from RF -#define NumRfRegs 0x1F -#define HmrStateSize 0x8*NumRfRegs - -void __attribute__((naked)) hmr_store_state() { - // Disable caches - __asm__ __volatile__ ( - "csrrwi x0, 0x7C1, 0x0 \n\t" - : : : "memory"); - - __asm__ __volatile__ ( - // Allocate space on top of the stack to store - // the state - "add sp, sp, -" QU(HmrStateSize) " \n\t" - - // Store registers to stack - // zero not stored as hardwired (x0) - // ra stored as HMR checkpoint (x1) - // sp stored to HMR once complete (x2) - "sd t0, 0x20(sp) \n\t" // x5 - "sd t1, 0x28(sp) \n\t" // x6 - "sd t2, 0x30(sp) \n\t" // x7 - : : : "memory"); - - __asm__ __volatile__ ( - "sd gp, 0x10(sp) \n\t" // x3 - "sd tp, 0x18(sp) \n\t" // x4 - "sd x8, 0x38(sp) \n\t" // fp - "sd s1, 0x40(sp) \n\t" // x9 - "sd a0, 0x48(sp) \n\t" // x10 - "sd a1, 0x50(sp) \n\t" // x11 - "sd a2, 0x58(sp) \n\t" // x12 - "sd a3, 0x60(sp) \n\t" // x13 - "sd a4, 0x68(sp) \n\t" // x14 - "sd a5, 0x70(sp) \n\t" // x15 - "sd a6, 0x78(sp) \n\t" // x16 - "sd a7, 0x80(sp) \n\t" // x17 - "sd s2, 0x88(sp) \n\t" // x18 - "sd s3, 0x90(sp) \n\t" // x19 - "sd s4, 0x98(sp) \n\t" // x20 - "sd s5, 0xA0(sp) \n\t" // x21 - "sd s6, 0xA8(sp) \n\t" // x22 - "sd s7, 0xB0(sp) \n\t" // x23 - "sd s8, 0xB8(sp) \n\t" // x24 - "sd s9, 0xC0(sp) \n\t" // x25 - "sd s10, 0xC8(sp) \n\t" // x26 - "sd s11, 0xD0(sp) \n\t" // x27 - "sd t3, 0xD8(sp) \n\t" // x28 - "sd t4, 0xE0(sp) \n\t" // x29 - "sd t5, 0xE8(sp) \n\t" // x30 - "sd t6, 0xF0(sp) \n\t" // x31 - - // Manually store necessary CSRs - // "csrr t1, 0x341 \n\t" // mepc - // "csrr t2, 0x300 \n\t" // mstatus - // "sw t1, 0x78(sp) \n\t" // mepc - // "csrr t1, 0x304 \n\t" // mie - // "sw t2, 0x7C(sp) \n\t" // mstatus - // "csrr t2, 0x305 \n\t" // mtvec - // "sw t1, 0x80(sp) \n\t" // mie - // "csrr t1, 0x340 \n\t" // mscratch - // "sw t2, 0x84(sp) \n\t" // mtvec - // "csrr t2, 0x342 \n\t" // mcause - // "sw t1, 0x88(sp) \n\t" // mscratch - // "csrr t1, 0x343 \n\t" // mtval - // "sw t2, 0x8C(sp) \n\t" // mcause - // "sw t1, 0x90(sp) \n\t" // mtval - : : : "memory"); - - // store sp to hmr core reg - __asm__ __volatile__( - "csrr t0, mhartid \n\t" - "li t1, " QU(HMR_BASE_ADDR + HMR_CORE_OFFS) " \n\t" - "sll t2, t0, " QU(HMR_CORE_SLL) " \n\t" - "add t2, t2, t1 \n\t" - "sw sp, " QU(HMR_CORE_REGS_SP_STORE_REG_OFFSET) "(t2) \n\t" - : : : "memory"); - - // Store the return address in - // the DMR checkpoint register - __asm__ __volatile__( - "la t1, " QU(HMR_DMR_CHECKPOINT) "\n\t" - "sw ra, 0(t1) \n\t" - : : : "memory"); - - // Request for resynchronization (reset) - __asm__ __volatile__( - "la t1, " QU(CHESHIRE_HARTS_SYNC) "\n\t" - "lw t2, 0(t1) \n\t" - "li t3, 1 \n\t" - "sll t3, t3, t0 \n\t" - "or t2, t2, t3 \n\t" - "sw t2, 0(t1) \n\t" - : : : "memory"); - - // Re-enable caches - __asm__ __volatile__ ( - "csrrwi x0, 0x7C1, 0x1 \n\t" - : : : "memory"); - - // Sleep until reset - __asm__ __volatile__("wfi" ::: "memory"); -} - -void __attribute__((naked)) hmr_load_state() { - // Read the SP from HMR register - __asm__ __volatile__( - "csrr t0, mhartid \n\t" // Read core id - "li t1, " QU(HMR_BASE_ADDR + HMR_CORE_OFFS) " \n\t" - "sll t0, t0, " QU(HMR_CORE_SLL) " \n\t" - "add t0, t0, t1 \n\t" - "lw sp, " QU(HMR_CORE_REGS_SP_STORE_REG_OFFSET) "(t0) \n\t" - "slli sp, sp, 0x20 \n\t" - "srli sp, sp, 0x20 \n\t" - // "mv ra, t0 \n\t" - : : : "memory"); - - __asm__ __volatile__ ( - // Manually load necessary CSRs - // "lw t1, 0x78(sp) \n\t" // mepc - // "lw t2, 0x7C(sp) \n\t" // mstatus - // "csrw 0x341, t1 \n\t" // mepc - // "lw t1, 0x80(sp) \n\t" // mie - // "csrw 0x300, t2 \n\t" // mstatus - // "lw t2, 0x84(sp) \n\t" // mtvec - // "csrw 0x304, t1 \n\t" // mie - // "lw t1, 0x88(sp) \n\t" // mscratch - // "csrw 0x305, t2 \n\t" // mtvec - // "lw t2, 0x8C(sp) \n\t" // mcause - // "csrw 0x340, t1 \n\t" // mscratch - // "lw t1, 0x90(sp) \n\t" // mtval - // "csrw 0x342, t2 \n\t" // mcause - // "csrw 0x343, t1 \n\t" // mtval - - // Load registers from stack - // zero not loaded as hardwired (x0) - // ra not touched is used for reboot (x1) - // sp loaded from HMR regs (x2) - "ld gp, 0x10(sp) \n\t" // x3 - "ld tp, 0x18(sp) \n\t" // x4 - "ld t0, 0x20(sp) \n\t" // x5 - "ld t1, 0x28(sp) \n\t" // x6 - "ld t2, 0x30(sp) \n\t" // x7 - "ld x8, 0x38(sp) \n\t" // fp - "ld s1, 0x40(sp) \n\t" // x9 - "ld a0, 0x48(sp) \n\t" // x10 - "ld a1, 0x50(sp) \n\t" // x11 - "ld a2, 0x58(sp) \n\t" // x12 - "ld a3, 0x60(sp) \n\t" // x13 - "ld a4, 0x68(sp) \n\t" // x14 - "ld a5, 0x70(sp) \n\t" // x15 - "ld a6, 0x78(sp) \n\t" // x16 - "ld a7, 0x80(sp) \n\t" // x17 - "ld s2, 0x88(sp) \n\t" // x18 - "ld s3, 0x90(sp) \n\t" // x19 - "ld s4, 0x98(sp) \n\t" // x20 - "ld s5, 0xA0(sp) \n\t" // x21 - "ld s6, 0xA8(sp) \n\t" // x22 - "ld s7, 0xB0(sp) \n\t" // x23 - "ld s8, 0xB8(sp) \n\t" // x24 - "ld s9, 0xC0(sp) \n\t" // x25 - "ld s10, 0xC8(sp) \n\t" // x26 - "ld s11, 0xD0(sp) \n\t" // x27 - "ld t3, 0xD8(sp) \n\t" // x28 - "ld t4, 0xE0(sp) \n\t" // x29 - "ld t5, 0xE8(sp) \n\t" // x30 - "ld t6, 0xF0(sp) \n\t" // x31 - - // Release space on the stack - "add sp, sp, " QU(HmrStateSize) " \n\t" - : : : "memory"); - - // Clear SP register in HMR - // __asm__ __volatile__( - // "sw zero, " QU(HMR_CORE_REGS_SP_STORE_REG_OFFSET) "(ra) \n\t" - // "lw ra, -" QU(HmrStateSize) "(sp) \n\t" - // : : : "memory"); -} diff --git a/sw/include/padframe.h b/sw/include/padframe.h new file mode 100644 index 00000000..cdc90d67 --- /dev/null +++ b/sw/include/padframe.h @@ -0,0 +1,66 @@ +// Copyright 2022 ETH Zurich and University of Bologna. +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +// +// Victor Isachi +// +// Padframe driver + +#ifndef __PADFRAME_H +#define __PADFRAME_H + +#include "io.h" +#include "car_memory_map.h" + +inline void write_padframe_mux(uint8_t mux_sel_reg_offset, uint8_t mux_id){ + writew(mux_id, PADFRAME_BASE_ADDRESS + mux_sel_reg_offset); +} + +void write_padframe_pen(uint8_t cfg_reg_offset, uint8_t pen){ + uint32_t config_reg = readw(PADFRAME_BASE_ADDRESS + cfg_reg_offset); + config_reg = (config_reg & ~0x8 ) | ((pen & 0x1) << 3); + writew(config_reg, PADFRAME_BASE_ADDRESS + cfg_reg_offset); +} + +void write_padframe_psel(uint8_t cfg_reg_offset, uint8_t psel){ + uint32_t config_reg = readw(PADFRAME_BASE_ADDRESS + cfg_reg_offset); + config_reg = (config_reg & ~0x10 ) | ((psel & 0x1) << 4); + writew(config_reg, PADFRAME_BASE_ADDRESS + cfg_reg_offset); +} + +void padframe_ethernet_cfg() { + // Configuring padframe - mux + write_padframe_mux(PADFRAME_CONFIG_MUXED_V_07_MUX_SEL, PADFRAME_MUXED_V_07_SEL_ETHERNET_RXCK); + write_padframe_mux(PADFRAME_CONFIG_MUXED_V_08_MUX_SEL, PADFRAME_MUXED_V_08_SEL_ETHERNET_RXCTL); + write_padframe_mux(PADFRAME_CONFIG_MUXED_V_09_MUX_SEL, PADFRAME_MUXED_V_09_SEL_ETHERNET_RXD_0); + write_padframe_mux(PADFRAME_CONFIG_MUXED_V_10_MUX_SEL, PADFRAME_MUXED_V_10_SEL_ETHERNET_RXD_1); + write_padframe_mux(PADFRAME_CONFIG_MUXED_V_11_MUX_SEL, PADFRAME_MUXED_V_11_SEL_ETHERNET_RXD_2); + write_padframe_mux(PADFRAME_CONFIG_MUXED_V_12_MUX_SEL, PADFRAME_MUXED_V_12_SEL_ETHERNET_RXD_3); + write_padframe_mux(PADFRAME_CONFIG_MUXED_V_13_MUX_SEL, PADFRAME_MUXED_V_13_SEL_ETHERNET_TXCK); + write_padframe_mux(PADFRAME_CONFIG_MUXED_V_14_MUX_SEL, PADFRAME_MUXED_V_14_SEL_ETHERNET_TXCTL); + write_padframe_mux(PADFRAME_CONFIG_MUXED_V_15_MUX_SEL, PADFRAME_MUXED_V_15_SEL_ETHERNET_TXD_0); + write_padframe_mux(PADFRAME_CONFIG_MUXED_V_16_MUX_SEL, PADFRAME_MUXED_V_16_SEL_ETHERNET_TXD_1); + write_padframe_mux(PADFRAME_CONFIG_MUXED_V_17_MUX_SEL, PADFRAME_MUXED_V_17_SEL_ETHERNET_TXD_2); + write_padframe_mux(PADFRAME_CONFIG_MUXED_H_00_MUX_SEL, PADFRAME_MUXED_H_00_SEL_ETHERNET_TXD_3); + write_padframe_mux(PADFRAME_CONFIG_MUXED_H_01_MUX_SEL, PADFRAME_MUXED_H_01_SEL_ETHERNET_MD); + write_padframe_mux(PADFRAME_CONFIG_MUXED_H_02_MUX_SEL, PADFRAME_MUXED_H_02_SEL_ETHERNET_MDC); + write_padframe_mux(PADFRAME_CONFIG_MUXED_H_03_MUX_SEL, PADFRAME_MUXED_H_03_SEL_ETHERNET_RST_N); + // Configuring padframe - pullup + write_padframe_pen(PADFRAME_CONFIG_MUXED_V_07_CFG, 0x1); write_padframe_psel(PADFRAME_CONFIG_MUXED_V_07_CFG, 0x1); + write_padframe_pen(PADFRAME_CONFIG_MUXED_V_08_CFG, 0x1); write_padframe_psel(PADFRAME_CONFIG_MUXED_V_08_CFG, 0x1); + write_padframe_pen(PADFRAME_CONFIG_MUXED_V_09_CFG, 0x1); write_padframe_psel(PADFRAME_CONFIG_MUXED_V_09_CFG, 0x1); + write_padframe_pen(PADFRAME_CONFIG_MUXED_V_10_CFG, 0x1); write_padframe_psel(PADFRAME_CONFIG_MUXED_V_10_CFG, 0x1); + write_padframe_pen(PADFRAME_CONFIG_MUXED_V_11_CFG, 0x1); write_padframe_psel(PADFRAME_CONFIG_MUXED_V_11_CFG, 0x1); + write_padframe_pen(PADFRAME_CONFIG_MUXED_V_12_CFG, 0x1); write_padframe_psel(PADFRAME_CONFIG_MUXED_V_12_CFG, 0x1); + write_padframe_pen(PADFRAME_CONFIG_MUXED_V_13_CFG, 0x1); write_padframe_psel(PADFRAME_CONFIG_MUXED_V_13_CFG, 0x1); + write_padframe_pen(PADFRAME_CONFIG_MUXED_V_14_CFG, 0x1); write_padframe_psel(PADFRAME_CONFIG_MUXED_V_14_CFG, 0x1); + write_padframe_pen(PADFRAME_CONFIG_MUXED_V_15_CFG, 0x1); write_padframe_psel(PADFRAME_CONFIG_MUXED_V_15_CFG, 0x1); + write_padframe_pen(PADFRAME_CONFIG_MUXED_V_16_CFG, 0x1); write_padframe_psel(PADFRAME_CONFIG_MUXED_V_16_CFG, 0x1); + write_padframe_pen(PADFRAME_CONFIG_MUXED_V_17_CFG, 0x1); write_padframe_psel(PADFRAME_CONFIG_MUXED_V_17_CFG, 0x1); + write_padframe_pen(PADFRAME_CONFIG_MUXED_H_00_CFG, 0x1); write_padframe_psel(PADFRAME_CONFIG_MUXED_H_00_CFG, 0x1); + write_padframe_pen(PADFRAME_CONFIG_MUXED_H_01_CFG, 0x1); write_padframe_psel(PADFRAME_CONFIG_MUXED_H_01_CFG, 0x1); + write_padframe_pen(PADFRAME_CONFIG_MUXED_H_02_CFG, 0x1); write_padframe_psel(PADFRAME_CONFIG_MUXED_H_02_CFG, 0x1); + write_padframe_pen(PADFRAME_CONFIG_MUXED_H_03_CFG, 0x1); write_padframe_psel(PADFRAME_CONFIG_MUXED_H_03_CFG, 0x1); +} + +#endif /*__PADFRAME_H*/ diff --git a/sw/include/regs/soc_ctrl.h b/sw/include/regs/soc_ctrl.h index 5f127b21..cd4eda95 100644 --- a/sw/include/regs/soc_ctrl.h +++ b/sw/include/regs/soc_ctrl.h @@ -141,42 +141,48 @@ extern "C" { #define CARFIELD_L2_CLK_EN_REG_OFFSET 0x80 #define CARFIELD_L2_CLK_EN_L2_CLK_EN_BIT 0 -// Periph Domain pll select (0 -> host pll, 1 -> alt PLL, 2 -> per pll) +// Periph Domain fll select (0 -> host fll, 1 -> alt fll, 2 -> per fll, 3 -> +// secd fll) #define CARFIELD_PERIPH_CLK_SEL_REG_OFFSET 0x84 #define CARFIELD_PERIPH_CLK_SEL_PERIPH_CLK_SEL_MASK 0x3 #define CARFIELD_PERIPH_CLK_SEL_PERIPH_CLK_SEL_OFFSET 0 #define CARFIELD_PERIPH_CLK_SEL_PERIPH_CLK_SEL_FIELD \ ((bitfield_field32_t) { .mask = CARFIELD_PERIPH_CLK_SEL_PERIPH_CLK_SEL_MASK, .index = CARFIELD_PERIPH_CLK_SEL_PERIPH_CLK_SEL_OFFSET }) -// Safety Island pll select (0 -> host pll, 1 -> alt PLL, 2 -> per pll) +// Safety Island fll select (0 -> host fll, 1 -> alt fll, 2 -> per fll, 3 -> +// secd fll) #define CARFIELD_SAFETY_ISLAND_CLK_SEL_REG_OFFSET 0x88 #define CARFIELD_SAFETY_ISLAND_CLK_SEL_SAFETY_ISLAND_CLK_SEL_MASK 0x3 #define CARFIELD_SAFETY_ISLAND_CLK_SEL_SAFETY_ISLAND_CLK_SEL_OFFSET 0 #define CARFIELD_SAFETY_ISLAND_CLK_SEL_SAFETY_ISLAND_CLK_SEL_FIELD \ ((bitfield_field32_t) { .mask = CARFIELD_SAFETY_ISLAND_CLK_SEL_SAFETY_ISLAND_CLK_SEL_MASK, .index = CARFIELD_SAFETY_ISLAND_CLK_SEL_SAFETY_ISLAND_CLK_SEL_OFFSET }) -// Security Island pll select (0 -> host pll, 1 -> alt PLL, 2 -> per pll) +// Security Island fll select (0 -> host fll, 1 -> alt fll, 2 -> per fll, 3 +// -> secd fll) #define CARFIELD_SECURITY_ISLAND_CLK_SEL_REG_OFFSET 0x8c #define CARFIELD_SECURITY_ISLAND_CLK_SEL_SECURITY_ISLAND_CLK_SEL_MASK 0x3 #define CARFIELD_SECURITY_ISLAND_CLK_SEL_SECURITY_ISLAND_CLK_SEL_OFFSET 0 #define CARFIELD_SECURITY_ISLAND_CLK_SEL_SECURITY_ISLAND_CLK_SEL_FIELD \ ((bitfield_field32_t) { .mask = CARFIELD_SECURITY_ISLAND_CLK_SEL_SECURITY_ISLAND_CLK_SEL_MASK, .index = CARFIELD_SECURITY_ISLAND_CLK_SEL_SECURITY_ISLAND_CLK_SEL_OFFSET }) -// PULP Cluster pll select (0 -> host pll, 1 -> alt PLL, 2 -> per pll) +// PULP Cluster fll select (0 -> host fll, 1 -> alt fll, 2 -> per fll, 3 -> +// secd fll) #define CARFIELD_PULP_CLUSTER_CLK_SEL_REG_OFFSET 0x90 #define CARFIELD_PULP_CLUSTER_CLK_SEL_PULP_CLUSTER_CLK_SEL_MASK 0x3 #define CARFIELD_PULP_CLUSTER_CLK_SEL_PULP_CLUSTER_CLK_SEL_OFFSET 0 #define CARFIELD_PULP_CLUSTER_CLK_SEL_PULP_CLUSTER_CLK_SEL_FIELD \ ((bitfield_field32_t) { .mask = CARFIELD_PULP_CLUSTER_CLK_SEL_PULP_CLUSTER_CLK_SEL_MASK, .index = CARFIELD_PULP_CLUSTER_CLK_SEL_PULP_CLUSTER_CLK_SEL_OFFSET }) -// Spatz Cluster pll select (0 -> host pll, 1 -> alt PLL, 2 -> per pll) +// Spatz Cluster fll select (0 -> host fll, 1 -> alt fll, 2 -> per fll, 3 -> +// secd fll) #define CARFIELD_SPATZ_CLUSTER_CLK_SEL_REG_OFFSET 0x94 #define CARFIELD_SPATZ_CLUSTER_CLK_SEL_SPATZ_CLUSTER_CLK_SEL_MASK 0x3 #define CARFIELD_SPATZ_CLUSTER_CLK_SEL_SPATZ_CLUSTER_CLK_SEL_OFFSET 0 #define CARFIELD_SPATZ_CLUSTER_CLK_SEL_SPATZ_CLUSTER_CLK_SEL_FIELD \ ((bitfield_field32_t) { .mask = CARFIELD_SPATZ_CLUSTER_CLK_SEL_SPATZ_CLUSTER_CLK_SEL_MASK, .index = CARFIELD_SPATZ_CLUSTER_CLK_SEL_SPATZ_CLUSTER_CLK_SEL_OFFSET }) -// L2 Memory pll select (0 -> host pll, 1 -> alt PLL, 2 -> per pll) +// L2 Memory fll select (0 -> host fll, 1 -> alt fll, 2 -> per fll, 3 -> secd +// fll) #define CARFIELD_L2_CLK_SEL_REG_OFFSET 0x98 #define CARFIELD_L2_CLK_SEL_L2_CLK_SEL_MASK 0x3 #define CARFIELD_L2_CLK_SEL_L2_CLK_SEL_OFFSET 0 @@ -308,6 +314,25 @@ extern "C" { #define CARFIELD_HYPERBUS_CLK_DIV_VALUE_HYPERBUS_CLK_DIV_VALUE_FIELD \ ((bitfield_field32_t) { .mask = CARFIELD_HYPERBUS_CLK_DIV_VALUE_HYPERBUS_CLK_DIV_VALUE_MASK, .index = CARFIELD_HYPERBUS_CLK_DIV_VALUE_HYPERBUS_CLK_DIV_VALUE_OFFSET }) +// Streamer clock divider enable +#define CARFIELD_STREAMER_CLK_DIV_ENABLE_REG_OFFSET 0xfc +#define CARFIELD_STREAMER_CLK_DIV_ENABLE_STREAMER_CLK_DIV_ENABLE_BIT 0 + +// Streamer clock divider value +#define CARFIELD_STREAMER_CLK_DIV_VALUE_REG_OFFSET 0x100 +#define CARFIELD_STREAMER_CLK_DIV_VALUE_STREAMER_CLK_DIV_VALUE_MASK 0x3f +#define CARFIELD_STREAMER_CLK_DIV_VALUE_STREAMER_CLK_DIV_VALUE_OFFSET 0 +#define CARFIELD_STREAMER_CLK_DIV_VALUE_STREAMER_CLK_DIV_VALUE_FIELD \ + ((bitfield_field32_t) { .mask = CARFIELD_STREAMER_CLK_DIV_VALUE_STREAMER_CLK_DIV_VALUE_MASK, .index = CARFIELD_STREAMER_CLK_DIV_VALUE_STREAMER_CLK_DIV_VALUE_OFFSET }) + +// Streamer general interrupt +#define CARFIELD_STREAMER_GENERAL_IRQ_REG_OFFSET 0x104 +#define CARFIELD_STREAMER_GENERAL_IRQ_STREAMER_GENERAL_IRQ_BIT 0 + +// SpaceWire general interrupt +#define CARFIELD_SPW_GENERAL_IRQ_REG_OFFSET 0x108 +#define CARFIELD_SPW_GENERAL_IRQ_SPW_GENERAL_IRQ_BIT 0 + #ifdef __cplusplus } // extern "C" #endif diff --git a/sw/include/tasi.h b/sw/include/tasi.h new file mode 100644 index 00000000..8f0ba3fa --- /dev/null +++ b/sw/include/tasi.h @@ -0,0 +1,325 @@ + +// Copyright 2023 ETH Zurich and University of Bologna. +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +// +// Robert Balas +// + +/* Description: Memory mapped register I/O access + */ + +#ifndef __TASI_H +#define __TASI_H + +#include "regs/cheshire.h" +#include "dif/clint.h" +#include "dif/uart.h" +#include "params.h" +#include "util.h" +#include "car_util.h" +#include "printf.h" +#include "regs/system_timer.h" +#include "csr.h" + + +#define MHZ 100 + +#define BIT0 0 +#define BIT1 1 +#define BIT2 2 +#define BIT3 3 +#define BIT4 4 +#define BIT5 5 +#define BIT6 6 +#define BIT7 7 +#define BIT8 8 +#define BIT9 9 +#define BIT10 10 +#define BIT11 11 +#define BIT12 12 +#define BIT13 13 +#define BIT14 14 +#define BIT15 15 +#define BIT16 16 +#define BIT17 17 +#define BIT18 18 +#define BIT19 19 +#define BIT20 20 +#define BIT21 21 +#define BIT22 22 +#define BIT23 23 +#define BIT24 24 +#define BIT25 25 +#define BIT26 26 +#define BIT27 27 +#define BIT28 28 +#define BIT29 29 +#define BIT30 30 +#define BIT31 31 + +#define STREAMER_REG_BUS 0x20009000 +#define STREAMER_APB 0x20011000 +#define SPW_REG_BUS 0x20019000 +#define SPW_APB 0x20019100 + +//Streamer + +#define STREAMER_PTME_CONFIG (STREAMER_APB | 0x000) +#define STREAMER_PTME_DATA (STREAMER_APB | 0x400) +#define STREAMER_PTD_DATA (STREAMER_APB | 0x800) +#define STREAMER_HPC_LLC_DATA (STREAMER_APB | 0xC00) + + +#define STREAMER_OBT_ATSS (STREAMER_REG_BUS | 0x120) +#define STREAMER_OBT_ATSSS (STREAMER_REG_BUS | 0x124) + +#define STREAMER_TC_BUFFER_STATUS (STREAMER_REG_BUS | 0x280) +#define STREAMER_TC_BUFFER_RELEASE (STREAMER_REG_BUS | 0x284) +#define STREAMER_HPC_LLC_BUFFER_BUSY_SET (STREAMER_REG_BUS | 0x288) +#define STREAMER_HPC_LLC_BUFFER_STATUS (STREAMER_REG_BUS | 0x28C) +#define STREAMER_HPTM_PACKET_HEADER (STREAMER_REG_BUS | 0x290) + +#define STREAMER_INTERRUPT_MASK (STREAMER_REG_BUS | 0x294) +#define STREAMER_INTERRUPT_CLEAR (STREAMER_REG_BUS | 0x298) +#define STREAMER_INTERRUPT_FORCE (STREAMER_REG_BUS | 0x29C) +#define STREAMER_INTERRUPT_PENDING (STREAMER_REG_BUS | 0x2A0) + +//#define STREAMER_INTERUPT_TC 0x1 +//#define STREAMER_INTERUPT_PPS 0x2 +//#define STREAMER_INTERUPT_TS 0x4 +//#define STREAMER_INTERUPT_RTC 0x8 + +#define STREAMER_PTME_CONFIG_READY BIT6 + +#define STREAMER_INTERRUPT_TC BIT0 +#define STREAMER_INTERRUPT_PPS BIT1 +#define STREAMER_INTERRUPT_TS BIT2 +#define STREAMER_INTERRUPT_RTC BIT3 + + + +#define STREAMER_INTERRUPT_TC_ABS_VALUE (1< return 1; + // If hart_id() == 1 -> return 0; + // Hart 0 enters first + if (hart_id() != 0) wfi(); + // Update clock divider value and re-enable streamer clock divider + writew(1, car_soc_ctrl + CARFIELD_STREAMER_CLK_DIV_VALUE_REG_OFFSET); + writew(0x1, car_soc_ctrl + CARFIELD_STREAMER_CLK_DIV_ENABLE_REG_OFFSET); +} + + + +void wait_us(unsigned int us); + +void wait_us(unsigned int us) +{ + unsigned long start_time = 0; + unsigned long end_time = 0; + + get_time_us (&start_time); + + do{ + get_time_us (&end_time); + } + while(end_time> j) & 1) * pow(2,24-j)); //due to lack of pow in math.h + time_s += (((atsss_internal >> j) & 1) * pow); + pow*=2; + } + + //printf("time_s = %f \n",time_s); + + //set us to s + time_us_internal = time_s*1000000; + //add seconds part + time_us_internal += atss_internal*1000000; + //printf("time_us %lu \n",time_us); + //assign return value to parameters + *time_us = time_us_internal; + *atss = atss_internal; + *atsss = atsss_internal; + +} + +void start_time (unsigned long * time_us) +{ + get_time_us(time_us); +} + +void end_time (unsigned long time_us,unsigned long * duration) +{ + unsigned long tmp; + + get_time_us(&tmp); + + *duration = tmp - time_us; +} + +void start_time_streamer (unsigned long * time_us) +{ + unsigned int atss,atsss; + + get_time_streamer_us(&atss,&atsss,time_us); +} + +void end_time_streamer (unsigned long time_us,unsigned long * duration) +{ + unsigned long tmp; + unsigned int atss,atsss; + + get_time_streamer_us(&atss,&atsss,&tmp); + + //calculate duration + *duration = tmp - time_us; +} + + +#endif + + + diff --git a/sw/tests/bare-metal/hostd/ethernet.c b/sw/tests/bare-metal/hostd/ethernet.c index 58f27754..cde3c2c4 100644 --- a/sw/tests/bare-metal/hostd/ethernet.c +++ b/sw/tests/bare-metal/hostd/ethernet.c @@ -8,12 +8,15 @@ #include "car_memory_map.h" #include "io.h" #include "sw/device/lib/dif/dif_rv_plic.h" +#include "regs/system_timer.h" #include #include #include #include "params.h" #include "printf.h" #include "util.h" +#include "padframe.h" +#include "fll.h" static dif_rv_plic_t plic0; @@ -46,11 +49,23 @@ static dif_rv_plic_t plic0; #define L2_TX_BASE 0x78000000 #define L2_RX_BASE 0x78001000 +#define FLL_WAIT_CYCLES 10000 + int main(void) { // Put SMP Hart to sleep if (hart_id() != 0) wfi(); + // Configure padframe for ethernet use. + padframe_ethernet_cfg(); + + // Setup the peripheral FLL to work at 500 MHz + set_periph_fll_div2(500 /* MHz */); + + // Wait for FLL clk out to stabilize + for (int i = 0; i < FLL_WAIT_CYCLES; i++) + asm volatile("addi x0, x0, 0" ::); + int prio = 0x1; bool t; unsigned global_irq_en = 0x00001808; @@ -92,11 +107,11 @@ int main(void) { // DMA Source Address *reg32(CAR_ETHERNET_BASE_ADDR, IDMA_SRC_ADDR_OFFSET) = L2_TX_BASE; // DMA Destination Address - *reg32(CAR_ETHERNET_BASE_ADDR, IDMA_DST_ADDR_OFFSET) = 0x0; + *reg32(CAR_ETHERNET_BASE_ADDR, IDMA_DST_ADDR_OFFSET) = 0x14000000; // Data length *reg32(CAR_ETHERNET_BASE_ADDR, IDMA_LENGTH_OFFSET) = DATA_CHUNK*BYTE_SIZE; // Source Protocol - *reg32(CAR_ETHERNET_BASE_ADDR, IDMA_SRC_PROTO_OFFSET) = 0x0; + *reg32(CAR_ETHERNET_BASE_ADDR, IDMA_SRC_PROTO_OFFSET) = 0x5; // Destination Protocol *reg32(CAR_ETHERNET_BASE_ADDR, IDMA_DST_PROTO_OFFSET) = 0x5; diff --git a/sw/tests/bare-metal/hostd/fll_basic.c b/sw/tests/bare-metal/hostd/fll_basic.c new file mode 100644 index 00000000..b4658f66 --- /dev/null +++ b/sw/tests/bare-metal/hostd/fll_basic.c @@ -0,0 +1,68 @@ +// Copyright 2023 ETH Zurich and University of Bologna. +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +// +// Victor Isachi +// +// Simple FLL test - no automatic checking + +#include "regs/cheshire.h" +#include "dif/clint.h" +#include "dif/uart.h" +#include "params.h" +#include "util.h" +#include "car_util.h" +#include "printf.h" +#include "fll.h" + +int main(void) { + + // Put SMP Hart to sleep + if (hart_id() != 0) wfi(); + + // Stand-alone mode + + set_fll_dco_code(0x1F5, FLL_HOST_ID); + set_fll_clk_div(0x1, FLL_HOST_ID); + + set_fll_dco_code(0x1F5, FLL_PERIPH_ID); + set_fll_clk_div(0x1, FLL_PERIPH_ID); + + set_fll_dco_code(0x1F5, FLL_ALT_ID); + set_fll_clk_div(0x1, FLL_ALT_ID); + + set_fll_dco_code(0x1F5, FLL_SECD_ID); + set_fll_clk_div(0x1, FLL_SECD_ID); + + set_fll_dco_code(0x1F5, FLL_RT_ID); + set_fll_clk_div(0x1, FLL_RT_ID); + + // Normal mode + + set_fll_clk_div(0x2, FLL_HOST_ID); + set_fll_clk_mul(0x63, FLL_HOST_ID); + fll_normal(FLL_HOST_ID); + + set_fll_clk_div(0x2, FLL_PERIPH_ID); + set_fll_clk_mul(0x63, FLL_PERIPH_ID); + fll_normal(FLL_PERIPH_ID); + + set_fll_clk_div(0x2, FLL_ALT_ID); + set_fll_clk_mul(0x63, FLL_ALT_ID); + fll_normal(FLL_ALT_ID); + + set_fll_clk_div(0x2, FLL_SECD_ID); + set_fll_clk_mul(0x63, FLL_SECD_ID); + fll_normal(FLL_SECD_ID); + + set_fll_clk_div(0x2, FLL_RT_ID); + set_fll_clk_mul(0x63, FLL_RT_ID); + fll_normal(FLL_RT_ID); + + // Init the HW + car_init_start(); + + // NEED TO MANUALLY VERIFY THE CORECTNESS OF THE GENERATED CLOCKS + + return 0; +} diff --git a/sw/tests/bare-metal/hostd/hmr.c b/sw/tests/bare-metal/hostd/hmr.c index 1cf346b2..dbdd268a 100644 --- a/sw/tests/bare-metal/hostd/hmr.c +++ b/sw/tests/bare-metal/hostd/hmr.c @@ -6,46 +6,38 @@ // // Test for HMR functionalities. -#include "car_util.h" +#include "util.h" #include "printf.h" #include "hmr.h" int main(void) { - // We read the number of available harts. - uint32_t NumHarts = readw(CHESHIRE_NUM_INT_HARTS); - uint32_t OtherHart = NumHarts - 1 - hart_id(); // If hart_id() == 0 -> return 1; - // If hart_id() == 1 -> return 0; - - // Hart 0 enters first - if (hart_id() != 0) wfi(); - - printf("%d!\n", hart_id()); - - // Only hart 0 gets here - if (hart_id() == 0){ - // Check if DMR is enabled. If not, enable it - if (!readw(HMR_DMR_ENABLE)) - writew(0x1, HMR_DMR_ENABLE); - - // Wake up sleeping hart - wakeup_hart(OtherHart); - } - - hmr_store_state(); // -> Save state on top of the stack - // Save sp (x2) in HMR dedicated reg - // Save ra (x1) in DMR checkpoint reg - // Write synchronization request - // wfi() until reset - - // Both harts restart from here, but are locked as one - hmr_load_state(); // -> Code restarts executing from here because we - // re-boot from the return address (x1) - // Re-loads the saved state - // Restores the sp - - printf("DMR: we are locked as hart %d!\n", hart_id()); - - // The two locked harts return - return 0; + // Hart 0 enters first + printf("%d!\n", hart_id()); + + // Only hart 0 gets here + if (hart_id() == 0) { + // Check if DMR is enabled. If not, enable it + if (!(*reg32(&__base_hmr, HMR_DMR_ENABLE))) *reg32(&__base_hmr, HMR_DMR_ENABLE) = 0x1; + // Wake up the SMP core + smp_resume(); + } + + chs_hmr_store_state(); // -> Save state on top of the stack + // Fence.i to flush caches + // Save sp (x2) in HMR dedicated reg + // Save ra (x1) in DMR checkpoint reg + // Write synchronization request + // wfi() until reset + + // Both harts restart from here, but are locked as one + chs_hmr_load_state(); // -> Code restarts executing from here because we + // re-boot from the return address (x1) + // Re-loads the saved state + // Restores the sp + + printf("DMR: %d!\n", hart_id()); + + // The two locked harts return + return 0; } diff --git a/sw/tests/bare-metal/hostd/streamer.c b/sw/tests/bare-metal/hostd/streamer.c new file mode 100644 index 00000000..a625139a --- /dev/null +++ b/sw/tests/bare-metal/hostd/streamer.c @@ -0,0 +1,108 @@ +// Copyright 2023 ETH Zurich and University of Bologna. +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +// +// Yvan Tortorella +// +// Streamer access test. + +#include "car_util.h" +#include "car_params.h" +#include "regs/soc_ctrl.h" +#include "printf.h" + +#define PTME_ENABLE_ADDR (TCTM_STREAMER_CFG_PTME_BASE + 0x04) +#define PTME_VIRT_CHANNELA_CFG_ADDR (TCTM_STREAMER_CFG_PTME_BASE + 0x10) +#define PTME_VIRT_CHANNELB_CFG_ADDR (TCTM_STREAMER_CFG_PTME_BASE + 0x14) +#define TM_FRAME_ADDR (TCTM_STREAMER_CFG_PTME_BASE + 0x48) +#define PTME_ENCODING_CFG_ADDR (TCTM_STREAMER_CFG_PTME_BASE + 0x60) +#define PTME_CLK_PRESCALER_ADDR (TCTM_STREAMER_CFG_PTME_BASE + 0x68) +#define BIT_CLK_DIVISOR_ADDR (TCTM_STREAMER_CFG_PTME_BASE + 0x6C) +#define TME_INIT_ADDR (TCTM_STREAMER_CFG_PTME_BASE + 0x00) +#define STREAMER_PENDING_IRQ_ADDR (TCTM_STREAMER_CFG_MAP_ROUTER_BASE + 0x20) + +#define PTME_ENABLE_VALUE 0x00010000 +#define TM_FRAME_CFG_VALUE 0x3FFE0020 +#define PTME_CLK_PRESCALE_VALUE 0x00000000 +#define BIT_CLK_DIVISOR_VALUE 0x00000000 +#define TME_INIT_VALUE 0x0000AAAA +#define PTME_ACTIVATE_VALUE 0x00000008 +#define PTME_DEACTIVATE_VALUE 0x00000000 +#define PTME_ENCODING_CFG_VALUE 0x2 + +#define PTME_ENABLE_RETURN_VALUE 0x00010001 +#define PTME_VIRT_CHANNELA_CFG_VALUE 0x21 +#define PTME_VIRT_CHANNELB_CFG_VALUE 0x31 + +int main(void) { + + if (hart_id() != 0) wfi(); + + // Update clock divider value and re-enable streamer clock divider + writew(10, car_soc_ctrl + CARFIELD_STREAMER_CLK_DIV_VALUE_REG_OFFSET); + writew(0x1, car_soc_ctrl + CARFIELD_STREAMER_CLK_DIV_ENABLE_REG_OFFSET); + + uint32_t error = 0; + + const char packet[] = { 0x09, 0x4C, 0xD2, 0x35, + 0x00, 0x1F, 0xAF, 0x01, + 0x00, 0x00, 0xAF, 0x02, + 0x00, 0x01, 0xAF, 0x03, + 0x00, 0x02, 0xAF, 0x04, + 0x00, 0x03, 0xAF, 0x05, + 0x00, 0x04, 0xAF, 0x06, + 0x00, 0x05, 0xAF, 0x07, + 0x00, 0x06, 0xAF, 0x08, + 0x00, 0x07 }; + + while ( readw(STREAMER_PENDING_IRQ_ADDR) == 0 ); + + // Start reading TC buffer + for (int i = 0; i < 4; i++) + readb(TCTM_STREAMER_APB_TC_BUFFER_BASE + i); + + // Write HPC LLC + for (int i = 0; i < 4; i++) + writeb(i, TCTM_STREAMER_APB_TX_BUFFER_BASE + i); + + // Configure telemetry frame + writew(TM_FRAME_CFG_VALUE, TM_FRAME_ADDR); + + writew(PTME_ENCODING_CFG_VALUE, PTME_ENCODING_CFG_ADDR); + + writew(PTME_VIRT_CHANNELA_CFG_VALUE, PTME_VIRT_CHANNELA_CFG_ADDR); + + writew(PTME_VIRT_CHANNELB_CFG_VALUE, PTME_VIRT_CHANNELB_CFG_ADDR); + + // Set PTME clock pre-scaler + writew(PTME_CLK_PRESCALE_VALUE, PTME_CLK_PRESCALER_ADDR); + // Set bit clock divisor + writew(BIT_CLK_DIVISOR_VALUE, BIT_CLK_DIVISOR_ADDR); + // TME_INIT (?) + writew(TME_INIT_VALUE, TME_INIT_ADDR); + // Enable PTME + writew(PTME_ENABLE_VALUE, PTME_ENABLE_ADDR); + + // Check the written registers for errors + error += (readw(PTME_ENABLE_ADDR) != PTME_ENABLE_RETURN_VALUE); + error += (readw(TM_FRAME_ADDR) != TM_FRAME_CFG_VALUE); + error += (readw(PTME_CLK_PRESCALER_ADDR) != PTME_CLK_PRESCALE_VALUE); + error += (readw(BIT_CLK_DIVISOR_ADDR) != BIT_CLK_DIVISOR_VALUE); + error += (readw(TME_INIT_ADDR) != TME_INIT_VALUE); + + // Manifest interest in sending data (specifying only LSB is meaningful) + writew(PTME_ACTIVATE_VALUE, TCTM_STREAMER_APB_PTME_CFG + 0x00); + + // Push data into the TM buffer + for (int i = 0; i < sizeof(packet); i++) + writew(packet[i], TCTM_STREAMER_APB_TM_PACKET_BASE + 0x04*i); + + // Disable ACTIVE signal to start the transmission + writew(PTME_DEACTIVATE_VALUE, TCTM_STREAMER_APB_PTME_CFG); + + // TODO: Should we wait for an event or something here? + if (error == 0) printf("Success!\n"); + else printf("Failed!\n"); + + return error; +} diff --git a/sw/tests/bare-metal/hostd/system_timer_test.c b/sw/tests/bare-metal/hostd/system_timer_test.c index 7f5295b1..d92522bd 100644 --- a/sw/tests/bare-metal/hostd/system_timer_test.c +++ b/sw/tests/bare-metal/hostd/system_timer_test.c @@ -2,7 +2,7 @@ // Licensed under the Apache License, Version 2.0, see LICENSE for details. // SPDX-License-Identifier: Apache-2.0 // -// Alessandro Ottaviano +// Yvan Tortorella // #include "car_memory_map.h" @@ -14,47 +14,54 @@ #include "regs/system_timer.h" #include "util.h" #include "car_util.h" +#include "printf.h" -// TODO: This test is really brittle. Its only purpose is to test timer accesses when the timer is -// configured in freerunning mode and check if the value is within a sensible range. A better test -// uses a periodic timer and checks if the periodic interrupts are taken. It will replace the -// current test when interrupts are tested in the SoC. +// In order to test the timer functionality, we reprogram the timer to do +// consecutively the same count, and compare the result. We set the number +// of runs to 4 so that the core can warm up the caches during the first two +// iterations, and use the last 2 to compare the results. An empyrical analysis +// shows that, in case of 500 rounds, the difference between two consecutive +// reads is around 2% with no cache warmup, and drops under 1% with a single +// cache warmup. In case of 250 rounds, with no cache warmup the difference is 4%. -#define assert(expression) \ - do { \ - if (!expression) { \ - return 1; \ - } \ - } while (0) - -#define DUMMY_TIMER_CNT_GOLDEN_MIN 20000 -#define DUMMY_TIMER_CNT_GOLDEN_MAX 21000 +#define Runs 4 +#define Rounds 500 int main(void) { // Put SMP Hart to sleep if (hart_id() != 0) wfi(); - // Reset system timer - writed(1, CAR_SYSTEM_TIMER_BASE_ADDR + TIMER_RESET_LO_OFFSET); + volatile int time [Runs]; - // Start system timer - writed(1, CAR_SYSTEM_TIMER_BASE_ADDR + TIMER_START_LO_OFFSET); + for (int i = 0; i < Runs; i++) { + // Reset system timer + writed(1, CAR_SYSTEM_TIMER_BASE_ADDR + TIMER_RESET_LO_OFFSET); + // Start system timer + writed(1, CAR_SYSTEM_TIMER_BASE_ADDR + TIMER_START_LO_OFFSET); - for (volatile int i = 0; i < 500; i++) - ; + for (volatile int i = 0; i < Rounds; i++) + ; + fencei(); - // Stop system timer - writed(0, CAR_SYSTEM_TIMER_BASE_ADDR + TIMER_CFG_LO_OFFSET); + // Stop system timer + writed(0, CAR_SYSTEM_TIMER_BASE_ADDR + TIMER_CFG_LO_OFFSET); + // Get system timer count + time[i] = readd(CAR_SYSTEM_TIMER_BASE_ADDR + TIMER_CNT_LO_OFFSET); + } - // Get system timer count - volatile int time = readd(CAR_SYSTEM_TIMER_BASE_ADDR + TIMER_CNT_LO_OFFSET); + // Extract the minimum value read from the timer and compute the difference + volatile int min, max; - // Note: the result is checked against a golden value that is probed from - // the waveforms, to check if the value is correctly read from sw. - if (time <= DUMMY_TIMER_CNT_GOLDEN_MIN || time >= DUMMY_TIMER_CNT_GOLDEN_MAX) { - return 1; + if (time[Runs-2] < time[Runs-1]) { + min = time[Runs-2]; + max = time[Runs-1]; + } else { + min = time[Runs-1]; + max = time[Runs-2]; } - return 0; + float diff = 100*(max - min)/min; + + return (diff > 1.0); } diff --git a/sw/tests/bare-metal/hostd/tasi_apb_test.c b/sw/tests/bare-metal/hostd/tasi_apb_test.c new file mode 100644 index 00000000..557bc78f --- /dev/null +++ b/sw/tests/bare-metal/hostd/tasi_apb_test.c @@ -0,0 +1,56 @@ + +#include "regs/cheshire.h" +#include "dif/clint.h" +#include "dif/uart.h" +#include "params.h" +#include "util.h" +#include "car_util.h" +#include "printf.h" +#include "tasi.h" + + +int main(void) { + + + + unsigned int i; + unsigned int len; + unsigned int offset; + unsigned char tmp; + //printf("TEST - Apb module \n\n"); + + //STREAMER_PTME_DATA + len=1024; + offset = STREAMER_PTME_DATA ; + for(i=0;i enable TME + //W_REG(STREAMER_TME_ENACONF) = 0xFFFFF001; //0x00010000; --> CBA=b1111 + + + + //check interface Ready + //wait bit Idle is set + WAIT_BIT_SET(R_REG(STREAMER_PTME_CONFIG),STREAMER_PTME_CONFIG_READY); + + + //enable packet + //W_REG(STREAMER_PTME_CONFIG) = 8 ;//0xB; //bit 3 Valid to 1 and Size to 32bit + SET_BIT(W_REG(STREAMER_PTME_CONFIG),BIT3); + + //write packet with 8bit access + for(i=0;i end of packet + + //wait bit Idle is set + WAIT_BIT_SET(R_REG(STREAMER_PTME_CONFIG),STREAMER_PTME_CONFIG_READY); + + //enable new packet with 32bit mode + W_REG(STREAMER_PTME_CONFIG) = 0xB; //bit 3 Valid to 1 and Size to 32bit + + //write packet with 32bit access + for(i=0;i end of packet + + //printf("\n end TEST TM module \n\n"); + if (error == 0) + printf("Success!\n"); + else + printf("Failed!\n"); + + while(1); + return error; +} + diff --git a/target/sim/sim.mk b/target/sim/sim.mk index d3b612ae..95819d5c 100644 --- a/target/sim/sim.mk +++ b/target/sim/sim.mk @@ -7,7 +7,7 @@ ## @section Carfield platform simulation QUESTA ?= questa-2023.4 -TBENCH ?= tb_carfield_soc +TBENCH ?= tb_astral ## Get HyperRAM verification IP (VIP) for simulation $(CAR_TGT_DIR)/sim/src/hyp_vip: @@ -35,6 +35,9 @@ RUNTIME_DEFINES := +define+HYP_USER_PRELOAD="$(HYP_USER_PRELOAD)" RUNTIME_DEFINES += +define+HYP0_PRELOAD_MEM_FILE=\"$(HYP0_PRELOAD_MEM_FILE)\" RUNTIME_DEFINES += +define+HYP1_PRELOAD_MEM_FILE=\"$(HYP1_PRELOAD_MEM_FILE)\" +TASI_LIB += vlib $ROOT/working_dir/streamer/TASI_generic_Lib +TASI_LIB += vmap TASI_generic_Lib $ROOT/working_dir/streamer/TASI_generic_Lib + ############# # Questasim # ############# @@ -42,6 +45,10 @@ RUNTIME_DEFINES += +define+HYP1_PRELOAD_MEM_FILE=\"$(HYP1_PRELOAD_MEM_FILE)\" ## @section Questasim simulator target QUESTA_FLAGS := -permissive -suppress 3009 -suppress 8386 -error 7 +UVM_NO_RELNOTES + +## TODO: this is a workaround to enable simulations with Thales IP! Fix this! +QUESTA_FLAGS += -suppress 1565 + ifeq ($(TECH_SIM), 1) # Technological memory macros have the checks on hold/setup violations encapsulated # within a 'specify' Questa directive. For this reason, to run simulations of the @@ -52,6 +59,8 @@ ifeq ($(TECH_SIM), 1) QUESTA_FLAGS += +nospecify QUESTA_FLAGS += -sdfnoerror QUESTA_FLAGS += -suppress 13271 +## TODO: this is a workaround to suppress sdf error! Fix it! + QUESTA_FLAGS += -sdfnoerror endif ifdef DEBUG VOPT_FLAGS := $(QUESTA_FLAGS) +acc @@ -66,6 +75,12 @@ endif .PHONY: $(CAR_VSIM_DIR)/compile.carfield_soc.tcl $(CAR_VSIM_DIR)/compile.carfield_soc.tcl: $(BENDER) script vsim $(common_targs) $(sim_targs) $(sim_defs) $(common_defs) $(safed_defs) --vlog-arg="$(RUNTIME_DEFINES)" --compilation-mode separate > $@ + sed -i '2a\ + set VsimDir "$(CAR_VSIM_DIR)"\ + set TCTMPATH "$(STREAMER_ROOT)"\ + set SPWPATH "$(SPACEWIRE_ROOT)"\ + source $(STREAMER_ROOT)/astral.compile.tcl \ + source $(SPACEWIRE_ROOT)/astr_compile.tcl' $@ echo 'vlog "$(CHS_ROOT)/target/sim/src/elfloader.cpp" -ccflags "-std=c++11"' >> $@ echo 'vopt $(VOPT_FLAGS) $(TBENCH) -o $(TBENCH)_opt' >> $@ @@ -85,7 +100,7 @@ car-vsim-sim-build: $(CAR_VSIM_DIR)/compile.carfield_soc.tcl .PHONY: car-vsim-sim-clean ## Remove all Questasim simulation build artifacts car-vsim-sim-clean: - rm -rf $(CAR_VSIM_DIR)/uart $(CAR_VSIM_DIR)/FETCH* $(CAR_VSIM_DIR)/logs $(CAR_VSIM_DIR)/*.ini $(CAR_VSIM_DIR)/trace* $(CAR_VSIM_DIR)/*.wlf $(CAR_VSIM_DIR)/transcript $(CAR_VSIM_DIR)/work + rm -rf $(CAR_VSIM_DIR)/uart $(CAR_VSIM_DIR)/FETCH* $(CAR_VSIM_DIR)/logs $(CAR_VSIM_DIR)/*.ini $(CAR_VSIM_DIR)/trace* $(CAR_VSIM_DIR)/*.wlf $(CAR_VSIM_DIR)/transcript $(CAR_VSIM_DIR)/work $(CAR_VSIM_DIR)/*lib $(CAR_VSIM_DIR)/*Lib $(CAR_VSIM_DIR)/*.vstf $(CAR_VSIM_DIR)/*.log $(CAR_VSIM_DIR)/*.txt .PHONY: car-vsim-sim-run ## Run simulation of the carfield RTL. @@ -103,7 +118,7 @@ car-vsim-sim-clean: ## @param PULPD_BOOTMODE=0 The bootmode of safe domain <0 JTAG|1 Serial Link> ## @param SPATZD_BINARY== ELF to be executed on integer PMCA ## @param SPATZD_BOOTMODE=0 The bootmode of safe domain <0 JTAG|1 Serial Link> -## @param TESTBENCH=tb_carfield_soc_opt The optimised toplevel testbench to use. Defaults to 'tb_carfield_soc_opt'. +## @param TESTBENCH=tb_astral_opt The optimised toplevel testbench to use. Defaults to 'tb_astral_opt'. ## @param VSIM_FLAGS The flags for the vsim invocation car-vsim-sim-run: $(eval CHS_BINARY_ABS := $(realpath $(CHS_BINARY))) @@ -115,6 +130,7 @@ car-vsim-sim-run: $(eval SPATZD_BINARY_ABS := $(realpath $(SPATZD_BINARY))) cd $(CAR_VSIM_DIR); $(QUESTA) vsim $(VSIM_FLAGS) -do \ "set HYP_USER_PRELOAD $(HYP_USER_PRELOAD); \ + set BYPASS_PLL $(BYPASS_PLL); \ set SECURE_BOOT $(SECURE_BOOT); \ set CHS_BOOTMODE $(CHS_BOOTMODE); \ set CHS_PRELMODE $(CHS_PRELMODE); \ diff --git a/target/sim/src/astral_fix.sv b/target/sim/src/astral_fix.sv new file mode 100644 index 00000000..ad6d66d9 --- /dev/null +++ b/target/sim/src/astral_fix.sv @@ -0,0 +1,1015 @@ +// Copyright 2023 ETH Zurich and University of Bologna. +// Solderpad Hardware License, Version 0.51, see LICENSE for details. +// SPDX-License-Identifier: SHL-0.51 +// +// Alessandro Ottaviano +// Victor Isachi + +module astral_fixture; + + `include "cheshire/typedef.svh" + `include "register_interface/assign.svh" + `include "axi/assign.svh" + + import carfield_chip_pkg::*; + import cheshire_pkg::*; + import carfield_pkg::*; +`ifdef SAFED_ENABLE + import safety_island_pkg::*; +`endif + import astral_padframe_periph_config_reg_pkg::*; + import pkg_internal_astral_padframe_periph::*; + + /////////// + // DPI // + /////////// + + import "DPI-C" function byte read_elf(input string filename); + import "DPI-C" function byte get_entry(output longint entry); + import "DPI-C" function byte get_section(output longint address, output longint len); + import "DPI-C" context function byte read_section(input longint address, inout byte buffer[], input longint len); + + ///////// + // DUT // + ///////// + + localparam time ClkPeriodRef = 17.936ns; // 55.75MHz reference clock generated by the FLL + localparam time ClkPeriodExt = 1us; // 1MHz external clock + localparam time ClkPeriodJtag = 100ns; // 10MHz JTAG clock + localparam int unsigned RstCycles = 5; + localparam int unsigned RstCyclesVip = 5; + localparam real TAppl = 0.1; + localparam real TTest = 0.9; + + localparam int NumPhys = 1; + localparam int NumChips = 2; + + //////////////////////// + // IN/OUT declaration // + //////////////////////// + + logic ref_clk, ext_clk; + logic bypass_pll; + logic pwr_on_rst_n; + logic pwr_on_ext_rst_n; + logic secure_boot; + logic testmode_hostd; + logic [1:0] bootmode_hostd; + logic [1:0] bootmode_safed; + logic [1:0] bootmode_secd; + + logic jtag_hostd_tck; + logic jtag_hostd_trst_n; + logic jtag_hostd_tms; + logic jtag_hostd_tdi; + logic jtag_hostd_tdo; + + logic jtag_safed_tck; + logic jtag_safed_trst_n; + logic jtag_safed_tms; + logic jtag_safed_tdi; + logic jtag_safed_tdo; + + logic jtag_secd_tck; + logic jtag_secd_trst_n; + logic jtag_secd_tms; + logic jtag_secd_tdi; + logic jtag_secd_tdo; + + logic jtag_pll_tck; + logic jtag_pll_trst_n; + logic jtag_pll_tms; + logic jtag_pll_tdi; + logic jtag_pll_tdo; + + logic uart_hostd_tx; + logic uart_hostd_rx; + logic uart_secd_tx; + logic uart_secd_rx; + + // Serial Link signals + logic [SlinkNumChan-1:0] slink_hostd_rcv_clk_to_vip; + logic [SlinkNumChan-1:0] slink_hostd_rcv_clk_from_vip; + logic [SlinkNumChan-1:0][SlinkNumLanes-1:0] slink_hostd_to_vip; + logic [SlinkNumChan-1:0][SlinkNumLanes-1:0] slink_hostd_from_vip; + + /////////////////////// + // INOUT declaration // + /////////////////////// + + // Clock + wire w_ref_clk; + // Bypass PLL + wire w_bypass_pll; + // External clock + wire w_ext_clk; + // POR (power-on reset, active low) + wire w_pwr_on_rst_n; + // secure boot emulation + wire w_secure_boot; + // Bootmode (hostd) + wire [2:0] w_bootmode_hostd; + // Bootmode (safed) + wire [1:0] w_bootmode_safed; + // Bootmode (secd) + wire [1:0] w_bootmode_secd; + // JTAG (hostd) + wire w_jtag_hostd_tck; + wire w_jtag_hostd_tms; + wire w_jtag_hostd_tdi; + wire w_jtag_hostd_trstn; + wire w_jtag_hostd_tdo; + // JTAG (safed) + wire w_jtag_safed_tck; + wire w_jtag_safed_tms; + wire w_jtag_safed_tdi; + wire w_jtag_safed_trstn; + wire w_jtag_safed_tdo; + // JTAG (secd) + wire w_jtag_secd_tck; + wire w_jtag_secd_tms; + wire w_jtag_secd_tdi; + wire w_jtag_secd_trstn; + wire w_jtag_secd_tdo; + // GPIOs + wire [21:0] w_gpio; + // Serial Link + wire w_slink_hostd_rcv_clk_to_vip; + wire w_slink_hostd_rcv_clk_from_vip; + wire [SlinkNumLanes-1:0] w_slink_hostd_to_vip; + wire [SlinkNumLanes-1:0] w_slink_hostd_from_vip; + // hyperbus tristate signals + wire [NumPhys-1:0][NumChips-1:0] w_hyper_csn; + wire [NumPhys-1:0] w_hyper_ck; + wire [NumPhys-1:0] w_hyper_ckn; + wire [NumPhys-1:0] w_hyper_rwds; + wire [NumPhys-1:0][7:0] w_hyper_dq; + wire [NumPhys-1:0] w_hyper_resetn; + // SPI (hostd) + wire w_spi_hostd_sck; + wire [SpihNumCs-1:0] w_spi_hostd_csb; + wire [3:0] w_spi_hostd_sd; + // SPI (secd) + wire w_spi_secd_sck; + wire [SpihNumCs-1:0] w_spi_secd_csb; + wire [3:0] w_spi_secd_sd; + // UART (hostd) + wire w_uart_hostd_tx; + wire w_uart_hostd_rx; + // UART (secd) + wire w_uart_secd_tx; + wire w_uart_secd_rx; + // I2C (hostd) + wire w_i2c_hostd_sda; + wire w_i2c_hostd_scl; + // CAN + wire w_can_tx; + wire w_can_rx; + // Ethernet + wire w_eth_rst; + wire w_eth_txck; + wire w_eth_txctl; + wire w_eth_txd0; + wire w_eth_txd1; + wire w_eth_txd2; + wire w_eth_txd3; + wire w_eth_mdc; + wire w_eth_md; + wire w_eth_rxck; + wire w_eth_rxctl; + wire w_eth_rxd0; + wire w_eth_rxd1; + wire w_eth_rxd2; + wire w_eth_rxd3; + // SpaceWier + wire w_spw_data_in; + wire w_spw_data_out; + wire w_spw_strobe_in; + wire w_spw_strobe_out; + // Telecommand + wire w_tc_active; + wire w_tc_clock; + wire w_tc_data; + wire w_ptme_clk; + wire w_ptme_enc; + wire w_ptme_sync; + wire w_ptme_ext_clk; + wire [2:0] w_hpc_addr; + wire w_hpc_cmd_en; + wire w_hpc_smp; + wire [1:0] w_llc_line; + wire w_obt_ext_clk; + // Debug signals + wire [2:0] debug_signals; + + wire w_jtag_pll_tck; + wire w_jtag_pll_tms; + wire w_jtag_pll_tdi; + wire w_jtag_pll_trstn; + wire w_jtag_pll_tdo; + // Muxed pads + wire w_muxed_v_00; + wire w_muxed_v_01; + wire w_muxed_v_02; + wire w_muxed_v_03; + wire w_muxed_v_04; + wire w_muxed_v_05; + wire w_muxed_v_06; + wire w_muxed_v_07; + wire w_muxed_v_08; + wire w_muxed_v_09; + wire w_muxed_v_10; + wire w_muxed_v_11; + wire w_muxed_v_12; + wire w_muxed_v_13; + wire w_muxed_v_14; + wire w_muxed_v_15; + wire w_muxed_v_16; + wire w_muxed_v_17; + wire w_muxed_h_00; + wire w_muxed_h_01; + wire w_muxed_h_02; + wire w_muxed_h_03; + // Muxed alternate functions + logic mux_0_spih_sck; + logic mux_0_spih_csb_0; + logic mux_0_spih_csb_1; + logic mux_0_spih_sd_0; + logic mux_0_spih_sd_1; + logic mux_0_spih_sd_2; + logic mux_0_spih_sd_3; + logic mux_0_eth_rxck; + logic mux_0_eth_rxctl; + logic mux_0_eth_rxd_0; + logic mux_0_eth_rxd_1; + logic mux_0_eth_rxd_2; + logic mux_0_eth_rxd_3; + logic mux_0_eth_txck; + logic mux_0_eth_txctl; + logic mux_0_eth_txd_0; + logic mux_0_eth_txd_1; + logic mux_0_eth_txd_2; + logic mux_0_eth_txd_3; + logic mux_0_eth_md; + logic mux_0_eth_mdc; + logic mux_0_eth_rst_n; + logic mux_1_can_rx; + logic mux_1_can_tx; + logic mux_1_slink_rcv_clk_i; + logic mux_1_slink_0_i; + logic mux_1_slink_1_i; + logic mux_1_slink_2_i; + logic mux_1_slink_3_i; + logic mux_1_slink_4_i; + logic mux_1_slink_5_i; + logic mux_1_slink_6_i; + logic mux_1_slink_7_i; + logic mux_1_slink_rcv_clk_o; + logic mux_1_slink_0_o; + logic mux_1_slink_1_o; + logic mux_1_slink_2_o; + logic mux_1_slink_3_o; + logic mux_1_slink_4_o; + logic mux_1_slink_5_o; + logic mux_1_slink_6_o; + logic mux_1_slink_7_o; + logic mux_2_i2c_sda; + logic mux_2_i2c_scl; + logic mux_2_tc_active; + logic mux_2_tc_clk; + logic mux_2_tc_data; + logic mux_2_ptme_clk; + logic mux_2_ptme_enc; + logic mux_2_ptme_sync; + logic mux_2_ptme_ext_clk; + logic [2:0] mux_2_hpc_addr; + logic mux_2_hpc_cmd_en; + logic mux_2_hpc_smp; + logic [1:0] mux_2_llc_line; + logic mux_2_obt_ext_clk; + logic mux_3_spih_ot_sck; + logic mux_3_spih_ot_csb; + logic mux_3_spih_ot_sd_0; + logic mux_3_spih_ot_sd_1; + logic mux_3_spih_ot_sd_2; + logic mux_3_spih_ot_sd_3; + logic mux_4_gpio_0; + logic mux_4_gpio_1; + logic mux_4_gpio_2; + logic mux_4_gpio_3; + logic mux_4_gpio_4; + logic mux_4_gpio_5; + logic mux_4_gpio_6; + logic mux_4_gpio_7; + logic mux_4_gpio_8; + logic mux_4_gpio_9; + logic mux_4_gpio_10; + logic mux_4_gpio_11; + logic mux_4_gpio_12; + logic mux_4_gpio_13; + logic mux_4_gpio_14; + logic mux_4_gpio_15; + logic mux_4_gpio_16; + logic mux_4_gpio_17; + logic mux_4_gpio_18; + logic mux_4_gpio_19; + logic mux_4_gpio_20; + logic mux_4_gpio_21; + + ///////////////// + // Assignments // + ///////////////// + + // Clock + assign w_ref_clk = ref_clk; + // External clock + assign w_ext_clk = ext_clk; + // PLL/FLL bypass + assign w_bypass_pll = bypass_pll; + // POR +`ifndef BYPASS_PLL + assign w_pwr_on_rst_n = pwr_on_rst_n; +`else + assign w_pwr_on_rst_n = pwr_on_ext_rst_n; +`endif + // secure boot emulation + assign w_secure_boot = secure_boot; + // Bootmode (hostd) + // We only use 2 bits at the moment, the thirs is tied to 0 + assign w_bootmode_hostd = {1'b0, bootmode_hostd}; + // Bootmode (safed) + assign w_bootmode_safed = bootmode_safed; + // Bootmode (secd) + assign w_bootmode_secd = bootmode_secd; + // JTAG (hostd) + assign w_jtag_hostd_tck = jtag_hostd_tck; + assign w_jtag_hostd_tms = jtag_hostd_tms; + assign w_jtag_hostd_tdi = jtag_hostd_tdi; + assign w_jtag_hostd_trstn = jtag_hostd_trst_n; + // TODO the pad is inverted wrt output signal, FIXME! This is just a hack, + // some parameters in the padframe are off + assign jtag_hostd_tdo = w_jtag_hostd_tdo; + // JTAG (safed) + assign w_jtag_safed_tck = jtag_safed_tck; + assign w_jtag_safed_tms = jtag_safed_tms; + assign w_jtag_safed_tdi = jtag_safed_tdi; + assign w_jtag_safed_trstn = jtag_safed_trst_n; + assign jtag_safed_tdo = w_jtag_safed_tdo; + // JTAG (secd) + assign w_jtag_secd_tck = jtag_secd_tck; + assign w_jtag_secd_tms = jtag_secd_tms; + assign w_jtag_secd_tdi = jtag_secd_tdi; + assign w_jtag_secd_trstn = jtag_secd_trst_n; + assign jtag_secd_tdo = w_jtag_secd_tdo; + // GPIOs (hostd) + assign w_gpio = '0; + // Serial Link (hostd) + assign w_slink_hostd_rcv_clk_from_vip = slink_hostd_rcv_clk_from_vip; + assign w_slink_hostd_from_vip = slink_hostd_from_vip; + assign slink_hostd_rcv_clk_to_vip = w_slink_hostd_rcv_clk_to_vip; + assign slink_hostd_to_vip = w_slink_hostd_to_vip; + // UART (hostd) + assign uart_hostd_tx = w_uart_hostd_tx; + assign w_uart_hostd_rx = uart_hostd_rx; + // UART (secd) + assign uart_secd_tx = w_uart_secd_tx; + assign w_uart_secd_rx = uart_secd_rx; + // CAN + // TODO connect + assign w_can_rx = '0; + // Ethernet + // TODO connect + assign w_eth_rxck = '0; + assign w_eth_rxctl = '0; + assign w_eth_rxd0 = '0; + assign w_eth_rxd1 = '0; + assign w_eth_rxd2 = '0; + assign w_eth_rxd3 = '0; + // PLL JTAG + assign w_jtag_pll_tck = jtag_pll_tck; + assign w_jtag_pll_tms = jtag_pll_tms; + assign w_jtag_pll_tdi = jtag_pll_tdi; + assign w_jtag_pll_trstn = jtag_pll_trst_n; + assign jtag_pll_tdo = w_jtag_pll_tdo; + + /////////////////////////////// + // External Clock generation // + /////////////////////////////// + + clk_rst_gen #( + .ClkPeriod ( ClkPeriodExt ), + .RstClkCycles ( RstCycles ) + ) i_ext_clk ( + .clk_o ( ext_clk ), +`ifndef BYPASS_PLL + .rst_no ( ) +`else + .rst_no ( pwr_on_ext_rst_n ) +`endif + ); + + //////////////////////////// + // Carfield configuration // + //////////////////////////// + + localparam cheshire_cfg_t DutCfg = carfield_pkg::CarfieldCfgDefault; + `CHESHIRE_TYPEDEF_ALL(, DutCfg) + + +`ifndef CARFIELD_CHIP_NETLIST + astral_wrap #( + .HypNumPhys ( NumPhys ), + .HypNumChips ( NumChips ) + ) i_dut ( +`else + astral_wrap i_dut ( +`endif + // Reference clock + .pad_periph_ref_clk_pad ( w_ext_clk ), + .pad_periph_fll_bypass_pad ( w_bypass_pll ), + // POR + .pad_periph_pwr_on_rst_n_pad ( w_pwr_on_rst_n ), + // Bootmode + .pad_periph_test_mode_pad ( pd_testmode_net ), + .pad_periph_boot_mode_0_pad ( w_bootmode_hostd[0] ), + .pad_periph_boot_mode_1_pad ( w_bootmode_hostd[1] ), + .pad_periph_ot_boot_mode_pad ( bootmode_secd[0] ), + .pad_periph_secure_boot_pad ( w_secure_boot ), + // JTAG + .pad_periph_jtag_tclk_pad ( w_jtag_hostd_tck ), + .pad_periph_jtag_trst_n_pad ( w_jtag_hostd_trstn ), + .pad_periph_jtag_tms_pad ( w_jtag_hostd_tms ), + .pad_periph_jtag_tdi_pad ( w_jtag_hostd_tdi ), + .pad_periph_jtag_tdo_pad ( w_jtag_hostd_tdo ), + // JTAG OT + .pad_periph_jtag_ot_tclk_pad ( w_jtag_secd_tck ), + .pad_periph_jtag_ot_trst_ni_pad ( w_jtag_secd_trstn ), + .pad_periph_jtag_ot_tms_pad ( w_jtag_secd_tms ), + .pad_periph_jtag_ot_tdi_pad ( w_jtag_secd_tdi ), + .pad_periph_jtag_ot_tdo_pad ( w_jtag_secd_tdo ), + // Hyper + .pad_periph_hyper_cs_0_n_pad ( w_hyper_csn[0][0] ), + .pad_periph_hyper_cs_1_n_pad ( w_hyper_csn[0][1] ), + .pad_periph_hyper_ck_pad ( w_hyper_ck[0] ), + .pad_periph_hyper_ck_n_pad ( w_hyper_ckn[0] ), + .pad_periph_hyper_rwds_pad ( w_hyper_rwds[0] ), + .pad_periph_hyper_dq_0_pad ( w_hyper_dq[0][0] ), + .pad_periph_hyper_dq_1_pad ( w_hyper_dq[0][1] ), + .pad_periph_hyper_dq_2_pad ( w_hyper_dq[0][2] ), + .pad_periph_hyper_dq_3_pad ( w_hyper_dq[0][3] ), + .pad_periph_hyper_dq_4_pad ( w_hyper_dq[0][4] ), + .pad_periph_hyper_dq_5_pad ( w_hyper_dq[0][5] ), + .pad_periph_hyper_dq_6_pad ( w_hyper_dq[0][6] ), + .pad_periph_hyper_dq_7_pad ( w_hyper_dq[0][7] ), + .pad_periph_hyper_reset_n_pad ( w_hyper_resetn[0] ), + // SPW + .pad_periph_spw_data_in_pad ( w_spw_data_in ), + .pad_periph_spw_strb_in_pad ( w_spw_strobe_in ), + .pad_periph_spw_data_out_pad ( w_spw_data_out ), + .pad_periph_spw_strb_out_pad ( w_spw_strobe_out ), + // UART + .pad_periph_uart_tx_out_pad ( w_uart_hostd_tx ), + .pad_periph_uart_rx_in_pad ( w_uart_hostd_rx ), + // Muxed pads + .pad_periph_muxed_v_00_pad ( w_muxed_v_00 ), + .pad_periph_muxed_v_01_pad ( w_muxed_v_01 ), + .pad_periph_muxed_v_02_pad ( w_muxed_v_02 ), + .pad_periph_muxed_v_03_pad ( w_muxed_v_03 ), + .pad_periph_muxed_v_04_pad ( w_muxed_v_04 ), + .pad_periph_muxed_v_05_pad ( w_muxed_v_05 ), + .pad_periph_muxed_v_06_pad ( w_muxed_v_06 ), + .pad_periph_muxed_v_07_pad ( w_muxed_v_07 ), + .pad_periph_muxed_v_08_pad ( w_muxed_v_08 ), + .pad_periph_muxed_v_09_pad ( w_muxed_v_09 ), + .pad_periph_muxed_v_10_pad ( w_muxed_v_10 ), + .pad_periph_muxed_v_11_pad ( w_muxed_v_11 ), + .pad_periph_muxed_v_12_pad ( w_muxed_v_12 ), + .pad_periph_muxed_v_13_pad ( w_muxed_v_13 ), + .pad_periph_muxed_v_14_pad ( w_muxed_v_14 ), + .pad_periph_muxed_v_15_pad ( w_muxed_v_15 ), + .pad_periph_muxed_v_16_pad ( w_muxed_v_16 ), + .pad_periph_muxed_v_17_pad ( w_muxed_v_17 ), + .pad_periph_muxed_h_00_pad ( w_muxed_h_00 ), + .pad_periph_muxed_h_01_pad ( w_muxed_h_01 ), + .pad_periph_muxed_h_02_pad ( w_muxed_h_02 ), + .pad_periph_muxed_h_03_pad ( w_muxed_h_03 ) + ); + + pulldown (pd_testmode_net); + + //////////////////////////// + // Muxed Pads Connections // + //////////////////////////// + + `define PAD_MUX_REG_PATH i_dut.i_astral_padframe.i_periph.i_periph_muxer.s_reg2hw + + // SPI + assign mux_0_spih_sck = (`PAD_MUX_REG_PATH.muxed_v_00_mux_sel.q == PAD_MUX_GROUP_MUXED_V_00_SEL_SPI_SCK); + assign mux_0_spih_csb_0 = (`PAD_MUX_REG_PATH.muxed_v_01_mux_sel.q == PAD_MUX_GROUP_MUXED_V_01_SEL_SPI_CSB_0); + assign mux_0_spih_csb_1 = (`PAD_MUX_REG_PATH.muxed_v_02_mux_sel.q == PAD_MUX_GROUP_MUXED_V_02_SEL_SPI_CSB_1); + assign mux_0_spih_sd_0 = (`PAD_MUX_REG_PATH.muxed_v_03_mux_sel.q == PAD_MUX_GROUP_MUXED_V_03_SEL_SPI_SD_0); + assign mux_0_spih_sd_1 = (`PAD_MUX_REG_PATH.muxed_v_04_mux_sel.q == PAD_MUX_GROUP_MUXED_V_04_SEL_SPI_SD_1); + assign mux_0_spih_sd_2 = (`PAD_MUX_REG_PATH.muxed_v_05_mux_sel.q == PAD_MUX_GROUP_MUXED_V_05_SEL_SPI_SD_2); + assign mux_0_spih_sd_3 = (`PAD_MUX_REG_PATH.muxed_v_06_mux_sel.q == PAD_MUX_GROUP_MUXED_V_06_SEL_SPI_SD_3); + tranif1 tran_spih_sck (w_muxed_v_00, w_spi_hostd_sck, mux_0_spih_sck); + tranif1 tran_spih_csb_0 (w_muxed_v_01, w_spi_hostd_csb[0], mux_0_spih_csb_0); + tranif1 tran_spih_csb_1 (w_muxed_v_02, w_spi_hostd_csb[1], mux_0_spih_csb_1); + tranif1 tran_spih_sd_0 (w_muxed_v_03, w_spi_hostd_sd[0], mux_0_spih_sd_0); + tranif1 tran_spih_sd_1 (w_muxed_v_04, w_spi_hostd_sd[1], mux_0_spih_sd_1); + tranif1 tran_spih_sd_2 (w_muxed_v_05, w_spi_hostd_sd[2], mux_0_spih_sd_2); + tranif1 tran_spih_sd_3 (w_muxed_v_06, w_spi_hostd_sd[3], mux_0_spih_sd_3); + pullup (w_spi_hostd_sck); + pullup (w_spi_hostd_sd[0]); + pullup (w_spi_hostd_sd[1]); + pullup (w_spi_hostd_sd[2]); + pullup (w_spi_hostd_sd[3]); + // Ethernet + assign mux_0_eth_rxck = (`PAD_MUX_REG_PATH.muxed_v_07_mux_sel.q == PAD_MUX_GROUP_MUXED_V_07_SEL_ETHERNET_RXCK); + assign mux_0_eth_rxctl = (`PAD_MUX_REG_PATH.muxed_v_08_mux_sel.q == PAD_MUX_GROUP_MUXED_V_08_SEL_ETHERNET_RXCTL); + assign mux_0_eth_rxd_0 = (`PAD_MUX_REG_PATH.muxed_v_09_mux_sel.q == PAD_MUX_GROUP_MUXED_V_09_SEL_ETHERNET_RXD_0); + assign mux_0_eth_rxd_1 = (`PAD_MUX_REG_PATH.muxed_v_10_mux_sel.q == PAD_MUX_GROUP_MUXED_V_10_SEL_ETHERNET_RXD_1); + assign mux_0_eth_rxd_2 = (`PAD_MUX_REG_PATH.muxed_v_11_mux_sel.q == PAD_MUX_GROUP_MUXED_V_11_SEL_ETHERNET_RXD_2); + assign mux_0_eth_rxd_3 = (`PAD_MUX_REG_PATH.muxed_v_12_mux_sel.q == PAD_MUX_GROUP_MUXED_V_12_SEL_ETHERNET_RXD_3); + assign mux_0_eth_txck = (`PAD_MUX_REG_PATH.muxed_v_13_mux_sel.q == PAD_MUX_GROUP_MUXED_V_13_SEL_ETHERNET_TXCK); + assign mux_0_eth_txctl = (`PAD_MUX_REG_PATH.muxed_v_14_mux_sel.q == PAD_MUX_GROUP_MUXED_V_14_SEL_ETHERNET_TXCTL); + assign mux_0_eth_txd_0 = (`PAD_MUX_REG_PATH.muxed_v_15_mux_sel.q == PAD_MUX_GROUP_MUXED_V_15_SEL_ETHERNET_TXD_0); + assign mux_0_eth_txd_1 = (`PAD_MUX_REG_PATH.muxed_v_16_mux_sel.q == PAD_MUX_GROUP_MUXED_V_16_SEL_ETHERNET_TXD_1); + assign mux_0_eth_txd_2 = (`PAD_MUX_REG_PATH.muxed_v_17_mux_sel.q == PAD_MUX_GROUP_MUXED_V_17_SEL_ETHERNET_TXD_2); + assign mux_0_eth_txd_3 = (`PAD_MUX_REG_PATH.muxed_h_00_mux_sel.q == PAD_MUX_GROUP_MUXED_H_00_SEL_ETHERNET_TXD_3); + assign mux_0_eth_md = (`PAD_MUX_REG_PATH.muxed_h_01_mux_sel.q == PAD_MUX_GROUP_MUXED_H_01_SEL_ETHERNET_MD); + assign mux_0_eth_mdc = (`PAD_MUX_REG_PATH.muxed_h_02_mux_sel.q == PAD_MUX_GROUP_MUXED_H_02_SEL_ETHERNET_MDC); + assign mux_0_eth_rst_n = (`PAD_MUX_REG_PATH.muxed_h_03_mux_sel.q == PAD_MUX_GROUP_MUXED_H_03_SEL_ETHERNET_RST_N); + tranif1 tran_eth_rxck (w_muxed_v_07, w_eth_rxck, mux_0_eth_rxck); + tranif1 tran_eth_rxctl (w_muxed_v_08, w_eth_rxctl, mux_0_eth_rxctl); + tranif1 tran_eth_rxd_0 (w_muxed_v_09, w_eth_rxd0, mux_0_eth_rxd_0); + tranif1 tran_eth_rxd_1 (w_muxed_v_10, w_eth_rxd1, mux_0_eth_rxd_1); + tranif1 tran_eth_rxd_2 (w_muxed_v_11, w_eth_rxd2, mux_0_eth_rxd_2); + tranif1 tran_eth_rxd_3 (w_muxed_v_12, w_eth_rxd3, mux_0_eth_rxd_3); + tranif1 tran_eth_txck (w_muxed_v_13, w_eth_txck, mux_0_eth_txck); + tranif1 tran_eth_txctl (w_muxed_v_14, w_eth_txctl, mux_0_eth_txctl); + tranif1 tran_eth_txd_0 (w_muxed_v_15, w_eth_txd0, mux_0_eth_txd_0); + tranif1 tran_eth_txd_1 (w_muxed_v_16, w_eth_txd1, mux_0_eth_txd_1); + tranif1 tran_eth_txd_2 (w_muxed_v_17, w_eth_txd2, mux_0_eth_txd_2); + tranif1 tran_eth_txd_3 (w_muxed_h_00, w_eth_txd3, mux_0_eth_txd_3); + tranif1 tran_eth_md (w_muxed_h_01, w_eth_md, mux_0_eth_md); + tranif1 tran_eth_mdc (w_muxed_h_02, w_eth_mdc, mux_0_eth_mdc); + tranif1 tran_eth_rst_n (w_muxed_h_03, w_eth_rst, mux_0_eth_rst_n); + // CAN + assign mux_1_can_rx = (`PAD_MUX_REG_PATH.muxed_v_00_mux_sel.q == PAD_MUX_GROUP_MUXED_V_00_SEL_CAN_RX); + assign mux_1_can_tx = (`PAD_MUX_REG_PATH.muxed_v_01_mux_sel.q == PAD_MUX_GROUP_MUXED_V_01_SEL_CAN_TX); + tranif1 tran_can_rx (w_muxed_v_00, w_can_rx, mux_1_can_rx); + tranif1 tran_can_tx (w_muxed_v_01, w_can_tx, mux_1_can_tx); + // Serial Link + assign mux_1_slink_rcv_clk_i = (`PAD_MUX_REG_PATH.muxed_v_04_mux_sel.q == PAD_MUX_GROUP_MUXED_V_04_SEL_SERIAL_LINK_RCV_CLK_I); + assign mux_1_slink_0_i = (`PAD_MUX_REG_PATH.muxed_v_05_mux_sel.q == PAD_MUX_GROUP_MUXED_V_05_SEL_SERIAL_LINK_I_0); + assign mux_1_slink_1_i = (`PAD_MUX_REG_PATH.muxed_v_06_mux_sel.q == PAD_MUX_GROUP_MUXED_V_06_SEL_SERIAL_LINK_I_1); + assign mux_1_slink_2_i = (`PAD_MUX_REG_PATH.muxed_v_07_mux_sel.q == PAD_MUX_GROUP_MUXED_V_07_SEL_SERIAL_LINK_I_2); + assign mux_1_slink_3_i = (`PAD_MUX_REG_PATH.muxed_v_08_mux_sel.q == PAD_MUX_GROUP_MUXED_V_08_SEL_SERIAL_LINK_I_3); + assign mux_1_slink_4_i = (`PAD_MUX_REG_PATH.muxed_v_09_mux_sel.q == PAD_MUX_GROUP_MUXED_V_09_SEL_SERIAL_LINK_I_4); + assign mux_1_slink_5_i = (`PAD_MUX_REG_PATH.muxed_v_10_mux_sel.q == PAD_MUX_GROUP_MUXED_V_10_SEL_SERIAL_LINK_I_5); + assign mux_1_slink_6_i = (`PAD_MUX_REG_PATH.muxed_v_11_mux_sel.q == PAD_MUX_GROUP_MUXED_V_11_SEL_SERIAL_LINK_I_6); + assign mux_1_slink_7_i = (`PAD_MUX_REG_PATH.muxed_v_12_mux_sel.q == PAD_MUX_GROUP_MUXED_V_12_SEL_SERIAL_LINK_I_7); + assign mux_1_slink_rcv_clk_o = (`PAD_MUX_REG_PATH.muxed_v_13_mux_sel.q == PAD_MUX_GROUP_MUXED_V_13_SEL_SERIAL_LINK_RCV_CLK_O); + assign mux_1_slink_0_o = (`PAD_MUX_REG_PATH.muxed_v_14_mux_sel.q == PAD_MUX_GROUP_MUXED_V_14_SEL_SERIAL_LINK_O_V_0); + assign mux_1_slink_1_o = (`PAD_MUX_REG_PATH.muxed_v_15_mux_sel.q == PAD_MUX_GROUP_MUXED_V_15_SEL_SERIAL_LINK_O_V_1); + assign mux_1_slink_2_o = (`PAD_MUX_REG_PATH.muxed_v_16_mux_sel.q == PAD_MUX_GROUP_MUXED_V_16_SEL_SERIAL_LINK_O_V_2); + assign mux_1_slink_3_o = (`PAD_MUX_REG_PATH.muxed_v_17_mux_sel.q == PAD_MUX_GROUP_MUXED_V_17_SEL_SERIAL_LINK_O_V_3); + assign mux_1_slink_4_o = (`PAD_MUX_REG_PATH.muxed_h_00_mux_sel.q == PAD_MUX_GROUP_MUXED_H_00_SEL_SERIAL_LINK_O_H_0); + assign mux_1_slink_5_o = (`PAD_MUX_REG_PATH.muxed_h_01_mux_sel.q == PAD_MUX_GROUP_MUXED_H_01_SEL_SERIAL_LINK_O_H_1); + assign mux_1_slink_6_o = (`PAD_MUX_REG_PATH.muxed_h_02_mux_sel.q == PAD_MUX_GROUP_MUXED_H_02_SEL_SERIAL_LINK_O_H_2); + assign mux_1_slink_7_o = (`PAD_MUX_REG_PATH.muxed_h_03_mux_sel.q == PAD_MUX_GROUP_MUXED_H_03_SEL_SERIAL_LINK_O_H_3); + tranif1 tran_slink_rcv_clk_i (w_muxed_v_04, w_slink_hostd_rcv_clk_from_vip, mux_1_slink_rcv_clk_i); + tranif1 tran_slink_0_i (w_muxed_v_05, w_slink_hostd_from_vip[0], mux_1_slink_0_i); + tranif1 tran_slink_1_i (w_muxed_v_06, w_slink_hostd_from_vip[1], mux_1_slink_1_i); + tranif1 tran_slink_2_i (w_muxed_v_07, w_slink_hostd_from_vip[2], mux_1_slink_2_i); + tranif1 tran_slink_3_i (w_muxed_v_08, w_slink_hostd_from_vip[3], mux_1_slink_3_i); + tranif1 tran_slink_4_i (w_muxed_v_09, w_slink_hostd_from_vip[4], mux_1_slink_4_i); + tranif1 tran_slink_5_i (w_muxed_v_10, w_slink_hostd_from_vip[5], mux_1_slink_5_i); + tranif1 tran_slink_6_i (w_muxed_v_11, w_slink_hostd_from_vip[6], mux_1_slink_6_i); + tranif1 tran_slink_7_i (w_muxed_v_12, w_slink_hostd_from_vip[7], mux_1_slink_7_i); + tranif1 tran_slink_rcv_clk_o (w_muxed_v_13, w_slink_hostd_rcv_clk_to_vip, mux_1_slink_rcv_clk_o); + tranif1 tran_slink_0_o (w_muxed_v_14, w_slink_hostd_to_vip[0], mux_1_slink_0_o); + tranif1 tran_slink_1_o (w_muxed_v_15, w_slink_hostd_to_vip[1], mux_1_slink_1_o); + tranif1 tran_slink_2_o (w_muxed_v_16, w_slink_hostd_to_vip[2], mux_1_slink_2_o); + tranif1 tran_slink_3_o (w_muxed_v_17, w_slink_hostd_to_vip[3], mux_1_slink_3_o); + tranif1 tran_slink_4_o (w_muxed_h_00, w_slink_hostd_to_vip[4], mux_1_slink_4_o); + tranif1 tran_slink_5_o (w_muxed_h_01, w_slink_hostd_to_vip[5], mux_1_slink_5_o); + tranif1 tran_slink_6_o (w_muxed_h_02, w_slink_hostd_to_vip[6], mux_1_slink_6_o); + tranif1 tran_slink_7_o (w_muxed_h_03, w_slink_hostd_to_vip[7], mux_1_slink_7_o); + // I2C + assign mux_2_i2c_sda = (`PAD_MUX_REG_PATH.muxed_v_00_mux_sel.q == PAD_MUX_GROUP_MUXED_V_00_SEL_I2C_SDA); + assign mux_2_i2c_scl = (`PAD_MUX_REG_PATH.muxed_v_01_mux_sel.q == PAD_MUX_GROUP_MUXED_V_01_SEL_I2C_SCL); + tranif1 tran_i2c_sda (w_muxed_v_00, w_i2c_hostd_sda, mux_2_i2c_sda); + tranif1 tran_i2c_scl (w_muxed_v_01, w_i2c_hostd_scl, mux_2_i2c_scl); + pullup (w_i2c_hostd_sda); + pullup (w_i2c_hostd_scl); + // Telecommand + assign mux_2_tc_active = (`PAD_MUX_REG_PATH.muxed_v_07_mux_sel.q == PAD_MUX_GROUP_MUXED_V_07_SEL_TC_ACTIVE); + assign mux_2_tc_clk = (`PAD_MUX_REG_PATH.muxed_v_08_mux_sel.q == PAD_MUX_GROUP_MUXED_V_08_SEL_TC_CLK); + assign mux_2_tc_data = (`PAD_MUX_REG_PATH.muxed_v_09_mux_sel.q == PAD_MUX_GROUP_MUXED_V_09_SEL_TC_DATA); + tranif1 tran_tc_active (w_muxed_v_07, w_tc_active, mux_2_tc_active); + tranif1 tran_tc_clk (w_muxed_v_08, w_tc_clock, mux_2_tc_clk); + tranif1 tran_tc_data (w_muxed_v_09, w_tc_data, mux_2_tc_data); + // PTME + assign mux_2_ptme_clk = (`PAD_MUX_REG_PATH.muxed_v_10_mux_sel.q == PAD_MUX_GROUP_MUXED_V_10_SEL_PTME_CLK); + assign mux_2_ptme_enc = (`PAD_MUX_REG_PATH.muxed_v_11_mux_sel.q == PAD_MUX_GROUP_MUXED_V_11_SEL_PTME_ENC); + assign mux_2_ptme_sync = (`PAD_MUX_REG_PATH.muxed_v_12_mux_sel.q == PAD_MUX_GROUP_MUXED_V_12_SEL_PTME_SYNC); + assign mux_2_ptme_ext_clk = (`PAD_MUX_REG_PATH.muxed_v_13_mux_sel.q == PAD_MUX_GROUP_MUXED_V_13_SEL_PTME_EXT_CLK); + tranif1 tran_ptme_active (w_muxed_v_10, w_ptme_clk, mux_2_ptme_clk); + tranif1 tran_ptme_clk (w_muxed_v_11, w_ptme_enc, mux_2_ptme_enc); + tranif1 tran_ptme_data (w_muxed_v_12, w_ptme_sync, mux_2_ptme_sync); + tranif1 tran_ptme_ext_clk (w_muxed_v_13, w_ptme_ext_clk, mux_2_ptme_ext_clk); + // HPC + assign mux_2_hpc_addr[0] = (`PAD_MUX_REG_PATH.muxed_v_14_mux_sel.q == PAD_MUX_GROUP_MUXED_V_14_SEL_HPC_ADDR_0); + assign mux_2_hpc_addr[1] = (`PAD_MUX_REG_PATH.muxed_v_15_mux_sel.q == PAD_MUX_GROUP_MUXED_V_15_SEL_HPC_ADDR_1); + assign mux_2_hpc_addr[2] = (`PAD_MUX_REG_PATH.muxed_v_16_mux_sel.q == PAD_MUX_GROUP_MUXED_V_16_SEL_HPC_ADDR_2); + assign mux_2_hpc_cmd_en = (`PAD_MUX_REG_PATH.muxed_v_17_mux_sel.q == PAD_MUX_GROUP_MUXED_V_17_SEL_HPC_CMD_EN); + assign mux_2_hpc_smp = (`PAD_MUX_REG_PATH.muxed_h_00_mux_sel.q == PAD_MUX_GROUP_MUXED_H_00_SEL_HPC_SAMPLE); + tranif1 tran_hpc_addr_0 (w_muxed_v_14, w_hpc_addr[0], mux_2_hpc_addr[0]); + tranif1 tran_hpc_addr_1 (w_muxed_v_15, w_hpc_addr[1], mux_2_hpc_addr[1]); + tranif1 tran_hpc_addr_2 (w_muxed_v_16, w_hpc_addr[2], mux_2_hpc_addr[2]); + tranif1 tran_hpc_cmd_en (w_muxed_v_17, w_hpc_cmd_en, mux_2_hpc_cmd_en); + tranif1 tran_hpc_smp (w_muxed_h_00, w_hpc_smp, mux_2_hpc_smp); + // LLC LINE + assign mux_2_llc_line[0] = (`PAD_MUX_REG_PATH.muxed_h_01_mux_sel.q == PAD_MUX_GROUP_MUXED_H_01_SEL_LLC_LINE_0); + assign mux_2_llc_line[1] = (`PAD_MUX_REG_PATH.muxed_h_02_mux_sel.q == PAD_MUX_GROUP_MUXED_H_02_SEL_LLC_LINE_1); + tranif1 tran_llc_line_0 (w_muxed_h_01, w_llc_line[0], mux_2_llc_line[0]); + tranif1 tran_llc_line_1 (w_muxed_h_02, w_llc_line[1], mux_2_llc_line[1]); + // OBT + assign mux_2_obt_ext_clk = (`PAD_MUX_REG_PATH.muxed_h_03_mux_sel.q == PAD_MUX_GROUP_MUXED_H_03_SEL_OBT_EXT_CLK); + tranif1 tran_obt_ext_cl (w_muxed_h_03, w_obt_ext_clk, mux_2_obt_ext_clk); + // SPI OT + assign mux_3_spih_ot_sck = (`PAD_MUX_REG_PATH.muxed_v_00_mux_sel.q == PAD_MUX_GROUP_MUXED_V_00_SEL_SPI_OT_SCK); + assign mux_3_spih_ot_csb = (`PAD_MUX_REG_PATH.muxed_v_01_mux_sel.q == PAD_MUX_GROUP_MUXED_V_01_SEL_SPI_OT_CSB); + assign mux_3_spih_ot_sd_0 = (`PAD_MUX_REG_PATH.muxed_v_02_mux_sel.q == PAD_MUX_GROUP_MUXED_V_02_SEL_SPI_OT_SD_0); + assign mux_3_spih_ot_sd_1 = (`PAD_MUX_REG_PATH.muxed_v_03_mux_sel.q == PAD_MUX_GROUP_MUXED_V_03_SEL_SPI_OT_SD_1); + assign mux_3_spih_ot_sd_2 = (`PAD_MUX_REG_PATH.muxed_v_04_mux_sel.q == PAD_MUX_GROUP_MUXED_V_04_SEL_SPI_OT_SD_2); + assign mux_3_spih_ot_sd_3 = (`PAD_MUX_REG_PATH.muxed_v_05_mux_sel.q == PAD_MUX_GROUP_MUXED_V_05_SEL_SPI_OT_SD_3); + tranif1 tran_spih_ot_sck (w_muxed_v_00, w_spi_secd_sck, mux_3_spih_ot_sck); + tranif1 tran_spih_ot_csb (w_muxed_v_01, w_spi_secd_csb[0], mux_3_spih_ot_csb); + tranif1 tran_spih_ot_sd_0 (w_muxed_v_02, w_spi_secd_sd[0], mux_3_spih_ot_sd_0); + tranif1 tran_spih_ot_sd_1 (w_muxed_v_03, w_spi_secd_sd[1], mux_3_spih_ot_sd_1); + tranif1 tran_spih_ot_sd_2 (w_muxed_v_04, w_spi_secd_sd[2], mux_3_spih_ot_sd_2); + tranif1 tran_spih_ot_sd_3 (w_muxed_v_05, w_spi_secd_sd[3], mux_3_spih_ot_sd_3); + // GPIO + assign mux_4_gpio_0 = (`PAD_MUX_REG_PATH.muxed_v_00_mux_sel.q == PAD_MUX_GROUP_MUXED_V_00_SEL_GPIO_IO_V_0); + assign mux_4_gpio_1 = (`PAD_MUX_REG_PATH.muxed_v_01_mux_sel.q == PAD_MUX_GROUP_MUXED_V_01_SEL_GPIO_IO_V_1); + assign mux_4_gpio_2 = (`PAD_MUX_REG_PATH.muxed_v_02_mux_sel.q == PAD_MUX_GROUP_MUXED_V_02_SEL_GPIO_IO_V_2); + assign mux_4_gpio_3 = (`PAD_MUX_REG_PATH.muxed_v_03_mux_sel.q == PAD_MUX_GROUP_MUXED_V_03_SEL_GPIO_IO_V_3); + assign mux_4_gpio_4 = (`PAD_MUX_REG_PATH.muxed_v_04_mux_sel.q == PAD_MUX_GROUP_MUXED_V_04_SEL_GPIO_IO_V_4); + assign mux_4_gpio_5 = (`PAD_MUX_REG_PATH.muxed_v_05_mux_sel.q == PAD_MUX_GROUP_MUXED_V_05_SEL_GPIO_IO_V_5); + assign mux_4_gpio_6 = (`PAD_MUX_REG_PATH.muxed_v_06_mux_sel.q == PAD_MUX_GROUP_MUXED_V_06_SEL_GPIO_IO_V_6); + assign mux_4_gpio_7 = (`PAD_MUX_REG_PATH.muxed_v_07_mux_sel.q == PAD_MUX_GROUP_MUXED_V_07_SEL_GPIO_IO_V_7); + assign mux_4_gpio_8 = (`PAD_MUX_REG_PATH.muxed_v_08_mux_sel.q == PAD_MUX_GROUP_MUXED_V_08_SEL_GPIO_IO_V_8); + assign mux_4_gpio_9 = (`PAD_MUX_REG_PATH.muxed_v_09_mux_sel.q == PAD_MUX_GROUP_MUXED_V_09_SEL_GPIO_IO_V_9); + assign mux_4_gpio_10 = (`PAD_MUX_REG_PATH.muxed_v_10_mux_sel.q == PAD_MUX_GROUP_MUXED_V_10_SEL_GPIO_IO_V_10); + assign mux_4_gpio_11 = (`PAD_MUX_REG_PATH.muxed_v_11_mux_sel.q == PAD_MUX_GROUP_MUXED_V_11_SEL_GPIO_IO_V_11); + assign mux_4_gpio_12 = (`PAD_MUX_REG_PATH.muxed_v_12_mux_sel.q == PAD_MUX_GROUP_MUXED_V_12_SEL_GPIO_IO_V_12); + assign mux_4_gpio_13 = (`PAD_MUX_REG_PATH.muxed_v_13_mux_sel.q == PAD_MUX_GROUP_MUXED_V_13_SEL_GPIO_IO_V_13); + assign mux_4_gpio_14 = (`PAD_MUX_REG_PATH.muxed_v_14_mux_sel.q == PAD_MUX_GROUP_MUXED_V_14_SEL_GPIO_IO_V_14); + assign mux_4_gpio_15 = (`PAD_MUX_REG_PATH.muxed_v_15_mux_sel.q == PAD_MUX_GROUP_MUXED_V_15_SEL_GPIO_IO_V_15); + assign mux_4_gpio_16 = (`PAD_MUX_REG_PATH.muxed_v_16_mux_sel.q == PAD_MUX_GROUP_MUXED_V_16_SEL_GPIO_IO_V_16); + assign mux_4_gpio_17 = (`PAD_MUX_REG_PATH.muxed_v_17_mux_sel.q == PAD_MUX_GROUP_MUXED_V_17_SEL_GPIO_IO_V_17); + assign mux_4_gpio_18 = (`PAD_MUX_REG_PATH.muxed_h_00_mux_sel.q == PAD_MUX_GROUP_MUXED_H_00_SEL_GPIO_IO_H_0); + assign mux_4_gpio_19 = (`PAD_MUX_REG_PATH.muxed_h_01_mux_sel.q == PAD_MUX_GROUP_MUXED_H_01_SEL_GPIO_IO_H_1); + assign mux_4_gpio_20 = (`PAD_MUX_REG_PATH.muxed_h_02_mux_sel.q == PAD_MUX_GROUP_MUXED_H_02_SEL_GPIO_IO_H_2); + assign mux_4_gpio_21 = (`PAD_MUX_REG_PATH.muxed_h_03_mux_sel.q == PAD_MUX_GROUP_MUXED_H_03_SEL_GPIO_IO_H_3); + tranif1 tran_gpio_0 (w_muxed_v_00, w_gpio[0], mux_4_gpio_0); + tranif1 tran_gpio_1 (w_muxed_v_01, w_gpio[1], mux_4_gpio_1); + tranif1 tran_gpio_2 (w_muxed_v_02, w_gpio[2], mux_4_gpio_2); + tranif1 tran_gpio_3 (w_muxed_v_03, w_gpio[3], mux_4_gpio_3); + tranif1 tran_gpio_4 (w_muxed_v_04, w_gpio[4], mux_4_gpio_4); + tranif1 tran_gpio_5 (w_muxed_v_05, w_gpio[5], mux_4_gpio_5); + tranif1 tran_gpio_6 (w_muxed_v_06, w_gpio[6], mux_4_gpio_6); + tranif1 tran_gpio_7 (w_muxed_v_07, w_gpio[7], mux_4_gpio_7); + tranif1 tran_gpio_8 (w_muxed_v_08, w_gpio[8], mux_4_gpio_8); + tranif1 tran_gpio_9 (w_muxed_v_09, w_gpio[9], mux_4_gpio_9); + tranif1 tran_gpio_10 (w_muxed_v_10, w_gpio[10], mux_4_gpio_10); + tranif1 tran_gpio_11 (w_muxed_v_11, w_gpio[11], mux_4_gpio_11); + tranif1 tran_gpio_12 (w_muxed_v_12, w_gpio[12], mux_4_gpio_12); + tranif1 tran_gpio_13 (w_muxed_v_13, w_gpio[13], mux_4_gpio_13); + tranif1 tran_gpio_14 (w_muxed_v_14, w_gpio[14], mux_4_gpio_14); + tranif1 tran_gpio_15 (w_muxed_v_15, w_gpio[15], mux_4_gpio_15); + tranif1 tran_gpio_16 (w_muxed_v_16, w_gpio[16], mux_4_gpio_16); + tranif1 tran_gpio_17 (w_muxed_v_17, w_gpio[17], mux_4_gpio_17); + tranif1 tran_gpio_18 (w_muxed_h_00, w_gpio[18], mux_4_gpio_18); + tranif1 tran_gpio_19 (w_muxed_h_01, w_gpio[19], mux_4_gpio_19); + tranif1 tran_gpio_20 (w_muxed_h_02, w_gpio[20], mux_4_gpio_20); + tranif1 tran_gpio_21 (w_muxed_h_03, w_gpio[21], mux_4_gpio_21); + + for (genvar i = 0; i < 4; ++i) begin : gen_spih_sd_io + pullup (w_spi_hostd_sd[i]); + end + + for (genvar i = 0; i < SpihNumCs; ++i) begin : gen_spih_cs_io + pullup (w_spi_hostd_csb[i]); + end + + for (genvar i = 0 ; i // Alessandro Ottaviano // Maicol Ciani +// Victor Isachi -// The security island is inaccessible from other parts of the SoC, hence we -// need to preload it from the testbench. This testbench checks the -// mailbox-based communication between the security_island and other subsystems. +// Main testbench for carfield chip. It contains code sequences to boot the +// various islands standalone or in cooperation. -module tb_carfield_soc; +module tb_astral; import uvm_pkg::*; import carfield_pkg::*; import cheshire_pkg::*; import carfield_configuration::*; + import astral_padframe_periph_config_reg_pkg::*; + import pkg_internal_astral_padframe_periph::*; - // carfield top - carfield_soc_fixture fix(); + astral_fixture fix(); bit jtag_check_write = 1'b0; // cheshire @@ -34,7 +35,7 @@ module tb_carfield_soc; // hyperbus localparam int unsigned HyperbusTburstMax = carfield_configuration::HyperBusBase + 32'h8; - // mailbox unit + // MailBox parameter logic [31:0] CAR_MBOX_BASE = 32'h40000000; parameter logic [31:0] CAR_NUM_MAILBOXES = 32'h25; parameter logic [31:0] MBOX_INT_SND_STAT_OFFSET = 32'h00; @@ -55,27 +56,37 @@ module tb_carfield_soc; logic [63:0] unused; - logic secure_boot; + // bypass pll + logic bypass_pll; + + // secure boot mode + logic secure_boot; // Decide whether to preload hyperram model at time 0 logic hyp_user_preload; logic chs_mem_rand; + // Pad synchronization + event pad_configured; + // timing format for $display("...$t..", $realtime) initial begin : timing_format $timeformat(-9, 0, "ns", 9); end : timing_format - // Cheshire standalone binary execution initial begin // Fetch plusargs or use safe (fail-fast) defaults + if (!$value$plusargs("BYPASS_PLL=%d", bypass_pll)) bypass_pll = 0; if (!$value$plusargs("SECURE_BOOT=%d", secure_boot)) secure_boot = 0; if (!$value$plusargs("CHS_BOOTMODE=%d", boot_mode)) boot_mode = 0; if (!$value$plusargs("CHS_PRELMODE=%d", preload_mode)) preload_mode = 0; if (!$value$plusargs("CHS_BINARY=%s", chs_preload_elf)) chs_preload_elf = ""; if (!$value$plusargs("CHS_IMAGE=%s", chs_boot_hex)) chs_boot_hex = ""; - if (!$value$plusargs("CHS_MEM_RAND=%d", chs_mem_rand)) chs_mem_rand = 0; + if (!$value$plusargs("CHS_MEM_RAND=%d", chs_mem_rand)) chs_mem_rand = 0; + + // PLL bypass + fix.set_bypass_pll(bypass_pll); // Set boot mode and preload boot image if there is one fix.set_secure_boot(secure_boot); @@ -88,6 +99,12 @@ module tb_carfield_soc; // Wait for reset fix.chs_vip.wait_for_reset(); + // Wait for FLL lock + fix.wait_fll_lock(); + + // Initialize JTAG at first + fix.chs_vip.jtag_init(); + // We need to initialize memories after the reset due to limitations of the memory models. if (chs_mem_rand) begin `ifdef CHS_NETLIST @@ -108,42 +125,50 @@ module tb_carfield_soc; $display("[TB] INFO: Randomizing LLC memory not supported for RTL sim. Use +initmem"); `endif end - + // Writing max burst length in Hyperbus configuration registers to // prevent the Verification IPs from triggering timing checks. - $display("[TB] INFO: Configuring Hyperbus through serial link."); - fix.chs_vip.slink_write_32(HyperbusTburstMax, 32'd128); + if (preload_mode == 1) begin: gen_slink_hyperbus_cfg + // Configure Serial link padframe + fix.configure_sl_pad(jtag_check_write); - // If the safety island is enabled, when Cheshire is offloading to it - // it should be set in passive preload bootmode - `ifdef SAFED_PRESENT - fix.boot_mode_safed = safety_island_pkg::Preloaded; - `else - fix.boot_mode_safed = '0; - `endif + -> pad_configured; + $display("[TB] INFO: Configuring Hyperbus through serial link."); + fix.chs_vip.slink_write_32(HyperbusTburstMax, 32'd128); + end else begin: gen_jtag_hyperbus_cfg + $display("[TB] INFO: Configuring Hyperbus through JTAG."); + fix.chs_vip.jtag_write_reg32(HyperbusTburstMax, 32'd128, 1); + end + // When Cheshire is offloading to safety island, the latter should be set in passive preloaded + // bootmode +`ifdef SAFED_PRESENT + fix.gen_safed_vip.safed_vip.set_safed_boot_mode(SafetyIslandPreloaded); +`endif // Preload in idle mode or wait for completion in autonomous boot if (boot_mode == 0) begin // Idle boot: preload with the specified mode case (preload_mode) - 0: begin // Standalone JTAG passive preload + 0: begin // Standalone JTAG passive preload // Cheshire is_dram = uvm_re_match("dram",chs_preload_elf); if(~is_dram) begin $display("[TB] %t - Wait for HyperRAM", $realtime); repeat(HyperRstCycles) - @(posedge fix.clk); +`ifndef CARFIELD_CHIP_NETLIST + @(posedge fix.i_dut.periph_clk); +`else + #10ns; +`endif end - fix.chs_vip.jtag_init(); $display("[TB] %t - Loading '%s' through JTAG", $realtime, chs_preload_elf); fix.chs_vip.jtag_elf_run(chs_preload_elf); fix.chs_vip.jtag_wait_for_eoc(exit_code); end 1: begin // Standalone Serial Link passive preload - // Cheshire $display("[TB] %t - Loading '%s' through SLINK", $realtime, chs_preload_elf); fix.chs_vip.slink_elf_run(chs_preload_elf); fix.chs_vip.slink_wait_for_eoc(exit_code); - end 2: begin // Standalone UART passive preload + end 2: begin // Standalone UART passive preload fix.chs_vip.uart_debug_elf_run_and_wait(chs_preload_elf, exit_code); end 3: begin // Secure boot: Opentitan booting CVA6 fix.chs_vip.slink_elf_preload(chs_preload_elf, unused); @@ -156,14 +181,24 @@ module tb_carfield_soc; endcase end else if (boot_mode == 1) begin $fatal(1, "Unsupported boot mode %d (SD Card)!", boot_mode); + end else if (boot_mode == 2) begin + // Configure SPI padframe + fix.configure_spi_pad(jtag_check_write); + // Autonomous boot: Only poll return code + $display("[TB] %t - Entering autonomous boot mode", $realtime); + fix.chs_vip.jtag_wait_for_eoc(exit_code); end else begin + // Configure I2C padframe + fix.configure_i2c_pad(jtag_check_write); // Autonomous boot: Only poll return code $display("[TB] %t - Entering autonomous boot mode", $realtime); - fix.chs_vip.jtag_init(); fix.chs_vip.jtag_wait_for_eoc(exit_code); end - // Eventually wait for HWRoT to end initialization anda ssert Ibex's fetch enable + // Sample carfield's clock source frequencies (host, alt, periph) + //fix.sample_freq_debug_signals(); + + // Eventually wait for HWRoT to end initialization and assert Ibex's fetch enable fix.passthrough_or_wait_for_secd_hw_init(); // Wait for the UART to finish reading the current byte @@ -190,20 +225,29 @@ module tb_carfield_soc; initial begin // Fetch plusargs or use safe (fail-fast) defaults - if (!$value$plusargs("SECURE_BOOT=%d", secure_boot)) secure_boot = 0; + if (!$value$plusargs("BYPASS_PLL=%d", bypass_pll)) bypass_pll = 0; + if (!$value$plusargs("SECURE_BOOT=%d", secure_boot)) secure_boot = 0; if (!$value$plusargs("SAFED_BOOTMODE=%d", safed_boot_mode)) safed_boot_mode = 0; if (!$value$plusargs("SAFED_BINARY=%s", safed_preload_elf)) safed_preload_elf = ""; + + // PLL bypass + fix.set_bypass_pll(bypass_pll); // set secure boot mode fix.set_secure_boot(secure_boot); // set boot mode before reset - fix.boot_mode_safed = safed_boot_mode; + fix.gen_safed_vip.safed_vip.set_safed_boot_mode(safed_boot_mode); if (safed_preload_elf != "") begin fix.gen_safed_vip.safed_vip.safed_wait_for_reset(); + // Wait for FLL lock + fix.wait_fll_lock(); + + wait (pad_configured.triggered); + // Writing max burst length in Hyperbus configuration registers to // prevent the Verification IPs from triggering timing checks. $display("[TB] INFO: Configuring Hyperbus through serial link."); @@ -225,7 +269,7 @@ module tb_carfield_soc; end 1: begin fix.gen_safed_vip.safed_vip.axi_safed_elf_run(safed_preload_elf); fix.gen_safed_vip.safed_vip.axi_safed_wait_for_eoc(safed_exit_code, safed_exit_status); - end default: begin + end default: begin $fatal(1, "Unsupported boot mode %d (reserved)!", safed_boot_mode); end endcase @@ -235,30 +279,36 @@ module tb_carfield_soc; end end - // security island + // security island standalone if (CarfieldIslandsCfg.secured.enable) begin: gen_secured_tb string secd_preload_elf; string secd_flash_vmem; logic secd_boot_mode; - - // security island standalone + initial begin // Fetch plusargs or use safe (fail-fast) defaults + if (!$value$plusargs("BYPASS_PLL=%d", bypass_pll)) bypass_pll = 0; if (!$value$plusargs("SECURE_BOOT=%d", secure_boot)) secure_boot = 0; if (!$value$plusargs("SECD_IMAGE=%s", secd_flash_vmem)) secd_flash_vmem = ""; if (!$value$plusargs("SECD_BINARY=%s", secd_preload_elf)) secd_preload_elf = ""; - if (!$value$plusargs("SECD_BOOTMODE=%d", secd_boot_mode)) secd_boot_mode = 0; + if (!$value$plusargs("SECD_BOOTMODE=%d", secd_boot_mode)) secd_boot_mode = 0; + + // PLL bypass + fix.set_bypass_pll(bypass_pll); // set secure boot mode fix.set_secure_boot(secure_boot); // set bootmode - fix.gen_scured_vip.secd_vip.set_secd_boot_mode(secd_boot_mode); + fix.gen_secured_vip.secd_vip.set_secd_boot_mode(secd_boot_mode); if (secd_preload_elf != "" || secd_flash_vmem != "") begin // Wait for reset fix.chs_vip.wait_for_reset(); + // Wait for FLL lock + fix.wait_fll_lock(); + // Writing max burst length in Hyperbus configuration registers to // prevent the Verification IPs from triggering timing checks. $display("[TB] INFO: Configuring Hyperbus through serial link."); @@ -268,17 +318,17 @@ module tb_carfield_soc; 0: begin // Wait before security island HW is initialized repeat(10000) - @(posedge fix.clk); - fix.gen_scured_vip.secd_vip.debug_secd_module_init(); - fix.gen_scured_vip.secd_vip.load_secd_binary(secd_preload_elf); - fix.gen_scured_vip.secd_vip.jtag_secd_data_preload(); - fix.gen_scured_vip.secd_vip.jtag_secd_wakeup(32'hE0000080); - fix.gen_scured_vip.secd_vip.jtag_secd_wait_eoc(); + @(posedge fix.ref_clk); + fix.gen_secured_vip.secd_vip.debug_secd_module_init(); + fix.gen_secured_vip.secd_vip.load_secd_binary(secd_preload_elf); + fix.gen_secured_vip.secd_vip.jtag_secd_data_preload(); + fix.gen_secured_vip.secd_vip.jtag_secd_wakeup(32'hE0000080); + fix.gen_secured_vip.secd_vip.jtag_secd_wait_eoc(); end 1: begin - fix.gen_scured_vip.secd_vip.spih_norflash_preload(secd_flash_vmem); + fix.gen_secured_vip.secd_vip.spih_norflash_preload(secd_flash_vmem); repeat(10000) - @(posedge fix.clk); - fix.gen_scured_vip.secd_vip.jtag_secd_wait_eoc(); + @(posedge fix.ref_clk); + fix.gen_secured_vip.secd_vip.jtag_secd_wait_eoc(); end default: begin $fatal(1, "Unsupported boot mode %d (reserved)!", secd_boot_mode); end @@ -314,15 +364,34 @@ module tb_carfield_soc; initial begin // Fetch plusargs or use safe (fail-fast) defaults + if (!$value$plusargs("BYPASS_PLL=%d", bypass_pll)) bypass_pll = 0; if (!$value$plusargs("PULPD_BOOTMODE=%d", pulpd_boot_mode)) pulpd_boot_mode = 0; if (!$value$plusargs("PULPD_BINARY=%s", pulpd_preload_elf)) pulpd_preload_elf = ""; if (!$value$plusargs("HYP_USER_PRELOAD=%s", hyp_user_preload)) hyp_user_preload = 0; - // Wait for reset - fix.chs_vip.wait_for_reset(); - if (pulpd_preload_elf != "") begin + // Wait for system reset from Cheshire VIP + fix.chs_vip.wait_for_reset(); + + // PLL bypass + fix.set_bypass_pll(bypass_pll); + + // Wait for FLL lock + fix.wait_fll_lock(); + + // Configure padframe for Serial Link usage depending + // on the selected preload-mode + if (pulpd_boot_mode == 1) begin: gen_pulpd_slink_cfg + // Configure Serial link padframe + fix.configure_sl_pad(jtag_check_write); + + -> pad_configured; + end else begin: pulpd_jtag_init + $display("[JTAG PULPD] Init "); + fix.chs_vip.jtag_init(); + end + $display("[TB] %t - Enabling PULP cluster clock for stand-alone tests ", $realtime); // Clock island after PoR fix.chs_vip.slink_write_32(CarSocCtrlPulpdClkEnRegAddr, 32'h1); @@ -332,9 +401,6 @@ module tb_carfield_soc; case (pulpd_boot_mode) 0: begin - // JTAG - $display("[JTAG PULPD] Init "); - fix.chs_vip.jtag_init(); $display("[JTAG PULPD] Halt the core and load the binary to L2 "); fix.chs_vip.jtag_elf_halt_load(pulpd_preload_elf, pulpd_binary_entry ); @@ -358,9 +424,7 @@ module tb_carfield_soc; else $display("[JTAG PULP] SUCCESS"); end - 1: begin - // serial link - + 1: begin // -> Serial Link // preload $display("[SLINK PULPD] Preload the binary to L2 "); fix.chs_vip.slink_elf_preload(pulpd_preload_elf, pulpd_binary_entry); @@ -390,6 +454,8 @@ module tb_carfield_soc; endcase $finish; + end else begin + $display("[PULP TB] No binary preloaded."); end // Fast preload of hyperram @@ -405,8 +471,14 @@ module tb_carfield_soc; $display("[TB] %t - Wait for HyperRAM", $realtime); repeat(HyperRstCycles) - @(posedge fix.clk); - + `ifndef CARFIELD_CHIP_NETLIST + @(posedge fix.i_dut.periph_clk); + `else + #10ns; + `endif + + wait (pad_configured.triggered); + $display("[TB] %t - Enabling PULP cluster clock for stand-alone tests ", $realtime); // Clock island after PoR fix.chs_vip.slink_write_32(CarSocCtrlPulpdClkEnRegAddr, 32'h1); @@ -452,10 +524,14 @@ module tb_carfield_soc; initial begin // Fetch plusargs or use safe (fail-fast) defaults + if (!$value$plusargs("BYPASS_PLL=%d", bypass_pll)) bypass_pll = 0; if (!$value$plusargs("SECURE_BOOT=%d", secure_boot)) secure_boot = 0; if (!$value$plusargs("SPATZD_BOOTMODE=%d", spatzd_boot_mode)) spatzd_boot_mode = 0; if (!$value$plusargs("SPATZD_BINARY=%s", spatzd_preload_elf)) spatzd_preload_elf = ""; + // PLL bypass + fix.set_bypass_pll(bypass_pll); + // set secure boot mode fix.set_secure_boot(secure_boot); @@ -464,6 +540,11 @@ module tb_carfield_soc; // Wait for reset fix.chs_vip.wait_for_reset(); + // Wait for FLL lock + fix.wait_fll_lock(); + + wait (pad_configured.triggered); + // Writing max burst length in Hyperbus configuration registers to // prevent the Verification IPs from triggering timing checks. $display("[TB] INFO: Configuring Hyperbus through serial link."); @@ -545,10 +626,9 @@ module tb_carfield_soc; $fatal(1, "Unsupported boot mode %d (reserved)!", spatzd_boot_mode); end endcase - $finish; end end end -endmodule +endmodule: tb_astral diff --git a/target/sim/src/carfield_fix.sv b/target/sim/src/carfield_fix.sv index 1f2fc951..bff92abc 100644 --- a/target/sim/src/carfield_fix.sv +++ b/target/sim/src/carfield_fix.sv @@ -33,12 +33,12 @@ module carfield_soc_fixture; localparam cheshire_cfg_t DutCfg = carfield_pkg::CarfieldCfgDefault; `CHESHIRE_TYPEDEF_ALL(, DutCfg) - localparam time ClkPeriodSys = 10ns; + localparam time ClkPeriodSys = 10ns; localparam time ClkPeriodJtag = 40ns; localparam time ClkPeriodPeriph = 4ns; localparam time ClkPeriodRtc = 1000ns; // 1MHz RTC clock. Note: needs to equal // `DutCfg.RTCFreq` for successful autonomous boot - // (e.g., SPI) + // (e.g., SPI) localparam int unsigned RstCycles = 5; localparam real TAppl = 0.1; localparam real TTest = 0.9; @@ -135,6 +135,12 @@ module carfield_soc_fixture; logic [NumPhys-1:0] hyper_dq_oe_o; logic [NumPhys-1:0] hyper_reset_no; + logic ptme_clk, ptme_enc; + logic tc_active, tc_clock, tc_data; + logic [2:0] hpc_addr; + logic hpc_cmd_en, hpc_smp; + logic [1:0] llc_line; + wire [NumPhys-1:0][NumChips-1:0] pad_hyper_csn; wire [NumPhys-1:0] pad_hyper_ck; wire [NumPhys-1:0] pad_hyper_ckn; @@ -142,6 +148,11 @@ module carfield_soc_fixture; wire [NumPhys-1:0] pad_hyper_resetn; wire [NumPhys-1:0][7:0] pad_hyper_dq; + wire spw_data_in, spw_strobe_in; + wire spw_data_out, spw_strobe_out; + + logic eth_clk; + clk_rst_gen #( .ClkPeriod ( ClkPeriodPeriph ), .RstClkCycles ( RstCycles ) @@ -238,6 +249,24 @@ module carfield_soc_fixture; .hyper_dq_o ( hyper_dq_o ), .hyper_dq_oe_o ( hyper_dq_oe_o ), .hyper_reset_no ( hyper_reset_no ), + .tc_active_i ( tc_active ), + .tc_clock_i ( tc_clock ), + .tc_data_i ( tc_data ), + .ptme_clk_o ( ptme_clk ), + .ptme_enc_o ( ptme_enc ), + .ptme_sync_o ( ), + .ptme_ext_clk_i ( '0 ), + .hpc_addr_o ( hpc_addr ), + .hpc_cmd_en_o ( hpc_cmd_en ), + .hpc_sample_o ( hpc_smp ), + .llc_line_o ( llc_line ), + .obt_ext_clk_i ( '0 ), + .obt_pps_in_i ( '0 ), + .obt_sync_out_o ( ), + .spw_data_i ( spw_data_in ), + .spw_strb_i ( spw_strobe_in ), + .spw_data_o ( spw_data_out ), + .spw_strb_o ( spw_strobe_out ), .ext_reg_async_slv_req_i ( '0 ), .ext_reg_async_slv_ack_o ( ), .ext_reg_async_slv_data_i ( '0 ), @@ -247,9 +276,7 @@ module carfield_soc_fixture; .debug_signals_o ( ) ); - logic eth_clk; - - assign eth_clk = i_dut.gen_ethernet.eth_clk; + assign eth_clk = i_dut.eth_clk; ////////////////// // Carfield VIP // @@ -298,6 +325,19 @@ module carfield_soc_fixture; .axi_slvs_rsp ( ext_to_vip_rsp ), .axi_muxed_req ( axi_muxed_req ), .axi_muxed_rsp ( axi_muxed_rsp ), + .ptme_clk_i ( ptme_clk ), + .ptme_enc_i ( ptme_enc ), + .hpc_addr_i ( hpc_addr ), + .hpc_cmd_en_i ( hpc_cmd_en ), + .hpc_smp_i ( hpc_smp ), + .llc_line_i ( llc_line ), + .tc_active ( tc_active ), + .tc_clk ( tc_clock ), + .tc_data ( tc_data ), + .spw_din ( spw_data_out ), + .spw_sin ( spw_strobe_out), + .spw_dout ( spw_data_in ), + .spw_sout ( spw_strobe_in ), .* ); diff --git a/target/sim/src/vip_carfield_soc.sv b/target/sim/src/vip_carfield_soc.sv index df8aaee8..e6e44bdd 100644 --- a/target/sim/src/vip_carfield_soc.sv +++ b/target/sim/src/vip_carfield_soc.sv @@ -3,6 +3,8 @@ // SPDX-License-Identifier: SHL-0.51 // // Alessandro Ottaviano +// Chaoqun Liang + // collects all existing verification ip (vip) for carfield SoC @@ -64,7 +66,20 @@ module vip_carfield_soc output axi_slv_ext_rsp_t [NumAxiExtSlvPorts-1:0] axi_slvs_rsp, // Multiplexed virtual AXI ports output axi_slv_ext_req_t axi_muxed_req, - input axi_slv_ext_rsp_t axi_muxed_rsp + input axi_slv_ext_rsp_t axi_muxed_rsp, + input logic ptme_clk_i, + input logic ptme_enc_i, + input logic [2:0] hpc_addr_i, + input logic hpc_cmd_en_i, + input logic hpc_smp_i, + input logic [1:0] llc_line_i, + output logic tc_active, + output logic tc_clk, + output logic tc_data, + input logic spw_din, + input logic spw_sin, + output logic spw_dout, + output logic spw_sout ); `include "cheshire/typedef.svh" @@ -89,6 +104,7 @@ module vip_carfield_soc .clk_o ( clk ), .rst_no ( rst_n ) ); + clk_rst_gen #( .ClkPeriod ( ClkPeriodPeriph ), @@ -196,72 +212,72 @@ module vip_carfield_soc .axi_rsp_o ( axi_rsp_mem ) ); - initial begin + initial begin - @(posedge eth_rx_irq); - @(posedge periph_clk); + @(posedge eth_rx_irq); + @(posedge periph_clk); - @(posedge periph_clk); - reg_drv_rx.send_write( CarfieldIslandsCfg.ethernet.base + eth_idma_reg_pkg::ETH_IDMA_MACLO_ADDR_OFFSET, 32'h98001032, 'hf, reg_error); //lower 32bits of MAC address - @(posedge periph_clk); + @(posedge periph_clk); + reg_drv_rx.send_write( CarfieldIslandsCfg.ethernet.base + eth_idma_reg_pkg::ETH_IDMA_MACLO_ADDR_OFFSET, 32'h98001032, 'hf, reg_error); //lower 32bits of MAC address + @(posedge periph_clk); - reg_drv_rx.send_write( CarfieldIslandsCfg.ethernet.base + eth_idma_reg_pkg::ETH_IDMA_MACHI_MDIO_OFFSET, 32'h00002070, 'hf, reg_error); //upper 16bits of MAC address + other configuration set to false/0 - @(posedge periph_clk); + reg_drv_rx.send_write( CarfieldIslandsCfg.ethernet.base + eth_idma_reg_pkg::ETH_IDMA_MACHI_MDIO_OFFSET, 32'h00002070, 'hf, reg_error); //upper 16bits of MAC address + other configuration set to false/0 + @(posedge periph_clk); - reg_drv_rx.send_write( CarfieldIslandsCfg.ethernet.base + eth_idma_reg_pkg::ETH_IDMA_SRC_ADDR_OFFSET, 32'h0, 'hf, reg_error ); // SRC_ADDR - @(posedge periph_clk); + reg_drv_rx.send_write( CarfieldIslandsCfg.ethernet.base + eth_idma_reg_pkg::ETH_IDMA_SRC_ADDR_OFFSET, 32'h0, 'hf, reg_error ); // SRC_ADDR + @(posedge periph_clk); - reg_drv_rx.send_write( CarfieldIslandsCfg.ethernet.base + eth_idma_reg_pkg::ETH_IDMA_DST_ADDR_OFFSET, 32'h0, 'hf, reg_error); // DST_ADDR - @(posedge periph_clk); + reg_drv_rx.send_write( CarfieldIslandsCfg.ethernet.base + eth_idma_reg_pkg::ETH_IDMA_DST_ADDR_OFFSET, 32'h0, 'hf, reg_error); // DST_ADDR + @(posedge periph_clk); - reg_drv_rx.send_write( CarfieldIslandsCfg.ethernet.base + eth_idma_reg_pkg::ETH_IDMA_LENGTH_OFFSET, 32'h40,'hf , reg_error); // Size in bytes - @(posedge periph_clk); + reg_drv_rx.send_write( CarfieldIslandsCfg.ethernet.base + eth_idma_reg_pkg::ETH_IDMA_LENGTH_OFFSET, 32'h40,'hf , reg_error); // Size in bytes + @(posedge periph_clk); - reg_drv_rx.send_write( CarfieldIslandsCfg.ethernet.base + eth_idma_reg_pkg::ETH_IDMA_SRC_PROTOCOL_OFFSET, 32'h5, 'hf , reg_error); // src protocol - @(posedge periph_clk); + reg_drv_rx.send_write( CarfieldIslandsCfg.ethernet.base + eth_idma_reg_pkg::ETH_IDMA_SRC_PROTOCOL_OFFSET, 32'h5, 'hf , reg_error); // src protocol + @(posedge periph_clk); - reg_drv_rx.send_write( CarfieldIslandsCfg.ethernet.base + eth_idma_reg_pkg::ETH_IDMA_DST_PROTOCOL_OFFSET, 32'h0,'hf , reg_error); // dst protocol - @(posedge periph_clk); + reg_drv_rx.send_write( CarfieldIslandsCfg.ethernet.base + eth_idma_reg_pkg::ETH_IDMA_DST_PROTOCOL_OFFSET, 32'h0,'hf , reg_error); // dst protocol + @(posedge periph_clk); - reg_drv_rx.send_write( CarfieldIslandsCfg.ethernet.base + eth_idma_reg_pkg::ETH_IDMA_REQ_VALID_OFFSET, 'h1, 'hf , reg_error); // req valid - @(posedge periph_clk); - - //wait till all data written into rx_axi_sim_mem - while(1) begin - reg_drv_rx.send_read( CarfieldIslandsCfg.ethernet.base + eth_idma_reg_pkg::ETH_IDMA_RSP_VALID_OFFSET, rx_rsp_valid, reg_error); - if( rx_rsp_valid ) begin - break; - end + reg_drv_rx.send_write( CarfieldIslandsCfg.ethernet.base + eth_idma_reg_pkg::ETH_IDMA_REQ_VALID_OFFSET, 'h1, 'hf , reg_error); // req valid @(posedge periph_clk); - end - // Tx test starts here: external back to core - @(posedge periph_clk); - reg_drv_rx.send_write( CarfieldIslandsCfg.ethernet.base + eth_idma_reg_pkg::ETH_IDMA_MACLO_ADDR_OFFSET, 32'h98001032, 'hf, reg_error); //lower 32bits of MAC address - @(posedge periph_clk); + //wait till all data written into rx_axi_sim_mem + while(1) begin + reg_drv_rx.send_read( CarfieldIslandsCfg.ethernet.base + eth_idma_reg_pkg::ETH_IDMA_RSP_VALID_OFFSET, rx_rsp_valid, reg_error); + if( rx_rsp_valid ) begin + break; + end + @(posedge periph_clk); + end + + // Tx test starts here: external back to core + @(posedge periph_clk); + reg_drv_rx.send_write( CarfieldIslandsCfg.ethernet.base + eth_idma_reg_pkg::ETH_IDMA_MACLO_ADDR_OFFSET, 32'h98001032, 'hf, reg_error); //lower 32bits of MAC address + @(posedge periph_clk); - reg_drv_rx.send_write( CarfieldIslandsCfg.ethernet.base + eth_idma_reg_pkg::ETH_IDMA_MACHI_MDIO_OFFSET, 32'h00002070, 'hf, reg_error); //upper 16bits of MAC address + other configuration set to false/0 - @(posedge periph_clk); + reg_drv_rx.send_write( CarfieldIslandsCfg.ethernet.base + eth_idma_reg_pkg::ETH_IDMA_MACHI_MDIO_OFFSET, 32'h00002070, 'hf, reg_error); //upper 16bits of MAC address + other configuration set to false/0 + @(posedge periph_clk); - reg_drv_rx.send_write( CarfieldIslandsCfg.ethernet.base + eth_idma_reg_pkg::ETH_IDMA_SRC_ADDR_OFFSET, 32'h0, 'hf, reg_error ); // SRC_ADDR - @(posedge periph_clk); + reg_drv_rx.send_write( CarfieldIslandsCfg.ethernet.base + eth_idma_reg_pkg::ETH_IDMA_SRC_ADDR_OFFSET, 32'h0, 'hf, reg_error ); // SRC_ADDR + @(posedge periph_clk); - reg_drv_rx.send_write( CarfieldIslandsCfg.ethernet.base + eth_idma_reg_pkg::ETH_IDMA_DST_ADDR_OFFSET, 32'h0, 'hf, reg_error); // DST_ADDR - @(posedge periph_clk); + reg_drv_rx.send_write( CarfieldIslandsCfg.ethernet.base + eth_idma_reg_pkg::ETH_IDMA_DST_ADDR_OFFSET, 32'h0, 'hf, reg_error); // DST_ADDR + @(posedge periph_clk); - reg_drv_rx.send_write( CarfieldIslandsCfg.ethernet.base + eth_idma_reg_pkg::ETH_IDMA_LENGTH_OFFSET, 32'h40,'hf , reg_error); // Size in bytes - @(posedge periph_clk); + reg_drv_rx.send_write( CarfieldIslandsCfg.ethernet.base + eth_idma_reg_pkg::ETH_IDMA_LENGTH_OFFSET, 32'h40,'hf , reg_error); // Size in bytes + @(posedge periph_clk); - reg_drv_rx.send_write( CarfieldIslandsCfg.ethernet.base + eth_idma_reg_pkg::ETH_IDMA_SRC_PROTOCOL_OFFSET, 32'h0, 'hf , reg_error); // src protocol - @(posedge periph_clk); + reg_drv_rx.send_write( CarfieldIslandsCfg.ethernet.base + eth_idma_reg_pkg::ETH_IDMA_SRC_PROTOCOL_OFFSET, 32'h0, 'hf , reg_error); // src protocol + @(posedge periph_clk); - reg_drv_rx.send_write( CarfieldIslandsCfg.ethernet.base + eth_idma_reg_pkg::ETH_IDMA_DST_PROTOCOL_OFFSET, 32'h5,'hf , reg_error); // dst protocol - @(posedge periph_clk); + reg_drv_rx.send_write( CarfieldIslandsCfg.ethernet.base + eth_idma_reg_pkg::ETH_IDMA_DST_PROTOCOL_OFFSET, 32'h5,'hf , reg_error); // dst protocol + @(posedge periph_clk); - reg_drv_rx.send_write( CarfieldIslandsCfg.ethernet.base + eth_idma_reg_pkg::ETH_IDMA_REQ_VALID_OFFSET, 'h1, 'hf , reg_error); // req valid - @(posedge periph_clk); + reg_drv_rx.send_write( CarfieldIslandsCfg.ethernet.base + eth_idma_reg_pkg::ETH_IDMA_REQ_VALID_OFFSET, 'h1, 'hf , reg_error); // req valid + @(posedge periph_clk); + end end -end ////////////// // Hyperbus // @@ -367,6 +383,35 @@ end .mst_resp_i ( axi_muxed_rsp ) ); + /* + PTME_EMULATOR i_ptme_emulator ( + .Reset_N ( rst_n ), + .CADUClk ( ptme_clk_i ), + .CADUOut ( ptme_enc_i ) + ); + */ + + tb_MuSA_compact i_tb_MuSA_compact ( + .CADUClk ( ptme_clk_i), + .CADUOut ( ptme_enc_i), + .HPC_ADDR ( hpc_addr_i), + .HPC_CMD_EN ( hpc_cmd_en_i), + .HPC_SMP ( hpc_smp_i), + .LLC_LINE ( llc_line_i), + .RST_BOARD ( rst_n), + .TCA ( tc_active), + .TCC ( tc_clk), + .TCS ( tc_data) + ); + + spw_codec_tb i_spw_codec_tb ( + .DATA_IN (spw_din), + .STROBE_IN (spw_sin), + .DATA_OUT (spw_dout), + .STROBE_OUT(spw_sout) + ); + + endmodule module vip_carfield_soc_tristate import carfield_pkg::*; # ( diff --git a/target/sim/vsim/start.carfield_soc.tcl b/target/sim/vsim/start.carfield_soc.tcl index 08f9c153..968938fa 100644 --- a/target/sim/vsim/start.carfield_soc.tcl +++ b/target/sim/vsim/start.carfield_soc.tcl @@ -12,6 +12,7 @@ if {[info exists VSIM_FLAGS]} { append flags "${VSIM_FLAGS}" } set pargs "" if {[info exists HYP_USER_PRELOAD]} { append pargs "+HYP_USER_PRELOAD=${HYP_USER_PRELOAD} " } +if {[info exists BYPASS_PLL]} { append pargs "+BYPASS_PLL=${BYPASS_PLL} " } if {[info exists SECURE_BOOT]} { append pargs "+SECURE_BOOT=${SECURE_BOOT} " } if {[info exists CHS_BOOTMODE]} { append pargs "+CHS_BOOTMODE=${CHS_BOOTMODE} " } if {[info exists CHS_PRELMODE]} { append pargs "+CHS_PRELMODE=${CHS_PRELMODE} " } diff --git a/target/synth/src/carfield_synth_wrap.sv b/target/synth/src/carfield_synth_wrap.sv deleted file mode 100644 index 991cc885..00000000 --- a/target/synth/src/carfield_synth_wrap.sv +++ /dev/null @@ -1,218 +0,0 @@ -// Copyright 2023 ETH Zurich and University of Bologna. -// Solderpad Hardware License, Version 0.51, see LICENSE for details. -// SPDX-License-Identifier: SHL-0.51 -// -// Thomas Benz -// Luca Valente -// Yvan Tortorella -// Alessandro Ottaviano - -`include "cheshire/typedef.svh" -`include "axi/typedef.svh" -`include "apb/typedef.svh" - -// Wrap for synthesis of carfield -module carfield_synth_wrap - import carfield_pkg::*; - import carfield_reg_pkg::*; - import cheshire_pkg::*; -#( - parameter int unsigned HypNumPhys = 2, - parameter int unsigned HypNumChips = 2, -) ( - // host clock - input logic host_clk_i, - // peripheral clock - input logic periph_clk_i, - // accelerator and island clock - input logic alt_clk_i, - // external reference clock for timers (CLINT, islands) - input logic rt_clk_i, - - input logic pwr_on_rst_ni, - - // testmode pin - input logic test_mode_i, - // Cheshire BOOT pins (3 pins) - input logic [1:0] boot_mode_i, - // Cheshire JTAG Interface - input logic jtag_tck_i, - input logic jtag_trst_ni, - input logic jtag_tms_i, - input logic jtag_tdi_i, - output logic jtag_tdo_o, - output logic jtag_tdo_oe_o, - // Secure Subsystem JTAG Interface - input logic jtag_ot_tck_i, - input logic jtag_ot_trst_ni, - input logic jtag_ot_tms_i, - input logic jtag_ot_tdi_i, - output logic jtag_ot_tdo_o, - output logic jtag_ot_tdo_oe_o, - // Safety Island JTAG Interface - input logic jtag_safety_island_tck_i, - input logic jtag_safety_island_trst_ni, - input logic jtag_safety_island_tms_i, - input logic jtag_safety_island_tdi_i, - output logic jtag_safety_island_tdo_o, - // Secure Subsystem BOOT pins - input logic [1:0] bootmode_ot_i, - // unused by safety island -- tdo pad always out mode - output logic jtag_safe_isln_tdo_oe_o, - // Safety Island BOOT pins - input logic [1:0] bootmode_safe_isln_i, - // Host UART Interface - output logic uart_tx_o, - input logic uart_rx_i, - // Secure Subsystem UART Interface - output logic uart_ot_tx_o, - input logic uart_ot_rx_i, - // Host I2C Interface pins - output logic i2c_sda_o, - input logic i2c_sda_i, - output logic i2c_sda_en_o, - output logic i2c_scl_o, - input logic i2c_scl_i, - output logic i2c_scl_en_o, - // Host SPI Master Interface - output logic spih_sck_o, - output logic spih_sck_en_o, - output logic [SpihNumCs-1:0] spih_csb_o, - output logic [SpihNumCs-1:0] spih_csb_en_o, - output logic [ 3:0] spih_sd_o, - output logic [ 3:0] spih_sd_en_o, - input logic [ 3:0] spih_sd_i, - // Secure Subsystem QSPI Master Interface - output logic spih_ot_sck_o, - output logic spih_ot_sck_en_o, - output logic spih_ot_csb_o, - output logic spih_ot_csb_en_o, - output logic [ 3:0] spih_ot_sd_o, - output logic [ 3:0] spih_ot_sd_en_o, - input logic [ 3:0] spih_ot_sd_i, - // ETHERNET interface - input logic eth_rxck_i, - input logic eth_rxctl_i, - input logic [ 3:0] eth_rxd_i, - input logic eth_md_i, - output logic eth_txck_o, - output logic eth_txctl_o, - output logic [ 3:0] eth_txd_o, - output logic eth_md_o, - output logic eth_md_oe, - output logic eth_mdc_o, - output logic eth_rst_n_o, - // CAN interface - input logic can_rx_i, - output logic can_tx_o, - // GPIOs - input logic [31:0] gpio_i, - output logic [31:0] gpio_o, - output logic [31:0] gpio_en_o, - // Serial link interface - input logic [SlinkNumChan-1:0] slink_rcv_clk_i, - output logic [SlinkNumChan-1:0] slink_rcv_clk_o, - input logic [SlinkNumChan-1:0][SlinkNumLanes-1:0] slink_i, - output logic [SlinkNumChan-1:0][SlinkNumLanes-1:0] slink_o, - // HyperBus interface - output logic [HypNumPhys-1:0][HypNumChips-1:0] hyper_cs_no, - output logic [HypNumPhys-1:0] hyper_ck_o, - output logic [HypNumPhys-1:0] hyper_ck_no, - output logic [HypNumPhys-1:0] hyper_rwds_o, - input logic [HypNumPhys-1:0] hyper_rwds_i, - output logic [HypNumPhys-1:0] hyper_rwds_oe_o, - input logic [HypNumPhys-1:0][7:0] hyper_dq_i, - output logic [HypNumPhys-1:0][7:0] hyper_dq_o, - output logic [HypNumPhys-1:0] hyper_dq_oe_o, - output logic [HypNumPhys-1:0] hyper_reset_no, - // Debug signals - output carfield_debug_sigs_t debug_signals_o -); - - localparam cheshire_cfg_t DutCfg = carfield_pkg::CarfieldCfgDefault; - `CHESHIRE_TYPEDEF_ALL(, DutCfg) - - carfield #( - .Cfg ( DutCfg ), - .HypNumPhys ( HypNumPhys ), - .HypNumChips ( HypNumChips ), - .reg_req_t ( reg_req_t ), - .reg_rsp_t ( reg_rsp_t ) - ) i_dut ( - .host_clk_i , - .periph_clk_i , - .alt_clk_i , - .rt_clk_i , - .pwr_on_rst_ni , - .test_mode_i , - .boot_mode_i , - .jtag_tck_i , - .jtag_trst_ni , - .jtag_tms_i , - .jtag_tdi_i , - .jtag_tdo_o , - .jtag_tdo_oe_o , - .jtag_ot_tck_i , - .jtag_ot_trst_ni , - .jtag_ot_tms_i , - .jtag_ot_tdi_i , - .jtag_ot_tdo_o , - .jtag_ot_tdo_oe_o , - .jtag_safety_island_tck_i , - .jtag_safety_island_trst_ni, // Temporary - .jtag_safety_island_tms_i , // Temporary - .jtag_safety_island_tdi_i , // Temporary - .jtag_safety_island_tdo_o , - .uart_tx_o , - .uart_rx_i , - .uart_ot_tx_o , - .uart_ot_rx_i , - .i2c_sda_o , - .i2c_sda_i , - .i2c_sda_en_o , - .i2c_scl_o , - .i2c_scl_i , - .i2c_scl_en_o , - // hostd spi - .spih_sck_o , - .spih_sck_en_o , - .spih_csb_o , - .spih_csb_en_o , - .spih_sd_o , - .spih_sd_en_o , - .spih_sd_i , - // secd spi - .spih_ot_sck_o , - .spih_ot_sck_en_o , - .spih_ot_csb_o , - .spih_ot_csb_en_o , - .spih_ot_sd_o , - .spih_ot_sd_en_o , - .spih_ot_sd_i , - .gpio_i , - .gpio_o , - .gpio_en_o , - .slink_rcv_clk_i , - .slink_rcv_clk_o , - .slink_i , - .slink_o , - .hyper_cs_no , - .hyper_ck_o , - .hyper_ck_no , - .hyper_rwds_o , - .hyper_rwds_i , - .hyper_rwds_oe_o , - .hyper_dq_i , - .hyper_dq_o , - .hyper_dq_oe_o , - .hyper_reset_no , - .ext_reg_async_slv_req_i ( '0 ), - .ext_reg_async_slv_ack_o ( ), - .ext_reg_async_slv_data_i ( '0 ), - .ext_reg_async_slv_req_o ( ), - .ext_reg_async_slv_ack_i ( '0 ), - .ext_reg_async_slv_data_o ( ), - .debug_signals_o ( ) - ); - -endmodule