From 31d6c14bde5b73e4bc2d2d35c1a3f709278e7e62 Mon Sep 17 00:00:00 2001 From: Yvan Tortorella Date: Tue, 3 Sep 2024 09:50:14 +0200 Subject: [PATCH] Move scope of padframe and FLL drivers. --- sw/include/fll.h | 9 ++++++ sw/include/padframe.h | 37 +++++++++++++++++++++++- sw/tests/bare-metal/hostd/ethernet.c | 42 ++++------------------------ 3 files changed, 50 insertions(+), 38 deletions(-) diff --git a/sw/include/fll.h b/sw/include/fll.h index 8d15ee02..5fa91c17 100644 --- a/sw/include/fll.h +++ b/sw/include/fll.h @@ -60,4 +60,13 @@ void set_fll_clk_mul(uint32_t clk_mul, uint8_t fll_id){ write_fll_bitfield(clk_mul, fll_id, FLL_CONFIG_REG_I, FLL_CLK_MUL_MASK, FLL_CLK_MUL_OFFSET); } +void set_periph_fll(){ + // Configuring FLL + fll_normal(FLL_PERIPH_ID); + // What is the meaning of 0x3E7? + set_fll_clk_mul(0x3E7, FLL_PERIPH_ID); + // What is the meaning of 0x2? + set_fll_clk_div(0x2, FLL_PERIPH_ID); +} + #endif /*__FLL_H*/ diff --git a/sw/include/padframe.h b/sw/include/padframe.h index 0b2fec28..cdc90d67 100644 --- a/sw/include/padframe.h +++ b/sw/include/padframe.h @@ -28,4 +28,39 @@ void write_padframe_psel(uint8_t cfg_reg_offset, uint8_t psel){ writew(config_reg, PADFRAME_BASE_ADDRESS + cfg_reg_offset); } -#endif /*__PADFRAME_H*/ \ No newline at end of file +void padframe_ethernet_cfg() { + // Configuring padframe - mux + write_padframe_mux(PADFRAME_CONFIG_MUXED_V_07_MUX_SEL, PADFRAME_MUXED_V_07_SEL_ETHERNET_RXCK); + write_padframe_mux(PADFRAME_CONFIG_MUXED_V_08_MUX_SEL, PADFRAME_MUXED_V_08_SEL_ETHERNET_RXCTL); + write_padframe_mux(PADFRAME_CONFIG_MUXED_V_09_MUX_SEL, PADFRAME_MUXED_V_09_SEL_ETHERNET_RXD_0); + write_padframe_mux(PADFRAME_CONFIG_MUXED_V_10_MUX_SEL, PADFRAME_MUXED_V_10_SEL_ETHERNET_RXD_1); + write_padframe_mux(PADFRAME_CONFIG_MUXED_V_11_MUX_SEL, PADFRAME_MUXED_V_11_SEL_ETHERNET_RXD_2); + write_padframe_mux(PADFRAME_CONFIG_MUXED_V_12_MUX_SEL, PADFRAME_MUXED_V_12_SEL_ETHERNET_RXD_3); + write_padframe_mux(PADFRAME_CONFIG_MUXED_V_13_MUX_SEL, PADFRAME_MUXED_V_13_SEL_ETHERNET_TXCK); + write_padframe_mux(PADFRAME_CONFIG_MUXED_V_14_MUX_SEL, PADFRAME_MUXED_V_14_SEL_ETHERNET_TXCTL); + write_padframe_mux(PADFRAME_CONFIG_MUXED_V_15_MUX_SEL, PADFRAME_MUXED_V_15_SEL_ETHERNET_TXD_0); + write_padframe_mux(PADFRAME_CONFIG_MUXED_V_16_MUX_SEL, PADFRAME_MUXED_V_16_SEL_ETHERNET_TXD_1); + write_padframe_mux(PADFRAME_CONFIG_MUXED_V_17_MUX_SEL, PADFRAME_MUXED_V_17_SEL_ETHERNET_TXD_2); + write_padframe_mux(PADFRAME_CONFIG_MUXED_H_00_MUX_SEL, PADFRAME_MUXED_H_00_SEL_ETHERNET_TXD_3); + write_padframe_mux(PADFRAME_CONFIG_MUXED_H_01_MUX_SEL, PADFRAME_MUXED_H_01_SEL_ETHERNET_MD); + write_padframe_mux(PADFRAME_CONFIG_MUXED_H_02_MUX_SEL, PADFRAME_MUXED_H_02_SEL_ETHERNET_MDC); + write_padframe_mux(PADFRAME_CONFIG_MUXED_H_03_MUX_SEL, PADFRAME_MUXED_H_03_SEL_ETHERNET_RST_N); + // Configuring padframe - pullup + write_padframe_pen(PADFRAME_CONFIG_MUXED_V_07_CFG, 0x1); write_padframe_psel(PADFRAME_CONFIG_MUXED_V_07_CFG, 0x1); + write_padframe_pen(PADFRAME_CONFIG_MUXED_V_08_CFG, 0x1); write_padframe_psel(PADFRAME_CONFIG_MUXED_V_08_CFG, 0x1); + write_padframe_pen(PADFRAME_CONFIG_MUXED_V_09_CFG, 0x1); write_padframe_psel(PADFRAME_CONFIG_MUXED_V_09_CFG, 0x1); + write_padframe_pen(PADFRAME_CONFIG_MUXED_V_10_CFG, 0x1); write_padframe_psel(PADFRAME_CONFIG_MUXED_V_10_CFG, 0x1); + write_padframe_pen(PADFRAME_CONFIG_MUXED_V_11_CFG, 0x1); write_padframe_psel(PADFRAME_CONFIG_MUXED_V_11_CFG, 0x1); + write_padframe_pen(PADFRAME_CONFIG_MUXED_V_12_CFG, 0x1); write_padframe_psel(PADFRAME_CONFIG_MUXED_V_12_CFG, 0x1); + write_padframe_pen(PADFRAME_CONFIG_MUXED_V_13_CFG, 0x1); write_padframe_psel(PADFRAME_CONFIG_MUXED_V_13_CFG, 0x1); + write_padframe_pen(PADFRAME_CONFIG_MUXED_V_14_CFG, 0x1); write_padframe_psel(PADFRAME_CONFIG_MUXED_V_14_CFG, 0x1); + write_padframe_pen(PADFRAME_CONFIG_MUXED_V_15_CFG, 0x1); write_padframe_psel(PADFRAME_CONFIG_MUXED_V_15_CFG, 0x1); + write_padframe_pen(PADFRAME_CONFIG_MUXED_V_16_CFG, 0x1); write_padframe_psel(PADFRAME_CONFIG_MUXED_V_16_CFG, 0x1); + write_padframe_pen(PADFRAME_CONFIG_MUXED_V_17_CFG, 0x1); write_padframe_psel(PADFRAME_CONFIG_MUXED_V_17_CFG, 0x1); + write_padframe_pen(PADFRAME_CONFIG_MUXED_H_00_CFG, 0x1); write_padframe_psel(PADFRAME_CONFIG_MUXED_H_00_CFG, 0x1); + write_padframe_pen(PADFRAME_CONFIG_MUXED_H_01_CFG, 0x1); write_padframe_psel(PADFRAME_CONFIG_MUXED_H_01_CFG, 0x1); + write_padframe_pen(PADFRAME_CONFIG_MUXED_H_02_CFG, 0x1); write_padframe_psel(PADFRAME_CONFIG_MUXED_H_02_CFG, 0x1); + write_padframe_pen(PADFRAME_CONFIG_MUXED_H_03_CFG, 0x1); write_padframe_psel(PADFRAME_CONFIG_MUXED_H_03_CFG, 0x1); +} + +#endif /*__PADFRAME_H*/ diff --git a/sw/tests/bare-metal/hostd/ethernet.c b/sw/tests/bare-metal/hostd/ethernet.c index 867abc49..504e9cd3 100644 --- a/sw/tests/bare-metal/hostd/ethernet.c +++ b/sw/tests/bare-metal/hostd/ethernet.c @@ -56,43 +56,11 @@ int main(void) { // Put SMP Hart to sleep if (hart_id() != 0) wfi(); - // Configuring padframe - mux - write_padframe_mux(PADFRAME_CONFIG_MUXED_V_07_MUX_SEL, PADFRAME_MUXED_V_07_SEL_ETHERNET_RXCK); - write_padframe_mux(PADFRAME_CONFIG_MUXED_V_08_MUX_SEL, PADFRAME_MUXED_V_08_SEL_ETHERNET_RXCTL); - write_padframe_mux(PADFRAME_CONFIG_MUXED_V_09_MUX_SEL, PADFRAME_MUXED_V_09_SEL_ETHERNET_RXD_0); - write_padframe_mux(PADFRAME_CONFIG_MUXED_V_10_MUX_SEL, PADFRAME_MUXED_V_10_SEL_ETHERNET_RXD_1); - write_padframe_mux(PADFRAME_CONFIG_MUXED_V_11_MUX_SEL, PADFRAME_MUXED_V_11_SEL_ETHERNET_RXD_2); - write_padframe_mux(PADFRAME_CONFIG_MUXED_V_12_MUX_SEL, PADFRAME_MUXED_V_12_SEL_ETHERNET_RXD_3); - write_padframe_mux(PADFRAME_CONFIG_MUXED_V_13_MUX_SEL, PADFRAME_MUXED_V_13_SEL_ETHERNET_TXCK); - write_padframe_mux(PADFRAME_CONFIG_MUXED_V_14_MUX_SEL, PADFRAME_MUXED_V_14_SEL_ETHERNET_TXCTL); - write_padframe_mux(PADFRAME_CONFIG_MUXED_V_15_MUX_SEL, PADFRAME_MUXED_V_15_SEL_ETHERNET_TXD_0); - write_padframe_mux(PADFRAME_CONFIG_MUXED_V_16_MUX_SEL, PADFRAME_MUXED_V_16_SEL_ETHERNET_TXD_1); - write_padframe_mux(PADFRAME_CONFIG_MUXED_V_17_MUX_SEL, PADFRAME_MUXED_V_17_SEL_ETHERNET_TXD_2); - write_padframe_mux(PADFRAME_CONFIG_MUXED_H_00_MUX_SEL, PADFRAME_MUXED_H_00_SEL_ETHERNET_TXD_3); - write_padframe_mux(PADFRAME_CONFIG_MUXED_H_01_MUX_SEL, PADFRAME_MUXED_H_01_SEL_ETHERNET_MD); - write_padframe_mux(PADFRAME_CONFIG_MUXED_H_02_MUX_SEL, PADFRAME_MUXED_H_02_SEL_ETHERNET_MDC); - write_padframe_mux(PADFRAME_CONFIG_MUXED_H_03_MUX_SEL, PADFRAME_MUXED_H_03_SEL_ETHERNET_RST_N); - // Configuring padframe - pullup - write_padframe_pen(PADFRAME_CONFIG_MUXED_V_07_CFG, 0x1); write_padframe_psel(PADFRAME_CONFIG_MUXED_V_07_CFG, 0x1); - write_padframe_pen(PADFRAME_CONFIG_MUXED_V_08_CFG, 0x1); write_padframe_psel(PADFRAME_CONFIG_MUXED_V_08_CFG, 0x1); - write_padframe_pen(PADFRAME_CONFIG_MUXED_V_09_CFG, 0x1); write_padframe_psel(PADFRAME_CONFIG_MUXED_V_09_CFG, 0x1); - write_padframe_pen(PADFRAME_CONFIG_MUXED_V_10_CFG, 0x1); write_padframe_psel(PADFRAME_CONFIG_MUXED_V_10_CFG, 0x1); - write_padframe_pen(PADFRAME_CONFIG_MUXED_V_11_CFG, 0x1); write_padframe_psel(PADFRAME_CONFIG_MUXED_V_11_CFG, 0x1); - write_padframe_pen(PADFRAME_CONFIG_MUXED_V_12_CFG, 0x1); write_padframe_psel(PADFRAME_CONFIG_MUXED_V_12_CFG, 0x1); - write_padframe_pen(PADFRAME_CONFIG_MUXED_V_13_CFG, 0x1); write_padframe_psel(PADFRAME_CONFIG_MUXED_V_13_CFG, 0x1); - write_padframe_pen(PADFRAME_CONFIG_MUXED_V_14_CFG, 0x1); write_padframe_psel(PADFRAME_CONFIG_MUXED_V_14_CFG, 0x1); - write_padframe_pen(PADFRAME_CONFIG_MUXED_V_15_CFG, 0x1); write_padframe_psel(PADFRAME_CONFIG_MUXED_V_15_CFG, 0x1); - write_padframe_pen(PADFRAME_CONFIG_MUXED_V_16_CFG, 0x1); write_padframe_psel(PADFRAME_CONFIG_MUXED_V_16_CFG, 0x1); - write_padframe_pen(PADFRAME_CONFIG_MUXED_V_17_CFG, 0x1); write_padframe_psel(PADFRAME_CONFIG_MUXED_V_17_CFG, 0x1); - write_padframe_pen(PADFRAME_CONFIG_MUXED_H_00_CFG, 0x1); write_padframe_psel(PADFRAME_CONFIG_MUXED_H_00_CFG, 0x1); - write_padframe_pen(PADFRAME_CONFIG_MUXED_H_01_CFG, 0x1); write_padframe_psel(PADFRAME_CONFIG_MUXED_H_01_CFG, 0x1); - write_padframe_pen(PADFRAME_CONFIG_MUXED_H_02_CFG, 0x1); write_padframe_psel(PADFRAME_CONFIG_MUXED_H_02_CFG, 0x1); - write_padframe_pen(PADFRAME_CONFIG_MUXED_H_03_CFG, 0x1); write_padframe_psel(PADFRAME_CONFIG_MUXED_H_03_CFG, 0x1); - - // Configuring FLL - fll_normal(FLL_PERIPH_ID); - set_fll_clk_mul(0x3E7, FLL_PERIPH_ID); - set_fll_clk_div(0x2, FLL_PERIPH_ID); + // Configure padframe for ethernet use. + padframe_ethernet_cfg(); + + // Setup the peripheral FLL. + set_periph_fll(); // Wait for FLL clk out to stabilize for (int i = 0; i < FLL_WAIT_CYCLES; i++)