Running on FLEX devices

[Rasta8889]

First of all: Thank you for maintaining this project.

I used a Terasic Development board in first semester but didn't learn Verilog or Altera HDL. Some minor VHDL knowledge is there, but it's not really enough for such a project.

Is there a easy way to convert the project to run on a Altera FLEX 10K20 FPGA, mounted on a UP1 Development Board? I know, Hashrate will be poor.

best regards,

Sascha

[progranism]

Hello Sascha,

Is there a easy way to convert the project to run on a Altera FLEX 10K20
FPGA, mounted on a UP1 Development Board? I know, Hashrate will be poor.
Looking at the specs for the 10K20, it is a very limited device. I don't
think anything but a serial hasher would fit into it, and there isn't
really a good serial hasher implementation in my repo yet.

If it were possible, you would want to base it off this project variant:

https://github.com/progranism/Open-Source-FPGA-Bitcoin-Miner/tree/master/projects/DE2_115_makomk_mod

That code supports having a short hashing pipeline, so it can fit onto
smaller chips. Unfortunately the FLEX devices require an older version of
Quartus (9.0), so I was not able to put together an example project for
you. The general idea is to set the correct device in the project for your
FLEX chip (Assignments->Device), set the correct clock pin
(Assignments->Assignment Editor), and possibly adjust the PLL (main_pll.v).

~William

On Tue, Jan 31, 2012 at 6:26 AM, Rasta8889 <
[email protected]

wrote:

First of all: Thank you for maintaining this project.

I used a Terasic Development board in first semester but didn't learn
Verilog or Altera HDL. Some minor VHDL knowledge is there, but it's not
really enough for such a project.

Is there a easy way to convert the project to run on a Altera FLEX 10K20
FPGA, mounted on a UP1 Development Board? I know, Hashrate will be poor.

best regards,

Sascha

---

Reply to this email directly or view it on GitHub:
#10

[Rasta8889]

Thanks for your answer.

I figured the steps out myself so far (Change device, adjust PLL). I think I also started my own project using the makomk_mod you mentioned. But only by chance ^^

Quartus 9.0 can be found here: ftp://ftp.altera.com/outgoing/release/ although i don't want to force you to download and install it - it's quite time-consuming.

I have some problems setting up the PLL. The frequency speed-up ratio in your project is 5, am I right? The Flex10K series only supports a double speed-up. Will that work?

Also, I can't seem to manage to use the MegaWizard Plugin Manager to include the CLKLOCK megafunction, it doesn't get displayed. ALTCLKLOCK or ALTPLL are not supported by FLEX10k devices.

Seems like I have to learn some VHDL. Fortunately, VHDL is also part of a exam I have in March, so the knowledge won't go to waste ;)

best regards,

Sascha