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vhdlrng.ldf
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vhdlrng.ldf
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<?xml version="1.0" encoding="UTF-8"?>
<BaliProject version="2.0" title="vhdlrng" device="LCMXO2-7000HE-4TG144C" synthesis="synplify" default_implementation="vhdlrng">
<Options/>
<Implementation title="vhdlrng" dir="vhdlrng" description="vhdlrng" default_strategy="Strategy1">
<Options def_top="blinking_led"/>
<Source name="vhdlrng/source/blinking_led.vhd" type="VHDL" type_short="VHDL">
<Options top_module="blinking_led"/>
</Source>
<Source name="vhdlrng/source/firo_closed.vhd" type="VHDL" type_short="VHDL">
<Options/>
</Source>
<Source name="vhdlrng/source/firo_open.vhd" type="VHDL" type_short="VHDL">
<Options/>
</Source>
<Source name="vhdlrng/source/vhdlrng.vhd" type="VHDL" type_short="VHDL">
<Options/>
</Source>
<Source name="vhdlrng/source/lut4_inverter.vhd" type="VHDL" type_short="VHDL">
<Options/>
</Source>
<Source name="vhdlrng.lpf" type="Logic Preference" type_short="LPF">
<Options/>
</Source>
<Source name="vhdlrng/vhdlrng.xcf" type="Programming Project File" type_short="Programming">
<Options/>
</Source>
</Implementation>
<Strategy name="Strategy1" file="vhdlrng1.sty"/>
</BaliProject>