Need PcieEndpointController.bsv
to follow the PCIe spec around PERST
#226
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PcieEndpointController.bsv
to follow the PCIe spec around PERST
#226
Right now the
PcieEndpointController
block is used to proxy PERST# from a server to the Tofino 2. That block should honor the various timings around PERST# defined by the PCIe spec:Tpvperl
- PERST# must remain active at least this long after power becomes validTperst
- When asserted, PERST# must remain asserted at least this longTfail
- When power becomes invalid, PERST# must be asserted within this timeTperst-clk
- PERST# must remain active at least this long after any supplied reference clock isstable
There is a discussion of this in RFD 123. Right now we don't have any software controls around enforcing this behavior, things are working just due to the nature of boot. We can enforce the right behavior in the FPGA, so we should. The CEM spec is the worst case scenario around PERST#, so we should implement to that.
Tpvperl
- 100 ms (min)Tperst
- 100 us (min)Tfail
- 500 ns (max)Tperst-clk
- 100 us (min)The text was updated successfully, but these errors were encountered: