FPGA: i2c/3c controller

[rmustacc]

This implements support for the i2c and i3c basic controller logic that will be required for the DRAM proxy and related access. These are blocks that provide the SP access as an initiator.

[Aaron-Hartwig]

Thanks to @nathanaelhuffman we have a capture of IxC DDR5 things from Ruby: https://drive.google.com/file/d/1A_qxI4eRBv3MXRqyqjgfUS8hg8s13Sgo/view?usp=drive_link

[Aaron-Hartwig]

I have some stream of consciousness notes here, but I figured a summary is warranted at this point.

The system we have been doing investigation on is an AMD Ruby with a DDR5 DIMM at A1 and G1. The capture above is on that GHIJKL DIMM1 bus. The main takeaways are:

• We can see the SP5 attempt to talk to all six potential DDR5 channels, with the communication to G1 being successful (HID b000).
• All comms are happening at 100KHz
• We do not observe any attempt to move from I2C to I3C Basic. i.e., no 7'h7E address broadcasts with CCCs.
• We can see communications with the SPD/Hub, PMIC, and RCD.
• • While in I2C mode, the Hub can page in the SPD contents in the upper 128-bytes it exposes in its own memory map.

All this was running a ?? version of firmware that is definitely out of date. We should do another analysis with the latest bits we have access to.

[Aaron-Hartwig]

Nathanael uploaded a capture from turin 1.0.0.1 here. Still appears to be completely I2C.