-
Notifications
You must be signed in to change notification settings - Fork 3
Home
taoli4rs edited this page Nov 5, 2022
·
3 revisions
Welcome to the Backend wiki!
FPGA backend is composed by below stages:
- Packing: Cluster tech-mapped synthesized design and pack them into atoms supplied by the target device.
- Placement: Follow target device's floor-planning and place blocks on int.
- Routing: Route wires and connect the netlist.
- Timing analysis: Apply static timing analysis, check and report timing violations.
- Bitstream generation: Generate configure bits for all configurable blocks to realize the netlist.