{"payload":{"pageCount":1,"repositories":[{"type":"Public","name":"rapcores.github.io","owner":"RAPcores","isFork":false,"description":"RAPcores website","allTopics":[],"primaryLanguage":{"name":"Nix","color":"#7e7eff"},"pullRequestCount":0,"issueCount":1,"starsCount":0,"forksCount":0,"license":null,"participation":null,"lastUpdated":{"hasBeenPushedTo":true,"timestamp":"2023-08-27T03:17:05.630Z"}},{"type":"Public","name":"rapcores","owner":"RAPcores","isFork":false,"description":"Robotic Application Processor","allTopics":["fpga","robotics","verilog","cnc","3d-printing","motors"],"primaryLanguage":{"name":"Verilog","color":"#b2b7f8"},"pullRequestCount":7,"issueCount":21,"starsCount":24,"forksCount":6,"license":"ISC License","participation":null,"lastUpdated":{"hasBeenPushedTo":true,"timestamp":"2022-01-02T03:54:53.823Z"}},{"type":"Public","name":"nix-rapcores-support","owner":"RAPcores","isFork":false,"description":"Nix packages to support RAPcores development","allTopics":[],"primaryLanguage":{"name":"Nix","color":"#7e7eff"},"pullRequestCount":0,"issueCount":0,"starsCount":0,"forksCount":0,"license":null,"participation":null,"lastUpdated":{"hasBeenPushedTo":true,"timestamp":"2021-07-25T22:56:19.574Z"}},{"type":"Public","name":"common_cells","owner":"RAPcores","isFork":true,"description":"Common SystemVerilog components","allTopics":[],"primaryLanguage":{"name":"SystemVerilog","color":"#DAE1C2"},"pullRequestCount":0,"issueCount":0,"starsCount":0,"forksCount":138,"license":"Other","participation":null,"lastUpdated":{"hasBeenPushedTo":true,"timestamp":"2021-06-14T10:11:39.599Z"}},{"type":"Public","name":"fpga-hal","owner":"RAPcores","isFork":false,"description":"Experimental Verilog FPGA HAL","allTopics":[],"primaryLanguage":{"name":"Verilog","color":"#b2b7f8"},"pullRequestCount":0,"issueCount":0,"starsCount":0,"forksCount":0,"license":null,"participation":null,"lastUpdated":{"hasBeenPushedTo":true,"timestamp":"2021-04-26T02:27:25.024Z"}},{"type":"Public","name":"rapcores-idx","owner":"RAPcores","isFork":false,"description":"Interactive Development environment","allTopics":[],"primaryLanguage":{"name":"Jupyter Notebook","color":"#DA5B0B"},"pullRequestCount":0,"issueCount":0,"starsCount":0,"forksCount":0,"license":null,"participation":null,"lastUpdated":{"hasBeenPushedTo":true,"timestamp":"2021-03-22T23:42:42.086Z"}},{"type":"Public","name":"JupyterNotebooks","owner":"RAPcores","isFork":false,"description":"Jupyter Notebooks for analysis","allTopics":[],"primaryLanguage":{"name":"Jupyter Notebook","color":"#DA5B0B"},"pullRequestCount":0,"issueCount":0,"starsCount":0,"forksCount":0,"license":"MIT License","participation":null,"lastUpdated":{"hasBeenPushedTo":true,"timestamp":"2021-03-22T17:18:08.721Z"}},{"type":"Public","name":"foc-fixture","owner":"RAPcores","isFork":false,"description":"Fixtures for hands-on Field Oriented Control development","allTopics":[],"primaryLanguage":{"name":"nesC","color":"#94B0C7"},"pullRequestCount":0,"issueCount":0,"starsCount":0,"forksCount":0,"license":null,"participation":null,"lastUpdated":{"hasBeenPushedTo":true,"timestamp":"2021-02-05T00:31:07.268Z"}},{"type":"Public","name":"caravel_rapcores","owner":"RAPcores","isFork":false,"description":"rapcore ASIC prototype on the openmpw/caravel shuttle ","allTopics":["caravel-shuttle"],"primaryLanguage":{"name":"Verilog","color":"#b2b7f8"},"pullRequestCount":4,"issueCount":0,"starsCount":2,"forksCount":0,"license":"Apache License 2.0","participation":null,"lastUpdated":{"hasBeenPushedTo":true,"timestamp":"2020-12-23T19:44:29.256Z"}},{"type":"Public","name":"openlane","owner":"RAPcores","isFork":true,"description":"OpenLANE is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen, Fault and custom methodology scripts for design exploration and optimization.","allTopics":[],"primaryLanguage":{"name":"Verilog","color":"#b2b7f8"},"pullRequestCount":0,"issueCount":0,"starsCount":0,"forksCount":369,"license":"Apache License 2.0","participation":null,"lastUpdated":{"hasBeenPushedTo":true,"timestamp":"2020-11-30T19:08:06.303Z"}},{"type":"Public","name":"open_pdks","owner":"RAPcores","isFork":true,"description":"PDK installer for open-source EDA tools and toolchains. Distributed with a setup for the Google/SkyWater 130nm process.","allTopics":[],"primaryLanguage":{"name":"Python","color":"#3572A5"},"pullRequestCount":0,"issueCount":0,"starsCount":0,"forksCount":85,"license":"Apache License 2.0","participation":null,"lastUpdated":{"hasBeenPushedTo":true,"timestamp":"2020-11-30T18:50:48.966Z"}},{"type":"Public","name":"caravel","owner":"RAPcores","isFork":true,"description":"","allTopics":[],"primaryLanguage":{"name":"Verilog","color":"#b2b7f8"},"pullRequestCount":0,"issueCount":1,"starsCount":0,"forksCount":136,"license":"Apache License 2.0","participation":null,"lastUpdated":{"hasBeenPushedTo":true,"timestamp":"2020-11-26T04:19:45.161Z"}},{"type":"Public","name":"spi-flash-programmer","owner":"RAPcores","isFork":true,"description":"","allTopics":[],"primaryLanguage":{"name":"C++","color":"#f34b7d"},"pullRequestCount":0,"issueCount":0,"starsCount":0,"forksCount":1,"license":"Creative Commons Zero v1.0 Universal","participation":null,"lastUpdated":{"hasBeenPushedTo":true,"timestamp":"2020-08-12T17:53:33.232Z"}}],"repositoryCount":13,"userInfo":null,"searchable":true,"definitions":[],"typeFilters":[{"id":"all","text":"All"},{"id":"public","text":"Public"},{"id":"source","text":"Sources"},{"id":"fork","text":"Forks"},{"id":"archived","text":"Archived"},{"id":"template","text":"Templates"}],"compactMode":false},"title":"RAPcores repositories"}