Performance Monitoring of the Processor Core

[mashahedurrahman]

Hi, does CVA6 have any PMU (Performance Monitoring Unit) with the processor core? I need to have some performance data like the percentage of non-idling CPU clock cycles, number of executed instructions per cycle, number of L1 data cache accesses and the miss rate, and CPU (Write/Read) stall cycles per instruction.

[Moschn]

CVA6 supports a number of performance counters: https://github.com/openhwgroup/cva6/blob/master/core/csr_regfile.sv#L566-L600. For example, minstret returns the number of retired instructions, mcycle the number of cycles, and ml1_icache_miss the number of cache misses. Note that minstret and mcycle are standard names. In contrast, the other performance counters typically have a generic name and most software refers to them using the generic name, i.e., MHPM_COUNTER_3 is the generic name for ml1_icache_miss. For more information see Table 2.6 in the RISC-V privilege spec.

[mashahedurrahman]

Thank you so much @Moschn