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Arm64: Float32 support #3707

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Merged
merged 4 commits into from
Mar 20, 2025
Merged

Arm64: Float32 support #3707

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6883d5b
arm64 float32 regs
gretay-js Mar 18, 2025
fd2c095
arm64 float32 emit
gretay-js Mar 18, 2025
c2d3de7
remove unused rotate_registers
gretay-js Mar 20, 2025
edcb49f
Generalize [hard_float_reg_gen] to cover int_hard_reg
gretay-js Mar 20, 2025
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4 changes: 0 additions & 4 deletions backend/amd64/proc.ml
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Original file line number Diff line number Diff line change
Expand Up @@ -140,10 +140,6 @@ let register_name ty r =
| Float | Float32 | Vec128 | Valx2 ->
float_reg_name.(r - first_available_register.(1))

(* Pack registers starting at %rax so as to reduce the number of REX
prefixes and thus improve code density *)
let rotate_registers = false

(* Representation of hard registers by pseudo-registers *)

let hard_int_reg =
Expand Down
3 changes: 2 additions & 1 deletion backend/arm64/cfg_selection.ml
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Expand Up @@ -159,8 +159,9 @@ class selector =
| [Cop (Cmulf Float64, args, _); arg] ->
specific Inegmulsubf, arg :: args
| _ -> super#select_operation op args dbg ~label_after)
| Cpackf32 -> specific (Isimd Zip1_f32), args
(* Recognize floating-point square root *)
| Cextcall { func = "sqrt" } -> specific Isqrtf, args
| Cextcall { func = "sqrt" | "sqrtf" } -> specific Isqrtf, args
| Cextcall { func; builtin = true; _ } -> (
match Simd_selection.select_operation_cfg func args with
| Some (op, args) -> Basic (Op op), args
Expand Down
88 changes: 43 additions & 45 deletions backend/arm64/emit.mlp
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Expand Up @@ -317,6 +317,11 @@ let is_immediate_float bits =
let mant = Int64.logand bits 0xF_FFFF_FFFF_FFFFL in
exp >= -3 && exp <= 4 && Int64.logand mant 0xF_0000_0000_0000L = mant

let is_immediate_float32 bits =
let exp = (Int32.(to_int (shift_right_logical bits 23)) land 0x7F) - 63 in
let mant = Int32.logand bits 0x7F_FFFFl in
exp >= -3 && exp <= 4 && Int32.logand mant 0x78_0000l = mant

(* Adjust sp (up or down) by the given byte amount *)

let emit_stack_adjustment n =
Expand Down Expand Up @@ -703,9 +708,7 @@ module BR = Branch_relaxation.Make (struct
| Lop (Move | Spill | Reload) -> 1
| Lop (Const_int n) ->
num_instructions_for_intconst n
| Lop (Const_float32 _) ->
(* CR mslater: (float32) arm64 *)
Misc.fatal_error "float32 is not supported on this architecture"
| Lop (Const_float32 _) -> 2
| Lop (Const_float _) -> 2
| Lop (Const_symbol _) -> 2
| Lop (Const_vec128 _) ->
Expand Down Expand Up @@ -755,22 +758,19 @@ module BR = Branch_relaxation.Make (struct
| Lop (Begin_region | End_region) -> 1
| Lop (Intop (Icomp _)) -> 2
| Lop (Floatop (Float64, Icompf _)) -> 2
| Lop (Floatop (Float32, Icompf _)) ->
(* CR mslater: (float32) arm64 *)
Misc.fatal_error "float32 is not supported on this architecture"
| Lop (Floatop (Float32, Icompf _)) -> 2
| Lop (Intop_imm (Icomp _, _)) -> 2
| Lop (Intop Imod) -> 2
| Lop (Intop (Imulh _)) -> 1
| Lop (Intop (Iclz _)) -> 1
| Lop (Intop (Ictz _)) -> 2
| Lop (Floatop (Float64, (Iabsf | Inegf)) | Specific Isqrtf) -> 1
| Lop (Floatop (Float32, (Iabsf | Inegf))) ->
(* CR mslater: (float32) arm64 *)
Misc.fatal_error "float32 is not supported on this architecture"
| Lop (Intop (Iadd|Isub|Imul|Idiv|Iand|Ior|Ixor|Ilsl|Ilsr|Iasr|Ipopcnt)) -> 1
| Lop (Intop_imm
((Iadd|Isub|Imul|Idiv|Imod|Imulh _|Iand|Ior|Ixor|Ilsl|Ilsr|Iasr
| Iclz _ | Ictz _ |Ipopcnt),_)) -> 1
| Lop (Floatop (Float64, (Iabsf | Inegf))) -> 1
| Lop (Floatop (Float32, (Iabsf | Inegf))) -> 1
| Lop (Specific Isqrtf) -> 1
| Lop (Reinterpret_cast (Value_of_int | Int_of_value |
Float_of_int64 | Int64_of_float)) -> 1
| Lop (Reinterpret_cast (Float32_of_float | Float_of_float32 |
Expand All @@ -788,10 +788,9 @@ module BR = Branch_relaxation.Make (struct
| Lop (Static_cast (V128_of_scalar _ | Scalar_of_v128 _)) ->
(* CR mslater: (SIMD) arm64 *)
Misc.fatal_error "SIMD is not supported on this architecture"
| Lop (Floatop (Float64, (Iaddf | Isubf | Imulf | Idivf)) | Specific Inegmulf) -> 1
| Lop (Floatop (Float32, (Iaddf | Isubf | Imulf | Idivf))) ->
(* CR mslater: (float32) arm64 *)
Misc.fatal_error "float32 is not supported on this architecture"
| Lop (Floatop (Float64, (Iaddf | Isubf | Imulf | Idivf))) -> 1
| Lop (Floatop (Float32, (Iaddf | Isubf | Imulf | Idivf))) -> 1
| Lop (Specific Inegmulf) -> 1
| Lop (Opaque) -> 0
| Lop (Specific (Imuladdf | Inegmuladdf | Imulsubf | Inegmulsubf)) -> 1
| Lop (Specific (Ishiftarith _)) -> 1
Expand Down Expand Up @@ -1030,7 +1029,7 @@ let emit_instr i =
move i.arg.(0) i.res.(0)
| Lop(Specific Imove32) ->
let src = i.arg.(0) and dst = i.res.(0) in
if src.loc <> dst.loc then begin
if not (Reg.same_loc src dst) then begin
match (src, dst) with
| {loc = Reg _}, {loc = Reg _} ->
` mov {emit_wreg dst}, {emit_wreg src}\n`
Expand All @@ -1045,9 +1044,17 @@ let emit_instr i =
end
| Lop(Const_int n) ->
emit_intconst i.res.(0) n
| Lop (Const_float32 _) ->
(* CR mslater: (float32) arm64 *)
Misc.fatal_error "float32 is not supported on this architecture"
| Lop (Const_float32 f) ->
DSL.check_reg Float32 i.res.(0);
if f = 0l then
` fmov {emit_reg i.res.(0)}, wzr\n`
else if is_immediate_float32 f then
` fmov {emit_reg i.res.(0)}, #{emit_printf "%.7f" (Int32.float_of_bits f)}\n`
else begin
(* float32 constants still take up 8 bytes; we load the lower half. *)
let lbl = float_literal (Int64.of_int32 f) in
emit_load_literal i.res.(0) lbl
end
| Lop(Const_float f) ->
if f = 0L then
` fmov {emit_reg i.res.(0)}, xzr\n`
Expand Down Expand Up @@ -1134,6 +1141,7 @@ let emit_instr i =
| Thirtytwo_signed ->
` ldrsw {emit_reg dst}, {emit_addressing addressing_mode base}\n`
| Single { reg = Float64 } ->
DSL.check_reg Float dst;
` ldr s7, {emit_addressing addressing_mode base}\n`;
` fcvt {emit_reg dst}, s7\n`
| Word_int | Word_val ->
Expand All @@ -1146,8 +1154,8 @@ let emit_instr i =
| Double ->
` ldr {emit_reg dst}, {emit_addressing addressing_mode base}\n`
| Single { reg = Float32 } ->
(* CR mslater: (float32) arm64 *)
fatal_error "arm64: got float32 memory chunk"
DSL.check_reg Float32 dst;
` ldr {emit_reg dst}, {emit_addressing addressing_mode base}\n`
| Onetwentyeight_aligned | Onetwentyeight_unaligned ->
(* CR mslater: (SIMD) arm64 *)
fatal_error "arm64: got 128 bit memory chunk"
Expand All @@ -1171,6 +1179,7 @@ let emit_instr i =
| Thirtytwo_unsigned | Thirtytwo_signed ->
` str {emit_wreg src}, {emit_addressing addr base}\n`
| Single { reg = Float64 } ->
DSL.check_reg Float src;
` fcvt s7, {emit_reg src}\n`;
` str s7, {emit_addressing addr base}\n`;
| Word_int | Word_val ->
Expand All @@ -1180,8 +1189,8 @@ let emit_instr i =
| Double ->
` str {emit_reg src}, {emit_addressing addr base}\n`
| Single { reg = Float32 } ->
(* CR mslater: (float32) arm64 *)
fatal_error "arm64: got float32 memory chunk"
DSL.check_reg Float32 src;
` str {emit_reg src}, {emit_addressing addr base}\n`
| Onetwentyeight_aligned | Onetwentyeight_unaligned ->
(* CR mslater: (SIMD) arm64 *)
fatal_error "arm64: got 128 bit memory chunk"
Expand Down Expand Up @@ -1213,9 +1222,10 @@ let emit_instr i =
let comp = name_for_float_comparison cmp in
` fcmp {emit_reg i.arg.(0)}, {emit_reg i.arg.(1)}\n`;
` cset {emit_reg i.res.(0)}, {emit_string comp}\n`
| Lop(Floatop(Float32, Icompf _)) ->
(* CR mslater: (float32) arm64 *)
Misc.fatal_error "float32 is not supported on this architecture"
| Lop(Floatop(Float32, Icompf cmp)) ->
let comp = name_for_float_comparison cmp in
` fcmp {emit_reg i.arg.(0)}, {emit_reg i.arg.(1)}\n`;
` cset {emit_reg i.res.(0)}, {emit_string comp}\n`
| Lop(Intop_imm(Icomp cmp, n)) ->
emit_cmpimm i.arg.(0) n;
` cset {emit_reg i.res.(0)}, {emit_string (name_for_comparison cmp)}\n`
Expand All @@ -1240,25 +1250,19 @@ let emit_instr i =
| Lop(Intop_imm(op, n)) ->
let instr = name_for_int_operation op in
` {emit_string instr} {emit_reg i.res.(0)}, {emit_reg i.arg.(0)}, #{emit_int n}\n`
| Lop(Floatop (Float32, (Iabsf | Inegf))) ->
(* CR mslater: (float32) arm64 *)
Misc.fatal_error "float32 is not supported on this architecture"
| Lop(Floatop (Float32, (Iaddf | Isubf | Imulf | Idivf))) ->
(* CR mslater: (float32) arm64 *)
Misc.fatal_error "float32 is not supported on this architecture"
| Lop(Specific Isqrtf) ->
` fsqrt {emit_reg i.res.(0)}, {emit_reg i.arg.(0)}\n`
| Lop(Floatop ((Float64), Iabsf)) ->
| Lop(Floatop ((Float32 | Float64), Iabsf)) ->
` fabs {emit_reg i.res.(0)}, {emit_reg i.arg.(0)}\n`
| Lop(Floatop ((Float64), Inegf)) ->
| Lop(Floatop ((Float32 | Float64), Inegf)) ->
` fneg {emit_reg i.res.(0)}, {emit_reg i.arg.(0)}\n`
| Lop(Floatop ((Float64), Iaddf)) ->
| Lop(Floatop ((Float32 | Float64), Iaddf)) ->
` fadd {emit_reg i.res.(0)}, {emit_reg i.arg.(0)}, {emit_reg i.arg.(1)}\n`
| Lop(Floatop ((Float64), Isubf)) ->
| Lop(Floatop ((Float32 | Float64), Isubf)) ->
` fsub {emit_reg i.res.(0)}, {emit_reg i.arg.(0)}, {emit_reg i.arg.(1)}\n`
| Lop(Floatop ((Float64), Imulf)) ->
| Lop(Floatop ((Float32 | Float64), Imulf)) ->
` fmul {emit_reg i.res.(0)}, {emit_reg i.arg.(0)}, {emit_reg i.arg.(1)}\n`
| Lop(Floatop ((Float64), Idivf)) ->
| Lop(Floatop ((Float32 | Float64), Idivf)) ->
` fdiv {emit_reg i.res.(0)}, {emit_reg i.arg.(0)}, {emit_reg i.arg.(1)}\n`
| Lop(Specific Inegmulf) ->
` fnmul {emit_reg i.res.(0)}, {emit_reg i.arg.(0)}, {emit_reg i.arg.(1)}\n`
Expand Down Expand Up @@ -1341,10 +1345,7 @@ let emit_instr i =
let comp = name_for_comparison cmp in
emit_cmpimm i.arg.(0) n;
` csel {emit_reg i.res.(0)}, {emit_reg i.arg.(1)}, {emit_reg i.arg.(2)}, {emit_string comp}\n`
| Ifloattest (Float32, _cmp) ->
(* CR mslater: (float32) arm64 *)
Misc.fatal_error "float32 is not supported on this architecture"
| Ifloattest (Float64, cmp) ->
| Ifloattest ((Float32 | Float64), cmp) ->
let comp = name_for_float_comparison cmp in
` fcmp {emit_reg i.arg.(0)}, {emit_reg i.arg.(1)}\n`;
` csel {emit_reg i.res.(0)}, {emit_reg i.arg.(2)}, {emit_reg i.arg.(3)}, {emit_string comp}\n`
Expand Down Expand Up @@ -1377,10 +1378,7 @@ let emit_instr i =
emit_cmpimm i.arg.(0) n;
let comp = name_for_comparison cmp in
` b.{emit_string comp} {emit_label lbl}\n`
| Ifloattest (Float32, _cmp) ->
(* CR mslater: (float32) arm64 *)
Misc.fatal_error "float32 is not supported on this architecture"
| Ifloattest (Float64, cmp) ->
| Ifloattest ((Float32 | Float64), cmp) ->
let comp = name_for_float_comparison cmp in
` fcmp {emit_reg i.arg.(0)}, {emit_reg i.arg.(1)}\n`;
` b.{emit_string comp} {emit_label lbl}\n`
Expand Down
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