Minor documentation updates

- Renamed behavioral_adder source files
- Updated READMEs for Project 4

Author: nxbyte

Project 4 - 64-Bit Adder/behavioral_adder_64/README.md

@@ -4,7 +4,7 @@
 
 This model was an abstracted implementation of a full adder written in a behavioral Verilog sense with no specific logic circuit design.
 
-This module tested: all possible combinations from 0 to 31 and, separately, two large 32-bit integers. 
+This module tested: all possible combinations from 0 to 31 and, separately, two large 32-bit integers.
 
 ## Waveforms
 
@@ -18,5 +18,5 @@ Test 2: Simulation results from the Verilog representation of this Behavioral Ad
 
 ## Source Files
 
-- **Behavioral Adder Adder Module** - behavioral_64_full_adder.v
-- **Behavioral Adder Test Bench (Test 1)** - behavioral_full_adder_test.v
+- **Behavioral Adder Adder Module** - behavioral_full_adder_64.v
+- **Behavioral Adder Test Bench** - behavioral_full_adder_test.v

Project 4 - 64-Bit Adder/behavioral_adder_64/behavioral_64_full_adder.v renamed to Project 4 - 64-Bit Adder/behavioral_adder_64/behavioral_full_adder_64.v

@@ -6,7 +6,7 @@
     Design Description: Verilog Module to implement a behavioral 64-bit adder
 */
 
-module behavioral_64_full_adder
+module behavioral_full_adder_64
 (
   input [63:0] A,
   input [63:0] B,

Project 4 - 64-Bit Adder/behavioral_adder_64/behavioral_full_adder_test.v

@@ -20,7 +20,7 @@ module behavioral_full_adder_test;
   integer count2;
 
   // Instantiate the Unit Under Test (UUT)
-  behavioral_64_full_adder uut
+  behavioral_full_adder_64 uut
   (
     .A(A),
     .B(B),

Project 4 - 64-Bit Adder/look_ahead_adder_64/README.md

@@ -6,7 +6,7 @@ This adder model was implemented using a structural gate-level implementation of
 
 Each modular circuit is capable of taking 4 bits and summing them into a two bit output.
 
-This module tested: all possible combinations from 0 to 31 and, separately, two large 32-bit integers. 
+This module tested: all possible combinations from 0 to 31 and, separately, two large 32-bit integers.
 
 ## Waveforms
 
@@ -21,4 +21,4 @@ Test 2: Simulation results from the Verilog representation of this 2-Bit Look Ah
 ## Source Files
 
 - **2-Bit Look Ahead Adder Module** - look_ahead_adder_64.v
-- **2-Bit Look Ahead Adder Test Bench (Test 1)** - look_ahead_adder_test.v
+- **2-Bit Look Ahead Adder Test Bench** - look_ahead_adder_test.v

Project 4 - 64-Bit Adder/look_ahead_adder_64/look_ahead_adder_test.v

@@ -2,7 +2,6 @@
 
 /*
     Group Members: Nikita Eisenhauer and Warren Seto
-
     Lab Name: Adder Design
     Design Description: Verilog test fixture to test the 64-bit look ahead adder
 */

Project 4 - 64-Bit Adder/ripple_adder_64/README.md

@@ -4,7 +4,7 @@
 
 This 64-bit adder was designed using a structural gate-level implementation of many full adders linked together into a ripple-carry adder design.
 
-This module tested: all possible combinations from 0 to 31 and, separately, two large 32-bit integers. 
+This module tested: all possible combinations from 0 to 31 and, separately, two large 32-bit integers.
 
 ## Waveforms
 
@@ -19,4 +19,4 @@ Test 2: Simulation results from the Verilog representation of this Ripple Carry
 ## Source Files
 
 - **Ripple Carry Adder Module** - ripple_adder_64.v
-- **Ripple Carry Adder Test Bench (Test 1)** - ripple_adder_64_test.v
+- **Ripple Carry Adder Test Bench** - ripple_adder_64_test.v

Project 4 - 64-Bit Adder/ripple_adder_64/ripple_adder_64.v

@@ -2,7 +2,6 @@
 
 /*
     Group Members: Nikita Eisenhauer and Warren Seto
-
     Lab Name: Adder Design
     Design Description: Verilog Module to implement a 64-bit ripple adder
 */

Project 4 - 64-Bit Adder/ripple_adder_64/ripple_adder_64_test.v

@@ -2,7 +2,6 @@
 
 /*
     Group Members: Nikita Eisenhauer and Warren Seto
-
     Lab Name: Adder Design
     Design Description: Verilog test fixture to test the 64-bit ripple adder
 */