nRF5340 wrong GPIO mapping

[sw]

nrf5340_app_hal and nrf5340_net_hal seem to have a wrong mapping of the GPIOs.

The nRF5340 has two GPIO ports:

• P0 (pins 0 .. 31)
• P1 (pins 0 .. 15)

Both are available on both the application core and the network core. On the application core, there are secure and non-secure variants:

• P0_S (0x50842500)
• P0_NS (0x40842500)
• P1_S (0x50842800)
• P1_NS (0x40842800)

There are at least two problems in the current implementation:

First, P1 is not available on nrf5340_app_hal.

Second, if you use P0_S on nrf5340_app_hal, pin_port will actually select P1:

nrf-hal/nrf-hal-common/src/gpio.rs

Lines 94 to 97 in 63ca6b5

	#[cfg(any(feature = "5340-app"))]
	Port::Port0Secure => 0x20,
	#[cfg(any(feature = "52833", feature = "52840", feature = "5340-net"))]
	Port::Port1 => 0x20,