Porting to ICE5LP4K

[krzysztofgawrys]

Is it possible to port bootloader to ICE5LP4K FPGA, main problem is that this chip does not have SPRAM at all, then question is will the RISC-V run on BRAM, will it fit?

[smunaut]

Yes, but not "as-is".
Not only does it not have SPRAM, it also only has 20 BRAM rather then the 30 from the UP5k which is a bit disappointing :/

I've been pretty liberal in my usage of RAM because .. I had it so I used it to speed things up and buffer things but it's surely possible to reduce.

The hardware itself can probably be reduced to 8 BRAM, leaving 12 BRAM for program memory which is 6 kbytes.

The current code is around 11.2kbyte usage but :

• The DFU code uses overly large buffers (again, I had them so might as well) and could be reduced from 4096 to 512, gaining 3.5k
• Clocking the picorv at 12 MHz instead of 24 MHz would allow to make use of compressed ISA and gain 1.7k

So doing that we get to like 6k, maybe need to trim a bit of fat else where to be safe but it should be possible without too much trouble.

So yeah, I think this can be done without major changes to the architecture or anything.