Forwarding generic package to component fails

[maltaisn]

I'm not sure whether this is allowed in VHDL-2019, although it seems logical to me.

pkg.vhd

package pkg is
    generic (type data_type);
end package;

bar.vhd

entity bar is
    generic (
        package pkg is new work.pkg generic map (<>));
    port (
        input : in pkg.data_type;
        output : out pkg.data_type);
end entity;

architecture rtl of bar is
begin
end architecture;

foo.vhd

entity foo is
    generic (
        package pkg is new work.pkg generic map (<>));
    port (
        input : in pkg.data_type;
        output : out pkg.data_type);
end entity;

architecture rtl of foo is
begin

    bar_inst : entity work.bar
        generic map (pkg => pkg)
        port map (input => input, output => output);

end architecture;

With nvc --std=2019 -a pkg.vhd bar.vhd foo.vhd I get the following error:

** Error: actual for generic PKG is not an instantiated package name
    > foo.vhd:14
    |
 14 |         generic map (pkg => pkg)
    |                             ^^^

Should it be allowed according to the standard? pkg is usually visible within the architecture.

If not, is there a way to achieve the same thing without needing to reinstantiate the package with the same parameters in the architecture declarative section?

architecture rtl of foo is

    use pkg.all;
    package pkg2 is new work.pkg generic map (data_type => data_type);

begin

    bar_inst : entity work.bar
        generic map (pkg => pkg2)
        port map (input => input, output => output);

end architecture;

[nickg]

It's not clear from the LRM whether this is valid or not. There's some related information in ghdl/ghdl#2039.

[maltaisn]

I see. Thanks.