From fc84ecba13c6225170e78e74e5f206386084fc5a Mon Sep 17 00:00:00 2001 From: Robin Jones Date: Sat, 2 Mar 2024 00:33:32 +0000 Subject: [PATCH] Add fixes to mpuconf As found at https://github.com/ArduPilot/ChibiOS.svn/commit/ad5f683d23e276e2bd1e63f1b2e5d0ded4949148 --- .../ChibiOS/ORGPAL_PALTHREE/nanoBooter/mcuconf.h | 15 +++++++++------ targets/ChibiOS/ORGPAL_PALTHREE/nanoCLR/mcuconf.h | 15 +++++++++------ .../ST_STM32F769I_DISCOVERY/nanoBooter/mcuconf.h | 15 +++++++++------ .../ST_STM32F769I_DISCOVERY/nanoCLR/mcuconf.h | 15 +++++++++------ 4 files changed, 36 insertions(+), 24 deletions(-) diff --git a/targets/ChibiOS/ORGPAL_PALTHREE/nanoBooter/mcuconf.h b/targets/ChibiOS/ORGPAL_PALTHREE/nanoBooter/mcuconf.h index 71a955b95e..2aa768652d 100644 --- a/targets/ChibiOS/ORGPAL_PALTHREE/nanoBooter/mcuconf.h +++ b/targets/ChibiOS/ORGPAL_PALTHREE/nanoBooter/mcuconf.h @@ -26,18 +26,22 @@ #define STM32F7xx_MCUCONF #define STM32F769_MCUCONF +/* + * General settings. + */ +#define STM32_NO_INIT FALSE + /* * Memory attributes settings. */ -#define STM32_NOCACHE_ENABLE FALSE -// #define STM32_NOCACHE_MPU_REGION MPU_REGION_6 -// #define STM32_NOCACHE_RBAR 0x2004C000U -// #define STM32_NOCACHE_RASR MPU_RASR_SIZE_16K +#define STM32_NOCACHE_ENABLE TRUE +#define STM32_NOCACHE_MPU_REGION MPU_REGION_6 +#define STM32_NOCACHE_RBAR 0x2004C000U +#define STM32_NOCACHE_RASR MPU_RASR_SIZE_16K /* * HAL driver system settings. */ -#define STM32_NO_INIT FALSE #define STM32_PVD_ENABLE FALSE #define STM32_PLS STM32_PLS_LEV0 #define STM32_BKPRAM_ENABLE TRUE @@ -95,7 +99,6 @@ #define STM32_CK48MSEL STM32_CK48MSEL_PLL #define STM32_SDMMC1SEL STM32_SDMMC1SEL_PLL48CLK #define STM32_SDMMC2SEL STM32_SDMMC2SEL_PLL48CLK -#define STM32_SRAM2_NOCACHE FALSE /* * IRQ system settings. diff --git a/targets/ChibiOS/ORGPAL_PALTHREE/nanoCLR/mcuconf.h b/targets/ChibiOS/ORGPAL_PALTHREE/nanoCLR/mcuconf.h index 17f8d41b78..d915452d76 100644 --- a/targets/ChibiOS/ORGPAL_PALTHREE/nanoCLR/mcuconf.h +++ b/targets/ChibiOS/ORGPAL_PALTHREE/nanoCLR/mcuconf.h @@ -26,18 +26,22 @@ #define STM32F7xx_MCUCONF #define STM32F769_MCUCONF +/* + * General settings. + */ +#define STM32_NO_INIT FALSE + /* * Memory attributes settings. */ -#define STM32_NOCACHE_ENABLE FALSE -// #define STM32_NOCACHE_MPU_REGION MPU_REGION_6 -// #define STM32_NOCACHE_RBAR 0x2004C000U -// #define STM32_NOCACHE_RASR MPU_RASR_SIZE_16K +#define STM32_NOCACHE_ENABLE TRUE +#define STM32_NOCACHE_MPU_REGION MPU_REGION_6 +#define STM32_NOCACHE_RBAR 0x2004C000U +#define STM32_NOCACHE_RASR MPU_RASR_SIZE_16K /* * HAL driver system settings. */ -#define STM32_NO_INIT FALSE #define STM32_PVD_ENABLE FALSE #define STM32_PLS STM32_PLS_LEV0 #define STM32_BKPRAM_ENABLE TRUE @@ -95,7 +99,6 @@ #define STM32_CK48MSEL STM32_CK48MSEL_PLL #define STM32_SDMMC1SEL STM32_SDMMC1SEL_PLL48CLK #define STM32_SDMMC2SEL STM32_SDMMC2SEL_PLL48CLK -#define STM32_SRAM2_NOCACHE FALSE /* * IRQ system settings. diff --git a/targets/ChibiOS/ST_STM32F769I_DISCOVERY/nanoBooter/mcuconf.h b/targets/ChibiOS/ST_STM32F769I_DISCOVERY/nanoBooter/mcuconf.h index 8ba2bbec15..ef6e280124 100644 --- a/targets/ChibiOS/ST_STM32F769I_DISCOVERY/nanoBooter/mcuconf.h +++ b/targets/ChibiOS/ST_STM32F769I_DISCOVERY/nanoBooter/mcuconf.h @@ -26,18 +26,22 @@ #define STM32F7xx_MCUCONF #define STM32F769_MCUCONF +/* + * General settings. + */ +#define STM32_NO_INIT FALSE + /* * Memory attributes settings. */ -#define STM32_NOCACHE_ENABLE FALSE -// #define STM32_NOCACHE_MPU_REGION MPU_REGION_6 -// #define STM32_NOCACHE_RBAR 0x2004C000U -// #define STM32_NOCACHE_RASR MPU_RASR_SIZE_16K +#define STM32_NOCACHE_ENABLE TRUE +#define STM32_NOCACHE_MPU_REGION MPU_REGION_6 +#define STM32_NOCACHE_RBAR 0x2004C000U +#define STM32_NOCACHE_RASR MPU_RASR_SIZE_16K /* * HAL driver system settings. */ -#define STM32_NO_INIT FALSE #define STM32_PVD_ENABLE FALSE #define STM32_PLS STM32_PLS_LEV0 #define STM32_BKPRAM_ENABLE FALSE @@ -95,7 +99,6 @@ #define STM32_CK48MSEL STM32_CK48MSEL_PLL #define STM32_SDMMC1SEL STM32_SDMMC1SEL_PLL48CLK #define STM32_SDMMC2SEL STM32_SDMMC2SEL_PLL48CLK -#define STM32_SRAM2_NOCACHE FALSE /* * IRQ system settings. diff --git a/targets/ChibiOS/ST_STM32F769I_DISCOVERY/nanoCLR/mcuconf.h b/targets/ChibiOS/ST_STM32F769I_DISCOVERY/nanoCLR/mcuconf.h index 28231717e5..9bc55849f0 100644 --- a/targets/ChibiOS/ST_STM32F769I_DISCOVERY/nanoCLR/mcuconf.h +++ b/targets/ChibiOS/ST_STM32F769I_DISCOVERY/nanoCLR/mcuconf.h @@ -26,18 +26,22 @@ #define STM32F7xx_MCUCONF #define STM32F769_MCUCONF +/* + * General settings. + */ +#define STM32_NO_INIT FALSE + /* * Memory attributes settings. */ -#define STM32_NOCACHE_ENABLE FALSE -// #define STM32_NOCACHE_MPU_REGION MPU_REGION_6 -// #define STM32_NOCACHE_RBAR 0x2004C000U -// #define STM32_NOCACHE_RASR MPU_RASR_SIZE_16K +#define STM32_NOCACHE_ENABLE TRUE +#define STM32_NOCACHE_MPU_REGION MPU_REGION_6 +#define STM32_NOCACHE_RBAR 0x2004C000U +#define STM32_NOCACHE_RASR MPU_RASR_SIZE_16K /* * HAL driver system settings. */ -#define STM32_NO_INIT FALSE #define STM32_PVD_ENABLE FALSE #define STM32_PLS STM32_PLS_LEV0 #define STM32_BKPRAM_ENABLE FALSE @@ -95,7 +99,6 @@ #define STM32_CK48MSEL STM32_CK48MSEL_PLL #define STM32_SDMMC1SEL STM32_SDMMC1SEL_PLL48CLK #define STM32_SDMMC2SEL STM32_SDMMC2SEL_PLL48CLK -#define STM32_SRAM2_NOCACHE FALSE /* * IRQ system settings.