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openhcl/virt_mshv_vtl/src/processor/mshv/tlb_lock.rs

Lines changed: 14 additions & 14 deletions
Original file line numberDiff line numberDiff line change
@@ -30,7 +30,7 @@ impl UhProcessor<'_, HypervisorBacked> {
3030
pub(crate) fn set_tlb_lock(&mut self, requesting_vtl: Vtl, target_vtl: GuestVtl) {
3131
debug_assert_eq!(requesting_vtl, Vtl::Vtl2);
3232

33-
if self.is_tlb_locked(requesting_vtl, target_vtl) {
33+
if self.vtls_tlb_locked.get(requesting_vtl, target_vtl) {
3434
return;
3535
}
3636

@@ -52,19 +52,26 @@ impl UhProcessor<'_, HypervisorBacked> {
5252
debug_assert_eq!(requesting_vtl, Vtl::Vtl2);
5353
let locally_locked = self.vtls_tlb_locked.get(requesting_vtl, target_vtl);
5454
// The hypervisor may lock the TLB without us knowing, but the inverse should never happen.
55-
#[expect(
56-
clippy::debug_assert_with_mut_call,
57-
reason = "just sanity checking, but the function can update the cached value in the non-debug-assert branch"
58-
)]
5955
if locally_locked {
60-
debug_assert!(self.is_tlb_locked_in_hypervisor(requesting_vtl, target_vtl));
56+
debug_assert!(self.is_tlb_locked_in_hypervisor_noncaching(target_vtl));
6157
true
6258
} else {
6359
self.is_tlb_locked_in_hypervisor(requesting_vtl, target_vtl)
6460
}
6561
}
6662

6763
fn is_tlb_locked_in_hypervisor(&mut self, requesting_vtl: Vtl, target_vtl: GuestVtl) -> bool {
64+
let result = self.is_tlb_locked_in_hypervisor_noncaching(target_vtl);
65+
// The hypervisor may lock the TLB without us knowing, but the inverse should never happen.
66+
if result {
67+
self.vtls_tlb_locked.set(requesting_vtl, target_vtl, true);
68+
} else {
69+
assert!(!self.vtls_tlb_locked.get(requesting_vtl, target_vtl));
70+
}
71+
result
72+
}
73+
74+
fn is_tlb_locked_in_hypervisor_noncaching(&self, target_vtl: GuestVtl) -> bool {
6875
let name = HvAllArchRegisterName(
6976
HvAllArchRegisterName::VsmVpSecureConfigVtl0.0 + target_vtl as u32,
7077
);
@@ -74,14 +81,7 @@ impl UhProcessor<'_, HypervisorBacked> {
7481
.get_vp_register(name, HvInputVtl::CURRENT_VTL)
7582
.expect("failure is a misconfiguration");
7683
let config = hvdef::HvRegisterVsmVpSecureVtlConfig::from(result.as_u64());
77-
let result = config.tlb_locked();
78-
// The hypervisor may lock the TLB without us knowing, but the inverse should never happen.
79-
if result {
80-
self.vtls_tlb_locked.set(requesting_vtl, target_vtl, true);
81-
} else {
82-
assert!(!self.vtls_tlb_locked.get(requesting_vtl, target_vtl));
83-
}
84-
result
84+
config.tlb_locked()
8585
}
8686

8787
/// Marks the TLBs of all lower VTLs as unlocked.

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