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Vaquita

A CHISEL based RISC-V Vector (RVV) v1.0 Extension Coprocessor Generator.

Vaquita: RISC-V Vector Co-Processor

A CHISEL-based RISC-V Vector (RVV) v1.0 Extension Coprocessor Generator.

Vaquita is currently integrated with the NucleusRV

Features

Instruction Coverage

  • Vector-to-Vector Instructions: 25 implemented
  • Vector-to-Scalar Instructions: 29 implemented
  • Vector-to-Immediate Instructions: 19 implemented

Testing and Compliance

Hardware Specifications

  • VLEN (Vector Length): 256 bits
  • Architecture: 4-stage co-processor pipeline for optimal throughput and latency

Usage

Prerequisites

  • RISCV GCC Toolchain: Install the RISC-V toolchain for compilation and testing
  • Imperas RISC-V Compliance Tools: For instruction set compliance testing

Building the Co-Processor with NucleusRV

  1. Clone the repository:
   git clone --recurse-submodule https://github.com/merledu/nucleusrv.git -b vec_dev_csr
   cd nucleusrv
  1. Building with SBT Run this command is SBT shell
testOnly nucleusrv.components.TopTest -- -DwriteVcd=1 -DprogramFile=/path/to/instructions/hex
  1. To Run imperas test cases
make compliance ISA=rv32i_m DEVICE=Vi TEST=<test case name>

to find the test case name from

./imperas-riscv-tests/riscv-test-suite/rv32i_m/<devise name>/Makefrag

Running Imperas Test Cases

To validate the compliance of the Vaquita RISC-V Vector Co-Processor with the RISC-V specifications, you can execute Imperas test cases using the steps outlined below.

Command to Execute Test Cases

Use the following command to run a specific test case:

make compliance ISA=rv32i_m DEVICE=<device name> TEST=<test case name>

Explanation of Command Parameters

ISA=rv32i_m: Specifies RISC-V instruction set architecture.
DEVICE=<device name>: Defines the target device for testing.
TEST=<test case name>: Specifies the name of the test case to run. Replace <test case name> with the actual test name.

Finding Test Case Names

To locate the available test case names for the vector processor:

Navigate to the test suite directory:

./imperas-riscv-tests/riscv-test-suite/rv32i_m/<device name>/Makefrag

Open the Makefrag file to view the list of test cases associated with the specified <device name>.

Identify the desired test case name to be used in the TEST parameter of the command.

Example

make compliance ISA=rv32i_m DEVICE=Vi TEST=VADD-VV-SEW32_LMUL1

Dependencies

Dependencies Version
sbt 1.10.1
verilator 5.026

GSoC Contribution

This project is a part of Google Summer of Code of 2024 mentored by Micro Electronics Research Lab (MERL).

GSoC Project: https://summerofcode.withgoogle.com/programs/2024/projects/FWHAVeL5