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vhdl2_engineering.qsf
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vhdl2_engineering.qsf
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# -------------------------------------------------------------------------- #
#
# Copyright (C) 2018 Intel Corporation. All rights reserved.
# Your use of Intel Corporation's design tools, logic functions
# and other software and tools, and its AMPP partner logic
# functions, and any output files from any of the foregoing
# (including device programming or simulation files), and any
# associated documentation or information are expressly subject
# to the terms and conditions of the Intel Program License
# Subscription Agreement, the Intel Quartus Prime License Agreement,
# the Intel FPGA IP License Agreement, or other applicable license
# agreement, including, without limitation, that your use is for
# the sole purpose of programming logic devices manufactured by
# Intel and sold by Intel or its authorized distributors. Please
# refer to the applicable agreement for further details.
#
# -------------------------------------------------------------------------- #
#
# Quartus Prime
# Version 18.1.0 Build 625 09/12/2018 SJ Lite Edition
# Date created = 09:46:44 November 06, 2020
#
# -------------------------------------------------------------------------- #
#
# Notes:
#
# 1) The default values for assignments are stored in the file:
# vhdl2_engineering_assignment_defaults.qdf
# If this file doesn't exist, see file:
# assignment_defaults.qdf
#
# 2) Altera recommends that you do not modify this file. This
# file is updated automatically by the Quartus Prime software
# and any changes you make may be lost or overwritten.
#
# -------------------------------------------------------------------------- #
set_global_assignment -name FAMILY "MAX 10"
set_global_assignment -name DEVICE 10M50DAF484C7G
set_global_assignment -name TOP_LEVEL_ENTITY top
set_global_assignment -name ORIGINAL_QUARTUS_VERSION 18.1.0
set_global_assignment -name PROJECT_CREATION_TIME_DATE "09:46:44 NOVEMBER 06, 2020"
set_global_assignment -name LAST_QUARTUS_VERSION "18.1.0 Lite Edition"
set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 256
set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim-Altera (VHDL)"
set_global_assignment -name EDA_TIME_SCALE "1 ps" -section_id eda_simulation
set_global_assignment -name EDA_OUTPUT_DATA_FORMAT VHDL -section_id eda_simulation
set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW"
set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
set_location_assignment PIN_P11 -to clk_50
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to clk_50
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to i2s_d_in
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to i2s_lr_clk
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to i2s_m_clk
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to i2s_s_clk
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to reset_n
set_location_assignment PIN_W8 -to i2s_d_in
set_location_assignment PIN_W10 -to i2s_lr_clk
set_location_assignment PIN_V10 -to i2s_m_clk
set_location_assignment PIN_W9 -to i2s_s_clk
set_location_assignment PIN_F15 -to reset_n
set_global_assignment -name TIMING_ANALYZER_MULTICORNER_ANALYSIS ON
set_global_assignment -name NUM_PARALLEL_PROCESSORS ALL
set_global_assignment -name ENABLE_SIGNALTAP OFF
set_global_assignment -name USE_SIGNALTAP_FILE stp.stp
set_global_assignment -name VHDL_INPUT_VERSION VHDL_2008
set_global_assignment -name VHDL_SHOW_LMF_MAPPING_MESSAGES OFF
set_location_assignment PIN_AA1 -to vga_r[0]
set_location_assignment PIN_V1 -to vga_r[1]
set_location_assignment PIN_Y2 -to vga_r[2]
set_location_assignment PIN_Y1 -to vga_r[3]
set_location_assignment PIN_W1 -to vga_g[0]
set_location_assignment PIN_T2 -to vga_g[1]
set_location_assignment PIN_R2 -to vga_g[2]
set_location_assignment PIN_R1 -to vga_g[3]
set_location_assignment PIN_P1 -to vga_b[0]
set_location_assignment PIN_T1 -to vga_b[1]
set_location_assignment PIN_P4 -to vga_b[2]
set_location_assignment PIN_N2 -to vga_b[3]
set_location_assignment PIN_N3 -to vga_hs
set_location_assignment PIN_N1 -to vga_vs
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to vga_b[0]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to vga_b[1]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to vga_b[2]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to vga_b[3]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to vga_g[0]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to vga_g[1]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to vga_g[2]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to vga_g[3]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to vga_hs
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to vga_r[0]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to vga_r[1]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to vga_r[2]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to vga_r[3]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to vga_vs
set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST ON -section_id eda_simulation
set_global_assignment -name SMART_RECOMPILE OFF
set_global_assignment -name SDC_FILE vhdl2_engineering.sdc
set_global_assignment -name VHDL_FILE hdl/sample_framer_ram.vhd
set_global_assignment -name VHDL_FILE hdl/i2s_transceiver.vhd
set_global_assignment -name VHDL_FILE hdl/sample_framer.vhd
set_global_assignment -name VHDL_FILE hdl/vga.vhd
set_global_assignment -name VHDL_FILE hdl/fft_post.vhd
set_global_assignment -name VHDL_FILE hdl/vga_sync.vhd
set_global_assignment -name VHDL_FILE hdl/fft.vhd
set_global_assignment -name VHDL_FILE hdl/top.vhd
set_global_assignment -name VHDL_FILE hdl/fft_window.vhd
set_global_assignment -name VHDL_FILE hdl/fixed_float/float_pkg_c.vhdl
set_global_assignment -name VHDL_FILE hdl/fixed_float/fixed_pkg_c.vhdl
set_global_assignment -name VHDL_FILE hdl/fixed_float/fixed_float_types_c.vhdl
set_global_assignment -name VERILOG_FILE "fft-core/shiftaddmpy.v"
set_global_assignment -name VERILOG_FILE "fft-core/qtrstage.v"
set_global_assignment -name VERILOG_FILE "fft-core/longbimpy.v"
set_global_assignment -name VERILOG_FILE "fft-core/laststage.v"
set_global_assignment -name VERILOG_FILE "fft-core/hwbfly.v"
set_global_assignment -name VERILOG_FILE "fft-core/fftstage.v"
set_global_assignment -name VERILOG_FILE "fft-core/fftmain.v"
set_global_assignment -name VERILOG_FILE "fft-core/convround.v"
set_global_assignment -name VERILOG_FILE "fft-core/butterfly.v"
set_global_assignment -name VERILOG_FILE "fft-core/bitreverse.v"
set_global_assignment -name VERILOG_FILE "fft-core/bimpy.v"
set_global_assignment -name QIP_FILE pll.qip
set_global_assignment -name QIP_FILE result_ram.qip
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to i2s_lr_clk
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to i2s_m_clk
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to i2s_s_clk
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to vga_b[3]
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to vga_b[2]
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to vga_b[1]
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to vga_b[0]
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to vga_g[3]
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to vga_g[2]
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to vga_g[1]
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to vga_g[0]
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to vga_hs
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to vga_r[3]
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to vga_r[2]
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to vga_r[1]
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to vga_r[0]
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to vga_vs
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to clk_50
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to i2s_d_in
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to reset_n
set_instance_assignment -name SLEW_RATE 2 -to vga_vs
set_instance_assignment -name SLEW_RATE 2 -to vga_r[0]
set_instance_assignment -name SLEW_RATE 2 -to vga_r[1]
set_instance_assignment -name SLEW_RATE 2 -to vga_r[2]
set_instance_assignment -name SLEW_RATE 2 -to vga_r[3]
set_instance_assignment -name SLEW_RATE 2 -to vga_hs
set_instance_assignment -name SLEW_RATE 2 -to vga_g[0]
set_instance_assignment -name SLEW_RATE 2 -to vga_g[1]
set_instance_assignment -name SLEW_RATE 2 -to vga_g[2]
set_instance_assignment -name SLEW_RATE 2 -to vga_g[3]
set_instance_assignment -name SLEW_RATE 2 -to vga_b[0]
set_instance_assignment -name SLEW_RATE 2 -to vga_b[1]
set_instance_assignment -name SLEW_RATE 2 -to vga_b[2]
set_instance_assignment -name SLEW_RATE 2 -to vga_b[3]
set_instance_assignment -name SLEW_RATE 2 -to i2s_s_clk
set_instance_assignment -name SLEW_RATE 2 -to i2s_m_clk
set_instance_assignment -name SLEW_RATE 2 -to i2s_lr_clk
set_global_assignment -name CYCLONEII_OPTIMIZATION_TECHNIQUE AREA
set_global_assignment -name ADV_NETLIST_OPT_SYNTH_WYSIWYG_REMAP ON
set_global_assignment -name AUTO_SHIFT_REGISTER_RECOGNITION ALWAYS
set_global_assignment -name REMOVE_REDUNDANT_LOGIC_CELLS ON
set_global_assignment -name MUX_RESTRUCTURE ON
set_global_assignment -name ALLOW_ANY_ROM_SIZE_FOR_RECOGNITION ON
set_global_assignment -name ALLOW_ANY_RAM_SIZE_FOR_RECOGNITION ON
set_global_assignment -name ALLOW_ANY_SHIFT_REGISTER_SIZE_FOR_RECOGNITION ON
set_global_assignment -name ALLOW_SHIFT_REGISTER_MERGING_ACROSS_HIERARCHIES ALWAYS
set_global_assignment -name AUTO_RAM_RECOGNITION ON
set_global_assignment -name FITTER_EFFORT "STANDARD FIT"
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top